AWfaw/ai-hdlcoder-dataset · Datasets at Hugging Face

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bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/proc_sys_reset_v5_0/hdl/src/vhdl/lpf.vhd	7	15991	------------------------------------------------------------------------------- -- lpf - entity/architecture pair ------------------------------------------------------------------------------- -- -- ********************************************************************** -- DISCLAIMER OF LIABILITY -- -- This file contains proprietary and confidential information of -- Xilinx, Inc. ("Xilinx"), that is distributed under a license -- from Xilinx, and may be used, copied and/or disclosed only -- pursuant to the terms of a valid license agreement with Xilinx. -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION -- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER -- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT -- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, -- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx -- does not warrant that functions included in the Materials will -- meet the requirements of Licensee, or that the operation of the -- Materials will be uninterrupted or error-free, or that defects -- in the Materials will be corrected. Furthermore, Xilinx does -- not warrant or make any representations regarding use, or the -- results of the use, of the Materials in terms of correctness, -- accuracy, reliability or otherwise. -- -- Xilinx products are not designed or intended to be fail-safe, -- or for use in any application requiring fail-safe performance, -- such as life-support or safety devices or systems, Class III -- medical devices, nuclear facilities, applications related to -- the deployment of airbags, or any other applications that could -- lead to death, personal injury or severe property or -- environmental damage (individually and collectively, "critical -- applications"). Customer assumes the sole risk and liability -- of any use of Xilinx products in critical applications, -- subject only to applicable laws and regulations governing -- limitations on product liability. -- -- Copyright 2012 Xilinx, Inc. -- All rights reserved. -- -- This disclaimer and copyright notice must be retained as part -- of this file at all times. -- ********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: lpf.vhd -- Version: v4.00a -- Description: Parameterizeable top level processor reset module. -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: This section should show the hierarchical structure of the -- designs.Separate lines with blank lines if necessary to improve -- readability. -- -- proc_sys_reset.vhd -- upcnt_n.vhd -- lpf.vhd -- sequence.vhd ------------------------------------------------------------------------------- -- Author: Kurt Conover -- History: -- Kurt Conover 11/08/01 -- First Release -- -- KC 02/25/2002 -- Added Dcm_locked as an input -- -- Added Power on reset srl_time_out -- -- KC 08/26/2003 -- Added attribute statements for power on -- reset SRL -- -- ~~~~~~~ -- SK 03/11/10 -- ^^^^^^^ -- 1. Updated the core so support the active low "Interconnect_aresetn" and -- "Peripheral_aresetn" signals. -- ^^^^^^^ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_com" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; library Unisim; use Unisim.all; ------------------------------------------------------------------------------- -- Port Declaration ------------------------------------------------------------------------------- -- Definition of Generics: -- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting -- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting -- C_EXT_RESET_HIGH -- External Reset Active High or Active Low -- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low -- -- Definition of Ports: -- Slowest_sync_clk -- Clock -- External_System_Reset -- External Reset Input -- Auxiliary_System_Reset -- Auxiliary Reset Input -- Dcm_locked -- DCM Locked, hold system in reset until 1 -- Lpf_reset -- Low Pass Filtered Output -- ------------------------------------------------------------------------------- entity lpf is generic( C_EXT_RST_WIDTH : Integer; C_AUX_RST_WIDTH : Integer; C_EXT_RESET_HIGH : std_logic; C_AUX_RESET_HIGH : std_logic ); port( MB_Debug_Sys_Rst : in std_logic; Dcm_locked : in std_logic; External_System_Reset : in std_logic; Auxiliary_System_Reset : in std_logic; Slowest_Sync_Clk : in std_logic; Lpf_reset : out std_logic ); end lpf; architecture imp of lpf is component SRL16 is -- synthesis translate_off generic ( INIT : bit_vector ); -- synthesis translate_on port (D : in std_logic; CLK : in std_logic; A0 : in std_logic; A1 : in std_logic; A2 : in std_logic; A3 : in std_logic; Q : out std_logic); end component SRL16; constant CLEAR : std_logic := '0'; signal exr_d1 : std_logic := '0'; -- delayed External_System_Reset signal exr_lpf : std_logic_vector(0 to C_EXT_RST_WIDTH - 1) := (others => '0'); -- LPF DFF signal asr_d1 : std_logic := '0'; -- delayed Auxiliary_System_Reset signal asr_lpf : std_logic_vector(0 to C_AUX_RST_WIDTH - 1) := (others => '0'); -- LPF DFF signal exr_and : std_logic := '0'; -- varible input width "and" gate signal exr_nand : std_logic := '0'; -- vaiable input width "and" gate signal asr_and : std_logic := '0'; -- varible input width "and" gate signal asr_nand : std_logic := '0'; -- vaiable input width "and" gate signal lpf_int : std_logic := '0'; -- internal Lpf_reset signal lpf_exr : std_logic := '0'; signal lpf_asr : std_logic := '0'; signal srl_time_out : std_logic; attribute INIT : string; attribute INIT of POR_SRL_I: label is "FFFF"; begin Lpf_reset <= lpf_int; ------------------------------------------------------------------------------- -- Power On Reset Generation ------------------------------------------------------------------------------- -- This generates a reset for the first 16 clocks after a power up ------------------------------------------------------------------------------- POR_SRL_I: SRL16 -- synthesis translate_off generic map ( INIT => X"FFFF") -- synthesis translate_on port map ( D => '0', CLK => Slowest_sync_clk, A0 => '1', A1 => '1', A2 => '1', A3 => '1', Q => srl_time_out); ------------------------------------------------------------------------------- -- LPF_OUTPUT_PROCESS ------------------------------------------------------------------------------- -- This generates the reset pulse and the count enable to core reset counter -- --ACTIVE_HIGH_LPF_EXT: if (C_EXT_RESET_HIGH = '1') generate --begin LPF_OUTPUT_PROCESS: process (Slowest_sync_clk) begin if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then lpf_int <= lpf_exr or lpf_asr or srl_time_out or not Dcm_locked; end if; end process LPF_OUTPUT_PROCESS; --end generate ACTIVE_HIGH_LPF_EXT; --ACTIVE_LOW_LPF_EXT: if (C_EXT_RESET_HIGH = '0') generate --begin --LPF_OUTPUT_PROCESS: process (Slowest_sync_clk) -- begin -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then -- lpf_int <= not (lpf_exr or -- lpf_asr or -- srl_time_out)or -- not Dcm_locked; -- end if; -- end process; --end generate ACTIVE_LOW_LPF_EXT; EXR_OUTPUT_PROCESS: process (Slowest_sync_clk) begin if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then if exr_and = '1' then lpf_exr <= '1'; elsif (exr_and = '0' and exr_nand = '1') then lpf_exr <= '0'; end if; end if; end process EXR_OUTPUT_PROCESS; ASR_OUTPUT_PROCESS: process (Slowest_sync_clk) begin if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then if asr_and = '1' then lpf_asr <= '1'; elsif (asr_and = '0' and asr_nand = '1') then lpf_asr <= '0'; end if; end if; end process ASR_OUTPUT_PROCESS; ------------------------------------------------------------------------------- -- This If-generate selects an active high input for External System Reset ------------------------------------------------------------------------------- ACTIVE_HIGH_EXT: if (C_EXT_RESET_HIGH /= '0') generate begin ----------------------------------- ACT_HI_EXT:process(Slowest_Sync_Clk) begin if (Slowest_Sync_Clk'event and Slowest_Sync_Clk = '1') then exr_d1 <= External_System_Reset or MB_Debug_Sys_Rst; exr_lpf(0) <= exr_d1; end if; end process; ----------------------------------- end generate ACTIVE_HIGH_EXT; ------------------------------------------------------------------------------- -- This If-generate selects an active low input for External System Reset ------------------------------------------------------------------------------- ACTIVE_LOW_EXT: if (C_EXT_RESET_HIGH = '0') generate begin ------------------------------------- ACT_LO_EXT: process(Slowest_Sync_Clk) begin if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then exr_d1 <= not External_System_Reset or MB_Debug_Sys_Rst; exr_lpf(0) <= exr_d1; end if; end process; ------------------------------------- end generate ACTIVE_LOW_EXT; ------------------------------------------------------------------------------- -- This If-generate selects an active high input for Auxiliary System Reset ------------------------------------------------------------------------------- ACTIVE_HIGH_AUX: if (C_AUX_RESET_HIGH /= '0') generate begin ------------------------------------- ACT_HI_AUX: process(Slowest_Sync_Clk) begin if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then asr_d1 <= Auxiliary_System_Reset; asr_lpf(0) <= asr_d1; end if; end process; ------------------------------------- end generate ACTIVE_HIGH_AUX; ------------------------------------------------------------------------------- -- This If-generate selects an active low input for Auxiliary System Reset ------------------------------------------------------------------------------- ACTIVE_LOW_AUX: if (C_AUX_RESET_HIGH = '0') generate begin ------------------------------------- ACT_LO_AUX: process(Slowest_Sync_Clk) begin if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then asr_d1 <= not Auxiliary_System_Reset; asr_lpf(0) <= asr_d1; end if; end process; ------------------------------------- end generate ACTIVE_LOW_AUX; ------------------------------------------------------------------------------- -- This For-generate creates the low pass filter D-Flip Flops ------------------------------------------------------------------------------- EXT_LPF: for i in 1 to C_EXT_RST_WIDTH - 1 generate begin ---------------------------------------- EXT_LPF_DFF : process (Slowest_Sync_Clk) begin if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then exr_lpf(i) <= exr_lpf(i-1); end if; end process; ---------------------------------------- end generate EXT_LPF; ------------------------------------------------------------------------------------------ -- Implement the 'AND' function on the for the LPF ------------------------------------------------------------------------------------------ EXT_LPF_AND : process (exr_lpf) Variable loop_and : std_logic; Variable loop_nand : std_logic; Begin loop_and := '1'; loop_nand := '1'; for j in 0 to C_EXT_RST_WIDTH - 1 loop loop_and := loop_and and exr_lpf(j); loop_nand := loop_nand and not exr_lpf(j); End loop; exr_and <= loop_and; exr_nand <= loop_nand; end process; ------------------------------------------------------------------------------- -- This For-generate creates the low pass filter D-Flip Flops ------------------------------------------------------------------------------- AUX_LPF: for k in 1 to C_AUX_RST_WIDTH - 1 generate begin ---------------------------------------- AUX_LPF_DFF : process (Slowest_Sync_Clk) begin if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then asr_lpf(k) <= asr_lpf(k-1); end if; end process; ---------------------------------------- end generate AUX_LPF; ------------------------------------------------------------------------------------------ -- Implement the 'AND' function on the for the LPF ------------------------------------------------------------------------------------------ AUX_LPF_AND : process (asr_lpf) Variable aux_loop_and : std_logic; Variable aux_loop_nand : std_logic; Begin aux_loop_and := '1'; aux_loop_nand := '1'; for m in 0 to C_AUX_RST_WIDTH - 1 loop aux_loop_and := aux_loop_and and asr_lpf(m); aux_loop_nand := aux_loop_nand and not asr_lpf(m); End loop; asr_and <= aux_loop_and; asr_nand <= aux_loop_nand; end process; end imp;	mit
bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/proc_common_v4_0/hdl/src/vhdl/mux_onehot_f.vhd	15	12692	------------------------------------------------------------------------------- -- $Id: mux_onehot_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $ ------------------------------------------------------------------------------- -- mux_onehot_f - arch and entity ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under -- license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid -- license agreement with Xilinx, Inc. Xilinx hereby -- grants you a license to use this text/file solely for -- design, simulation, implementation and creation of -- design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly -- prohibited and immediately terminates your license unless -- covered by a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices, with no obligation on the -- part of Xilinx to provide support. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining -- any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- Any modifications that are made to the Source Code are -- done at the users sole risk and will be unsupported. -- The Xilinx Support Hotline does not have access to source -- code and therefore cannot answer specific questions related -- to source HDL. The Xilinx Hotline support of original source -- code IP shall only address issues and questions related -- to the standard Netlist version of the core (and thus -- indirectly, the original core source). -- -- Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: mux_onehot_f.vhd -- -- Description: Parameterizable multiplexer with one hot select lines. -- -- Please refer to the entity interface while reading the -- remainder of this description. -- -- If n is the index of the single select line of S(0 to C_NB-1) -- that is asserted, then -- -- Y(0 to C_DW-1) <= D(nC_DW to nC_DW + C_DW -1) -- -- That is, Y selects the nth group of C_DW consecutive -- bits of D. -- -- Note that C_NB = 1 is handled as a special case in which -- Y <= D, without regard to the select line, S. -- -- The Implementation depends on the C_FAMILY parameter. -- If the target family supports the needed primitives, -- a carry-chain structure will be implemented. Otherwise, -- an implementation dependent on synthesis inferral will -- be generated. -- ------------------------------------------------------------------------------- -- Structure: -- mux_onehot_f -- family_support -------------------------------------------------------------------------------- -- Author: FLO -- History: -- FLO 11/30/05 -- First version derived from mux_onehot.vhd -- -- by BLT and ALS. -- -- ~~~~~~ -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Changed proc_common library version to v4_0 -- - Incorporated new disclaimer header -- ^^^^^^ -- --------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_cmb" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; ------------------------------------------------------------------------------- -- Generic and Port Declaration ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Definition of Generics and Ports -- -- C_DW: Data width of buses entering the mux. Valid range is 1 to 256. -- C_NB: Number of data buses entering the mux. Valid range is 1 to 64. -- -- input D -- input data bus -- input S -- input select bus -- output Y -- output bus -- -- The input data is represented by a one-dimensional bus that is made up -- of all of the data buses concatenated together. For example, a 4 to 1 -- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by: -- -- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1, -- Bus3Data0, Bus3Data1) -- -- Y = (Bus0Data0, Bus0Data1) if S(0)=1 else -- (Bus1Data0, Bus1Data1) if S(1)=1 else -- (Bus2Data0, Bus2Data1) if S(2)=1 else -- (Bus3Data0, Bus3Data1) if S(3)=1 -- -- Only one bit of S should be asserted at a time. -- ------------------------------------------------------------------------------- library proc_common_v4_0; use proc_common_v4_0.family_support.all; -- 'supported' function, etc. -- entity mux_onehot_f is generic( C_DW: integer := 32; C_NB: integer := 5; C_FAMILY : string := "virtexe"); port( D: in std_logic_vector(0 to C_DWC_NB-1); S: in std_logic_vector(0 to C_NB-1); Y: out std_logic_vector(0 to C_DW-1)); end mux_onehot_f; library unisim; use unisim.all; -- Make unisim entities available for default binding. architecture imp of mux_onehot_f is constant NLS : natural := native_lut_size(fam_as_string => C_FAMILY, no_lut_return_val => 2C_NB); function lut_val(D, S : std_logic_vector) return std_logic is variable rn : std_logic := '0'; begin for i in D'range loop rn := rn or (S(i) and D(i)); end loop; return not rn; end; function min(i, j : integer) return integer is begin if i < j then return i; else return j; end if; end; ----------------------------------------------------------------------------- -- Signal and Type Declarations ------------------------------------------------------------------------------- signal Dreord: std_logic_vector(0 to C_DWC_NB-1); signal sel: std_logic_vector(0 to C_DWC_NB-1); ------------------------------------------------------------------------------- -- Component Declarations ------------------------------------------------------------------------------- component MUXCY port ( O : out std_ulogic; CI : in std_ulogic; DI : in std_ulogic; S : in std_ulogic ); end component; begin -- Reorder data buses WA_GEN : if C_DW > 0 generate -- XST WA REORD: process( D ) variable m,n: integer; begin for m in 0 to C_DW-1 loop for n in 0 to C_NB-1 loop Dreord( mC_NB+n) <= D( nC_DW+m ); end loop; end loop; end process REORD; end generate; ------------------------------------------------------------------------------- -- REPSELS_PROCESS ------------------------------------------------------------------------------- -- The one-hot select bus contains 1-bit for each bus. To more easily -- parameterize the carry chains and reduce loading on the select bus, these -- signals are replicated into a bus that replicates the select bits for the -- data width of the busses ------------------------------------------------------------------------------- REPSELS_PROCESS : process ( S ) variable i, j : integer; begin -- loop through all data bits and busses for i in 0 to C_DW-1 loop for j in 0 to C_NB-1 loop sel(iC_NB+j) <= S(j); end loop; end loop; end process REPSELS_PROCESS; GEN: if C_NB > 1 generate constant BPL : positive := NLS / 2; -- Buses per LUT is the native lut -- size divided by two.signals per bus. constant NUMLUTS : positive := (C_NB+(BPL-1))/BPL; begin DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate signal cyout : std_logic_vector(0 to NUMLUTS); signal lutout : std_logic_vector(0 to NUMLUTS-1); begin cyout(0) <= '0'; NUM_BUSES_GEN: for j in 0 to NUMLUTS - 1 generate constant BTL : positive := min(BPL, C_NB - jBPL); -- Number of Buses This Lut (for last LUT this may be less than BPL) begin lutout(j) <= lut_val(D => Dreord(iC_NB+jBPL to iC_NB+jBPL+BTL-1), S => sel(iC_NB+jBPL to iC_NB+j*BPL+BTL-1) ); MUXCY_GEN : if NUMLUTS > 1 generate MUXCY_I : component MUXCY port map (CI=>cyout(j), DI=> '1', S=>lutout(j), O=>cyout(j+1)); end generate; end generate; Y(i) <= cyout(NUMLUTS) when NUMLUTS > 1 else not lutout(0); -- If just one -- LUT, then take value from -- lutout rather than cyout. end generate; end generate; ONE_GEN: if C_NB = 1 generate Y <= D; end generate; end imp;	mit
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bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/basic_sfifo_fg.vhd	12	55233	------------------------------------------------------------------------------- -- basic_sfifo_fg.vhd ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: basic_sfifo_fg.vhd -- -- Description: -- This HDL file implements a basic synchronous (single clock) fifo using the -- FIFO Generator tool. It is intended to offer a simple interface to the user -- with the complexity of the FIFO Generator interface hidden from the user. -- -- Note that in normal op mode (not First Word Fall Through FWFT) the data count -- output goes to zero when the FIFO goes full. This the way FIFO Generator works. -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- basic_sfifo_fg.vhd -- \| -- \|-- fifo_generator_v8_2 -- ------------------------------------------------------------------------------- -- Revision History: -- -- -- Author: DET -- Revision: $Revision: 1.0 $ -- Date: $3/07/2011$ -- -- History: -- DET 3/07/2011 Initial Version -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library fifo_generator_v11_0; use fifo_generator_v11_0.all; library proc_common_v4_0; use proc_common_v4_0.proc_common_pkg.all; use proc_common_v4_0.proc_common_pkg.log2; --use proc_common_v4_0.coregen_comp_defs.all; -- synopsys translate_off --library XilinxCoreLib; --use XilinxCoreLib.all; -- synopsys translate_on ------------------------------------------------------------------------------- entity basic_sfifo_fg is generic ( C_DWIDTH : Integer := 32 ; -- FIFO data Width (Read and write data ports are symetric) C_DEPTH : Integer := 512 ; -- FIFO Depth (set to power of 2) C_HAS_DATA_COUNT : integer := 1 ; -- 0 = Data Count output not needed -- 1 = Data Count output needed C_DATA_COUNT_WIDTH : integer := 10 ; -- Data Count bit width (Max value is log2(C_DEPTH)) C_IMPLEMENTATION_TYPE : integer range 0 to 1 := 0; -- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO) -- 1 = Common Clock Shift Register (Synchronous FIFO) C_MEMORY_TYPE : integer := 1; -- 0 = Any -- 1 = BRAM -- 2 = Distributed Memory -- 3 = Shift Registers C_PRELOAD_REGS : integer := 1; -- 0 = normal -- 1 = FWFT C_PRELOAD_LATENCY : integer := 0; -- 0 = FWFT -- 1 = normal C_USE_FWFT_DATA_COUNT : integer := 0; -- 0 = normal -- 1 for FWFT C_SYNCHRONIZER_STAGE : integer := 2; -- valid values are 0 to 8; C_FAMILY : string := "virtex6" ); port ( CLK : IN std_logic := '0'; DIN : IN std_logic_vector(C_DWIDTH-1 DOWNTO 0) := (OTHERS => '0'); RD_EN : IN std_logic := '0'; SRST : IN std_logic := '0'; WR_EN : IN std_logic := '0'; DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0); DOUT : OUT std_logic_vector(C_DWIDTH-1 DOWNTO 0); EMPTY : OUT std_logic; FULL : OUT std_logic ); end entity basic_sfifo_fg; architecture implementation of basic_sfifo_fg is -- Constant Declarations ---------------------------------------------- Constant POINTER_WIDTH : integer := log2(C_DEPTH); -- Constant zeros for programmable threshold inputs signal PROG_RDTHRESH_ZEROS : std_logic_vector(POINTER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); signal PROG_WRTHRESH_ZEROS : std_logic_vector(POINTER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- Signals --Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE" signal ALMOST_FULL : std_logic; signal WR_ACK : std_logic; signal OVERFLOW : std_logic; signal VALID : std_logic; signal UNDERFLOW : std_logic; signal ALMOST_EMPTY : std_logic; signal RD_DATA_COUNT : std_logic_vector(C_DATA_COUNT_WIDTH-1 downto 0); signal WR_DATA_COUNT : std_logic_vector(C_DATA_COUNT_WIDTH-1 downto 0); signal PROG_FULL : std_logic; signal PROG_EMPTY : std_logic; signal SBITERR : std_logic; signal DBITERR : std_logic; signal S_AXI_AWREADY : std_logic; signal S_AXI_WREADY : std_logic; signal S_AXI_BID : std_logic_vector(3 DOWNTO 0); signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0); signal S_AXI_BUSER : std_logic_vector(0 downto 0); signal S_AXI_BVALID : std_logic; -- AXI Full/Lite Master Write Channel (Read side) signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0); signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0); signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0); signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0); signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0); signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0); signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0); signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_AWUSER : std_logic_vector(0 downto 0); signal M_AXI_AWVALID : std_logic; signal M_AXI_WID : std_logic_vector(3 DOWNTO 0); signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0); signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0); signal M_AXI_WLAST : std_logic; signal M_AXI_WUSER : std_logic_vector(0 downto 0); signal M_AXI_WVALID : std_logic; signal M_AXI_BREADY : std_logic; -- AXI Full/Lite Slave Read Channel (Write side) signal S_AXI_ARREADY : std_logic; signal S_AXI_RID : std_logic_vector(3 DOWNTO 0); signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0); signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0); signal S_AXI_RLAST : std_logic; signal S_AXI_RUSER : std_logic_vector(0 downto 0); signal S_AXI_RVALID : std_logic; -- AXI Full/Lite Master Read Channel (Read side) signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0); signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0); signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0); signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0); signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0); signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0); signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0); signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_ARUSER : std_logic_vector(0 downto 0); signal M_AXI_ARVALID : std_logic; signal M_AXI_RREADY : std_logic; -- AXI Streaming Slave Signals (Write side) signal S_AXIS_TREADY : std_logic; -- AXI Streaming Master Signals (Read side) signal M_AXIS_TVALID : std_logic; signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0); signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0); signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0); signal M_AXIS_TLAST : std_logic; signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0); signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0); signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0); -- AXI Full/Lite Write Address Channel Signals signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AW_SBITERR : std_logic; signal AXI_AW_DBITERR : std_logic; signal AXI_AW_OVERFLOW : std_logic; signal AXI_AW_UNDERFLOW : std_logic; signal AXI_AW_PROG_FULL : STD_LOGIC; signal AXI_AW_PROG_EMPTY : STD_LOGIC; -- AXI Full/Lite Write Data Channel Signals signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_W_SBITERR : std_logic; signal AXI_W_DBITERR : std_logic; signal AXI_W_OVERFLOW : std_logic; signal AXI_W_UNDERFLOW : std_logic; signal AXI_W_PROG_FULL : STD_LOGIC; signal AXI_W_PROG_EMPTY : STD_LOGIC; -- AXI Full/Lite Write Response Channel Signals signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_B_SBITERR : std_logic; signal AXI_B_DBITERR : std_logic; signal AXI_B_OVERFLOW : std_logic; signal AXI_B_UNDERFLOW : std_logic; signal AXI_B_PROG_FULL : STD_LOGIC; signal AXI_B_PROG_EMPTY : STD_LOGIC; -- AXI Full/Lite Read Address Channel Signals signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AR_SBITERR : std_logic; signal AXI_AR_DBITERR : std_logic; signal AXI_AR_OVERFLOW : std_logic; signal AXI_AR_UNDERFLOW : std_logic; signal AXI_AR_PROG_FULL : STD_LOGIC; signal AXI_AR_PROG_EMPTY : STD_LOGIC; -- AXI Full/Lite Read Data Channel Signals signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_R_SBITERR : std_logic; signal AXI_R_DBITERR : std_logic; signal AXI_R_OVERFLOW : std_logic; signal AXI_R_UNDERFLOW : std_logic; signal AXI_R_PROG_FULL : STD_LOGIC; signal AXI_R_PROG_EMPTY : STD_LOGIC; -- AXI Streaming FIFO Related Signals signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXIS_SBITERR : std_logic; signal AXIS_DBITERR : std_logic; signal AXIS_OVERFLOW : std_logic; signal AXIS_UNDERFLOW : std_logic; signal AXIS_PROG_FULL : STD_LOGIC; signal AXIS_PROG_EMPTY : STD_LOGIC; begin --(architecture implementation) ------------------------------------------------------------------------------- -- Instantiate the generalized FIFO Generator instance -- -- NOTE: -- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!! -- This is a Coregen FIFO Generator Call module for -- BRAM implementations of a basic Sync FIFO -- ------------------------------------------------------------------------------- I_BASIC_SFIFO : entity fifo_generator_v11_0.fifo_generator_v11_0 generic map( C_COMMON_CLOCK => 1, C_COUNT_TYPE => 0, C_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH, C_DEFAULT_VALUE => "BlankString", C_DIN_WIDTH => C_DWIDTH, C_DOUT_RST_VAL => "0", C_DOUT_WIDTH => C_DWIDTH, C_ENABLE_RLOCS => 0, -- n0 C_FAMILY => C_FAMILY, C_HAS_ALMOST_EMPTY => 0, -- n0 C_HAS_ALMOST_FULL => 0, -- n0 C_HAS_BACKUP => 0, -- n0 C_HAS_DATA_COUNT => C_HAS_DATA_COUNT, C_HAS_MEMINIT_FILE => 0, -- n0 C_HAS_OVERFLOW => 0, -- n0 C_HAS_RD_DATA_COUNT => 0, -- n0 C_HAS_RD_RST => 0, -- n0 C_HAS_RST => 0, -- n0 C_HAS_SRST => 1, -- yes C_HAS_UNDERFLOW => 0, -- n0 C_HAS_VALID => 0, -- n0 C_HAS_WR_ACK => 0, -- n0 C_HAS_WR_DATA_COUNT => 0, -- n0 C_HAS_WR_RST => 0, -- n0 C_IMPLEMENTATION_TYPE => 0, -- Common clock BRAM C_INIT_WR_PNTR_VAL => 0, C_MEMORY_TYPE => C_MEMORY_TYPE, C_MIF_FILE_NAME => "BlankString", C_OPTIMIZATION_MODE => 0, C_OVERFLOW_LOW => 0, C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, C_PRELOAD_REGS => C_PRELOAD_REGS, C_PRIM_FIFO_TYPE => "512x36", C_PROG_EMPTY_THRESH_ASSERT_VAL => 0, C_PROG_EMPTY_THRESH_NEGATE_VAL => 0, C_PROG_EMPTY_TYPE => 0, C_PROG_FULL_THRESH_ASSERT_VAL => 0, C_PROG_FULL_THRESH_NEGATE_VAL => 0, C_PROG_FULL_TYPE => 0, C_RD_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH, C_RD_DEPTH => C_DEPTH, C_RD_FREQ => 1, C_RD_PNTR_WIDTH => POINTER_WIDTH, C_UNDERFLOW_LOW => 0, C_USE_DOUT_RST => 1, C_USE_EMBEDDED_REG => 0, C_USE_FIFO16_FLAGS => 0, C_USE_FWFT_DATA_COUNT => C_USE_FWFT_DATA_COUNT, C_VALID_LOW => 0, C_WR_ACK_LOW => 0, C_WR_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH, C_WR_DEPTH => C_DEPTH, C_WR_FREQ => 1, C_WR_PNTR_WIDTH => POINTER_WIDTH, C_WR_RESPONSE_LATENCY => 1, C_USE_ECC => 0, C_FULL_FLAGS_RST_VAL => 0, C_ENABLE_RST_SYNC => 1, C_ERROR_INJECTION_TYPE => 0, C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE, C_HAS_INT_CLK => 0, C_MSGON_VAL => 1, -- AXI Interface related parameters start here C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0; C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0; C_HAS_SLAVE_CE => 0, -- : integer := 0; C_HAS_MASTER_CE => 0, -- : integer := 0; C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0; C_USE_COMMON_OVERFLOW => 0, -- : integer := 0; C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0; C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0; -- AXI Full/Lite C_AXI_ID_WIDTH => 4 , -- : integer := 0; C_AXI_ADDR_WIDTH => 32, -- : integer := 0; C_AXI_DATA_WIDTH => 64, -- : integer := 0; C_AXI_LEN_WIDTH => 8, -- : integer := 8; C_AXI_LOCK_WIDTH => 2, -- : integer := 2; C_HAS_AXI_ID => 0, -- : integer := 0; C_HAS_AXI_AWUSER => 0 , -- : integer := 0; C_HAS_AXI_WUSER => 0 , -- : integer := 0; C_HAS_AXI_BUSER => 0 , -- : integer := 0; C_HAS_AXI_ARUSER => 0 , -- : integer := 0; C_HAS_AXI_RUSER => 0 , -- : integer := 0; C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0; C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0; C_AXI_WUSER_WIDTH => 1 , -- : integer := 0; C_AXI_BUSER_WIDTH => 1 , -- : integer := 0; C_AXI_RUSER_WIDTH => 1 , -- : integer := 0; -- AXI Streaming C_HAS_AXIS_TDATA => 0 , -- : integer := 0; C_HAS_AXIS_TID => 0 , -- : integer := 0; C_HAS_AXIS_TDEST => 0 , -- : integer := 0; C_HAS_AXIS_TUSER => 0 , -- : integer := 0; C_HAS_AXIS_TREADY => 1 , -- : integer := 0; C_HAS_AXIS_TLAST => 0 , -- : integer := 0; C_HAS_AXIS_TSTRB => 0 , -- : integer := 0; C_HAS_AXIS_TKEEP => 0 , -- : integer := 0; C_AXIS_TDATA_WIDTH => 64, -- : integer := 1; C_AXIS_TID_WIDTH => 8 , -- : integer := 1; C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1; C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1; C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1; C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1; -- AXI Channel Type -- WACH --> Write Address Channel -- WDCH --> Write Data Channel -- WRCH --> Write Response Channel -- RACH --> Read Address Channel -- RDCH --> Read Data Channel -- AXIS --> AXI Streaming C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie -- AXI Implementation Type -- 1 = Common Clock Block RAM FIFO -- 2 = Common Clock Distributed RAM FIFO -- 11 = Independent Clock Block RAM FIFO -- 12 = Independent Clock Distributed RAM FIFO C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0; -- AXI FIFO Type -- 0 = Data FIFO -- 1 = Packet FIFO -- 2 = Low Latency Data FIFO C_APPLICATION_TYPE_WACH => 0, -- : integer := 0; C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0; C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0; C_APPLICATION_TYPE_RACH => 0, -- : integer := 0; C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0; C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0; -- Enable ECC -- 0 = ECC disabled -- 1 = ECC enabled C_USE_ECC_WACH => 0, -- : integer := 0; C_USE_ECC_WDCH => 0, -- : integer := 0; C_USE_ECC_WRCH => 0, -- : integer := 0; C_USE_ECC_RACH => 0, -- : integer := 0; C_USE_ECC_RDCH => 0, -- : integer := 0; C_USE_ECC_AXIS => 0, -- : integer := 0; -- ECC Error Injection Type -- 0 = No Error Injection -- 1 = Single Bit Error Injection -- 2 = Double Bit Error Injection -- 3 = Single Bit and Double Bit Error Injection C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0; -- Input Data Width -- Accumulation of all AXI input signal's width C_DIN_WIDTH_WACH => 32, -- : integer := 1; C_DIN_WIDTH_WDCH => 64, -- : integer := 1; C_DIN_WIDTH_WRCH => 2 , -- : integer := 1; C_DIN_WIDTH_RACH => 32, -- : integer := 1; C_DIN_WIDTH_RDCH => 64, -- : integer := 1; C_DIN_WIDTH_AXIS => 1 , -- : integer := 1; C_WR_DEPTH_WACH => 16 , -- : integer := 16; C_WR_DEPTH_WDCH => 1024, -- : integer := 16; C_WR_DEPTH_WRCH => 16 , -- : integer := 16; C_WR_DEPTH_RACH => 16 , -- : integer := 16; C_WR_DEPTH_RDCH => 1024, -- : integer := 16; C_WR_DEPTH_AXIS => 1024, -- : integer := 16; C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4; C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4; C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4; C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4; C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4; C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4; C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0; C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0; C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0; C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0; C_REG_SLICE_MODE_WACH => 0, -- : integer := 0; C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0; C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0; C_REG_SLICE_MODE_RACH => 0, -- : integer := 0; C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0; C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0 ) port map( backup => '0', backup_marker => '0', clk => CLK, rst => '0', srst => SRST, wr_clk => '0', wr_rst => '0', rd_clk => '0', rd_rst => '0', din => DIN, -- uses this one wr_en => WR_EN, -- uses this one rd_en => RD_EN, -- uses this one prog_empty_thresh => PROG_RDTHRESH_ZEROS, prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS, prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS, prog_full_thresh => PROG_WRTHRESH_ZEROS, prog_full_thresh_assert => PROG_WRTHRESH_ZEROS, prog_full_thresh_negate => PROG_WRTHRESH_ZEROS, int_clk => '0', injectdbiterr => '0', injectsbiterr => '0', dout => DOUT, -- uses this one full => FULL, -- uses this one almost_full => ALMOST_FULL, wr_ack => WR_ACK, overflow => OVERFLOW, empty => EMPTY, -- uses this one almost_empty => ALMOST_EMPTY, valid => VALID, underflow => UNDERFLOW, data_count => DATA_COUNT, -- uses this one rd_data_count => RD_DATA_COUNT, wr_data_count => WR_DATA_COUNT, prog_full => PROG_FULL, prog_empty => PROG_EMPTY, sbiterr => SBITERR, dbiterr => DBITERR, -- AXI Global Signal m_aclk => '0', -- : IN std_logic := '0'; s_aclk => '0', -- : IN std_logic := '0'; s_aresetn => '0', -- : IN std_logic := '0'; m_aclk_en => '0', -- : IN std_logic := '0'; s_aclk_en => '0', -- : IN std_logic := '0'; -- AXI Full/Lite Slave Write Channel (write side) s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awvalid => '0', -- : IN std_logic := '0'; s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic; s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wlast => '0', -- : IN std_logic := '0'; s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wvalid => '0', -- : IN std_logic := '0'; s_axi_wready => S_AXI_WREADY, -- : OUT std_logic; s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0); s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0); s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic; s_axi_bready => '0', -- : IN std_logic := '0'; -- AXI Full/Lite Master Write Channel (Read side) m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0); m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0); m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0); m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic; m_axi_awready => '0', -- : IN std_logic := '0'; m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0); m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0); m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic; m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0); m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic; m_axi_wready => '0', -- : IN std_logic := '0'; m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_bvalid => '0', -- : IN std_logic := '0'; m_axi_bready => M_AXI_BREADY, -- : OUT std_logic; -- AXI Full/Lite Slave Read Channel (Write side) s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arvalid => '0', -- : IN std_logic := '0'; s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic; s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0); s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0); s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic; s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0); s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic; s_axi_rready => '0', -- : IN std_logic := '0'; -- AXI Full/Lite Master Read Channel (Read side) m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0); m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0); m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0); m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic; m_axi_arready => '0', -- : IN std_logic := '0'; m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rlast => '0', -- : IN std_logic := '0'; m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rvalid => '0', -- : IN std_logic := '0'; m_axi_rready => M_AXI_RREADY, -- : OUT std_logic; -- AXI Streaming Slave Signals (Write side) s_axis_tvalid => '0', -- : IN std_logic := '0'; s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic; s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tlast => '0', -- : IN std_logic := '0'; s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- AXI Streaming Master Signals (Read side) m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic; m_axis_tready => '0', -- : IN std_logic := '0'; m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0); m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0); m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0); m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic; m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0); m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0); m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0); -- AXI Full/Lite Write Address Channel Signals axi_aw_injectsbiterr => '0', -- : IN std_logic := '0'; axi_aw_injectdbiterr => '0', -- : IN std_logic := '0'; axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0'); axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0'); axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0); axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0); axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0); axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic; axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic; axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic; axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic; axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Write Data Channel Signals axi_w_injectsbiterr => '0', -- : IN std_logic := '0'; axi_w_injectdbiterr => '0', -- : IN std_logic := '0'; axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0); axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0); axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0); axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic; axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic; axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic; axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic; axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Write Response Channel Signals axi_b_injectsbiterr => '0', -- : IN std_logic := '0'; axi_b_injectdbiterr => '0', -- : IN std_logic := '0'; axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0'); axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0'); axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0); axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0); axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0); axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic; axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic; axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic; axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic; axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Read Address Channel Signals axi_ar_injectsbiterr => '0', -- : IN std_logic := '0'; axi_ar_injectdbiterr => '0', -- : IN std_logic := '0'; axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0'); axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0'); axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0); axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0); axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0); axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic; axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic; axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic; axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic; axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Read Data Channel Signals axi_r_injectsbiterr => '0', -- : IN std_logic := '0'; axi_r_injectdbiterr => '0', -- : IN std_logic := '0'; axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0); axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0); axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0); axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic; axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic; axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic; axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic; axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Streaming FIFO Related Signals axis_injectsbiterr => '0', -- : IN std_logic := '0'; axis_injectdbiterr => '0', -- : IN std_logic := '0'; axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0'); axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0'); axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0); axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0); axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0); axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic; axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic; axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic; axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0'; axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1'; ); end implementation;	mit
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djmatt/VHDL-Lib	VHDL/Muxer/muxer.vhd	1	3482	---------------------------------------------------------------------------------------------------- -- muxer ---------------------------------------------------------------------------------------------------- -- Matthew Dallmeyer - [email protected] ---------------------------------------------------------------------------------------------------- -- PACKAGE ---------------------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library work; package muxer_pkg is --muxer componenet declaration component muxer is generic( INIT_SEL : std_logic_vector(1 downto 0) := b"10"); port( clk : in std_logic; clk_2x : in std_logic; rst : in std_logic; sig1 : in std_logic_vector; sig2 : in std_logic_vector; sigs : out std_logic_vector); end component; end package; ---------------------------------------------------------------------------------------------------- -- ENTITY ---------------------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; --This entity takes 2 input signals and interlaces them into 1 output signal. During development --it was determined that the clock inputs must be phase aligned for best results entity muxer is generic( INIT_SEL : std_logic_vector(1 downto 0) := b"10"); port( clk : in std_logic; clk_2x : in std_logic; rst : in std_logic; sig1 : in std_logic_vector; sig2 : in std_logic_vector; sigs : out std_logic_vector); end muxer; ---------------------------------------------------------------------------------------------------- -- ARCHITECTURE ---------------------------------------------------------------------------------------------------- architecture behave of muxer is signal sig1_reg : std_logic_vector(sig1'range) := (others => '0'); signal sig2_reg : std_logic_vector(sig2'range) := (others => '0'); signal selector : std_logic_vector(1 downto 0) := INIT_SEL; signal sigs_reg : std_logic_vector(sigs'range) := (others => '0'); begin --Register the inputs reg_in : process(clk) begin if(rising_edge(clk)) then if(rst = '1') then sig1_reg <= (others => '0'); sig2_reg <= (others => '0'); else sig1_reg <= sig1; sig2_reg <= sig2; end if; end if; end process; --Selection update_selection : process(clk_2x) begin if(rising_edge(clk_2x)) then if(rst = '1') then selector <= INIT_SEL; else selector <= std_logic_vector(rotate_left(unsigned(selector), 1)); end if; end if; end process; --Register the output reg_out : process(clk_2x) begin if(rising_edge(clk_2x)) then if(rst = '1') then sigs_reg <= (others => '0'); else case selector is when b"01" => sigs_reg <= sig1; when b"10" => sigs_reg <= sig2; when others => sigs_reg <= (others => '-'); end case; end if; end if; end process; sigs <= sigs_reg; end behave;	mit
bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/proc_common_v4_0/hdl/src/vhdl/pf_counter_top.vhd	15	8369	------------------------------------------------------------------------------- -- $Id: pf_counter_top.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $ ------------------------------------------------------------------------------- -- pf_counter_top - entity/architecture pair ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under -- license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid -- license agreement with Xilinx, Inc. Xilinx hereby -- grants you a license to use this text/file solely for -- design, simulation, implementation and creation of -- design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly -- prohibited and immediately terminates your license unless -- covered by a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices, with no obligation on the -- part of Xilinx to provide support. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining -- any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- Any modifications that are made to the Source Code are -- done at the users sole risk and will be unsupported. -- The Xilinx Support Hotline does not have access to source -- code and therefore cannot answer specific questions related -- to source HDL. The Xilinx Hotline support of original source -- code IP shall only address issues and questions related -- to the standard Netlist version of the core (and thus -- indirectly, the original core source). -- -- Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: pf_counter_top.vhd -- -- Description: Implements parameterized up/down counter -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- pf_counter_top.vhd -- ------------------------------------------------------------------------------- -- Author: D. Thorpe -- Revision: $Revision: 1.1.4.1 $ -- Date: $Date: 2010/09/14 22:35:47 $ -- -- History: -- DET 2001-08-30 First Version -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Changed proc_common library version to v4_0 -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_com" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; --Use IEEE.numeric_std.all; library unisim; use unisim.vcomponents.all; library proc_common_v4_0; use proc_common_v4_0.pf_counter; ----------------------------------------------------------------------------- -- Entity section ----------------------------------------------------------------------------- entity pf_counter_top is generic ( C_COUNT_WIDTH : integer := 10 ); port ( Clk : in std_logic; Rst : in std_logic; Load_Enable : in std_logic; Load_value : in std_logic_vector(0 to C_COUNT_WIDTH-1); Count_Down : in std_logic; Count_Up : in std_logic; --Carry_Out : out std_logic; Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1) ); end entity pf_counter_top; ----------------------------------------------------------------------------- -- Architecture section ----------------------------------------------------------------------------- architecture implementation of pf_counter_top is Signal sig_cnt_enable : std_logic; Signal sig_cnt_up_n_dwn : std_logic; Signal sig_carry_out : std_logic; Signal sig_count_out : std_logic_vector(0 to C_COUNT_WIDTH-1); begin -- VHDL_RTL -- Misc signal assignments Count_Out <= sig_count_out; --Carry_Out <= sig_carry_Out; sig_cnt_enable <= Count_Up xor Count_Down; sig_cnt_up_n_dwn <= not(Count_Up); I_UP_DWN_COUNTER : entity proc_common_v4_0.pf_counter generic map ( C_COUNT_WIDTH => C_COUNT_WIDTH ) port map( Clk => Clk, -- : in std_logic; Rst => Rst, -- : in std_logic; Carry_Out => sig_carry_out, -- : out std_logic; Load_In => Load_value, -- : in std_logic_vector(0 to C_COUNT_WIDTH-1); Count_Enable => sig_cnt_enable, -- : in std_logic; Count_Load => Load_Enable, -- : in std_logic; Count_Down => sig_cnt_up_n_dwn,-- : in std_logic; Count_Out => sig_count_out -- : out std_logic_vector(0 to C_COUNT_WIDTH-1) ); end architecture implementation;	mit
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bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_1_1/fifo_generator_v11_0/ramfifo/wr_dc_fwft_ext_as.vhd	19	13630	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block pabZO1I/O5UlEfYaQEPwd4l9eUai0bqYoMxFZDUmBPXyS95K3GW98Ld97MzJKAXXnSlf1PewGW2v 0RIeWd32HQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block MnYS98CLv6GUlLtXXj0MDq/aXJWBamrEeFXZFkhzX7OjMU68I3JzEc2/1UN3CHInfTII6cQBis+f MSPPkhHYfjWA/UnlZNCfIbUjCA7v4zzzEDOXLdUwHhey61M2PDbtjo4F0M+PSYsHQUE61FCJYZr6 +aBOwyo0CpKkCUVEbxg= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block qncW/Cwz6DQ02ZtEcvyp5WdAA4sItotGPpP0REUtLyqefQhCtJmFILcg4T0iyRUg7VuYEwIANO5+ QvHNNc39qIJv9lOesalgHBZQgvNRJnIdYWaRfS0GyacwI/2JQRwAkuAQstvDCp4RTc3l8lwP6/ls 9Kgq/wnF0FIDD2zIsqBFYPVau5gOg+E2Yv8daLhsLbgUNkGI+w4/OZjRbQGSUjwZLuzAjcC7dEzW IiD8iCe2E3P5aTpTA2tXeuvseQy8KOwVCxJQuur+f/bmnE2QrPi5PPQMRcOyc4ok7k5U/64SCKlJ oITfL/xIL/xwZa26tMPcLgkkx7p0G3RLvL/tVw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Dnf6vaqe/V3pNaiPDsCpL4mEkUhuRTF8jsptuAsYR5QlsF0hNdnCfK2+aKM5H69faCvd5mpbM0GP Pqz+qhNmOYPHdckgaTUGR5o/7QyV8YKLvzwfyDMqTu2isTv6FP6Q6welH2CNBnmC1/h5T7i+fy/Q rlaoXYJxfrB3B6n9clU= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block IMf8iBP4Q72XIQn7cHjsTbT2wNsnwrpqWy35OTpGthg9IgmIl2PQf4/c9imtaZPdkPVpIBywT+vW p0seCgJeCim8uHSlCA4Yuvzi7NiJqnEZtjEX9xSzaDj4EflUudOJTsvuYMqv/3kxvUgkIK0AS+U7 CWRV3RwJIjyzXaV3SkeD5i2xf0d/bezTocOrvt7wO8hz1n7ziicW5bgdFMZpO18+84bLDi0MzKYQ Ad5OLz8QJgoCqRTe+B2lLXuByvKd2+XBYArz50J0pDfy4RubYe7FYpZdW50ze6dgBWVP0HOw0tLX Pt7eQrmsKxnIhjnIQBRBht+Bb5QLkHSbaJnGbg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8352) `protect data_block 3Txl86gxySTjspY1bX6mjaEtHzHyJ6PEwV30HseHtq4UpP2jRFV0RDcUeckeAq3gEZ5Qu030LNT9 bbOM++HUbE1I8N7rcDRyyG1/zAJa57yK2mi3blq8tQKZ32YObDq6jHS9U2gM3rYjhBhVr2aKK7qQ c8X7nouwkJNW94GkZ7OhWlUV608zX7vk9Ytc1anxwA7VNM5uWs0oTqvG08wzxEO/Wp7eKojoSXwO 3Xhea7t/apLpI0orOHVPwHMzsjaxq56UlxouX+wqfNeT7gOjE86Icz9Kv6qJveIr35SBEOvmKTEu XXSNT6K9tm6q88SyQn3Fynw4R45InLxk96cdtyVOQFxzvDOOUUpt48giFXLbSh2J5eWLkh7wKkBY NwQFlaCkJdKCsT643SDourT31zKF+Ez8++L0sOmdPaVStcet+0/LOBpXifaCvmNLeKxnE44uDown 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bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/proc_common_v4_0/hdl/src/vhdl/srl_fifo_rbu_f.vhd	15	16038	------------------------------------------------------------------------------- -- $Id: srl_fifo_rbu_f.vhd,v 1.1.4.2 2010/09/14 22:35:47 dougt Exp $ ------------------------------------------------------------------------------- -- srl_fifo_rbu_f - entity / architecture pair ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under -- license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid -- license agreement with Xilinx, Inc. Xilinx hereby -- grants you a license to use this text/file solely for -- design, simulation, implementation and creation of -- design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly -- prohibited and immediately terminates your license unless -- covered by a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices, with no obligation on the -- part of Xilinx to provide support. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining -- any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- Any modifications that are made to the Source Code are -- done at the users sole risk and will be unsupported. -- The Xilinx Support Hotline does not have access to source -- code and therefore cannot answer specific questions related -- to source HDL. The Xilinx Hotline support of original source -- code IP shall only address issues and questions related -- to the standard Netlist version of the core (and thus -- indirectly, the original core source). -- -- Copyright (c) 2007-2010 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: srl_fifo_rbu_f.vhd -- -- Description: A small-to-medium depth FIFO with optional -- capability to back up and reread data. For -- data storage, the SRL elements native to the -- target FGPA family are used. If the FIFO depth -- exceeds the available depth of the SRL elements, -- then SRLs are cascaded and MUXFN elements are -- used to select the output of the appropriate SRL stage. -- -- Features: -- - Width and depth are arbitrary, but each doubling of -- depth, starting from the native SRL depth, adds -- a level of MUXFN. Generally, in performance-oriented -- applications, the fifo depth may need to be limited to -- not exceed the SRL cascade depth supported by local -- fast interconnect or the number of MUXFN levels. -- However, deeper fifos will correctly build. -- - Commands: read, write, and reread n. -- - Flags: empty and full. -- - The reread n command (executed by applying -- a non-zero value, n, to signal Num_To_Reread -- for one clock period) allows n -- previously read elements to be restored to the FIFO, -- limited, however, to the number of elements that have -- not been overwritten. (It is the user's responsibility -- to assure that the elements being restored are -- actually in the FIFO storage; once the depth of the -- FIFO has been written, the maximum number that can -- be restored is equal to the vacancy.) -- The reread capability does not cost extra LUTs or FFs. -- - Commands may be asserted simultaneously. -- However, if read and reread n are asserted -- simultaneously, only the read is carried out. -- - Overflow and underflow are detected and latched until -- Reset. The state of the FIFO is undefined during -- status of underflow or overflow. -- Underflow can occur only by reading the FIFO when empty. -- Overflow can occur either from a write, a reread n, -- or a combination of both that would result in more -- elements occupying the FIFO that its C_DEPTH. -- - Any of the signals FIFO_Full, Underflow, or Overflow -- left unconnected can be expected to be trimmed. -- - The Addr output is always one less than the current -- occupancy when the FIFO is non-empty, and is all ones -- otherwise. Therefore, the value <FIFO_Empty, Addr>-- -- i.e. FIFO_Empty concatenated on the left with Addr-- -- when taken as a signed value, is one less than the -- current occupancy. -- This information can be used to generate additional -- flags, if needed. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- srl_fifo_rbu_f.vhd -- dynshreg_f.vhd -- cntr_incr_decr_addn_f.vhd -- ------------------------------------------------------------------------------- -- Author: Farrell Ostler -- -- History: -- FLO 12/05/05 First Version. Derived from srl_fifo_rbu. -- ~~~~~~ -- FLO 2007-12-12 -- ^^^^^^ -- Using function clog2 now instead of log2 to eliminate superfluous warnings. -- ~~~~~~ -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Changed proc_common library version to v4_0 -- - Incorporated new disclaimer header -- ^^^^^^ -- FLO 2008-11-25 -- ^^^^^^ -- Changed to functionally equivalent code to generate FIFO_Full. The new code -- steers the current XST toward a better implementation. CR 496211. -- ~~~~~~ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_com" -- pipelined or register delay signals: "_d#" -- predecessor value by # clks: "_p#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.UNSIGNED; use ieee.numeric_std.">="; use ieee.numeric_std.TO_UNSIGNED; library proc_common_v4_0; use proc_common_v4_0.proc_common_pkg.clog2; entity srl_fifo_rbu_f is generic ( C_DWIDTH : natural; C_DEPTH : positive := 16; C_FAMILY : string := "nofamily" ); port ( Clk : in std_logic; Reset : in std_logic; FIFO_Write : in std_logic; Data_In : in std_logic_vector(0 to C_DWIDTH-1); FIFO_Read : in std_logic; Data_Out : out std_logic_vector(0 to C_DWIDTH-1); FIFO_Full : out std_logic; FIFO_Empty : out std_logic; Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1); Num_To_Reread : in std_logic_vector(0 to clog2(C_DEPTH)-1); Underflow : out std_logic; Overflow : out std_logic ); end entity srl_fifo_rbu_f; architecture imp of srl_fifo_rbu_f is function bitwise_or(s: std_logic_vector) return std_logic is variable v: std_logic := '0'; begin for i in s'range loop v := v or s(i); end loop; return v; end bitwise_or; constant ADDR_BITS : integer := clog2(C_DEPTH); -- An extra bit will be carried as the empty flag. signal addr_i : std_logic_vector(ADDR_BITS downto 0); signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0); signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0); signal fifo_empty_i : std_logic; signal overflow_i : std_logic; signal underflow_i : std_logic; signal fifo_full_p1 : std_logic; begin fifo_empty_i <= addr_i(ADDR_BITS); Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0); FIFO_Empty <= fifo_empty_i; num_to_reread_zeroext <= '0' & Num_To_Reread; ---------------------------------------------------------------------------- -- The FIFO address counter. Addresses the next element to be read. -- All ones when the FIFO is empty. ---------------------------------------------------------------------------- CNTR_INCR_DECR_ADDN_F_I : entity proc_common_v4_0.cntr_incr_decr_addn_f generic map ( C_SIZE => ADDR_BITS + 1, C_FAMILY => C_FAMILY ) port map ( Clk => Clk, Reset => Reset, Incr => FIFO_Write, Decr => FIFO_Read, N_to_add => num_to_reread_zeroext, Cnt => addr_i, Cnt_p1 => addr_i_p1 ); ---------------------------------------------------------------------------- -- The dynamic shift register that holds the FIFO elements. ---------------------------------------------------------------------------- DYNSHREG_F_I : entity proc_common_v4_0.dynshreg_f generic map ( C_DEPTH => C_DEPTH, C_DWIDTH => C_DWIDTH, C_FAMILY => C_FAMILY ) port map ( Clk => Clk, Clken => FIFO_Write, Addr => addr_i(ADDR_BITS-1 downto 0), Din => Data_In, Dout => Data_Out ); ---------------------------------------------------------------------------- -- Full flag. ---------------------------------------------------------------------------- fifo_full_p1 <= '1' when ( addr_i_p1 = std_logic_vector( TO_UNSIGNED(C_DEPTH-1, ADDR_BITS+1) ) ) else '0'; FULL_PROCESS: process (Clk) begin if Clk'event and Clk='1' then if Reset='1' then FIFO_Full <= '0'; else FIFO_Full <= fifo_full_p1; end if; end if; end process; ---------------------------------------------------------------------------- -- Underflow detection. ---------------------------------------------------------------------------- UNDERFLOW_PROCESS: process (Clk) begin if Clk'event and Clk='1' then if Reset = '1' then underflow_i <= '0'; elsif underflow_i = '1' then underflow_i <= '1'; -- Underflow sticks until reset else underflow_i <= fifo_empty_i and FIFO_Read; end if; end if; end process; Underflow <= underflow_i; ---------------------------------------------------------------------------- -- Overflow detection. -- The only case of non-erroneous operation for which addr_i (including -- the high-order bit used as the empty flag) taken as an unsigned value -- may be greater than or equal to C_DEPTH is when the FIFO is empty. -- No overflow is possible when FIFO_Read, since Num_To_Reread is -- overriden in this case and the number elements can at most remain -- unchanged (that being when there is a simultaneous FIFO_Write). -- However, when there is no FIFO_Read and there is either a -- FIFO_Write or a restoration of one or more read elements, or both, then -- addr_i, extended by the carry-out bit, becoming greater than -- or equal to C_DEPTH indicates an overflow. ---------------------------------------------------------------------------- OVERFLOW_PROCESS: process (Clk) begin if Clk'event and Clk='1' then if Reset = '1' then overflow_i <= '0'; elsif overflow_i = '1' then overflow_i <= '1'; -- Overflow sticks until Reset elsif FIFO_Read = '0' and (FIFO_Write= '1' or bitwise_or(Num_To_Reread)='1') and UNSIGNED(addr_i_p1) >= C_DEPTH then overflow_i <= '1'; else overflow_i <= '0'; end if; end if; end process; Overflow <= overflow_i; end architecture imp;	mit
bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/eval_timer.vhd	15	11230	------------------------------------------------------------------------------- -- $Id: eval_timer.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $ ------------------------------------------------------------------------------- -- eval_timer.vhd - entity/architecture pair ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under -- license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid -- license agreement with Xilinx, Inc. Xilinx hereby -- grants you a license to use this text/file solely for -- design, simulation, implementation and creation of -- design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly -- prohibited and immediately terminates your license unless -- covered by a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices, with no obligation on the -- part of Xilinx to provide support. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining -- any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- Any modifications that are made to the Source Code are -- done at the users sole risk and will be unsupported. -- The Xilinx Support Hotline does not have access to source -- code and therefore cannot answer specific questions related -- to source HDL. The Xilinx Hotline support of original source -- code IP shall only address issues and questions related -- to the standard Netlist version of the core (and thus -- indirectly, the original core source). -- -- Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: eval_timer.vhd -- Version: v1.00a -- Description: 40-bit counter that enables IP to be used in an evaluation -- mode. Once the counter expires, the eval_timeout signal -- asserts and can be used to reset the IP. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- eval_timer.vhd -- ------------------------------------------------------------------------------- -- Author: ALS -- History: -- ALS 09/12/01 -- Created from PCI eval timer -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Changed proc_common library version to v4_0 -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_com" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; library unisim; use unisim.all; library proc_common_v4_0; use proc_common_v4_0.proc_common_pkg.all; use proc_common_v4_0.all; ----------------------------------------------------------------------------- -- Entity section ----------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Definition of Generics: -- No generics -- -- Definition of Ports: -- Clk -- clock -- Rst -- active high reset -- Eval_timeout -- timer has expired ------------------------------------------------------------------------------- entity eval_timer is port ( Clk : in std_logic; Rst : in std_logic; Eval_timeout : out std_logic ); end entity eval_timer; ----------------------------------------------------------------------------- -- Architecture section ----------------------------------------------------------------------------- architecture imp of eval_timer is ----------------------------------------------------------------------------- -- Constant Declarations ----------------------------------------------------------------------------- constant NUM_BITS : integer := 8; ----------------------------------------------------------------------------- -- Signal Declarations ----------------------------------------------------------------------------- signal co : std_logic_vector(0 to 4); -- carry out signal ceo : std_logic_vector(0 to 4); -- count enable out signal ceo_d1 : std_logic_vector(0 to 4); -- registered count enable out signal zeros : std_logic_vector(NUM_BITS-1 downto 0); ----------------------------------------------------------------------------- -- Component Declarations ----------------------------------------------------------------------------- component Counter is generic( C_NUM_BITS : Integer := 9 ); port ( Clk : in std_logic; Rst : in std_logic; Load_In : in std_logic_vector(C_NUM_BITS - 1 downto 0); Count_Enable : in std_logic; Count_Load : in std_logic; Count_Down : in std_logic; Count_Out : out std_logic_vector(C_NUM_BITS - 1 downto 0); Carry_Out : out std_logic ); end component Counter; component FDRE port ( Q : out std_logic; C : in std_logic; CE : in std_logic; D : in std_logic; R : in std_logic ); end component; component FDR port ( Q : out std_logic; C : in std_logic; D : in std_logic; R : in std_logic ); end component; begin -- VHDL_RTL -- set the load value to zero zeros <= (others => '0'); -- Generate a 40-bit counter from 5 8-bit counters. Register the carry-out between counters -- to avoid timing problems. COUNTER_GEN: for i in 0 to 4 generate -- first 8-bit counter FIRST: if i = 0 generate COUNT_0_I: Counter generic map (C_NUM_BITS => NUM_BITS) port map ( Clk => Clk, Rst => Rst, Load_in => zeros, Count_Enable => '1', Count_Load => '0', Count_Down => '0', Count_out => open, Carry_Out => co(0) ); -- register the carry out to create the count enable out ceo(i) <= co(i); FDR_0_I: FDR port map ( Q => ceo_d1(i), C => Clk, D => ceo(i), R => Rst ); end generate FIRST; -- all other eight bit counters and the carry out register ALL_OTHERS: if i /= 0 generate COUNT_I: Counter generic map (C_NUM_BITS => NUM_BITS) port map ( Clk => Clk, Rst => Rst, Load_in => zeros, Count_Enable => ceo_d1(i-1), Count_Load => '0', Count_Down => '0', Count_out => open, Carry_Out => co(i) ); -- register the carry out AND the count enable to create the count enable out ceo(i) <= co(i) and ceo_d1(i-1); FDR_0_I: FDR port map ( Q => ceo_d1(i), C => Clk, D => ceo(i), R => Rst ); end generate ALL_OTHERS; end generate COUNTER_GEN; -- Using the final carry out as a CE, clock a '1' to assert and hold the eval_timeout signal. FDRE_I: FDRE port map ( Q => eval_timeout, --[out] C => Clk, --[in] CE => ceo_d1(4), --[in] D => '1', --[in] R => Rst --[in] ); end imp;	mit
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bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_1_1/blk_mem_gen_v8_1/blk_mem_axi_read_wrapper.vhd	27	57813	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block gqDFw5NFAM6CTSTQpb6ewV0dkTDze+wC3QoGAxwxbjcNW9/DsOht+2F009+7g6jE2OnhGLtqTq+c HspFg2GBAA== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block OROCzcjj1wgCYlIqlabkGZopoXwccuhDPoDiFwbBlsbzl7flKX8tC5m+07o0XejIs9tQT70vCTz8 eor9UB573WqZyEwu6nS7RfReZTn9rXIEfFTmb5LNQYR53WQufFJWXVGGzbi12Azu0TUMNBykYjra GCJvYkOLjulS+N02/QU= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block y306+4wGPVAAsHa7Tcr0Z+Y/dNy6G34dYeGbx7ATqkdiT3xoZwFMriTbyxCB/BNDpEEpWtR2x6B5 1geIXl7xRsYW2a/OzYZ1VgC14cIMMrlyvjd+Q0oeBhNwIf7zzOU0YeLe10Ln0VhNNlM9hG1yxJpm PklN0o7dbe4z3qSMhzdrqG9CNO1AfE0zEYRDe4xK7ci9EcGBPeIBnjhSSGUwaUeKV6BzeVeTBH5k pFfAdDfvgi3P1VwvurSSAL/VyrhWR7M2OhP7fekXRqEU99K00pFciI0NAEcJPUl8pbYtjc86ccu3 OmuQ0fZKcUeaRlPX6glqeiiehMLm/EPWzCdMgg== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block gSn/ibMO73s4UyV+DQBAOvPjnov0A3ONpbzDn5S1gDHbJc8laliw/uAOvABs0KKAN8Q7GKr5UYxh qWYO6FhJPBG8V6RCU+sAaoeSnleJb/buC83HgJws4chUKE1EbA08UnkA2E57wCSfAlSkdEQl5xrl E4NsCY7zrBmnjMH1Xu4= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/fifo_generator_v11_0/builtin/fifo_generator_v11_0_builtin.vhd	19	49663	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block MxpeY9fwU4EddFSpExWohS5o9i8UPinR6kQv/f7rVpVjW9v1XPHFNv5NQBBqnxbGk/3GroOhKYHi zeZXd9sb8Q== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block genV68U/jEyVif/FXdfTRcDdNLXMaB4JkzDnEPHISJLebDAxHBqab4xQb3vzSMzS4EZxJxM3czS7 l6/Pa+/lUNH4iHFgH3/d34ImoXy9UrVsNWI4O1k56f8CO5JZkX0ENM2JUr2+jZNnrmepHCpz3pyr N2xknPLUPWomWT5p45Y= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 4dyOi6X0ND7jxJKLfQYpMzBQUnXRUvqhIlWd2qdz2OgGY9VUivCAp2239OkMu2rIWSpkdV3gd8Tn 4E+XnpveIi4nHAn1AdqR2yW6qJRqYI/CpvcG8E7ZhuUiWSAPiQ/jcxRmeyzLFdVhgEV4hed5vk+9 Qi0C1DUHqDNPvc06f+xZUSTzBSqXkxyUqGIa+j3ZmCrjq04hmRDILUEkjqmR0K0TOLNdsLd81gAl LqIfeuzK3hLcVWnnJG54RzS/q6bahPN8UaYhtJREcAC9BD1S+QEdDXRxFczj2T1LQBL5rSryR8bI LV6YqNl+85SCCMZmZV8Io9S7fDVIrhzNm4Kcmw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block PIdLn+S6alHzFt/ir7zZvMPdMeYQTL6BrWSuIGxsOazGugSdn7m2jtyII74LXXAGUQ0h11spxnUf W/HpoHHxg6pfmAZclwmfvLsFiVi0w0hNMmIWoR8TGPdAC93Y5+aRfoAJNuDfUDfLzdBM4O7G2ZFx YGYpvBcNhzcFFuSCCK4= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block KkGw0OOEdMUjhZKEmICwPPGTbEeQxk+K4HH0ah7Z5cm5dbbyDDJyn1CdBy6WY7ZD/SXDbXp0Ibi6 BH7Y9BzUsE3rhTUVWQo0OMHXc+hE0CnmrdIq6Yy3Wkf73IKl+pu+66Qo9W7SdJGNPpreGME4X4AM zBwAv9xByRwGoY45EIIGTaE7VL15piKgLihjK8Y2Ee8q921qHsI62b9osdj+stH9M0nIgGIwpsIA DiUOa8Naw0kRMS8QCXDqKr1fJ0jPj3cnclvP9Taz8J5tp8Sf8I6bs8irg+MGD1MgQIfeKkimA5VH MerNz8gbn3+/Vz2X2+nKanM3LebAMLyCO8EBfA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 35024) `protect data_block CjDiOg1OOWaCAImu7V6e17mSTdTG2VshsQC9TgLVgEdt6LRfbWLFj7pjliLiaI75jL0DarVVZgIB YBxEiViEXJlBW0IDp+HN4/r03Ji75adj6JPgX/zTVva61hh2R45tKi+4cQj4r2XZGM6xGu8u02BO 7JM1KptVa0q6XfKxOCC/GxzgVmjiw7cJ36bA6JopQxHWJu8OYGv84q09mD3akYnNi5S8Wbp6zMAt Fvpvaz+d8Rgc2qy70/QeE4cM3Jn/H6O2e5WbExJNTitRy53P2ux9mweTwPS/iui87euYB4mUJizQ fAnUOoARGGl+FhwvQpZRvegPkiOWzWibLQrU3a9dBDHMUUU+wlUjtWs/UUGRoppRSc+j5BGfHJoZ 6/Ai/2YSXvVXYocBD/mIuZChqg/cutPhK7QniSuMh7QYsxKPmyoLYGzps6wXbL0jPflW3EXnqHcL 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bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/proc_common_v4_0/hdl/src/vhdl/or_gate_f.vhd	15	9178	------------------------------------------------------------------------------- -- $Id: or_gate_f.vhd,v 1.1.4.2 2010/09/14 22:35:46 dougt Exp $ ------------------------------------------------------------------------------- -- or_gate_f.vhd - entity/architecture pair ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under -- license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid -- license agreement with Xilinx, Inc. Xilinx hereby -- grants you a license to use this text/file solely for -- design, simulation, implementation and creation of -- design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly -- prohibited and immediately terminates your license unless -- covered by a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices, with no obligation on the -- part of Xilinx to provide support. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining -- any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- Any modifications that are made to the Source Code are -- done at the users sole risk and will be unsupported. -- The Xilinx Support Hotline does not have access to source -- code and therefore cannot answer specific questions related -- to source HDL. The Xilinx Hotline support of original source -- code IP shall only address issues and questions related -- to the standard Netlist version of the core (and thus -- indirectly, the original core source). -- -- Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: or_gate_f.vhd -- -- Description: OR gates. The width of each OR gate (C_OR_WIDTH) -- and the number of or gates (C_BUS_WIDTH) are -- parameterizable. -- -- Y(j) <= A(j) OR A(C_BUS_WIDTH+j) -- OR A(2C_BUS_WIDTH+j) -- ... -- OR A((C_OR_WIDTH-1)C_BUS_WIDTH+j), -- -- for 0 <= j < C_BUS_WIDTH -- -- If C_FAMILY is set (or left defaulted) to "nofamily" -- then the implementation will be by synthesis inference. -- Otherwise, a structural implementation optimized to -- C_FAMILY may be generated, depending on whether -- C_FAMILY supports the needed primtives. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- or_gate_f.vhd -- ------------------------------------------------------------------------------- -- Author: FLO -- History: -- FLO 2006-12-11 -- ^^^^^^ -- First Version, derived from or_gate by BLT -- ~~~~~~ -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Changed proc_common library version to v4_0 -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_com" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library proc_common_v4_0; ------------------------------------------------------------------------------- -- Definition of Generics: -- C_OR_WIDTH -- Which Xilinx FPGA family to target when -- syntesizing, affect the RLOC string values -- C_BUS_WIDTH -- Which Y position the RLOC should start from -- -- Definition of Ports: -- A -- Input. Input buses are concatenated together to -- form input A. Example: to OR buses R, S, and T, -- assign A <= R & S & T; -- Y -- Output. Same width as input buses. -- ------------------------------------------------------------------------------- entity or_gate_f is generic ( C_OR_WIDTH : natural := 17; C_BUS_WIDTH : natural := 1; C_FAMILY : string := "nofamily" ); port ( A : in std_logic_vector(0 to C_OR_WIDTHC_BUS_WIDTH-1); Y : out std_logic_vector(0 to C_BUS_WIDTH-1) ); end entity or_gate_f; architecture imp of or_gate_f is ------------------------------------------------------------------------------- -- Component Declarations ------------------------------------------------------------------------------- signal test : std_logic_vector(0 to C_BUS_WIDTH-1); ------------------------------------------------------------------------------- -- Begin architecture ------------------------------------------------------------------------------- begin BUS_WIDTH_FOR_GEN: for i in 0 to C_BUS_WIDTH-1 generate signal in_Bus : std_logic_vector(0 to C_OR_WIDTH-1); begin ORDER_INPUT_BUS_PROCESS: process( A ) is begin for k in 0 to C_OR_WIDTH-1 loop in_Bus(k) <= A(k*C_BUS_WIDTH+i); end loop; end process ORDER_INPUT_BUS_PROCESS; OR_BITS_I: entity proc_common_v4_0.or_muxcy_f generic map ( C_NUM_BITS => C_OR_WIDTH, C_FAMILY => C_FAMILY ) port map ( In_bus => in_Bus, --[in] Or_out => Y(i) --[out] ); end generate BUS_WIDTH_FOR_GEN; end architecture imp;	mit
bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/ipif_mirror128.vhd	15	17011	--SINGLE_FILE_TAG ------------------------------------------------------------------------------- -- $Id: ipif_mirror128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $ ------------------------------------------------------------------------------- -- ipif_mirror128 - entity/architecture pair ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under -- license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid -- license agreement with Xilinx, Inc. Xilinx hereby -- grants you a license to use this text/file solely for -- design, simulation, implementation and creation of -- design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly -- prohibited and immediately terminates your license unless -- covered by a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices, with no obligation on the -- part of Xilinx to provide support. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining -- any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- Any modifications that are made to the Source Code are -- done at the users sole risk and will be unsupported. -- The Xilinx Support Hotline does not have access to source -- code and therefore cannot answer specific questions related -- to source HDL. The Xilinx Hotline support of original source -- code IP shall only address issues and questions related -- to the standard Netlist version of the core (and thus -- indirectly, the original core source). -- -- Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: ipif_steer128.vhd -- Version: v1.00b -- Description: Read and Write Steering logic for IPIF -- -- For writes, this logic mirrors data from the master with -- the smaller bus width to the correct byte lanes of the -- larger IPIF devices. The BE signals are also mirrored. -- -- For reads, the Decode_size signal determines how read -- data is steered onto the byte lanes. To simplify the -- logic, the read data is mirrored onto the entire data -- bus, insuring that the lanes corrsponding to the BE's -- have correct data. -- -- -- ------------------------------------------------------------------------------- -- Structure: -- -- ipif_steer128.vhd -- ------------------------------------------------------------------------------- -- Author: Gary Burch -- History: -- GAB 10-10-2008 -- First version -- ^^^^^^ -- First version of IPIF mirror logic. -- ~~~~~~ -- -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_cmb" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; ------------------------------------------------------------------------------- -- Port declarations -- generic definitions: -- C_DWIDTH : integer := width of IPIF Slave -- C_SMALLEST : integer := width of smallest Master (not access size) -- that will access the IPIF Slave -- C_AWIDTH : integer := width of the host address bus attached to -- the IPIF -- port definitions: -- Wr_Data_In : in Write Data In (from host data bus) -- Rd_Data_In : in Read Data In (from IPIC data bus) -- Addr : in Address bus from host address bus -- BE_In : in Byte Enables In from host side -- Decode_size : in Size of Master accessing slave -- Size indication (Decode_size) -- 00 - 32-Bit Master -- 01 - 64-Bit Master -- 10 - 128-Bit Master -- 11 - 256-Bit Master (Not Support) -- -- Wr_Data_Out : out Write Data Out (to IPIF data bus) -- Rd_Data_Out : out Read Data Out (to host data bus) -- BE_Out : out Byte Enables Out to IPIF side -- ------------------------------------------------------------------------------- entity ipif_mirror128 is generic ( C_DWIDTH : integer := 32; -- 64, 128 (Slave Dwidth) C_SMALLEST : integer := 32; -- 32, 64, 128 (Smallest Master) C_AWIDTH : integer := 32 ); port ( Wr_Addr : in std_logic_vector(0 to C_AWIDTH-1); Wr_Size : in std_logic_vector(0 to 1); Rd_Addr : in std_logic_vector(0 to C_AWIDTH-1); Rd_Size : in std_logic_vector(0 to 1); Wr_Data_In : in std_logic_vector(0 to C_DWIDTH-1); Rd_Data_In : in std_logic_vector(0 to C_DWIDTH-1); BE_In : in std_logic_vector(0 to C_DWIDTH/8-1); Wr_Data_Out : out std_logic_vector(0 to C_DWIDTH-1); Rd_Data_Out : out std_logic_vector(0 to C_DWIDTH-1); BE_Out : out std_logic_vector(0 to C_DWIDTH/8-1) ); end entity ipif_mirror128; ------------------------------------------------------------------------------- -- Architecture section ------------------------------------------------------------------------------- architecture IMP of ipif_mirror128 is ------------------------------------------------------------------------------- -- Begin architecture ------------------------------------------------------------------------------- begin -- architecture IMP GEN_SAME: if C_DWIDTH <= C_SMALLEST generate Wr_Data_Out <= Wr_Data_In; BE_Out <= BE_In; Rd_Data_Out <= Rd_Data_In; end generate GEN_SAME; ------------------------------------------------------------------------------- -- Write Data Mirroring ------------------------------------------------------------------------------- --------------------- -- 64 Bit Support -- --------------------- GEN_WR_64_32: if C_DWIDTH = 64 and C_SMALLEST = 32 generate signal addr_bits : std_logic; begin CONNECT_PROC: process (addr_bits,Wr_Addr,Wr_Data_In,BE_In,Wr_Size) begin Wr_Data_Out <= Wr_Data_In; BE_Out <= BE_In; addr_bits <= Wr_Addr(C_AWIDTH-3); --a29 case addr_bits is when '0' => case Wr_Size is when "00" => -- 32-Bit Master BE_Out(4 to 7) <= (others => '0'); when others => null; end case; when '1' => case Wr_Size is when "00" => -- 32-Bit Master Wr_Data_Out(32 to 63) <= Wr_Data_In(0 to 31); BE_Out(4 to 7) <= BE_In(0 to 3); BE_Out(0 to 3) <= (others => '0'); when others => null; end case; when others => null; end case; end process CONNECT_PROC; end generate GEN_WR_64_32; --------------------- -- 128 Bit Support -- --------------------- GEN_WR_128_32: if C_DWIDTH = 128 and C_SMALLEST = 32 generate signal addr_bits : std_logic_vector(0 to 1); begin CONNECT_PROC: process (addr_bits,Wr_Addr,Wr_Data_In,BE_In,Wr_Size) begin Wr_Data_Out <= Wr_Data_In; BE_Out <= BE_In; addr_bits <= Wr_Addr(C_AWIDTH-4 to C_AWIDTH-3); case addr_bits is when "00" => --0 case Wr_Size is when "00" => -- 32-Bit Master BE_Out(4 to 15) <= (others => '0'); when "01" => -- 64-Bit Master BE_Out(8 to 15) <= (others => '0'); when others => null; end case; when "01" => --4 case Wr_Size is when "00" => -- 32-Bit Master Wr_Data_Out(32 to 63) <= Wr_Data_In(0 to 31); BE_Out(4 to 7) <= BE_In(0 to 3); BE_Out(0 to 3) <= (others => '0'); BE_Out(8 to 15) <= (others => '0'); when others => null; end case; when "10" => --8 case Wr_Size is when "00" => -- 32-Bit Master Wr_Data_Out(64 to 95) <= Wr_Data_In(0 to 31); BE_Out(8 to 11) <= BE_In(0 to 3); BE_Out(0 to 7) <= (others => '0'); BE_Out(12 to 15) <= (others => '0'); when "01" => -- 64-Bit Master Wr_Data_Out(64 to 127) <= Wr_Data_In(0 to 63); BE_Out(8 to 15) <= BE_In(0 to 7); BE_Out(0 to 7) <= (others => '0'); when others => null; end case; when "11" => --C case Wr_Size is when "00" => --32-Bit Master Wr_Data_Out(96 to 127) <= Wr_Data_In(0 to 31); BE_Out(12 to 15) <= BE_In(0 to 3); BE_Out(0 to 11) <= (others => '0'); when "01" => --64-Bit Master Wr_Data_Out(64 to 127) <= Wr_Data_In(0 to 63); BE_Out(8 to 15) <= BE_In(0 to 7); BE_Out(0 to 7) <= (others => '0'); when others => null; end case; when others => null; end case; end process CONNECT_PROC; end generate GEN_WR_128_32; GEN_WR_128_64: if C_DWIDTH = 128 and C_SMALLEST = 64 generate signal addr_bits : std_logic; begin CONNECT_PROC: process (addr_bits,Wr_Addr,Wr_Data_In,BE_In,Wr_Size) begin Wr_Data_Out <= Wr_Data_In; BE_Out <= BE_In; addr_bits <= Wr_Addr(C_AWIDTH-4); case addr_bits is when '0' => case Wr_Size is when "01" => -- 64-Bit Master BE_Out(8 to 15) <= (others => '0'); when others => null; end case; when '1' => --8 case Wr_Size is when "01" => -- 64-Bit Master Wr_Data_Out(64 to 127) <= Wr_Data_In(0 to 63); BE_Out(8 to 15) <= BE_In(0 to 7); BE_Out(0 to 7) <= (others => '0'); when others => null; end case; when others => null; end case; end process CONNECT_PROC; end generate GEN_WR_128_64; ------------------------------------------------------------------------------- -- Read Data Steering ------------------------------------------------------------------------------- --------------------- -- 64 Bit Support -- --------------------- GEN_RD_64_32: if C_DWIDTH = 64 and C_SMALLEST = 32 generate signal addr_bits : std_logic; begin CONNECT_PROC: process (addr_bits,Rd_Addr,Rd_Data_In,Rd_Size) begin Rd_Data_Out <= Rd_Data_In; addr_bits <= Rd_Addr(C_AWIDTH-3); --a29 case addr_bits is when '1' => case Rd_Size is when "00" => -- 32-Bit Master Rd_Data_Out(0 to 31) <= Rd_Data_In(32 to 63); when others => null; end case; when others => null; end case; end process CONNECT_PROC; end generate GEN_RD_64_32; --------------------- -- 128 Bit Support -- --------------------- GEN_RD_128_32: if C_DWIDTH = 128 and C_SMALLEST = 32 generate signal addr_bits : std_logic_vector(0 to 1); begin CONNECT_PROC: process (addr_bits,Rd_Addr,Rd_Data_In,Rd_Size) begin Rd_Data_Out <= Rd_Data_In; addr_bits <= Rd_Addr(C_AWIDTH-4 to C_AWIDTH-3); case addr_bits is when "01" => --4 case Rd_Size is when "00" => -- 32-Bit Master Rd_Data_Out(0 to 31) <= Rd_Data_In(32 to 63); when others => null; end case; when "10" => --8 case Rd_Size is when "00" => -- 32-Bit Master Rd_Data_Out(0 to 31) <= Rd_Data_In(64 to 95); when "01" => -- 64-Bit Master Rd_Data_Out(0 to 63) <= Rd_Data_In(64 to 127); when others => null; end case; when "11" => --C case Rd_Size is when "00" => --32-Bit Master Rd_Data_Out(0 to 31) <= Rd_Data_In(96 to 127); when "01" => --64-Bit Master Rd_Data_Out(0 to 63) <= Rd_Data_In(64 to 127); when others => null; end case; when others => null; end case; end process CONNECT_PROC; end generate GEN_RD_128_32; GEN_RD_128_64: if C_DWIDTH = 128 and C_SMALLEST = 64 generate signal addr_bits : std_logic; begin CONNECT_PROC: process (addr_bits,Rd_Addr,Rd_Data_In,Rd_Size) begin Rd_Data_Out <= Rd_Data_In; addr_bits <= Rd_Addr(C_AWIDTH-4); case addr_bits is when '1' => --8 case Rd_Size is when "01" => -- 64-Bit Master Rd_Data_Out(0 to 63) <= Rd_Data_In(64 to 127); when others => null; end case; when others => null; end case; end process CONNECT_PROC; end generate GEN_RD_128_64; end architecture IMP;	mit
djmatt/VHDL-Lib	VHDL/Muxer/demuxer.vhd	1	4036	---------------------------------------------------------------------------------------------------- -- demuxer ---------------------------------------------------------------------------------------------------- -- Matthew Dallmeyer - [email protected] ---------------------------------------------------------------------------------------------------- -- PACKAGE ---------------------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library work; package demuxer_pkg is --demuxer componenet declaration component demuxer is generic( INIT_SEL : std_logic_vector(1 downto 0) := b"01"); port( clk : in std_logic; clk_2x : in std_logic; rst : in std_logic; sigs : in std_logic_vector; sig1 : out std_logic_vector; sig2 : out std_logic_vector); end component; end package; ---------------------------------------------------------------------------------------------------- -- ENTITY ---------------------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; --This entity takes 2 input signals and interlaces them into 1 output signal. During development --it was determined that the clock inputs must be phase aligned for best results entity demuxer is generic( INIT_SEL : std_logic_vector(1 downto 0) := b"01"); port( clk : in std_logic; clk_2x : in std_logic; rst : in std_logic; sigs : in std_logic_vector; sig1 : out std_logic_vector; sig2 : out std_logic_vector); end demuxer; ---------------------------------------------------------------------------------------------------- -- ARCHITECTURE ---------------------------------------------------------------------------------------------------- architecture behave of demuxer is signal sigs_reg : std_logic_vector(sig1'range) := (others => '0'); signal selector : std_logic_vector(INIT_SEL'range) := INIT_SEL; signal sel1 : std_logic_vector(sig1'range) := (others => '0'); signal sel2 : std_logic_vector(sig2'range) := (others => '0'); signal selx : std_logic_vector(sig1'range) := (others => '0'); signal sig1_reg : std_logic_vector(sig1'range) := (others => '0'); signal sig2_reg : std_logic_vector(sig2'range) := (others => '0'); begin --Register the input reg_in : process(clk_2x) begin if(rising_edge(clk_2x)) then if(rst = '1') then sigs_reg <= (others => '0'); else sigs_reg <= sigs; end if; end if; end process; --Selection update_selection : process(clk_2x) begin if(rising_edge(clk_2x)) then if(rst = '1') then selector <= INIT_SEL; else selector <= std_logic_vector(rotate_right(unsigned(selector), 1)); end if; end if; end process; --Register the selection reg_sel : process(clk_2x) begin if(rising_edge(clk_2x)) then if(rst = '1') then sel1 <= (others => '0'); sel2 <= (others => '0'); else case selector is when b"01" => sel1 <= sigs; when b"10" => sel2 <= sigs; when others => selx <= sigs; end case; end if; end if; end process; --Register the output reg_out : process(clk) begin if(rising_edge(clk)) then if(rst = '1') then sig1_reg <= (others => '0'); sig2_reg <= (others => '0'); else sig1_reg <= sel1; sig2_reg <= sel2; end if; end if; end process; sig1 <= sig1_reg; sig2 <= sig2_reg; end behave;	mit
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bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/proc_common_v4_0/hdl/src/vhdl/srl_fifo.vhd	15	11841	------------------------------------------------------------------------------- -- $Id: srl_fifo.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $ ------------------------------------------------------------------------------- -- SRL_FIFO entity and architecture ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under -- license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid -- license agreement with Xilinx, Inc. Xilinx hereby -- grants you a license to use this text/file solely for -- design, simulation, implementation and creation of -- design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly -- prohibited and immediately terminates your license unless -- covered by a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices, with no obligation on the -- part of Xilinx to provide support. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining -- any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- Any modifications that are made to the Source Code are -- done at the users sole risk and will be unsupported. -- The Xilinx Support Hotline does not have access to source -- code and therefore cannot answer specific questions related -- to source HDL. The Xilinx Hotline support of original source -- code IP shall only address issues and questions related -- to the standard Netlist version of the core (and thus -- indirectly, the original core source). -- -- Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: srl_fifo.vhd -- -- Description: -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- srl_fifo.vhd -- ------------------------------------------------------------------------------- -- Author: goran -- Revision: $Revision: 1.1.4.1 $ -- Date: $Date: 2010/09/14 22:35:47 $ -- -- History: -- goran 2001-05-11 First Version -- KC 2001-06-20 Added Addr as an output port, for use as an occupancy -- value -- -- DCW 2002-03-12 Structural implementation of synchronous reset for -- Data_Exists DFF (using FDR) -- jam 2002-04-12 added C_XON generic for mixed vhdl/verilog sims -- -- als 2002-04-18 added default for XON generic in SRL16E, FDRE, and FDR -- component declarations -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_com" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; library unisim; use unisim.all; entity SRL_FIFO is generic ( C_DATA_BITS : natural := 8; C_DEPTH : natural := 16; C_XON : boolean := false ); port ( Clk : in std_logic; Reset : in std_logic; FIFO_Write : in std_logic; Data_In : in std_logic_vector(0 to C_DATA_BITS-1); FIFO_Read : in std_logic; Data_Out : out std_logic_vector(0 to C_DATA_BITS-1); FIFO_Full : out std_logic; Data_Exists : out std_logic; Addr : out std_logic_vector(0 to 3) -- Added Addr as a port ); end entity SRL_FIFO; architecture IMP of SRL_FIFO is component SRL16E is -- pragma translate_off generic ( INIT : bit_vector := X"0000" ); -- pragma translate_on port ( CE : in std_logic; D : in std_logic; Clk : in std_logic; A0 : in std_logic; A1 : in std_logic; A2 : in std_logic; A3 : in std_logic; Q : out std_logic); end component SRL16E; component LUT4 generic( INIT : bit_vector := X"0000" ); port ( O : out std_logic; I0 : in std_logic; I1 : in std_logic; I2 : in std_logic; I3 : in std_logic); end component; component MULT_AND port ( I0 : in std_logic; I1 : in std_logic; LO : out std_logic); end component; component MUXCY_L port ( DI : in std_logic; CI : in std_logic; S : in std_logic; LO : out std_logic); end component; component XORCY port ( LI : in std_logic; CI : in std_logic; O : out std_logic); end component; component FDRE is port ( Q : out std_logic; C : in std_logic; CE : in std_logic; D : in std_logic; R : in std_logic); end component FDRE; component FDR is port ( Q : out std_logic; C : in std_logic; D : in std_logic; R : in std_logic); end component FDR; signal addr_i : std_logic_vector(0 to 3); signal buffer_Full : std_logic; signal buffer_Empty : std_logic; signal next_Data_Exists : std_logic; signal data_Exists_I : std_logic; signal valid_Write : std_logic; signal hsum_A : std_logic_vector(0 to 3); signal sum_A : std_logic_vector(0 to 3); signal addr_cy : std_logic_vector(0 to 4); begin -- architecture IMP buffer_Full <= '1' when (addr_i = "1111") else '0'; FIFO_Full <= buffer_Full; buffer_Empty <= '1' when (addr_i = "0000") else '0'; next_Data_Exists <= (data_Exists_I and not buffer_Empty) or (buffer_Empty and FIFO_Write) or (data_Exists_I and not FIFO_Read); Data_Exists_DFF : FDR port map ( Q => data_Exists_I, -- [out std_logic] C => Clk, -- [in std_logic] D => next_Data_Exists, -- [in std_logic] R => Reset); -- [in std_logic] Data_Exists <= data_Exists_I; valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full); addr_cy(0) <= valid_Write; Addr_Counters : for I in 0 to 3 generate hsum_A(I) <= (FIFO_Read xor addr_i(I)) and (FIFO_Write or not buffer_Empty); MUXCY_L_I : MUXCY_L port map ( DI => addr_i(I), -- [in std_logic] CI => addr_cy(I), -- [in std_logic] S => hsum_A(I), -- [in std_logic] LO => addr_cy(I+1)); -- [out std_logic] XORCY_I : XORCY port map ( LI => hsum_A(I), -- [in std_logic] CI => addr_cy(I), -- [in std_logic] O => sum_A(I)); -- [out std_logic] FDRE_I : FDRE port map ( Q => addr_i(I), -- [out std_logic] C => Clk, -- [in std_logic] CE => data_Exists_I, -- [in std_logic] D => sum_A(I), -- [in std_logic] R => Reset); -- [in std_logic] end generate Addr_Counters; FIFO_RAM : for I in 0 to C_DATA_BITS-1 generate SRL16E_I : SRL16E -- pragma translate_off generic map ( INIT => x"0000") -- pragma translate_on port map ( CE => valid_Write, -- [in std_logic] D => Data_In(I), -- [in std_logic] Clk => Clk, -- [in std_logic] A0 => addr_i(0), -- [in std_logic] A1 => addr_i(1), -- [in std_logic] A2 => addr_i(2), -- [in std_logic] A3 => addr_i(3), -- [in std_logic] Q => Data_Out(I)); -- [out std_logic] end generate FIFO_RAM; ------------------------------------------------------------------------------- -- INT_ADDR_PROCESS ------------------------------------------------------------------------------- -- This process assigns the internal address to the output port ------------------------------------------------------------------------------- INT_ADDR_PROCESS:process (addr_i) begin -- process Addr <= addr_i; end process; end architecture IMP;	mit
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bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_0_0/fifo_generator_v11_0/common/wr_pf_as.vhd	19	27402	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block e5HXux03McEJscFg80ZeuZznrIJptNO1SFQrz1pWkRP7P3QoqpS2mJZRj5k487CXMg1LSvaDqmT2 OL7PFCCTiQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block hgCd2yd1Ey3kW4Xi8EYui71ziVJlfu+yPA/iSZYYtw01d1xCQQbb29qdxk14t+CL2ulbT/AG/Tph KVRTNfPiGK79TWiKACghNYtvZsEbOSiWp2tzfhZzsTJKt6Q/Tnk5KS0q9lShCg5S46ZxNmKbnoII YTwtWH6VQAWKrWw0gQI= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block tPm67AAwZoJgqE6aGdH3UBgFSYY0hEjWFTT4t/9DwITm8ODgcytWQbTKxugKHOWkwgxnsfouuhwt QO5L1ilTy6LqSek7CTlbPwPy4k6tJZltW8YhAKZe6X8IJvIcPyG5jVx+6vlxM+WibCk/roITcPkm 9mxr1ZYPG61/YergLsZha0lMNqW4wq3ID24jQg1utjPuifsU4f5hPPbAaCmkiuYhwkMNuj6VHmIU m/hi3cIAvUetwb+LazrLlZHRjTpygeOmt1PlMgoOOBXow6h7AJvjUUWQmikWL+0eXLxGX1SKnX5+ Op5qf6RZYmh6jR7nN97PHzmxB7CCeLZXWlS7Bw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block as6iakL3FcmLsNV7kgkV+92olQIBIL1+cbziWnl5Jjo3DH55nMZNZI73AcIS3DfwFYnxJCqB2SLa SuhR2kAcUXkLjAVN6C44hN7PokTEYbZ0O/DrWDwmWxnool0q47JMJkAhu6l9w278iR2KPAv+EoYt +JQKH1y1F/+RNrZ1eYU= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_auto_pc_3/fifo_generator_v11_0/common/wr_pf_as.vhd	19	27402	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block e5HXux03McEJscFg80ZeuZznrIJptNO1SFQrz1pWkRP7P3QoqpS2mJZRj5k487CXMg1LSvaDqmT2 OL7PFCCTiQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block hgCd2yd1Ey3kW4Xi8EYui71ziVJlfu+yPA/iSZYYtw01d1xCQQbb29qdxk14t+CL2ulbT/AG/Tph KVRTNfPiGK79TWiKACghNYtvZsEbOSiWp2tzfhZzsTJKt6Q/Tnk5KS0q9lShCg5S46ZxNmKbnoII YTwtWH6VQAWKrWw0gQI= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block tPm67AAwZoJgqE6aGdH3UBgFSYY0hEjWFTT4t/9DwITm8ODgcytWQbTKxugKHOWkwgxnsfouuhwt QO5L1ilTy6LqSek7CTlbPwPy4k6tJZltW8YhAKZe6X8IJvIcPyG5jVx+6vlxM+WibCk/roITcPkm 9mxr1ZYPG61/YergLsZha0lMNqW4wq3ID24jQg1utjPuifsU4f5hPPbAaCmkiuYhwkMNuj6VHmIU m/hi3cIAvUetwb+LazrLlZHRjTpygeOmt1PlMgoOOBXow6h7AJvjUUWQmikWL+0eXLxGX1SKnX5+ Op5qf6RZYmh6jR7nN97PHzmxB7CCeLZXWlS7Bw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block as6iakL3FcmLsNV7kgkV+92olQIBIL1+cbziWnl5Jjo3DH55nMZNZI73AcIS3DfwFYnxJCqB2SLa SuhR2kAcUXkLjAVN6C44hN7PokTEYbZ0O/DrWDwmWxnool0q47JMJkAhu6l9w278iR2KPAv+EoYt +JQKH1y1F/+RNrZ1eYU= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/fifo_generator_v11_0/common/wr_pf_as.vhd	19	27402	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block e5HXux03McEJscFg80ZeuZznrIJptNO1SFQrz1pWkRP7P3QoqpS2mJZRj5k487CXMg1LSvaDqmT2 OL7PFCCTiQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block hgCd2yd1Ey3kW4Xi8EYui71ziVJlfu+yPA/iSZYYtw01d1xCQQbb29qdxk14t+CL2ulbT/AG/Tph KVRTNfPiGK79TWiKACghNYtvZsEbOSiWp2tzfhZzsTJKt6Q/Tnk5KS0q9lShCg5S46ZxNmKbnoII YTwtWH6VQAWKrWw0gQI= `protect key_keyowner = "Xilinx", key_keyname= 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bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/fifo_generator_v11_0/builtin/clk_x_pntrs_builtin.vhd	19	43418	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block rMj+x3ocDbJ+0HvlMPtFLLYN4V3iOWmu0i3VYcvwPU8r9dUqilqv5BoOperD1z/j12cu4ait0bNC TvgieQY6qg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block LiFkBwHJvbvIRsrs7TuS9x+hbpgzWqPRKAN+86jD7W/DWOy2HiTI+Pr3kejl0F7PQ/wd2Tf3u0hB l5PFI7Uciy5uXiQA7fDmYLdPcNoMNQWm9hohp6Q8wB4H3kSwMFgjlrwYcv97jBF9K/DD+f6kjMEJ pjxxREwM6oJfyPhyhBI= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block mlNr/JQ7BAznEw9Lq2hOb9T0FUxDG5TxOJH6VJoPGS12EjdrVMK5Jwy/CrH7dSOtWY2eUHhpsxFO HZJnPHkoY6pnOp56kFqNAyiHJP+z5BexlWOYCHMzTTDXl5ecpknkEs/jFqX2DjV6R1MuxPdeXOjM JpDfpA+rd8xFCgAvhOcvKEKjw2lJmNukB/NqmGdLZU9Yd/iDC6mJcVuTrR2gzFDMoFjQUitH7TCG r1krtYbVQjkm691WyHmxufh/qSc3KdzrpZqycBevqxjmEqCq0nMXCiMyQRHMFNk9XLymhnx09LIk 8Ck9EeU7sTUKIMhZ7oB9NRbr0Jmue7w3V7zoXw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block jcrZIuGwyVPSe4eEqA3CjxEN8wKBf64m71qLvmqrllZ8mLFeyFjj3f796U4fol5LeUOSCUITklpk 5B0LZiT34IugfACCFG6eSa/KnYkpqdaiyFEJag2zBthAbQTJIoKzv4hrVDSwoJffRhWS6ZAZmMOH 9HJ1Z4KODhrBj2PMMOQ= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block He/hsXsp9htM4v1ezeHFxTi8NbCInK4GRCTZh00v46syUmSwf+mXhIjhLm4sHKCSUqmWt1TLUp0m CWcpoGxiawBF6wEpl5GgUNyVTq+T/CrlV9Oykyiw8ESh1/7hqCFXSES7D6yS14KOyEm1cr2UmC+u X/NTzDDvOd9e5R6zaiks/z3Qdqxiq6f6jnMuQiSiMBsAMCHxpq5kEezVTATURKXvDebBjGkSTomU Wve9JRKQPSiMHuUURnaiqzi8t62PeJzIwk64jI0DQYpuyHeGDNIZt8qQokGYPimAYp9IilmsSuGG FM6CnM5XioVenoNWDUkk1F8M0K5I/5eHgYEnkw== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 30400) `protect data_block sy6Ib3lMvpwhxxPC+M7rwVnxAGXLfvjhwSbL9qwbP13a47pbcyAYAtiBiXbPyjK/tyIySUtf7vSa /27KkY7mREwqrFv3FGqB88Gpqs7JFiB/I8qWsXo8R/PJNcQqQiygxZGy2G++1VltjcmVUFKc+iUv lEZHWhwQRBs7d/5w140Her/1aydzCPG8TA3vwh4kFyhOSY/8Z2DD4Rp2CHXxckzDJfuNUp6HVuBa A8AbDVOTOsxchTyOQRSiZmdfzqybZrGXTHJC4zYovBp3tl0VutkvVyeIF94iJ6T7abwwNkAcl8/2 RoGwAux0t5btLYN2qnqAIFKIMZRXAlZcJjaKHVglcoNCk+N+phnff6qAFFxQlMyVf17URMYPZyyM lsRoXvydSzn7hdhaW2OvlP5l+jygneHTXx7VvZbnVHnuSyfOdAZcb90R5h7c5lGYCrzU/EHIsZPo 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djmatt/VHDL-Lib	VHDL/FIR_Filter/tb_sparse_fir_filter.vhd	1	3105	-------------------------------------------------------------------------------------------------- -- FIR Filter Testbench -------------------------------------------------------------------------------------------------- -- Matthew Dallmeyer - [email protected] -------------------------------------------------------------------------------------------------- -- ENTITY -------------------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.tb_clockgen_pkg.all; use work.tb_read_csv_pkg.all; use work.tb_write_csv_pkg.all; use work.dsp_pkg.all; use work.sparse_fir_filter_pkg.all; --This module is a test-bench for simulating the fir filter entity tb_sparse_fir_filter is end tb_sparse_fir_filter; -------------------------------------------------------------------------------------------------- -- ARCHITECTURE -------------------------------------------------------------------------------------------------- architecture sim of tb_sparse_fir_filter is constant INPUT_FILE : string := "X:\Education\Masters Thesis\matlab\sparse_fir_filter\chirp.csv"; -- constant TEST_FILTER : coefficient_array := LOW_PASS_21; -- constant OUTPUT_FILE : string -- := "X:\Education\Masters Thesis\matlab\sparse_fir_filter\chirp_lowpass21.csv"; -- constant TEST_FILTER : coefficient_array := HIGH_PASS_41; -- constant OUTPUT_FILE : string -- := "X:\Education\Masters Thesis\matlab\sparse_fir_filter\chirp_highpass41.csv"; constant TEST_FILTER : coefficient_array := LOW_PASS_101; constant OUTPUT_FILE : string := "X:\Education\Masters Thesis\matlab\sparse_fir_filter\chirp_lowpass101.csv"; signal rst : std_logic := '0'; signal clk : std_logic := '0'; signal sig : std_logic_vector(NUM_SIG_BITS-1 downto 0) := (others => '0'); signal filtered : fir_sig := (others => '0'); begin --Instantiate clock generator clk1 : tb_clockgen generic map(PERIOD => 10ns, DUTY_CYCLE => 0.50) port map( clk => clk); --Instantiate file reader reader : tb_read_csv generic map(FILENAME => INPUT_FILE) port map( clk => clk, data => sig); --Instantiate unit under test uut : entity work.sparse_fir_filter(behave) generic map(h => TEST_FILTER) port map( clk => clk, rst => rst, x => signed(sig), y => filtered); --Instantiate a file writer writer : tb_write_csv generic map(FILENAME => OUTPUT_FILE) port map( clk => clk, data => std_logic_vector(filtered(30 downto 15))); --Main Process --TODO: Add a check for end of file, once reached terminate simulation. main: process begin rst <= '1'; wait for 10ns; rst <= '0'; wait; end process; end sim;	mit
bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_0_0/fifo_generator_v11_0/builtin/bin_cntr.vhd	19	8597	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block CJc8rmbxQK7PiD9FE9h/V8z28Q2yjtwOLUGOHj92X0D4bGhAiTKxH6Gs6WbTk3x8dF6WKWHXW0Xd imaqryWs/A== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block KUGgnJN/sGLwh1pfD6BBRkJkdz3qYXsMmFAG0D8TIT3kvn1DM/WYFdJfNjuI3TZJ+GjJhgQt/TQj vszszvccproNtKL+iK2kDAI+dODbmK/3dk8pZpjNIY8iqG+SZd4LOHkCbGnDn8J5L1SCb1FbgOpc lYLzGKyKMfpMp2H5zrU= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", 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bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/blk_mem_gen_wrapper.vhd	12	33638	------------------------------------------------------------------------------- -- $Id: blk_mem_gen_wrapper.vhd,v 1.1.2.69 2010/12/17 19:23:25 dougt Exp $ ------------------------------------------------------------------------------- -- blk_mem_gen_wrapper.vhd - entity/architecture pair ------------------------------------------------------------------------------- -- -- ************************************************************************** -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under -- license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid -- license agreement with Xilinx, Inc. Xilinx hereby -- grants you a license to use this text/file solely for -- design, simulation, implementation and creation of -- design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly -- prohibited and immediately terminates your license unless -- covered by a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices, with no obligation on the -- part of Xilinx to provide support. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining -- any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- Any modifications that are made to the Source Code are -- done at the users sole risk and will be unsupported. -- The Xilinx Support Hotline does not have access to source -- code and therefore cannot answer specific questions related -- to source HDL. The Xilinx Hotline support of original source -- code IP shall only address issues and questions related -- to the standard Netlist version of the core (and thus -- indirectly, the original core source). -- -- Copyright (c) 2008, 2009. 2010 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- ************************************************************************ -- ------------------------------------------------------------------------------- -- Filename: blk_mem_gen_wrapper.vhd -- Version: v1.00a -- Description: -- This wrapper file performs the direct call to Block Memory Generator -- during design implementation ------------------------------------------------------------------------------- -- ------------------------------------------------------------------------------- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- blk_mem_gen_wrapper.vhd -- \| -- \|-- blk_mem_gen_v2_7 -- \| -- \|-- blk_mem_gen_v6_2 -- ------------------------------------------------------------------------------- -- Revision History: -- -- -- Author: MW -- Revision: $Revision: 1.1.2.69 $ -- Date: $7/11/2008$ -- -- History: -- MW 7/11/2008 Initial Version -- MSH 2/26/2009 Add new blk_mem_gen version -- -- DET 4/8/2009 EDK 11.2 -- ~~~~~~ -- - Added blk_mem_gen_v3_2 instance callout -- ^^^^^^ -- -- DET 2/9/2010 for EDK 12.1 -- ~~~~~~ -- - Updated the the Blk Mem Gen version from blk_mem_gen_v3_2 -- to blk_mem_gen_v3_3 (for the S6/V6 IfGen case) -- ^^^^^^ -- -- DET 3/10/2010 For EDK 12.x -- ~~~~~~ -- -- Per CR553307 -- - Updated the the Blk Mem Gen version from blk_mem_gen_v3_3 -- to blk_mem_gen_v4_1 (for the S6/V6 IfGen case) -- ^^^^^^ -- -- DET 3/17/2010 Initial -- ~~~~~~ -- -- Per CR554253 -- - Incorporated changes to comment out FLOP_DELAY parameter from the -- blk_mem_gen_v4_1 instance. This parameter is on the XilinxCoreLib -- model for blk_mem_gen_v4_1 but is declared as a TIME type for the -- vhdl version and an integer for the verilog. -- ^^^^^^ -- -- DET 6/18/2010 EDK_MS2 -- ~~~~~~ -- -- Per IR565916 -- - Added constants FAM_IS_V6_OR_S6 and FAM_IS_NOT_V6_OR_S6. -- - Added derivative part type checks for S6 or V6. -- ^^^^^^ -- -- DET 8/27/2010 EDK 12.4 -- ~~~~~~ -- -- Per CR573867 -- - Added the the Blk Mem Gen version blk_mem_gen_v4_3 for the S6/V6 -- and later build case. -- - Updated method for derivative part support using new family -- aliasing function in family_support.vhd. -- - Incorporated an implementation to deal with unsupported FPGA -- parts passed in on the C_FAMILY parameter. -- ^^^^^^ -- -- DET 10/4/2010 EDK 13.1 -- ~~~~~~ -- - Updated to blk_mem_gen V5.2. -- ^^^^^^ -- -- DET 12/8/2010 EDK 13.1 -- ~~~~~~ -- -- Per CR586109 -- - Updated to blk_mem_gen V6.1 -- ^^^^^^ -- -- DET 12/17/2010 EDK 13.1 -- ~~~~~~ -- -- Per CR587494 -- - Regressed back to blk_mem_gen V5.2 -- ^^^^^^ -- -- DET 3/2/2011 EDk 13.2 -- ~~~~~~ -- -- Per CR595473 -- - Update to use blk_mem_gen_v6_2 for s6, v6, and later. -- ^^^^^^ -- -- DET 3/3/2011 EDK 13.2 -- ~~~~~~ -- - Removed C_ELABORATION_DIR parameter from the blk_mem_gen_v6_2 -- instance. -- ^^^^^^ -- ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synopsys translate_off --Library XilinxCoreLib; -- synopsys translate_on library blk_mem_gen_v8_1; library proc_common_v4_0; use blk_mem_gen_v8_1.all; --use proc_common_v4_0.coregen_comp_defs.all; use proc_common_v4_0.family_support.all; ------------------------------------------------------------------------------ -- Port Declaration ------------------------------------------------------------------------------ entity blk_mem_gen_wrapper is generic ( -- Device Family c_family : string := "virtex5"; -- "Virtex2" -- "Virtex4" -- "Virtex5" c_xdevicefamily : string := "virtex5"; -- Finest Resolution Device Family -- "Virtex2" -- "Virtex2-Pro" -- "Virtex4" -- "Virtex5" -- "Spartan-3A" -- "Spartan-3A DSP" c_elaboration_dir : string := ""; -- Memory Specific Configurations c_mem_type : integer := 2; -- This wrapper only supports the True Dual Port RAM -- 0: Single Port RAM -- 1: Simple Dual Port RAM -- 2: True Dual Port RAM -- 3: Single Port Rom -- 4: Dual Port RAM c_algorithm : integer := 1; -- 0: Selectable Primative -- 1: Minimum Area c_prim_type : integer := 1; -- 0: ( 1-bit wide) -- 1: ( 2-bit wide) -- 2: ( 4-bit wide) -- 3: ( 9-bit wide) -- 4: (18-bit wide) -- 5: (36-bit wide) -- 6: (72-bit wide, single port only) c_byte_size : integer := 9; -- 8 or 9 -- Simulation Behavior Options c_sim_collision_check : string := "NONE"; -- "None" -- "Generate_X" -- "All" -- "Warnings_only" c_common_clk : integer := 1; -- 0, 1 c_disable_warn_bhv_coll : integer := 0; -- 0, 1 c_disable_warn_bhv_range : integer := 0; -- 0, 1 -- Initialization Configuration Options c_load_init_file : integer := 0; c_init_file_name : string := "no_coe_file_loaded"; c_use_default_data : integer := 0; -- 0, 1 c_default_data : string := "0"; -- "..." -- Port A Specific Configurations c_has_mem_output_regs_a : integer := 0; -- 0, 1 c_has_mux_output_regs_a : integer := 0; -- 0, 1 c_write_width_a : integer := 32; -- 1 to 1152 c_read_width_a : integer := 32; -- 1 to 1152 c_write_depth_a : integer := 64; -- 2 to 9011200 c_read_depth_a : integer := 64; -- 2 to 9011200 c_addra_width : integer := 6; -- 1 to 24 c_write_mode_a : string := "WRITE_FIRST"; -- "Write_First" -- "Read_first" -- "No_Change" c_has_ena : integer := 1; -- 0, 1 c_has_regcea : integer := 0; -- 0, 1 c_has_ssra : integer := 0; -- 0, 1 c_sinita_val : string := "0"; --"..." c_use_byte_wea : integer := 0; -- 0, 1 c_wea_width : integer := 1; -- 1 to 128 -- Port B Specific Configurations c_has_mem_output_regs_b : integer := 0; -- 0, 1 c_has_mux_output_regs_b : integer := 0; -- 0, 1 c_write_width_b : integer := 32; -- 1 to 1152 c_read_width_b : integer := 32; -- 1 to 1152 c_write_depth_b : integer := 64; -- 2 to 9011200 c_read_depth_b : integer := 64; -- 2 to 9011200 c_addrb_width : integer := 6; -- 1 to 24 c_write_mode_b : string := "WRITE_FIRST"; -- "Write_First" -- "Read_first" -- "No_Change" c_has_enb : integer := 1; -- 0, 1 c_has_regceb : integer := 0; -- 0, 1 c_has_ssrb : integer := 0; -- 0, 1 c_sinitb_val : string := "0"; -- "..." c_use_byte_web : integer := 0; -- 0, 1 c_web_width : integer := 1; -- 1 to 128 -- Other Miscellaneous Configurations c_mux_pipeline_stages : integer := 0; -- 0, 1, 2, 3 -- The number of pipeline stages within the MUX -- for both Port A and Port B c_use_ecc : integer := 0; -- See DS512 for the limited core option selections for ECC support c_use_ramb16bwer_rst_bhv : integer := 0--; --0, 1 -- c_corename : string := "blk_mem_gen_v2_7" --Uncommenting the above parameter (C_CORENAME) will cause --the a failure in NGCBuild!!! ); port ( clka : in std_logic; ssra : in std_logic := '0'; dina : in std_logic_vector(c_write_width_a-1 downto 0) := (OTHERS => '0'); addra : in std_logic_vector(c_addra_width-1 downto 0); ena : in std_logic := '1'; regcea : in std_logic := '1'; wea : in std_logic_vector(c_wea_width-1 downto 0) := (OTHERS => '0'); douta : out std_logic_vector(c_read_width_a-1 downto 0); clkb : in std_logic := '0'; ssrb : in std_logic := '0'; dinb : in std_logic_vector(c_write_width_b-1 downto 0) := (OTHERS => '0'); addrb : in std_logic_vector(c_addrb_width-1 downto 0) := (OTHERS => '0'); enb : in std_logic := '1'; regceb : in std_logic := '1'; web : in std_logic_vector(c_web_width-1 downto 0) := (OTHERS => '0'); doutb : out std_logic_vector(c_read_width_b-1 downto 0); dbiterr : out std_logic; -- Double bit error that that cannot be auto corrected by ECC sbiterr : out std_logic -- Single Bit Error that has been auto corrected on the output bus ); end entity blk_mem_gen_wrapper; architecture implementation of blk_mem_gen_wrapper is Constant FAMILY_TO_USE : string := get_root_family(C_FAMILY); -- function from family_support.vhd Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily")); Constant FAMILY_IS_SUPPORTED : boolean := not(FAMILY_NOT_SUPPORTED); --Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or -- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or -- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and -- FAMILY_IS_SUPPORTED; -- --Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and -- FAMILY_IS_SUPPORTED; --Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE" signal RDADDRECC : STD_LOGIC_VECTOR(c_addrb_width-1 DOWNTO 0); signal S_AXI_AWREADY : STD_LOGIC; signal S_AXI_WREADY : STD_LOGIC; signal S_AXI_BID : STD_LOGIC_VECTOR(3 DOWNTO 0); signal S_AXI_BRESP : STD_LOGIC_VECTOR(1 DOWNTO 0); signal S_AXI_BVALID : STD_LOGIC; signal S_AXI_ARREADY : STD_LOGIC; signal S_AXI_RID : STD_LOGIC_VECTOR(3 DOWNTO 0); signal S_AXI_RDATA : STD_LOGIC_VECTOR(c_write_width_b-1 DOWNTO 0); signal S_AXI_RRESP : STD_LOGIC_VECTOR(1 DOWNTO 0); signal S_AXI_RLAST : STD_LOGIC; signal S_AXI_RVALID : STD_LOGIC; signal S_AXI_SBITERR : STD_LOGIC; signal S_AXI_DBITERR : STD_LOGIC; signal S_AXI_RDADDRECC : STD_LOGIC_VECTOR(c_addrb_width-1 DOWNTO 0); signal S_AXI_WSTRB : STD_LOGIC_VECTOR(c_wea_width-1 downto 0); signal S_AXI_WDATA : STD_LOGIC_VECTOR(c_write_width_a-1 downto 0); begin S_AXI_WSTRB <= (others => '0'); S_AXI_WDATA <= (others => '0'); ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_FAMILY -- -- If Generate Description: -- This IfGen is implemented if an unsupported FPGA family -- is passed in on the C_FAMILY parameter, -- ------------------------------------------------------------ GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate begin -- synthesis translate_off ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_ASSERTION -- -- Process Description: -- Generate a simulation error assertion for an unsupported -- FPGA family string passed in on the C_FAMILY parameter. -- ------------------------------------------------------------- DO_ASSERTION : process begin -- Wait until second rising clock edge to issue assertion Wait until clka = '1'; wait until clka = '0'; Wait until clka = '1'; -- Report an error in simulation environment assert FALSE report "******* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!" severity ERROR; Wait; -- halt this process end process DO_ASSERTION; -- synthesis translate_on -- Tie outputs to logic low douta <= (others => '0'); -- : out std_logic_vector(c_read_width_a-1 downto 0); doutb <= (others => '0'); -- : out std_logic_vector(c_read_width_b-1 downto 0); dbiterr <= '0' ; -- : out std_logic; sbiterr <= '0' ; -- : out std_logic end generate GEN_NO_FAMILY; ------------------------------------------------------------ -- If Generate -- -- Label: V6_S6_AND_LATER -- -- If Generate Description: -- This IFGen Implements the Block Memeory using blk_mem_gen 5.2. -- This is for new cores designed and tested with FPGA -- Families of Virtex-6, Spartan-6 and later. -- ------------------------------------------------------------ FAMILY_SUPPORTED: if(FAMILY_IS_SUPPORTED) generate begin ------------------------------------------------------------------------------- -- Instantiate the generalized FIFO Generator instance -- -- NOTE: -- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!! -- This is a Coregen Block Memory Generator Call module -- for new IP BRAM implementations. -- ------------------------------------------------------------------------------- I_TRUE_DUAL_PORT_BLK_MEM_GEN : entity blk_mem_gen_v8_1.blk_mem_gen_v8_1 generic map ( --C_CORENAME => c_corename , -- Device Family C_FAMILY => FAMILY_TO_USE , C_XDEVICEFAMILY => c_xdevicefamily , C_ELABORATION_DIR => c_elaboration_dir , ------------------ C_INTERFACE_TYPE => 0 , C_USE_BRAM_BLOCK => 0 , C_AXI_TYPE => 0 , C_AXI_SLAVE_TYPE => 0 , C_HAS_AXI_ID => 0 , C_AXI_ID_WIDTH => 4 , ------------------ -- Memory Specific Configurations C_MEM_TYPE => c_mem_type , C_BYTE_SIZE => c_byte_size , C_ALGORITHM => c_algorithm , C_PRIM_TYPE => c_prim_type , C_LOAD_INIT_FILE => c_load_init_file , C_INIT_FILE_NAME => c_init_file_name , C_INIT_FILE => "" , C_USE_DEFAULT_DATA => c_use_default_data , C_DEFAULT_DATA => c_default_data , -- Port A Specific Configurations C_RST_TYPE => "SYNC" , C_HAS_RSTA => c_has_ssra , C_RST_PRIORITY_A => "CE" , C_RSTRAM_A => 0 , C_INITA_VAL => c_sinita_val , C_HAS_ENA => c_has_ena , C_HAS_REGCEA => c_has_regcea , C_USE_BYTE_WEA => c_use_byte_wea , C_WEA_WIDTH => c_wea_width , C_WRITE_MODE_A => c_write_mode_a , C_WRITE_WIDTH_A => c_write_width_a , C_READ_WIDTH_A => c_read_width_a , C_WRITE_DEPTH_A => c_write_depth_a , C_READ_DEPTH_A => c_read_depth_a , C_ADDRA_WIDTH => c_addra_width , -- Port B Specific Configurations C_HAS_RSTB => c_has_ssrb , C_RST_PRIORITY_B => "CE" , C_RSTRAM_B => 0 , C_INITB_VAL => c_sinitb_val , C_HAS_ENB => c_has_enb , C_HAS_REGCEB => c_has_regceb , C_USE_BYTE_WEB => c_use_byte_web , C_WEB_WIDTH => c_web_width , C_WRITE_MODE_B => c_write_mode_b , C_WRITE_WIDTH_B => c_write_width_b , C_READ_WIDTH_B => c_read_width_b , C_WRITE_DEPTH_B => c_write_depth_b , C_READ_DEPTH_B => c_read_depth_b , C_ADDRB_WIDTH => c_addrb_width , C_HAS_MEM_OUTPUT_REGS_A => c_has_mem_output_regs_a , C_HAS_MEM_OUTPUT_REGS_B => c_has_mem_output_regs_b , C_HAS_MUX_OUTPUT_REGS_A => c_has_mux_output_regs_a , C_HAS_MUX_OUTPUT_REGS_B => c_has_mux_output_regs_b , C_HAS_SOFTECC_INPUT_REGS_A => 0 , C_HAS_SOFTECC_OUTPUT_REGS_B => 0 , -- Other Miscellaneous Configurations C_MUX_PIPELINE_STAGES => c_mux_pipeline_stages , C_USE_SOFTECC => 0 , C_USE_ECC => c_use_ecc , -- Simulation Behavior Options C_HAS_INJECTERR => 0 , C_SIM_COLLISION_CHECK => c_sim_collision_check , C_COMMON_CLK => c_common_clk , C_DISABLE_WARN_BHV_COLL => c_disable_warn_bhv_coll , C_DISABLE_WARN_BHV_RANGE => c_disable_warn_bhv_range ) port map ( CLKA => clka , RSTA => ssra , ENA => ena , REGCEA => regcea , WEA => wea , ADDRA => addra , DINA => dina , DOUTA => douta , CLKB => clkb , RSTB => ssrb , ENB => enb , REGCEB => regceb , WEB => web , ADDRB => addrb , DINB => dinb , DOUTB => doutb , INJECTSBITERR => '0' , -- input INJECTDBITERR => '0' , -- input SBITERR => sbiterr , DBITERR => dbiterr , RDADDRECC => RDADDRECC , -- output -- AXI BMG Input and Output Port Declarations -- new for v6.2 -- new for v6.2 -- AXI Global Signals -- new for v6.2 S_AClk => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2 S_ARESETN => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2 -- new for v6.2 -- AXI Full/Lite Slave Write (write side) -- new for v6.2 S_AXI_AWID => "0000" , -- : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2 S_AXI_AWADDR => "00000000000000000000000000000000" , -- : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2 S_AXI_AWLEN => "00000000" , -- : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2 S_AXI_AWSIZE => "000" , -- : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2 S_AXI_AWBURST => "00" , -- : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2 S_AXI_AWVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2 S_AXI_AWREADY => S_AXI_AWREADY , -- : OUT STD_LOGIC; -- new for v6.2 S_AXI_WDATA => S_AXI_WDATA , -- : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2 S_AXI_WSTRB => S_AXI_WSTRB , -- : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2 S_AXI_WLAST => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2 S_AXI_WVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2 S_AXI_WREADY => S_AXI_WREADY , -- : OUT STD_LOGIC; -- new for v6.2 S_AXI_BID => S_AXI_BID , -- : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2 S_AXI_BRESP => S_AXI_BRESP , -- : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- new for v6.2 S_AXI_BVALID => S_AXI_BVALID , -- : OUT STD_LOGIC; -- new for v6.2 S_AXI_BREADY => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2 -- new for v6.2 -- AXI Full/Lite Slave Read (Write side) -- new for v6.2 S_AXI_ARID => "0000" , -- : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2 S_AXI_ARADDR => "00000000000000000000000000000000" , -- : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2 S_AXI_ARLEN => "00000000" , -- : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2 S_AXI_ARSIZE => "000" , -- : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2 S_AXI_ARBURST => "00" , -- : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2 S_AXI_ARVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2 S_AXI_ARREADY => S_AXI_ARREADY , -- : OUT STD_LOGIC; -- new for v6.2 S_AXI_RID => S_AXI_RID , -- : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2 S_AXI_RDATA => S_AXI_RDATA , -- : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0); -- new for v6.2 S_AXI_RRESP => S_AXI_RRESP , -- : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0); -- new for v6.2 S_AXI_RLAST => S_AXI_RLAST , -- : OUT STD_LOGIC; -- new for v6.2 S_AXI_RVALID => S_AXI_RVALID , -- : OUT STD_LOGIC; -- new for v6.2 S_AXI_RREADY => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2 -- new for v6.2 -- AXI Full/Lite Sideband Signals -- new for v6.2 S_AXI_INJECTSBITERR => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2 S_AXI_INJECTDBITERR => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2 S_AXI_SBITERR => S_AXI_SBITERR , -- : OUT STD_LOGIC; -- new for v6.2 S_AXI_DBITERR => S_AXI_DBITERR , -- : OUT STD_LOGIC; -- new for v6.2 S_AXI_RDADDRECC => S_AXI_RDADDRECC -- : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) -- new for v6.2 ); end generate FAMILY_SUPPORTED; end implementation;	mit
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bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/fifo_generator_v11_0/ramfifo/rd_pe_sshft.vhd	19	17676	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block SOOYAbmSVdMSmEhVcX6OANZAlRBhIeIgp+j8aWie5qMiZZfkKWRKGFlDj4dOK2MxGgpLi60kolAl iwo8CvQQmg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block XO8hvx7ayNrMYNs+QowHbS9oiS1GjnY7XWvxUBWvS8S0pBwgguPJgxI5Jawjx75IEBra9z6gur8D +8bJ3wjB5uOzP0Op4TufbsYZTMy5/IRaR1m1haAiZDNWpnRaJY0iGIl1ZfXnFFB/FNm2d6rg/H7b +K1wV2KmxNsYmhxGeUs= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block qrXPktUjITPZaeyYovMGSvjyrwEeWSEPCoXArB49zu0J+taotc50izauZkw4BvtuT10+TUqV3pWu H2Y4+wBhbI0avNdhBTQ6WysNgxNkl4xSoIMSUDeWLPrThpvXqf5EM2xFWnYEsoSt1fOlTzsbNp4Z xTF0/8eRzGcTqQK8goNirFS4li1yNxnvMyocM7UB0Hgwd4r1WhVfwqexmsE2F2aKD0WceDfUKvzW BkaD/pggzoFKe9ZBj4krjm5QO6MJe6tmyETtklCe5Tp5KFVAoUG5SSUacYfOW5JRRQQN1B29KV6+ B/PXOjnEprmrDoW2/GvnZUOJ8iICUgvcDDx9Gw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block RfdpJMuL5lneUspdc3THLHWNRfMy7ZKvo7MAlgXNSeMyJ16shj6csIbQx7zWlYY0s5cmQ5qBeuky S0nRybRR8cWMHwN/9rEo4V+uesao4mJ5GbtqRFTH0pGXUIW0hSA/qLXBAZCtANiThLFmTTovXGQx QWChhP7QcQZsZBRuEUY= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block KfAPtRUOpYg8KaNj0Wxd1r4Bcs5Lt64mregrxrObBeYBNNIje2iGcuv2d5+PQzzomKwP4NoGlbzx CSYz6XLlhFat5X0Kad65Lvso8ilyZLrxVgz/cQQVMyGtqJsflyi+jbqMWdWQzDlLboEzDolIGqLM T16l7bjdTv+UHoBJFQNNpgCUB8RCwZwGjuOrDkNOQRBxFbXP4ewZBD1TITGRJ+9yag2oeIszJxFS OnxOibAvqbpn5K7zetHoNiQFD0HLxODP6ACT7OZWy2QVwDRr6smLhIBBF+7E8S7up2WgvZZ778OW 7Swo175PkHbmEfmpa+y5XkNQNOq7GC6XNCURkg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11344) `protect data_block XeolcEv1XcxF/7A6Cf/Dp/bpAs8ntvHlmi5MxmmgThFenKkDUOe0vGxkk6+KPD+i0agVeShdlmul lMhEPVzitkHiQwmsXhdtyH0Dng6XgzNj4avaL5TqEPpu9Xajl+B2bCTGRPcjUMiPxZNI4MMFHqO6 tDdxK9pjDipsCZOeCNolfFGko1pVMwWAFlRIR4D50wi9T/+J0yVYS4CYGj5qYhO7+7TTQK1thbKn kM62L9XgNsvCbmrircZTugxc9SuDEHzFq0r9tcze3bIUqrFd3nyvLpXbgCHhtRBAl6j/kabk+9Gx QKoms8bbim1d1wcIsXw5LhAgHKy3qF9LgDygsJkSclgn1Hh6VJ/2MyQRpWIR/D40H/ryvbLbElnr zrPnbwPob8ezkMHZK//tJHJjmU7iRaV+2fOQJsYFrZJ7X3cpnfOyp/3zUqc7vYCJ1UkXucgyDvuI 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bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_auto_pc_3/blk_mem_gen_v8_1/blk_mem_gen_mux.vhd	27	91985	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block PFFltKdLY0A82yxFqahMaWdN+zxj5kThYAcsDyz3A2vhpKKQpGJvV8/AkpYYPyltKlIzJB6Md9uF AN2ca05J0g== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block obdm7XtHPDQGZMrK3kNZKnRt8ypfk4aZ9VtSDpnSwNdbgwrFg4uylDkc4YjBW8BFR32vEdXmCKFe 3L1bSMhXRkPXZ88hMJlBty0IcmSYNatn3RV9VG9yYtXM73zMkJ4NIx7KoDtvOCnGQpHNAJTknAv6 BNEUXajqHzh/vB/QNBQ= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block nx2eU410BtrBCSzpvDl9pNpIplyp0nHGgzB9LvwnXgdhN5HNF/YNjnH8WXRfWZhIT380E9zFeNz1 cIYhUxogcuyFP2sgar0PDv645GG14wyLd7prd/d1E3Ur29iNukQkz59OjXTEIN/U9Gy3hPt+oLVA TwpP0P8RgeQqCkJY93IlvPGfZ/yeDQHrxDZUMFMxHHI51HM/LG6Y5RjcVEJMkX5GTsC4gSd5fEHc DWDREOSmqmG5Gmciy22xZEiB1SI044vcLqlJadcUhINRbAw0576LfZrf0pjCGq0s1+nEKeJm9MeA baA5VHd6hhXLwLD9jRkKDvFp76mdZ8cpvFpcXw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block my8iGpxybuJuMik3+8MRqWVv3aAmCE4oY3Ij0YIUQTpme5jJv8e5DOlNoLmgXWhUlepBCUyZ1Ysj JGlFKQ8MBs9R5aa1TLi8cCVfI579Nm4AO6VpackDfb6c5/BXCbiBb8XeC9Q6z0hKyH6xYDDC0Z7w m1jdROr8ONcmGBJr57g= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block pEGUMbCVqav8XqUNf0y2o1L56804gb2pssAnfqbrEzVo5CXZ9MmyISfyPG7HY7huXkJ9tWIeWtYt bUG1XTbOUAj3uDqhigkZ4KnTE/68izmD5rgLlGDQ1sI7w5GLUgtjCBINeZsiQZ8IbdNK2b2sCu2x 1k1tcyPPvRv3myvuFaOhmiYYyCNc8F9T3cW6mq34yHrMb8GcN1rGLFkL16mdIcoRSSN9znhYYcLe 21llq9uuuR5MD7mOGEYx4bKUQGVdPOHLC411Ms5bCd0IbhTC0qWispRkmO0D1uXT6TguY5Z6gKTw vMvXdJYpwStmSqzikX3kYI1zljpfWHQ7HMzzTQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 66352) `protect data_block a8U68t86Z3o/C3FQDJmOiqxctxRfzciGtiexeWX5/tf0YTY0s8Y3Y0I7bLXU1IZx4byo3l4tenB2 kusR0ylj1fHEU0otcwy6uhkEj1fBdDkfehty39aVpUPBuagKC3Im1ayCXGtzUoPoild7NpYA10ZW 2jGK3qYKQ69zfUu41oM6AJChIYA3g+BEc/OAgj2t+TnQHXwT2LsyuAmSYIFbCJCyTAyyPtpIr0Nn zBrAnG9wzCjZkgFSy8ze/vycqshGS+8Y+IyIzi3+Sa91w1OZfG2CvRoPx0zArX82JxTm5TmlFU1N Uo+UXTX5EZWlBfzrPAZfGpUtNkJslzlT3Eb3G5/98LCTJb/3TGWjL9PinvuEoEGzklGYjPZneyNc XZNYLESXa4QUcj1iroZRElWxvh5eMXAkwSIIoNIenJJFM1Q17TMT0idV3R2tNPjGjSg+ZEUqJliG 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bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/blk_mem_gen_v8_1/blk_mem_gen_mux.vhd	27	91985	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block PFFltKdLY0A82yxFqahMaWdN+zxj5kThYAcsDyz3A2vhpKKQpGJvV8/AkpYYPyltKlIzJB6Md9uF AN2ca05J0g== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block obdm7XtHPDQGZMrK3kNZKnRt8ypfk4aZ9VtSDpnSwNdbgwrFg4uylDkc4YjBW8BFR32vEdXmCKFe 3L1bSMhXRkPXZ88hMJlBty0IcmSYNatn3RV9VG9yYtXM73zMkJ4NIx7KoDtvOCnGQpHNAJTknAv6 BNEUXajqHzh/vB/QNBQ= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block nx2eU410BtrBCSzpvDl9pNpIplyp0nHGgzB9LvwnXgdhN5HNF/YNjnH8WXRfWZhIT380E9zFeNz1 cIYhUxogcuyFP2sgar0PDv645GG14wyLd7prd/d1E3Ur29iNukQkz59OjXTEIN/U9Gy3hPt+oLVA TwpP0P8RgeQqCkJY93IlvPGfZ/yeDQHrxDZUMFMxHHI51HM/LG6Y5RjcVEJMkX5GTsC4gSd5fEHc DWDREOSmqmG5Gmciy22xZEiB1SI044vcLqlJadcUhINRbAw0576LfZrf0pjCGq0s1+nEKeJm9MeA baA5VHd6hhXLwLD9jRkKDvFp76mdZ8cpvFpcXw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block my8iGpxybuJuMik3+8MRqWVv3aAmCE4oY3Ij0YIUQTpme5jJv8e5DOlNoLmgXWhUlepBCUyZ1Ysj JGlFKQ8MBs9R5aa1TLi8cCVfI579Nm4AO6VpackDfb6c5/BXCbiBb8XeC9Q6z0hKyH6xYDDC0Z7w m1jdROr8ONcmGBJr57g= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block pEGUMbCVqav8XqUNf0y2o1L56804gb2pssAnfqbrEzVo5CXZ9MmyISfyPG7HY7huXkJ9tWIeWtYt bUG1XTbOUAj3uDqhigkZ4KnTE/68izmD5rgLlGDQ1sI7w5GLUgtjCBINeZsiQZ8IbdNK2b2sCu2x 1k1tcyPPvRv3myvuFaOhmiYYyCNc8F9T3cW6mq34yHrMb8GcN1rGLFkL16mdIcoRSSN9znhYYcLe 21llq9uuuR5MD7mOGEYx4bKUQGVdPOHLC411Ms5bCd0IbhTC0qWispRkmO0D1uXT6TguY5Z6gKTw vMvXdJYpwStmSqzikX3kYI1zljpfWHQ7HMzzTQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 66352) `protect data_block a8U68t86Z3o/C3FQDJmOiqxctxRfzciGtiexeWX5/tf0YTY0s8Y3Y0I7bLXU1IZx4byo3l4tenB2 kusR0ylj1fHEU0otcwy6uhkEj1fBdDkfehty39aVpUPBuagKC3Im1ayCXGtzUoPoild7NpYA10ZW 2jGK3qYKQ69zfUu41oM6AJChIYA3g+BEc/OAgj2t+TnQHXwT2LsyuAmSYIFbCJCyTAyyPtpIr0Nn zBrAnG9wzCjZkgFSy8ze/vycqshGS+8Y+IyIzi3+Sa91w1OZfG2CvRoPx0zArX82JxTm5TmlFU1N Uo+UXTX5EZWlBfzrPAZfGpUtNkJslzlT3Eb3G5/98LCTJb/3TGWjL9PinvuEoEGzklGYjPZneyNc XZNYLESXa4QUcj1iroZRElWxvh5eMXAkwSIIoNIenJJFM1Q17TMT0idV3R2tNPjGjSg+ZEUqJliG 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bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/fifo_generator_v11_0/builtin/builtin_extdepth_v6.vhd	19	50137	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block hezhI5arYh5Ll2LsYr9SKRVb8M09iAN2m4JSbciXeqmprOA6kAYKyNVYZrZl+7uJ9rCbSy2t8SS7 C18wuehlMQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block iG3qoWxeKUs22C9+IygRgNw/Ob9GNJdHtLxrQAtYdMzP86eceFi53EP4Epvud6QFqZ+YCcJAJz6X BiP6+zFZ6SCjFFuXw9pefFKNSIH8+q7UF5dPb1d06lbHzIZD+3mRDkhnSZjrqT/zLAUZb/IQ1Lbm Z5oVMb2d2CoW5etMngE= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block lCcH3M3hshWBn3vT8V7Ds2ckpLb00IXg/NREvwDTgQ0x1n/TYrAfJvH7lJwH3QNYGbvde2S4oTtp dxVz5eb3NKybz4CG1wYBC2N8cyfQblBGlezgCm3PFTB/fb7+0CJP6o+JNkedc2s49uA9zPZB2axM QOZ+WiL1UDOqHRt1CYUPiwYxRC9z2R+kY3HwbNnbrtScHXOfjyqwc/ifFZR8DvMU1CEJYRjuFvoW cH+V2gM6YyOHMcuZuaYjA16MxseT+50plqCZJKvjkYTDhSYcuZeDAun28dPbdfRu3AO52/Kq9gTu MLy1G+7O2B+746vqe0NC8W62Tyb+rHxVnOWRgw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block NvvNy4fG+VCfM9NYumsm2clZ8IZDrJQ3Wi+cnwU6WbSkr/joDlB0ZRXsdo0mhVbkhlHdY0OhRpkR 3RYDWBuljULA6BTyF1sag+KB46HFjV7grhZmVLUbBkCWRKYz0xq7bDcNxf7s4evpI4rWpbAGWyJ9 TlfOT5npzM2PM090g2k= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block KN7EzciqITw/PNwj48fL1Z5o1AjZa3hMKXx25N37JjIMxkR/++b3PX0LoYvLH1v4MmFRO2F2HE6o +A9StU1NJwej2oLxLD63NMJa+VjJBFCfkNayO25s8BHSFsZkhjc8mIC5S+PHU5t+p8zDOXzJvXOx j/qM+zNzxFnZOpagckJWraMSJbbFjRIGq2RuUI6DTykdz7949XyxajpE+pE2TrgIaNudJhMJkV8s PmKxeai9osJTVlAQyTdS+HOwcKIcXexlGTP+JSkiagntbBuHEhDR83LTtvkaJx0GY9b8oHB0RXsI Jp2E0CkC4MgVpkaduxkwBZ7NjlyO6dFeIGiehA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 35376) `protect data_block /woyh6GJLpiwOUul1TNz4DVoF2tJq/d6R8jRy1QYhHHYUMhWROwDb8Z8HuZ1A9UehYJWQ2146G90 sGmxawsm8YvYNUVd6v7T0YYtEaCbTcGwMWUvsMPnsi+x0acBae6oHA7iCXjCClgN7+Xpgrd3hsTK bDmhpohSJ2hTEYVRU1jjkieYe2gxAw97DeiNjI9eWmeHH+G/LBkAj0DEYo3Su++WRTsKAs+9bf0i 5Q+RqZKtI4JTLUqv+JsA9t9csGY2uadHOdF4yoBMCrbUMkgZRmOimzKfx7wmIgMYe+OtyXXh/M2J D1De/Em76Ky0qEkgYLyFxDvtyF/erCwQjivqQmUlFp/gQi53TVXsEXggZB5wiH54KylVNvOLI4uA cWS2Qkt9vl6ZYzJseyCdM4PveCWsb3wl94ieTLedmzcfUmNdcAUr3GoC7Eknao3kkiy624knjWrI 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bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_0_0/fifo_generator_v11_0/ramfifo/rd_status_flags_ss.vhd	19	18129	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block IVTcVKz+qqR6KelbIxn6hKss0fyLwIejVgwej+TN1ST/vU6syUW6hxZyGugx/VRu65UT+0QU+88C 5SDN434/fA== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block W0uuDuJZlgdtFvYMz+doOP0vwnGc2SXfLiGH2a5FulZQF1GjNx3fjKnarWbbCm92Rksm2FFSGof4 SgtGKAeCq4Yz/Vqm5xuP6QHmdBwou49vkKDs52HUud9c3EaEYtdNlkb4+DCcueqZu76yWN8rf2DJ ekmu+LGiL1dmyzv30tE= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Da9hmR0COgf/nsNRjZU5mrjIzRjN0/ufJQ7crbPh82WrNgInUm192216ks1D/Quh1gQ5TieAOChY 26CHNdLfPPmjLAo5/cOIRsIuy2JD7JAEIDFhFO2BcC4GrUAhSArSC4/9FyqXrVJUKuDybwv0tWSf qpHjmJw18CiVw84ne90mESBOJ0fW1ujayfbI70yaGaFjJM/DPm4Lq+TC+TFlaimxpTFNrAUzQNVF VSkf44Zb11D7if2jaL6ua4hPGgYpPcisaJtcEYpURXS8Lw+NjmMExnMpUW39NqnMiTEPom3YBwag JMKm6/EZOnBvVc8SljH7y69fXiGUXgw6Z6POkg== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 1/llP5a+sEX6Ky1I5ak8Fr3e35uMro1bXNqkrntPBRVTqUhQPFl7wfr/6Abnu74l73YggylsZJi1 1Erm6sC9oDhL9IE4pENErrDQRZHuFnl4+DlguLd11swTlNfBwauGoCBXbTtZ8+O70UI/sRzXqbZc NDH1RywyQLhMRmSOjCU= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block OI4vyCtRzSCtjYNsCqL7rYkcvPw30aumOHoxNPQx0NU0Kc5/zvGo5pjE7sDqPsv0b00mAjKXUE8e pVllo+uquegdt9Smrq3DaiQC/9hKGiZzOG1rJH9JbLcfPMXDGpwm1inP51BNgkQwocfUEAVndeWo GE1Y28I9gt/5q5Fs/OUAX9cAh1VoS1OcnYX2wbgJSlzuLqnGWRIxOHl4+NkNkBq5Q3Xm589bPnnz m+d2tBEPyqaCTvb13xXW7hqIf0ahuv0AQTuiClY+KmF0GjLdJTWJjDWPuRd9WYhybCp/lrgDnhAK cnRXJnAOwP1Vgr7EPuoyVc3UkNsZTxEr3wrouw== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11680) `protect data_block tdwK5ZdqC1lTmlGUnRR7Yt2xC9sSxvluJ8GKoF4/PBy8cuepaO0uf0LYKTkNKeeHpd3Wema6aqcj srLXXbWWz4UGB4hdvxBJtYqwadIfgGECjDVXp6uQrfP31vtCOA9+FmtMLs4FfxWATHXFb0PTQw3G isIc6KFtVvVydNQmy1ZLPS6jP6h/lwbX8n/pnSL2WZXvrD1jm2jXxu1cc7g9OeoazdHUZzZvFix6 FgwGMXR3s27tEh4f9m5V/ihoSjMFOz87/tU/DB+DnLn7awHkl/wkbteyhhrGIUjKmzrL5F65y7N1 pUUhXTAj3RgbYQVgjkkS98xFL2X8ivYVa26+AF8gdleuWtFIrRpG06eNFIhnSLPq9gGIspbM+Ihw +/YB5GhQ/v9g9jT6Se5RLKCmFbky/wpFSjcJLcsaM2PCKL11Y5V3YFUJ6xRDmvlC9enre5fbsqYr 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bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/fifo_generator_v11_0/ramfifo/rd_status_flags_ss.vhd	19	18129	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block IVTcVKz+qqR6KelbIxn6hKss0fyLwIejVgwej+TN1ST/vU6syUW6hxZyGugx/VRu65UT+0QU+88C 5SDN434/fA== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block W0uuDuJZlgdtFvYMz+doOP0vwnGc2SXfLiGH2a5FulZQF1GjNx3fjKnarWbbCm92Rksm2FFSGof4 SgtGKAeCq4Yz/Vqm5xuP6QHmdBwou49vkKDs52HUud9c3EaEYtdNlkb4+DCcueqZu76yWN8rf2DJ ekmu+LGiL1dmyzv30tE= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Da9hmR0COgf/nsNRjZU5mrjIzRjN0/ufJQ7crbPh82WrNgInUm192216ks1D/Quh1gQ5TieAOChY 26CHNdLfPPmjLAo5/cOIRsIuy2JD7JAEIDFhFO2BcC4GrUAhSArSC4/9FyqXrVJUKuDybwv0tWSf qpHjmJw18CiVw84ne90mESBOJ0fW1ujayfbI70yaGaFjJM/DPm4Lq+TC+TFlaimxpTFNrAUzQNVF VSkf44Zb11D7if2jaL6ua4hPGgYpPcisaJtcEYpURXS8Lw+NjmMExnMpUW39NqnMiTEPom3YBwag JMKm6/EZOnBvVc8SljH7y69fXiGUXgw6Z6POkg== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 1/llP5a+sEX6Ky1I5ak8Fr3e35uMro1bXNqkrntPBRVTqUhQPFl7wfr/6Abnu74l73YggylsZJi1 1Erm6sC9oDhL9IE4pENErrDQRZHuFnl4+DlguLd11swTlNfBwauGoCBXbTtZ8+O70UI/sRzXqbZc NDH1RywyQLhMRmSOjCU= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block OI4vyCtRzSCtjYNsCqL7rYkcvPw30aumOHoxNPQx0NU0Kc5/zvGo5pjE7sDqPsv0b00mAjKXUE8e pVllo+uquegdt9Smrq3DaiQC/9hKGiZzOG1rJH9JbLcfPMXDGpwm1inP51BNgkQwocfUEAVndeWo GE1Y28I9gt/5q5Fs/OUAX9cAh1VoS1OcnYX2wbgJSlzuLqnGWRIxOHl4+NkNkBq5Q3Xm589bPnnz m+d2tBEPyqaCTvb13xXW7hqIf0ahuv0AQTuiClY+KmF0GjLdJTWJjDWPuRd9WYhybCp/lrgDnhAK cnRXJnAOwP1Vgr7EPuoyVc3UkNsZTxEr3wrouw== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11680) `protect data_block tdwK5ZdqC1lTmlGUnRR7Yt2xC9sSxvluJ8GKoF4/PBy8cuepaO0uf0LYKTkNKeeHpd3Wema6aqcj srLXXbWWz4UGB4hdvxBJtYqwadIfgGECjDVXp6uQrfP31vtCOA9+FmtMLs4FfxWATHXFb0PTQw3G isIc6KFtVvVydNQmy1ZLPS6jP6h/lwbX8n/pnSL2WZXvrD1jm2jXxu1cc7g9OeoazdHUZzZvFix6 FgwGMXR3s27tEh4f9m5V/ihoSjMFOz87/tU/DB+DnLn7awHkl/wkbteyhhrGIUjKmzrL5F65y7N1 pUUhXTAj3RgbYQVgjkkS98xFL2X8ivYVa26+AF8gdleuWtFIrRpG06eNFIhnSLPq9gGIspbM+Ihw +/YB5GhQ/v9g9jT6Se5RLKCmFbky/wpFSjcJLcsaM2PCKL11Y5V3YFUJ6xRDmvlC9enre5fbsqYr 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jakubcabal/uart_for_fpga	examples/uart2wb/uart2wbm.vhd	2	9087	-------------------------------------------------------------------------------- -- PROJECT: SIMPLE UART FOR FPGA -------------------------------------------------------------------------------- -- AUTHORS: Jakub Cabal <[email protected]> -- LICENSE: The MIT License, please read LICENSE file -- WEBSITE: https://github.com/jakubcabal/uart-for-fpga -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity UART2WBM is Generic ( CLK_FREQ : integer := 50e6; -- system clock frequency in Hz BAUD_RATE : integer := 115200 -- baud rate value ); Port ( -- CLOCK AND RESET CLK : in std_logic; RST : in std_logic; -- UART INTERFACE UART_TXD : out std_logic; UART_RXD : in std_logic; -- WISHBONE MASTER INTERFACE WB_CYC : out std_logic; WB_STB : out std_logic; WB_WE : out std_logic; WB_ADDR : out std_logic_vector(15 downto 0); WB_DOUT : out std_logic_vector(31 downto 0); WB_STALL : in std_logic; WB_ACK : in std_logic; WB_DIN : in std_logic_vector(31 downto 0) ); end entity; architecture RTL of UART2WBM is type state is (cmd, addr_low, addr_high, dout0, dout1, dout2, dout3, request, wait4ack, response, din0, din1, din2, din3); signal fsm_pstate : state; signal fsm_nstate : state; signal cmd_reg : std_logic_vector(7 downto 0); signal cmd_next : std_logic_vector(7 downto 0); signal addr_reg : std_logic_vector(15 downto 0); signal addr_next : std_logic_vector(15 downto 0); signal dout_reg : std_logic_vector(31 downto 0); signal dout_next : std_logic_vector(31 downto 0); signal din_reg : std_logic_vector(31 downto 0); signal uart_dout : std_logic_vector(7 downto 0); signal uart_dout_vld : std_logic; signal uart_din : std_logic_vector(7 downto 0); signal uart_din_vld : std_logic; signal uart_din_rdy : std_logic; begin process (CLK) begin if (rising_edge(CLK)) then cmd_reg <= cmd_next; addr_reg <= addr_next; dout_reg <= dout_next; end if; end process; WB_WE <= cmd_reg(0); WB_ADDR <= addr_reg; WB_DOUT <= dout_reg; process (CLK) begin if (rising_edge(CLK)) then if (WB_ACK = '1') then din_reg <= WB_DIN; end if; end if; end process; -- ------------------------------------------------------------------------- -- FSM -- ------------------------------------------------------------------------- process (CLK) begin if (rising_edge(CLK)) then if (RST = '1') then fsm_pstate <= cmd; else fsm_pstate <= fsm_nstate; end if; end if; end process; process (fsm_pstate, uart_dout, uart_dout_vld, cmd_reg, addr_reg, dout_reg, WB_STALL, WB_ACK, uart_din_rdy, din_reg) begin fsm_nstate <= cmd; cmd_next <= cmd_reg; addr_next <= addr_reg; dout_next <= dout_reg; WB_STB <= '0'; WB_CYC <= '0'; uart_din <= cmd_reg; uart_din_vld <= '0'; case fsm_pstate is when cmd => -- idle and read request cmd from UART cmd_next <= uart_dout; if (uart_dout_vld = '1') then fsm_nstate <= addr_low; else fsm_nstate <= cmd; end if; when addr_low => -- read low bits of address from UART addr_next(7 downto 0) <= uart_dout; if (uart_dout_vld = '1') then fsm_nstate <= addr_high; else fsm_nstate <= addr_low; end if; when addr_high => -- read high bits of address from UART addr_next(15 downto 8) <= uart_dout; if (uart_dout_vld = '1') then if (cmd_reg(0) = '1') then fsm_nstate <= dout0; -- write cmd else fsm_nstate <= request; -- read cmd end if; else fsm_nstate <= addr_high; end if; when dout0 => -- read data byte 0 from UART (write cmd only) dout_next(7 downto 0) <= uart_dout; if (uart_dout_vld = '1') then fsm_nstate <= dout1; else fsm_nstate <= dout0; end if; when dout1 => -- read data byte 1 from UART (write cmd only) dout_next(15 downto 8) <= uart_dout; if (uart_dout_vld = '1') then fsm_nstate <= dout2; else fsm_nstate <= dout1; end if; when dout2 => -- read data byte 2 from UART (write cmd only) dout_next(23 downto 16) <= uart_dout; if (uart_dout_vld = '1') then fsm_nstate <= dout3; else fsm_nstate <= dout2; end if; when dout3 => -- read data byte 3 from UART (write cmd only) dout_next(31 downto 24) <= uart_dout; if (uart_dout_vld = '1') then fsm_nstate <= request; -- write request else fsm_nstate <= dout3; end if; when request => -- send WR or RD request to Wishbone bus WB_STB <= '1'; -- request is valid WB_CYC <= '1'; if (WB_STALL = '0') then fsm_nstate <= wait4ack; else fsm_nstate <= request; end if; when wait4ack => -- wait for ACK on Wishbone bus WB_CYC <= '1'; if (WB_ACK = '1') then fsm_nstate <= response; else fsm_nstate <= wait4ack; end if; when response => -- send response cmd to UART uart_din <= cmd_reg; uart_din_vld <= '1'; if (uart_din_rdy = '1') then if (cmd_reg(0) = '1') then fsm_nstate <= cmd; -- idle or new read request cmd (write cmd only) else fsm_nstate <= din0; -- send read data to UART (read cmd only) end if; else fsm_nstate <= response; end if; when din0 => -- send read data byte 0 to UART (read cmd only) uart_din <= din_reg(7 downto 0); uart_din_vld <= '1'; if (uart_din_rdy = '1') then fsm_nstate <= din1; else fsm_nstate <= din0; end if; when din1 => -- send read data byte 1 to UART (read cmd only) uart_din <= din_reg(15 downto 8); uart_din_vld <= '1'; if (uart_din_rdy = '1') then fsm_nstate <= din2; else fsm_nstate <= din1; end if; when din2 => -- send read data byte 2 to UART (read cmd only) uart_din <= din_reg(23 downto 16); uart_din_vld <= '1'; if (uart_din_rdy = '1') then fsm_nstate <= din3; else fsm_nstate <= din2; end if; when din3 => -- send read data byte 3 to UART (read cmd only) uart_din <= din_reg(31 downto 24); uart_din_vld <= '1'; if (uart_din_rdy = '1') then fsm_nstate <= cmd; else fsm_nstate <= din3; end if; end case; end process; -- ------------------------------------------------------------------------- -- UART module -- ------------------------------------------------------------------------- uart_i : entity work.UART generic map ( CLK_FREQ => CLK_FREQ, BAUD_RATE => BAUD_RATE, PARITY_BIT => "none", USE_DEBOUNCER => True ) port map ( CLK => CLK, RST => RST, -- UART INTERFACE UART_TXD => UART_TXD, UART_RXD => UART_RXD, -- USER DATA INPUT INTERFACE DIN => uart_din, DIN_VLD => uart_din_vld, DIN_RDY => uart_din_rdy, -- USER DATA OUTPUT INTERFACE DOUT => uart_dout, DOUT_VLD => uart_dout_vld, FRAME_ERROR => open, PARITY_ERROR => open ); end architecture;	mit
bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_1_1/proc_common_v4_0/hdl/src/vhdl/pf_dpram_select.vhd	15	118961	------------------------------------------------------------------------------- -- $Id: pf_dpram_select.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $ ------------------------------------------------------------------------------- -- pf_dpram_select.vhd ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under -- license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid -- license agreement with Xilinx, Inc. Xilinx hereby -- grants you a license to use this text/file solely for -- design, simulation, implementation and creation of -- design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly -- prohibited and immediately terminates your license unless -- covered by a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices, with no obligation on the -- part of Xilinx to provide support. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining -- any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- Any modifications that are made to the Source Code are -- done at the users sole risk and will be unsupported. -- The Xilinx Support Hotline does not have access to source -- code and therefore cannot answer specific questions related -- to source HDL. The Xilinx Hotline support of original source -- code IP shall only address issues and questions related -- to the standard Netlist version of the core (and thus -- indirectly, the original core source). -- -- Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: pf_dpram_select.vhd -- -- Description: This vhdl design file uses three input parameters describing -- the desired storage depth, data width, and FPGA family type. -- From these, the design selects the optimum Block RAM -- primitive for the basic storage element and connects them -- in parallel to accomodate the desired data width. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- pf_dpram_select.vhd -- ------------------------------------------------------------------------------- -- Author: D. Thorpe -- Revision: $Revision: 1.1.4.1 $ -- Date: $Date: 2010/09/14 22:35:47 $ -- -- History: -- DET Oct. 7, 2001 First Version -- - Adopted design concepts from Goran Bilski's -- opb_bram.vhd design in the formulation of this -- design for the Mauna Loa packet FIFO dual port -- core function. -- -- DET Oct-31-2001 -- - Changed the generic input parameter C_FAMILY of type string -- back to the boolean type parameter C_VIRTEX_II. XST support -- change. -- -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_com" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library unisim; use unisim.all; -- uses BRAM primitives ------------------------------------------------------------------------------- entity pf_dpram_select is generic ( C_DP_DATA_WIDTH : Integer := 32; C_DP_ADDRESS_WIDTH : Integer := 9; C_VIRTEX_II : Boolean := true ); port ( -- Write Port signals Wr_rst : In std_logic; Wr_Clk : in std_logic; Wr_Enable : In std_logic; Wr_Req : In std_logic; Wr_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1); Wr_Data : In std_logic_vector(0 to C_DP_DATA_WIDTH-1); -- Read Port Signals Rd_rst : In std_logic; Rd_Clk : in std_logic; Rd_Enable : In std_logic; Rd_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1); Rd_Data : out std_logic_vector(0 to C_DP_DATA_WIDTH-1) ); end entity pf_dpram_select; architecture implementation of pf_dpram_select is Type family_type is ( any , x4k , x4ke , x4kl , x4kex , x4kxl , x4kxv , x4kxla , spartan , spartanxl, spartan2 , spartan2e, virtex , virtexe , virtex2 , virtex2p , unsupported ); Type bram_prim_type is ( use_srl , B4_S1_S1 , B4_S2_S2 , B4_S4_S4 , B4_S8_S8 , B4_S16_S16 , B16_S1_S1 , B16_S2_S2 , B16_S4_S4 , B16_S9_S9 , B16_S18_S18 , B16_S36_S36 , indeterminate ); ----------------------------------------------------------------------------- -- This function converts the input C_VIRTEX_II boolean type to an enumerated -- type. Only Virtex and Virtex II types are currently supported. This -- used to convert a string to a family type function but string support in -- the synthesis tools was found to be mutually exclusive between Synplicity -- and XST. ----------------------------------------------------------------------------- function get_prim_family (vertex2_select : boolean) return family_type is Variable prim_family : family_type; begin If (vertex2_select) Then prim_family := virtex2; else prim_family := virtex; End if; Return (prim_family); end function get_prim_family; ----------------------------------------------------------------------------- -- This function chooses the optimum BRAM primitive to utilize as -- specified by the inputs for data depth, data width, and FPGA part family. ----------------------------------------------------------------------------- function get_bram_primitive (target_depth: integer; target_width: integer; family : family_type ) return bram_prim_type is Variable primitive : bram_prim_type; begin Case family Is When virtex2p \| virtex2 => Case target_depth Is When 1 \| 2 => primitive := indeterminate; -- depth is too small for BRAM -- based fifo control logic When 4 \| 8 \| 16 => -- primitive := use_srl; -- activate when SRL FIFO incorporated Case target_width Is -- use BRAM for now When 1 => primitive := B16_S1_S1; When 2 => primitive := B16_S2_S2; When 3 \| 4 => primitive := B16_S4_S4; When 5 \| 6 \| 7 \| 8 \| 9 => primitive := B16_S9_S9; When 10 \| 11 \| 12 \| 13 \| 14 \| 15 \| 16 \| 17 \| 18 => primitive := B16_S18_S18; When others => primitive := B16_S36_S36; End case; when 32 \| 64 \| 128 \| 256 \| 512 => Case target_width Is When 1 => primitive := B16_S1_S1; When 2 => primitive := B16_S2_S2; When 3 \| 4 => primitive := B16_S4_S4; When 5 \| 6 \| 7 \| 8 \| 9 => primitive := B16_S9_S9; When 10 \| 11 \| 12 \| 13 \| 14 \| 15 \| 16 \| 17 \| 18 => primitive := B16_S18_S18; When others => primitive := B16_S36_S36; End case; When 1024 => Case target_width Is When 1 => primitive := B16_S1_S1; When 2 => primitive := B16_S2_S2; When 3 \| 4 => primitive := B16_S4_S4; When 5 \| 6 \| 7 \| 8 \| 9 => primitive := B16_S9_S9; When others => primitive := B16_S18_S18; End case; When 2048 => Case target_width Is When 1 => primitive := B16_S1_S1; When 2 => primitive := B16_S2_S2; When 3 \| 4 => primitive := B16_S4_S4; When others => primitive := B16_S9_S9; End case; When 4096 => Case target_width Is When 1 => primitive := B16_S1_S1; When 2 => primitive := B16_S2_S2; When others => primitive := B16_S4_S4; End case; When 8192 => Case target_width Is When 1 => primitive := B16_S1_S1; When others => primitive := B16_S2_S2; End case; When 16384 => primitive := B16_S1_S1; When others => primitive := indeterminate; End case; When spartan2 \| spartan2e \| virtex \| virtexe => Case target_depth Is When 1 \| 2 => primitive := indeterminate; -- depth is too small for BRAM -- based fifo control logic When 4 \| 8 \| 16 => -- primitive := use_srl; -- activate this when SRL FIFO is -- incorporated Case target_width Is -- use BRAM for now When 1 => primitive := B4_S1_S1; When 2 => primitive := B4_S2_S2; When 3 \| 4 => primitive := B4_S4_S4; When 5 \| 6 \| 7 \| 8 => primitive := B4_S8_S8; When others => primitive := B4_S16_S16; End case; when 32 \| 64 \| 128 \| 256 => Case target_width Is When 1 => primitive := B4_S1_S1; When 2 => primitive := B4_S2_S2; When 3 \| 4 => primitive := B4_S4_S4; When 5 \| 6 \| 7 \| 8 => primitive := B4_S8_S8; When others => primitive := B4_S16_S16; End case; when 512 => Case target_width Is When 1 => primitive := B4_S1_S1; When 2 => primitive := B4_S2_S2; When 3 \| 4 => primitive := B4_S4_S4; When others => primitive := B4_S8_S8; End case; When 1024 => Case target_width Is When 1 => primitive := B4_S1_S1; When 2 => primitive := B4_S2_S2; When others => primitive := B4_S4_S4; End case; When 2048 => Case target_width Is When 1 => primitive := B4_S1_S1; When others => primitive := B4_S2_S2; End case; When 4096 => primitive := B4_S1_S1; When others => primitive := indeterminate; End case; When others => primitive := indeterminate; End case; Return primitive; end function get_bram_primitive; ----------------------------------------------------------------------------- -- This function calculates the number of BRAM primitives required as -- specified by the inputs for data width and BRAM primitive type. ----------------------------------------------------------------------------- function get_num_prims (bram_prim : bram_prim_type; mem_width : integer) return integer is Variable bram_num : integer; begin Case bram_prim Is When B16_S1_S1 \| B4_S1_S1 => bram_num := mem_width; When B16_S2_S2 \| B4_S2_S2 => bram_num := (mem_width+1)/2; When B16_S4_S4 \| B4_S4_S4 => bram_num := (mem_width+3)/4; When B4_S8_S8 => bram_num := (mem_width+7)/8; When B16_S9_S9 => bram_num := (mem_width+8)/9; When B4_S16_S16 => bram_num := (mem_width+15)/16; When B16_S18_S18 => bram_num := (mem_width+17)/18; When B16_S36_S36 => bram_num := (mem_width+35)/36; When others => bram_num := 1; End case; Return (bram_num); end function get_num_prims; -- Now set the global CONSTANTS needed for IF-Generates -- Determine the number of BRAM storage locations needed constant FIFO_DEPTH : Integer := 2C_DP_ADDRESS_WIDTH; -- Convert the input C_VIRTEX_II generic boolean to enumerated type Constant BRAM_FAMILY : family_type := get_prim_family(C_VIRTEX_II); -- Select the optimum BRAM primitive to use constant BRAM_PRIMITIVE : bram_prim_type := get_bram_primitive(FIFO_DEPTH, C_DP_DATA_WIDTH, BRAM_FAMILY); -- Calculate how many of the selected primitives are needed -- to populate the desired data width constant BRAM_NUM : integer := get_num_prims(BRAM_PRIMITIVE, C_DP_DATA_WIDTH); begin -- architecture ---------------------------------------------------------------------------- -- Using VII 512 x 36 Dual Port Primitive ---------------------------------------------------------------------------- Using_RAMB16_S36_S36 : if (BRAM_PRIMITIVE = B16_S36_S36) generate component RAMB16_S36_S36 port (DIA : in STD_LOGIC_VECTOR (31 downto 0); DIB : in STD_LOGIC_VECTOR (31 downto 0); DIPA : in STD_LOGIC_VECTOR (3 downto 0); DIPB : in STD_LOGIC_VECTOR (3 downto 0); ENA : in std_logic; ENB : in std_logic; WEA : in std_logic; WEB : in std_logic; SSRA : in std_logic; SSRB : in std_logic; CLKA : in std_logic; CLKB : in std_logic; ADDRA : in STD_LOGIC_VECTOR (8 downto 0); ADDRB : in STD_LOGIC_VECTOR (8 downto 0); DOA : out STD_LOGIC_VECTOR (31 downto 0); DOB : out STD_LOGIC_VECTOR (31 downto 0); DOPA : out STD_LOGIC_VECTOR (3 downto 0); DOPB : out STD_LOGIC_VECTOR (3 downto 0)); end component; Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep Constant PRIM_PDBUS_WIDTH : integer := 4; -- 4 parity data bits Constant PRIM_DBUS_WIDTH : integer := 32; -- 4 parity data bits Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH + PRIM_PDBUS_WIDTH; -- (data + parity) Constant BRAM_DATA_WIDTH : integer := BRAM_NUM SLICE_DBUS_WIDTH; type dbus_slice_array is array(BRAM_NUM downto 1) of std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); type pdbus_slice_array is array(BRAM_NUM downto 1) of std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_enable : std_logic; signal port_a_wr_enable : std_logic; signal port_a_ssr : std_logic; signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_enable : std_logic; signal port_b_wr_enable : std_logic; signal port_b_ssr : std_logic; begin -- generate port_a_enable <= Wr_Enable; port_a_wr_enable <= Wr_Req; port_a_ssr <= Wr_rst; port_b_data_in <= (others => '0'); -- no input data to port B port_b_enable <= Rd_Enable; port_b_wr_enable <= '0'; -- no writing to port B port_b_ssr <= Rd_rst; -- translate big-endian and little_endian indexes of the -- data buses TRANSLATE_DATA : process (Wr_Data, port_b_data_out) Begin port_a_data_in <= (others => '0'); for i in C_DP_DATA_WIDTH-1 downto 0 loop port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i); Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i); End loop; End process TRANSLATE_DATA; -- translate big-endian and little_endian indexes of the -- address buses (makes simulation easier) TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address) Begin port_a_addr <= (others => '0'); port_b_addr <= (others => '0'); for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i); port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i); End loop; End process TRANSLATE_ADDRESS; slice_a_abus <= port_a_addr; slice_b_abus <= port_b_addr; BRAM_LOOP : for i in BRAM_NUM downto 1 generate slice_a_pdbus_in(i) <= port_a_data_in((iSLICE_DBUS_WIDTH)-1 downto (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH); slice_a_dbus_in(i) <= port_a_data_in((iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH); port_a_data_out((iSLICE_DBUS_WIDTH)-1 downto (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i); port_a_data_out((iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i); slice_b_pdbus_in(i) <= port_b_data_in((iSLICE_DBUS_WIDTH)-1 downto (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH); slice_b_dbus_in(i) <= port_b_data_in((iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH); port_b_data_out((iSLICE_DBUS_WIDTH)-1 downto (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i); port_b_data_out((iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i); -- Port A is fixed as the input (write) port -- Port B is fixed as the output (read) port I_DPB16_512x32 : RAMB16_S36_S36 port map( DIA => slice_a_dbus_in(i), DIB => slice_b_dbus_in(i), DIPA => slice_a_pdbus_in(i), DIPB => slice_b_pdbus_in(i), ENA => port_a_enable, ENB => port_b_enable, WEA => port_a_wr_enable, WEB => port_b_wr_enable, SSRA => port_a_ssr, SSRB => port_b_ssr, CLKA => Wr_Clk, CLKB => Rd_Clk, ADDRA => slice_a_abus, ADDRB => slice_b_abus, DOA => slice_a_dbus_out(i), DOB => slice_b_dbus_out(i), DOPA => slice_a_pdbus_out(i), DOPB => slice_b_pdbus_out(i) ); End generate BRAM_LOOP; end generate Using_RAMB16_S36_S36; --========================================================================== ---------------------------------------------------------------------------- -- Using VII 1024 x 18 Dual Port Primitive ---------------------------------------------------------------------------- Using_RAMB16_S18_S18 : if (BRAM_PRIMITIVE = B16_S18_S18) generate component RAMB16_S18_S18 port (DIA : in STD_LOGIC_VECTOR (15 downto 0); DIB : in STD_LOGIC_VECTOR (15 downto 0); DIPA : in STD_LOGIC_VECTOR (1 downto 0); DIPB : in STD_LOGIC_VECTOR (1 downto 0); ENA : in std_logic; ENB : in std_logic; WEA : in std_logic; WEB : in std_logic; SSRA : in std_logic; SSRB : in std_logic; CLKA : in std_logic; CLKB : in std_logic; ADDRA : in STD_LOGIC_VECTOR (9 downto 0); ADDRB : in STD_LOGIC_VECTOR (9 downto 0); DOA : out STD_LOGIC_VECTOR (15 downto 0); DOB : out STD_LOGIC_VECTOR (15 downto 0); DOPA : out STD_LOGIC_VECTOR (1 downto 0); DOPB : out STD_LOGIC_VECTOR (1 downto 0) ); end component; Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep Constant PRIM_PDBUS_WIDTH : integer := 2; -- 2 parity data bits Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH + PRIM_PDBUS_WIDTH; -- (data + parity) Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH; type dbus_slice_array is array(BRAM_NUM downto 1) of std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); type pdbus_slice_array is array(BRAM_NUM downto 1) of std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_enable : std_logic; signal port_a_wr_enable : std_logic; signal port_a_ssr : std_logic; signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_enable : std_logic; signal port_b_wr_enable : std_logic; signal port_b_ssr : std_logic; begin -- generate port_a_enable <= Wr_Enable; port_a_wr_enable <= Wr_Req; port_a_ssr <= Wr_rst; port_b_data_in <= (others => '0'); -- no input data to port B port_b_enable <= Rd_Enable; port_b_wr_enable <= '0'; -- no writing to port B port_b_ssr <= Rd_rst; -- translate big-endian and little_endian indexes of the -- data buses TRANSLATE_DATA : process (Wr_Data, port_b_data_out) Begin port_a_data_in <= (others => '0'); for i in C_DP_DATA_WIDTH-1 downto 0 loop port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i); Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i); End loop; End process TRANSLATE_DATA; -- translate big-endian and little_endian indexes of the -- address buses (makes simulation easier) TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address) Begin port_a_addr <= (others => '0'); port_b_addr <= (others => '0'); for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i); port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i); End loop; End process TRANSLATE_ADDRESS; slice_a_abus <= port_a_addr; slice_b_abus <= port_b_addr; BRAM_LOOP : for i in BRAM_NUM downto 1 generate slice_a_pdbus_in(i) <= port_a_data_in((iSLICE_DBUS_WIDTH)-1 downto (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH); slice_a_dbus_in(i) <= port_a_data_in((iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH); port_a_data_out((iSLICE_DBUS_WIDTH)-1 downto (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i); port_a_data_out((iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i); slice_b_pdbus_in(i) <= port_b_data_in((iSLICE_DBUS_WIDTH)-1 downto (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH); slice_b_dbus_in(i) <= port_b_data_in((iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH); port_b_data_out((iSLICE_DBUS_WIDTH)-1 downto (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i); port_b_data_out((iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i); -- Port A is fixed as the input (write) port -- Port B is fixed as the output (read) port I_DPB16_1024x18 : RAMB16_S18_S18 port map( DIA => slice_a_dbus_in(i), DIB => slice_b_dbus_in(i), DIPA => slice_a_pdbus_in(i), DIPB => slice_b_pdbus_in(i), ENA => port_a_enable, ENB => port_b_enable, WEA => port_a_wr_enable, WEB => port_b_wr_enable, SSRA => port_a_ssr, SSRB => port_b_ssr, CLKA => Wr_Clk, CLKB => Rd_Clk, ADDRA => slice_a_abus, ADDRB => slice_b_abus, DOA => slice_a_dbus_out(i), DOB => slice_b_dbus_out(i), DOPA => slice_a_pdbus_out(i), DOPB => slice_b_pdbus_out(i) ); End generate BRAM_LOOP; end generate Using_RAMB16_S18_S18; --========================================================================== ---------------------------------------------------------------------------- -- Using VII 2048 x 9 Dual Port Primitive ---------------------------------------------------------------------------- Using_RAMB16_S9_S9 : if (BRAM_PRIMITIVE = B16_S9_S9) generate component RAMB16_S9_S9 port ( DIA : in std_logic_vector (7 downto 0); DIB : in std_logic_vector (7 downto 0); DIPA : in std_logic_vector (0 downto 0); DIPB : in std_logic_vector (0 downto 0); ENA : in std_logic; ENB : in std_logic; WEA : in std_logic; WEB : in std_logic; SSRA : in std_logic; SSRB : in std_logic; CLKA : in std_logic; CLKB : in std_logic; ADDRA : in std_logic_vector (10 downto 0); ADDRB : in std_logic_vector (10 downto 0); DOA : out std_logic_vector (7 downto 0); DOB : out std_logic_vector (7 downto 0); DOPA : out std_logic_vector (0 downto 0); DOPB : out std_logic_vector (0 downto 0) ); end component; Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep Constant PRIM_PDBUS_WIDTH : integer := 1; -- 1 parity data bit Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH + PRIM_PDBUS_WIDTH; -- (data + parity) Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH; type dbus_slice_array is array(BRAM_NUM downto 1) of std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); type pdbus_slice_array is array(BRAM_NUM downto 1) of std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_enable : std_logic; signal port_a_wr_enable : std_logic; signal port_a_ssr : std_logic; signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_enable : std_logic; signal port_b_wr_enable : std_logic; signal port_b_ssr : std_logic; begin -- generate port_a_enable <= Wr_Enable; port_a_wr_enable <= Wr_Req; port_a_ssr <= Wr_rst; port_b_data_in <= (others => '0'); -- no input data to port B port_b_enable <= Rd_Enable; port_b_wr_enable <= '0'; -- no writing to port B port_b_ssr <= Rd_rst; -- translate big-endian and little_endian indexes of the -- data buses TRANSLATE_DATA : process (Wr_Data, port_b_data_out) Begin port_a_data_in <= (others => '0'); for i in C_DP_DATA_WIDTH-1 downto 0 loop port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i); Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i); End loop; End process TRANSLATE_DATA; -- translate big-endian and little_endian indexes of the -- address buses (makes simulation easier) TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address) Begin port_a_addr <= (others => '0'); port_b_addr <= (others => '0'); for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i); port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i); End loop; End process TRANSLATE_ADDRESS; slice_a_abus <= port_a_addr; slice_b_abus <= port_b_addr; BRAM_LOOP : for i in BRAM_NUM downto 1 generate slice_a_pdbus_in(i) <= port_a_data_in((iSLICE_DBUS_WIDTH)-1 downto (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH); slice_a_dbus_in(i) <= port_a_data_in((iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH); port_a_data_out((iSLICE_DBUS_WIDTH)-1 downto (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i); port_a_data_out((iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i); slice_b_pdbus_in(i) <= port_b_data_in((iSLICE_DBUS_WIDTH)-1 downto (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH); slice_b_dbus_in(i) <= port_b_data_in((iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH); port_b_data_out((iSLICE_DBUS_WIDTH)-1 downto (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i); port_b_data_out((iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i); -- Port A is fixed as the input (write) port -- Port B is fixed as the output (read) port I_DPB16_2048x9 : RAMB16_S9_S9 port map( DIA => slice_a_dbus_in(i), DIB => slice_b_dbus_in(i), DIPA => slice_a_pdbus_in(i), DIPB => slice_b_pdbus_in(i), ENA => port_a_enable, ENB => port_b_enable, WEA => port_a_wr_enable, WEB => port_b_wr_enable, SSRA => port_a_ssr, SSRB => port_b_ssr, CLKA => Wr_Clk, CLKB => Rd_Clk, ADDRA => slice_a_abus, ADDRB => slice_b_abus, DOA => slice_a_dbus_out(i), DOB => slice_b_dbus_out(i), DOPA => slice_a_pdbus_out(i), DOPB => slice_b_pdbus_out(i) ); End generate BRAM_LOOP; end generate Using_RAMB16_S9_S9; --========================================================================== ---------------------------------------------------------------------------- -- Using VII 4096 x 4 Dual Port Primitive ---------------------------------------------------------------------------- Using_RAMB16_S4_S4 : if (BRAM_PRIMITIVE = B16_S4_S4) generate component RAMB16_S4_S4 port ( DIA : in std_logic_vector (3 downto 0); DIB : in std_logic_vector (3 downto 0); ENA : in std_logic; ENB : in std_logic; WEA : in std_logic; WEB : in std_logic; SSRA : in std_logic; SSRB : in std_logic; CLKA : in std_logic; CLKB : in std_logic; ADDRA : in std_logic_vector (11 downto 0); ADDRB : in std_logic_vector (11 downto 0); DOA : out std_logic_vector (3 downto 0); DOB : out std_logic_vector (3 downto 0) ); end component; Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH + PRIM_PDBUS_WIDTH; -- (data + parity) Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH; type dbus_slice_array is array(BRAM_NUM downto 1) of std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); --type pdbus_slice_array is array(BRAM_NUM downto 1) of -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); --Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); --Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); --Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); --Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_enable : std_logic; signal port_a_wr_enable : std_logic; signal port_a_ssr : std_logic; signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_enable : std_logic; signal port_b_wr_enable : std_logic; signal port_b_ssr : std_logic; begin -- generate port_a_enable <= Wr_Enable; port_a_wr_enable <= Wr_Req; port_a_ssr <= Wr_rst; port_b_data_in <= (others => '0'); -- no input data to port B port_b_enable <= Rd_Enable; port_b_wr_enable <= '0'; -- no writing to port B port_b_ssr <= Rd_rst; -- translate big-endian and little_endian indexes of the -- data buses TRANSLATE_DATA : process (Wr_Data, port_b_data_out) Begin port_a_data_in <= (others => '0'); for i in C_DP_DATA_WIDTH-1 downto 0 loop port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i); Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i); End loop; End process TRANSLATE_DATA; -- translate big-endian and little_endian indexes of the -- address buses (makes simulation easier) TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address) Begin port_a_addr <= (others => '0'); port_b_addr <= (others => '0'); for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i); port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i); End loop; End process TRANSLATE_ADDRESS; slice_a_abus <= port_a_addr; slice_b_abus <= port_b_addr; BRAM_LOOP : for i in BRAM_NUM downto 1 generate --slice_a_pdbus_in(i) <= port_a_data_in((iSLICE_DBUS_WIDTH)-1 downto -- (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH); slice_a_dbus_in(i) <= port_a_data_in((iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH); --port_a_data_out((iSLICE_DBUS_WIDTH)-1 downto -- (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i); port_a_data_out((iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i); --slice_b_pdbus_in(i) <= port_b_data_in((iSLICE_DBUS_WIDTH)-1 downto -- (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH); slice_b_dbus_in(i) <= port_b_data_in((iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH); --port_b_data_out((iSLICE_DBUS_WIDTH)-1 downto -- (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i); port_b_data_out((iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i); -- Port A is fixed as the input (write) port -- Port B is fixed as the output (read) port I_DPB16_4096x4 : RAMB16_S4_S4 port map( DIA => slice_a_dbus_in(i), DIB => slice_b_dbus_in(i), ENA => port_a_enable, ENB => port_b_enable, WEA => port_a_wr_enable, WEB => port_b_wr_enable, SSRA => port_a_ssr, SSRB => port_b_ssr, CLKA => Wr_Clk, CLKB => Rd_Clk, ADDRA => slice_a_abus, ADDRB => slice_b_abus, DOA => slice_a_dbus_out(i), DOB => slice_b_dbus_out(i) ); End generate BRAM_LOOP; end generate Using_RAMB16_S4_S4; --========================================================================== ---------------------------------------------------------------------------- -- Using VII 8192 x 2 Dual Port Primitive ---------------------------------------------------------------------------- Using_RAMB16_S2_S2 : if (BRAM_PRIMITIVE = B16_S2_S2) generate component RAMB16_S2_S2 port ( DIA : in std_logic_vector (1 downto 0); DIB : in std_logic_vector (1 downto 0); ENA : in std_logic; ENB : in std_logic; WEA : in std_logic; WEB : in std_logic; SSRA : in std_logic; SSRB : in std_logic; CLKA : in std_logic; CLKB : in std_logic; ADDRA : in std_logic_vector (12 downto 0); ADDRB : in std_logic_vector (12 downto 0); DOA : out std_logic_vector (1 downto 0); DOB : out std_logic_vector (1 downto 0) ); end component; Constant PRIM_ADDR_WIDTH : integer := 13; -- 8192 deep Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH + PRIM_PDBUS_WIDTH; -- (data + parity) Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH; type dbus_slice_array is array(BRAM_NUM downto 1) of std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); --type pdbus_slice_array is array(BRAM_NUM downto 1) of -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); --Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); --Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); --Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); --Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_enable : std_logic; signal port_a_wr_enable : std_logic; signal port_a_ssr : std_logic; signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_enable : std_logic; signal port_b_wr_enable : std_logic; signal port_b_ssr : std_logic; begin -- generate port_a_enable <= Wr_Enable; port_a_wr_enable <= Wr_Req; port_a_ssr <= Wr_rst; port_b_data_in <= (others => '0'); -- no input data to port B port_b_enable <= Rd_Enable; port_b_wr_enable <= '0'; -- no writing to port B port_b_ssr <= Rd_rst; -- translate big-endian and little_endian indexes of the -- data buses TRANSLATE_DATA : process (Wr_Data, port_b_data_out) Begin port_a_data_in <= (others => '0'); for i in C_DP_DATA_WIDTH-1 downto 0 loop port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i); Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i); End loop; End process TRANSLATE_DATA; -- translate big-endian and little_endian indexes of the -- address buses (makes simulation easier) TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address) Begin port_a_addr <= (others => '0'); port_b_addr <= (others => '0'); for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i); port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i); End loop; End process TRANSLATE_ADDRESS; slice_a_abus <= port_a_addr; slice_b_abus <= port_b_addr; BRAM_LOOP : for i in BRAM_NUM downto 1 generate --slice_a_pdbus_in(i) <= port_a_data_in((iSLICE_DBUS_WIDTH)-1 downto -- (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH); slice_a_dbus_in(i) <= port_a_data_in((iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH); --port_a_data_out((iSLICE_DBUS_WIDTH)-1 downto -- (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i); port_a_data_out((iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i); --slice_b_pdbus_in(i) <= port_b_data_in((iSLICE_DBUS_WIDTH)-1 downto -- (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH); slice_b_dbus_in(i) <= port_b_data_in((iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH); --port_b_data_out((iSLICE_DBUS_WIDTH)-1 downto -- (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i); port_b_data_out((iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i); -- Port A is fixed as the input (write) port -- Port B is fixed as the output (read) port I_DPB16_8192x2 : RAMB16_S2_S2 port map( DIA => slice_a_dbus_in(i), DIB => slice_b_dbus_in(i), ENA => port_a_enable, ENB => port_b_enable, WEA => port_a_wr_enable, WEB => port_b_wr_enable, SSRA => port_a_ssr, SSRB => port_b_ssr, CLKA => Wr_Clk, CLKB => Rd_Clk, ADDRA => slice_a_abus, ADDRB => slice_b_abus, DOA => slice_a_dbus_out(i), DOB => slice_b_dbus_out(i) ); End generate BRAM_LOOP; end generate Using_RAMB16_S2_S2; --========================================================================== ---------------------------------------------------------------------------- -- Using VII 16384 x 1 Dual Port Primitive ---------------------------------------------------------------------------- Using_RAMB16_S1_S1 : if (BRAM_PRIMITIVE = B16_S1_S1) generate component RAMB16_S1_S1 port ( DIA : in std_logic_vector (0 downto 0); DIB : in std_logic_vector (0 downto 0); ENA : in std_logic; ENB : in std_logic; WEA : in std_logic; WEB : in std_logic; SSRA : in std_logic; SSRB : in std_logic; CLKA : in std_logic; CLKB : in std_logic; ADDRA : in std_logic_vector (13 downto 0); ADDRB : in std_logic_vector (13 downto 0); DOA : out std_logic_vector (0 downto 0); DOB : out std_logic_vector (0 downto 0) ); end component; Constant PRIM_ADDR_WIDTH : integer := 14; -- 16384 deep Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bits Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH + PRIM_PDBUS_WIDTH; -- (data + parity) Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH; type dbus_slice_array is array(BRAM_NUM downto 1) of std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); --type pdbus_slice_array is array(BRAM_NUM downto 1) of -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); --Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); --Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); --Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); --Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_enable : std_logic; signal port_a_wr_enable : std_logic; signal port_a_ssr : std_logic; signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_enable : std_logic; signal port_b_wr_enable : std_logic; signal port_b_ssr : std_logic; begin -- generate port_a_enable <= Wr_Enable; port_a_wr_enable <= Wr_Req; port_a_ssr <= Wr_rst; port_b_data_in <= (others => '0'); -- no input data to port B port_b_enable <= Rd_Enable; port_b_wr_enable <= '0'; -- no writing to port B port_b_ssr <= Rd_rst; -- translate big-endian and little_endian indexes of the -- data buses TRANSLATE_DATA : process (Wr_Data, port_b_data_out) Begin port_a_data_in <= (others => '0'); for i in C_DP_DATA_WIDTH-1 downto 0 loop port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i); Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i); End loop; End process TRANSLATE_DATA; -- translate big-endian and little_endian indexes of the -- address buses (makes simulation easier) TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address) Begin port_a_addr <= (others => '0'); port_b_addr <= (others => '0'); for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i); port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i); End loop; End process TRANSLATE_ADDRESS; slice_a_abus <= port_a_addr; slice_b_abus <= port_b_addr; BRAM_LOOP : for i in BRAM_NUM downto 1 generate --slice_a_pdbus_in(i) <= port_a_data_in((iSLICE_DBUS_WIDTH)-1 downto -- (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH); slice_a_dbus_in(i) <= port_a_data_in((iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH); --port_a_data_out((iSLICE_DBUS_WIDTH)-1 downto -- (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i); port_a_data_out((iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i); --slice_b_pdbus_in(i) <= port_b_data_in((iSLICE_DBUS_WIDTH)-1 downto -- (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH); slice_b_dbus_in(i) <= port_b_data_in((iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH); --port_b_data_out((iSLICE_DBUS_WIDTH)-1 downto -- (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i); port_b_data_out((iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (iSLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i); -- Port A is fixed as the input (write) port -- Port B is fixed as the output (read) port I_DPB16_16384x1 : RAMB16_S1_S1 port map( DIA => slice_a_dbus_in(i), DIB => slice_b_dbus_in(i), ENA => port_a_enable, ENB => port_b_enable, WEA => port_a_wr_enable, WEB => port_b_wr_enable, SSRA => port_a_ssr, SSRB => port_b_ssr, CLKA => Wr_Clk, CLKB => Rd_Clk, ADDRA => slice_a_abus, ADDRB => slice_b_abus, DOA => slice_a_dbus_out(i), DOB => slice_b_dbus_out(i) ); End generate BRAM_LOOP; end generate Using_RAMB16_S1_S1; --========================================================================== -- End of Virtex-II and Virtex-II Pro support --/////////////////////////////////////////////////////////////////////////// --/////////////////////////////////////////////////////////////////////////// -- Start Spartan-II, Spartan-IIE, Virtex, and VirtexE support ---------------------------------------------------------------------------- -- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE -- 4096 x 1 Dual Port Primitive ---------------------------------------------------------------------------- Using_RAMB4_S1_S1 : if (BRAM_PRIMITIVE = B4_S1_S1) generate component RAMB4_S1_S1 port ( DIA : in std_logic_vector (0 downto 0); DIB : in std_logic_vector (0 downto 0); ENA : in std_logic; ENB : in std_logic; WEA : in std_logic; WEB : in std_logic; RSTA : in std_logic; RSTB : in std_logic; CLKA : in std_logic; CLKB : in std_logic; ADDRA : in std_logic_vector (11 downto 0); ADDRB : in std_logic_vector (11 downto 0); DOA : out std_logic_vector (0 downto 0); DOB : out std_logic_vector (0 downto 0)); end component; Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bit Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH; type dbus_slice_array is array(BRAM_NUM downto 1) of std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); Signal slice_a_dbus_in : dbus_slice_array; Signal slice_a_dbus_out : dbus_slice_array; Signal slice_b_dbus_in : dbus_slice_array; Signal slice_b_dbus_out : dbus_slice_array; Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_enable : std_logic; signal port_a_wr_enable : std_logic; signal port_a_ssr : std_logic; signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_enable : std_logic; signal port_b_wr_enable : std_logic; signal port_b_ssr : std_logic; begin -- generate port_a_enable <= Wr_Enable; port_a_wr_enable <= Wr_Req; port_a_ssr <= wr_rst; -- no output reset value port_b_data_in <= (others => '0'); -- no input data to port B port_b_enable <= Rd_Enable; port_b_wr_enable <= '0'; -- no writing to port B port_b_ssr <= rd_rst; -- no output reset value -- translate big-endian and little_endian indexes of the -- data buses TRANSLATE_DATA : process (Wr_Data, port_b_data_out) Begin port_a_data_in <= (others => '0'); for i in C_DP_DATA_WIDTH-1 downto 0 loop port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i); Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i); End loop; End process TRANSLATE_DATA; -- translate big-endian and little_endian indexes of the -- address buses (makes simulation easier) TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address) Begin port_a_addr <= (others => '0'); port_b_addr <= (others => '0'); for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i); port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i); End loop; End process TRANSLATE_ADDRESS; slice_a_abus <= port_a_addr; slice_b_abus <= port_b_addr; BRAM_LOOP : for i in BRAM_NUM downto 1 generate slice_a_dbus_in(i) <= port_a_data_in((iPRIM_DBUS_WIDTH)-1 downto (iPRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH); port_a_data_out((iPRIM_DBUS_WIDTH)-1 downto (iPRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i); slice_b_dbus_in(i) <= port_b_data_in((iPRIM_DBUS_WIDTH)-1 downto (iPRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH); port_b_data_out((iPRIM_DBUS_WIDTH)-1 downto (iPRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i); -- Port A is fixed as the input (write) port -- Port B is fixed as the output (read) port I_DPB4_4096x1 : RAMB4_S1_S1 port map( DIA => slice_a_dbus_in(i), DIB => slice_b_dbus_in(i), ENA => port_a_enable, ENB => port_b_enable, WEA => port_a_wr_enable, WEB => port_b_wr_enable, RSTA => port_a_ssr, RSTB => port_b_ssr, CLKA => Wr_Clk, CLKB => Rd_Clk, ADDRA => slice_a_abus, ADDRB => slice_b_abus, DOA => slice_a_dbus_out(i), DOB => slice_b_dbus_out(i) ); End generate BRAM_LOOP; end generate Using_RAMB4_S1_S1; --========================================================================== ---------------------------------------------------------------------------- -- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE -- 2048 x 2 Dual Port Primitive ---------------------------------------------------------------------------- Using_RAMB4_S2_S2 : if (BRAM_PRIMITIVE = B4_S2_S2) generate component RAMB4_S2_S2 port ( DIA : in std_logic_vector (1 downto 0); DIB : in std_logic_vector (1 downto 0); ENA : in std_logic; ENB : in std_logic; WEA : in std_logic; WEB : in std_logic; RSTA : in std_logic; RSTB : in std_logic; CLKA : in std_logic; CLKB : in std_logic; ADDRA : in std_logic_vector (10 downto 0); ADDRB : in std_logic_vector (10 downto 0); DOA : out std_logic_vector (1 downto 0); DOB : out std_logic_vector (1 downto 0)); end component; Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH; type dbus_slice_array is array(BRAM_NUM downto 1) of std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); Signal slice_a_dbus_in : dbus_slice_array; Signal slice_a_dbus_out : dbus_slice_array; Signal slice_b_dbus_in : dbus_slice_array; Signal slice_b_dbus_out : dbus_slice_array; Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_enable : std_logic; signal port_a_wr_enable : std_logic; signal port_a_ssr : std_logic; signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_enable : std_logic; signal port_b_wr_enable : std_logic; signal port_b_ssr : std_logic; begin -- generate port_a_enable <= Wr_Enable; port_a_wr_enable <= Wr_Req; port_a_ssr <= wr_rst; -- no output reset value port_b_data_in <= (others => '0'); -- no input data to port B port_b_enable <= Rd_Enable; port_b_wr_enable <= '0'; -- no writing to port B port_b_ssr <= rd_rst; -- no output reset value -- translate big-endian and little_endian indexes of the -- data buses TRANSLATE_DATA : process (Wr_Data, port_b_data_out) Begin port_a_data_in <= (others => '0'); for i in C_DP_DATA_WIDTH-1 downto 0 loop port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i); Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i); End loop; End process TRANSLATE_DATA; -- translate big-endian and little_endian indexes of the -- address buses (makes simulation easier) TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address) Begin port_a_addr <= (others => '0'); port_b_addr <= (others => '0'); for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i); port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i); End loop; End process TRANSLATE_ADDRESS; slice_a_abus <= port_a_addr; slice_b_abus <= port_b_addr; BRAM_LOOP : for i in BRAM_NUM downto 1 generate slice_a_dbus_in(i) <= port_a_data_in((iPRIM_DBUS_WIDTH)-1 downto (iPRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH); port_a_data_out((iPRIM_DBUS_WIDTH)-1 downto (iPRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i); slice_b_dbus_in(i) <= port_b_data_in((iPRIM_DBUS_WIDTH)-1 downto (iPRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH); port_b_data_out((iPRIM_DBUS_WIDTH)-1 downto (iPRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i); -- Port A is fixed as the input (write) port -- Port B is fixed as the output (read) port I_DPB4_2048x2 : RAMB4_S2_S2 port map( DIA => slice_a_dbus_in(i), DIB => slice_b_dbus_in(i), ENA => port_a_enable, ENB => port_b_enable, WEA => port_a_wr_enable, WEB => port_b_wr_enable, RSTA => port_a_ssr, RSTB => port_b_ssr, CLKA => Wr_Clk, CLKB => Rd_Clk, ADDRA => slice_a_abus, ADDRB => slice_b_abus, DOA => slice_a_dbus_out(i), DOB => slice_b_dbus_out(i) ); End generate BRAM_LOOP; end generate Using_RAMB4_S2_S2; --========================================================================== ---------------------------------------------------------------------------- -- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE -- 1024 x 4 Dual Port Primitive ---------------------------------------------------------------------------- Using_RAMB4_S4_S4 : if (BRAM_PRIMITIVE = B4_S4_S4) generate component RAMB4_S4_S4 port ( DIA : in std_logic_vector (3 downto 0); DIB : in std_logic_vector (3 downto 0); ENA : in std_logic; ENB : in std_logic; WEA : in std_logic; WEB : in std_logic; RSTA : in std_logic; RSTB : in std_logic; CLKA : in std_logic; CLKB : in std_logic; ADDRA : in std_logic_vector (9 downto 0); ADDRB : in std_logic_vector (9 downto 0); DOA : out std_logic_vector (3 downto 0); DOB : out std_logic_vector (3 downto 0)); end component; Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH; type dbus_slice_array is array(BRAM_NUM downto 1) of std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); Signal slice_a_dbus_in : dbus_slice_array; Signal slice_a_dbus_out : dbus_slice_array; Signal slice_b_dbus_in : dbus_slice_array; Signal slice_b_dbus_out : dbus_slice_array; Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_enable : std_logic; signal port_a_wr_enable : std_logic; signal port_a_ssr : std_logic; signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_enable : std_logic; signal port_b_wr_enable : std_logic; signal port_b_ssr : std_logic; begin -- generate port_a_enable <= Wr_Enable; port_a_wr_enable <= Wr_Req; port_a_ssr <= wr_rst; -- no output reset value port_b_data_in <= (others => '0'); -- no input data to port B port_b_enable <= Rd_Enable; port_b_wr_enable <= '0'; -- no writing to port B port_b_ssr <= rd_rst; -- no output reset value -- translate big-endian and little_endian indexes of the -- data buses TRANSLATE_DATA : process (Wr_Data, port_b_data_out) Begin port_a_data_in <= (others => '0'); for i in C_DP_DATA_WIDTH-1 downto 0 loop port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i); Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i); End loop; End process TRANSLATE_DATA; -- translate big-endian and little_endian indexes of the -- address buses (makes simulation easier) TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address) Begin port_a_addr <= (others => '0'); port_b_addr <= (others => '0'); for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i); port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i); End loop; End process TRANSLATE_ADDRESS; slice_a_abus <= port_a_addr; slice_b_abus <= port_b_addr; BRAM_LOOP : for i in BRAM_NUM downto 1 generate slice_a_dbus_in(i) <= port_a_data_in((iPRIM_DBUS_WIDTH)-1 downto (iPRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH); port_a_data_out((iPRIM_DBUS_WIDTH)-1 downto (iPRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i); slice_b_dbus_in(i) <= port_b_data_in((iPRIM_DBUS_WIDTH)-1 downto (iPRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH); port_b_data_out((iPRIM_DBUS_WIDTH)-1 downto (iPRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i); -- Port A is fixed as the input (write) port -- Port B is fixed as the output (read) port I_DPB4_1024x4 : RAMB4_S4_S4 port map( DIA => slice_a_dbus_in(i), DIB => slice_b_dbus_in(i), ENA => port_a_enable, ENB => port_b_enable, WEA => port_a_wr_enable, WEB => port_b_wr_enable, RSTA => port_a_ssr, RSTB => port_b_ssr, CLKA => Wr_Clk, CLKB => Rd_Clk, ADDRA => slice_a_abus, ADDRB => slice_b_abus, DOA => slice_a_dbus_out(i), DOB => slice_b_dbus_out(i) ); End generate BRAM_LOOP; end generate Using_RAMB4_S4_S4; --========================================================================== ---------------------------------------------------------------------------- -- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE -- 512 x 8 Dual Port Primitive ---------------------------------------------------------------------------- Using_RAMB4_S8_S8 : if (BRAM_PRIMITIVE = B4_S8_S8) generate component RAMB4_S8_S8 port ( DIA : in std_logic_vector (7 downto 0); DIB : in std_logic_vector (7 downto 0); ENA : in std_logic; ENB : in std_logic; WEA : in std_logic; WEB : in std_logic; RSTA : in std_logic; RSTB : in std_logic; CLKA : in std_logic; CLKB : in std_logic; ADDRA : in std_logic_vector (8 downto 0); ADDRB : in std_logic_vector (8 downto 0); DOA : out std_logic_vector (7 downto 0); DOB : out std_logic_vector (7 downto 0)); end component; Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH; type dbus_slice_array is array(BRAM_NUM downto 1) of std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); Signal slice_a_dbus_in : dbus_slice_array; Signal slice_a_dbus_out : dbus_slice_array; Signal slice_b_dbus_in : dbus_slice_array; Signal slice_b_dbus_out : dbus_slice_array; Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_enable : std_logic; signal port_a_wr_enable : std_logic; signal port_a_ssr : std_logic; signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_enable : std_logic; signal port_b_wr_enable : std_logic; signal port_b_ssr : std_logic; begin -- generate port_a_enable <= Wr_Enable; port_a_wr_enable <= Wr_Req; port_a_ssr <= wr_rst; -- no output reset value port_b_data_in <= (others => '0'); -- no input data to port B port_b_enable <= Rd_Enable; port_b_wr_enable <= '0'; -- no writing to port B port_b_ssr <= rd_rst; -- no output reset value -- translate big-endian and little_endian indexes of the -- data buses TRANSLATE_DATA : process (Wr_Data, port_b_data_out) Begin port_a_data_in <= (others => '0'); for i in C_DP_DATA_WIDTH-1 downto 0 loop port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i); Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i); End loop; End process TRANSLATE_DATA; -- translate big-endian and little_endian indexes of the -- address buses (makes simulation easier) TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address) Begin port_a_addr <= (others => '0'); port_b_addr <= (others => '0'); for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i); port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i); End loop; End process TRANSLATE_ADDRESS; slice_a_abus <= port_a_addr; slice_b_abus <= port_b_addr; BRAM_LOOP : for i in BRAM_NUM downto 1 generate slice_a_dbus_in(i) <= port_a_data_in((iPRIM_DBUS_WIDTH)-1 downto (iPRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH); port_a_data_out((iPRIM_DBUS_WIDTH)-1 downto (iPRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i); slice_b_dbus_in(i) <= port_b_data_in((iPRIM_DBUS_WIDTH)-1 downto (iPRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH); port_b_data_out((iPRIM_DBUS_WIDTH)-1 downto (iPRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i); -- Port A is fixed as the input (write) port -- Port B is fixed as the output (read) port I_DPB4_512x8 : RAMB4_S8_S8 port map( DIA => slice_a_dbus_in(i), DIB => slice_b_dbus_in(i), ENA => port_a_enable, ENB => port_b_enable, WEA => port_a_wr_enable, WEB => port_b_wr_enable, RSTA => port_a_ssr, RSTB => port_b_ssr, CLKA => Wr_Clk, CLKB => Rd_Clk, ADDRA => slice_a_abus, ADDRB => slice_b_abus, DOA => slice_a_dbus_out(i), DOB => slice_b_dbus_out(i) ); End generate BRAM_LOOP; end generate Using_RAMB4_S8_S8; --========================================================================== ---------------------------------------------------------------------------- -- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE -- 256 x 16 Dual Port Primitive ---------------------------------------------------------------------------- Using_RAMB4_S16_S16 : if (BRAM_PRIMITIVE = B4_S16_S16) generate component RAMB4_S16_S16 port (DIA : in STD_LOGIC_VECTOR (15 downto 0); DIB : in STD_LOGIC_VECTOR (15 downto 0); ENA : in std_logic; ENB : in std_logic; WEA : in std_logic; WEB : in std_logic; RSTA : in std_logic; RSTB : in std_logic; CLKA : in std_logic; CLKB : in std_logic; ADDRA : in STD_LOGIC_VECTOR (7 downto 0); ADDRB : in STD_LOGIC_VECTOR (7 downto 0); DOA : out STD_LOGIC_VECTOR (15 downto 0); DOB : out STD_LOGIC_VECTOR (15 downto 0)); end component; Constant PRIM_ADDR_WIDTH : integer := 8; -- 256 deep Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH; type dbus_slice_array is array(BRAM_NUM downto 1) of std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); Signal slice_a_dbus_in : dbus_slice_array; Signal slice_a_dbus_out : dbus_slice_array; Signal slice_b_dbus_in : dbus_slice_array; Signal slice_b_dbus_out : dbus_slice_array; Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_enable : std_logic; signal port_a_wr_enable : std_logic; signal port_a_ssr : std_logic; signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_enable : std_logic; signal port_b_wr_enable : std_logic; signal port_b_ssr : std_logic; begin -- generate port_a_enable <= Wr_Enable; port_a_wr_enable <= Wr_Req; port_a_ssr <= wr_rst; -- no output reset value port_b_data_in <= (others => '0'); -- no input data to port B port_b_enable <= Rd_Enable; port_b_wr_enable <= '0'; -- no writing to port B port_b_ssr <= rd_rst; -- no output reset value -- translate big-endian and little_endian indexes of the -- data buses TRANSLATE_DATA : process (Wr_Data, port_b_data_out) Begin port_a_data_in <= (others => '0'); for i in C_DP_DATA_WIDTH-1 downto 0 loop port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i); Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i); End loop; End process TRANSLATE_DATA; -- translate big-endian and little_endian indexes of the -- address buses (makes simulation easier) TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address) Begin port_a_addr <= (others => '0'); port_b_addr <= (others => '0'); for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i); port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i); End loop; End process TRANSLATE_ADDRESS; slice_a_abus <= port_a_addr; slice_b_abus <= port_b_addr; BRAM_LOOP : for i in BRAM_NUM downto 1 generate slice_a_dbus_in(i) <= port_a_data_in((iPRIM_DBUS_WIDTH)-1 downto (iPRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH); port_a_data_out((iPRIM_DBUS_WIDTH)-1 downto (iPRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i); slice_b_dbus_in(i) <= port_b_data_in((iPRIM_DBUS_WIDTH)-1 downto (iPRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH); port_b_data_out((iPRIM_DBUS_WIDTH)-1 downto (iPRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i); -- Port A is fixed as the input (write) port -- Port B is fixed as the output (read) port I_DPB4_256x16 : RAMB4_S16_S16 port map( DIA => slice_a_dbus_in(i), DIB => slice_b_dbus_in(i), ENA => port_a_enable, ENB => port_b_enable, WEA => port_a_wr_enable, WEB => port_b_wr_enable, RSTA => port_a_ssr, RSTB => port_b_ssr, CLKA => Wr_Clk, CLKB => Rd_Clk, ADDRA => slice_a_abus, ADDRB => slice_b_abus, DOA => slice_a_dbus_out(i), DOB => slice_b_dbus_out(i) ); End generate BRAM_LOOP; end generate Using_RAMB4_S16_S16; --========================================================================== UNSUPPORTED_FAMILY : if (BRAM_PRIMITIVE = indeterminate) generate begin -- assert (false) -- report "Unsupported Part Family Selected or FIFO Depth/Width is invalid!" -- severity failure; -- end generate UNSUPPORTED_FAMILY; end architecture implementation;	mit
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bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_1_1/proc_common_v4_0/hdl/src/vhdl/inferred_lut4.vhd	15	7214	------------------------------------------------------------------------------- -- $Id: inferred_lut4.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $ ------------------------------------------------------------------------------- -- inferred_lut4.vhd ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under -- license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid -- license agreement with Xilinx, Inc. Xilinx hereby -- grants you a license to use this text/file solely for -- design, simulation, implementation and creation of -- design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly -- prohibited and immediately terminates your license unless -- covered by a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices, with no obligation on the -- part of Xilinx to provide support. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining -- any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- Any modifications that are made to the Source Code are -- done at the users sole risk and will be unsupported. -- The Xilinx Support Hotline does not have access to source -- code and therefore cannot answer specific questions related -- to source HDL. The Xilinx Hotline support of original source -- code IP shall only address issues and questions related -- to the standard Netlist version of the core (and thus -- indirectly, the original core source). -- -- Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: inferred_lut4.vhd -- -- Description: This module is used to infer a LUT4 instantiation in -- structural VHDL. It is compatable with Synplicity and xst -- synthesis tools. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- inferred_lut4.vhd -- ------------------------------------------------------------------------------- -- Author: D.Thorpe -- -- History: -- DET 2001-10-11 LUT4 implementation to work around xst lut4 problem with -- INIT generic. Adapted from XST France work-around -- solution sent to Bert Tise. -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "Bus_clk", "Bus_clk_div#", "Bus_clk_#x" -- Bus_rst signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_com" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library ieee; use ieee.std_logic_arith.all; library ieee; use ieee.std_logic_unsigned.all; ------------------------------------------------------------------------------- entity inferred_lut4 is generic (INIT : bit_vector(15 downto 0)); port ( O : out std_logic; I0 : in std_logic; I1 : in std_logic; I2 : in std_logic; I3 : in std_logic ); end entity inferred_lut4; ------------------------------------------------------------------------------- architecture implementation of inferred_lut4 is signal b : std_logic_vector(3 downto 0); signal tmp : integer range 0 to 15; begin b <= (I3, I2, I1, I0); tmp <= conv_integer(b); O <= To_StdUlogic(INIT(tmp)); end architecture implementation;	mit
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bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/fifo_generator_v11_0/ramfifo/bram_fifo_rstlogic.vhd	19	21262	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block dKfOe1Fgzj6faSFeL/IK/IGbXRIzt9OQ8DZnq2KAQwbAq1xs/txiDbhMB5jT5GTGOpfv1lX7K9mJ mDVaIsrDmA== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block cmnaZ+nYMcuVxuKDdMnuchBB9inZOxPR3/E/irYVdWCPhl0UM4JuWPFoKMQnAcsoQ3vgnwO/qltn 0x8JvlvddPokOTwabXK7+R741NBmTaawP5Y3zobRhI33jusePpwNTanCHaHjalZxzALXRseOguzG AwGiKgpBkrzwT+frUqs= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block sUxQSwzYYe52m4+VJThnA3rSxL81p7y01A34NmBjYzEeDRUnhBCVE2EYcZxUZHf3SzWeAqe17qZn +OUEYPsHFdXLy5QnKWkfeT6eelEedeGrqLjWta/XE+CwvggarDRC3yCpKHD1RObvSaidPkoLOQaz Mr6i41kRIdL7xQbC4uLsdgEZKWh/fWAVQ0EsVnkKqE8EuxaCZ+UTjEptEyr1FyibFlRQuCcRV1zc KGcqqHxwzSvE0/TqNDvaxlN4HZAny51ra9dxL1achi8jzJgZlO8wt9Agqbh7GQueaCXon2S1zoWz ehgKeTmxlL7ytzeVDSpaRq2XKBPlYb/82fe70w== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block nlRZm6Q4mAeDfFS8oXcdcSIf6QMcM0qJWL/GpoNfKsPw7GwRrG7w5Fv9DZ3ev8dGDXi3ZhhDXcQa Irin1hT7IkRZSupkXr6uysVtJeCdG/feYDkdTZzOR87EjbK5yer40aqraNg1lVIuObcgZ8AniYE5 0hMf7gQTkG+H4+tX0yk= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) 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bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_1_1/proc_common_v4_0/hdl/src/vhdl/pf_occ_counter.vhd	15	10945	------------------------------------------------------------------------------- -- $Id: pf_occ_counter.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $ ------------------------------------------------------------------------------- -- pf_occ_counter - entity/architecture pair ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under -- license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid -- license agreement with Xilinx, Inc. Xilinx hereby -- grants you a license to use this text/file solely for -- design, simulation, implementation and creation of -- design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly -- prohibited and immediately terminates your license unless -- covered by a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices, with no obligation on the -- part of Xilinx to provide support. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining -- any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- Any modifications that are made to the Source Code are -- done at the users sole risk and will be unsupported. -- The Xilinx Support Hotline does not have access to source -- code and therefore cannot answer specific questions related -- to source HDL. The Xilinx Hotline support of original source -- code IP shall only address issues and questions related -- to the standard Netlist version of the core (and thus -- indirectly, the original core source). -- -- Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: pf_occ_counter.vhd -- -- Description: Implements packet fifo occupancy counter. This special -- counter provides these functions: -- - up/down count control -- - pre-increment/pre-decrement of input load value -- - count by 2 -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- pf_occ_counter.vhd -- ------------------------------------------------------------------------------- -- Author: B.L. Tise -- Revision: $Revision: 1.1.4.1 $ -- Date: $Date: 2010/09/14 22:35:47 $ -- -- History: -- D. Thorpe 2001-09-07 First Version -- - adapted from B Tise MicroBlaze counters -- -- DET 2001-09-11 -- - Added the Rst signal connect to the pf_counter_bit module -- -- DET 2002-02-24 -- - Changed the use of MUXCY_L to MUXCY. -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Changed proc_common library version to v4_0 -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_com" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; library unisim; use unisim.vcomponents.all; library proc_common_v4_0; use proc_common_v4_0.pf_counter_bit; ----------------------------------------------------------------------------- -- Entity section ----------------------------------------------------------------------------- entity pf_occ_counter is generic ( C_COUNT_WIDTH : integer := 9 ); port ( Clk : in std_logic; Rst : in std_logic; Carry_Out : out std_logic; Load_In : in std_logic_vector(0 to C_COUNT_WIDTH-1); Count_Enable : in std_logic; Count_Load : in std_logic; Count_Down : in std_logic; Cnt_by_2 : In std_logic; Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1) ); end entity pf_occ_counter; ----------------------------------------------------------------------------- -- Architecture section ----------------------------------------------------------------------------- architecture implementation of pf_occ_counter is component MUXCY is port ( DI : in std_logic; CI : in std_logic; S : in std_logic; O : out std_logic); end component MUXCY; constant CY_START : integer := 1; signal alu_cy : std_logic_vector(0 to C_COUNT_WIDTH-1); signal iCount_Out : std_logic_vector(0 to C_COUNT_WIDTH-2); signal i_mux_Count_Out : std_logic_vector(0 to C_COUNT_WIDTH-2); signal count_clock_en : std_logic; signal carry_out_lsb : std_logic; signal carry_in_lsb : std_logic; signal count_out_lsb : std_logic; Signal mux_cnt_in_lsb : std_logic; Signal carry_out_select_di: std_logic; Signal carry_start : std_logic; Signal carry_start_select : std_logic; Signal by_2_carry_start : std_logic; begin -- VHDL_RTL ----------------------------------------------------------------------------- -- Generate the Counter bits ----------------------------------------------------------------------------- count_clock_en <= Count_Enable or Count_Load; MUX_THE_LSB_INPUT : process (count_out_lsb, Load_In, Count_Load) Begin If (Count_Load = '0') Then mux_cnt_in_lsb <= count_out_lsb; else mux_cnt_in_lsb <= Load_In(C_COUNT_WIDTH-1); End if; End process MUX_THE_LSB_INPUT; carry_start <= Count_Down xor Count_Enable; by_2_carry_start <= Cnt_by_2 and Count_Down; carry_start_select <= not(Cnt_by_2); I_MUXCY_LSB_IN : MUXCY port map ( DI => by_2_carry_start, CI => carry_start, S => carry_start_select, O => carry_in_lsb); I_COUNTER_BIT_LSB : entity proc_common_v4_0.pf_counter_bit port map ( Clk => Clk, Rst => Rst, Count_In => mux_cnt_in_lsb, Load_In => '0', Count_Load => '0', Count_Down => Count_Down, Carry_In => carry_in_lsb, Clock_Enable => count_clock_en, Result => count_out_lsb, Carry_Out => carry_out_lsb); carry_out_select_di <= Count_Down xor Cnt_by_2; I_MUXCY_LSB_OUT : MUXCY port map ( DI => carry_out_select_di, CI => carry_out_lsb, S => carry_start_select, O => alu_cy(C_COUNT_WIDTH-1)); I_ADDSUB_GEN : for i in 0 to C_COUNT_WIDTH-2 generate begin MUX_THE_INPUT : process (iCount_Out, Load_In, Count_Load) Begin If (Count_Load = '0') Then i_mux_Count_Out(i) <= iCount_Out(i); else i_mux_Count_Out(i) <= Load_In(i); End if; End process MUX_THE_INPUT; Counter_Bit_I : entity proc_common_v4_0.pf_counter_bit port map ( Clk => Clk, Rst => Rst, Count_In => i_mux_Count_Out(i), Load_In => '0', Count_Load => '0', Count_Down => Count_Down, Carry_In => alu_cy(i+1), Clock_Enable => count_clock_en, Result => iCount_Out(i), Carry_Out => alu_cy(i)); end generate I_ADDSUB_GEN; Count_Out <= iCount_Out & count_out_lsb; Carry_Out <= '0'; end architecture implementation;	mit
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bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/fifo_generator_v11_0/ramfifo/rd_handshaking_flags.vhd	19	13954	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block YeJs3h9nPnCnr3aRxIBZUXmhDS7WeTgKjgxxU15evXAwgLO5UoYuCJb2fGld8H5MyDQGWc8UFp3Q QS1bcwQeLw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block QMDnsLueMbfhPqb347LcBnHgrgkl6fbZ0QORe+igLd+Fn4pMYglXhNwzAsr45PWnZnHEuCtMe3Am 9p5sJ/ms8icpsPjNhMihj0/+LhkVUeJEYGJR6AGOi4DauCIoKWFsirWy53ZScEPa2MEe+a32HUq7 sCpglfzmrbsWEab4EEg= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block F3FpAl1oCeVkGEm2PKCJ71S6Z3CGasBF9SuzLFWQnXwmvUuKd7HyekhOce1QfyX+pLQcgfmP3XmZ qpZIDWOrbZbtPCk3pZcRYdM0rjk3gWPTq89GN09GyodyzYH5nERal74RXFzqDSlXYzgzDvsSzAku WQ8fc8R6wi9d8ZzaPtv7Mn3RMOg32FvlzTpy40zwgHFS17RZjspNh23gqb62COtY3bIw5wgzOnnc pwYSu+4rxmNM105eSJdh2TJiSEN9+pTEYMITQ2PUZ0OLL5Qstj3GHFD8/78u9ynXfzh4PnzFHX+c DtImYoh20HOPJeCFpBeWPHfekXHEPhbC52n0dQ== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Lq9ua7Pc8cPhzNKkRvioUx2DGTzaswIzLnIP4rJJ3cLZM5wsk5kiUTKl9rdBpb7G3yE/zCnmkGDT ZEvIhQ4CGdpOb9ZjoYg0BIc1GhYnGIexWpvkFarqP15NwctZCibdBpj579M1D8fvQ9Xw1j6ILLQ5 gUYJd4OzxaJCHTNx0vw= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block qzr81pSyvLThhRepJmzjPLJdFa8x8hA7KFKfUSPL+CaCFf8sC6XyXYts+1DRzPvdthUp8ISKrFAv jy1EBIdnZB3D8J/YmjzA1s/E0S3V/3tyfjjyCDrQgRkpjqKN1zwlXCzBMyGSBWpl8ENwa6XmbY6s fYy2IxFIrKpit7mWPaxU1OjywKhHRwk63dw93KzE2hJmtDZhJmXSPJNkgusdN/mkZzbIYUj8bMZ1 mRTDgqzRIp9L2zyHSB7GfUn9cIiKtJb71ztIZtRMoFGfKpLMWPUiRhyoCIz55vgxKfE+F3ghCh2A ig+nnH/YWVIR6bKztafV39mEL7utiMvwk79iag== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8592) `protect data_block puDyzv0/PE73A/GBtm46F0vR/NPeoCtT0duHksnbd0Cx4Ob+Ymi7I9DZ9CaQktdUFa08Gt9ZZUvp juG7WNawmamAlHIn1x1dRRSbR4DqTWd1tEB8YLydsK4ei0h45nmJQf7jIO9TF/BPCGZJwVvImz4F 6VpQTlx2navOwMTH0So1nDmcuIu2E1NZxrIbTT4/Ly1C+r6Q5a1UfVXGtGD7OcSQf1QmwppVkdtw 1wc+vIRtGUjhN2a38+Na876F4yiJfcXY+5wKJmrtaHmEcmwsGLA86wQVwUmeKscL3tzK16I1oSWn PhDzfy5ENy96AmL+u+uf8KwfmBotYMkvEaW9Z5k2Fy+5PrsVQgbhf5hUebTCD25x8y41/9rbDkzu 2DPl8V7XlAdcffVYPx70UovkI8JFPeib44aL1PM2S/QTuhIU7/4q0yO3aDVsZEoH8Cuqu2aCn3Nb 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bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/fifo_generator_v11_0/fifo_generator_v11_0_synth.vhd	19	237901	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block bvOwtDo+u1XQuHmmirIW0G1Eep8h4q1lu6sagQVNOpqoo1dUL25zlZCKWpryXBrbavlsSVZj+/Kj u5U6Rqq3pA== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block R8VeuF45EN20zhkGmJksRGl35KTSV0YbXBmOJfN53AFOKNxf64co0R3kMl1KH48vuem/BXWPzNwW 17k9On+EP4ryAUZ6V1YvtlO9Er2xv4nZefuEO+pELxS67R6s3b0HhdPIKa2fxDF3e7AwjfjDxMiG HOQbqK01rVOmqe+2yps= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block qqYTedtVydnDu0uy4wgVS9xnI5W4e3CBu2tom9I4ji9x6Du0u8YzLw4sHBXlBjTr0CIBWi+453uv 6i+HBaHUw6WLmgP+uD0PvRoMp9iMm4rcTjCZCtUo+5bxaKDQQyKy3VozWJN9cYsOEXUyn41sbHk0 MfnFQ231FTzHKrD8+sW8iXzJhrvAxVZSOCQNc8FKSuvFHDKgrQOZi/Dde7fskgmy7Y+pQzZQUv6h 7xsxzMyVpdCwJjhjdow/xj17Fc+yTtNKSxkHMIxVK6RXkbOidb7jBkIw+8aEzlqsG5f5vpboGqLH 6uQ8IqqBeKv3BDowwIwUDotWgCgTdyFmv35LwA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block xgoCG0tChkhv+ljdCxpV0I73D5nOgliZqF/G39R6pkQNEQixpt7jSEz4sP4s78dR6d8BiB9A3KNg s8gNghB9SqKmhRG0Jvm/hSIBQCWAqWOwg26IvTnT3j3MalMVsj1r5WE9uyiqdJ+QCTo/Y58NBx8l pM5ABblrTJM59LnIcqI= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block VTcA7V7opij8+vJ+tjjgJGiOJ+o6V1u444VHa/k01STvZB7T6/Ztq4KXHSVmD+driESiC+2EQRes dfVcUifCMaPU4kNZrlpS+Cz6GGzKHuujVBDhNOZum+ncGM2VGmayYd6F9EbhwKFTOVOkQmEz/eFL 4IAryyIE59LghhLnEgKJ/yOFNS6XwipLZ1ztAAj7QDruS/h8wJcmBcjwC4vXftAO79YXKmVgRKly SlrrXAPgfawAm5V0hj7SI23oHUFrT671NQiN+jfhZylivDC/aANQXHsoSuY7NkiKvHESuXKmJ3iX cfk8aGjoqSspgWZUBuwV9vfaTHDt+AtBbt97TQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 174368) `protect data_block Coihc3vuw+nnGrqpA9jXzelo2V1TKhFG2KyqfizD5loBME2ac7oZ0SbKNvleKrm8yLH8imrB8Eyl /pQ6zcj4KO7G0U5k5xc9k5ojHU2OGkz6nBS9ljb4VH8uT3Ku3nHsI+eWYfnrJqBkKl+OCPrcUOoW HW1nm6ghSE2wneFqZPfonxLnm/ymo5gSxDzbPtotsGfIfyN+q1x+Obt3qpsae9X4k290E/4+6Vv7 dudq402e8G9MmP1cQXeimx8/jFyteVUZgwmTfuByAtNj8H0ceFdpH6IVZTcy97epOYT/hQvaTF+U X/UutKlhLBoucr7ta2k3usI0eKysUa8O7akBPlfCRJ5RKSnVOih6Id2NiahpLWBo51kWf1xgkJkG ApBcqcrZPkSZGoXjXweO3rWRkzFX+FGkfaL87tejbzi84YaCHjj8ceFSsnuohJmGOQz88RZSJFKT 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bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/proc_common_v4_0/hdl/src/vhdl/cntr_incr_decr_addn_f.vhd	15	11429	------------------------------------------------------------------------------- -- $Id: cntr_incr_decr_addn_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $ ------------------------------------------------------------------------------- -- cntr_incr_decr_addn_f - entity / architecture pair ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under -- license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid -- license agreement with Xilinx, Inc. Xilinx hereby -- grants you a license to use this text/file solely for -- design, simulation, implementation and creation of -- design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly -- prohibited and immediately terminates your license unless -- covered by a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices, with no obligation on the -- part of Xilinx to provide support. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining -- any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- Any modifications that are made to the Source Code are -- done at the users sole risk and will be unsupported. -- The Xilinx Support Hotline does not have access to source -- code and therefore cannot answer specific questions related -- to source HDL. The Xilinx Hotline support of original source -- code IP shall only address issues and questions related -- to the standard Netlist version of the core (and thus -- indirectly, the original core source). -- -- Copyright (c) 2005 - 2010 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: cntr_incr_decr_addn_f.vhd -- -- Description: This counter can increment, decrement or skip ahead -- by an arbitrary amount. -- -- If Reset is active, the value Cnt synchronously resets -- to all ones. (This reset value, different than the -- customary reset value of zero, caters to the original -- application of cntr_incr_decr_addn_f as the address -- counter for srl_fifo_rbu_f.) -- -- Otherwise, on each Clk, one is added to Cnt if Incr is -- asserted and one is subtracted if Decr is asserted. (If -- both are asserted, then there is no change to Cnt.) -- -- If Decr is not asserted, then the input value, -- Nm_to_add, is added. (Simultaneous assertion of Incr -- would add one more.) If Decr is asserted, then -- N_to_add, is ignored, i.e., it is possible to decrement -- by one or add N, but not both, and Decr overrides. -- -- The value that Cnt will take on at the next clock -- is available as Cnt_p1. -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- cntr_incr_decr_addn_f.vhd -- ------------------------------------------------------------------------------- -- -- History: -- FLO 12/30/05 First Version. -- -- ~~~~~~ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_com" -- pipelined or register delay signals: "_d#" -- predecessor value by # clks: "_p#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; -- entity cntr_incr_decr_addn_f is generic ( C_SIZE : natural; C_FAMILY : string := "nofamily" ); port ( Clk : in std_logic; Reset : in std_logic; -- Note: the counter resets to all ones! Incr : in std_logic; Decr : in std_logic; N_to_add : in std_logic_vector(C_SIZE-1 downto 0); Cnt : out std_logic_vector(C_SIZE-1 downto 0); Cnt_p1 : out std_logic_vector(C_SIZE-1 downto 0) ); end entity cntr_incr_decr_addn_f; ---( library proc_common_v4_0; library ieee; use ieee.numeric_std.UNSIGNED; use ieee.numeric_std."+"; library unisim; use unisim.all; -- Make unisim entities available for default binding. -- architecture imp of cntr_incr_decr_addn_f is use proc_common_v4_0.family_support; use family_support.all; -- primitives_type, primitive_array_type, supported constant COUNTER_PRIMS_AVAIL : boolean := supported(C_FAMILY, (u_MUXCY_L, u_XORCY, u_FDS)); signal cnt_i : std_logic_vector(Cnt'range); signal cnt_i_p1 : std_logic_vector(Cnt'range); ---------------------------------------------------------------------------- -- Unisim components declared locally for maximum avoidance of default -- binding and vcomponents version issues. ---------------------------------------------------------------------------- component MUXCY_L port ( LO : out std_ulogic; CI : in std_ulogic; DI : in std_ulogic; S : in std_ulogic ); end component; component XORCY port ( O : out std_ulogic; CI : in std_ulogic; LI : in std_ulogic ); end component; component FDS generic ( INIT : bit := '1' ); port ( Q : out std_ulogic; C : in std_ulogic; D : in std_ulogic; S : in std_ulogic ); end component; begin -- architecture imp ---( STRUCTURAL_A_GEN : if COUNTER_PRIMS_AVAIL = true generate signal hsum_A : std_logic_vector(Cnt'range); signal cry : std_logic_vector(Cnt'length downto 0); begin ---( cry(0) <= Incr; Addr_Counters : for I in cnt_i'range generate hsum_A(I) <= ((Decr or N_to_add(i)) xor cnt_i(I)); MUXCY_L_I : component MUXCY_L port map ( DI => cnt_i(I), CI => cry(I), S => hsum_A(I), LO => cry(I+1)); XORCY_I : component XORCY port map ( LI => hsum_A(I), CI => cry(I), O => cnt_i_p1(I)); FDS_I : component FDS port map ( Q => cnt_i(I), C => Clk, D => cnt_i_p1(I), S => Reset); end generate Addr_Counters; ---) end generate STRUCTURAL_A_GEN; ---) ---( INFERRED_GEN : if COUNTER_PRIMS_AVAIL = false generate -- CNT_I_P1_PROC : process( cnt_i, N_to_add, Decr, Incr ) is -- function qual_n_to_add(N_to_add : std_logic_vector; Decr : std_logic ) return UNSIGNED is variable r: UNSIGNED(N_to_add'range); begin for i in r'range loop r(i) := N_to_add(i) or Decr; end loop; return r; end; -- function to_singleton_unsigned(s : std_logic) return unsigned is variable r : unsigned(0 to 0) := (others => s); begin return r; end; -- begin cnt_i_p1 <= std_logic_vector( UNSIGNED(cnt_i) + qual_n_to_add(N_to_add, Decr) + to_singleton_unsigned(Incr) ); end process; -- CNT_I_PROC : process(Clk) is begin if Clk'event and Clk = '1' then if Reset = '1' then cnt_i <= (others => '1'); else cnt_i <= cnt_i_p1; end if; end if; end process; -- end generate INFERRED_GEN; ---) Cnt <= cnt_i; Cnt_p1 <= cnt_i_p1; end architecture imp; ---)	mit
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2ziCeftFxgi/mUBQ1zcT `protect end_protected	mit
bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_1_1/proc_common_v4_0/hdl/src/vhdl/soft_reset.vhd	15	13928	------------------------------------------------------------------------------- -- $Id: soft_reset.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $ ------------------------------------------------------------------------------- --soft_reset.vhd v1.01a ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under -- license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid -- license agreement with Xilinx, Inc. Xilinx hereby -- grants you a license to use this text/file solely for -- design, simulation, implementation and creation of -- design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly -- prohibited and immediately terminates your license unless -- covered by a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices, with no obligation on the -- part of Xilinx to provide support. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining -- any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- Any modifications that are made to the Source Code are -- done at the users sole risk and will be unsupported. -- The Xilinx Support Hotline does not have access to source -- code and therefore cannot answer specific questions related -- to source HDL. The Xilinx Hotline support of original source -- code IP shall only address issues and questions related -- to the standard Netlist version of the core (and thus -- indirectly, the original core source). -- -- Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: soft_reset.vhd -- Version: v1_00_a -- Description: This VHDL design file is the Soft Reset Service -- ------------------------------------------------------------------------------- -- Structure: -- -- soft_reset.vhd -- -- ------------------------------------------------------------------------------- -- Author: Gary Burch -- -- History: -- GAB Aug 2, 2006 v1.00a (initial release) -- -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_com" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- -- Library definitions library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; ------------------------------------------------------------------------------- entity soft_reset is generic ( C_SIPIF_DWIDTH : integer := 32; -- Width of the write data bus C_RESET_WIDTH : integer := 4 -- Width of triggered reset in Bus Clocks ); port ( -- Inputs From the IPIF Bus Bus2IP_Reset : in std_logic; Bus2IP_Clk : in std_logic; Bus2IP_WrCE : in std_logic; Bus2IP_Data : in std_logic_vector(0 to C_SIPIF_DWIDTH-1); Bus2IP_BE : in std_logic_vector(0 to (C_SIPIF_DWIDTH/8)-1); -- Final Device Reset Output Reset2IP_Reset : out std_logic; -- Status Reply Outputs to the Bus Reset2Bus_WrAck : out std_logic; Reset2Bus_Error : out std_logic; Reset2Bus_ToutSup : out std_logic ); end soft_reset ; ------------------------------------------------------------------------------- architecture implementation of soft_reset is ------------------------------------------------------------------------------- -- Function Declarations ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Type Declarations ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- -- Module Software Reset screen value for write data -- This requires a Hex 'A' to be written to ativate the S/W reset port constant RESET_MATCH : std_logic_vector(0 to 3) := "1010"; -- Required BE index to be active during Reset activation constant BE_MATCH : integer := 3; ------------------------------------------------------------------------------- -- Signal Declarations ------------------------------------------------------------------------------- signal sm_reset : std_logic; signal error_reply : std_logic; signal reset_wrack : std_logic; signal reset_error : std_logic; signal reset_trig : std_logic; signal wrack : std_logic; signal wrack_ff_chain : std_logic; signal flop_q_chain : std_logic_vector(0 to C_RESET_WIDTH); --signal bus2ip_wrce_d1 : std_logic; signal data_is_non_reset_match : std_logic; signal sw_rst_cond : std_logic; signal sw_rst_cond_d1 : std_logic; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- begin -- Misc assignments Reset2Bus_WrAck <= reset_wrack; Reset2Bus_Error <= reset_error; Reset2Bus_ToutSup <= sm_reset; -- Suppress a data phase timeout when -- a commanded reset is active. reset_wrack <= (reset_error or wrack);-- and Bus2IP_WrCE; reset_error <= data_is_non_reset_match and Bus2IP_WrCE; Reset2IP_Reset <= Bus2IP_Reset or sm_reset; --------------------------------------------------------------------------------- ---- Register WRCE for use in creating a strobe pulse --------------------------------------------------------------------------------- --REG_WRCE : process(Bus2IP_Clk) -- begin -- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then -- if(Bus2IP_Reset = '1')then -- bus2ip_wrce_d1 <= '0'; -- else -- bus2ip_wrce_d1 <= Bus2IP_WrCE; -- end if; -- end if; -- end process REG_WRCE; -- ------------------------------------------------------------------------------- -- Start the S/W reset state machine as a result of an IPIF Bus write to -- the Reset port and the data on the DBus inputs matching the Reset -- match value. If the value on the data bus input does not match the -- designated reset key, an error acknowledge is generated. ------------------------------------------------------------------------------- --DETECT_SW_RESET : process (Bus2IP_Clk) -- begin -- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then -- if (Bus2IP_Reset = '1') then -- error_reply <= '0'; -- reset_trig <= '0'; -- elsif (Bus2IP_WrCE = '1' -- and Bus2IP_BE(BE_MATCH) = '1' -- and Bus2IP_Data(28 to 31) = RESET_MATCH) then -- error_reply <= '0'; -- reset_trig <= Bus2IP_WrCE and not bus2ip_wrce_d1; -- elsif (Bus2IP_WrCE = '1') then -- error_reply <= '1'; -- reset_trig <= '0'; -- else -- error_reply <= '0'; -- reset_trig <= '0'; -- end if; -- end if; -- end process DETECT_SW_RESET; data_is_non_reset_match <= '0' when (Bus2IP_Data(C_SIPIF_DWIDTH-4 to C_SIPIF_DWIDTH-1) = RESET_MATCH and Bus2IP_BE(BE_MATCH) = '1') else '1'; -------------------------------------------------------------------------------- -- SW Reset -------------------------------------------------------------------------------- ---------------------------------------------------------------------------- sw_rst_cond <= Bus2IP_WrCE and not data_is_non_reset_match; -- RST_PULSE_PROC : process (Bus2IP_Clk) Begin if (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then if (Bus2IP_Reset = '1') Then sw_rst_cond_d1 <= '0'; reset_trig <= '0'; else sw_rst_cond_d1 <= sw_rst_cond; reset_trig <= sw_rst_cond and not sw_rst_cond_d1; end if; end if; End process; ------------------------------------------------------------------------------- -- RESET_FLOPS: -- This FORGEN implements the register chain used to create -- the parameterizable reset pulse width. ------------------------------------------------------------------------------- RESET_FLOPS : for index in 0 to C_RESET_WIDTH-1 generate flop_q_chain(0) <= '0'; RST_FLOPS : FDRSE port map( Q => flop_q_chain(index+1), -- : out std_logic; C => Bus2IP_Clk, -- : in std_logic; CE => '1', -- : in std_logic; D => flop_q_chain(index), -- : in std_logic; R => Bus2IP_Reset, -- : in std_logic; S => reset_trig -- : in std_logic ); end generate RESET_FLOPS; -- Use the last flop output for the commanded reset pulse sm_reset <= flop_q_chain(C_RESET_WIDTH); wrack_ff_chain <= flop_q_chain(C_RESET_WIDTH) and not(flop_q_chain(C_RESET_WIDTH-1)); -- Register the Write Acknowledge for the Reset write -- This is generated at the end of the reset pulse. This -- keeps the Slave busy until the commanded reset completes. FF_WRACK : FDRSE port map( Q => wrack, -- : out std_logic; C => Bus2IP_Clk, -- : in std_logic; CE => '1', -- : in std_logic; D => wrack_ff_chain, -- : in std_logic; R => Bus2IP_Reset, -- : in std_logic; S => '0' -- : in std_logic ); end implementation;	mit
bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/proc_common_v4_0/hdl/src/vhdl/proc_common_pkg.vhd	15	18735	------------------------------------------------------------------------------- -- $Id: proc_common_pkg.vhd,v 1.1.4.46 2010/10/28 01:14:32 ostlerf Exp $ ------------------------------------------------------------------------------- -- Processor Common Library Package ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under -- license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid -- license agreement with Xilinx, Inc. Xilinx hereby -- grants you a license to use this text/file solely for -- design, simulation, implementation and creation of -- design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly -- prohibited and immediately terminates your license unless -- covered by a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices, with no obligation on the -- part of Xilinx to provide support. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining -- any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- Any modifications that are made to the Source Code are -- done at the users sole risk and will be unsupported. -- The Xilinx Support Hotline does not have access to source -- code and therefore cannot answer specific questions related -- to source HDL. The Xilinx Hotline support of original source -- code IP shall only address issues and questions related -- to the standard Netlist version of the core (and thus -- indirectly, the original core source). -- -- Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: proc_common_pkg.vhd -- Version: v1.21b -- Description: This file contains the constants and functions used in the -- processor common library components. -- ------------------------------------------------------------------------------- -- Structure: -- ------------------------------------------------------------------------------- -- Author: ALS -- History: -- ALS 09/12/01 -- Created from opb_arb_pkg.vhd -- -- ALS 09/21/01 -- ^^^^^^ -- Added pwr function. Replaced log2 function with one that works for XST. -- ~~~~~~ -- -- ALS 12/07/01 -- ^^^^^^ -- Added Addr_bits function. -- ~~~~~~ -- ALS 01/31/02 -- ^^^^^^ -- Added max2 function. -- ~~~~~~ -- FLO 02/22/02 -- ^^^^^^ -- Extended input argument range of log2 function to 2^30. Also, added -- a check that the argument does not exceed this value; a failure -- assertion violation is generated if it does not. -- ~~~~~~ -- FLO 08/31/06 -- ^^^^^^ -- Removed type TARGET_FAMILY_TYPE and functions Get_Reg_File_Area and -- Get_RLOC_Name. These objects are not used. Further, the functions -- produced misleading warnings (CR419886, CR419898). -- ~~~~~~ -- FLO 05/25/07 -- ^^^^^^ -- -Reimplemented function pad_power2 to correct error when the input -- argument is 1. (fixes CR 303469) -- -Added function clog2(x), which returns the integer ceiling of the -- base 2 logarithm of x. This function can be used in place of log2 -- when wishing to avoid the XST warning, "VHDL Assertion Statement -- with non constant condition is ignored". -- ~~~~~~ -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Incorporated new disclaimer header -- ^^^^^^ -- -- DET 5/8/2009 v4_0 for EDK L.SP2 -- ~~~~~~ -- - Per CR520627 -- - Added synthesis translate_off/on constructs to the log2 function -- around the assertion statement. This removes a repetative XST Warning -- in SRP files about a non-constant assertion check. -- ^^^^^^ -- FL0 20/27/2010 -- ^^^^^^ -- Removed 42 TBD comment, again. (CR 568493) -- ~~~~~~ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_com" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; -- need conversion function to convert reals/integers to std logic vectors use ieee.std_logic_arith.conv_std_logic_vector; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; package proc_common_pkg is ------------------------------------------------------------------------------- -- Type Declarations ------------------------------------------------------------------------------- type CHAR_TO_INT_TYPE is array (character) of integer; -- type INTEGER_ARRAY_TYPE is array (natural range <>) of integer; -- Type SLV64_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 63); ------------------------------------------------------------------------------- -- Function and Procedure Declarations ------------------------------------------------------------------------------- function max2 (num1, num2 : integer) return integer; function min2 (num1, num2 : integer) return integer; function Addr_Bits(x,y : std_logic_vector) return integer; function clog2(x : positive) return natural; function pad_power2 ( in_num : integer ) return integer; function pad_4 ( in_num : integer ) return integer; function log2(x : natural) return integer; function pwr(x: integer; y: integer) return integer; function String_To_Int(S : string) return integer; function itoa (int : integer) return string; ------------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- -- the RESET_ACTIVE constant should denote the logic level of an active reset constant RESET_ACTIVE : std_logic := '1'; -- table containing strings representing hex characters for conversion to -- integers constant STRHEX_TO_INT_TABLE : CHAR_TO_INT_TYPE := ('0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4, '5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9, 'A'\|'a' => 10, 'B'\|'b' => 11, 'C'\|'c' => 12, 'D'\|'d' => 13, 'E'\|'e' => 14, 'F'\|'f' => 15, others => -1); end proc_common_pkg; package body proc_common_pkg is ------------------------------------------------------------------------------- -- Function Definitions ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Function max2 -- -- This function returns the greater of two numbers. ------------------------------------------------------------------------------- function max2 (num1, num2 : integer) return integer is begin if num1 >= num2 then return num1; else return num2; end if; end function max2; ------------------------------------------------------------------------------- -- Function min2 -- -- This function returns the lesser of two numbers. ------------------------------------------------------------------------------- function min2 (num1, num2 : integer) return integer is begin if num1 <= num2 then return num1; else return num2; end if; end function min2; ------------------------------------------------------------------------------- -- Function Addr_bits -- -- function to convert an address range (base address and an upper address) -- into the number of upper address bits needed for decoding a device -- select signal. will handle slices and big or little endian ------------------------------------------------------------------------------- function Addr_Bits(x,y : std_logic_vector) return integer is variable addr_xor : std_logic_vector(x'range); variable count : integer := 0; begin assert x'length = y'length and (x'ascending xnor y'ascending) report "Addr_Bits: arguments are not the same type" severity ERROR; addr_xor := x xor y; for i in x'range loop if addr_xor(i) = '1' then return count; end if; count := count + 1; end loop; return x'length; end Addr_Bits; -------------------------------------------------------------------------------- -- Function clog2 - returns the integer ceiling of the base 2 logarithm of x, -- i.e., the least integer greater than or equal to log2(x). -------------------------------------------------------------------------------- function clog2(x : positive) return natural is variable r : natural := 0; variable rp : natural := 1; -- rp tracks the value 2r begin while rp < x loop -- Termination condition T: x <= 2r -- Loop invariant L: 2(r-1) < x r := r + 1; if rp > integer'high - rp then exit; end if; -- If doubling rp overflows -- the integer range, the doubled value would exceed x, so safe to exit. rp := rp + rp; end loop; -- L and T <-> 2(r-1) < x <= 2r <-> (r-1) < log2(x) <= r return r; -- end clog2; ------------------------------------------------------------------------------- -- Function pad_power2 -- -- This function returns the next power of 2 from the input number. If the -- input number is a power of 2, this function returns the input number. -- -- This function is used to round up the number of masters to the next power -- of 2 if the number of masters is not already a power of 2. -- -- Input argument 0, which is not a power of two, is accepted and returns 0. -- Input arguments less than 0 are not allowed. ------------------------------------------------------------------------------- -- function pad_power2 (in_num : integer ) return integer is begin if in_num = 0 then return 0; else return 2(clog2(in_num)); end if; end pad_power2; ------------------------------------------------------------------------------- -- Function pad_4 -- -- This function returns the next multiple of 4 from the input number. If the -- input number is a multiple of 4, this function returns the input number. -- ------------------------------------------------------------------------------- -- function pad_4 (in_num : integer ) return integer is variable out_num : integer; begin out_num := (((in_num-1)/4) + 1)4; return out_num; end pad_4; ------------------------------------------------------------------------------- -- Function log2 -- returns number of bits needed to encode x choices -- x = 0 returns 0 -- x = 1 returns 0 -- x = 2 returns 1 -- x = 4 returns 2, etc. ------------------------------------------------------------------------------- -- function log2(x : natural) return integer is variable i : integer := 0; variable val: integer := 1; begin if x = 0 then return 0; else for j in 0 to 29 loop -- for loop for XST if val >= x then null; else i := i+1; val := val2; end if; end loop; -- Fix per CR520627 XST was ignoring this anyway and printing a -- Warning in SRP file. This will get rid of the warning and not -- impact simulation. -- synthesis translate_off assert val >= x report "Function log2 received argument larger" & " than its capability of 2^30. " severity failure; -- synthesis translate_on return i; end if; end function log2; ------------------------------------------------------------------------------- -- Function pwr -- xy -- negative numbers not allowed for y ------------------------------------------------------------------------------- function pwr(x: integer; y: integer) return integer is variable z : integer := 1; begin if y = 0 then return 1; else for i in 1 to y loop z := z x; end loop; return z; end if; end function pwr; ------------------------------------------------------------------------------- -- Function itoa -- -- The itoa function converts an integer to a text string. -- This function is required since `image doesn't work in Synplicity -- Valid input range is -9999 to 9999 ------------------------------------------------------------------------------- -- function itoa (int : integer) return string is type table is array (0 to 9) of string (1 to 1); constant LUT : table := ("0", "1", "2", "3", "4", "5", "6", "7", "8", "9"); variable str1 : string(1 to 1); variable str2 : string(1 to 2); variable str3 : string(1 to 3); variable str4 : string(1 to 4); variable str5 : string(1 to 5); variable abs_int : natural; variable thousands_place : natural; variable hundreds_place : natural; variable tens_place : natural; variable ones_place : natural; variable sign : integer; begin abs_int := abs(int); if abs_int > int then sign := -1; else sign := 1; end if; thousands_place := abs_int/1000; hundreds_place := (abs_int-thousands_place1000)/100; tens_place := (abs_int-thousands_place1000-hundreds_place100)/10; ones_place := (abs_int-thousands_place1000-hundreds_place100-tens_place10); if sign>0 then if thousands_place>0 then str4 := LUT(thousands_place) & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place); return str4; elsif hundreds_place>0 then str3 := LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place); return str3; elsif tens_place>0 then str2 := LUT(tens_place) & LUT(ones_place); return str2; else str1 := LUT(ones_place); return str1; end if; else if thousands_place>0 then str5 := "-" & LUT(thousands_place) & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place); return str5; elsif hundreds_place>0 then str4 := "-" & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place); return str4; elsif tens_place>0 then str3 := "-" & LUT(tens_place) & LUT(ones_place); return str3; else str2 := "-" & LUT(ones_place); return str2; end if; end if; end itoa; ----------------------------------------------------------------------------- -- Function String_To_Int -- -- Converts a string of hex character to an integer -- accept negative numbers ----------------------------------------------------------------------------- function String_To_Int(S : String) return Integer is variable Result : integer := 0; variable Temp : integer := S'Left; variable Negative : integer := 1; begin for I in S'Left to S'Right loop if (S(I) = '-') then Temp := 0; Negative := -1; else Temp := STRHEX_TO_INT_TABLE(S(I)); if (Temp = -1) then assert false report "Wrong value in String_To_Int conversion " & S(I) severity error; end if; end if; Result := Result * 16 + Temp; end loop; return (Negative * Result); end String_To_Int; end package body proc_common_pkg;	mit
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bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_1_1/proc_common_v4_0/hdl/src/vhdl/ld_arith_reg.vhd	15	15091	------------------------------------------------------------------------------- -- $Id: ld_arith_reg.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $ ------------------------------------------------------------------------------- -- Loadable arithmetic register. ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under -- license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid -- license agreement with Xilinx, Inc. Xilinx hereby -- grants you a license to use this text/file solely for -- design, simulation, implementation and creation of -- design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly -- prohibited and immediately terminates your license unless -- covered by a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices, with no obligation on the -- part of Xilinx to provide support. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining -- any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- Any modifications that are made to the Source Code are -- done at the users sole risk and will be unsupported. -- The Xilinx Support Hotline does not have access to source -- code and therefore cannot answer specific questions related -- to source HDL. The Xilinx Hotline support of original source -- code IP shall only address issues and questions related -- to the standard Netlist version of the core (and thus -- indirectly, the original core source). -- -- Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: ld_arith_reg.vhd -- Version: -------------------------------------------------------------------------------- -- Description: A register that can be loaded and added to or subtracted from -- (but not both). The width of the register is specified -- with a generic. The load value and the arith -- value, i.e. the value to be added (subtracted), may be of -- lesser width than the register and may be -- offset from the LSB position. (Uncovered positions -- load or add (subtract) zero.) The register can be -- reset, via the RST signal, to a freely selectable value. -- The register is defined in terms of big-endian bit ordering. -- ------------------------------------------------------------------------------- -- Structure: -- -- ld_arith_reg.vhd ------------------------------------------------------------------------------- -- Author: FO -- -- History: -- -- FO 08/01 -- First version -- -- FO 11/14/01 -- Cosmetic improvements -- -- FO 02/22/02 -- Switched from MUXCY_L primitive to MUXCY. -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_com" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity ld_arith_reg is generic ( ------------------------------------------------------------------------ -- True if the arithmetic operation is add, false if subtract. C_ADD_SUB_NOT : boolean := false; ------------------------------------------------------------------------ -- Width of the register. C_REG_WIDTH : natural := 8; ------------------------------------------------------------------------ -- Reset value. (No default, must be specified in the instantiation.) C_RESET_VALUE : std_logic_vector; ------------------------------------------------------------------------ -- Width of the load data. C_LD_WIDTH : natural := 8; ------------------------------------------------------------------------ -- Offset from the LSB (toward more significant) of the load data. C_LD_OFFSET : natural := 0; ------------------------------------------------------------------------ -- Width of the arithmetic data. C_AD_WIDTH : natural := 8; ------------------------------------------------------------------------ -- Offset from the LSB of the arithmetic data. C_AD_OFFSET : natural := 0 ------------------------------------------------------------------------ -- Dependencies: (1) C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH -- (2) C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH ------------------------------------------------------------------------ ); port ( CK : in std_logic; RST : in std_logic; -- Reset to C_RESET_VALUE. (Overrides OP,LOAD) Q : out std_logic_vector(0 to C_REG_WIDTH-1); LD : in std_logic_vector(0 to C_LD_WIDTH-1); -- Load data. AD : in std_logic_vector(0 to C_AD_WIDTH-1); -- Arith data. LOAD : in std_logic; -- Enable for the load op, Q <= LD. OP : in std_logic -- Enable for the arith op, Q <= Q + AD. -- (Q <= Q - AD if C_ADD_SUB_NOT = false.) -- (Overrrides LOAD.) ); end ld_arith_reg; library unisim; use unisim.all; library ieee; use ieee.numeric_std.all; architecture imp of ld_arith_reg is component MULT_AND port( LO : out std_ulogic; I1 : in std_ulogic; I0 : in std_ulogic); end component; component MUXCY is port ( DI : in std_logic; CI : in std_logic; S : in std_logic; O : out std_logic); end component MUXCY; component XORCY is port ( LI : in std_logic; CI : in std_logic; O : out std_logic); end component XORCY; component FDRE is port ( Q : out std_logic; C : in std_logic; CE : in std_logic; D : in std_logic; R : in std_logic ); end component FDRE; component FDSE is port ( Q : out std_logic; C : in std_logic; CE : in std_logic; D : in std_logic; S : in std_logic ); end component FDSE; signal q_i, q_i_ns, xorcy_out, gen_cry_kill_n : std_logic_vector(0 to C_REG_WIDTH-1); signal cry : std_logic_vector(0 to C_REG_WIDTH); begin -- synthesis translate_off assert C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH report "ld_arith_reg, constraint does not hold: " & "C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH" severity error; assert C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH report "ld_arith_reg, constraint does not hold: " & "C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH" severity error; -- synthesis translate_on Q <= q_i; cry(C_REG_WIDTH) <= '0' when C_ADD_SUB_NOT else OP; PERBIT_GEN: for j in C_REG_WIDTH-1 downto 0 generate signal load_bit, arith_bit, CE : std_logic; begin ------------------------------------------------------------------------ -- Assign to load_bit either zero or the bit from input port LD. ------------------------------------------------------------------------ D_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_LD_OFFSET or j < C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET generate load_bit <= '0'; end generate; D_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_LD_OFFSET and j >= C_REG_WIDTH - C_LD_OFFSET - C_LD_WIDTH generate load_bit <= LD(j - (C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET)); end generate; ------------------------------------------------------------------------ -- Assign to arith_bit either zero or the bit from input port AD. ------------------------------------------------------------------------ AD_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_AD_OFFSET or j < C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET generate arith_bit <= '0'; end generate; AD_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_AD_OFFSET and j >= C_REG_WIDTH - C_AD_OFFSET - C_AD_WIDTH generate arith_bit <= AD(j - (C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET)); end generate; ------------------------------------------------------------------------ -- LUT output generation. -- Adder case ------------------------------------------------------------------------ Q_I_GEN_ADD: if C_ADD_SUB_NOT generate q_i_ns(j) <= q_i(j) xor arith_bit when OP = '1' else load_bit; end generate; ------------------------------------------------------------------------ -- Subtractor case ------------------------------------------------------------------------ Q_I_GEN_SUB: if not C_ADD_SUB_NOT generate q_i_ns(j) <= q_i(j) xnor arith_bit when OP = '1' else load_bit; end generate; ------------------------------------------------------------------------ -- Kill carries (borrows) for loads but -- generate or kill carries (borrows) for add (sub). ------------------------------------------------------------------------ MULT_AND_i1: MULT_AND port map ( LO => gen_cry_kill_n(j), I1 => OP, I0 => Q_i(j) ); ------------------------------------------------------------------------ -- Propagate the carry (borrow) out. ------------------------------------------------------------------------ MUXCY_i1: MUXCY port map ( DI => gen_cry_kill_n(j), CI => cry(j+1), S => q_i_ns(j), O => cry(j) ); ------------------------------------------------------------------------ -- Apply the effect of carry (borrow) in. ------------------------------------------------------------------------ XORCY_i1: XORCY port map ( LI => q_i_ns(j), CI => cry(j+1), O => xorcy_out(j) ); CE <= LOAD or OP; ------------------------------------------------------------------------ -- Generate either a resettable or setable FF for bit j, depending -- on C_RESET_VALUE at bit j. ------------------------------------------------------------------------ FF_RST0_GEN: if C_RESET_VALUE(j) = '0' generate FDRE_i1: FDRE port map ( Q => q_i(j), C => CK, CE => CE, D => xorcy_out(j), R => RST ); end generate; FF_RST1_GEN: if C_RESET_VALUE(j) = '1' generate FDSE_i1: FDSE port map ( Q => q_i(j), C => CK, CE => CE, D => xorcy_out(j), S => RST ); end generate; end generate; end imp;	mit
bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd	15	12529	------------------------------------------------------------------------------- -- $Id: pselect_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $ ------------------------------------------------------------------------------- -- pselect_f.vhd - entity/architecture pair ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under -- license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid -- license agreement with Xilinx, Inc. Xilinx hereby -- grants you a license to use this text/file solely for -- design, simulation, implementation and creation of -- design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly -- prohibited and immediately terminates your license unless -- covered by a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices, with no obligation on the -- part of Xilinx to provide support. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining -- any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- Any modifications that are made to the Source Code are -- done at the users sole risk and will be unsupported. -- The Xilinx Support Hotline does not have access to source -- code and therefore cannot answer specific questions related -- to source HDL. The Xilinx Hotline support of original source -- code IP shall only address issues and questions related -- to the standard Netlist version of the core (and thus -- indirectly, the original core source). -- -- Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: pselect_f.vhd -- -- Description: -- (Note: At least as early as I.31, XST implements a carry- -- chain structure for most decoders when these are coded in -- inferrable VHLD. An example of such code can be seen -- below in the "INFERRED_GEN" Generate Statement. -- -- -> New code should not need to instantiate pselect-type -- components. -- -- -> Existing code can be ported to Virtex5 and later by -- replacing pselect instances by pselect_f instances. -- As long as the C_FAMILY parameter is not included -- in the Generic Map, an inferred implementation -- will result. -- -- -> If the designer wishes to force an explicit carry- -- chain implementation, pselect_f can be used with -- the C_FAMILY parameter set to the target -- Xilinx FPGA family. -- ) -- -- Parameterizeable peripheral select (address decode). -- AValid qualifier comes in on Carry In at bottom -- of carry chain. -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: pselect_f.vhd -- family_support.vhd -- ------------------------------------------------------------------------------- -- History: -- Vaibhav & FLO 05/26/06 First Version -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Changed proc_common library version to v4_0 -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_com" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; library unisim; use unisim.all; library proc_common_v4_0; use proc_common_v4_0.family_support.all; ----------------------------------------------------------------------------- -- Entity section ----------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Definition of Generics: -- C_AB -- number of address bits to decode -- C_AW -- width of address bus -- C_BAR -- base address of peripheral (peripheral select -- is asserted when the C_AB most significant -- address bits match the C_AB most significant -- C_BAR bits -- Definition of Ports: -- A -- address input -- AValid -- address qualifier -- CS -- peripheral select ------------------------------------------------------------------------------- entity pselect_f is generic ( C_AB : integer := 9; C_AW : integer := 32; C_BAR : std_logic_vector; C_FAMILY : string := "nofamily" ); port ( A : in std_logic_vector(0 to C_AW-1); AValid : in std_logic; CS : out std_logic ); end entity pselect_f; ----------------------------------------------------------------------------- -- Architecture section ----------------------------------------------------------------------------- architecture imp of pselect_f is component MUXCY is port ( O : out std_logic; CI : in std_logic; DI : in std_logic; S : in std_logic ); end component MUXCY; constant NLS : natural := native_lut_size(C_FAMILY); constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY) or NLS=0 -- LUT not supported. or C_AB <= NLS; -- Just one LUT -- needed. ----------------------------------------------------------------------------- -- C_BAR may not be indexed from 0 and may not be ascending; -- BAR recasts C_BAR to have these properties. ----------------------------------------------------------------------------- constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR; type bo2sl_type is array (boolean) of std_logic; constant bo2sl : bo2sl_type := (false => '0', true => '1'); function min(i, j: integer) return integer is begin if i<j then return i; else return j; end if; end; begin ------------------------------------------------------------------------------ -- Check that the generics are valid. ------------------------------------------------------------------------------ -- synthesis translate_off assert (C_AB <= C_BAR'length) and (C_AB <= C_AW) report "pselect_f generic error: " & "(C_AB <= C_BAR'length) and (C_AB <= C_AW)" & " does not hold." severity failure; -- synthesis translate_on ------------------------------------------------------------------------------ -- Build a behavioral decoder ------------------------------------------------------------------------------ INFERRED_GEN : if (USE_INFERRED = TRUE ) generate begin XST_WA:if C_AB > 0 generate CS <= AValid when A(0 to C_AB-1) = BAR (0 to C_AB-1) else '0' ; end generate XST_WA; PASS_ON_GEN:if C_AB = 0 generate CS <= AValid ; end generate PASS_ON_GEN; end generate INFERRED_GEN; ------------------------------------------------------------------------------ -- Build a structural decoder using the fast carry chain ------------------------------------------------------------------------------ GEN_STRUCTURAL_A : if (USE_INFERRED = FALSE ) generate constant NUM_LUTS : integer := (C_AB+(NLS-1))/NLS; signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround signal carry_chain : std_logic_vector(0 to NUM_LUTS); begin carry_chain(NUM_LUTS) <= AValid; -- Initialize start of carry chain. CS <= carry_chain(0); -- Assign end of carry chain to output. XST_WA: if NUM_LUTS > 0 generate -- workaround for XST begin GEN_DECODE: for i in 0 to NUM_LUTS-1 generate constant NI : natural := i; constant BTL : positive := min(NLS, C_AB-NINLS);-- num Bits This LUT begin lut_out(i) <= bo2sl(A(NINLS to NINLS+BTL-1) = -- LUT BAR(NINLS to NINLS+BTL-1)); MUXCY_I: component MUXCY -- MUXCY port map ( O => carry_chain(i), CI => carry_chain(i+1), DI => '0', S => lut_out(i) ); end generate GEN_DECODE; end generate XST_WA; end generate GEN_STRUCTURAL_A; end imp;	mit
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bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/proc_common_v4_0/hdl/src/vhdl/down_counter.vhd	15	8398	------------------------------------------------------------------------------- -- $Id: down_counter.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $ ------------------------------------------------------------------------------ -- PLB Arbiter ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under -- license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid -- license agreement with Xilinx, Inc. Xilinx hereby -- grants you a license to use this text/file solely for -- design, simulation, implementation and creation of -- design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly -- prohibited and immediately terminates your license unless -- covered by a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices, with no obligation on the -- part of Xilinx to provide support. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining -- any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- Any modifications that are made to the Source Code are -- done at the users sole risk and will be unsupported. -- The Xilinx Support Hotline does not have access to source -- code and therefore cannot answer specific questions related -- to source HDL. The Xilinx Hotline support of original source -- code IP shall only address issues and questions related -- to the standard Netlist version of the core (and thus -- indirectly, the original core source). -- -- Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- -- *********************************************************************** -- ------------------------------------------------------------------------------ -- Filename: down_counter.vhd -- -- Description: Parameterizable down counter with synchronous load and -- reset. -- ------------------------------------------------------------------------------- -- Structure: -- Multi-use module ------------------------------------------------------------------------------- -- Author: ALS -- History: -- ALS 04/10/01 -- First version -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Changed proc_common library version to v4_0 -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_cmb" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.STD_LOGIC_1164.all; use ieee.STD_LOGIC_ARITH.all; -- PROC_COMMON_PKG contains the RESET_ACTIVE constant library proc_common_v4_0; use proc_common_v4_0.proc_common_pkg.all; ------------------------------------------------------------------------------- -- Port Declaration ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Definition of Generics: -- C_CNT_WIDTH -- counter width -- -- Definition of Ports: -- input Din -- data to be loaded into counter -- input Load -- load control signal -- input Cnt_en -- count enable signal -- input Clk -- input Rst -- -- output Cnt_out -- counter output ------------------------------------------------------------------------------- entity down_counter is generic ( -- Select width of counter C_CNT_WIDTH : INTEGER := 4 ); port ( Din : in std_logic_vector(0 to C_CNT_WIDTH-1); Load : in std_logic; Cnt_en : in std_logic; Cnt_out : out std_logic_vector(0 to C_CNT_WIDTH - 1 ); Clk : in std_logic; Rst : in std_logic ); end down_counter; architecture simulation of down_counter is ------------------------------------------------------------------------------- -- Signal Declarations ------------------------------------------------------------------------------- -- internal count signal cnt : unsigned(0 to C_CNT_WIDTH - 1 ); begin ------------------------------------------------------------------------------- -- COUNTER_PROCESS process ------------------------------------------------------------------------------- COUNTER_PROCESS:process (Clk) begin if Clk'event and Clk = '1' then if Rst = RESET_ACTIVE then cnt <= (others => '0'); elsif Load = '1' then cnt <= unsigned(Din); elsif Cnt_en = '1' then cnt <= cnt - 1; else cnt <= cnt; end if; end if; end process COUNTER_PROCESS; CNTOUT_PROCESS:process (cnt) begin Cnt_out <= conv_std_logic_vector(cnt, C_CNT_WIDTH); end process CNTOUT_PROCESS; end simulation;	mit
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bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_xbar_1/fifo_generator_v11_0/builtin/fifo_generator_v11_0_comps_builtin.vhd	19	32006	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block bdlZLEAewQqpv1o7OoBr4R377V8Hk5Fd8+q/Az6G9nxroFaOnD3V9+lWQZaiTQ+UR8tYlBixiDT3 2rrbvlUYqg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block PNj5XhRRPylbuLUnq16m36512+Iu+tuxUNOB5vui/U9Vyxliy5LDYUjGyTrkosJ5RLmSfgYfmdaq x3GXyG6MVOiZo15XiDmGz5Xa3WMM3TuUhfpzNItvR+cjVJcfSX1Vpo9/m4Gf2HbgWDY8/uge9Yz+ pdDWTg9IqOS1f9m0bhc= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block tfy6e9ewB1av8IAVBQg5F0wJVpezM47U5T38niEmKqoHE2EAQIsVtLXdGuC0EVCv8iR27vcg17Oa mBfBXWB60tzPu8Q6DSJi1RmV8OgW+NgUvCiTMpLKqqsw6FnhMEK3lQVXfOtnfyh9msybPw9byzXC dambJMmCpKtH2TBazWP4yb5ww1Nsz/1jL5i1zPiiJqwiUek+yJBHinlLsKOdmxiEOjEIxiuXMNyg LMJzb839xkVhlMYTWXZYlSQVwwm/sLGnZ2Znntlf9sYBoE6D2vYri/PUGcfI5TqvvhrwG3MMHoTN rPYZvU5TTqkZ0UHzprP9ZbAAvBMMlhHGjyKLgw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block enscaK3Um9KpWwQm1hA2XwO16XJLOAeYZ3URNnasJSAORmdXiuv1QgNvxstTqRmJdf6aiVcX+SBW QAS4XOQmaHblVVCTrTFxq+i8/M/uWIiPlKdwfgcbq6W9GDVZEH2g71B4sNE7sbY88daOW+dsFMn8 evKdCCrOhrfApxD2w7E= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/fifo_generator_v11_0/builtin/builtin_extdepth_low_latency.vhd	19	43742	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block L9EbKuxxzV/09pnAb0OGW9DxPQ+o+m/MvX4x5f3JCiR63+KWt2eYB17k+9mGgVY+K1VLxoYz0z6V YvlDefublw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block gJD53XIM6IXGcoGao7b+pChhlJwhGxOuVwSTI1iU+aaEVIG37JelabzUSiGlwgboK2Zv8N9/EzBK Y9pDSGcMvhlTABOa75VEGmta9QvVzRVMjXtd0b/jrdUkZar600zvkPbB8+QESNshxT7B96klkdIo XvMdlDR/SEQxmh4Mkpk= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block uMh613zg14bfl9MaiMXKdALr5q+gvlBiCCfJpnudkmj/VEzNaqE3gABSgWbIJEk6l3XEblsHwoSZ 2eueijgOoGBjZq9eDXqLeir52M0Z4RoybrJFqX7YgYE+2quggoW8XJjUPK7bExWH1Wd6un6XRwZo +XQ53VUhkTgctFKNHRr7bEqxJa0qk8dm+fTRKVmCc1Tr5X6rd28yRrr4koH3+liBwEPKquwcMKJL zK5B0g+bSiHJvGXlQQpKzQNF3+4MebcveUUQPOYG2FAjfRJs1t60dgE73q6y3I1DMI/3MguCuvoX 78TA3nOFRYGLkISVFXDX28xYA0EnciH3BlzGiA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 2ADp5V47yVkwRII2+UsRY3zvclviExupZdil2h787eVOjYg5odQlZCOMnldkarIbxDBoj52vjMGc rG04pAKa/Z3oDUnDkDe8ZMmBI29kynugqgc8aGxYPVKp3KD8EvhnicB6/4Tt66g9A8WsjHtxXLuC 0ImlGHU3T8u48JygeUs= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block s5k0DDcwk1Yhkk6mc4rW2ITc+jBCojX0QPFrzARjmvIjcmc9EJT8pAYSdJK1ykoSIGmT8u4U6vaF 5pchZ1NWV4+0T78Lu7ir0M6lHPYDFRgXZTR6CNdPGqAe+Si56W7NnXEM0Yylf/w4tAQ0u+05yvCg wK+mPCq/91Em5ZiPcvKOHOdJBSTTkSYC7/n0QNniR1mBmd7+dgsFr5yshClYY/q8HngDDE/aNYfx P9AT4ECjL+OzARXCnbTA6RjbHEjVx1ewIc83WIXkwbZjUYAzp9rYNjFdx68zjq8U1XW92RXAEXCc AYKv676uVGq/WAryucxGApaihL/izu2+HGUsYA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 30640) `protect data_block TGoYSUtq9QXorwtXYAiku5PRRrofa1QO0tKP2kJaj3QuzD8XFFlvgmBxexyLYDE6gDfD3y1MimNL y+GFR4k8uGqsTU4X/c+yG7qWrgec1Z/r4nV+jBcL0IflUtTCMpq+DQitly34B3lyEm+/ewhdWbag sQU92u1xDPqyW4Fay+CZNGjpJEW6bQ6IDAJc7vACSdWHqRQ6Wrr7OvEkDQEjVx6I5FstZJSKRDyM kkrVQ7wugbCgqedvuZCna1k8+ZH7dyRcyOIbqwtOUx3+ole5A/bpTq1405Z8HHOPnnLBzuvKN/i2 h3Ik0stJQYc41NspCzWtUqxX9Bi28wMdEtl98p6niJJJspPsNRs/+hdLPK8mB93Edi4KWJ/uhRqS yxZFf7LkvVi+N1jLa10d3keQqXfEUiWSaCDXPOWY79DklbnODKMFO7yWaBJejaztQDzeKsm65LPQ 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bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/proc_common_v4_0/hdl/src/vhdl/or_gate.vhd	15	9199	------------------------------------------------------------------------------- -- $Id: or_gate.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $ ------------------------------------------------------------------------------- -- or_gate.vhd - entity/architecture pair ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- DISCLAIMER OF LIABILITY -- -- This text/file contains proprietary, confidential -- information of Xilinx, Inc., is distributed under -- license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid -- license agreement with Xilinx, Inc. Xilinx hereby -- grants you a license to use this text/file solely for -- design, simulation, implementation and creation of -- design files limited to Xilinx devices or technologies. -- Use with non-Xilinx devices or technologies is expressly -- prohibited and immediately terminates your license unless -- covered by a separate agreement. -- -- Xilinx is providing this design, code, or information -- "as-is" solely for use in developing programs and -- solutions for Xilinx devices, with no obligation on the -- part of Xilinx to provide support. By providing this design, -- code, or information as one possible implementation of -- this feature, application or standard, Xilinx is making no -- representation that this implementation is free from any -- claims of infringement. You are responsible for obtaining -- any rights you may require for your implementation. -- Xilinx expressly disclaims any warranty whatsoever with -- respect to the adequacy of the implementation, including -- but not limited to any warranties or representations that this -- implementation is free from claims of infringement, implied -- warranties of merchantability or fitness for a particular -- purpose. -- -- Xilinx products are not intended for use in life support -- appliances, devices, or systems. Use in such applications is -- expressly prohibited. -- -- Any modifications that are made to the Source Code are -- done at the users sole risk and will be unsupported. -- The Xilinx Support Hotline does not have access to source -- code and therefore cannot answer specific questions related -- to source HDL. The Xilinx Hotline support of original source -- code IP shall only address issues and questions related -- to the standard Netlist version of the core (and thus -- indirectly, the original core source). -- -- Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. -- -- This copyright and support notice must be retained as part -- of this text at all times. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: or_gate.vhd -- Version: v1.00a -- Description: OR gate implementation -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- or_gate.vhd -- ------------------------------------------------------------------------------- -- Author: B.L. Tise -- History: -- BLT 2001-05-23 First Version -- ^^^^^^ -- First version of OPB Bus. -- ~~~~~~ -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Changed proc_common library version to v4_0 -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_com" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library proc_common_v4_0; use proc_common_v4_0.all; ------------------------------------------------------------------------------- -- Definition of Generics: -- C_OR_WIDTH -- Which Xilinx FPGA family to target when -- syntesizing, affect the RLOC string values -- C_BUS_WIDTH -- Which Y position the RLOC should start from -- -- Definition of Ports: -- A -- Input. Input buses are concatenated together to -- form input A. Example: to OR buses R, S, and T, -- assign A <= R & S & T; -- Y -- Output. Same width as input buses. -- ------------------------------------------------------------------------------- entity or_gate is generic ( C_OR_WIDTH : natural range 1 to 32 := 17; C_BUS_WIDTH : natural range 1 to 64 := 1; C_USE_LUT_OR : boolean := TRUE ); port ( A : in std_logic_vector(0 to C_OR_WIDTHC_BUS_WIDTH-1); Y : out std_logic_vector(0 to C_BUS_WIDTH-1) ); end entity or_gate; architecture imp of or_gate is ------------------------------------------------------------------------------- -- Component Declarations ------------------------------------------------------------------------------- component or_muxcy generic ( C_NUM_BITS : integer := 8 ); port ( In_bus : in std_logic_vector(0 to C_NUM_BITS-1); Or_out : out std_logic ); end component or_muxcy; signal test : std_logic_vector(0 to C_BUS_WIDTH-1); ------------------------------------------------------------------------------- -- Begin architecture ------------------------------------------------------------------------------- begin USE_LUT_OR_GEN: if C_USE_LUT_OR generate OR_PROCESS: process( A ) is variable yi : std_logic_vector(0 to (C_OR_WIDTH)); begin for j in 0 to C_BUS_WIDTH-1 loop yi(0) := '0'; for i in 0 to C_OR_WIDTH-1 loop yi(i+1) := yi(i) or A(iC_BUS_WIDTH+j); end loop; Y(j) <= yi(C_OR_WIDTH); end loop; end process OR_PROCESS; end generate USE_LUT_OR_GEN; USE_MUXCY_OR_GEN: if not C_USE_LUT_OR generate BUS_WIDTH_FOR_GEN: for i in 0 to C_BUS_WIDTH-1 generate signal in_Bus : std_logic_vector(0 to C_OR_WIDTH-1); begin ORDER_INPUT_BUS_PROCESS: process( A ) is begin for k in 0 to C_OR_WIDTH-1 loop in_Bus(k) <= A(kC_BUS_WIDTH+i); end loop; end process ORDER_INPUT_BUS_PROCESS; OR_BITS_I: or_muxcy generic map ( C_NUM_BITS => C_OR_WIDTH ) port map ( In_bus => in_Bus, --[in] Or_out => Y(i) --[out] ); end generate BUS_WIDTH_FOR_GEN; end generate USE_MUXCY_OR_GEN; end architecture imp;	mit
bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_xbar_1/fifo_generator_v11_0/fifo_generator_v11_0_defaults.vhd	19	30145	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block lHZAv/MVAAt3F19GG6CyO2D9ozHTHXUyHUqVqPhHJ9Up8V3v4BMtL2rZCdPHvvrLl9m3lxdPLeMd yZjuwpNKug== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block V11pDh2GdTX922gInHRdE4PGQC5LocLJP7s9hbeXjPbTiX/dPLHGusbEN2B0toY0K8U4vuWNSniM 1aH2SNR2JV5BnhJYTc5D8l2e07TnA0V6ktY1z+NOBfbsIHPai5FO4rlYQdX0gfNxjRiE4WpTGufJ +8B9yaPmasK5qJ0hmyc= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", 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bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_0_0/fifo_generator_v11_0/ramfifo/wr_logic_pkt_fifo.vhd	19	31831	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block Pb7E+qNVEP4sE5d3TkwQJMYKTR/FjAPrexB6qdDJcLdscPV5w27UvNCqw/kg86JgS2hNrfoEvTNF uJ9eNTpy4Q== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Egq1eCtVuCp02bpffloqFi7UMw6fphk3UOZCcejhe9NQNeC0Z0b1+S1NY8yEfAVY74l4oz8pZ1vA hbrAzplanZae/BDY57rCQ6UjD8G9keaOwYv6mG13f+m77D7Y1nVpXOE4Uujw3cZ1QgwXR1H4YfYp ysjb+lxmo0pqYRikRIQ= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block KJqrZ5TKkbTlecBRrKRCsxKhAd1omWJvIin7DNafgTE5a5N2or7GsTSawdWWjYWHESLBvStvRGQE jVUeK8m63dYVJN98fa8T9iAHTDt9yiBRki/VqfvAejvDOEI+l8row+LhhHMvCd29xmkCeQKiq4Qt hsdsz+jNufnCYY4Y1CVO/4preMZeG5Ow85vRd/341CoWEOBji8o4pk0XyIttBBgjBzWO8JyhLpza R+Z8LgFoZ5OTfgpyTJ4SjYRWp9IHP2HL9TShNo3PmM36nFNBvQSLoEjLgk4+rUr657++ugJH31/C Y/QScvwJcbqMK15awb6twj42y2gxJSFzAPzSGg== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block KxmYEF19quU2lnDIx1hLVbiBV1iU7MlwBSbpQKNAVv6HLtZNpIjv2UPtz6sPs9Xac0T26s1Kjo2c fAw+uaSeKdgWE1BMMV8ya3nIO40+wJlyaPYGp3qW9dt6kM+FZZl/3MCpgIMx24FXg4CPHrHNKu54 /3DZJ7o9x/QjyM8WSeM= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect end_protected	mit
bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_auto_pc_3/fifo_generator_v11_0/ramfifo/wr_logic_pkt_fifo.vhd	19	31831	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block Pb7E+qNVEP4sE5d3TkwQJMYKTR/FjAPrexB6qdDJcLdscPV5w27UvNCqw/kg86JgS2hNrfoEvTNF uJ9eNTpy4Q== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Egq1eCtVuCp02bpffloqFi7UMw6fphk3UOZCcejhe9NQNeC0Z0b1+S1NY8yEfAVY74l4oz8pZ1vA hbrAzplanZae/BDY57rCQ6UjD8G9keaOwYv6mG13f+m77D7Y1nVpXOE4Uujw3cZ1QgwXR1H4YfYp ysjb+lxmo0pqYRikRIQ= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block KJqrZ5TKkbTlecBRrKRCsxKhAd1omWJvIin7DNafgTE5a5N2or7GsTSawdWWjYWHESLBvStvRGQE jVUeK8m63dYVJN98fa8T9iAHTDt9yiBRki/VqfvAejvDOEI+l8row+LhhHMvCd29xmkCeQKiq4Qt hsdsz+jNufnCYY4Y1CVO/4preMZeG5Ow85vRd/341CoWEOBji8o4pk0XyIttBBgjBzWO8JyhLpza R+Z8LgFoZ5OTfgpyTJ4SjYRWp9IHP2HL9TShNo3PmM36nFNBvQSLoEjLgk4+rUr657++ugJH31/C Y/QScvwJcbqMK15awb6twj42y2gxJSFzAPzSGg== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block KxmYEF19quU2lnDIx1hLVbiBV1iU7MlwBSbpQKNAVv6HLtZNpIjv2UPtz6sPs9Xac0T26s1Kjo2c fAw+uaSeKdgWE1BMMV8ya3nIO40+wJlyaPYGp3qW9dt6kM+FZZl/3MCpgIMx24FXg4CPHrHNKu54 /3DZJ7o9x/QjyM8WSeM= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect end_protected	mit
bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_0_0/fifo_generator_v11_0/ramfifo/bram_sync_reg.vhd	19	7904	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block ISK+8BrzqbDVc2hIh4k9UuGvqsq6yFic71tfszsK7KRf52jFUoK33AosGVUYsGH1pmrUc2NUQcDQ LseNrcojiQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block CxxZHetyKRTjg1ePIJzq+w/Yg+inN7g9nkhYUjpPSXav+SKIAQvdh174FZUi0SnoR2INo+rdZ3gz yq46XymO3b/3npnRNCCU259giTvnOJxmkrtnjRyUpOg8jB2jnHg/f/BlL3OJUGGiFonBs+6rnNvW 4aiU6ycFpLQsNzqRlAw= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block HZ1Kttz7DNn3t428AVZ/hrbCqljpJfsdfcEo7T7pfqxl88ELioDFFp9rVcvvZiZMU++45qS8CpOD SfwcEjOj8ndwnIsrDamIUHs+Qm4vUDDq8EtyiGhux+pwMtpg8rH6kCwLDCkdk848fWRbBOGctdAr AiQz4Fie2ectzKGEhjERjquMNqkQkhNIuEu/CSTnyD7KnG+FK+llVBavN8lxjWeDvk+quMyk8Dbo gA/SdzYI7TCZkNEFS/PvF3Z8fPBK4pBWz7TyfdHacMjMkaPd5zGsPBmQy77xwc4m/sfhM7ZX+YW6 VBTILiYtg7u194UVgu4fHE7f45jr0jTur9wbVw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 2VX2NPBJC/FYSjnVp8ueqtxuxLgenRIKbrff8tdhuTb77js7o9S4OVH2n84fEyvr3hl3lrO9ekVq VvQQOlQBg7Zv5/tFAeI5YFisgygYrqeX9dQcI485CaCpeN9nanYXhtHWROH+ZOYckBZHUhhjC82p LnYwoausKSjsi+rXE64= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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+ZTCmZXqn/Iz4EVz38kKAjet/kPqPS/Fj/atI6Bx2Mk/8h8CXOIlPx0Ho7P276GsCOwEBUHVdAEy GPxAxnrSDPM= `protect end_protected	mit
bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_1_1/fifo_generator_v11_0/ramfifo/bram_sync_reg.vhd	19	7904	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block ISK+8BrzqbDVc2hIh4k9UuGvqsq6yFic71tfszsK7KRf52jFUoK33AosGVUYsGH1pmrUc2NUQcDQ LseNrcojiQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block CxxZHetyKRTjg1ePIJzq+w/Yg+inN7g9nkhYUjpPSXav+SKIAQvdh174FZUi0SnoR2INo+rdZ3gz yq46XymO3b/3npnRNCCU259giTvnOJxmkrtnjRyUpOg8jB2jnHg/f/BlL3OJUGGiFonBs+6rnNvW 4aiU6ycFpLQsNzqRlAw= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block HZ1Kttz7DNn3t428AVZ/hrbCqljpJfsdfcEo7T7pfqxl88ELioDFFp9rVcvvZiZMU++45qS8CpOD SfwcEjOj8ndwnIsrDamIUHs+Qm4vUDDq8EtyiGhux+pwMtpg8rH6kCwLDCkdk848fWRbBOGctdAr AiQz4Fie2ectzKGEhjERjquMNqkQkhNIuEu/CSTnyD7KnG+FK+llVBavN8lxjWeDvk+quMyk8Dbo gA/SdzYI7TCZkNEFS/PvF3Z8fPBK4pBWz7TyfdHacMjMkaPd5zGsPBmQy77xwc4m/sfhM7ZX+YW6 VBTILiYtg7u194UVgu4fHE7f45jr0jTur9wbVw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 2VX2NPBJC/FYSjnVp8ueqtxuxLgenRIKbrff8tdhuTb77js7o9S4OVH2n84fEyvr3hl3lrO9ekVq VvQQOlQBg7Zv5/tFAeI5YFisgygYrqeX9dQcI485CaCpeN9nanYXhtHWROH+ZOYckBZHUhhjC82p LnYwoausKSjsi+rXE64= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block HdQIwrCqCFDZv9OQZsva3DMtF+8TwiePvWLQndNAXK/1V46C6C4sVLdH6SK4FvPis45PZ52T91rx x7mjaMnTgTVkK+VoFF3Ej7xzh/2PoR+YkiToyHCbvwHQXXvv3GAu3HyqWx9b4oOndnrx5Z1mco/s lNgEY825qOfDqrTkPvvNBXThybVoOKs2SBHAdaQhQemuYVAjS7mEC/lA7vom+55/0dhIN44Q0vMz 6utkLeK9axPmrUz/LHNLm3BFQsfvacsQoIQe/Y7g5V8ehxANfnzft/Jgo74fJAU3odGS++0PsHF5 2T1joNptoFFljB/U6DScrAB2FxigoQal7I/OSA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4112) `protect data_block 3u5JIWlY+sJCqsl5QYyfL8WimseQwuJN0rkH9NXcbsS7Rt71nSblODV6U80qYV7PQQBUgi7MIkr3 HhB80mVFXzhq03+IsvG1wT04pnRKUdjg8ie5ACc1KZyJzkBz1AoMYj8LIyYOfu5egdpx7hnlcrtc oMVqdqAkXV7SfIyeRr+lT2ka1rchyxgy/De7WO04vRL9oeE9RcJ9dBv1wr0O3CTselhBxOW1zVMw VAIAfDSqygylxQ3yBGTnNYvRqgjwbIDq9qrVv2Suz92kP9MPjiqJNh+Bl2oXJ4RpniHsbunWAgYk u8htsKr/Y5G/lv1Dti4uvGyDQc6n4n4m6zawTfv6qfGRG+QxlxQbJYAjHfK8NQmU/rbLQnZOQzKx nWuJgpAxqNY55zImfUi7u9EaW8P5tnNRTCHRpFTP7maxF/yrAvQ9F70ow37gmox0htVWAHNvXHEA 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bpervan/zedboard	LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/fifo_generator_v11_0/ramfifo/dc_ss_fwft.vhd	19	9156	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block eRz+leRSRPpou0Iyb6bnhB8hg9kPbBirrzFUAdKqw/be3+N8ZrhDizYaLfXqnwxlgZsSWJCzRfM7 HvMw/rTLhw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Rl74r1iJC/bnSjzA+Rx4NZe56NnmjoVRFzUux12uAkwgT++rVuZ0cWQxVSY31Gff9TGn02lNxavo U1xWF81U2u/Zi0XY7ZHmbpbdUEdpSv9huiEIrpuLuTgWjBSUwsGYqRxHLx1vq4vioRXFlAhPk9JA iYodwxjKI7YbbZElfVA= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block lO1ylq105LQ/xiJNZcB3fPTy1RngsQ3yQ/KJ6FM1qs+SoXmUQjQaEb6hJLPAypYN8r4VdJAzSC/U 5nFe27DWNjEKmiIleROkH20okne+9N7+PhPIZQnib521U3SV/ecBImKKPYRpHhAeqE7OE/DzQFWx 10ISqR1I6WBii4R8gkz5k4dkFHhiTU6fgkIHLUXXclJrpQ6fHHlk7MPcpQDjK7bXjIiQ81qfpVmp P5Kh8wiY7VppUj33GlIcYsNio8GAIV3e0kBKLoX73uDqdvJ/2zBzKOZoDd0As7C4AHF8YSixL0MC djalIDRCSOBX8Rd9h057rIe8ZIXNMu/BHoKk/g== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block aJoUzTg4Ju9hNY+ZPcuNUmGg+rCD8aivgSTst8VRB5/g9QHuzghA24ad2z08gxWDFeIOT/HFgT6H g4nDsyLlbHK2gxUijkJ6ORkRfGOxb8UwHTzLEIRJ5zmkHtJXYM250JOsiukrgEDT40HqdtSgre6O kXXliGFm9MU0LwRby+I= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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dries007/Basys3	FPGA-Z/FPGA-Z.srcs/sim_1/new/test2.vhd	1	902	---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 04/16/2016 09:56:37 PM -- Design Name: -- Module Name: test2 - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity test2 is -- Port ( ); end test2; architecture Behavioral of test2 is begin end Behavioral;	mit
dries007/Basys3	VGA_text/VGA_text.srcs/sources_1/ip/FrameBuffer/FrameBuffer_sim_netlist.vhdl	1	105072	-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015 -- Date : Fri Jun 3 00:16:36 2016 -- Host : Dries007-Arch running 64-bit unknown -- Command : write_vhdl -force -mode funcsim -- /home/dries/Projects/Basys3/VGA_text/VGA_text.srcs/sources_1/ip/FrameBuffer/FrameBuffer_sim_netlist.vhdl -- Design : FrameBuffer -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7a35tcpg236-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity FrameBuffer_blk_mem_gen_mux is port ( douta : out STD_LOGIC_VECTOR ( 7 downto 0 ); DOADO : in STD_LOGIC_VECTOR ( 7 downto 0 ); \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); addra : in STD_LOGIC_VECTOR ( 2 downto 0 ); ena : in STD_LOGIC; clka : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_mux : entity is "blk_mem_gen_mux"; end FrameBuffer_blk_mem_gen_mux; architecture STRUCTURE of FrameBuffer_blk_mem_gen_mux is signal \no_softecc_sel_reg.ce_pri.sel_pipe[0]_i_1_n_0\ : STD_LOGIC; signal \no_softecc_sel_reg.ce_pri.sel_pipe[1]_i_1_n_0\ : STD_LOGIC; signal \no_softecc_sel_reg.ce_pri.sel_pipe[2]_i_1_n_0\ : STD_LOGIC; signal sel_pipe : STD_LOGIC_VECTOR ( 2 downto 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \no_softecc_sel_reg.ce_pri.sel_pipe[1]_i_1\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \no_softecc_sel_reg.ce_pri.sel_pipe[2]_i_1\ : label is "soft_lutpair0"; begin \douta[0]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOADO(0), I1 => sel_pipe(0), I2 => sel_pipe(1), I3 => sel_pipe(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(0), I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(0), O => douta(0) ); \douta[1]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOADO(1), I1 => sel_pipe(0), I2 => sel_pipe(1), I3 => sel_pipe(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(1), I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(1), O => douta(1) ); \douta[2]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOADO(2), I1 => sel_pipe(0), I2 => sel_pipe(1), I3 => sel_pipe(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(2), I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(2), O => douta(2) ); \douta[3]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOADO(3), I1 => sel_pipe(0), I2 => sel_pipe(1), I3 => sel_pipe(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3), I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(3), O => douta(3) ); \douta[4]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOADO(4), I1 => sel_pipe(0), I2 => sel_pipe(1), I3 => sel_pipe(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(4), I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(4), O => douta(4) ); \douta[5]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOADO(5), I1 => sel_pipe(0), I2 => sel_pipe(1), I3 => sel_pipe(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(5), I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(5), O => douta(5) ); \douta[6]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOADO(6), I1 => sel_pipe(0), I2 => sel_pipe(1), I3 => sel_pipe(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(6), I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(6), O => douta(6) ); \douta[7]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOADO(7), I1 => sel_pipe(0), I2 => sel_pipe(1), I3 => sel_pipe(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(7), I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7), O => douta(7) ); \no_softecc_sel_reg.ce_pri.sel_pipe[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => addra(0), I1 => ena, I2 => sel_pipe(0), O => \no_softecc_sel_reg.ce_pri.sel_pipe[0]_i_1_n_0\ ); \no_softecc_sel_reg.ce_pri.sel_pipe[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => addra(1), I1 => ena, I2 => sel_pipe(1), O => \no_softecc_sel_reg.ce_pri.sel_pipe[1]_i_1_n_0\ ); \no_softecc_sel_reg.ce_pri.sel_pipe[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => addra(2), I1 => ena, I2 => sel_pipe(2), O => \no_softecc_sel_reg.ce_pri.sel_pipe[2]_i_1_n_0\ ); \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clka, CE => '1', D => \no_softecc_sel_reg.ce_pri.sel_pipe[0]_i_1_n_0\, Q => sel_pipe(0), R => '0' ); \no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clka, CE => '1', D => \no_softecc_sel_reg.ce_pri.sel_pipe[1]_i_1_n_0\, Q => sel_pipe(1), R => '0' ); \no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clka, CE => '1', D => \no_softecc_sel_reg.ce_pri.sel_pipe[2]_i_1_n_0\, Q => sel_pipe(2), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \FrameBuffer_blk_mem_gen_mux__parameterized0\ is port ( doutb : out STD_LOGIC_VECTOR ( 7 downto 0 ); DOBDO : in STD_LOGIC_VECTOR ( 7 downto 0 ); \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 2 downto 0 ); clkb : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \FrameBuffer_blk_mem_gen_mux__parameterized0\ : entity is "blk_mem_gen_mux"; end \FrameBuffer_blk_mem_gen_mux__parameterized0\; architecture STRUCTURE of \FrameBuffer_blk_mem_gen_mux__parameterized0\ is signal \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0]\ : STD_LOGIC; signal \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[1]\ : STD_LOGIC; signal \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[2]\ : STD_LOGIC; signal sel_pipe_d1 : STD_LOGIC_VECTOR ( 2 downto 0 ); begin \doutb[0]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOBDO(0), I1 => sel_pipe_d1(0), I2 => sel_pipe_d1(1), I3 => sel_pipe_d1(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(0), I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(0), O => doutb(0) ); \doutb[1]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOBDO(1), I1 => sel_pipe_d1(0), I2 => sel_pipe_d1(1), I3 => sel_pipe_d1(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(1), I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(1), O => doutb(1) ); \doutb[2]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOBDO(2), I1 => sel_pipe_d1(0), I2 => sel_pipe_d1(1), I3 => sel_pipe_d1(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(2), I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(2), O => doutb(2) ); \doutb[3]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOBDO(3), I1 => sel_pipe_d1(0), I2 => sel_pipe_d1(1), I3 => sel_pipe_d1(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3), I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(3), O => doutb(3) ); \doutb[4]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOBDO(4), I1 => sel_pipe_d1(0), I2 => sel_pipe_d1(1), I3 => sel_pipe_d1(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(4), I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(4), O => doutb(4) ); \doutb[5]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOBDO(5), I1 => sel_pipe_d1(0), I2 => sel_pipe_d1(1), I3 => sel_pipe_d1(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(5), I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(5), O => doutb(5) ); \doutb[6]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOBDO(6), I1 => sel_pipe_d1(0), I2 => sel_pipe_d1(1), I3 => sel_pipe_d1(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(6), I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(6), O => doutb(6) ); \doutb[7]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOBDO(7), I1 => sel_pipe_d1(0), I2 => sel_pipe_d1(1), I3 => sel_pipe_d1(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(7), I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7), O => doutb(7) ); \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clkb, CE => '1', D => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0]\, Q => sel_pipe_d1(0), R => '0' ); \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clkb, CE => '1', D => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[1]\, Q => sel_pipe_d1(1), R => '0' ); \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clkb, CE => '1', D => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[2]\, Q => sel_pipe_d1(2), R => '0' ); \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clkb, CE => '1', D => addrb(0), Q => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0]\, R => '0' ); \no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clkb, CE => '1', D => addrb(1), Q => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[1]\, R => '0' ); \no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clkb, CE => '1', D => addrb(2), Q => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[2]\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity FrameBuffer_blk_mem_gen_prim_wrapper_init is port ( \douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); \doutb[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); clka : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 7 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ); web : in STD_LOGIC_VECTOR ( 0 to 0 ); ena : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init"; end FrameBuffer_blk_mem_gen_prim_wrapper_init; architecture STRUCTURE of FrameBuffer_blk_mem_gen_prim_wrapper_init is signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1_n_0\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2_n_0\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_n_92\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute CLOCK_DOMAINS : string; attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT"; attribute box_type : string; attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE"; begin \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1 generic map( DOA_REG => 0, DOB_REG => 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\NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1), DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_n_88\, DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1), DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_n_92\, ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0), ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1_n_0\, ENBWREN => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2_n_0\, INJECTDBITERR => '0', INJECTSBITERR => '0', RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0), REGCEAREGCE => '0', REGCEB => '1', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\, WEA(3) => wea(0), WEA(2) => wea(0), WEA(1) => wea(0), WEA(0) => wea(0), WEBWE(7 downto 4) => B"0000", WEBWE(3) => web(0), WEBWE(2) => web(0), WEBWE(1) => web(0), WEBWE(0) => web(0) ); \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => ena, I1 => addra(12), I2 => addra(13), O => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1_n_0\ ); \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => addrb(12), I1 => addrb(13), O => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized0\ is port ( \douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); \doutb[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); clka : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 7 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ); web : in STD_LOGIC_VECTOR ( 0 to 0 ); ena : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init"; end \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized0\; architecture STRUCTURE of \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized0\ is signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1__0_n_0\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2__0_n_0\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_n_92\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute CLOCK_DOMAINS : string; attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT"; attribute box_type : string; attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE"; begin \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1 generic map( DOA_REG => 0, DOB_REG => 1, EN_ECC_READ => false, EN_ECC_WRITE => false, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => 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SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", WRITE_WIDTH_A => 9, WRITE_WIDTH_B => 9 ) port map ( ADDRARDADDR(15) => '1', ADDRARDADDR(14 downto 3) => addra(11 downto 0), ADDRARDADDR(2 downto 0) => B"111", ADDRBWRADDR(15) => '1', ADDRBWRADDR(14 downto 3) => addrb(11 downto 0), ADDRBWRADDR(2 downto 0) => B"111", CASCADEINA => '0', CASCADEINB => '0', CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\, CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\, CLKARDCLK => clka, CLKBWRCLK => clkb, DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\, DIADI(31 downto 8) => B"000000000000000000000000", DIADI(7 downto 0) => dina(7 downto 0), DIBDI(31 downto 8) => B"000000000000000000000000", DIBDI(7 downto 0) => dinb(7 downto 0), DIPADIP(3 downto 0) => B"0000", DIPBDIP(3 downto 0) => B"0000", DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8), DOADO(7 downto 0) => \douta[7]\(7 downto 0), DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8), DOBDO(7 downto 0) => \doutb[7]\(7 downto 0), DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1), DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_n_88\, DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1), DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_n_92\, ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0), ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1__0_n_0\, ENBWREN => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2__0_n_0\, INJECTDBITERR => '0', INJECTSBITERR => '0', RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0), REGCEAREGCE => '0', REGCEB => '1', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\, WEA(3) => wea(0), WEA(2) => wea(0), WEA(1) => wea(0), WEA(0) => wea(0), WEBWE(7 downto 4) => B"0000", WEBWE(3) => web(0), WEBWE(2) => web(0), WEBWE(1) => web(0), WEBWE(0) => web(0) ); \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"08" ) port map ( I0 => addra(12), I1 => ena, I2 => addra(13), O => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1__0_n_0\ ); \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2__0\: unisim.vcomponents.LUT2 generic map( INIT => X"4" ) port map ( I0 => addrb(13), I1 => addrb(12), O => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2__0_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized1\ is port ( DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 ); DOBDO : out STD_LOGIC_VECTOR ( 7 downto 0 ); clka : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 7 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ); web : in STD_LOGIC_VECTOR ( 0 to 0 ); ena : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized1\ : entity is "blk_mem_gen_prim_wrapper_init"; end \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized1\; architecture STRUCTURE of \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized1\ is signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_n_33\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_n_35\ : STD_LOGIC; signal ram_ena : STD_LOGIC; signal ram_enb : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 8 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 8 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 to 1 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 to 1 ); attribute CLOCK_DOMAINS : string; attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\ : label is "INDEPENDENT"; attribute box_type : string; attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE"; begin \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1 generic map( DOA_REG => 0, DOB_REG => 1, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_01 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_02 => 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X"20202020202020202020202020202020202020202020203E74656E2E37303073", INIT_3F => X"802B202020202020202020202020202020202020202020202020202020202020", INIT_A => X"00000", INIT_B => X"00000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", READ_WIDTH_A => 9, READ_WIDTH_B => 9, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"00000", SRVAL_B => X"00000", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", WRITE_WIDTH_A => 9, WRITE_WIDTH_B => 9 ) port map ( ADDRARDADDR(13 downto 3) => addra(10 downto 0), ADDRARDADDR(2 downto 0) => B"000", ADDRBWRADDR(13 downto 3) => addrb(10 downto 0), ADDRBWRADDR(2 downto 0) => B"000", CLKARDCLK => clka, CLKBWRCLK => clkb, DIADI(15 downto 8) => B"00000000", DIADI(7 downto 0) => dina(7 downto 0), DIBDI(15 downto 8) => B"00000000", DIBDI(7 downto 0) => dinb(7 downto 0), DIPADIP(1 downto 0) => B"00", DIPBDIP(1 downto 0) => B"00", DOADO(15 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 8), DOADO(7 downto 0) => DOADO(7 downto 0), DOBDO(15 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 8), DOBDO(7 downto 0) => DOBDO(7 downto 0), DOPADOP(1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1), DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_n_33\, DOPBDOP(1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1), DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_n_35\, ENARDEN => ram_ena, ENBWREN => ram_enb, REGCEAREGCE => '0', REGCEB => '1', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', WEA(1) => wea(0), WEA(0) => wea(0), WEBWE(3 downto 2) => B"00", WEBWE(1) => web(0), WEBWE(0) => web(0) ); \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"1000" ) port map ( I0 => addra(12), I1 => addra(11), I2 => addra(13), I3 => ena, O => ram_ena ); \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"04" ) port map ( I0 => addrb(11), I1 => addrb(13), I2 => addrb(12), O => ram_enb ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity FrameBuffer_blk_mem_gen_prim_width is port ( \douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); \doutb[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); clka : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 7 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ); web : in STD_LOGIC_VECTOR ( 0 to 0 ); ena : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width"; end FrameBuffer_blk_mem_gen_prim_width; architecture STRUCTURE of FrameBuffer_blk_mem_gen_prim_width is begin \prim_init.ram\: entity work.FrameBuffer_blk_mem_gen_prim_wrapper_init port map ( addra(13 downto 0) => addra(13 downto 0), addrb(13 downto 0) => addrb(13 downto 0), clka => clka, clkb => clkb, dina(7 downto 0) => dina(7 downto 0), dinb(7 downto 0) => dinb(7 downto 0), \douta[7]\(7 downto 0) => \douta[7]\(7 downto 0), \doutb[7]\(7 downto 0) => \doutb[7]\(7 downto 0), ena => ena, wea(0) => wea(0), web(0) => web(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \FrameBuffer_blk_mem_gen_prim_width__parameterized0\ is port ( \douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); \doutb[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); clka : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 7 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ); web : in STD_LOGIC_VECTOR ( 0 to 0 ); ena : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \FrameBuffer_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width"; end \FrameBuffer_blk_mem_gen_prim_width__parameterized0\; architecture STRUCTURE of \FrameBuffer_blk_mem_gen_prim_width__parameterized0\ is begin \prim_init.ram\: entity work.\FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized0\ port map ( addra(13 downto 0) => addra(13 downto 0), addrb(13 downto 0) => addrb(13 downto 0), clka => clka, clkb => clkb, dina(7 downto 0) => dina(7 downto 0), dinb(7 downto 0) => dinb(7 downto 0), \douta[7]\(7 downto 0) => \douta[7]\(7 downto 0), \doutb[7]\(7 downto 0) => \doutb[7]\(7 downto 0), ena => ena, wea(0) => wea(0), web(0) => web(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \FrameBuffer_blk_mem_gen_prim_width__parameterized1\ is port ( DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 ); DOBDO : out STD_LOGIC_VECTOR ( 7 downto 0 ); clka : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 7 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ); web : in STD_LOGIC_VECTOR ( 0 to 0 ); ena : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \FrameBuffer_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width"; end \FrameBuffer_blk_mem_gen_prim_width__parameterized1\; architecture STRUCTURE of \FrameBuffer_blk_mem_gen_prim_width__parameterized1\ is begin \prim_init.ram\: entity work.\FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized1\ port map ( DOADO(7 downto 0) => DOADO(7 downto 0), DOBDO(7 downto 0) => DOBDO(7 downto 0), addra(13 downto 0) => addra(13 downto 0), addrb(13 downto 0) => addrb(13 downto 0), clka => clka, clkb => clkb, dina(7 downto 0) => dina(7 downto 0), dinb(7 downto 0) => dinb(7 downto 0), ena => ena, wea(0) => wea(0), web(0) => web(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity FrameBuffer_blk_mem_gen_generic_cstr is port ( doutb : out STD_LOGIC_VECTOR ( 7 downto 0 ); douta : out STD_LOGIC_VECTOR ( 7 downto 0 ); clka : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 7 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ); web : in STD_LOGIC_VECTOR ( 0 to 0 ); ena : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr"; end FrameBuffer_blk_mem_gen_generic_cstr; architecture STRUCTURE of FrameBuffer_blk_mem_gen_generic_cstr is signal ram_douta : STD_LOGIC_VECTOR ( 7 downto 0 ); signal ram_doutb : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \ramloop[1].ram.r_n_0\ : STD_LOGIC; signal \ramloop[1].ram.r_n_1\ : STD_LOGIC; signal \ramloop[1].ram.r_n_10\ : STD_LOGIC; signal \ramloop[1].ram.r_n_11\ : STD_LOGIC; signal \ramloop[1].ram.r_n_12\ : STD_LOGIC; signal \ramloop[1].ram.r_n_13\ : STD_LOGIC; signal \ramloop[1].ram.r_n_14\ : STD_LOGIC; signal \ramloop[1].ram.r_n_15\ : STD_LOGIC; signal \ramloop[1].ram.r_n_2\ : STD_LOGIC; signal \ramloop[1].ram.r_n_3\ : STD_LOGIC; signal \ramloop[1].ram.r_n_4\ : STD_LOGIC; signal \ramloop[1].ram.r_n_5\ : STD_LOGIC; signal \ramloop[1].ram.r_n_6\ : STD_LOGIC; signal \ramloop[1].ram.r_n_7\ : STD_LOGIC; signal \ramloop[1].ram.r_n_8\ : STD_LOGIC; signal \ramloop[1].ram.r_n_9\ : STD_LOGIC; signal \ramloop[2].ram.r_n_0\ : STD_LOGIC; signal \ramloop[2].ram.r_n_1\ : STD_LOGIC; signal \ramloop[2].ram.r_n_10\ : STD_LOGIC; signal \ramloop[2].ram.r_n_11\ : STD_LOGIC; signal \ramloop[2].ram.r_n_12\ : STD_LOGIC; signal \ramloop[2].ram.r_n_13\ : STD_LOGIC; signal \ramloop[2].ram.r_n_14\ : STD_LOGIC; signal \ramloop[2].ram.r_n_15\ : STD_LOGIC; signal \ramloop[2].ram.r_n_2\ : STD_LOGIC; signal \ramloop[2].ram.r_n_3\ : STD_LOGIC; signal \ramloop[2].ram.r_n_4\ : STD_LOGIC; signal \ramloop[2].ram.r_n_5\ : STD_LOGIC; signal \ramloop[2].ram.r_n_6\ : STD_LOGIC; signal \ramloop[2].ram.r_n_7\ : STD_LOGIC; signal \ramloop[2].ram.r_n_8\ : STD_LOGIC; signal \ramloop[2].ram.r_n_9\ : STD_LOGIC; begin \has_mux_a.A\: entity work.FrameBuffer_blk_mem_gen_mux port map ( \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(7) => \ramloop[1].ram.r_n_0\, \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(6) => \ramloop[1].ram.r_n_1\, \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(5) => \ramloop[1].ram.r_n_2\, \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(4) => \ramloop[1].ram.r_n_3\, \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3) => \ramloop[1].ram.r_n_4\, \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(2) => \ramloop[1].ram.r_n_5\, \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(1) => \ramloop[1].ram.r_n_6\, \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(0) => \ramloop[1].ram.r_n_7\, \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7 downto 0) => ram_douta(7 downto 0), DOADO(7) => \ramloop[2].ram.r_n_0\, DOADO(6) => \ramloop[2].ram.r_n_1\, DOADO(5) => \ramloop[2].ram.r_n_2\, DOADO(4) => \ramloop[2].ram.r_n_3\, DOADO(3) => \ramloop[2].ram.r_n_4\, DOADO(2) => \ramloop[2].ram.r_n_5\, DOADO(1) => \ramloop[2].ram.r_n_6\, DOADO(0) => \ramloop[2].ram.r_n_7\, addra(2 downto 0) => addra(13 downto 11), clka => clka, douta(7 downto 0) => douta(7 downto 0), ena => ena ); \has_mux_b.B\: entity work.\FrameBuffer_blk_mem_gen_mux__parameterized0\ port map ( \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(7) => \ramloop[1].ram.r_n_8\, \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(6) => \ramloop[1].ram.r_n_9\, \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(5) => \ramloop[1].ram.r_n_10\, \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(4) => \ramloop[1].ram.r_n_11\, \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3) => \ramloop[1].ram.r_n_12\, \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(2) => \ramloop[1].ram.r_n_13\, \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(1) => \ramloop[1].ram.r_n_14\, \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(0) => \ramloop[1].ram.r_n_15\, \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7 downto 0) => ram_doutb(7 downto 0), DOBDO(7) => \ramloop[2].ram.r_n_8\, DOBDO(6) => \ramloop[2].ram.r_n_9\, DOBDO(5) => \ramloop[2].ram.r_n_10\, DOBDO(4) => \ramloop[2].ram.r_n_11\, DOBDO(3) => \ramloop[2].ram.r_n_12\, DOBDO(2) => \ramloop[2].ram.r_n_13\, DOBDO(1) => \ramloop[2].ram.r_n_14\, DOBDO(0) => \ramloop[2].ram.r_n_15\, addrb(2 downto 0) => addrb(13 downto 11), clkb => clkb, doutb(7 downto 0) => doutb(7 downto 0) ); \ramloop[0].ram.r\: entity work.FrameBuffer_blk_mem_gen_prim_width port map ( addra(13 downto 0) => addra(13 downto 0), addrb(13 downto 0) => addrb(13 downto 0), clka => clka, clkb => clkb, dina(7 downto 0) => dina(7 downto 0), dinb(7 downto 0) => dinb(7 downto 0), \douta[7]\(7 downto 0) => ram_douta(7 downto 0), \doutb[7]\(7 downto 0) => ram_doutb(7 downto 0), ena => ena, wea(0) => wea(0), web(0) => web(0) ); \ramloop[1].ram.r\: entity work.\FrameBuffer_blk_mem_gen_prim_width__parameterized0\ port map ( addra(13 downto 0) => addra(13 downto 0), addrb(13 downto 0) => addrb(13 downto 0), clka => clka, clkb => clkb, dina(7 downto 0) => dina(7 downto 0), dinb(7 downto 0) => dinb(7 downto 0), \douta[7]\(7) => \ramloop[1].ram.r_n_0\, \douta[7]\(6) => \ramloop[1].ram.r_n_1\, \douta[7]\(5) => \ramloop[1].ram.r_n_2\, \douta[7]\(4) => \ramloop[1].ram.r_n_3\, \douta[7]\(3) => \ramloop[1].ram.r_n_4\, \douta[7]\(2) => \ramloop[1].ram.r_n_5\, \douta[7]\(1) => \ramloop[1].ram.r_n_6\, \douta[7]\(0) => \ramloop[1].ram.r_n_7\, \doutb[7]\(7) => \ramloop[1].ram.r_n_8\, \doutb[7]\(6) => \ramloop[1].ram.r_n_9\, \doutb[7]\(5) => \ramloop[1].ram.r_n_10\, \doutb[7]\(4) => \ramloop[1].ram.r_n_11\, \doutb[7]\(3) => \ramloop[1].ram.r_n_12\, \doutb[7]\(2) => \ramloop[1].ram.r_n_13\, \doutb[7]\(1) => \ramloop[1].ram.r_n_14\, \doutb[7]\(0) => \ramloop[1].ram.r_n_15\, ena => ena, wea(0) => wea(0), web(0) => web(0) ); \ramloop[2].ram.r\: entity work.\FrameBuffer_blk_mem_gen_prim_width__parameterized1\ port map ( DOADO(7) => \ramloop[2].ram.r_n_0\, DOADO(6) => \ramloop[2].ram.r_n_1\, DOADO(5) => \ramloop[2].ram.r_n_2\, DOADO(4) => \ramloop[2].ram.r_n_3\, DOADO(3) => \ramloop[2].ram.r_n_4\, DOADO(2) => \ramloop[2].ram.r_n_5\, DOADO(1) => \ramloop[2].ram.r_n_6\, DOADO(0) => \ramloop[2].ram.r_n_7\, DOBDO(7) => \ramloop[2].ram.r_n_8\, DOBDO(6) => \ramloop[2].ram.r_n_9\, DOBDO(5) => \ramloop[2].ram.r_n_10\, DOBDO(4) => \ramloop[2].ram.r_n_11\, DOBDO(3) => \ramloop[2].ram.r_n_12\, DOBDO(2) => \ramloop[2].ram.r_n_13\, DOBDO(1) => \ramloop[2].ram.r_n_14\, DOBDO(0) => \ramloop[2].ram.r_n_15\, addra(13 downto 0) => addra(13 downto 0), addrb(13 downto 0) => addrb(13 downto 0), clka => clka, clkb => clkb, dina(7 downto 0) => dina(7 downto 0), dinb(7 downto 0) => dinb(7 downto 0), ena => ena, wea(0) => wea(0), web(0) => web(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity FrameBuffer_blk_mem_gen_top is port ( doutb : out STD_LOGIC_VECTOR ( 7 downto 0 ); douta : out STD_LOGIC_VECTOR ( 7 downto 0 ); clka : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 7 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ); web : in STD_LOGIC_VECTOR ( 0 to 0 ); ena : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_top : entity is "blk_mem_gen_top"; end FrameBuffer_blk_mem_gen_top; architecture STRUCTURE of FrameBuffer_blk_mem_gen_top is begin \valid.cstr\: entity work.FrameBuffer_blk_mem_gen_generic_cstr port map ( addra(13 downto 0) => addra(13 downto 0), addrb(13 downto 0) => addrb(13 downto 0), clka => clka, clkb => clkb, dina(7 downto 0) => dina(7 downto 0), dinb(7 downto 0) => dinb(7 downto 0), douta(7 downto 0) => douta(7 downto 0), doutb(7 downto 0) => doutb(7 downto 0), ena => ena, wea(0) => wea(0), web(0) => web(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity FrameBuffer_blk_mem_gen_v8_3_1_synth is port ( doutb : out STD_LOGIC_VECTOR ( 7 downto 0 ); douta : out STD_LOGIC_VECTOR ( 7 downto 0 ); clka : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 7 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ); web : in STD_LOGIC_VECTOR ( 0 to 0 ); ena : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_v8_3_1_synth : entity is "blk_mem_gen_v8_3_1_synth"; end FrameBuffer_blk_mem_gen_v8_3_1_synth; architecture STRUCTURE of FrameBuffer_blk_mem_gen_v8_3_1_synth is begin \gnativebmg.native_blk_mem_gen\: entity work.FrameBuffer_blk_mem_gen_top port map ( addra(13 downto 0) => addra(13 downto 0), addrb(13 downto 0) => addrb(13 downto 0), clka => clka, clkb => clkb, dina(7 downto 0) => dina(7 downto 0), dinb(7 downto 0) => dinb(7 downto 0), douta(7 downto 0) => douta(7 downto 0), doutb(7 downto 0) => doutb(7 downto 0), ena => ena, wea(0) => wea(0), web(0) => web(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity FrameBuffer_blk_mem_gen_v8_3_1 is port ( clka : in STD_LOGIC; rsta : in STD_LOGIC; ena : in STD_LOGIC; regcea : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); douta : out STD_LOGIC_VECTOR ( 7 downto 0 ); clkb : in STD_LOGIC; rstb : in STD_LOGIC; enb : in STD_LOGIC; regceb : in STD_LOGIC; web : in STD_LOGIC_VECTOR ( 0 to 0 ); addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 7 downto 0 ); doutb : out STD_LOGIC_VECTOR ( 7 downto 0 ); injectsbiterr : in STD_LOGIC; injectdbiterr : in STD_LOGIC; eccpipece : in STD_LOGIC; sbiterr : out STD_LOGIC; dbiterr : out STD_LOGIC; rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 ); sleep : in STD_LOGIC; deepsleep : in STD_LOGIC; shutdown : in STD_LOGIC; rsta_busy : out STD_LOGIC; rstb_busy : out STD_LOGIC; s_aclk : in STD_LOGIC; s_aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; s_axi_injectsbiterr : in STD_LOGIC; s_axi_injectdbiterr : in STD_LOGIC; s_axi_sbiterr : out STD_LOGIC; s_axi_dbiterr : out STD_LOGIC; s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 ) ); attribute C_ADDRA_WIDTH : integer; attribute C_ADDRA_WIDTH of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 14; attribute C_ADDRB_WIDTH : integer; attribute C_ADDRB_WIDTH of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 14; attribute C_ALGORITHM : integer; attribute C_ALGORITHM of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 4; attribute C_AXI_SLAVE_TYPE : integer; attribute C_AXI_SLAVE_TYPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_AXI_TYPE : integer; attribute C_AXI_TYPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1; attribute C_BYTE_SIZE : integer; attribute C_BYTE_SIZE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 8; attribute C_COMMON_CLK : integer; attribute C_COMMON_CLK of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_COUNT_18K_BRAM : string; attribute C_COUNT_18K_BRAM of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "1"; attribute C_COUNT_36K_BRAM : string; attribute C_COUNT_36K_BRAM of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "2"; attribute C_CTRL_ECC_ALGO : string; attribute C_CTRL_ECC_ALGO of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "NONE"; attribute C_DEFAULT_DATA : string; attribute C_DEFAULT_DATA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "0"; attribute C_DISABLE_WARN_BHV_COLL : integer; attribute C_DISABLE_WARN_BHV_COLL of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_DISABLE_WARN_BHV_RANGE : integer; attribute C_DISABLE_WARN_BHV_RANGE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_ELABORATION_DIR : string; attribute C_ELABORATION_DIR of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "./"; attribute C_ENABLE_32BIT_ADDRESS : integer; attribute C_ENABLE_32BIT_ADDRESS of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_EN_DEEPSLEEP_PIN : integer; attribute C_EN_DEEPSLEEP_PIN of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_EN_ECC_PIPE : integer; attribute C_EN_ECC_PIPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_EN_RDADDRA_CHG : integer; attribute C_EN_RDADDRA_CHG of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_EN_RDADDRB_CHG : integer; attribute C_EN_RDADDRB_CHG of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_EN_SAFETY_CKT : integer; attribute C_EN_SAFETY_CKT of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_EN_SHUTDOWN_PIN : integer; attribute C_EN_SHUTDOWN_PIN of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_EN_SLEEP_PIN : integer; attribute C_EN_SLEEP_PIN of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_EST_POWER_SUMMARY : string; attribute C_EST_POWER_SUMMARY of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "Estimated Power for IP : 4.61856 mW"; attribute C_FAMILY : string; attribute C_FAMILY of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "artix7"; attribute C_HAS_AXI_ID : integer; attribute C_HAS_AXI_ID of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_ENA : integer; attribute C_HAS_ENA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1; attribute C_HAS_ENB : integer; attribute C_HAS_ENB of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_INJECTERR : integer; attribute C_HAS_INJECTERR of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_MEM_OUTPUT_REGS_A : integer; attribute C_HAS_MEM_OUTPUT_REGS_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_MEM_OUTPUT_REGS_B : integer; attribute C_HAS_MEM_OUTPUT_REGS_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1; attribute C_HAS_MUX_OUTPUT_REGS_A : integer; attribute C_HAS_MUX_OUTPUT_REGS_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_MUX_OUTPUT_REGS_B : integer; attribute C_HAS_MUX_OUTPUT_REGS_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_REGCEA : integer; attribute C_HAS_REGCEA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_REGCEB : integer; attribute C_HAS_REGCEB of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_RSTA : integer; attribute C_HAS_RSTA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_RSTB : integer; attribute C_HAS_RSTB of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; attribute C_HAS_SOFTECC_INPUT_REGS_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; attribute C_HAS_SOFTECC_OUTPUT_REGS_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_INITA_VAL : string; attribute C_INITA_VAL of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "0"; attribute C_INITB_VAL : string; attribute C_INITB_VAL of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "0"; attribute C_INIT_FILE : string; attribute C_INIT_FILE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "FrameBuffer.mem"; attribute C_INIT_FILE_NAME : string; attribute C_INIT_FILE_NAME of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "FrameBuffer.mif"; attribute C_INTERFACE_TYPE : integer; attribute C_INTERFACE_TYPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_LOAD_INIT_FILE : integer; attribute C_LOAD_INIT_FILE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1; attribute C_MEM_TYPE : integer; attribute C_MEM_TYPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 2; attribute C_MUX_PIPELINE_STAGES : integer; attribute C_MUX_PIPELINE_STAGES of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_PRIM_TYPE : integer; attribute C_PRIM_TYPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1; attribute C_READ_DEPTH_A : integer; attribute C_READ_DEPTH_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 10240; attribute C_READ_DEPTH_B : integer; attribute C_READ_DEPTH_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 10240; attribute C_READ_WIDTH_A : integer; attribute C_READ_WIDTH_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 8; attribute C_READ_WIDTH_B : integer; attribute C_READ_WIDTH_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 8; attribute C_RSTRAM_A : integer; attribute C_RSTRAM_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_RSTRAM_B : integer; attribute C_RSTRAM_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_RST_PRIORITY_A : string; attribute C_RST_PRIORITY_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "CE"; attribute C_RST_PRIORITY_B : string; attribute C_RST_PRIORITY_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "CE"; attribute C_SIM_COLLISION_CHECK : string; attribute C_SIM_COLLISION_CHECK of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "ALL"; attribute C_USE_BRAM_BLOCK : integer; attribute C_USE_BRAM_BLOCK of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_USE_BYTE_WEA : integer; attribute C_USE_BYTE_WEA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1; attribute C_USE_BYTE_WEB : integer; attribute C_USE_BYTE_WEB of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1; attribute C_USE_DEFAULT_DATA : integer; attribute C_USE_DEFAULT_DATA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_USE_ECC : integer; attribute C_USE_ECC of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_USE_SOFTECC : integer; attribute C_USE_SOFTECC of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_USE_URAM : integer; attribute C_USE_URAM of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_WEA_WIDTH : integer; attribute C_WEA_WIDTH of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1; attribute C_WEB_WIDTH : integer; attribute C_WEB_WIDTH of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1; attribute C_WRITE_DEPTH_A : integer; attribute C_WRITE_DEPTH_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 10240; attribute C_WRITE_DEPTH_B : integer; attribute C_WRITE_DEPTH_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 10240; attribute C_WRITE_MODE_A : string; attribute C_WRITE_MODE_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "WRITE_FIRST"; attribute C_WRITE_MODE_B : string; attribute C_WRITE_MODE_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "WRITE_FIRST"; attribute C_WRITE_WIDTH_A : integer; attribute C_WRITE_WIDTH_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 8; attribute C_WRITE_WIDTH_B : integer; attribute C_WRITE_WIDTH_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 8; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "artix7"; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "blk_mem_gen_v8_3_1"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "yes"; end FrameBuffer_blk_mem_gen_v8_3_1; architecture STRUCTURE of FrameBuffer_blk_mem_gen_v8_3_1 is signal \<const0>\ : STD_LOGIC; begin dbiterr <= \<const0>\; rdaddrecc(13) <= \<const0>\; rdaddrecc(12) <= \<const0>\; rdaddrecc(11) <= \<const0>\; rdaddrecc(10) <= \<const0>\; rdaddrecc(9) <= \<const0>\; rdaddrecc(8) <= \<const0>\; rdaddrecc(7) <= \<const0>\; rdaddrecc(6) <= \<const0>\; rdaddrecc(5) <= \<const0>\; rdaddrecc(4) <= \<const0>\; rdaddrecc(3) <= \<const0>\; rdaddrecc(2) <= \<const0>\; rdaddrecc(1) <= \<const0>\; rdaddrecc(0) <= \<const0>\; rsta_busy <= \<const0>\; rstb_busy <= \<const0>\; s_axi_arready <= \<const0>\; s_axi_awready <= \<const0>\; s_axi_bid(3) <= \<const0>\; s_axi_bid(2) <= \<const0>\; s_axi_bid(1) <= \<const0>\; s_axi_bid(0) <= \<const0>\; s_axi_bresp(1) <= \<const0>\; s_axi_bresp(0) <= \<const0>\; s_axi_bvalid <= \<const0>\; s_axi_dbiterr <= \<const0>\; s_axi_rdaddrecc(13) <= \<const0>\; s_axi_rdaddrecc(12) <= \<const0>\; s_axi_rdaddrecc(11) <= \<const0>\; s_axi_rdaddrecc(10) <= \<const0>\; s_axi_rdaddrecc(9) <= \<const0>\; s_axi_rdaddrecc(8) <= \<const0>\; s_axi_rdaddrecc(7) <= \<const0>\; s_axi_rdaddrecc(6) <= \<const0>\; s_axi_rdaddrecc(5) <= \<const0>\; s_axi_rdaddrecc(4) <= \<const0>\; s_axi_rdaddrecc(3) <= \<const0>\; s_axi_rdaddrecc(2) <= \<const0>\; s_axi_rdaddrecc(1) <= \<const0>\; s_axi_rdaddrecc(0) <= \<const0>\; s_axi_rdata(7) <= \<const0>\; s_axi_rdata(6) <= \<const0>\; s_axi_rdata(5) <= \<const0>\; s_axi_rdata(4) <= \<const0>\; s_axi_rdata(3) <= \<const0>\; s_axi_rdata(2) <= \<const0>\; s_axi_rdata(1) <= \<const0>\; s_axi_rdata(0) <= \<const0>\; s_axi_rid(3) <= \<const0>\; s_axi_rid(2) <= \<const0>\; s_axi_rid(1) <= \<const0>\; s_axi_rid(0) <= \<const0>\; s_axi_rlast <= \<const0>\; s_axi_rresp(1) <= \<const0>\; s_axi_rresp(0) <= \<const0>\; s_axi_rvalid <= \<const0>\; s_axi_sbiterr <= \<const0>\; s_axi_wready <= \<const0>\; sbiterr <= \<const0>\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); inst_blk_mem_gen: entity work.FrameBuffer_blk_mem_gen_v8_3_1_synth port map ( addra(13 downto 0) => addra(13 downto 0), addrb(13 downto 0) => addrb(13 downto 0), clka => clka, clkb => clkb, dina(7 downto 0) => dina(7 downto 0), dinb(7 downto 0) => dinb(7 downto 0), douta(7 downto 0) => douta(7 downto 0), doutb(7 downto 0) => doutb(7 downto 0), ena => ena, wea(0) => wea(0), web(0) => web(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity FrameBuffer is port ( clka : in STD_LOGIC; ena : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); douta : out STD_LOGIC_VECTOR ( 7 downto 0 ); clkb : in STD_LOGIC; web : in STD_LOGIC_VECTOR ( 0 to 0 ); addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 7 downto 0 ); doutb : out STD_LOGIC_VECTOR ( 7 downto 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of FrameBuffer : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of FrameBuffer : entity is "FrameBuffer,blk_mem_gen_v8_3_1,{}"; attribute core_generation_info : string; attribute core_generation_info of FrameBuffer : entity is "FrameBuffer,blk_mem_gen_v8_3_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=2,C_BYTE_SIZE=8,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=FrameBuffer.mif,C_INIT_FILE=FrameBuffer.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=1,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=10240,C_READ_DEPTH_A=10240,C_ADDRA_WIDTH=14,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=1,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=10240,C_READ_DEPTH_B=10240,C_ADDRB_WIDTH=14,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=1,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=2,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 4.61856 mW}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of FrameBuffer : entity is "yes"; attribute x_core_info : string; attribute x_core_info of FrameBuffer : entity is "blk_mem_gen_v8_3_1,Vivado 2015.4"; end FrameBuffer; architecture STRUCTURE of FrameBuffer is signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC; signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC; signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 ); signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 ); signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute C_ADDRA_WIDTH : integer; attribute C_ADDRA_WIDTH of U0 : label is 14; attribute C_ADDRB_WIDTH : integer; attribute C_ADDRB_WIDTH of U0 : label is 14; attribute C_ALGORITHM : integer; attribute C_ALGORITHM of U0 : label is 1; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of U0 : label is 4; attribute C_AXI_SLAVE_TYPE : integer; attribute C_AXI_SLAVE_TYPE of U0 : label is 0; attribute C_AXI_TYPE : integer; attribute C_AXI_TYPE of U0 : label is 1; attribute C_BYTE_SIZE : integer; attribute C_BYTE_SIZE of U0 : label is 8; attribute C_COMMON_CLK : integer; attribute C_COMMON_CLK of U0 : label is 0; attribute C_COUNT_18K_BRAM : string; attribute C_COUNT_18K_BRAM of U0 : label is "1"; attribute C_COUNT_36K_BRAM : string; attribute C_COUNT_36K_BRAM of U0 : label is "2"; attribute C_CTRL_ECC_ALGO : string; attribute C_CTRL_ECC_ALGO of U0 : label is "NONE"; attribute C_DEFAULT_DATA : string; attribute C_DEFAULT_DATA of U0 : label is "0"; attribute C_DISABLE_WARN_BHV_COLL : integer; attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0; attribute C_DISABLE_WARN_BHV_RANGE : integer; attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0; attribute C_ELABORATION_DIR : string; attribute C_ELABORATION_DIR of U0 : label is "./"; attribute C_ENABLE_32BIT_ADDRESS : integer; attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0; attribute C_EN_DEEPSLEEP_PIN : integer; attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0; attribute C_EN_ECC_PIPE : integer; attribute C_EN_ECC_PIPE of U0 : label is 0; attribute C_EN_RDADDRA_CHG : integer; attribute C_EN_RDADDRA_CHG of U0 : label is 0; attribute C_EN_RDADDRB_CHG : integer; attribute C_EN_RDADDRB_CHG of U0 : label is 0; attribute C_EN_SAFETY_CKT : integer; attribute C_EN_SAFETY_CKT of U0 : label is 0; attribute C_EN_SHUTDOWN_PIN : integer; attribute C_EN_SHUTDOWN_PIN of U0 : label is 0; attribute C_EN_SLEEP_PIN : integer; attribute C_EN_SLEEP_PIN of U0 : label is 0; attribute C_EST_POWER_SUMMARY : string; attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 4.61856 mW"; attribute C_FAMILY : string; attribute C_FAMILY of U0 : label is "artix7"; attribute C_HAS_AXI_ID : integer; attribute C_HAS_AXI_ID of U0 : label is 0; attribute C_HAS_ENA : integer; attribute C_HAS_ENA of U0 : label is 1; attribute C_HAS_ENB : integer; attribute C_HAS_ENB of U0 : label is 0; attribute C_HAS_INJECTERR : integer; attribute C_HAS_INJECTERR of U0 : label is 0; attribute C_HAS_MEM_OUTPUT_REGS_A : integer; attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0; attribute C_HAS_MEM_OUTPUT_REGS_B : integer; attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 1; attribute C_HAS_MUX_OUTPUT_REGS_A : integer; attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0; attribute C_HAS_MUX_OUTPUT_REGS_B : integer; attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0; attribute C_HAS_REGCEA : integer; attribute C_HAS_REGCEA of U0 : label is 0; attribute C_HAS_REGCEB : integer; attribute C_HAS_REGCEB of U0 : label is 0; attribute C_HAS_RSTA : integer; attribute C_HAS_RSTA of U0 : label is 0; attribute C_HAS_RSTB : integer; attribute C_HAS_RSTB of U0 : label is 0; attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0; attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0; attribute C_INITA_VAL : string; attribute C_INITA_VAL of U0 : label is "0"; attribute C_INITB_VAL : string; attribute C_INITB_VAL of U0 : label is "0"; attribute C_INIT_FILE : string; attribute C_INIT_FILE of U0 : label is "FrameBuffer.mem"; attribute C_INIT_FILE_NAME : string; attribute C_INIT_FILE_NAME of U0 : label is "FrameBuffer.mif"; attribute C_INTERFACE_TYPE : integer; attribute C_INTERFACE_TYPE of U0 : label is 0; attribute C_LOAD_INIT_FILE : integer; attribute C_LOAD_INIT_FILE of U0 : label is 1; attribute C_MEM_TYPE : integer; attribute C_MEM_TYPE of U0 : label is 2; attribute C_MUX_PIPELINE_STAGES : integer; attribute C_MUX_PIPELINE_STAGES of U0 : label is 0; attribute C_PRIM_TYPE : integer; attribute C_PRIM_TYPE of U0 : label is 1; attribute C_READ_DEPTH_A : integer; attribute C_READ_DEPTH_A of U0 : label is 10240; attribute C_READ_DEPTH_B : integer; attribute C_READ_DEPTH_B of U0 : label is 10240; attribute C_READ_WIDTH_A : integer; attribute C_READ_WIDTH_A of U0 : label is 8; attribute C_READ_WIDTH_B : integer; attribute C_READ_WIDTH_B of U0 : label is 8; attribute C_RSTRAM_A : integer; attribute C_RSTRAM_A of U0 : label is 0; attribute C_RSTRAM_B : integer; attribute C_RSTRAM_B of U0 : label is 0; attribute C_RST_PRIORITY_A : string; attribute C_RST_PRIORITY_A of U0 : label is "CE"; attribute C_RST_PRIORITY_B : string; attribute C_RST_PRIORITY_B of U0 : label is "CE"; attribute C_SIM_COLLISION_CHECK : string; attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL"; attribute C_USE_BRAM_BLOCK : integer; attribute C_USE_BRAM_BLOCK of U0 : label is 0; attribute C_USE_BYTE_WEA : integer; attribute C_USE_BYTE_WEA of U0 : label is 1; attribute C_USE_BYTE_WEB : integer; attribute C_USE_BYTE_WEB of U0 : label is 1; attribute C_USE_DEFAULT_DATA : integer; attribute C_USE_DEFAULT_DATA of U0 : label is 0; attribute C_USE_ECC : integer; attribute C_USE_ECC of U0 : label is 0; attribute C_USE_SOFTECC : integer; attribute C_USE_SOFTECC of U0 : label is 0; attribute C_USE_URAM : integer; attribute C_USE_URAM of U0 : label is 0; attribute C_WEA_WIDTH : integer; attribute C_WEA_WIDTH of U0 : label is 1; attribute C_WEB_WIDTH : integer; attribute C_WEB_WIDTH of U0 : label is 1; attribute C_WRITE_DEPTH_A : integer; attribute C_WRITE_DEPTH_A of U0 : label is 10240; attribute C_WRITE_DEPTH_B : integer; attribute C_WRITE_DEPTH_B of U0 : label is 10240; attribute C_WRITE_MODE_A : string; attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST"; attribute C_WRITE_MODE_B : string; attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST"; attribute C_WRITE_WIDTH_A : integer; attribute C_WRITE_WIDTH_A of U0 : label is 8; attribute C_WRITE_WIDTH_B : integer; attribute C_WRITE_WIDTH_B of U0 : label is 8; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of U0 : label is "artix7"; attribute DONT_TOUCH : boolean; attribute DONT_TOUCH of U0 : label is std.standard.true; attribute downgradeipidentifiedwarnings of U0 : label is "yes"; begin U0: entity work.FrameBuffer_blk_mem_gen_v8_3_1 port map ( addra(13 downto 0) => addra(13 downto 0), addrb(13 downto 0) => addrb(13 downto 0), clka => clka, clkb => clkb, dbiterr => NLW_U0_dbiterr_UNCONNECTED, deepsleep => '0', dina(7 downto 0) => dina(7 downto 0), dinb(7 downto 0) => dinb(7 downto 0), douta(7 downto 0) => douta(7 downto 0), doutb(7 downto 0) => doutb(7 downto 0), eccpipece => '0', ena => ena, enb => '0', injectdbiterr => '0', injectsbiterr => '0', rdaddrecc(13 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(13 downto 0), regcea => '0', regceb => '0', rsta => '0', rsta_busy => NLW_U0_rsta_busy_UNCONNECTED, rstb => '0', rstb_busy => NLW_U0_rstb_busy_UNCONNECTED, s_aclk => '0', s_aresetn => '0', s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000", s_axi_arburst(1 downto 0) => B"00", s_axi_arid(3 downto 0) => B"0000", s_axi_arlen(7 downto 0) => B"00000000", s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED, s_axi_arsize(2 downto 0) => B"000", s_axi_arvalid => '0', s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000", s_axi_awburst(1 downto 0) => B"00", s_axi_awid(3 downto 0) => B"0000", s_axi_awlen(7 downto 0) => B"00000000", s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED, s_axi_awsize(2 downto 0) => B"000", s_axi_awvalid => '0', s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0), s_axi_bready => '0', s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0), s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED, s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED, s_axi_injectdbiterr => '0', s_axi_injectsbiterr => '0', s_axi_rdaddrecc(13 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(13 downto 0), s_axi_rdata(7 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(7 downto 0), s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0), s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED, s_axi_rready => '0', s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0), s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED, s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED, s_axi_wdata(7 downto 0) => B"00000000", s_axi_wlast => '0', s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED, s_axi_wstrb(0) => '0', s_axi_wvalid => '0', sbiterr => NLW_U0_sbiterr_UNCONNECTED, shutdown => '0', sleep => '0', wea(0) => wea(0), web(0) => web(0) ); end STRUCTURE;	mit
huahu/zenturio-editor	public/vendor/ace-builds/kitchen-sink/docs/vhdl.vhd	472	830	library IEEE user IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity COUNT16 is port ( cOut :out std_logic_vector(15 downto 0); -- counter output clkEn :in std_logic; -- count enable clk :in std_logic; -- clock input rst :in std_logic -- reset input ); end entity; architecture count_rtl of COUNT16 is signal count :std_logic_vector (15 downto 0); begin process (clk, rst) begin if(rst = '1') then count <= (others=>'0'); elsif(rising_edge(clk)) then if(clkEn = '1') then count <= count + 1; end if; end if; end process; cOut <= count; end architecture;	mit
whitef0x0/EECE353-Lab5	drawline.vhd	1	4263	library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity drawline is port(CLK : in std_logic; RST : in std_logic; DRAW : in std_logic x_start : in std_logic_vector(7 downto 0); y_start : in std_logic_vector(7 downto 0); x_end : in std_logic_vector(7 downto 0); y_end : in std_logic_vector(7 downto 0); line_color : in std_logic_vector(2 downto 0); VGA_R, VGA_G, VGA_B : out std_logic_vector(9 downto 0); -- The outs go to VGA controller VGA_HS : out std_logic; VGA_VS : out std_logic; VGA_BLANK : out std_logic; VGA_SYNC : out std_logic; VGA_CLK : out std_logic); end drawline; architecture rtl of drawline is -- Component from the Verilog file: vga_adapter.v component vga_adapter generic(RESOLUTION : string); port ( resetn : in std_logic; clock : in std_logic; colour : in std_logic_vector(2 downto 0); x : in std_logic_vector(7 downto 0); y : in std_logic_vector(6 downto 0); plot : in std_logic; VGA_R, VGA_G, VGA_B : out std_logic_vector(9 downto 0); VGA_HS, VGA_VS, VGA_BLANK, VGA_SYNC, VGA_CLK : out std_logic); end component; component fsm_line is PORT ( clock : IN STD_LOGIC; resetb : IN STD_LOGIC; xdone, ydone, ldone : IN STD_LOGIC; sw : IN STD_LOGIC_VECTOR(17 downto 0); draw : IN STD_LOGIC; resetx, resety, incr_y, incr_x, plot, initl, drawl : OUT STD_LOGIC; colour : OUT STD_LOGIC_VECTOR(2 downto 0); x : OUT STD_LOGIC_VECTOR(7 downto 0); y : OUT STD_LOGIC_VECTOR(6 downto 0); ledg : OUT STD_LOGIC_VECTOR(7 downto 0) ); end component; component datapath_line is PORT ( clock : IN STD_LOGIC; resetb : IN STD_LOGIC; resetx, resety, incr_y, incr_x, initl, drawl : IN STD_LOGIC; x : OUT STD_LOGIC_VECTOR(7 downto 0); y : OUT STD_LOGIC_VECTOR(6 downto 0); x0in : IN STD_LOGIC_VECTOR(7 downto 0); -- x1 y0in : IN STD_LOGIC_VECTOR(6 downto 0); -- y1 x1in : IN STD_LOGIC_VECTOR(7 downto 0); -- x0 y1in : IN STD_LOGIC_VECTOR(6 downto 0); -- y0 xdone, ydone, ldone : OUT STD_LOGIC ); end component; signal s_x : std_logic_vector(7 downto 0) := "00000000"; signal s_y : std_logic_vector(6 downto 0) := "0000000"; signal colour : std_logic_vector(2 downto 0); signal plot : std_logic; signal resety, resetx, initl : std_logic; signal xdone, ydone, ldone : std_logic; signal incr_y, incr_x, drawl : std_logic; signal x_int : std_logic_vector(7 downto 0); signal y_int : std_logic_vector(6 downto 0); begin vga_u0 : vga_adapter generic map(RESOLUTION => "160x120") port map(resetn => RST, clock => CLK, colour => colour, x => s_x, y => s_y, plot => plot, VGA_R => VGA_R, VGA_G => VGA_G, VGA_B => VGA_B, VGA_HS => VGA_HS, VGA_VS => VGA_VS, VGA_BLANK => VGA_BLANK, VGA_SYNC => VGA_SYNC, VGA_CLK => VGA_CLK ); fsm_line0 : fsm_line PORT MAP( clock => CLK, resetb => RST, xdone => xdone, ydone => ydone, ldone => ldone, --sw => SW, draw => DRAW, resetx => resetx, resety => resety, incr_y => incr_y, incr_x => incr_x, plot => plot, initl => initl, drawl => drawl, colour_in => line_color, colour_out => colour, x => x_int, y => y_int, ); datapath_line0 : datapath_line PORT MAP( clock => CLK, resetb => RST, resetx => resetx, resety => resety, initl => initl, drawl => drawl, x => s_x, y => s_y, xin => x_int, yin => y_int, xdone => xdone, ydone => ydone, ldone => ldone, incr_y => incr_y, incr_x => incr_x ); end rtl;	mit
oetr/FPGA-I2C-Slave	txt_util.vhd	4	14508	library ieee; use ieee.std_logic_1164.all; use std.textio.all; package txt_util is -- prints a message to the screen procedure print(text: string); -- prints the message when active -- useful for debug switches procedure print(active: boolean; text: string); -- converts std_logic into a character function chr(sl: std_logic) return character; -- converts std_logic into a string (1 to 1) function str(sl: std_logic) return string; -- converts std_logic_vector into a string (binary base) function str(slv: std_logic_vector) return string; -- converts boolean into a string function str(b: boolean) return string; -- converts an integer into a single character -- (can also be used for hex conversion and other bases) function chr(int: integer) return character; -- converts integer into string using specified base function str(int: integer; base: integer) return string; -- converts integer to string, using base 10 function str(int: integer) return string; -- convert std_logic_vector into a string in hex format function hstr(slv: std_logic_vector) return string; -- functions to manipulate strings ----------------------------------- -- convert a character to upper case function to_upper(c: character) return character; -- convert a character to lower case function to_lower(c: character) return character; -- convert a string to upper case function to_upper(s: string) return string; -- convert a string to lower case function to_lower(s: string) return string; -- functions to convert strings into other formats -------------------------------------------------- -- converts a character into std_logic function to_std_logic(c: character) return std_logic; -- converts a string into std_logic_vector function to_std_logic_vector(s: string) return std_logic_vector; -- file I/O ----------- -- read variable length string from input file procedure str_read(file in_file: TEXT; res_string: out string); -- print string to a file and start new line procedure print(file out_file: TEXT; new_string: in string); -- print character to a file and start new line procedure print(file out_file: TEXT; char: in character); end txt_util; package body txt_util is -- prints text to the screen procedure print(text: string) is variable msg_line: line; begin write(msg_line, text); writeline(output, msg_line); end print; -- prints text to the screen when active procedure print(active: boolean; text: string) is begin if active then print(text); end if; end print; -- converts std_logic into a character function chr(sl: std_logic) return character is variable c: character; begin case sl is when 'U' => c:= 'U'; when 'X' => c:= 'X'; when '0' => c:= '0'; when '1' => c:= '1'; when 'Z' => c:= 'Z'; when 'W' => c:= 'W'; when 'L' => c:= 'L'; when 'H' => c:= 'H'; when '-' => c:= '-'; end case; return c; end chr; -- converts std_logic into a string (1 to 1) function str(sl: std_logic) return string is variable s: string(1 to 1); begin s(1) := chr(sl); return s; end str; -- converts std_logic_vector into a string (binary base) -- (this also takes care of the fact that the range of -- a string is natural while a std_logic_vector may -- have an integer range) function str(slv: std_logic_vector) return string is variable result : string (1 to slv'length); variable r : integer; begin r := 1; for i in slv'range loop result(r) := chr(slv(i)); r := r + 1; end loop; return result; end str; function str(b: boolean) return string is begin if b then return "true"; else return "false"; end if; end str; -- converts an integer into a character -- for 0 to 9 the obvious mapping is used, higher -- values are mapped to the characters A-Z -- (this is usefull for systems with base > 10) -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) function chr(int: integer) return character is variable c: character; begin case int is when 0 => c := '0'; when 1 => c := '1'; when 2 => c := '2'; when 3 => c := '3'; when 4 => c := '4'; when 5 => c := '5'; when 6 => c := '6'; when 7 => c := '7'; when 8 => c := '8'; when 9 => c := '9'; when 10 => c := 'A'; when 11 => c := 'B'; when 12 => c := 'C'; when 13 => c := 'D'; when 14 => c := 'E'; when 15 => c := 'F'; when 16 => c := 'G'; when 17 => c := 'H'; when 18 => c := 'I'; when 19 => c := 'J'; when 20 => c := 'K'; when 21 => c := 'L'; when 22 => c := 'M'; when 23 => c := 'N'; when 24 => c := 'O'; when 25 => c := 'P'; when 26 => c := 'Q'; when 27 => c := 'R'; when 28 => c := 'S'; when 29 => c := 'T'; when 30 => c := 'U'; when 31 => c := 'V'; when 32 => c := 'W'; when 33 => c := 'X'; when 34 => c := 'Y'; when 35 => c := 'Z'; when others => c := '?'; end case; return c; end chr; -- convert integer to string using specified base -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) function str(int: integer; base: integer) return string is variable temp: string(1 to 10); variable num: integer; variable abs_int: integer; variable len: integer := 1; variable power: integer := 1; begin -- bug fix for negative numbers abs_int := abs(int); num := abs_int; while num >= base loop -- Determine how many len := len + 1; -- characters required num := num / base; -- to represent the end loop ; -- number. for i in len downto 1 loop -- Convert the number to temp(i) := chr(abs_int/power mod base); -- a string starting power := power * base; -- with the right hand end loop ; -- side. -- return result and add sign if required if int < 0 then return '-'& temp(1 to len); else return temp(1 to len); end if; end str; -- convert integer to string, using base 10 function str(int: integer) return string is begin return str(int, 10) ; end str; -- converts a std_logic_vector into a hex string. function hstr(slv: std_logic_vector) return string is variable hexlen: integer; variable longslv : std_logic_vector(67 downto 0) := (others => '0'); variable hex : string(1 to 16); variable fourbit : std_logic_vector(3 downto 0); begin hexlen := (slv'left+1)/4; if (slv'left+1) mod 4 /= 0 then hexlen := hexlen + 1; end if; longslv(slv'left downto 0) := slv; for i in (hexlen -1) downto 0 loop fourbit := longslv(((i4)+3) downto (i4)); case fourbit is when "0000" => hex(hexlen -I) := '0'; when "0001" => hex(hexlen -I) := '1'; when "0010" => hex(hexlen -I) := '2'; when "0011" => hex(hexlen -I) := '3'; when "0100" => hex(hexlen -I) := '4'; when "0101" => hex(hexlen -I) := '5'; when "0110" => hex(hexlen -I) := '6'; when "0111" => hex(hexlen -I) := '7'; when "1000" => hex(hexlen -I) := '8'; when "1001" => hex(hexlen -I) := '9'; when "1010" => hex(hexlen -I) := 'A'; when "1011" => hex(hexlen -I) := 'B'; when "1100" => hex(hexlen -I) := 'C'; when "1101" => hex(hexlen -I) := 'D'; when "1110" => hex(hexlen -I) := 'E'; when "1111" => hex(hexlen -I) := 'F'; when "ZZZZ" => hex(hexlen -I) := 'z'; when "UUUU" => hex(hexlen -I) := 'u'; when "XXXX" => hex(hexlen -I) := 'x'; when others => hex(hexlen -I) := '?'; end case; end loop; return hex(1 to hexlen); end hstr; -- functions to manipulate strings ----------------------------------- -- convert a character to upper case function to_upper(c: character) return character is variable u: character; begin case c is when 'a' => u := 'A'; when 'b' => u := 'B'; when 'c' => u := 'C'; when 'd' => u := 'D'; when 'e' => u := 'E'; when 'f' => u := 'F'; when 'g' => u := 'G'; when 'h' => u := 'H'; when 'i' => u := 'I'; when 'j' => u := 'J'; when 'k' => u := 'K'; when 'l' => u := 'L'; when 'm' => u := 'M'; when 'n' => u := 'N'; when 'o' => u := 'O'; when 'p' => u := 'P'; when 'q' => u := 'Q'; when 'r' => u := 'R'; when 's' => u := 'S'; when 't' => u := 'T'; when 'u' => u := 'U'; when 'v' => u := 'V'; when 'w' => u := 'W'; when 'x' => u := 'X'; when 'y' => u := 'Y'; when 'z' => u := 'Z'; when others => u := c; end case; return u; end to_upper; -- convert a character to lower case function to_lower(c: character) return character is variable l: character; begin case c is when 'A' => l := 'a'; when 'B' => l := 'b'; when 'C' => l := 'c'; when 'D' => l := 'd'; when 'E' => l := 'e'; when 'F' => l := 'f'; when 'G' => l := 'g'; when 'H' => l := 'h'; when 'I' => l := 'i'; when 'J' => l := 'j'; when 'K' => l := 'k'; when 'L' => l := 'l'; when 'M' => l := 'm'; when 'N' => l := 'n'; when 'O' => l := 'o'; when 'P' => l := 'p'; when 'Q' => l := 'q'; when 'R' => l := 'r'; when 'S' => l := 's'; when 'T' => l := 't'; when 'U' => l := 'u'; when 'V' => l := 'v'; when 'W' => l := 'w'; when 'X' => l := 'x'; when 'Y' => l := 'y'; when 'Z' => l := 'z'; when others => l := c; end case; return l; end to_lower; -- convert a string to upper case function to_upper(s: string) return string is variable uppercase: string (s'range); begin for i in s'range loop uppercase(i):= to_upper(s(i)); end loop; return uppercase; end to_upper; -- convert a string to lower case function to_lower(s: string) return string is variable lowercase: string (s'range); begin for i in s'range loop lowercase(i):= to_lower(s(i)); end loop; return lowercase; end to_lower; -- functions to convert strings into other types -- converts a character into a std_logic function to_std_logic(c: character) return std_logic is variable sl: std_logic; begin case c is when 'U' => sl := 'U'; when 'X' => sl := 'X'; when '0' => sl := '0'; when '1' => sl := '1'; when 'Z' => sl := 'Z'; when 'W' => sl := 'W'; when 'L' => sl := 'L'; when 'H' => sl := 'H'; when '-' => sl := '-'; when others => sl := 'X'; end case; return sl; end to_std_logic; -- converts a string into std_logic_vector function to_std_logic_vector(s: string) return std_logic_vector is variable slv: std_logic_vector(s'high-s'low downto 0); variable k: integer; begin k := s'high-s'low; for i in s'range loop slv(k) := to_std_logic(s(i)); k := k - 1; end loop; return slv; end to_std_logic_vector; ---------------- -- file I/O -- ---------------- -- read variable length string from input file procedure str_read(file in_file: TEXT; res_string: out string) is variable l: line; variable c: character; variable is_string: boolean; begin readline(in_file, l); -- clear the contents of the result string for i in res_string'range loop res_string(i) := ' '; end loop; -- read all characters of the line, up to the length -- of the results string for i in res_string'range loop read(l, c, is_string); res_string(i) := c; if not is_string then -- found end of line exit; end if; end loop; end str_read; -- print string to a file procedure print(file out_file: TEXT; new_string: in string) is variable l: line; begin write(l, new_string); writeline(out_file, l); end print; -- print character to a file and start new line procedure print(file out_file: TEXT; char: in character) is variable l: line; begin write(l, char); writeline(out_file, l); end print; -- appends contents of a string to a file until line feed occurs -- (LF is considered to be the end of the string) procedure str_write(file out_file: TEXT; new_string: in string) is begin for i in new_string'range loop print(out_file, new_string(i)); if new_string(i) = LF then -- end of string exit; end if; end loop; end str_write; end txt_util;	mit
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whitef0x0/EECE353-Lab5	lab5.vhd	1	630	library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity lab5 is port(CLOCK_50 : in std_logic; KEY : in std_logic_vector(3 downto 0); SW : in std_logic_vector(17 downto 0); VGA_R, VGA_G, VGA_B : out std_logic_vector(9 downto 0); -- The outs go to VGA controller VGA_HS : out std_logic; VGA_VS : out std_logic; VGA_BLANK : out std_logic; VGA_SYNC : out std_logic; VGA_CLK : out std_logic); end lab5; architecture RTL of lab5 is begin end RTL;	mit
oetr/FPGA-I2C-Slave	debounce.vhd	1	2024	------------------------------------------------------------ -- File : debounce.vhd ------------------------------------------------------------ -- Author : Peter Samarin <[email protected]> ------------------------------------------------------------ -- Copyright (c) 2019 Peter Samarin ------------------------------------------------------------ -- Description: debouncing circuit that forwards only -- signals that have been stable for the whole duration of -- the counter ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ------------------------------------------------------------ entity debounce is generic ( WAIT_CYCLES : integer := 5); port ( signal_in : in std_logic; signal_out : out std_logic; clk : in std_logic); end entity debounce; ------------------------------------------------------------ architecture arch of debounce is type state_t is (idle, check_input_stable); signal state_reg : state_t := idle; signal out_reg : std_logic := signal_in; signal signal_in_reg : std_logic; signal counter : integer range 0 to WAIT_CYCLES-1 := 0; begin process (clk) is begin if rising_edge(clk) then case state_reg is when idle => if out_reg /= signal_in then signal_in_reg <= signal_in; state_reg <= check_input_stable; counter <= WAIT_CYCLES-1; end if; when check_input_stable => if counter = 0 then if signal_in = signal_in_reg then out_reg <= signal_in; end if; state_reg <= idle; else if signal_in /= signal_in_reg then state_reg <= idle; end if; counter <= counter - 1; end if; end case; end if; end process; -- output signal_out <= out_reg; end architecture arch;	mit
dries007/Basys3	FPGA-Z/FPGA-Z.srcs/sim_2/new/test2.vhd	1	874	library IEEE; use IEEE.STD_LOGIC_1164.ALL; use work.Font.all; use ieee.std_logic_textio.all; use std.textio.all; entity test2 is end test2; architecture Behavioral of test2 is begin process variable output : boolean; variable y : integer; variable x : integer; file outfile : text is out "out.txt"; --declare output file variable outline : line; --line number declaration begin for yl in 0 to 15 loop for xl in 0 to 7 loop x := xl; y := yl; output := draw_char(xl, yl, 33); if output then write(outline, string'("1")); else write(outline, string'("0")); end if; wait for 1ps; end loop; writeline(outfile, outline); end loop; writeline(outfile, outline); end process; end Behavioral;	mit
dries007/Basys3	VGA_text/VGA_text.srcs/sources_1/new/Vga.vhd	1	3873	library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; use ieee.math_real.all; use work.Font.all; -- Information from http://tinyvga.com/vga-timing/1280x1024@60Hz entity Vga is Generic ( H_PIX : integer := 1280; -- Horizontal frame size H_FP : integer := 48; -- Horizontal Front Porch H_SY : integer := 112; -- Horizontal Sync H_BP : integer := 248; -- Horizontal Back Porch H_POL : std_logic := '1'; -- Horizontal Sync Polarity V_PIX : integer := 1024; -- Vertical frame size V_FP : integer := 1; -- Vertical Front Porch V_SY : integer := 3; -- Vertical Sync V_BP : integer := 36; -- Vertical Back Porch V_POL : std_logic := '1' -- Vertical Sync Polarity ); Port ( clk : in std_logic; hSync : out std_logic; vSync : out std_logic; vgaRed : out std_logic_vector (3 downto 0); vgaGreen : out std_logic_vector (3 downto 0); vgaBlue : out std_logic_vector (3 downto 0); fbOutAddr : out std_logic_vector(13 downto 0); fbOutDat : in std_logic_vector(7 downto 0) ); end Vga; architecture Behavioral of Vga is constant H_MAX : integer := H_PIX + H_FP + H_SY + H_BP; -- 1688 for 1280x1024@60Hz constant V_MAX : integer := V_PIX + V_FP + V_SY + V_BP; -- 1066 for 1280x1024@60Hz -------------------------------------------------------- begin -- BEGIN -------------------------------------------------------- process(clk) variable h_count : integer range 0 to H_MAX - 1 := 0; --horizontal counter (counts the columns) variable v_count : integer range 0 to V_MAX - 1 := 0; --vertical counter (counts the rows) variable char : std_logic_vector(7 downto 0); --variable nextChar : std_logic_vector(7 downto 0); variable charX : integer range 0 to 8; variable charY : integer range 0 to 16; begin if (rising_edge(clk)) then --counters if (h_count < H_MAX - 1) then h_count := h_count + 1; else h_count := 0; if (v_count < V_MAX - 1) then v_count := v_count + 1; else v_count := 0; end if; end if; --horizontal sync signal if (h_count < H_PIX + H_FP or h_count > H_PIX + H_FP + H_SY) then hSync <= not H_POL; else hSync <= H_POL; end if; --vertical sync signal if (v_count < V_PIX + V_FP or v_count > V_PIX + V_FP + V_SY) then vSync <= not V_POL; else vSync <= V_POL; end if; --text display if (h_count < H_PIX AND v_count < V_PIX) then charX := h_count mod 8; charY := v_count mod 16; if (charX = 0) then -- Set up next character char := fbOutDat; elsif (charX = 1) then fbOutAddr <= std_logic_vector(to_unsigned(1 + (h_count / 8) + ((v_count / 16) * 160), fbOutAddr'LENGTH)); end if; -- char[7] = invert bit if (char(7) = '1' xor draw_char(charX, charY, to_integer(unsigned(char and "01111111")))) then vgaRed <= "1111"; vgaGreen <= "1111"; vgaBlue <= "1111"; else vgaRed <= "0000"; vgaGreen <= "0000"; vgaBlue <= "0000"; end if; else fbOutAddr <= std_logic_vector(to_unsigned(((v_count / 16) * 160), fbOutAddr'LENGTH)); vgaRed <= "0000"; vgaGreen <= "0000"; vgaBlue <= "0000"; end if; end if; end process; -------------------------------------------------------- end Behavioral; -- END --------------------------------------------------------	mit
dries007/Basys3	FPGA-Z/FPGA-Z.sim/sim_1/impl/func/test1_func_impl.vhd	1	420761	-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015 -- Date : Fri Apr 15 21:41:42 2016 -- Host : Dries007-Arch running 64-bit unknown -- Command : write_vhdl -mode funcsim -nolib -force -file -- /home/dries/Projects/Basys3/FPGA-Z/FPGA-Z.sim/sim_1/impl/func/test1_func_impl.vhd -- Design : top -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7a35tcpg236-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity ClockDivider_ClockDivider_clk_wiz is port ( clkIn : in STD_LOGIC; clk108M : out STD_LOGIC; clk10M : out STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of ClockDivider_ClockDivider_clk_wiz : entity is "ClockDivider_clk_wiz"; end ClockDivider_ClockDivider_clk_wiz; architecture STRUCTURE of ClockDivider_ClockDivider_clk_wiz is signal clk108M_ClockDivider : STD_LOGIC; signal clk10M_ClockDivider : STD_LOGIC; signal clkfbout_ClockDivider : STD_LOGIC; signal clkfbout_buf_ClockDivider : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_LOCKED_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); attribute BOX_TYPE : string; attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE"; attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE"; attribute BOX_TYPE of clkout2_buf : label is "PRIMITIVE"; attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE"; begin clkf_buf: unisim.vcomponents.BUFG port map ( I => clkfbout_ClockDivider, O => clkfbout_buf_ClockDivider ); clkout1_buf: unisim.vcomponents.BUFG port map ( I => clk108M_ClockDivider, O => clk108M ); clkout2_buf: unisim.vcomponents.BUFG port map ( I => clk10M_ClockDivider, O => clk10M ); mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV generic map( BANDWIDTH => "OPTIMIZED", CLKFBOUT_MULT_F => 54.000000, CLKFBOUT_PHASE => 0.000000, CLKFBOUT_USE_FINE_PS => false, CLKIN1_PERIOD => 10.000000, CLKIN2_PERIOD => 0.000000, CLKOUT0_DIVIDE_F => 10.000000, CLKOUT0_DUTY_CYCLE => 0.500000, CLKOUT0_PHASE => 0.000000, CLKOUT0_USE_FINE_PS => false, CLKOUT1_DIVIDE => 108, CLKOUT1_DUTY_CYCLE => 0.500000, CLKOUT1_PHASE => 0.000000, CLKOUT1_USE_FINE_PS => false, CLKOUT2_DIVIDE => 1, CLKOUT2_DUTY_CYCLE => 0.500000, CLKOUT2_PHASE => 0.000000, CLKOUT2_USE_FINE_PS => false, CLKOUT3_DIVIDE => 1, CLKOUT3_DUTY_CYCLE => 0.500000, CLKOUT3_PHASE => 0.000000, CLKOUT3_USE_FINE_PS => false, CLKOUT4_CASCADE => false, CLKOUT4_DIVIDE => 1, CLKOUT4_DUTY_CYCLE => 0.500000, CLKOUT4_PHASE => 0.000000, CLKOUT4_USE_FINE_PS => false, CLKOUT5_DIVIDE => 1, CLKOUT5_DUTY_CYCLE => 0.500000, CLKOUT5_PHASE => 0.000000, CLKOUT5_USE_FINE_PS => false, CLKOUT6_DIVIDE => 1, CLKOUT6_DUTY_CYCLE => 0.500000, CLKOUT6_PHASE => 0.000000, CLKOUT6_USE_FINE_PS => false, COMPENSATION => "BUF_IN", DIVCLK_DIVIDE => 5, IS_CLKINSEL_INVERTED => '0', IS_PSEN_INVERTED => '0', IS_PSINCDEC_INVERTED => '0', IS_PWRDWN_INVERTED => '0', IS_RST_INVERTED => '0', REF_JITTER1 => 0.010000, REF_JITTER2 => 0.010000, SS_EN => "FALSE", SS_MODE => "CENTER_HIGH", SS_MOD_PERIOD => 10000, STARTUP_WAIT => false ) port map ( CLKFBIN => clkfbout_buf_ClockDivider, CLKFBOUT => clkfbout_ClockDivider, CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED, CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED, CLKIN1 => clkIn, CLKIN2 => '0', CLKINSEL => '1', CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED, CLKOUT0 => clk108M_ClockDivider, CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED, CLKOUT1 => clk10M_ClockDivider, CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED, CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED, CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED, CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED, CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED, CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED, CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED, CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED, DADDR(6 downto 0) => B"0000000", DCLK => '0', DEN => '0', DI(15 downto 0) => B"0000000000000000", DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0), DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED, DWE => '0', LOCKED => NLW_mmcm_adv_inst_LOCKED_UNCONNECTED, PSCLK => '0', PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED, PSEN => '0', PSINCDEC => '0', PWRDWN => '0', RST => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \FrameBuffer_blk_mem_gen_mux__parameterized0\ is port ( doutb : out STD_LOGIC_VECTOR ( 7 downto 0 ); DOBDO : in STD_LOGIC_VECTOR ( 7 downto 0 ); \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 2 downto 0 ); clkb : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \FrameBuffer_blk_mem_gen_mux__parameterized0\ : entity is "blk_mem_gen_mux"; end \FrameBuffer_blk_mem_gen_mux__parameterized0\; architecture STRUCTURE of \FrameBuffer_blk_mem_gen_mux__parameterized0\ is signal sel_pipe : STD_LOGIC_VECTOR ( 2 downto 0 ); begin \doutb[0]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOBDO(0), I1 => sel_pipe(0), I2 => sel_pipe(1), I3 => sel_pipe(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(0), I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(0), O => doutb(0) ); \doutb[1]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOBDO(1), I1 => sel_pipe(0), I2 => sel_pipe(1), I3 => sel_pipe(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(1), I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(1), O => doutb(1) ); \doutb[2]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOBDO(2), I1 => sel_pipe(0), I2 => sel_pipe(1), I3 => sel_pipe(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(2), I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(2), O => doutb(2) ); \doutb[3]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOBDO(3), I1 => sel_pipe(0), I2 => sel_pipe(1), I3 => sel_pipe(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(3), I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(3), O => doutb(3) ); \doutb[4]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOBDO(4), I1 => sel_pipe(0), I2 => sel_pipe(1), I3 => sel_pipe(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(4), I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(4), O => doutb(4) ); \doutb[5]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOBDO(5), I1 => sel_pipe(0), I2 => sel_pipe(1), I3 => sel_pipe(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(5), I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(5), O => doutb(5) ); \doutb[6]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOBDO(6), I1 => sel_pipe(0), I2 => sel_pipe(1), I3 => sel_pipe(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(6), I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(6), O => doutb(6) ); \doutb[7]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOBDO(7), I1 => sel_pipe(0), I2 => sel_pipe(1), I3 => sel_pipe(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(7), I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(7), O => doutb(7) ); \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clkb, CE => '1', D => addrb(0), Q => sel_pipe(0), R => '0' ); \no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clkb, CE => '1', D => addrb(1), Q => sel_pipe(1), R => '0' ); \no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clkb, CE => '1', D => addrb(2), Q => sel_pipe(2), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity FrameBuffer_blk_mem_gen_prim_wrapper_init is port ( \doutb[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); clka : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init"; end FrameBuffer_blk_mem_gen_prim_wrapper_init; architecture STRUCTURE of FrameBuffer_blk_mem_gen_prim_wrapper_init is signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1_n_0\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2_n_0\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute BOX_TYPE : string; attribute BOX_TYPE of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE"; attribute CLOCK_DOMAINS : string; attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT"; attribute PWROPT_WRITE_MODE_CHANGE_A : string; attribute PWROPT_WRITE_MODE_CHANGE_A of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "READ_FIRST:NO_CHANGE_2"; begin \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1 generic map( DOA_REG => 0, DOB_REG => 0, EN_ECC_READ => false, EN_ECC_WRITE => false, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_01 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_02 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_03 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_04 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_05 => X"4646464646464646464646464646464646462020202020202020202020202020", INIT_06 => X"2020202020202020202020505050505050505050505050505050505046464646", INIT_07 => X"2041414120202020202020202020202020202047474747474747474747474747", INIT_08 => X"5A20202020202020202020202020202020202020202020202020202020202020", INIT_09 => X"20202020202020202020202020205A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A", INIT_0A => X"3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A462020202020202020202020202020", INIT_0B => X"47474720202020202020503A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A50463A3A3A", INIT_0C => X"413A3A3A412020202020202020202020202020473A3A3A3A3A3A3A3A3A3A3A3A", INIT_0D => X"5A20202020202020202020202020202020202020202020202020202020202020", INIT_0E => X"20202020202020202020202020205A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A", INIT_0F => X"3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A462020202020202020202020202020", INIT_10 => X"3A3A3A474720202020503A3A3A3A3A5050505050503A3A3A3A3A3A50463A3A3A", INIT_11 => X"3A3A3A3A3A4120202020202020202020202020473A3A3A3A3A3A3A3A3A3A3A3A", INIT_12 => X"5A20202020202020202020202020202020202020202020202020202020202041", INIT_13 => X"20202020202020202020202020205A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A", INIT_14 => X"3A4646464646464646463A3A3A3A3A3A46462020202020202020202020202020", INIT_15 => X"3A3A3A3A3A472020503A3A3A3A3A502020202020503A3A3A3A3A5050463A3A3A", INIT_16 => X"3A3A3A3A3A3A41202020202020202020202020473A3A3A3A4747474747474747", INIT_17 => X"5A2020202020202020202020202020202020202020202020202020202020413A", INIT_18 => X"2020202020202020202020202020205A3A3A3A3A3A5A5A5A5A5A5A5A5A3A3A3A", INIT_19 => X"464620202020202020463A3A3A3A3A4620202020202020202020202020202020", INIT_1A => X"473A3A3A3A3A4720503A3A3A3A3A502020202020503A3A3A3A50202046464646", INIT_1B => X"3A3A3A3A3A3A3A41202020202020202020202047474747474720202020202020", INIT_1C => X"5A20202020202020202020202020202020202020202020202020202020413A3A", INIT_1D => X"202020202020202020202020202020205A3A3A3A3A3A5A20202020205A5A5A5A", INIT_1E => X"202020202020202020463A3A3A3A3A4620202020202020202020202020202020", INIT_1F => X"20473A3A3A3A3A47503A3A3A3A3A502020202020503A3A3A3A50202020202020", INIT_20 => X"3A3A413A3A3A3A3A412020202020202020202020202020202020202020202020", INIT_21 => X"20202020202020202020202020202020202020202020202020202020413A3A3A", INIT_22 => X"2020202020202020202020202020202020205A3A3A3A3A3A5A20202020202020", INIT_23 => X"4646464646464646463A3A3A3A3A3A4620202020202020202020202020202020", INIT_24 => X"20473A3A3A3A3A4720503A3A3A3A3A5050505050503A3A3A3A50202020202046", INIT_25 => X"3A4120413A3A3A3A3A4120202020202020202020202020202020202020202020", INIT_26 => X"202020202020202020202020202020202020202020202020202020413A3A3A3A", INIT_27 => X"202020202020202020202020202020202020205A3A3A3A3A3A5A202020202020", INIT_28 => X"3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A4620202020202020202020202020202020", INIT_29 => X"20473A3A3A3A3A47202050503A3A3A3A3A3A3A3A3A3A3A3A3A50202020202046", INIT_2A => X"41202020413A3A3A3A3A41202020202020202047474747474747474747202020", INIT_2B => X"20202D2D2D2D2D2D2D2D2D2D2D2D2D2D2D202020202020202020413A3A3A3A3A", INIT_2C => X"20202020202020202020202020202020202020205A3A3A3A3A3A5A2020202020", INIT_2D => X"3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A4620202020202020202020202020202020", INIT_2E => X"20473A3A3A3A3A47202020205050505050505050503A3A3A3A50202020202046", INIT_2F => X"2020202020413A3A3A3A3A4120202020202020473A3A3A3A3A3A3A3A47202020", INIT_30 => X"20202D3A3A3A3A3A3A3A3A3A3A3A3A3A2D2020202020202020413A3A3A3A3A41", INIT_31 => X"2020202020202020202020202020202020202020205A3A3A3A3A3A5A20202020", INIT_32 => X"4646464646464646463A3A3A3A3A3A4620202020202020202020202020202020", INIT_33 => X"20473A3A3A3A3A47202020202020202020202020503A3A3A3A50202020202046", INIT_34 => X"414141414141413A3A3A3A3A41202020202020473A3A3A3A4747474747202020", INIT_35 => X"20202D2D2D2D2D2D2D2D2D2D2D2D2D2D2D20202020202020413A3A3A3A3A4141", INIT_36 => X"202020202020202020202020202020202020202020205A3A3A3A3A3A5A202020", INIT_37 => X"202020202020202020463A3A3A3A3A4620202020202020202020202020202020", INIT_38 => X"20473A3A3A3A3A47202020202020202020202020503A3A3A3A50202020202020", INIT_39 => X"3A3A3A3A3A3A3A3A3A3A3A3A3A412020202020473A3A3A3A4720202020202020", INIT_3A => X"2020202020202020202020202020202020202020202020413A3A3A3A3A3A3A3A", INIT_3B => X"20202020202020202020202020202020202020202020205A3A3A3A3A3A5A2020", INIT_3C => X"202020202020202020463A3A3A3A3A4620202020202020202020202020202020", INIT_3D => X"473A3A3A3A3A4720202020202020202020202020503A3A3A3A50202020202020", INIT_3E => X"4141414141414141413A3A3A3A3A4120202020473A3A3A3A4720202020202020", INIT_3F => X"5A202020202020202020202020202020202020202020413A3A3A3A3A41414141", INIT_40 => X"20202020202020202020202020205A5A5A5A5A20202020205A3A3A3A3A3A5A5A", INIT_41 => X"2020202020202046463A3A3A3A3A3A3A46462020202020202020202020202020", INIT_42 => X"3A3A3A3A3A4720202020202020202020202050503A3A3A3A3A3A505020202020", INIT_43 => X"202020202020202020413A3A3A3A3A41202020473A3A3A3A4747474747474747", INIT_44 => X"5A2020202020202020202020202020202020202020413A3A3A3A3A4120202020", INIT_45 => X"20202020202020202020202020205A3A3A3A5A5A5A5A5A5A5A5A3A3A3A3A3A3A", INIT_46 => X"2020202020202046463A3A3A3A3A3A3A3A462020202020202020202020202020", INIT_47 => X"3A3A3A474720202020202020202020202020503A3A3A3A3A3A3A3A5020202020", INIT_48 => X"20202020202020202020413A3A3A3A3A412020473A3A3A3A3A3A3A3A3A3A3A3A", INIT_49 => X"5A20202020202020202020202020202020202020413A3A3A3A3A412020202020", INIT_4A => X"20202020202020202020202020205A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A", INIT_4B => X"2020202020202046463A3A3A3A3A3A3A3A462020202020202020202020202020", INIT_4C => X"474747202020202020202020202020202020503A3A3A3A3A3A3A3A5020202020", INIT_4D => X"2020202020202020202020413A3A3A3A3A4120473A3A3A4747473A3A3A3A3A3A", INIT_4E => X"5A202020202020202020202020202020202020413A3A3A3A3A41202020202020", INIT_4F => X"20202020202020202020202020205A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A", INIT_50 => X"2020202020202046464646464646464646462020202020202020202020202020", INIT_51 => X"2020202020202020202020202020202020205050505050505050505020202020", INIT_52 => X"2020202020202020202020204141414141414147474747202020474747474747", INIT_53 => X"5A20202020202020202020202020202020204141414141414120202020202020", INIT_54 => X"20202020202020202020202020205A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A", INIT_55 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_56 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_57 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_58 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_59 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_5A => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_5B => X"2041475046206E41202020202020202020202020202020202020202020202020", INIT_5C => X"6D656C706D692033206E6F697372655620656E696863614D2D5A206465736162", INIT_5D => X"20202020202020202020202020202020202020202020202E6E6F697461746E65", INIT_5E => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_5F => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_60 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_61 => X"202E7475706E69207478657420726F662064616F6279656B2061206573552020", INIT_62 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_63 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_64 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_65 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_66 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_67 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_68 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_69 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_6A => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_6B => X"20202E2E2E65756E69746E6F63206F742079656B20796E612073736572502020", INIT_6C => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_6D => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_6E => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_6F => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_70 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_71 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_72 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_73 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_74 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_75 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_76 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_77 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_78 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_79 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_7A => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_7B => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_7C => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_7D => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_7E => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_7F => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_A => X"000000000", INIT_B => X"000000000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", READ_WIDTH_A => 9, READ_WIDTH_B => 9, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "NO_CHANGE", WRITE_MODE_B => "READ_FIRST", WRITE_WIDTH_A => 9, WRITE_WIDTH_B => 9 ) port map ( ADDRARDADDR(15) => '1', ADDRARDADDR(14 downto 3) => addra(11 downto 0), ADDRARDADDR(2 downto 0) => B"111", ADDRBWRADDR(15) => '1', ADDRBWRADDR(14 downto 3) => addrb(11 downto 0), ADDRBWRADDR(2 downto 0) => B"111", CASCADEINA => '0', CASCADEINB => '0', CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\, CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\, CLKARDCLK => clka, CLKBWRCLK => clkb, DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\, DIADI(31 downto 8) => B"000000000000000000000000", DIADI(7 downto 0) => dina(7 downto 0), DIBDI(31 downto 0) => B"00000000000000000000000000000000", DIPADIP(3 downto 0) => B"0000", DIPBDIP(3 downto 0) => B"0000", DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0), DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8), DOBDO(7 downto 0) => \doutb[7]\(7 downto 0), DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0), DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0), ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0), ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1_n_0\, ENBWREN => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2_n_0\, INJECTDBITERR => '0', INJECTSBITERR => '0', RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0), REGCEAREGCE => '0', REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\, WEA(3) => wea(0), WEA(2) => wea(0), WEA(1) => wea(0), WEA(0) => wea(0), WEBWE(7 downto 0) => B"00000000" ); \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => wea(0), I1 => addra(12), I2 => addra(13), O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1_n_0\ ); \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => addrb(12), I1 => addrb(13), O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized0\ is port ( \doutb[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); clka : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init"; end \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized0\; architecture STRUCTURE of \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized0\ is signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__0_n_0\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__0_n_0\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute BOX_TYPE : string; attribute BOX_TYPE of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE"; attribute CLOCK_DOMAINS : string; attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT"; attribute PWROPT_WRITE_MODE_CHANGE_A : string; attribute PWROPT_WRITE_MODE_CHANGE_A of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "READ_FIRST:NO_CHANGE_2"; begin \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1 generic map( DOA_REG => 0, DOB_REG => 0, EN_ECC_READ => false, EN_ECC_WRITE => false, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_01 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_02 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_03 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_04 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_05 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_06 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_07 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_08 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_09 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_0A => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_0B => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_0C => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_0D => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_0E => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_0F => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_10 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_11 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_12 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_13 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_14 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_15 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_16 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_17 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_18 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_19 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_1A => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_1B => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_1C => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_1D => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_1E => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_1F => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_20 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_21 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_22 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_23 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_24 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_25 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_26 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_27 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_28 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_29 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_2A => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_2B => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_2C => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_2D => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_2E => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_2F => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_30 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_31 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_32 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_33 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_34 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_35 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_36 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_37 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_38 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_39 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_3A => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_3B => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_3C => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_3D => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_3E => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_3F => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_40 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_41 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_42 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_43 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_44 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_45 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_46 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_47 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_48 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_49 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_4A => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_4B => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_4C => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_4D => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_4E => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_4F => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_50 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_51 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_52 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_53 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_54 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_55 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_56 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_57 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_58 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_59 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_5A => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_5B => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_5C => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_5D => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_5E => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_5F => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_60 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_61 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_62 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_63 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_64 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_65 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_66 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_67 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_68 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_69 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_6A => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_6B => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_6C => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_6D => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_6E => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_6F => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_70 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_71 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_72 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_73 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_74 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_75 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_76 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_77 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_78 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_79 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_7A => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_7B => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_7C => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_7D => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_7E => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_7F => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_A => X"000000000", INIT_B => X"000000000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", READ_WIDTH_A => 9, READ_WIDTH_B => 9, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "NO_CHANGE", WRITE_MODE_B => "READ_FIRST", WRITE_WIDTH_A => 9, WRITE_WIDTH_B => 9 ) port map ( ADDRARDADDR(15) => '1', ADDRARDADDR(14 downto 3) => addra(11 downto 0), ADDRARDADDR(2 downto 0) => B"111", ADDRBWRADDR(15) => '1', ADDRBWRADDR(14 downto 3) => addrb(11 downto 0), ADDRBWRADDR(2 downto 0) => B"111", CASCADEINA => '0', CASCADEINB => '0', CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\, CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\, CLKARDCLK => clka, CLKBWRCLK => clkb, DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\, DIADI(31 downto 8) => B"000000000000000000000000", DIADI(7 downto 0) => dina(7 downto 0), DIBDI(31 downto 0) => B"00000000000000000000000000000000", DIPADIP(3 downto 0) => B"0000", DIPBDIP(3 downto 0) => B"0000", DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0), DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8), DOBDO(7 downto 0) => \doutb[7]\(7 downto 0), DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0), DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0), ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0), ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__0_n_0\, ENBWREN => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__0_n_0\, INJECTDBITERR => '0', INJECTSBITERR => '0', RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0), REGCEAREGCE => '0', REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\, WEA(3) => wea(0), WEA(2) => wea(0), WEA(1) => wea(0), WEA(0) => wea(0), WEBWE(7 downto 0) => B"00000000" ); \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"08" ) port map ( I0 => addra(12), I1 => wea(0), I2 => addra(13), O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__0_n_0\ ); \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__0\: unisim.vcomponents.LUT2 generic map( INIT => X"4" ) port map ( I0 => addrb(13), I1 => addrb(12), O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__0_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized1\ is port ( DOBDO : out STD_LOGIC_VECTOR ( 7 downto 0 ); clka : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized1\ : entity is "blk_mem_gen_prim_wrapper_init"; end \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized1\; architecture STRUCTURE of \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized1\ is signal ram_ena : STD_LOGIC; signal ram_enb : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 8 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute BOX_TYPE : string; attribute BOX_TYPE of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE"; attribute CLOCK_DOMAINS : string; attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "INDEPENDENT"; attribute PWROPT_WRITE_MODE_CHANGE_A : string; attribute PWROPT_WRITE_MODE_CHANGE_A of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "READ_FIRST:NO_CHANGE_2"; begin \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1 generic map( DOA_REG => 0, DOB_REG => 0, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_01 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_02 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_03 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_04 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_05 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_06 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_07 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_08 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_09 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_0A => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_0B => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_0C => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_0D => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_0E => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_0F => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_10 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_11 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_12 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_13 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_14 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_15 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_16 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_17 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_18 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_19 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_1A => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_1B => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_1C => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_1D => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_1E => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_1F => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_20 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_21 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_22 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_23 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_24 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_25 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_26 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_27 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_28 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_29 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_2A => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_2B => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_2C => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_2D => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_2E => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_2F => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_30 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_31 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_32 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_33 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_34 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_35 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_36 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_37 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_38 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_39 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_3A => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_3B => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_3C => X"6867697279706F43202020202020202020202020202020202020202020202020", INIT_3D => X"656972642F2F3A707474683C2037303073656972442036313032202943282074", INIT_3E => X"20202020202020202020202020202020202020202020203E74656E2E37303073", INIT_3F => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_A => X"00000", INIT_B => X"00000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", READ_WIDTH_A => 9, READ_WIDTH_B => 9, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"00000", SRVAL_B => X"00000", WRITE_MODE_A => "NO_CHANGE", WRITE_MODE_B => "READ_FIRST", WRITE_WIDTH_A => 9, WRITE_WIDTH_B => 9 ) port map ( ADDRARDADDR(13 downto 3) => addra(10 downto 0), ADDRARDADDR(2 downto 0) => B"000", ADDRBWRADDR(13 downto 3) => addrb(10 downto 0), ADDRBWRADDR(2 downto 0) => B"000", CLKARDCLK => clka, CLKBWRCLK => clkb, DIADI(15 downto 8) => B"00000000", DIADI(7 downto 0) => dina(7 downto 0), DIBDI(15 downto 0) => B"0000000000000000", DIPADIP(1 downto 0) => B"00", DIPBDIP(1 downto 0) => B"00", DOADO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 0), DOBDO(15 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 8), DOBDO(7 downto 0) => DOBDO(7 downto 0), DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0), DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0), ENARDEN => ram_ena, ENBWREN => ram_enb, REGCEAREGCE => '0', REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', WEA(1) => wea(0), WEA(0) => wea(0), WEBWE(3 downto 0) => B"0000" ); \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"1000" ) port map ( I0 => addra(12), I1 => addra(11), I2 => addra(13), I3 => wea(0), O => ram_ena ); \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"04" ) port map ( I0 => addrb(11), I1 => addrb(13), I2 => addrb(12), O => ram_enb ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity Vga is port ( addrb : out STD_LOGIC_VECTOR ( 13 downto 0 ); Hsync_OBUF : out STD_LOGIC; Vsync_OBUF : out STD_LOGIC; vgaBlue_OBUF : out STD_LOGIC_VECTOR ( 0 to 0 ); clk108M : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 7 downto 0 ) ); end Vga; architecture STRUCTURE of Vga is signal X : STD_LOGIC_VECTOR ( 2 downto 0 ); signal Y : STD_LOGIC_VECTOR ( 3 downto 0 ); signal char : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \char[0]_i_1_n_0\ : STD_LOGIC; signal \char[1]_i_1_n_0\ : STD_LOGIC; signal \char[2]_i_1_n_0\ : STD_LOGIC; signal \char[3]_i_1_n_0\ : STD_LOGIC; signal \char[4]_i_1_n_0\ : STD_LOGIC; signal \char[5]_i_1_n_0\ : STD_LOGIC; signal \char[6]_i_1_n_0\ : STD_LOGIC; signal \char[7]_i_1_n_0\ : STD_LOGIC; signal enable : STD_LOGIC; signal enable_i_1_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_10_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_11_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_12_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_13_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_14_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_15_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_16_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_17_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_18_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_19_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_1_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_20_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_21_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_22_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_23_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_24_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_25_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_26_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_27_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_28_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_2_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_3_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_4_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_5_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_6_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_7_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_8_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_9_n_0 : STD_LOGIC; signal g0_b0_n_0 : STD_LOGIC; signal g0_b1_n_0 : STD_LOGIC; signal g0_b2_i_1_n_0 : STD_LOGIC; signal g0_b2_i_2_n_0 : STD_LOGIC; signal g0_b2_n_0 : STD_LOGIC; signal g0_b3_n_0 : STD_LOGIC; signal g0_b4_n_0 : STD_LOGIC; signal g0_b5_n_0 : STD_LOGIC; signal g0_b6_n_0 : STD_LOGIC; signal g0_b7_n_0 : STD_LOGIC; signal g10_b0_n_0 : STD_LOGIC; signal g10_b1_n_0 : STD_LOGIC; signal g10_b2_n_0 : STD_LOGIC; signal g10_b3_n_0 : STD_LOGIC; signal g10_b4_n_0 : STD_LOGIC; signal g10_b5_n_0 : STD_LOGIC; signal g11_b0_n_0 : STD_LOGIC; signal g11_b1_n_0 : STD_LOGIC; signal g11_b2_n_0 : STD_LOGIC; signal g11_b3_n_0 : STD_LOGIC; signal g11_b4_n_0 : STD_LOGIC; signal g11_b5_n_0 : STD_LOGIC; signal g11_b6_n_0 : STD_LOGIC; signal g12_b0_n_0 : STD_LOGIC; signal g12_b1_n_0 : STD_LOGIC; signal g12_b2_n_0 : STD_LOGIC; signal g12_b3_n_0 : STD_LOGIC; signal g12_b4_n_0 : STD_LOGIC; signal g12_b5_n_0 : STD_LOGIC; signal g12_b6_n_0 : STD_LOGIC; signal g13_b0_n_0 : STD_LOGIC; signal g13_b1_n_0 : STD_LOGIC; signal g13_b2_n_0 : STD_LOGIC; signal g13_b3_n_0 : STD_LOGIC; signal g13_b4_n_0 : STD_LOGIC; signal g13_b5_n_0 : STD_LOGIC; signal g13_b6_n_0 : STD_LOGIC; signal g14_b0_n_0 : STD_LOGIC; signal g14_b1_n_0 : STD_LOGIC; signal g14_b2_n_0 : STD_LOGIC; signal g14_b3_n_0 : STD_LOGIC; signal g14_b4_n_0 : STD_LOGIC; signal g14_b5_n_0 : STD_LOGIC; signal g14_b6_n_0 : STD_LOGIC; signal g15_b0_n_0 : STD_LOGIC; signal g15_b1_n_0 : STD_LOGIC; signal g15_b2_n_0 : STD_LOGIC; signal g15_b3_n_0 : STD_LOGIC; signal g15_b4_n_0 : STD_LOGIC; signal g15_b5_n_0 : STD_LOGIC; signal g15_b6_n_0 : STD_LOGIC; signal g16_b0_n_0 : STD_LOGIC; signal g16_b1_n_0 : STD_LOGIC; signal g16_b2_n_0 : STD_LOGIC; signal g16_b3_n_0 : STD_LOGIC; signal g16_b4_n_0 : STD_LOGIC; signal g16_b5_n_0 : STD_LOGIC; signal g16_b6_n_0 : STD_LOGIC; signal g17_b0_n_0 : STD_LOGIC; signal g17_b1_n_0 : STD_LOGIC; signal g17_b2_n_0 : STD_LOGIC; signal g17_b3_n_0 : STD_LOGIC; signal g17_b4_n_0 : STD_LOGIC; signal g17_b5_n_0 : STD_LOGIC; signal g17_b6_n_0 : STD_LOGIC; signal g18_b0_n_0 : STD_LOGIC; signal g18_b1_n_0 : STD_LOGIC; signal g18_b2_n_0 : STD_LOGIC; signal g18_b3_n_0 : STD_LOGIC; signal g18_b4_n_0 : STD_LOGIC; signal g18_b5_n_0 : STD_LOGIC; signal g18_b6_n_0 : STD_LOGIC; signal g19_b0_n_0 : STD_LOGIC; signal g19_b1_n_0 : STD_LOGIC; signal g19_b2_n_0 : STD_LOGIC; signal g19_b3_n_0 : STD_LOGIC; signal g19_b4_n_0 : STD_LOGIC; signal g19_b5_n_0 : STD_LOGIC; signal g19_b6_n_0 : STD_LOGIC; signal g19_b7_n_0 : STD_LOGIC; signal g1_b0_n_0 : STD_LOGIC; signal g1_b1_n_0 : STD_LOGIC; signal g1_b2_n_0 : STD_LOGIC; signal g1_b3_n_0 : STD_LOGIC; signal g1_b4_n_0 : STD_LOGIC; signal g1_b5_n_0 : STD_LOGIC; signal g1_b6_n_0 : STD_LOGIC; signal g1_b7_n_0 : STD_LOGIC; signal g20_b0_n_0 : STD_LOGIC; signal g20_b1_n_0 : STD_LOGIC; signal g20_b2_n_0 : STD_LOGIC; signal g20_b3_n_0 : STD_LOGIC; signal g20_b4_n_0 : STD_LOGIC; signal g20_b5_n_0 : STD_LOGIC; signal g20_b6_n_0 : STD_LOGIC; signal g21_b0_n_0 : STD_LOGIC; signal g21_b1_n_0 : STD_LOGIC; signal g21_b2_n_0 : STD_LOGIC; signal g21_b3_n_0 : STD_LOGIC; signal g21_b5_n_0 : STD_LOGIC; signal g21_b6_n_0 : STD_LOGIC; signal g21_b7_n_0 : STD_LOGIC; signal g22_b0_n_0 : STD_LOGIC; signal g22_b1_n_0 : STD_LOGIC; signal g22_b2_n_0 : STD_LOGIC; signal g22_b3_n_0 : STD_LOGIC; signal g22_b4_n_0 : STD_LOGIC; signal g22_b5_n_0 : STD_LOGIC; signal g22_b6_n_0 : STD_LOGIC; signal g22_b7_n_0 : STD_LOGIC; signal g23_b0_n_0 : STD_LOGIC; signal g23_b1_n_0 : STD_LOGIC; signal g23_b2_n_0 : STD_LOGIC; signal g23_b3_n_0 : STD_LOGIC; signal g23_b4_n_0 : STD_LOGIC; signal g23_b5_n_0 : STD_LOGIC; signal g23_b6_n_0 : STD_LOGIC; signal g23_b7_n_0 : STD_LOGIC; signal g24_b0_n_0 : STD_LOGIC; signal g24_b1_n_0 : STD_LOGIC; signal g24_b2_n_0 : STD_LOGIC; signal g24_b3_n_0 : STD_LOGIC; signal g24_b4_n_0 : STD_LOGIC; signal g24_b5_n_0 : STD_LOGIC; signal g24_b6_n_0 : STD_LOGIC; signal g25_b0_n_0 : STD_LOGIC; signal g25_b1_n_0 : STD_LOGIC; signal g25_b2_n_0 : STD_LOGIC; signal g25_b3_n_0 : STD_LOGIC; signal g25_b4_n_0 : STD_LOGIC; signal g25_b5_n_0 : STD_LOGIC; signal g25_b6_n_0 : STD_LOGIC; signal g26_b0_n_0 : STD_LOGIC; signal g26_b1_n_0 : STD_LOGIC; signal g26_b2_n_0 : STD_LOGIC; signal g26_b3_n_0 : STD_LOGIC; signal g26_b4_n_0 : STD_LOGIC; signal g26_b5_n_0 : STD_LOGIC; signal g26_b6_n_0 : STD_LOGIC; signal g27_b0_n_0 : STD_LOGIC; signal g27_b1_n_0 : STD_LOGIC; signal g27_b2_n_0 : STD_LOGIC; signal g27_b3_n_0 : STD_LOGIC; signal g27_b5_n_0 : STD_LOGIC; signal g27_b6_n_0 : STD_LOGIC; signal g27_b7_n_0 : STD_LOGIC; signal g28_b0_n_0 : STD_LOGIC; signal g28_b1_n_0 : STD_LOGIC; signal g28_b2_n_0 : STD_LOGIC; signal g28_b3_n_0 : STD_LOGIC; signal g28_b4_n_0 : STD_LOGIC; signal g28_b5_n_0 : STD_LOGIC; signal g28_b6_n_0 : STD_LOGIC; signal g29_b0_n_0 : STD_LOGIC; signal g29_b1_n_0 : STD_LOGIC; signal g29_b2_n_0 : STD_LOGIC; signal g29_b3_n_0 : STD_LOGIC; signal g29_b4_n_0 : STD_LOGIC; signal g29_b5_n_0 : STD_LOGIC; signal g29_b6_n_0 : STD_LOGIC; signal g29_b7_n_0 : STD_LOGIC; signal g2_b0_n_0 : STD_LOGIC; signal g2_b1_n_0 : STD_LOGIC; signal g2_b2_n_0 : STD_LOGIC; signal g2_b3_n_0 : STD_LOGIC; signal g2_b4_n_0 : STD_LOGIC; signal g2_b5_n_0 : STD_LOGIC; signal g2_b6_n_0 : STD_LOGIC; signal g2_b7_n_0 : STD_LOGIC; signal g30_b0_n_0 : STD_LOGIC; signal g30_b1_n_0 : STD_LOGIC; signal g30_b2_n_0 : STD_LOGIC; signal g30_b3_n_0 : STD_LOGIC; signal g30_b4_n_0 : STD_LOGIC; signal g30_b5_n_0 : STD_LOGIC; signal g30_b6_n_0 : STD_LOGIC; signal g30_b7_n_0 : STD_LOGIC; signal g31_b0_n_0 : STD_LOGIC; signal g31_b1_n_0 : STD_LOGIC; signal g31_b2_n_0 : STD_LOGIC; signal g31_b3_n_0 : STD_LOGIC; signal g31_b4_n_0 : STD_LOGIC; signal g31_b5_n_0 : STD_LOGIC; signal g31_b6_n_0 : STD_LOGIC; signal g3_b0_n_0 : STD_LOGIC; signal g3_b1_n_0 : STD_LOGIC; signal g3_b2_n_0 : STD_LOGIC; signal g3_b3_n_0 : STD_LOGIC; signal g3_b4_n_0 : STD_LOGIC; signal g3_b5_n_0 : STD_LOGIC; signal g3_b6_n_0 : STD_LOGIC; signal g3_b7_n_0 : STD_LOGIC; signal g4_b0_n_0 : STD_LOGIC; signal g4_b1_n_0 : STD_LOGIC; signal g4_b2_n_0 : STD_LOGIC; signal g4_b3_n_0 : STD_LOGIC; signal g4_b4_n_0 : STD_LOGIC; signal g4_b5_n_0 : STD_LOGIC; signal g4_b6_n_0 : STD_LOGIC; signal g5_b0_n_0 : STD_LOGIC; signal g5_b1_n_0 : STD_LOGIC; signal g5_b2_n_0 : STD_LOGIC; signal g5_b3_n_0 : STD_LOGIC; signal g5_b4_n_0 : STD_LOGIC; signal g5_b5_n_0 : STD_LOGIC; signal g5_b6_n_0 : STD_LOGIC; signal g5_b7_n_0 : STD_LOGIC; signal g6_b0_n_0 : STD_LOGIC; signal g6_b1_n_0 : STD_LOGIC; signal g6_b2_n_0 : STD_LOGIC; signal g6_b3_n_0 : STD_LOGIC; signal g6_b4_n_0 : STD_LOGIC; signal g6_b5_n_0 : STD_LOGIC; signal g6_b6_n_0 : STD_LOGIC; signal g7_b0_n_0 : STD_LOGIC; signal g7_b1_n_0 : STD_LOGIC; signal g7_b2_n_0 : STD_LOGIC; signal g7_b3_n_0 : STD_LOGIC; signal g7_b4_n_0 : STD_LOGIC; signal g7_b5_n_0 : STD_LOGIC; signal g7_b6_n_0 : STD_LOGIC; signal g7_b7_n_0 : STD_LOGIC; signal g8_b0_n_0 : STD_LOGIC; signal g8_b1_n_0 : STD_LOGIC; signal g8_b2_n_0 : STD_LOGIC; signal g8_b3_n_0 : STD_LOGIC; signal g8_b4_n_0 : STD_LOGIC; signal g8_b6_n_0 : STD_LOGIC; signal g9_b0_n_0 : STD_LOGIC; signal g9_b1_n_0 : STD_LOGIC; signal g9_b2_n_0 : STD_LOGIC; signal g9_b3_n_0 : STD_LOGIC; signal g9_b4_n_0 : STD_LOGIC; signal g9_b5_n_0 : STD_LOGIC; signal g9_b6_n_0 : STD_LOGIC; signal hSync_i_1_n_0 : STD_LOGIC; signal hSync_i_2_n_0 : STD_LOGIC; signal hSync_i_3_n_0 : STD_LOGIC; signal \h_count[2]_i_1_n_0\ : STD_LOGIC; signal \h_count_reg__0\ : STD_LOGIC_VECTOR ( 10 downto 3 ); signal nextChar : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \nextChar[7]_i_1_n_0\ : STD_LOGIC; signal p_0_in : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal vSync_i_1_n_0 : STD_LOGIC; signal vSync_i_2_n_0 : STD_LOGIC; signal \v_count[0]_rep_i_1_n_0\ : STD_LOGIC; signal \v_count[1]_rep_i_1_n_0\ : STD_LOGIC; signal \v_count[2]_rep_i_1_n_0\ : STD_LOGIC; signal \v_count[3]_rep__0_i_1_n_0\ : STD_LOGIC; signal \v_count[3]_rep_i_1_n_0\ : STD_LOGIC; signal \v_count_reg[0]_rep_n_0\ : STD_LOGIC; signal \v_count_reg[1]_rep_n_0\ : STD_LOGIC; signal \v_count_reg[2]_rep_n_0\ : STD_LOGIC; signal \v_count_reg[3]_rep__0_n_0\ : STD_LOGIC; signal \v_count_reg[3]_rep_n_0\ : STD_LOGIC; signal \v_count_reg__0\ : STD_LOGIC_VECTOR ( 10 downto 4 ); signal \vgaRed[0]_i_10_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_11_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_13_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_14_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_15_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_16_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_17_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_18_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_19_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_1_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_20_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_21_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_22_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_23_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_29_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_33_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_34_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_40_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_41_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_42_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_48_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_4_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_56_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_5_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_64_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_68_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_69_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_6_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_7_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_80_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_8_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_9_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_100_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_101_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_102_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_103_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_104_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_105_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_106_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_107_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_108_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_109_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_110_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_111_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_112_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_113_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_114_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_115_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_116_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_117_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_118_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_119_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_120_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_121_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_122_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_123_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_124_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_125_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_126_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_127_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_128_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_129_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_12_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_130_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_131_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_132_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_133_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_134_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_135_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_136_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_137_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_138_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_139_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_140_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_141_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_142_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_143_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_144_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_145_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_146_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_147_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_148_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_149_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_150_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_151_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_152_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_153_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_154_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_155_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_156_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_157_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_158_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_159_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_160_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_161_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_162_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_163_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_164_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_165_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_166_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_167_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_168_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_169_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_170_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_171_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_172_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_173_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_174_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_175_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_176_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_177_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_178_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_179_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_180_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_24_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_25_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_26_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_27_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_28_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_2_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_30_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_31_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_32_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_35_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_36_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_37_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_38_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_39_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_3_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_43_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_44_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_45_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_46_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_47_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_49_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_50_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_51_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_52_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_53_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_54_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_55_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_57_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_58_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_59_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_60_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_61_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_62_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_63_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_65_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_66_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_67_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_70_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_71_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_72_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_73_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_74_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_75_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_76_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_77_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_78_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_79_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_81_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_82_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_83_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_84_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_85_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_86_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_87_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_88_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_89_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_90_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_91_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_92_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_93_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_94_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_95_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_96_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_97_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_98_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_99_n_0\ : STD_LOGIC; signal NLW_fbOutAddr_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC; signal NLW_fbOutAddr_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC; signal NLW_fbOutAddr_reg_OVERFLOW_UNCONNECTED : STD_LOGIC; signal NLW_fbOutAddr_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC; signal NLW_fbOutAddr_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC; signal NLW_fbOutAddr_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC; signal NLW_fbOutAddr_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 ); signal NLW_fbOutAddr_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 ); signal NLW_fbOutAddr_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_fbOutAddr_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 14 ); signal NLW_fbOutAddr_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \v_count[0]_i_1\ : label is "soft_lutpair19"; attribute SOFT_HLUTNM of \v_count[0]_rep_i_1\ : label is "soft_lutpair19"; attribute SOFT_HLUTNM of \v_count[1]_i_1\ : label is "soft_lutpair18"; attribute SOFT_HLUTNM of \v_count[1]_rep_i_1\ : label is "soft_lutpair18"; attribute SOFT_HLUTNM of \v_count[2]_i_1\ : label is "soft_lutpair14"; attribute SOFT_HLUTNM of \v_count[3]_i_1\ : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \v_count[3]_rep__0_i_1\ : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \v_count[3]_rep_i_1\ : label is "soft_lutpair14"; attribute ORIG_CELL_NAME : string; attribute ORIG_CELL_NAME of \v_count_reg[0]\ : label is "v_count_reg[0]"; attribute ORIG_CELL_NAME of \v_count_reg[0]_rep\ : label is "v_count_reg[0]"; attribute ORIG_CELL_NAME of \v_count_reg[1]\ : label is "v_count_reg[1]"; attribute ORIG_CELL_NAME of \v_count_reg[1]_rep\ : label is "v_count_reg[1]"; attribute ORIG_CELL_NAME of \v_count_reg[2]\ : label is "v_count_reg[2]"; attribute ORIG_CELL_NAME of \v_count_reg[2]_rep\ : label is "v_count_reg[2]"; attribute ORIG_CELL_NAME of \v_count_reg[3]\ : label is "v_count_reg[3]"; attribute ORIG_CELL_NAME of \v_count_reg[3]_rep\ : label is "v_count_reg[3]"; attribute ORIG_CELL_NAME of \v_count_reg[3]_rep__0\ : label is "v_count_reg[3]"; begin \char[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0002" ) port map ( I0 => nextChar(0), I1 => X(1), I2 => X(0), I3 => X(2), I4 => char(0), O => \char[0]_i_1_n_0\ ); \char[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0002" ) port map ( I0 => nextChar(1), I1 => X(1), I2 => X(0), I3 => X(2), I4 => char(1), O => \char[1]_i_1_n_0\ ); \char[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0002" ) port map ( I0 => nextChar(2), I1 => X(1), I2 => X(0), I3 => X(2), I4 => char(2), O => \char[2]_i_1_n_0\ ); \char[3]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0002" ) port map ( I0 => nextChar(3), I1 => X(1), I2 => X(0), I3 => X(2), I4 => char(3), O => \char[3]_i_1_n_0\ ); \char[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0002" ) port map ( I0 => nextChar(4), I1 => X(1), I2 => X(0), I3 => X(2), I4 => char(4), O => \char[4]_i_1_n_0\ ); \char[5]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0002" ) port map ( I0 => nextChar(5), I1 => X(1), I2 => X(0), I3 => X(2), I4 => char(5), O => \char[5]_i_1_n_0\ ); \char[6]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0002" ) port map ( I0 => nextChar(6), I1 => X(1), I2 => X(0), I3 => X(2), I4 => char(6), O => \char[6]_i_1_n_0\ ); \char[7]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0002" ) port map ( I0 => nextChar(7), I1 => X(1), I2 => X(0), I3 => X(2), I4 => char(7), O => \char[7]_i_1_n_0\ ); \char_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => enable, D => \char[0]_i_1_n_0\, Q => char(0), R => '0' ); \char_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => enable, D => \char[1]_i_1_n_0\, Q => char(1), R => '0' ); \char_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => enable, D => \char[2]_i_1_n_0\, Q => char(2), R => '0' ); \char_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => enable, D => \char[3]_i_1_n_0\, Q => char(3), R => '0' ); \char_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => enable, D => \char[4]_i_1_n_0\, Q => char(4), R => '0' ); \char_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => enable, D => \char[5]_i_1_n_0\, Q => char(5), R => '0' ); \char_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => enable, D => \char[6]_i_1_n_0\, Q => char(6), R => '0' ); \char_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => enable, D => \char[7]_i_1_n_0\, Q => char(7), R => '0' ); enable_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"0057" ) port map ( I0 => \h_count_reg__0\(10), I1 => \h_count_reg__0\(8), I2 => \h_count_reg__0\(9), I3 => \v_count_reg__0\(10), O => enable_i_1_n_0 ); enable_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => '1', D => enable_i_1_n_0, Q => enable, R => '0' ); fbOutAddr_reg: unisim.vcomponents.DSP48E1 generic map( ACASCREG => 1, ADREG => 1, ALUMODEREG => 0, AREG => 1, AUTORESET_PATDET => "NO_RESET", A_INPUT => "DIRECT", BCASCREG => 0, BREG => 0, B_INPUT => "DIRECT", CARRYINREG => 0, CARRYINSELREG => 0, CREG => 1, DREG => 1, INMODEREG => 0, MASK => X"3FFFFFFFFFFF", MREG => 0, OPMODEREG => 0, PATTERN => X"000000000000", PREG => 1, SEL_MASK => "MASK", SEL_PATTERN => "PATTERN", USE_DPORT => false, USE_MULT => "MULTIPLY", USE_PATTERN_DETECT => "NO_PATDET", USE_SIMD => "ONE48" ) port map ( A(29 downto 7) => B"00000000000000000000000", A(6) => fbOutAddr_reg_i_5_n_0, A(5) => fbOutAddr_reg_i_6_n_0, A(4) => fbOutAddr_reg_i_7_n_0, A(3) => fbOutAddr_reg_i_8_n_0, A(2) => fbOutAddr_reg_i_9_n_0, A(1) => fbOutAddr_reg_i_10_n_0, A(0) => fbOutAddr_reg_i_11_n_0, ACIN(29 downto 0) => B"000000000000000000000000000000", ACOUT(29 downto 0) => NLW_fbOutAddr_reg_ACOUT_UNCONNECTED(29 downto 0), ALUMODE(3 downto 0) => B"0000", B(17 downto 0) => B"000000000010100000", BCIN(17 downto 0) => B"000000000000000000", BCOUT(17 downto 0) => NLW_fbOutAddr_reg_BCOUT_UNCONNECTED(17 downto 0), C(47 downto 8) => B"0000000000000000000000000000000000000000", C(7) => fbOutAddr_reg_i_12_n_0, C(6) => fbOutAddr_reg_i_13_n_0, C(5) => fbOutAddr_reg_i_14_n_0, C(4) => fbOutAddr_reg_i_15_n_0, C(3) => fbOutAddr_reg_i_16_n_0, C(2) => fbOutAddr_reg_i_17_n_0, C(1) => fbOutAddr_reg_i_18_n_0, C(0) => fbOutAddr_reg_i_19_n_0, CARRYCASCIN => '0', CARRYCASCOUT => NLW_fbOutAddr_reg_CARRYCASCOUT_UNCONNECTED, CARRYIN => '0', CARRYINSEL(2 downto 0) => B"000", CARRYOUT(3 downto 0) => NLW_fbOutAddr_reg_CARRYOUT_UNCONNECTED(3 downto 0), CEA1 => '0', CEA2 => fbOutAddr_reg_i_1_n_0, CEAD => '0', CEALUMODE => '0', CEB1 => '0', CEB2 => '0', CEC => '1', CECARRYIN => '0', CECTRL => '0', CED => '0', CEINMODE => '0', CEM => '0', CEP => fbOutAddr_reg_i_2_n_0, CLK => clk108M, D(24 downto 0) => B"0000000000000000000000000", INMODE(4 downto 0) => B"00000", MULTSIGNIN => '0', MULTSIGNOUT => NLW_fbOutAddr_reg_MULTSIGNOUT_UNCONNECTED, OPMODE(6) => '0', OPMODE(5) => enable, OPMODE(4) => enable, OPMODE(3 downto 0) => B"0101", OVERFLOW => NLW_fbOutAddr_reg_OVERFLOW_UNCONNECTED, P(47 downto 14) => NLW_fbOutAddr_reg_P_UNCONNECTED(47 downto 14), P(13 downto 0) => addrb(13 downto 0), PATTERNBDETECT => NLW_fbOutAddr_reg_PATTERNBDETECT_UNCONNECTED, PATTERNDETECT => NLW_fbOutAddr_reg_PATTERNDETECT_UNCONNECTED, PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000", PCOUT(47 downto 0) => NLW_fbOutAddr_reg_PCOUT_UNCONNECTED(47 downto 0), RSTA => fbOutAddr_reg_i_3_n_0, RSTALLCARRYIN => '0', RSTALUMODE => '0', RSTB => '0', RSTC => fbOutAddr_reg_i_1_n_0, RSTCTRL => '0', RSTD => '0', RSTINMODE => '0', RSTM => '0', RSTP => fbOutAddr_reg_i_4_n_0, UNDERFLOW => NLW_fbOutAddr_reg_UNDERFLOW_UNCONNECTED ); fbOutAddr_reg_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"88808888" ) port map ( I0 => \h_count_reg__0\(9), I1 => \h_count_reg__0\(10), I2 => \h_count_reg__0\(8), I3 => fbOutAddr_reg_i_20_n_0, I4 => fbOutAddr_reg_i_21_n_0, O => fbOutAddr_reg_i_1_n_0 ); fbOutAddr_reg_i_10: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => Y(3), I1 => Y(1), I2 => Y(0), I3 => Y(2), I4 => \v_count_reg__0\(4), I5 => \v_count_reg__0\(5), O => fbOutAddr_reg_i_10_n_0 ); fbOutAddr_reg_i_11: unisim.vcomponents.LUT5 generic map( INIT => X"6AAAAAAA" ) port map ( I0 => \v_count_reg__0\(4), I1 => Y(2), I2 => Y(0), I3 => Y(1), I4 => Y(3), O => fbOutAddr_reg_i_11_n_0 ); fbOutAddr_reg_i_12: unisim.vcomponents.LUT5 generic map( INIT => X"6AAAAAAA" ) port map ( I0 => \h_count_reg__0\(10), I1 => \h_count_reg__0\(8), I2 => fbOutAddr_reg_i_27_n_0, I3 => \h_count_reg__0\(7), I4 => \h_count_reg__0\(9), O => fbOutAddr_reg_i_12_n_0 ); fbOutAddr_reg_i_13: unisim.vcomponents.LUT4 generic map( INIT => X"6AAA" ) port map ( I0 => \h_count_reg__0\(9), I1 => \h_count_reg__0\(7), I2 => fbOutAddr_reg_i_27_n_0, I3 => \h_count_reg__0\(8), O => fbOutAddr_reg_i_13_n_0 ); fbOutAddr_reg_i_14: unisim.vcomponents.LUT6 generic map( INIT => X"AAAA6AAAAAAAAAAA" ) port map ( I0 => \h_count_reg__0\(8), I1 => \h_count_reg__0\(6), I2 => \h_count_reg__0\(5), I3 => \h_count_reg__0\(4), I4 => fbOutAddr_reg_i_28_n_0, I5 => \h_count_reg__0\(7), O => fbOutAddr_reg_i_14_n_0 ); fbOutAddr_reg_i_15: unisim.vcomponents.LUT5 generic map( INIT => X"9AAAAAAA" ) port map ( I0 => \h_count_reg__0\(7), I1 => fbOutAddr_reg_i_28_n_0, I2 => \h_count_reg__0\(4), I3 => \h_count_reg__0\(5), I4 => \h_count_reg__0\(6), O => fbOutAddr_reg_i_15_n_0 ); fbOutAddr_reg_i_16: unisim.vcomponents.LUT4 generic map( INIT => X"BF40" ) port map ( I0 => fbOutAddr_reg_i_28_n_0, I1 => \h_count_reg__0\(4), I2 => \h_count_reg__0\(5), I3 => \h_count_reg__0\(6), O => fbOutAddr_reg_i_16_n_0 ); fbOutAddr_reg_i_17: unisim.vcomponents.LUT6 generic map( INIT => X"6AAAAAAAAAAAAAAA" ) port map ( I0 => \h_count_reg__0\(5), I1 => X(2), I2 => X(0), I3 => X(1), I4 => \h_count_reg__0\(3), I5 => \h_count_reg__0\(4), O => fbOutAddr_reg_i_17_n_0 ); fbOutAddr_reg_i_18: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => X(2), I1 => X(0), I2 => X(1), I3 => \h_count_reg__0\(3), I4 => \h_count_reg__0\(4), O => fbOutAddr_reg_i_18_n_0 ); fbOutAddr_reg_i_19: unisim.vcomponents.LUT4 generic map( INIT => X"6AAA" ) port map ( I0 => \h_count_reg__0\(3), I1 => X(2), I2 => X(0), I3 => X(1), O => fbOutAddr_reg_i_19_n_0 ); fbOutAddr_reg_i_2: unisim.vcomponents.LUT5 generic map( INIT => X"AAAABAAA" ) port map ( I0 => fbOutAddr_reg_i_22_n_0, I1 => X(2), I2 => enable, I3 => X(1), I4 => X(0), O => fbOutAddr_reg_i_2_n_0 ); fbOutAddr_reg_i_20: unisim.vcomponents.LUT3 generic map( INIT => X"A8" ) port map ( I0 => \h_count_reg__0\(7), I1 => \h_count_reg__0\(6), I2 => \h_count_reg__0\(5), O => fbOutAddr_reg_i_20_n_0 ); fbOutAddr_reg_i_21: unisim.vcomponents.LUT6 generic map( INIT => X"1555FFFFFFFFFFFF" ) port map ( I0 => \h_count_reg__0\(3), I1 => X(1), I2 => X(0), I3 => X(2), I4 => \h_count_reg__0\(7), I5 => \h_count_reg__0\(4), O => fbOutAddr_reg_i_21_n_0 ); fbOutAddr_reg_i_22: unisim.vcomponents.LUT4 generic map( INIT => X"4440" ) port map ( I0 => enable, I1 => \h_count_reg__0\(10), I2 => \h_count_reg__0\(8), I3 => \h_count_reg__0\(9), O => fbOutAddr_reg_i_22_n_0 ); fbOutAddr_reg_i_23: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => \v_count_reg__0\(6), I1 => \v_count_reg__0\(7), I2 => \v_count_reg__0\(9), I3 => \v_count_reg__0\(8), O => fbOutAddr_reg_i_23_n_0 ); fbOutAddr_reg_i_24: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => Y(1), I1 => Y(0), I2 => Y(2), O => fbOutAddr_reg_i_24_n_0 ); fbOutAddr_reg_i_25: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => Y(3), I1 => \v_count_reg__0\(4), O => fbOutAddr_reg_i_25_n_0 ); fbOutAddr_reg_i_26: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => \v_count_reg__0\(5), I1 => \v_count_reg__0\(4), I2 => Y(2), I3 => Y(0), I4 => Y(1), I5 => Y(3), O => fbOutAddr_reg_i_26_n_0 ); fbOutAddr_reg_i_27: unisim.vcomponents.LUT4 generic map( INIT => X"0080" ) port map ( I0 => \h_count_reg__0\(6), I1 => \h_count_reg__0\(5), I2 => \h_count_reg__0\(4), I3 => fbOutAddr_reg_i_28_n_0, O => fbOutAddr_reg_i_27_n_0 ); fbOutAddr_reg_i_28: unisim.vcomponents.LUT4 generic map( INIT => X"7FFF" ) port map ( I0 => X(2), I1 => X(0), I2 => X(1), I3 => \h_count_reg__0\(3), O => fbOutAddr_reg_i_28_n_0 ); fbOutAddr_reg_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"AA8A888800000000" ) port map ( I0 => fbOutAddr_reg_i_1_n_0, I1 => fbOutAddr_reg_i_23_n_0, I2 => fbOutAddr_reg_i_24_n_0, I3 => fbOutAddr_reg_i_25_n_0, I4 => \v_count_reg__0\(5), I5 => \v_count_reg__0\(10), O => fbOutAddr_reg_i_3_n_0 ); fbOutAddr_reg_i_4: unisim.vcomponents.LUT5 generic map( INIT => X"0000A800" ) port map ( I0 => \v_count_reg__0\(10), I1 => \h_count_reg__0\(9), I2 => \h_count_reg__0\(8), I3 => \h_count_reg__0\(10), I4 => enable, O => fbOutAddr_reg_i_4_n_0 ); fbOutAddr_reg_i_5: unisim.vcomponents.LUT6 generic map( INIT => X"6AAAAAAAAAAAAAAA" ) port map ( I0 => \v_count_reg__0\(10), I1 => \v_count_reg__0\(8), I2 => \v_count_reg__0\(6), I3 => fbOutAddr_reg_i_26_n_0, I4 => \v_count_reg__0\(7), I5 => \v_count_reg__0\(9), O => fbOutAddr_reg_i_5_n_0 ); fbOutAddr_reg_i_6: unisim.vcomponents.LUT5 generic map( INIT => X"6AAAAAAA" ) port map ( I0 => \v_count_reg__0\(9), I1 => \v_count_reg__0\(7), I2 => fbOutAddr_reg_i_26_n_0, I3 => \v_count_reg__0\(6), I4 => \v_count_reg__0\(8), O => fbOutAddr_reg_i_6_n_0 ); fbOutAddr_reg_i_7: unisim.vcomponents.LUT4 generic map( INIT => X"6AAA" ) port map ( I0 => \v_count_reg__0\(8), I1 => \v_count_reg__0\(6), I2 => fbOutAddr_reg_i_26_n_0, I3 => \v_count_reg__0\(7), O => fbOutAddr_reg_i_7_n_0 ); fbOutAddr_reg_i_8: unisim.vcomponents.LUT6 generic map( INIT => X"AA6AAAAAAAAAAAAA" ) port map ( I0 => \v_count_reg__0\(7), I1 => \v_count_reg__0\(5), I2 => \v_count_reg__0\(4), I3 => fbOutAddr_reg_i_24_n_0, I4 => Y(3), I5 => \v_count_reg__0\(6), O => fbOutAddr_reg_i_8_n_0 ); fbOutAddr_reg_i_9: unisim.vcomponents.LUT5 generic map( INIT => X"A6AAAAAA" ) port map ( I0 => \v_count_reg__0\(6), I1 => Y(3), I2 => fbOutAddr_reg_i_24_n_0, I3 => \v_count_reg__0\(4), I4 => \v_count_reg__0\(5), O => fbOutAddr_reg_i_9_n_0 ); g0_b0: unisim.vcomponents.LUT6 generic map( INIT => X"000007F807F80000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g0_b0_n_0 ); g0_b1: unisim.vcomponents.LUT6 generic map( INIT => X"01E00FFC08040000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g0_b1_n_0 ); g0_b2: unisim.vcomponents.LUT6 generic map( INIT => X"03F00F6C08940000" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g0_b2_n_0 ); g0_b2_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0002" ) port map ( I0 => nextChar(0), I1 => X(1), I2 => X(0), I3 => X(2), I4 => char(0), O => g0_b2_i_1_n_0 ); g0_b2_i_2: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0002" ) port map ( I0 => nextChar(1), I1 => X(1), I2 => X(0), I3 => X(2), I4 => char(1), O => g0_b2_i_2_n_0 ); g0_b3: unisim.vcomponents.LUT6 generic map( INIT => X"07F00E7C09840000" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g0_b3_n_0 ); g0_b4: unisim.vcomponents.LUT6 generic map( INIT => X"0FE00E7C09840000" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g0_b4_n_0 ); g0_b5: unisim.vcomponents.LUT6 generic map( INIT => X"07F00F6C08940000" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g0_b5_n_0 ); g0_b6: unisim.vcomponents.LUT6 generic map( INIT => X"03F00FFC08040000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g0_b6_n_0 ); g0_b7: unisim.vcomponents.LUT6 generic map( INIT => X"01E007F807F80000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g0_b7_n_0 ); g10_b0: unisim.vcomponents.LUT6 generic map( INIT => X"0000008000000000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g10_b0_n_0 ); g10_b1: unisim.vcomponents.LUT6 generic map( INIT => X"008002A000000000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g10_b1_n_0 ); g10_b2: unisim.vcomponents.LUT6 generic map( INIT => X"008003E0080403F0" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g10_b2_n_0 ); g10_b3: unisim.vcomponents.LUT6 generic map( INIT => X"03E001C00C0C07F8" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g10_b3_n_0 ); g10_b4: unisim.vcomponents.LUT6 generic map( INIT => X"03E001C007F80C0C" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g10_b4_n_0 ); g10_b5: unisim.vcomponents.LUT6 generic map( INIT => X"008003E003F00804" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g10_b5_n_0 ); g11_b0: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => Y(1), I1 => \v_count_reg[2]_rep_n_0\, I2 => \v_count_reg[3]_rep_n_0\, I3 => \char[0]_i_1_n_0\, I4 => \char[1]_i_1_n_0\, O => g11_b0_n_0 ); g11_b1: unisim.vcomponents.LUT6 generic map( INIT => X"0600000000800000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g11_b1_n_0 ); g11_b2: unisim.vcomponents.LUT6 generic map( INIT => X"0300000000801000" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g11_b2_n_0 ); g11_b3: unisim.vcomponents.LUT6 generic map( INIT => X"01800C0000801E00" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g11_b3_n_0 ); g11_b4: unisim.vcomponents.LUT6 generic map( INIT => X"00C00C0000800E00" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g11_b4_n_0 ); g11_b5: unisim.vcomponents.LUT6 generic map( INIT => X"0060000000800000" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g11_b5_n_0 ); g11_b6: unisim.vcomponents.LUT6 generic map( INIT => X"0030000000800000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g11_b6_n_0 ); g12_b0: unisim.vcomponents.LUT6 generic map( INIT => X"04080E08000007F8" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g12_b0_n_0 ); g12_b1: unisim.vcomponents.LUT6 generic map( INIT => X"0C0C0F0C08100FFC" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g12_b1_n_0 ); g12_b2: unisim.vcomponents.LUT6 generic map( INIT => X"0844098408180984" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g12_b2_n_0 ); g12_b3: unisim.vcomponents.LUT6 generic map( INIT => X"084408C40FFC08C4" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g12_b3_n_0 ); g12_b4: unisim.vcomponents.LUT6 generic map( INIT => X"084408640FFC0864" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g12_b4_n_0 ); g12_b5: unisim.vcomponents.LUT6 generic map( INIT => X"0FFC0C3C08000FFC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g12_b5_n_0 ); g12_b6: unisim.vcomponents.LUT6 generic map( INIT => X"07B80C18080007F8" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g12_b6_n_0 ); g13_b0: unisim.vcomponents.LUT6 generic map( INIT => X"000C07F0047C00C0" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g13_b0_n_0 ); g13_b1: unisim.vcomponents.LUT6 generic map( INIT => X"000C0FF80C7C00E0" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g13_b1_n_0 ); g13_b2: unisim.vcomponents.LUT6 generic map( INIT => X"0F04084C084400B0" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g13_b2_n_0 ); g13_b3: unisim.vcomponents.LUT6 generic map( INIT => X"0F84084408440898" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g13_b3_n_0 ); g13_b4: unisim.vcomponents.LUT6 generic map( INIT => X"00C4084408440FFC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g13_b4_n_0 ); g13_b5: unisim.vcomponents.LUT6 generic map( INIT => X"007C0FC00FC40FFC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g13_b5_n_0 ); g13_b6: unisim.vcomponents.LUT6 generic map( INIT => X"003C078007840880" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g13_b6_n_0 ); g14_b0: unisim.vcomponents.LUT6 generic map( INIT => X"00000000003807B8" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g14_b0_n_0 ); g14_b1: unisim.vcomponents.LUT6 generic map( INIT => X"00000000087C0FFC" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g14_b1_n_0 ); g14_b2: unisim.vcomponents.LUT6 generic map( INIT => X"0800000008440844" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g14_b2_n_0 ); g14_b3: unisim.vcomponents.LUT6 generic map( INIT => X"0E30063008440844" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g14_b3_n_0 ); g14_b4: unisim.vcomponents.LUT6 generic map( INIT => X"063006300C440844" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g14_b4_n_0 ); g14_b5: unisim.vcomponents.LUT6 generic map( INIT => X"0000000007FC0FFC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g14_b5_n_0 ); g14_b6: unisim.vcomponents.LUT6 generic map( INIT => X"0000000003F807B8" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g14_b6_n_0 ); g15_b0: unisim.vcomponents.LUT6 generic map( INIT => X"0018000000000000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g15_b0_n_0 ); g15_b1: unisim.vcomponents.LUT6 generic map( INIT => X"001C080801200080" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g15_b1_n_0 ); g15_b2: unisim.vcomponents.LUT6 generic map( INIT => X"00040C18012001C0" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g15_b2_n_0 ); g15_b3: unisim.vcomponents.LUT6 generic map( INIT => X"0DC4063001200360" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g15_b3_n_0 ); g15_b4: unisim.vcomponents.LUT6 generic map( INIT => X"0DE4036001200630" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g15_b4_n_0 ); g15_b5: unisim.vcomponents.LUT6 generic map( INIT => X"003C01C001200C18" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g15_b5_n_0 ); g15_b6: unisim.vcomponents.LUT6 generic map( INIT => X"0018008001200808" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g15_b6_n_0 ); g16_b0: unisim.vcomponents.LUT6 generic map( INIT => X"03F008040FE007F8" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g16_b0_n_0 ); g16_b1: unisim.vcomponents.LUT6 generic map( INIT => X"07F80FFC0FF00FFC" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g16_b1_n_0 ); g16_b2: unisim.vcomponents.LUT6 generic map( INIT => X"0C0C0FFC00980804" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g16_b2_n_0 ); g16_b3: unisim.vcomponents.LUT6 generic map( INIT => X"08040844008C0BC4" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g16_b3_n_0 ); g16_b4: unisim.vcomponents.LUT6 generic map( INIT => X"0804084400980BC4" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g16_b4_n_0 ); g16_b5: unisim.vcomponents.LUT6 generic map( INIT => X"0C0C0FFC0FF00BFC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g16_b5_n_0 ); g16_b6: unisim.vcomponents.LUT6 generic map( INIT => X"061807B80FE001F8" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g16_b6_n_0 ); g17_b0: unisim.vcomponents.LUT6 generic map( INIT => X"03F0080408040804" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g17_b0_n_0 ); g17_b1: unisim.vcomponents.LUT6 generic map( INIT => X"07F80FFC0FFC0FFC" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g17_b1_n_0 ); g17_b2: unisim.vcomponents.LUT5 generic map( INIT => X"223E3E3E" ) port map ( I0 => \v_count_reg[1]_rep_n_0\, I1 => Y(2), I2 => \v_count_reg[3]_rep__0_n_0\, I3 => g0_b2_i_1_n_0, I4 => g0_b2_i_2_n_0, O => g17_b2_n_0 ); g17_b3: unisim.vcomponents.LUT6 generic map( INIT => X"0884084408440804" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g17_b3_n_0 ); g17_b4: unisim.vcomponents.LUT6 generic map( INIT => X"088400E408E40C0C" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g17_b4_n_0 ); g17_b5: unisim.vcomponents.LUT6 generic map( INIT => X"078C000C0C0C07F8" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g17_b5_n_0 ); g17_b6: unisim.vcomponents.LUT6 generic map( INIT => X"0F98001C0E1C03F0" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g17_b6_n_0 ); g18_b0: unisim.vcomponents.LUT6 generic map( INIT => X"0804070000000FFC" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g18_b0_n_0 ); g18_b1: unisim.vcomponents.LUT5 generic map( INIT => X"3E30003E" ) port map ( I0 => Y(1), I1 => \v_count_reg[2]_rep_n_0\, I2 => \v_count_reg[3]_rep_n_0\, I3 => \char[0]_i_1_n_0\, I4 => \char[1]_i_1_n_0\, O => g18_b1_n_0 ); g18_b2: unisim.vcomponents.LUT6 generic map( INIT => X"0FFC080008040040" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g18_b2_n_0 ); g18_b3: unisim.vcomponents.LUT6 generic map( INIT => X"00C008040FFC0040" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g18_b3_n_0 ); g18_b4: unisim.vcomponents.LUT6 generic map( INIT => X"01E00FFC0FFC0040" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g18_b4_n_0 ); g18_b5: unisim.vcomponents.LUT6 generic map( INIT => X"0F3C07FC08040FFC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g18_b5_n_0 ); g18_b6: unisim.vcomponents.LUT6 generic map( INIT => X"0E1C000400000FFC" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g18_b6_n_0 ); g19_b0: unisim.vcomponents.LUT6 generic map( INIT => X"07F80FFC0FFC0804" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g19_b0_n_0 ); g19_b1: unisim.vcomponents.LUT3 generic map( INIT => X"3E" ) port map ( I0 => Y(1), I1 => \v_count_reg[2]_rep_n_0\, I2 => \v_count_reg[3]_rep_n_0\, O => g19_b1_n_0 ); g19_b2: unisim.vcomponents.LUT6 generic map( INIT => X"0804003800380FFC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g19_b2_n_0 ); g19_b3: unisim.vcomponents.LUT6 generic map( INIT => X"0804007000700804" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g19_b3_n_0 ); g19_b4: unisim.vcomponents.LUT6 generic map( INIT => X"080400E000700800" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g19_b4_n_0 ); g19_b5: unisim.vcomponents.LUT6 generic map( INIT => X"0FFC0FFC00380C00" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g19_b5_n_0 ); g19_b6: unisim.vcomponents.LUT6 generic map( INIT => X"07F80FFC0FFC0E00" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g19_b6_n_0 ); g19_b7: unisim.vcomponents.LUT5 generic map( INIT => X"00003E00" ) port map ( I0 => Y(1), I1 => \v_count_reg[2]_rep_n_0\, I2 => \v_count_reg[3]_rep_n_0\, I3 => \char[0]_i_1_n_0\, I4 => \char[1]_i_1_n_0\, O => g19_b7_n_0 ); g1_b0: unisim.vcomponents.LUT6 generic map( INIT => X"000000C001C00080" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g1_b0_n_0 ); g1_b1: unisim.vcomponents.LUT6 generic map( INIT => X"000001E001C001C0" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g1_b1_n_0 ); g1_b2: unisim.vcomponents.LUT6 generic map( INIT => X"018009F009F003E0" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g1_b2_n_0 ); g1_b3: unisim.vcomponents.LUT6 generic map( INIT => X"03C00FF80E3807F0" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g1_b3_n_0 ); g1_b4: unisim.vcomponents.LUT6 generic map( INIT => X"03C00FF80E3803E0" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g1_b4_n_0 ); g1_b5: unisim.vcomponents.LUT6 generic map( INIT => X"018009F009F001C0" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g1_b5_n_0 ); g1_b6: unisim.vcomponents.LUT6 generic map( INIT => X"000001E001C00080" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g1_b6_n_0 ); g1_b7: unisim.vcomponents.LUT6 generic map( INIT => X"000000C001C00000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g1_b7_n_0 ); g20_b0: unisim.vcomponents.LUT6 generic map( INIT => X"0618080407F80804" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g20_b0_n_0 ); g20_b1: unisim.vcomponents.LUT6 generic map( INIT => X"0E3C0FFC0FFC0FFC" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g20_b1_n_0 ); g20_b2: unisim.vcomponents.LUT6 generic map( INIT => X"08640FFC08040FFC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g20_b2_n_0 ); g20_b3: unisim.vcomponents.LUT6 generic map( INIT => X"084400440E040844" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g20_b3_n_0 ); g20_b4: unisim.vcomponents.LUT6 generic map( INIT => X"08C400C43C040044" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g20_b4_n_0 ); g20_b5: unisim.vcomponents.LUT6 generic map( INIT => X"0F9C0FFC3FFC007C" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g20_b5_n_0 ); g20_b6: unisim.vcomponents.LUT6 generic map( INIT => X"07180F3827F80038" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g20_b6_n_0 ); g21_b0: unisim.vcomponents.LUT6 generic map( INIT => X"03FC01FC07FC001C" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g21_b0_n_0 ); g21_b1: unisim.vcomponents.LUT5 generic map( INIT => X"3E1E3E02" ) port map ( I0 => Y(1), I1 => \v_count_reg[2]_rep_n_0\, I2 => \v_count_reg[3]_rep_n_0\, I3 => \char[0]_i_1_n_0\, I4 => \char[1]_i_1_n_0\, O => g21_b1_n_0 ); g21_b2: unisim.vcomponents.LUT6 generic map( INIT => X"0E00060008000804" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g21_b2_n_0 ); g21_b3: unisim.vcomponents.LUT6 generic map( INIT => X"03800C0008000FFC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g21_b3_n_0 ); g21_b5: unisim.vcomponents.LUT6 generic map( INIT => X"0E0006000FFC0804" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g21_b5_n_0 ); g21_b6: unisim.vcomponents.LUT6 generic map( INIT => X"0FFC03FC07FC000C" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g21_b6_n_0 ); g21_b7: unisim.vcomponents.LUT6 generic map( INIT => X"03FC01FC0000001C" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g21_b7_n_0 ); g22_b0: unisim.vcomponents.LUT6 generic map( INIT => X"00000E1C001C0C0C" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g22_b0_n_0 ); g22_b1: unisim.vcomponents.LUT6 generic map( INIT => X"00000F0C003C0E1C" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g22_b1_n_0 ); g22_b2: unisim.vcomponents.LUT6 generic map( INIT => X"0FFC098408600330" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g22_b2_n_0 ); g22_b3: unisim.vcomponents.LUT6 generic map( INIT => X"0FFC08C40FC001E0" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g22_b3_n_0 ); g22_b4: unisim.vcomponents.LUT6 generic map( INIT => X"080408640FC001E0" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g22_b4_n_0 ); g22_b5: unisim.vcomponents.LUT6 generic map( INIT => X"0804083408600330" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g22_b5_n_0 ); g22_b6: unisim.vcomponents.LUT6 generic map( INIT => X"00000C1C003C0E1C" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g22_b6_n_0 ); g22_b7: unisim.vcomponents.LUT6 generic map( INIT => X"00000E0C001C0C0C" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g22_b7_n_0 ); g23_b0: unisim.vcomponents.LUT6 generic map( INIT => X"2000000800000038" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g23_b0_n_0 ); g23_b1: unisim.vcomponents.LUT6 generic map( INIT => X"2000000C00000070" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g23_b1_n_0 ); g23_b2: unisim.vcomponents.LUT6 generic map( INIT => X"20000006080400E0" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g23_b2_n_0 ); g23_b3: unisim.vcomponents.LUT6 generic map( INIT => X"20000003080401C0" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g23_b3_n_0 ); g23_b4: unisim.vcomponents.LUT6 generic map( INIT => X"200000060FFC0380" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g23_b4_n_0 ); g23_b5: unisim.vcomponents.LUT6 generic map( INIT => X"2000000C0FFC0700" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g23_b5_n_0 ); g23_b6: unisim.vcomponents.LUT6 generic map( INIT => X"2000000800000E00" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g23_b6_n_0 ); g23_b7: unisim.vcomponents.LUT6 generic map( INIT => X"2000000000000000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g23_b7_n_0 ); g24_b0: unisim.vcomponents.LUT6 generic map( INIT => X"07C0000407000000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g24_b0_n_0 ); g24_b1: unisim.vcomponents.LUT6 generic map( INIT => X"0FE00FFC0FA00000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g24_b1_n_0 ); g24_b2: unisim.vcomponents.LUT6 generic map( INIT => X"08200FFC08A00003" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g24_b2_n_0 ); g24_b3: unisim.vcomponents.LUT6 generic map( INIT => X"0820082008A00007" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g24_b3_n_0 ); g24_b4: unisim.vcomponents.LUT6 generic map( INIT => X"0820086007E00004" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g24_b4_n_0 ); g24_b5: unisim.vcomponents.LUT6 generic map( INIT => X"0C600FC00FC00000" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g24_b5_n_0 ); g24_b6: unisim.vcomponents.LUT6 generic map( INIT => X"0440078008000000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g24_b6_n_0 ); g25_b0: unisim.vcomponents.LUT6 generic map( INIT => X"27C0084007C00780" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g25_b0_n_0 ); g25_b1: unisim.vcomponents.LUT6 generic map( INIT => X"6FE00FF80FE00FC0" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g25_b1_n_0 ); g25_b2: unisim.vcomponents.LUT6 generic map( INIT => X"48200FFC08A00860" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g25_b2_n_0 ); g25_b3: unisim.vcomponents.LUT6 generic map( INIT => X"4820084408A00824" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g25_b3_n_0 ); g25_b4: unisim.vcomponents.LUT6 generic map( INIT => X"7FC0000C08A007FC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g25_b4_n_0 ); g25_b5: unisim.vcomponents.LUT6 generic map( INIT => X"3FE000180CE00FFC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g25_b5_n_0 ); g25_b6: unisim.vcomponents.LUT6 generic map( INIT => X"0020000004C00800" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g25_b6_n_0 ); g26_b0: unisim.vcomponents.LUT6 generic map( INIT => X"0804000000000804" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g26_b0_n_0 ); g26_b1: unisim.vcomponents.LUT5 generic map( INIT => X"3E40003E" ) port map ( I0 => Y(1), I1 => \v_count_reg[2]_rep_n_0\, I2 => \v_count_reg[3]_rep_n_0\, I3 => \char[0]_i_1_n_0\, I4 => \char[1]_i_1_n_0\, O => g26_b1_n_0 ); g26_b2: unisim.vcomponents.LUT6 generic map( INIT => X"0FFC700008200FFC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g26_b2_n_0 ); g26_b3: unisim.vcomponents.LUT6 generic map( INIT => X"018040000FEC0040" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g26_b3_n_0 ); g26_b4: unisim.vcomponents.LUT6 generic map( INIT => X"03C040200FEC0020" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g26_b4_n_0 ); g26_b5: unisim.vcomponents.LUT6 generic map( INIT => X"0E607FEC08000FE0" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g26_b5_n_0 ); g26_b6: unisim.vcomponents.LUT6 generic map( INIT => X"0C203FEC00000FC0" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g26_b6_n_0 ); g27_b0: unisim.vcomponents.LUT6 generic map( INIT => X"07C000200FE00000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g27_b0_n_0 ); g27_b1: unisim.vcomponents.LUT6 generic map( INIT => X"0FE00FE00FE00000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g27_b1_n_0 ); g27_b2: unisim.vcomponents.LUT6 generic map( INIT => X"08200FC000600804" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g27_b2_n_0 ); g27_b3: unisim.vcomponents.LUT6 generic map( INIT => X"082000200FC00FFC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g27_b3_n_0 ); g27_b5: unisim.vcomponents.LUT6 generic map( INIT => X"0FE00FE000600800" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g27_b5_n_0 ); g27_b6: unisim.vcomponents.LUT6 generic map( INIT => X"07C00FC00FE00000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g27_b6_n_0 ); g27_b7: unisim.vcomponents.LUT5 generic map( INIT => X"00003800" ) port map ( I0 => Y(1), I1 => \v_count_reg[2]_rep_n_0\, I2 => \v_count_reg[3]_rep_n_0\, I3 => \char[0]_i_1_n_0\, I4 => \char[1]_i_1_n_0\, O => g27_b7_n_0 ); g28_b0: unisim.vcomponents.LUT6 generic map( INIT => X"0440082007C04020" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g28_b0_n_0 ); g28_b1: unisim.vcomponents.LUT6 generic map( INIT => X"0CE00FE00FE07FE0" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g28_b1_n_0 ); g28_b2: unisim.vcomponents.LUT6 generic map( INIT => X"09A00FC008207FC0" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g28_b2_n_0 ); g28_b3: unisim.vcomponents.LUT6 generic map( INIT => X"0920086048204820" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g28_b3_n_0 ); g28_b4: unisim.vcomponents.LUT6 generic map( INIT => X"0B2000207FC00820" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g28_b4_n_0 ); g28_b5: unisim.vcomponents.LUT6 generic map( INIT => X"0E6000E07FE00FE0" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g28_b5_n_0 ); g28_b6: unisim.vcomponents.LUT6 generic map( INIT => X"044000C0402007C0" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g28_b6_n_0 ); g29_b0: unisim.vcomponents.LUT6 generic map( INIT => X"07E001E007E00020" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g29_b0_n_0 ); g29_b1: unisim.vcomponents.LUT6 generic map( INIT => X"0FE003E00FE00020" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g29_b1_n_0 ); g29_b2: unisim.vcomponents.LUT6 generic map( INIT => X"0C000600080007F8" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g29_b2_n_0 ); g29_b3: unisim.vcomponents.LUT6 generic map( INIT => X"07000C0008000FFC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g29_b3_n_0 ); g29_b4: unisim.vcomponents.LUT6 generic map( INIT => X"07000C0007E00820" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g29_b4_n_0 ); g29_b5: unisim.vcomponents.LUT6 generic map( INIT => X"0C0006000FE00C20" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g29_b5_n_0 ); g29_b6: unisim.vcomponents.LUT6 generic map( INIT => X"0FE003E008000400" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g29_b6_n_0 ); g29_b7: unisim.vcomponents.LUT6 generic map( INIT => X"07E001E000000000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g29_b7_n_0 ); g2_b0: unisim.vcomponents.LUT6 generic map( INIT => X"0780FFFF0000FFFF" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g2_b0_n_0 ); g2_b1: unisim.vcomponents.LUT5 generic map( INIT => X"38E718FF" ) port map ( I0 => Y(1), I1 => \v_count_reg[2]_rep_n_0\, I2 => \v_count_reg[3]_rep_n_0\, I3 => \char[0]_i_1_n_0\, I4 => \char[1]_i_1_n_0\, O => g2_b1_n_0 ); g2_b2: unisim.vcomponents.LUT6 generic map( INIT => X"0860F99F0660FE7F" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g2_b2_n_0 ); g2_b3: unisim.vcomponents.LUT6 generic map( INIT => X"0874FBDF0420FC3F" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g2_b3_n_0 ); g2_b4: unisim.vcomponents.LUT6 generic map( INIT => X"0FDCFBDF0420FC3F" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g2_b4_n_0 ); g2_b5: unisim.vcomponents.LUT6 generic map( INIT => X"078CF99F0660FE7F" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g2_b5_n_0 ); g2_b6: unisim.vcomponents.LUT5 generic map( INIT => X"06E718FF" ) port map ( I0 => Y(1), I1 => \v_count_reg[2]_rep_n_0\, I2 => \v_count_reg[3]_rep_n_0\, I3 => \char[0]_i_1_n_0\, I4 => \char[1]_i_1_n_0\, O => g2_b6_n_0 ); g2_b7: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \char[0]_i_1_n_0\, O => g2_b7_n_0 ); g30_b0: unisim.vcomponents.LUT6 generic map( INIT => X"00000C6047E00820" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g30_b0_n_0 ); g30_b1: unisim.vcomponents.LUT6 generic map( INIT => X"00400E604FE00C60" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g30_b1_n_0 ); g30_b2: unisim.vcomponents.LUT6 generic map( INIT => X"00400B20480006C0" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g30_b2_n_0 ); g30_b3: unisim.vcomponents.LUT6 generic map( INIT => X"07F809A048000380" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g30_b3_n_0 ); g30_b4: unisim.vcomponents.LUT6 generic map( INIT => X"0FBC08E068000380" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g30_b4_n_0 ); g30_b5: unisim.vcomponents.LUT6 generic map( INIT => X"08040C603FE006C0" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g30_b5_n_0 ); g30_b6: unisim.vcomponents.LUT6 generic map( INIT => X"08040C201FE00C60" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g30_b6_n_0 ); g30_b7: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000820" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g30_b7_n_0 ); g31_b0: unisim.vcomponents.LUT6 generic map( INIT => X"0780000800000000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g31_b0_n_0 ); g31_b1: unisim.vcomponents.LUT6 generic map( INIT => X"07C0000C08040000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g31_b1_n_0 ); g31_b2: unisim.vcomponents.LUT6 generic map( INIT => X"0460000408040000" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g31_b2_n_0 ); g31_b3: unisim.vcomponents.LUT6 generic map( INIT => X"0430000C0FBC0FBC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g31_b3_n_0 ); g31_b4: unisim.vcomponents.LUT6 generic map( INIT => X"0460000807F80FBC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g31_b4_n_0 ); g31_b5: unisim.vcomponents.LUT6 generic map( INIT => X"07C0000C00400000" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g31_b5_n_0 ); g31_b6: unisim.vcomponents.LUT6 generic map( INIT => X"0780000400400000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g31_b6_n_0 ); g3_b0: unisim.vcomponents.LUT6 generic map( INIT => X"02A01C000C000000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g3_b0_n_0 ); g3_b1: unisim.vcomponents.LUT6 generic map( INIT => X"02A01FFC0E000278" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g3_b1_n_0 ); g3_b2: unisim.vcomponents.LUT6 generic map( INIT => X"01C00FFC0FFC02FC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g3_b2_n_0 ); g3_b3: unisim.vcomponents.LUT6 generic map( INIT => X"0F78001407FC0F84" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g3_b3_n_0 ); g3_b4: unisim.vcomponents.LUT6 generic map( INIT => X"0F78001400140F84" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g3_b4_n_0 ); g3_b5: unisim.vcomponents.LUT6 generic map( INIT => X"01C00E14001402FC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g3_b5_n_0 ); g3_b6: unisim.vcomponents.LUT6 generic map( INIT => X"02A00FFC001C0278" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g3_b6_n_0 ); g3_b7: unisim.vcomponents.LUT6 generic map( INIT => X"02A007FC001C0000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g3_b7_n_0 ); g4_b0: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000400FFE" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g4_b0_n_0 ); g4_b1: unisim.vcomponents.LUT6 generic map( INIT => X"0DFC0110004007FC" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g4_b1_n_0 ); g4_b2: unisim.vcomponents.LUT6 generic map( INIT => X"0DFC031800E003F8" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g4_b2_n_0 ); g4_b3: unisim.vcomponents.LUT6 generic map( INIT => X"000007FC01F001F0" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g4_b3_n_0 ); g4_b4: unisim.vcomponents.LUT6 generic map( INIT => X"000007FC03F800E0" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g4_b4_n_0 ); g4_b5: unisim.vcomponents.LUT6 generic map( INIT => X"0DFC031807FC0040" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g4_b5_n_0 ); g4_b6: unisim.vcomponents.LUT6 generic map( INIT => X"0DFC01100FFE0040" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g4_b6_n_0 ); g5_b0: unisim.vcomponents.LUT6 generic map( INIT => X"00000F0008C40038" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g5_b0_n_0 ); g5_b1: unisim.vcomponents.LUT6 generic map( INIT => X"09100F0019EE007C" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g5_b1_n_0 ); g5_b2: unisim.vcomponents.LUT6 generic map( INIT => X"1B180F00133A0044" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g5_b2_n_0 ); g5_b3: unisim.vcomponents.LUT6 generic map( INIT => X"1FFC0F0012120FFC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g5_b3_n_0 ); g5_b4: unisim.vcomponents.LUT6 generic map( INIT => X"0FFC0F0017320FFC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g5_b4_n_0 ); g5_b5: unisim.vcomponents.LUT6 generic map( INIT => X"0B180F001DE60004" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g5_b5_n_0 ); g5_b6: unisim.vcomponents.LUT6 generic map( INIT => X"09100F0008C40FFC" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g5_b6_n_0 ); g5_b7: unisim.vcomponents.LUT5 generic map( INIT => X"0000003E" ) port map ( I0 => Y(1), I1 => \v_count_reg[2]_rep_n_0\, I2 => \v_count_reg[3]_rep_n_0\, I3 => \char[0]_i_1_n_0\, I4 => \char[1]_i_1_n_0\, O => g5_b7_n_0 ); g6_b0: unisim.vcomponents.LUT5 generic map( INIT => X"00800000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[1]_i_1_n_0\, O => g6_b0_n_0 ); g6_b1: unisim.vcomponents.LUT6 generic map( INIT => X"01C0008002000010" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g6_b1_n_0 ); g6_b2: unisim.vcomponents.LUT6 generic map( INIT => X"03E0008006000018" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g6_b2_n_0 ); g6_b3: unisim.vcomponents.LUT5 generic map( INIT => X"02A00FFC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_2_n_0, O => g6_b3_n_0 ); g6_b4: unisim.vcomponents.LUT6 generic map( INIT => X"008003E00FFC0FFC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g6_b4_n_0 ); g6_b5: unisim.vcomponents.LUT6 generic map( INIT => X"008001C006000018" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g6_b5_n_0 ); g6_b6: unisim.vcomponents.LUT6 generic map( INIT => X"0080008002000010" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g6_b6_n_0 ); g7_b0: unisim.vcomponents.LUT6 generic map( INIT => X"00300600008003C0" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g7_b0_n_0 ); g7_b1: unisim.vcomponents.LUT6 generic map( INIT => X"00F0078001C003C0" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g7_b1_n_0 ); g7_b2: unisim.vcomponents.LUT6 generic map( INIT => X"03F007E003E00200" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g7_b2_n_0 ); g7_b3: unisim.vcomponents.LUT6 generic map( INIT => X"07F007F000800200" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g7_b3_n_0 ); g7_b4: unisim.vcomponents.LUT6 generic map( INIT => X"03F007E000800200" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g7_b4_n_0 ); g7_b5: unisim.vcomponents.LUT6 generic map( INIT => X"00F0078003E00200" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g7_b5_n_0 ); g7_b6: unisim.vcomponents.LUT6 generic map( INIT => X"0030060001C00200" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g7_b6_n_0 ); g7_b7: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000800000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g7_b7_n_0 ); g8_b0: unisim.vcomponents.LUT6 generic map( INIT => X"0220000000000000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g8_b0_n_0 ); g8_b1: unisim.vcomponents.LUT6 generic map( INIT => X"0FF8000E00000000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g8_b1_n_0 ); g8_b2: unisim.vcomponents.LUT6 generic map( INIT => X"0FF8001E00380000" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g8_b2_n_0 ); g8_b3: unisim.vcomponents.LUT6 generic map( INIT => X"022000000DFC0000" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g8_b3_n_0 ); g8_b4: unisim.vcomponents.LUT6 generic map( INIT => X"0FF800000DFC0000" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g8_b4_n_0 ); g8_b6: unisim.vcomponents.LUT6 generic map( INIT => X"0220000E00000000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g8_b6_n_0 ); g9_b0: unisim.vcomponents.LUT6 generic map( INIT => X"000007800C300638" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g9_b0_n_0 ); g9_b1: unisim.vcomponents.LUT6 generic map( INIT => X"00100FD806300C7C" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g9_b1_n_0 ); g9_b2: unisim.vcomponents.LUT6 generic map( INIT => X"001E087C03000844" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g9_b2_n_0 ); g9_b3: unisim.vcomponents.LUT6 generic map( INIT => X"000E08E401803847" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g9_b3_n_0 ); g9_b4: unisim.vcomponents.LUT6 generic map( INIT => X"000007BC00C03847" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g9_b4_n_0 ); g9_b5: unisim.vcomponents.LUT6 generic map( INIT => X"00000FD80C600FCC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g9_b5_n_0 ); g9_b6: unisim.vcomponents.LUT6 generic map( INIT => X"000008400C300798" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g9_b6_n_0 ); hSync_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"00000000AAFFAFC0" ) port map ( I0 => hSync_i_2_n_0, I1 => \h_count_reg__0\(4), I2 => \h_count_reg__0\(5), I3 => \h_count_reg__0\(7), I4 => \h_count_reg__0\(6), I5 => hSync_i_3_n_0, O => hSync_i_1_n_0 ); hSync_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000001" ) port map ( I0 => X(2), I1 => X(0), I2 => X(1), I3 => \h_count_reg__0\(3), I4 => \h_count_reg__0\(4), I5 => \h_count_reg__0\(6), O => hSync_i_2_n_0 ); hSync_i_3: unisim.vcomponents.LUT3 generic map( INIT => X"BF" ) port map ( I0 => \h_count_reg__0\(9), I1 => \h_count_reg__0\(8), I2 => \h_count_reg__0\(10), O => hSync_i_3_n_0 ); hSync_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => '1', D => hSync_i_1_n_0, Q => Hsync_OBUF, R => '0' ); \h_count[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => X(0), O => p_0_in(0) ); \h_count[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => X(0), I1 => X(1), O => p_0_in(1) ); \h_count[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => X(2), I1 => X(1), I2 => X(0), O => \h_count[2]_i_1_n_0\ ); \h_count_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => '1', D => p_0_in(0), Q => X(0), R => fbOutAddr_reg_i_1_n_0 ); \h_count_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => '1', D => fbOutAddr_reg_i_12_n_0, Q => \h_count_reg__0\(10), R => fbOutAddr_reg_i_1_n_0 ); \h_count_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => '1', D => p_0_in(1), Q => X(1), R => fbOutAddr_reg_i_1_n_0 ); \h_count_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => '1', D => \h_count[2]_i_1_n_0\, Q => X(2), R => fbOutAddr_reg_i_1_n_0 ); \h_count_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => '1', D => fbOutAddr_reg_i_19_n_0, Q => \h_count_reg__0\(3), R => fbOutAddr_reg_i_1_n_0 ); \h_count_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => '1', D => fbOutAddr_reg_i_18_n_0, Q => \h_count_reg__0\(4), R => fbOutAddr_reg_i_1_n_0 ); \h_count_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => '1', D => fbOutAddr_reg_i_17_n_0, Q => \h_count_reg__0\(5), R => fbOutAddr_reg_i_1_n_0 ); \h_count_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => '1', D => fbOutAddr_reg_i_16_n_0, Q => \h_count_reg__0\(6), R => fbOutAddr_reg_i_1_n_0 ); \h_count_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => '1', D => fbOutAddr_reg_i_15_n_0, Q => \h_count_reg__0\(7), R => fbOutAddr_reg_i_1_n_0 ); \h_count_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => '1', D => fbOutAddr_reg_i_14_n_0, Q => \h_count_reg__0\(8), R => fbOutAddr_reg_i_1_n_0 ); \h_count_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => '1', D => fbOutAddr_reg_i_13_n_0, Q => \h_count_reg__0\(9), R => fbOutAddr_reg_i_1_n_0 ); \nextChar[7]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"1000" ) port map ( I0 => X(1), I1 => X(0), I2 => enable, I3 => X(2), O => \nextChar[7]_i_1_n_0\ ); \nextChar_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => \nextChar[7]_i_1_n_0\, D => D(0), Q => nextChar(0), R => '0' ); \nextChar_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => \nextChar[7]_i_1_n_0\, D => D(1), Q => nextChar(1), R => '0' ); \nextChar_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => \nextChar[7]_i_1_n_0\, D => D(2), Q => nextChar(2), R => '0' ); \nextChar_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => \nextChar[7]_i_1_n_0\, D => D(3), Q => nextChar(3), R => '0' ); \nextChar_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => \nextChar[7]_i_1_n_0\, D => D(4), Q => nextChar(4), R => '0' ); \nextChar_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => \nextChar[7]_i_1_n_0\, D => D(5), Q => nextChar(5), R => '0' ); \nextChar_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => \nextChar[7]_i_1_n_0\, D => D(6), Q => nextChar(6), R => '0' ); \nextChar_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => \nextChar[7]_i_1_n_0\, D => D(7), Q => nextChar(7), R => '0' ); vSync_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"0000001E" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => vSync_i_2_n_0, I4 => fbOutAddr_reg_i_23_n_0, O => vSync_i_1_n_0 ); vSync_i_2: unisim.vcomponents.LUT4 generic map( INIT => X"FFEF" ) port map ( I0 => \v_count_reg__0\(4), I1 => Y(3), I2 => \v_count_reg__0\(10), I3 => \v_count_reg__0\(5), O => vSync_i_2_n_0 ); vSync_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => '1', D => vSync_i_1_n_0, Q => Vsync_OBUF, R => '0' ); \v_count[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => Y(0), O => \p_0_in__0\(0) ); \v_count[0]_rep_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => Y(0), O => \v_count[0]_rep_i_1_n_0\ ); \v_count[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => Y(0), I1 => Y(1), O => \p_0_in__0\(1) ); \v_count[1]_rep_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => Y(0), I1 => Y(1), O => \v_count[1]_rep_i_1_n_0\ ); \v_count[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => Y(2), I1 => Y(0), I2 => Y(1), O => \p_0_in__0\(2) ); \v_count[2]_rep_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => Y(2), I1 => Y(0), I2 => Y(1), O => \v_count[2]_rep_i_1_n_0\ ); \v_count[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"6AAA" ) port map ( I0 => Y(3), I1 => Y(1), I2 => Y(0), I3 => Y(2), O => \p_0_in__0\(3) ); \v_count[3]_rep__0_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"6AAA" ) port map ( I0 => Y(3), I1 => Y(1), I2 => Y(0), I3 => Y(2), O => \v_count[3]_rep__0_i_1_n_0\ ); \v_count[3]_rep_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"6AAA" ) port map ( I0 => Y(3), I1 => Y(1), I2 => Y(0), I3 => Y(2), O => \v_count[3]_rep_i_1_n_0\ ); \v_count_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => fbOutAddr_reg_i_1_n_0, D => \p_0_in__0\(0), Q => Y(0), R => fbOutAddr_reg_i_3_n_0 ); \v_count_reg[0]_rep\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => fbOutAddr_reg_i_1_n_0, D => \v_count[0]_rep_i_1_n_0\, Q => \v_count_reg[0]_rep_n_0\, R => fbOutAddr_reg_i_3_n_0 ); \v_count_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => fbOutAddr_reg_i_1_n_0, D => fbOutAddr_reg_i_5_n_0, Q => \v_count_reg__0\(10), R => fbOutAddr_reg_i_3_n_0 ); \v_count_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => fbOutAddr_reg_i_1_n_0, D => \p_0_in__0\(1), Q => Y(1), R => fbOutAddr_reg_i_3_n_0 ); \v_count_reg[1]_rep\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => fbOutAddr_reg_i_1_n_0, D => \v_count[1]_rep_i_1_n_0\, Q => \v_count_reg[1]_rep_n_0\, R => fbOutAddr_reg_i_3_n_0 ); \v_count_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => fbOutAddr_reg_i_1_n_0, D => \p_0_in__0\(2), Q => Y(2), R => fbOutAddr_reg_i_3_n_0 ); \v_count_reg[2]_rep\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => fbOutAddr_reg_i_1_n_0, D => \v_count[2]_rep_i_1_n_0\, Q => \v_count_reg[2]_rep_n_0\, R => fbOutAddr_reg_i_3_n_0 ); \v_count_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => fbOutAddr_reg_i_1_n_0, D => \p_0_in__0\(3), Q => Y(3), R => fbOutAddr_reg_i_3_n_0 ); \v_count_reg[3]_rep\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => fbOutAddr_reg_i_1_n_0, D => \v_count[3]_rep_i_1_n_0\, Q => \v_count_reg[3]_rep_n_0\, R => fbOutAddr_reg_i_3_n_0 ); \v_count_reg[3]_rep__0\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => fbOutAddr_reg_i_1_n_0, D => \v_count[3]_rep__0_i_1_n_0\, Q => \v_count_reg[3]_rep__0_n_0\, R => fbOutAddr_reg_i_3_n_0 ); \v_count_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => fbOutAddr_reg_i_1_n_0, D => fbOutAddr_reg_i_11_n_0, Q => \v_count_reg__0\(4), R => fbOutAddr_reg_i_3_n_0 ); \v_count_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => fbOutAddr_reg_i_1_n_0, D => fbOutAddr_reg_i_10_n_0, Q => \v_count_reg__0\(5), R => fbOutAddr_reg_i_3_n_0 ); \v_count_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => fbOutAddr_reg_i_1_n_0, D => fbOutAddr_reg_i_9_n_0, Q => \v_count_reg__0\(6), R => fbOutAddr_reg_i_3_n_0 ); \v_count_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => fbOutAddr_reg_i_1_n_0, D => fbOutAddr_reg_i_8_n_0, Q => \v_count_reg__0\(7), R => fbOutAddr_reg_i_3_n_0 ); \v_count_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => fbOutAddr_reg_i_1_n_0, D => fbOutAddr_reg_i_7_n_0, Q => \v_count_reg__0\(8), R => fbOutAddr_reg_i_3_n_0 ); \v_count_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => fbOutAddr_reg_i_1_n_0, D => fbOutAddr_reg_i_6_n_0, Q => \v_count_reg__0\(9), R => fbOutAddr_reg_i_3_n_0 ); \vgaRed[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"28222888" ) port map ( I0 => enable, I1 => \char[7]_i_1_n_0\, I2 => \vgaRed_reg[0]_i_2_n_0\, I3 => X(2), I4 => \vgaRed_reg[0]_i_3_n_0\, O => \vgaRed[0]_i_1_n_0\ ); \vgaRed[0]_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \vgaRed_reg[0]_i_32_n_0\, I1 => \vgaRed[0]_i_33_n_0\, I2 => \char[5]_i_1_n_0\, I3 => \vgaRed[0]_i_34_n_0\, I4 => \char[4]_i_1_n_0\, I5 => \vgaRed_reg[0]_i_35_n_0\, O => \vgaRed[0]_i_10_n_0\ ); \vgaRed[0]_i_11\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \vgaRed_reg[0]_i_36_n_0\, I1 => \vgaRed_reg[0]_i_37_n_0\, I2 => \char[5]_i_1_n_0\, I3 => \vgaRed_reg[0]_i_38_n_0\, I4 => \char[4]_i_1_n_0\, I5 => \vgaRed_reg[0]_i_39_n_0\, O => \vgaRed[0]_i_11_n_0\ ); \vgaRed[0]_i_13\: unisim.vcomponents.LUT6 generic map( INIT => X"0020FFFF00200000" ) port map ( I0 => g10_b0_n_0, I1 => \char[2]_i_1_n_0\, I2 => \char[3]_i_1_n_0\, I3 => \char[4]_i_1_n_0\, I4 => \char[5]_i_1_n_0\, I5 => \vgaRed[0]_i_42_n_0\, O => \vgaRed[0]_i_13_n_0\ ); \vgaRed[0]_i_14\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \vgaRed_reg[0]_i_43_n_0\, I1 => \vgaRed_reg[0]_i_44_n_0\, I2 => \char[5]_i_1_n_0\, I3 => \vgaRed_reg[0]_i_45_n_0\, I4 => \char[4]_i_1_n_0\, I5 => \vgaRed_reg[0]_i_46_n_0\, O => \vgaRed[0]_i_14_n_0\ ); \vgaRed[0]_i_15\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \vgaRed_reg[0]_i_47_n_0\, I1 => \vgaRed[0]_i_48_n_0\, I2 => \char[5]_i_1_n_0\, I3 => \vgaRed_reg[0]_i_49_n_0\, I4 => \char[4]_i_1_n_0\, I5 => \vgaRed_reg[0]_i_50_n_0\, O => \vgaRed[0]_i_15_n_0\ ); \vgaRed[0]_i_16\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \vgaRed_reg[0]_i_51_n_0\, I1 => \vgaRed_reg[0]_i_52_n_0\, I2 => \char[5]_i_1_n_0\, I3 => \vgaRed_reg[0]_i_53_n_0\, I4 => \char[4]_i_1_n_0\, I5 => \vgaRed_reg[0]_i_54_n_0\, O => \vgaRed[0]_i_16_n_0\ ); \vgaRed[0]_i_17\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \vgaRed_reg[0]_i_55_n_0\, I1 => \vgaRed[0]_i_56_n_0\, I2 => \char[5]_i_1_n_0\, I3 => \vgaRed_reg[0]_i_57_n_0\, I4 => \char[4]_i_1_n_0\, I5 => \vgaRed_reg[0]_i_58_n_0\, O => \vgaRed[0]_i_17_n_0\ ); \vgaRed[0]_i_18\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \vgaRed_reg[0]_i_59_n_0\, I1 => \vgaRed_reg[0]_i_60_n_0\, I2 => \char[5]_i_1_n_0\, I3 => \vgaRed_reg[0]_i_61_n_0\, I4 => \char[4]_i_1_n_0\, I5 => \vgaRed_reg[0]_i_62_n_0\, O => \vgaRed[0]_i_18_n_0\ ); \vgaRed[0]_i_19\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \vgaRed_reg[0]_i_63_n_0\, I1 => \vgaRed[0]_i_64_n_0\, I2 => \char[5]_i_1_n_0\, I3 => \vgaRed_reg[0]_i_65_n_0\, I4 => \char[4]_i_1_n_0\, I5 => \vgaRed_reg[0]_i_66_n_0\, O => \vgaRed[0]_i_19_n_0\ ); \vgaRed[0]_i_20\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \vgaRed_reg[0]_i_67_n_0\, I1 => \vgaRed[0]_i_68_n_0\, I2 => \char[5]_i_1_n_0\, I3 => \vgaRed[0]_i_69_n_0\, I4 => \char[4]_i_1_n_0\, I5 => \vgaRed_reg[0]_i_70_n_0\, O => \vgaRed[0]_i_20_n_0\ ); \vgaRed[0]_i_21\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \vgaRed_reg[0]_i_71_n_0\, I1 => \vgaRed_reg[0]_i_72_n_0\, I2 => \char[5]_i_1_n_0\, I3 => \vgaRed_reg[0]_i_73_n_0\, I4 => \char[4]_i_1_n_0\, I5 => \vgaRed_reg[0]_i_74_n_0\, O => \vgaRed[0]_i_21_n_0\ ); \vgaRed[0]_i_22\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \vgaRed_reg[0]_i_75_n_0\, I1 => \vgaRed_reg[0]_i_76_n_0\, I2 => \char[5]_i_1_n_0\, I3 => \vgaRed_reg[0]_i_77_n_0\, I4 => \char[4]_i_1_n_0\, I5 => \vgaRed_reg[0]_i_78_n_0\, O => \vgaRed[0]_i_22_n_0\ ); \vgaRed[0]_i_23\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \vgaRed_reg[0]_i_79_n_0\, I1 => \vgaRed[0]_i_80_n_0\, I2 => \char[5]_i_1_n_0\, I3 => \vgaRed_reg[0]_i_81_n_0\, I4 => \char[4]_i_1_n_0\, I5 => \vgaRed_reg[0]_i_82_n_0\, O => \vgaRed[0]_i_23_n_0\ ); \vgaRed[0]_i_29\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => g11_b5_n_0, I1 => g10_b5_n_0, I2 => \char[3]_i_1_n_0\, I3 => g9_b5_n_0, I4 => \char[2]_i_1_n_0\, I5 => g8_b2_n_0, O => \vgaRed[0]_i_29_n_0\ ); \vgaRed[0]_i_33\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => g27_b3_n_0, I1 => g26_b4_n_0, I2 => \char[3]_i_1_n_0\, I3 => g25_b4_n_0, I4 => \char[2]_i_1_n_0\, I5 => g24_b4_n_0, O => \vgaRed[0]_i_33_n_0\ ); \vgaRed[0]_i_34\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => g23_b4_n_0, I1 => g22_b4_n_0, I2 => \char[3]_i_1_n_0\, I3 => g21_b3_n_0, I4 => \char[2]_i_1_n_0\, I5 => g20_b4_n_0, O => \vgaRed[0]_i_34_n_0\ ); \vgaRed[0]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \vgaRed[0]_i_8_n_0\, I1 => \vgaRed[0]_i_9_n_0\, I2 => X(0), I3 => \vgaRed[0]_i_10_n_0\, I4 => \char[6]_i_1_n_0\, I5 => \vgaRed[0]_i_11_n_0\, O => \vgaRed[0]_i_4_n_0\ ); \vgaRed[0]_i_40\: unisim.vcomponents.LUT6 generic map( INIT => X"AFC0A0C0A000A000" ) port map ( I0 => \vgaRed_reg[0]_i_109_n_0\, I1 => g21_b7_n_0, I2 => \char[4]_i_1_n_0\, I3 => \char[3]_i_1_n_0\, I4 => g19_b7_n_0, I5 => \char[2]_i_1_n_0\, O => \vgaRed[0]_i_40_n_0\ ); \vgaRed[0]_i_41\: unisim.vcomponents.LUT6 generic map( INIT => X"0FC000C0A000A000" ) port map ( I0 => g30_b7_n_0, I1 => g29_b7_n_0, I2 => \char[4]_i_1_n_0\, I3 => \char[3]_i_1_n_0\, I4 => g27_b7_n_0, I5 => \char[2]_i_1_n_0\, O => \vgaRed[0]_i_41_n_0\ ); \vgaRed[0]_i_42\: unisim.vcomponents.LUT6 generic map( INIT => X"B080FFFFB0800000" ) port map ( I0 => g7_b7_n_0, I1 => \char[3]_i_1_n_0\, I2 => \char[2]_i_1_n_0\, I3 => g5_b7_n_0, I4 => \char[4]_i_1_n_0\, I5 => \vgaRed_reg[0]_i_110_n_0\, O => \vgaRed[0]_i_42_n_0\ ); \vgaRed[0]_i_48\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => g11_b6_n_0, I1 => g10_b1_n_0, I2 => \char[3]_i_1_n_0\, I3 => g9_b6_n_0, I4 => \char[2]_i_1_n_0\, I5 => g8_b6_n_0, O => \vgaRed[0]_i_48_n_0\ ); \vgaRed[0]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \vgaRed_reg[0]_i_12_n_0\, I1 => \vgaRed[0]_i_13_n_0\, I2 => X(0), I3 => \vgaRed[0]_i_14_n_0\, I4 => \char[6]_i_1_n_0\, I5 => \vgaRed[0]_i_15_n_0\, O => \vgaRed[0]_i_5_n_0\ ); \vgaRed[0]_i_56\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => g11_b1_n_0, I1 => g10_b1_n_0, I2 => \char[3]_i_1_n_0\, I3 => g9_b1_n_0, I4 => \char[2]_i_1_n_0\, I5 => g8_b1_n_0, O => \vgaRed[0]_i_56_n_0\ ); \vgaRed[0]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \vgaRed[0]_i_16_n_0\, I1 => \vgaRed[0]_i_17_n_0\, I2 => X(0), I3 => \vgaRed[0]_i_18_n_0\, I4 => \char[6]_i_1_n_0\, I5 => \vgaRed[0]_i_19_n_0\, O => \vgaRed[0]_i_6_n_0\ ); \vgaRed[0]_i_64\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => g11_b0_n_0, I1 => g10_b0_n_0, I2 => \char[3]_i_1_n_0\, I3 => g9_b0_n_0, I4 => \char[2]_i_1_n_0\, I5 => g8_b0_n_0, O => \vgaRed[0]_i_64_n_0\ ); \vgaRed[0]_i_68\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => g27_b3_n_0, I1 => g26_b3_n_0, I2 => \char[3]_i_1_n_0\, I3 => g25_b3_n_0, I4 => \char[2]_i_1_n_0\, I5 => g24_b3_n_0, O => \vgaRed[0]_i_68_n_0\ ); \vgaRed[0]_i_69\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => g23_b3_n_0, I1 => g22_b3_n_0, I2 => \char[3]_i_1_n_0\, I3 => g21_b3_n_0, I4 => \char[2]_i_1_n_0\, I5 => g20_b3_n_0, O => \vgaRed[0]_i_69_n_0\ ); \vgaRed[0]_i_7\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \vgaRed[0]_i_20_n_0\, I1 => \vgaRed[0]_i_21_n_0\, I2 => X(0), I3 => \vgaRed[0]_i_22_n_0\, I4 => \char[6]_i_1_n_0\, I5 => \vgaRed[0]_i_23_n_0\, O => \vgaRed[0]_i_7_n_0\ ); \vgaRed[0]_i_8\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \vgaRed_reg[0]_i_24_n_0\, I1 => \vgaRed_reg[0]_i_25_n_0\, I2 => \char[5]_i_1_n_0\, I3 => \vgaRed_reg[0]_i_26_n_0\, I4 => \char[4]_i_1_n_0\, I5 => \vgaRed_reg[0]_i_27_n_0\, O => \vgaRed[0]_i_8_n_0\ ); \vgaRed[0]_i_80\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => g11_b2_n_0, I1 => g10_b2_n_0, I2 => \char[3]_i_1_n_0\, I3 => g9_b2_n_0, I4 => \char[2]_i_1_n_0\, I5 => g8_b2_n_0, O => \vgaRed[0]_i_80_n_0\ ); \vgaRed[0]_i_9\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \vgaRed_reg[0]_i_28_n_0\, I1 => \vgaRed[0]_i_29_n_0\, I2 => \char[5]_i_1_n_0\, I3 => \vgaRed_reg[0]_i_30_n_0\, I4 => \char[4]_i_1_n_0\, I5 => \vgaRed_reg[0]_i_31_n_0\, O => \vgaRed[0]_i_9_n_0\ ); \vgaRed_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => '1', D => \vgaRed[0]_i_1_n_0\, Q => vgaBlue_OBUF(0), R => '0' ); \vgaRed_reg[0]_i_100\: unisim.vcomponents.MUXF7 port map ( I0 => g18_b4_n_0, I1 => g19_b4_n_0, O => \vgaRed_reg[0]_i_100_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_101\: unisim.vcomponents.MUXF7 port map ( I0 => g12_b4_n_0, I1 => g13_b4_n_0, O => \vgaRed_reg[0]_i_101_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_102\: unisim.vcomponents.MUXF7 port map ( I0 => g14_b4_n_0, I1 => g15_b4_n_0, O => \vgaRed_reg[0]_i_102_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_103\: unisim.vcomponents.MUXF7 port map ( I0 => g8_b4_n_0, I1 => g9_b4_n_0, O => \vgaRed_reg[0]_i_103_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_104\: unisim.vcomponents.MUXF7 port map ( I0 => g10_b4_n_0, I1 => g11_b4_n_0, O => \vgaRed_reg[0]_i_104_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_105\: unisim.vcomponents.MUXF7 port map ( I0 => g4_b4_n_0, I1 => g5_b4_n_0, O => \vgaRed_reg[0]_i_105_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_106\: unisim.vcomponents.MUXF7 port map ( I0 => g6_b4_n_0, I1 => g7_b4_n_0, O => \vgaRed_reg[0]_i_106_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_107\: unisim.vcomponents.MUXF7 port map ( I0 => g0_b4_n_0, I1 => g1_b4_n_0, O => \vgaRed_reg[0]_i_107_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_108\: unisim.vcomponents.MUXF7 port map ( I0 => g2_b4_n_0, I1 => g3_b4_n_0, O => \vgaRed_reg[0]_i_108_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_109\: unisim.vcomponents.MUXF7 port map ( I0 => g22_b7_n_0, I1 => g23_b7_n_0, O => \vgaRed_reg[0]_i_109_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_110\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_179_n_0\, I1 => \vgaRed_reg[0]_i_180_n_0\, O => \vgaRed_reg[0]_i_110_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_111\: unisim.vcomponents.MUXF7 port map ( I0 => g28_b6_n_0, I1 => g29_b6_n_0, O => \vgaRed_reg[0]_i_111_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_112\: unisim.vcomponents.MUXF7 port map ( I0 => g30_b6_n_0, I1 => g31_b6_n_0, O => \vgaRed_reg[0]_i_112_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_113\: unisim.vcomponents.MUXF7 port map ( I0 => g24_b6_n_0, I1 => g25_b6_n_0, O => \vgaRed_reg[0]_i_113_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_114\: unisim.vcomponents.MUXF7 port map ( I0 => g26_b6_n_0, I1 => g27_b6_n_0, O => \vgaRed_reg[0]_i_114_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_115\: unisim.vcomponents.MUXF7 port map ( I0 => g20_b6_n_0, I1 => g21_b6_n_0, O => \vgaRed_reg[0]_i_115_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_116\: unisim.vcomponents.MUXF7 port map ( I0 => g22_b6_n_0, I1 => g23_b6_n_0, O => \vgaRed_reg[0]_i_116_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_117\: unisim.vcomponents.MUXF7 port map ( I0 => g16_b6_n_0, I1 => g17_b6_n_0, O => \vgaRed_reg[0]_i_117_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_118\: unisim.vcomponents.MUXF7 port map ( I0 => g18_b6_n_0, I1 => g19_b6_n_0, O => \vgaRed_reg[0]_i_118_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_119\: unisim.vcomponents.MUXF7 port map ( I0 => g12_b6_n_0, I1 => g13_b6_n_0, O => \vgaRed_reg[0]_i_119_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_12\: unisim.vcomponents.MUXF7 port map ( I0 => \vgaRed[0]_i_40_n_0\, I1 => \vgaRed[0]_i_41_n_0\, O => \vgaRed_reg[0]_i_12_n_0\, S => \char[5]_i_1_n_0\ ); \vgaRed_reg[0]_i_120\: unisim.vcomponents.MUXF7 port map ( I0 => g14_b6_n_0, I1 => g15_b6_n_0, O => \vgaRed_reg[0]_i_120_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_121\: unisim.vcomponents.MUXF7 port map ( I0 => g4_b6_n_0, I1 => g5_b6_n_0, O => \vgaRed_reg[0]_i_121_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_122\: unisim.vcomponents.MUXF7 port map ( I0 => g6_b6_n_0, I1 => g7_b6_n_0, O => \vgaRed_reg[0]_i_122_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_123\: unisim.vcomponents.MUXF7 port map ( I0 => g0_b6_n_0, I1 => g1_b6_n_0, O => \vgaRed_reg[0]_i_123_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_124\: unisim.vcomponents.MUXF7 port map ( I0 => g2_b6_n_0, I1 => g3_b6_n_0, O => \vgaRed_reg[0]_i_124_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_125\: unisim.vcomponents.MUXF7 port map ( I0 => g28_b1_n_0, I1 => g29_b1_n_0, O => \vgaRed_reg[0]_i_125_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_126\: unisim.vcomponents.MUXF7 port map ( I0 => g30_b1_n_0, I1 => g31_b1_n_0, O => \vgaRed_reg[0]_i_126_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_127\: unisim.vcomponents.MUXF7 port map ( I0 => g24_b1_n_0, I1 => g25_b1_n_0, O => \vgaRed_reg[0]_i_127_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_128\: unisim.vcomponents.MUXF7 port map ( I0 => g26_b1_n_0, I1 => g27_b1_n_0, O => \vgaRed_reg[0]_i_128_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_129\: unisim.vcomponents.MUXF7 port map ( I0 => g20_b1_n_0, I1 => g21_b1_n_0, O => \vgaRed_reg[0]_i_129_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_130\: unisim.vcomponents.MUXF7 port map ( I0 => g22_b1_n_0, I1 => g23_b1_n_0, O => \vgaRed_reg[0]_i_130_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_131\: unisim.vcomponents.MUXF7 port map ( I0 => g16_b1_n_0, I1 => g17_b1_n_0, O => \vgaRed_reg[0]_i_131_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_132\: unisim.vcomponents.MUXF7 port map ( I0 => g18_b1_n_0, I1 => g19_b1_n_0, O => \vgaRed_reg[0]_i_132_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_133\: unisim.vcomponents.MUXF7 port map ( I0 => g12_b1_n_0, I1 => g13_b1_n_0, O => \vgaRed_reg[0]_i_133_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_134\: unisim.vcomponents.MUXF7 port map ( I0 => g14_b1_n_0, I1 => g15_b1_n_0, O => \vgaRed_reg[0]_i_134_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_135\: unisim.vcomponents.MUXF7 port map ( I0 => g4_b1_n_0, I1 => g5_b1_n_0, O => \vgaRed_reg[0]_i_135_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_136\: unisim.vcomponents.MUXF7 port map ( I0 => g6_b1_n_0, I1 => g7_b1_n_0, O => \vgaRed_reg[0]_i_136_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_137\: unisim.vcomponents.MUXF7 port map ( I0 => g0_b1_n_0, I1 => g1_b1_n_0, O => \vgaRed_reg[0]_i_137_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_138\: unisim.vcomponents.MUXF7 port map ( I0 => g2_b1_n_0, I1 => g3_b1_n_0, O => \vgaRed_reg[0]_i_138_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_139\: unisim.vcomponents.MUXF7 port map ( I0 => g28_b0_n_0, I1 => g29_b0_n_0, O => \vgaRed_reg[0]_i_139_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_140\: unisim.vcomponents.MUXF7 port map ( I0 => g30_b0_n_0, I1 => g31_b0_n_0, O => \vgaRed_reg[0]_i_140_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_141\: unisim.vcomponents.MUXF7 port map ( I0 => g24_b0_n_0, I1 => g25_b0_n_0, O => \vgaRed_reg[0]_i_141_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_142\: unisim.vcomponents.MUXF7 port map ( I0 => g26_b0_n_0, I1 => g27_b0_n_0, O => \vgaRed_reg[0]_i_142_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_143\: unisim.vcomponents.MUXF7 port map ( I0 => g20_b0_n_0, I1 => g21_b0_n_0, O => \vgaRed_reg[0]_i_143_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_144\: unisim.vcomponents.MUXF7 port map ( I0 => g22_b0_n_0, I1 => g23_b0_n_0, O => \vgaRed_reg[0]_i_144_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_145\: unisim.vcomponents.MUXF7 port map ( I0 => g16_b0_n_0, I1 => g17_b0_n_0, O => \vgaRed_reg[0]_i_145_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_146\: unisim.vcomponents.MUXF7 port map ( I0 => g18_b0_n_0, I1 => g19_b0_n_0, O => \vgaRed_reg[0]_i_146_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_147\: unisim.vcomponents.MUXF7 port map ( I0 => g12_b0_n_0, I1 => g13_b0_n_0, O => \vgaRed_reg[0]_i_147_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_148\: unisim.vcomponents.MUXF7 port map ( I0 => g14_b0_n_0, I1 => g15_b0_n_0, O => \vgaRed_reg[0]_i_148_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_149\: unisim.vcomponents.MUXF7 port map ( I0 => g4_b0_n_0, I1 => g5_b0_n_0, O => \vgaRed_reg[0]_i_149_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_150\: unisim.vcomponents.MUXF7 port map ( I0 => g6_b0_n_0, I1 => g7_b0_n_0, O => \vgaRed_reg[0]_i_150_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_151\: unisim.vcomponents.MUXF7 port map ( I0 => g0_b0_n_0, I1 => g1_b0_n_0, O => \vgaRed_reg[0]_i_151_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_152\: unisim.vcomponents.MUXF7 port map ( I0 => g2_b0_n_0, I1 => g3_b0_n_0, O => \vgaRed_reg[0]_i_152_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_153\: unisim.vcomponents.MUXF7 port map ( I0 => g28_b3_n_0, I1 => g29_b3_n_0, O => \vgaRed_reg[0]_i_153_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_154\: unisim.vcomponents.MUXF7 port map ( I0 => g30_b3_n_0, I1 => g31_b3_n_0, O => \vgaRed_reg[0]_i_154_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_155\: unisim.vcomponents.MUXF7 port map ( I0 => g16_b3_n_0, I1 => g17_b3_n_0, O => \vgaRed_reg[0]_i_155_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_156\: unisim.vcomponents.MUXF7 port map ( I0 => g18_b3_n_0, I1 => g19_b3_n_0, O => \vgaRed_reg[0]_i_156_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_157\: unisim.vcomponents.MUXF7 port map ( I0 => g12_b3_n_0, I1 => g13_b3_n_0, O => \vgaRed_reg[0]_i_157_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_158\: unisim.vcomponents.MUXF7 port map ( I0 => g14_b3_n_0, I1 => g15_b3_n_0, O => \vgaRed_reg[0]_i_158_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_159\: unisim.vcomponents.MUXF7 port map ( I0 => g8_b3_n_0, I1 => g9_b3_n_0, O => \vgaRed_reg[0]_i_159_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_160\: unisim.vcomponents.MUXF7 port map ( I0 => g10_b3_n_0, I1 => g11_b3_n_0, O => \vgaRed_reg[0]_i_160_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_161\: unisim.vcomponents.MUXF7 port map ( I0 => g4_b3_n_0, I1 => g5_b3_n_0, O => \vgaRed_reg[0]_i_161_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_162\: unisim.vcomponents.MUXF7 port map ( I0 => g6_b3_n_0, I1 => g7_b3_n_0, O => \vgaRed_reg[0]_i_162_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_163\: unisim.vcomponents.MUXF7 port map ( I0 => g0_b3_n_0, I1 => g1_b3_n_0, O => \vgaRed_reg[0]_i_163_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_164\: unisim.vcomponents.MUXF7 port map ( I0 => g2_b3_n_0, I1 => g3_b3_n_0, O => \vgaRed_reg[0]_i_164_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_165\: unisim.vcomponents.MUXF7 port map ( I0 => g28_b2_n_0, I1 => g29_b2_n_0, O => \vgaRed_reg[0]_i_165_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_166\: unisim.vcomponents.MUXF7 port map ( I0 => g30_b2_n_0, I1 => g31_b2_n_0, O => \vgaRed_reg[0]_i_166_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_167\: unisim.vcomponents.MUXF7 port map ( I0 => g24_b2_n_0, I1 => g25_b2_n_0, O => \vgaRed_reg[0]_i_167_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_168\: unisim.vcomponents.MUXF7 port map ( I0 => g26_b2_n_0, I1 => g27_b2_n_0, O => \vgaRed_reg[0]_i_168_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_169\: unisim.vcomponents.MUXF7 port map ( I0 => g20_b2_n_0, I1 => g21_b2_n_0, O => \vgaRed_reg[0]_i_169_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_170\: unisim.vcomponents.MUXF7 port map ( I0 => g22_b2_n_0, I1 => g23_b2_n_0, O => \vgaRed_reg[0]_i_170_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_171\: unisim.vcomponents.MUXF7 port map ( I0 => g16_b2_n_0, I1 => g17_b2_n_0, O => \vgaRed_reg[0]_i_171_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_172\: unisim.vcomponents.MUXF7 port map ( I0 => g18_b2_n_0, I1 => g19_b2_n_0, O => \vgaRed_reg[0]_i_172_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_173\: unisim.vcomponents.MUXF7 port map ( I0 => g12_b2_n_0, I1 => g13_b2_n_0, O => \vgaRed_reg[0]_i_173_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_174\: unisim.vcomponents.MUXF7 port map ( I0 => g14_b2_n_0, I1 => g15_b2_n_0, O => \vgaRed_reg[0]_i_174_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_175\: unisim.vcomponents.MUXF7 port map ( I0 => g4_b2_n_0, I1 => g5_b2_n_0, O => \vgaRed_reg[0]_i_175_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_176\: unisim.vcomponents.MUXF7 port map ( I0 => g6_b2_n_0, I1 => g7_b2_n_0, O => \vgaRed_reg[0]_i_176_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_177\: unisim.vcomponents.MUXF7 port map ( I0 => g0_b2_n_0, I1 => g1_b2_n_0, O => \vgaRed_reg[0]_i_177_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_178\: unisim.vcomponents.MUXF7 port map ( I0 => g2_b2_n_0, I1 => g3_b2_n_0, O => \vgaRed_reg[0]_i_178_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_179\: unisim.vcomponents.MUXF7 port map ( I0 => g0_b7_n_0, I1 => g1_b7_n_0, O => \vgaRed_reg[0]_i_179_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_180\: unisim.vcomponents.MUXF7 port map ( I0 => g2_b7_n_0, I1 => g3_b7_n_0, O => \vgaRed_reg[0]_i_180_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_2\: unisim.vcomponents.MUXF7 port map ( I0 => \vgaRed[0]_i_4_n_0\, I1 => \vgaRed[0]_i_5_n_0\, O => \vgaRed_reg[0]_i_2_n_0\, S => X(1) ); \vgaRed_reg[0]_i_24\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_83_n_0\, I1 => \vgaRed_reg[0]_i_84_n_0\, O => \vgaRed_reg[0]_i_24_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_25\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_85_n_0\, I1 => \vgaRed_reg[0]_i_86_n_0\, O => \vgaRed_reg[0]_i_25_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_26\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_87_n_0\, I1 => \vgaRed_reg[0]_i_88_n_0\, O => \vgaRed_reg[0]_i_26_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_27\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_89_n_0\, I1 => \vgaRed_reg[0]_i_90_n_0\, O => \vgaRed_reg[0]_i_27_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_28\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_91_n_0\, I1 => \vgaRed_reg[0]_i_92_n_0\, O => \vgaRed_reg[0]_i_28_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_3\: unisim.vcomponents.MUXF7 port map ( I0 => \vgaRed[0]_i_6_n_0\, I1 => \vgaRed[0]_i_7_n_0\, O => \vgaRed_reg[0]_i_3_n_0\, S => X(1) ); \vgaRed_reg[0]_i_30\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_93_n_0\, I1 => \vgaRed_reg[0]_i_94_n_0\, O => \vgaRed_reg[0]_i_30_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_31\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_95_n_0\, I1 => \vgaRed_reg[0]_i_96_n_0\, O => \vgaRed_reg[0]_i_31_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_32\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_97_n_0\, I1 => \vgaRed_reg[0]_i_98_n_0\, O => \vgaRed_reg[0]_i_32_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_35\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_99_n_0\, I1 => \vgaRed_reg[0]_i_100_n_0\, O => \vgaRed_reg[0]_i_35_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_36\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_101_n_0\, I1 => \vgaRed_reg[0]_i_102_n_0\, O => \vgaRed_reg[0]_i_36_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_37\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_103_n_0\, I1 => \vgaRed_reg[0]_i_104_n_0\, O => \vgaRed_reg[0]_i_37_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_38\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_105_n_0\, I1 => \vgaRed_reg[0]_i_106_n_0\, O => \vgaRed_reg[0]_i_38_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_39\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_107_n_0\, I1 => \vgaRed_reg[0]_i_108_n_0\, O => \vgaRed_reg[0]_i_39_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_43\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_111_n_0\, I1 => \vgaRed_reg[0]_i_112_n_0\, O => \vgaRed_reg[0]_i_43_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_44\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_113_n_0\, I1 => \vgaRed_reg[0]_i_114_n_0\, O => \vgaRed_reg[0]_i_44_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_45\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_115_n_0\, I1 => \vgaRed_reg[0]_i_116_n_0\, O => \vgaRed_reg[0]_i_45_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_46\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_117_n_0\, I1 => \vgaRed_reg[0]_i_118_n_0\, O => \vgaRed_reg[0]_i_46_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_47\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_119_n_0\, I1 => \vgaRed_reg[0]_i_120_n_0\, O => \vgaRed_reg[0]_i_47_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_49\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_121_n_0\, I1 => \vgaRed_reg[0]_i_122_n_0\, O => \vgaRed_reg[0]_i_49_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_50\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_123_n_0\, I1 => \vgaRed_reg[0]_i_124_n_0\, O => \vgaRed_reg[0]_i_50_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_51\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_125_n_0\, I1 => \vgaRed_reg[0]_i_126_n_0\, O => \vgaRed_reg[0]_i_51_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_52\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_127_n_0\, I1 => \vgaRed_reg[0]_i_128_n_0\, O => \vgaRed_reg[0]_i_52_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_53\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_129_n_0\, I1 => \vgaRed_reg[0]_i_130_n_0\, O => \vgaRed_reg[0]_i_53_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_54\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_131_n_0\, I1 => \vgaRed_reg[0]_i_132_n_0\, O => \vgaRed_reg[0]_i_54_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_55\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_133_n_0\, I1 => \vgaRed_reg[0]_i_134_n_0\, O => \vgaRed_reg[0]_i_55_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_57\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_135_n_0\, I1 => \vgaRed_reg[0]_i_136_n_0\, O => \vgaRed_reg[0]_i_57_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_58\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_137_n_0\, I1 => \vgaRed_reg[0]_i_138_n_0\, O => \vgaRed_reg[0]_i_58_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_59\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_139_n_0\, I1 => \vgaRed_reg[0]_i_140_n_0\, O => \vgaRed_reg[0]_i_59_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_60\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_141_n_0\, I1 => \vgaRed_reg[0]_i_142_n_0\, O => \vgaRed_reg[0]_i_60_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_61\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_143_n_0\, I1 => \vgaRed_reg[0]_i_144_n_0\, O => \vgaRed_reg[0]_i_61_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_62\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_145_n_0\, I1 => \vgaRed_reg[0]_i_146_n_0\, O => \vgaRed_reg[0]_i_62_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_63\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_147_n_0\, I1 => \vgaRed_reg[0]_i_148_n_0\, O => \vgaRed_reg[0]_i_63_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_65\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_149_n_0\, I1 => \vgaRed_reg[0]_i_150_n_0\, O => \vgaRed_reg[0]_i_65_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_66\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_151_n_0\, I1 => \vgaRed_reg[0]_i_152_n_0\, O => \vgaRed_reg[0]_i_66_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_67\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_153_n_0\, I1 => \vgaRed_reg[0]_i_154_n_0\, O => \vgaRed_reg[0]_i_67_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_70\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_155_n_0\, I1 => \vgaRed_reg[0]_i_156_n_0\, O => \vgaRed_reg[0]_i_70_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_71\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_157_n_0\, I1 => \vgaRed_reg[0]_i_158_n_0\, O => \vgaRed_reg[0]_i_71_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_72\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_159_n_0\, I1 => \vgaRed_reg[0]_i_160_n_0\, O => \vgaRed_reg[0]_i_72_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_73\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_161_n_0\, I1 => \vgaRed_reg[0]_i_162_n_0\, O => \vgaRed_reg[0]_i_73_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_74\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_163_n_0\, I1 => \vgaRed_reg[0]_i_164_n_0\, O => \vgaRed_reg[0]_i_74_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_75\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_165_n_0\, I1 => \vgaRed_reg[0]_i_166_n_0\, O => \vgaRed_reg[0]_i_75_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_76\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_167_n_0\, I1 => \vgaRed_reg[0]_i_168_n_0\, O => \vgaRed_reg[0]_i_76_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_77\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_169_n_0\, I1 => \vgaRed_reg[0]_i_170_n_0\, O => \vgaRed_reg[0]_i_77_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_78\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_171_n_0\, I1 => \vgaRed_reg[0]_i_172_n_0\, O => \vgaRed_reg[0]_i_78_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_79\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_173_n_0\, I1 => \vgaRed_reg[0]_i_174_n_0\, O => \vgaRed_reg[0]_i_79_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_81\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_175_n_0\, I1 => \vgaRed_reg[0]_i_176_n_0\, O => \vgaRed_reg[0]_i_81_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_82\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_177_n_0\, I1 => \vgaRed_reg[0]_i_178_n_0\, O => \vgaRed_reg[0]_i_82_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_83\: unisim.vcomponents.MUXF7 port map ( I0 => g28_b5_n_0, I1 => g29_b5_n_0, O => \vgaRed_reg[0]_i_83_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_84\: unisim.vcomponents.MUXF7 port map ( I0 => g30_b5_n_0, I1 => g31_b5_n_0, O => \vgaRed_reg[0]_i_84_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_85\: unisim.vcomponents.MUXF7 port map ( I0 => g24_b5_n_0, I1 => g25_b5_n_0, O => \vgaRed_reg[0]_i_85_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_86\: unisim.vcomponents.MUXF7 port map ( I0 => g26_b5_n_0, I1 => g27_b5_n_0, O => \vgaRed_reg[0]_i_86_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_87\: unisim.vcomponents.MUXF7 port map ( I0 => g20_b5_n_0, I1 => g21_b5_n_0, O => \vgaRed_reg[0]_i_87_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_88\: unisim.vcomponents.MUXF7 port map ( I0 => g22_b5_n_0, I1 => g23_b5_n_0, O => \vgaRed_reg[0]_i_88_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_89\: unisim.vcomponents.MUXF7 port map ( I0 => g16_b5_n_0, I1 => g17_b5_n_0, O => \vgaRed_reg[0]_i_89_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_90\: unisim.vcomponents.MUXF7 port map ( I0 => g18_b5_n_0, I1 => g19_b5_n_0, O => \vgaRed_reg[0]_i_90_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_91\: unisim.vcomponents.MUXF7 port map ( I0 => g12_b5_n_0, I1 => g13_b5_n_0, O => \vgaRed_reg[0]_i_91_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_92\: unisim.vcomponents.MUXF7 port map ( I0 => g14_b5_n_0, I1 => g15_b5_n_0, O => \vgaRed_reg[0]_i_92_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_93\: unisim.vcomponents.MUXF7 port map ( I0 => g4_b5_n_0, I1 => g5_b5_n_0, O => \vgaRed_reg[0]_i_93_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_94\: unisim.vcomponents.MUXF7 port map ( I0 => g6_b5_n_0, I1 => g7_b5_n_0, O => \vgaRed_reg[0]_i_94_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_95\: unisim.vcomponents.MUXF7 port map ( I0 => g0_b5_n_0, I1 => g1_b5_n_0, O => \vgaRed_reg[0]_i_95_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_96\: unisim.vcomponents.MUXF7 port map ( I0 => g2_b5_n_0, I1 => g3_b5_n_0, O => \vgaRed_reg[0]_i_96_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_97\: unisim.vcomponents.MUXF7 port map ( I0 => g28_b4_n_0, I1 => g29_b4_n_0, O => \vgaRed_reg[0]_i_97_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_98\: unisim.vcomponents.MUXF7 port map ( I0 => g30_b4_n_0, I1 => g31_b4_n_0, O => \vgaRed_reg[0]_i_98_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_99\: unisim.vcomponents.MUXF7 port map ( I0 => g16_b4_n_0, I1 => g17_b4_n_0, O => \vgaRed_reg[0]_i_99_n_0\, S => \char[2]_i_1_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity ps2_keyboard is port ( ps2_code_new : out STD_LOGIC; break_reg : out STD_LOGIC; shift_l_reg : out STD_LOGIC; shift_r_reg : out STD_LOGIC; e0_code_reg : out STD_LOGIC; control_r_reg : out STD_LOGIC; control_l_reg : out STD_LOGIC; caps_lock_reg : out STD_LOGIC; \ascii_reg[7]\ : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 1 downto 0 ); \ascii_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 ); E : out STD_LOGIC_VECTOR ( 0 to 0 ); PS2Clk_IBUF : in STD_LOGIC; clk_BUFG : in STD_LOGIC; PS2Data_IBUF : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); break : in STD_LOGIC; shift_l : in STD_LOGIC; shift_r : in STD_LOGIC; e0_code : in STD_LOGIC; control_r_reg_0 : in STD_LOGIC; control_l_reg_0 : in STD_LOGIC; caps_lock_reg_0 : in STD_LOGIC; \ascii_reg[7]_0\ : in STD_LOGIC; prev_ps2_code_new : in STD_LOGIC ); end ps2_keyboard; architecture STRUCTURE of ps2_keyboard is signal \ascii[0]_i_10_n_0\ : STD_LOGIC; signal \ascii[0]_i_11_n_0\ : STD_LOGIC; signal \ascii[0]_i_2_n_0\ : STD_LOGIC; signal \ascii[0]_i_3_n_0\ : STD_LOGIC; signal \ascii[0]_i_4_n_0\ : STD_LOGIC; signal \ascii[0]_i_5_n_0\ : STD_LOGIC; signal \ascii[0]_i_6_n_0\ : STD_LOGIC; signal \ascii[0]_i_8_n_0\ : STD_LOGIC; signal \ascii[0]_i_9_n_0\ : STD_LOGIC; signal \ascii[1]_i_2_n_0\ : STD_LOGIC; signal \ascii[1]_i_3_n_0\ : STD_LOGIC; signal \ascii[1]_i_4_n_0\ : STD_LOGIC; signal \ascii[1]_i_5_n_0\ : STD_LOGIC; signal \ascii[1]_i_6_n_0\ : STD_LOGIC; signal \ascii[1]_i_7_n_0\ : STD_LOGIC; signal \ascii[1]_i_8_n_0\ : STD_LOGIC; signal \ascii[1]_i_9_n_0\ : STD_LOGIC; signal \ascii[2]_i_10_n_0\ : STD_LOGIC; signal \ascii[2]_i_11_n_0\ : STD_LOGIC; signal \ascii[2]_i_12_n_0\ : STD_LOGIC; signal \ascii[2]_i_3_n_0\ : STD_LOGIC; signal \ascii[2]_i_4_n_0\ : STD_LOGIC; signal \ascii[2]_i_5_n_0\ : STD_LOGIC; signal \ascii[2]_i_6_n_0\ : STD_LOGIC; signal \ascii[2]_i_7_n_0\ : STD_LOGIC; signal \ascii[2]_i_9_n_0\ : STD_LOGIC; signal \ascii[3]_i_10_n_0\ : STD_LOGIC; signal \ascii[3]_i_3_n_0\ : STD_LOGIC; signal \ascii[3]_i_4_n_0\ : STD_LOGIC; signal \ascii[3]_i_5_n_0\ : STD_LOGIC; signal \ascii[3]_i_6_n_0\ : STD_LOGIC; signal \ascii[3]_i_7_n_0\ : STD_LOGIC; signal \ascii[3]_i_8_n_0\ : STD_LOGIC; signal \ascii[3]_i_9_n_0\ : STD_LOGIC; signal \ascii[4]_i_10_n_0\ : STD_LOGIC; signal \ascii[4]_i_2_n_0\ : STD_LOGIC; signal \ascii[4]_i_3_n_0\ : STD_LOGIC; signal \ascii[4]_i_4_n_0\ : STD_LOGIC; signal \ascii[4]_i_5_n_0\ : STD_LOGIC; signal \ascii[4]_i_7_n_0\ : STD_LOGIC; signal \ascii[4]_i_8_n_0\ : STD_LOGIC; signal \ascii[4]_i_9_n_0\ : STD_LOGIC; signal \ascii[5]_i_10_n_0\ : STD_LOGIC; signal \ascii[5]_i_11_n_0\ : STD_LOGIC; signal \ascii[5]_i_12_n_0\ : STD_LOGIC; signal \ascii[5]_i_13_n_0\ : STD_LOGIC; signal \ascii[5]_i_14_n_0\ : STD_LOGIC; signal \ascii[5]_i_15_n_0\ : STD_LOGIC; signal \ascii[5]_i_16_n_0\ : STD_LOGIC; signal \ascii[5]_i_17_n_0\ : STD_LOGIC; signal \ascii[5]_i_2_n_0\ : STD_LOGIC; signal \ascii[5]_i_3_n_0\ : STD_LOGIC; signal \ascii[5]_i_4_n_0\ : STD_LOGIC; signal \ascii[6]_i_10_n_0\ : STD_LOGIC; signal \ascii[6]_i_11_n_0\ : STD_LOGIC; signal \ascii[6]_i_12_n_0\ : STD_LOGIC; signal \ascii[6]_i_13_n_0\ : STD_LOGIC; signal \ascii[6]_i_14_n_0\ : STD_LOGIC; signal \ascii[6]_i_15_n_0\ : STD_LOGIC; signal \ascii[6]_i_16_n_0\ : STD_LOGIC; signal \ascii[6]_i_17_n_0\ : STD_LOGIC; signal \ascii[6]_i_3_n_0\ : STD_LOGIC; signal \ascii[6]_i_4_n_0\ : STD_LOGIC; signal \ascii[6]_i_5_n_0\ : STD_LOGIC; signal \ascii[6]_i_6_n_0\ : STD_LOGIC; signal \ascii[6]_i_7_n_0\ : STD_LOGIC; signal \ascii[6]_i_8_n_0\ : STD_LOGIC; signal \ascii[6]_i_9_n_0\ : STD_LOGIC; signal \ascii_reg[0]_i_7_n_0\ : STD_LOGIC; signal \ascii_reg[2]_i_2_n_0\ : STD_LOGIC; signal \ascii_reg[2]_i_8_n_0\ : STD_LOGIC; signal \ascii_reg[3]_i_2_n_0\ : STD_LOGIC; signal \ascii_reg[4]_i_6_n_0\ : STD_LOGIC; signal \ascii_reg[5]_i_5_n_0\ : STD_LOGIC; signal \ascii_reg[5]_i_6_n_0\ : STD_LOGIC; signal \ascii_reg[5]_i_7_n_0\ : STD_LOGIC; signal \ascii_reg[5]_i_8_n_0\ : STD_LOGIC; signal \ascii_reg[5]_i_9_n_0\ : STD_LOGIC; signal break_i_2_n_0 : STD_LOGIC; signal caps_lock_i_2_n_0 : STD_LOGIC; signal clear : STD_LOGIC; signal control_l_i_2_n_0 : STD_LOGIC; signal control_r_i_2_n_0 : STD_LOGIC; signal control_r_i_3_n_0 : STD_LOGIC; signal \count_idle[0]_i_2_n_0\ : STD_LOGIC; signal \count_idle[0]_i_4_n_0\ : STD_LOGIC; signal \count_idle[0]_i_8_n_0\ : STD_LOGIC; signal \count_idle[0]_i_9_n_0\ : STD_LOGIC; signal count_idle_reg : STD_LOGIC_VECTOR ( 12 downto 0 ); signal \count_idle_reg[0]_i_3_n_0\ : STD_LOGIC; signal \count_idle_reg[0]_i_3_n_4\ : STD_LOGIC; signal \count_idle_reg[0]_i_3_n_5\ : STD_LOGIC; signal \count_idle_reg[0]_i_3_n_6\ : STD_LOGIC; signal \count_idle_reg[0]_i_3_n_7\ : STD_LOGIC; signal \count_idle_reg[12]_i_1_n_7\ : STD_LOGIC; signal \count_idle_reg[4]_i_1_n_0\ : STD_LOGIC; signal \count_idle_reg[4]_i_1_n_4\ : STD_LOGIC; signal \count_idle_reg[4]_i_1_n_5\ : STD_LOGIC; signal \count_idle_reg[4]_i_1_n_6\ : STD_LOGIC; signal \count_idle_reg[4]_i_1_n_7\ : STD_LOGIC; signal \count_idle_reg[8]_i_1_n_0\ : STD_LOGIC; signal \count_idle_reg[8]_i_1_n_4\ : STD_LOGIC; signal \count_idle_reg[8]_i_1_n_5\ : STD_LOGIC; signal \count_idle_reg[8]_i_1_n_6\ : STD_LOGIC; signal \count_idle_reg[8]_i_1_n_7\ : STD_LOGIC; signal e0_code_i_2_n_0 : STD_LOGIC; signal ps2_clk_int : STD_LOGIC; signal ps2_code : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \^ps2_code_new\ : STD_LOGIC; signal ps2_code_new0 : STD_LOGIC; signal ps2_code_new_i_2_n_0 : STD_LOGIC; signal ps2_code_new_i_3_n_0 : STD_LOGIC; signal ps2_code_new_i_4_n_0 : STD_LOGIC; signal ps2_code_new_i_5_n_0 : STD_LOGIC; signal ps2_code_new_i_6_n_0 : STD_LOGIC; signal ps2_code_new_i_7_n_0 : STD_LOGIC; signal ps2_data_int : STD_LOGIC; signal ps2_word : STD_LOGIC_VECTOR ( 10 downto 0 ); signal shift_l_i_2_n_0 : STD_LOGIC; signal shift_r_i_2_n_0 : STD_LOGIC; signal shift_r_i_3_n_0 : STD_LOGIC; signal \state[1]_i_2_n_0\ : STD_LOGIC; signal \NLW_count_idle_reg[0]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_count_idle_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_count_idle_reg[12]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_count_idle_reg[4]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_count_idle_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \ascii[5]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \ascii[6]_i_2\ : label is "soft_lutpair1"; begin ps2_code_new <= \^ps2_code_new\; \ascii[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CDC8" ) port map ( I0 => control_r_reg_0, I1 => \ascii[0]_i_2_n_0\, I2 => control_l_reg_0, I3 => \ascii[0]_i_3_n_0\, O => \ascii_reg[6]\(0) ); \ascii[0]_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"DCFDFFDF01000888" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(3), I3 => ps2_code(0), I4 => ps2_code(5), I5 => ps2_code(4), O => \ascii[0]_i_10_n_0\ ); \ascii[0]_i_11\: unisim.vcomponents.LUT6 generic map( INIT => X"FDBDFDFFEEBD030C" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(0), I3 => ps2_code(5), I4 => ps2_code(3), I5 => ps2_code(4), O => \ascii[0]_i_11_n_0\ ); \ascii[0]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"C0CFC0C0CACACFCF" ) port map ( I0 => ps2_code(2), I1 => \ascii[0]_i_4_n_0\, I2 => ps2_code(1), I3 => ps2_code(6), I4 => ps2_code(4), I5 => ps2_code(3), O => \ascii[0]_i_2_n_0\ ); \ascii[0]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"CDC8CDCDCDC8C8C8" ) port map ( I0 => shift_l, I1 => \ascii[0]_i_5_n_0\, I2 => shift_r, I3 => \ascii[0]_i_6_n_0\, I4 => ps2_code(7), I5 => \ascii_reg[0]_i_7_n_0\, O => \ascii[0]_i_3_n_0\ ); \ascii[0]_i_4\: unisim.vcomponents.LUT4 generic map( INIT => X"6515" ) port map ( I0 => ps2_code(5), I1 => ps2_code(0), I2 => ps2_code(3), I3 => ps2_code(4), O => \ascii[0]_i_4_n_0\ ); \ascii[0]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"EFE0CFCFEFE0C0C0" ) port map ( I0 => ps2_code(3), I1 => ps2_code(4), I2 => ps2_code(7), I3 => \ascii[0]_i_8_n_0\, I4 => ps2_code(2), I5 => \ascii[0]_i_9_n_0\, O => \ascii[0]_i_5_n_0\ ); \ascii[0]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"F8" ) port map ( I0 => ps2_code(3), I1 => ps2_code(2), I2 => ps2_code(4), O => \ascii[0]_i_6_n_0\ ); \ascii[0]_i_8\: unisim.vcomponents.LUT6 generic map( INIT => X"EDBDFDFFEEB90344" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(0), I3 => ps2_code(5), I4 => ps2_code(3), I5 => ps2_code(4), O => \ascii[0]_i_8_n_0\ ); \ascii[0]_i_9\: unisim.vcomponents.LUT6 generic map( INIT => X"DCFDFFD701000888" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(3), I3 => ps2_code(0), I4 => ps2_code(5), I5 => ps2_code(4), O => \ascii[0]_i_9_n_0\ ); \ascii[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CDC8" ) port map ( I0 => control_r_reg_0, I1 => \ascii[1]_i_2_n_0\, I2 => control_l_reg_0, I3 => \ascii[1]_i_3_n_0\, O => \ascii_reg[6]\(1) ); \ascii[1]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"6632FFFF66320000" ) port map ( I0 => ps2_code(6), I1 => ps2_code(0), I2 => ps2_code(4), I3 => ps2_code(3), I4 => ps2_code(2), I5 => \ascii[1]_i_4_n_0\, O => \ascii[1]_i_2_n_0\ ); \ascii[1]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"CDC8" ) port map ( I0 => shift_l, I1 => \ascii[1]_i_5_n_0\, I2 => shift_r, I3 => \ascii[1]_i_6_n_0\, O => \ascii[1]_i_3_n_0\ ); \ascii[1]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"55559DCDFFFFFFFF" ) port map ( I0 => ps2_code(0), I1 => ps2_code(3), I2 => ps2_code(5), I3 => ps2_code(4), I4 => ps2_code(6), I5 => ps2_code(1), O => \ascii[1]_i_4_n_0\ ); \ascii[1]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"2F202F2F2F202020" ) port map ( I0 => ps2_code(4), I1 => ps2_code(3), I2 => ps2_code(7), I3 => \ascii[1]_i_7_n_0\, I4 => ps2_code(2), I5 => \ascii[1]_i_8_n_0\, O => \ascii[1]_i_5_n_0\ ); \ascii[1]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"2F202F2F2F202020" ) port map ( I0 => ps2_code(4), I1 => ps2_code(3), I2 => ps2_code(7), I3 => \ascii[1]_i_9_n_0\, I4 => ps2_code(2), I5 => \ascii[1]_i_8_n_0\, O => \ascii[1]_i_6_n_0\ ); \ascii[1]_i_7\: unisim.vcomponents.LUT6 generic map( INIT => X"1120100EEEFD0024" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(5), I3 => ps2_code(0), I4 => ps2_code(4), I5 => ps2_code(3), O => \ascii[1]_i_7_n_0\ ); \ascii[1]_i_8\: unisim.vcomponents.LUT6 generic map( INIT => X"20222248DFFF1008" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(0), I3 => ps2_code(5), I4 => ps2_code(4), I5 => ps2_code(3), O => \ascii[1]_i_8_n_0\ ); \ascii[1]_i_9\: unisim.vcomponents.LUT6 generic map( INIT => X"11021004EAFD0024" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(5), I3 => ps2_code(0), I4 => ps2_code(4), I5 => ps2_code(3), O => \ascii[1]_i_9_n_0\ ); \ascii[2]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CDC8" ) port map ( I0 => control_r_reg_0, I1 => \ascii_reg[2]_i_2_n_0\, I2 => control_l_reg_0, I3 => \ascii[2]_i_3_n_0\, O => \ascii_reg[6]\(2) ); \ascii[2]_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"8AAA8E8ADEDDF777" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(4), I3 => ps2_code(0), I4 => ps2_code(5), I5 => ps2_code(3), O => \ascii[2]_i_10_n_0\ ); \ascii[2]_i_11\: unisim.vcomponents.LUT6 generic map( INIT => X"8AAA8E8ADEDDF7F7" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(4), I3 => ps2_code(0), I4 => ps2_code(5), I5 => ps2_code(3), O => \ascii[2]_i_11_n_0\ ); \ascii[2]_i_12\: unisim.vcomponents.LUT6 generic map( INIT => X"1504001010303814" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(5), I3 => ps2_code(3), I4 => ps2_code(4), I5 => ps2_code(0), O => \ascii[2]_i_12_n_0\ ); \ascii[2]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"CDC8CDCDCDC8C8C8" ) port map ( I0 => shift_l, I1 => \ascii[2]_i_6_n_0\, I2 => shift_r, I3 => \ascii[2]_i_7_n_0\, I4 => ps2_code(7), I5 => \ascii_reg[2]_i_8_n_0\, O => \ascii[2]_i_3_n_0\ ); \ascii[2]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"0FAFF0C0EF00CFC0" ) port map ( I0 => ps2_code(6), I1 => ps2_code(3), I2 => ps2_code(1), I3 => ps2_code(5), I4 => ps2_code(4), I5 => ps2_code(0), O => \ascii[2]_i_4_n_0\ ); \ascii[2]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"5FF0AAFA4EF0FFFF" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(5), I3 => ps2_code(0), I4 => ps2_code(4), I5 => ps2_code(3), O => \ascii[2]_i_5_n_0\ ); \ascii[2]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"0F00DFDF0F00D0D0" ) port map ( I0 => ps2_code(3), I1 => ps2_code(1), I2 => ps2_code(7), I3 => \ascii[2]_i_9_n_0\, I4 => ps2_code(2), I5 => \ascii[2]_i_10_n_0\, O => \ascii[2]_i_6_n_0\ ); \ascii[2]_i_7\: unisim.vcomponents.LUT3 generic map( INIT => X"0D" ) port map ( I0 => ps2_code(3), I1 => ps2_code(1), I2 => ps2_code(2), O => \ascii[2]_i_7_n_0\ ); \ascii[2]_i_9\: unisim.vcomponents.LUT6 generic map( INIT => X"1500001010303A14" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(5), I3 => ps2_code(3), I4 => ps2_code(4), I5 => ps2_code(0), O => \ascii[2]_i_9_n_0\ ); \ascii[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CDC8" ) port map ( I0 => control_r_reg_0, I1 => \ascii_reg[3]_i_2_n_0\, I2 => control_l_reg_0, I3 => \ascii[3]_i_3_n_0\, O => \ascii_reg[6]\(3) ); \ascii[3]_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"EEECFECDEBCDEBCF" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(5), I3 => ps2_code(0), I4 => ps2_code(3), I5 => ps2_code(4), O => \ascii[3]_i_10_n_0\ ); \ascii[3]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"CDC8" ) port map ( I0 => shift_l, I1 => \ascii[3]_i_6_n_0\, I2 => shift_r, I3 => \ascii[3]_i_7_n_0\, O => \ascii[3]_i_3_n_0\ ); \ascii[3]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"EFE2333F" ) port map ( I0 => ps2_code(6), I1 => ps2_code(5), I2 => ps2_code(0), I3 => ps2_code(3), I4 => ps2_code(4), O => \ascii[3]_i_4_n_0\ ); \ascii[3]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"FF444444F4F444F4" ) port map ( I0 => ps2_code(3), I1 => ps2_code(1), I2 => ps2_code(6), I3 => ps2_code(0), I4 => ps2_code(4), I5 => ps2_code(5), O => \ascii[3]_i_5_n_0\ ); \ascii[3]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"FFF0DFDFFFF0D0D0" ) port map ( I0 => ps2_code(0), I1 => ps2_code(6), I2 => ps2_code(7), I3 => \ascii[3]_i_8_n_0\, I4 => ps2_code(2), I5 => \ascii[3]_i_9_n_0\, O => \ascii[3]_i_6_n_0\ ); \ascii[3]_i_7\: unisim.vcomponents.LUT6 generic map( INIT => X"FFF0DFDFFFF0D0D0" ) port map ( I0 => ps2_code(0), I1 => ps2_code(6), I2 => ps2_code(7), I3 => \ascii[3]_i_10_n_0\, I4 => ps2_code(2), I5 => \ascii[3]_i_9_n_0\, O => \ascii[3]_i_7_n_0\ ); \ascii[3]_i_8\: unisim.vcomponents.LUT6 generic map( INIT => X"EEECFEEDEBCFEFCF" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(5), I3 => ps2_code(0), I4 => ps2_code(3), I5 => ps2_code(4), O => \ascii[3]_i_8_n_0\ ); \ascii[3]_i_9\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFDFFB313D333" ) port map ( I0 => ps2_code(1), I1 => ps2_code(0), I2 => ps2_code(5), I3 => ps2_code(4), I4 => ps2_code(3), I5 => ps2_code(6), O => \ascii[3]_i_9_n_0\ ); \ascii[4]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CDC8" ) port map ( I0 => control_r_reg_0, I1 => \ascii[4]_i_2_n_0\, I2 => control_l_reg_0, I3 => \ascii[4]_i_3_n_0\, O => \ascii_reg[6]\(4) ); \ascii[4]_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"15321434FFEF1428" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(5), I3 => ps2_code(0), I4 => ps2_code(4), I5 => ps2_code(3), O => \ascii[4]_i_10_n_0\ ); \ascii[4]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"CFCCC3FFCCCC8CB8" ) port map ( I0 => ps2_code(1), I1 => ps2_code(2), I2 => ps2_code(5), I3 => ps2_code(4), I4 => ps2_code(0), I5 => ps2_code(3), O => \ascii[4]_i_2_n_0\ ); \ascii[4]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"CDC8CDCDCDC8C8C8" ) port map ( I0 => shift_l, I1 => \ascii[4]_i_4_n_0\, I2 => shift_r, I3 => \ascii[4]_i_5_n_0\, I4 => ps2_code(7), I5 => \ascii_reg[4]_i_6_n_0\, O => \ascii[4]_i_3_n_0\ ); \ascii[4]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"2F202F2F2F202020" ) port map ( I0 => ps2_code(4), I1 => ps2_code(3), I2 => ps2_code(7), I3 => \ascii[4]_i_7_n_0\, I4 => ps2_code(2), I5 => \ascii[4]_i_8_n_0\, O => \ascii[4]_i_4_n_0\ ); \ascii[4]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => ps2_code(4), I1 => ps2_code(3), O => \ascii[4]_i_5_n_0\ ); \ascii[4]_i_7\: unisim.vcomponents.LUT6 generic map( INIT => X"0510141EFBED0000" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(5), I3 => ps2_code(0), I4 => ps2_code(4), I5 => ps2_code(3), O => \ascii[4]_i_7_n_0\ ); \ascii[4]_i_8\: unisim.vcomponents.LUT6 generic map( INIT => X"00A20248CDF70240" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(0), I3 => ps2_code(5), I4 => ps2_code(4), I5 => ps2_code(3), O => \ascii[4]_i_8_n_0\ ); \ascii[4]_i_9\: unisim.vcomponents.LUT6 generic map( INIT => X"00A20200CDF70200" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(0), I3 => ps2_code(5), I4 => ps2_code(4), I5 => ps2_code(3), O => \ascii[4]_i_9_n_0\ ); \ascii[5]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CDC8" ) port map ( I0 => control_r_reg_0, I1 => \ascii[6]_i_4_n_0\, I2 => control_l_reg_0, I3 => \ascii[5]_i_2_n_0\, O => \ascii_reg[6]\(5) ); \ascii[5]_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF8F4C8080" ) port map ( I0 => ps2_code(3), I1 => ps2_code(1), I2 => ps2_code(4), I3 => ps2_code(0), I4 => ps2_code(6), I5 => ps2_code(5), O => \ascii[5]_i_10_n_0\ ); \ascii[5]_i_11\: unisim.vcomponents.LUT6 generic map( INIT => X"111131335544166C" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(3), I3 => ps2_code(4), I4 => ps2_code(0), I5 => ps2_code(5), O => \ascii[5]_i_11_n_0\ ); \ascii[5]_i_12\: unisim.vcomponents.LUT6 generic map( INIT => X"F5F5F0F590201080" ) port map ( I0 => ps2_code(1), I1 => ps2_code(4), I2 => ps2_code(6), I3 => ps2_code(0), I4 => ps2_code(3), I5 => ps2_code(5), O => \ascii[5]_i_12_n_0\ ); \ascii[5]_i_13\: unisim.vcomponents.LUT6 generic map( INIT => X"1202001240064648" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(0), I3 => ps2_code(4), I4 => ps2_code(3), I5 => ps2_code(5), O => \ascii[5]_i_13_n_0\ ); \ascii[5]_i_14\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF0F4C8080" ) port map ( I0 => ps2_code(3), I1 => ps2_code(1), I2 => ps2_code(4), I3 => ps2_code(0), I4 => ps2_code(6), I5 => ps2_code(5), O => \ascii[5]_i_14_n_0\ ); \ascii[5]_i_15\: unisim.vcomponents.LUT6 generic map( INIT => X"11113333154432EC" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(3), I3 => ps2_code(4), I4 => ps2_code(0), I5 => ps2_code(5), O => \ascii[5]_i_15_n_0\ ); \ascii[5]_i_16\: unisim.vcomponents.LUT6 generic map( INIT => X"F5F5F0F510201080" ) port map ( I0 => ps2_code(1), I1 => ps2_code(4), I2 => ps2_code(6), I3 => ps2_code(0), I4 => ps2_code(3), I5 => ps2_code(5), O => \ascii[5]_i_16_n_0\ ); \ascii[5]_i_17\: unisim.vcomponents.LUT6 generic map( INIT => X"12020212020E4248" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(0), I3 => ps2_code(4), I4 => ps2_code(3), I5 => ps2_code(5), O => \ascii[5]_i_17_n_0\ ); \ascii[5]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"CDC8CDCDCDC8C8C8" ) port map ( I0 => shift_l, I1 => \ascii[5]_i_3_n_0\, I2 => shift_r, I3 => \ascii[5]_i_4_n_0\, I4 => ps2_code(7), I5 => \ascii_reg[5]_i_5_n_0\, O => \ascii[5]_i_2_n_0\ ); \ascii[5]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"2F202F2F2F202020" ) port map ( I0 => ps2_code(5), I1 => ps2_code(2), I2 => ps2_code(7), I3 => \ascii_reg[5]_i_6_n_0\, I4 => caps_lock_reg_0, I5 => \ascii_reg[5]_i_7_n_0\, O => \ascii[5]_i_3_n_0\ ); \ascii[5]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => ps2_code(5), I1 => ps2_code(2), O => \ascii[5]_i_4_n_0\ ); \ascii[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \ascii[6]_i_3_n_0\, I1 => Q(0), O => E(0) ); \ascii[6]_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"00B030300000C0C0" ) port map ( I0 => e0_code, I1 => ps2_code(6), I2 => ps2_code(0), I3 => ps2_code(3), I4 => ps2_code(4), I5 => ps2_code(5), O => \ascii[6]_i_10_n_0\ ); \ascii[6]_i_11\: unisim.vcomponents.LUT5 generic map( INIT => X"3333F4CC" ) port map ( I0 => ps2_code(0), I1 => ps2_code(6), I2 => ps2_code(3), I3 => ps2_code(4), I4 => ps2_code(5), O => \ascii[6]_i_11_n_0\ ); \ascii[6]_i_12\: unisim.vcomponents.LUT6 generic map( INIT => X"11113B3B555436EC" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(3), I3 => ps2_code(4), I4 => ps2_code(0), I5 => ps2_code(5), O => \ascii[6]_i_12_n_0\ ); \ascii[6]_i_13\: unisim.vcomponents.LUT6 generic map( INIT => X"0C040404C8C8F0C0" ) port map ( I0 => ps2_code(4), I1 => ps2_code(1), I2 => ps2_code(5), I3 => ps2_code(0), I4 => ps2_code(3), I5 => ps2_code(6), O => \ascii[6]_i_13_n_0\ ); \ascii[6]_i_14\: unisim.vcomponents.LUT6 generic map( INIT => X"0513141811340014" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(5), I3 => ps2_code(0), I4 => ps2_code(4), I5 => ps2_code(3), O => \ascii[6]_i_14_n_0\ ); \ascii[6]_i_15\: unisim.vcomponents.LUT6 generic map( INIT => X"0513141A11340014" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(5), I3 => ps2_code(0), I4 => ps2_code(4), I5 => ps2_code(3), O => \ascii[6]_i_15_n_0\ ); \ascii[6]_i_16\: unisim.vcomponents.LUT6 generic map( INIT => X"FCFFFCFCC8400840" ) port map ( I0 => ps2_code(4), I1 => ps2_code(1), I2 => ps2_code(6), I3 => ps2_code(3), I4 => ps2_code(0), I5 => ps2_code(5), O => \ascii[6]_i_16_n_0\ ); \ascii[6]_i_17\: unisim.vcomponents.LUT6 generic map( INIT => X"0511141211140014" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(5), I3 => ps2_code(0), I4 => ps2_code(4), I5 => ps2_code(3), O => \ascii[6]_i_17_n_0\ ); \ascii[6]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"CDC8" ) port map ( I0 => control_r_reg_0, I1 => \ascii[6]_i_4_n_0\, I2 => control_l_reg_0, I3 => \ascii[6]_i_5_n_0\, O => \ascii_reg[6]\(6) ); \ascii[6]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"F0E20000" ) port map ( I0 => \ascii[6]_i_6_n_0\, I1 => control_l_reg_0, I2 => \ascii[6]_i_7_n_0\, I3 => control_r_reg_0, I4 => Q(1), O => \ascii[6]_i_3_n_0\ ); \ascii[6]_i_4\: unisim.vcomponents.LUT4 generic map( INIT => X"0008" ) port map ( I0 => ps2_code(6), I1 => ps2_code(3), I2 => ps2_code(0), I3 => ps2_code(2), O => \ascii[6]_i_4_n_0\ ); \ascii[6]_i_5\: unisim.vcomponents.LUT4 generic map( INIT => X"CDC8" ) port map ( I0 => shift_l, I1 => \ascii[6]_i_8_n_0\, I2 => shift_r, I3 => \ascii[6]_i_9_n_0\, O => \ascii[6]_i_5_n_0\ ); \ascii[6]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"00000000FFE200E2" ) port map ( I0 => \ascii[6]_i_10_n_0\, I1 => ps2_code(1), I2 => \ascii[6]_i_11_n_0\, I3 => ps2_code(2), I4 => \ascii[6]_i_12_n_0\, I5 => ps2_code(7), O => \ascii[6]_i_6_n_0\ ); \ascii[6]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"00E2" ) port map ( I0 => \ascii[6]_i_13_n_0\, I1 => ps2_code(2), I2 => \ascii[6]_i_14_n_0\, I3 => ps2_code(7), O => \ascii[6]_i_7_n_0\ ); \ascii[6]_i_8\: unisim.vcomponents.LUT6 generic map( INIT => X"0F008F8F0F008080" ) port map ( I0 => ps2_code(6), I1 => ps2_code(5), I2 => ps2_code(7), I3 => \ascii[6]_i_15_n_0\, I4 => ps2_code(2), I5 => \ascii[6]_i_16_n_0\, O => \ascii[6]_i_8_n_0\ ); \ascii[6]_i_9\: unisim.vcomponents.LUT6 generic map( INIT => X"0F008F8F0F008080" ) port map ( I0 => ps2_code(6), I1 => ps2_code(5), I2 => ps2_code(7), I3 => \ascii[6]_i_17_n_0\, I4 => ps2_code(2), I5 => \ascii[6]_i_16_n_0\, O => \ascii[6]_i_9_n_0\ ); \ascii[7]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FF0FFFFF0D0F0D00" ) port map ( I0 => ps2_code(7), I1 => \state[1]_i_2_n_0\, I2 => Q(1), I3 => Q(0), I4 => \ascii[6]_i_3_n_0\, I5 => \ascii_reg[7]_0\, O => \ascii_reg[7]\ ); \ascii_reg[0]_i_7\: unisim.vcomponents.MUXF7 port map ( I0 => \ascii[0]_i_10_n_0\, I1 => \ascii[0]_i_11_n_0\, O => \ascii_reg[0]_i_7_n_0\, S => ps2_code(2) ); \ascii_reg[2]_i_2\: unisim.vcomponents.MUXF7 port map ( I0 => \ascii[2]_i_4_n_0\, I1 => \ascii[2]_i_5_n_0\, O => \ascii_reg[2]_i_2_n_0\, S => ps2_code(2) ); \ascii_reg[2]_i_8\: unisim.vcomponents.MUXF7 port map ( I0 => \ascii[2]_i_11_n_0\, I1 => \ascii[2]_i_12_n_0\, O => \ascii_reg[2]_i_8_n_0\, S => ps2_code(2) ); \ascii_reg[3]_i_2\: unisim.vcomponents.MUXF7 port map ( I0 => \ascii[3]_i_4_n_0\, I1 => \ascii[3]_i_5_n_0\, O => \ascii_reg[3]_i_2_n_0\, S => ps2_code(2) ); \ascii_reg[4]_i_6\: unisim.vcomponents.MUXF7 port map ( I0 => \ascii[4]_i_9_n_0\, I1 => \ascii[4]_i_10_n_0\, O => \ascii_reg[4]_i_6_n_0\, S => ps2_code(2) ); \ascii_reg[5]_i_5\: unisim.vcomponents.MUXF8 port map ( I0 => \ascii_reg[5]_i_8_n_0\, I1 => \ascii_reg[5]_i_9_n_0\, O => \ascii_reg[5]_i_5_n_0\, S => caps_lock_reg_0 ); \ascii_reg[5]_i_6\: unisim.vcomponents.MUXF7 port map ( I0 => \ascii[5]_i_10_n_0\, I1 => \ascii[5]_i_11_n_0\, O => \ascii_reg[5]_i_6_n_0\, S => ps2_code(2) ); \ascii_reg[5]_i_7\: unisim.vcomponents.MUXF7 port map ( I0 => \ascii[5]_i_12_n_0\, I1 => \ascii[5]_i_13_n_0\, O => \ascii_reg[5]_i_7_n_0\, S => ps2_code(2) ); \ascii_reg[5]_i_8\: unisim.vcomponents.MUXF7 port map ( I0 => \ascii[5]_i_14_n_0\, I1 => \ascii[5]_i_15_n_0\, O => \ascii_reg[5]_i_8_n_0\, S => ps2_code(2) ); \ascii_reg[5]_i_9\: unisim.vcomponents.MUXF7 port map ( I0 => \ascii[5]_i_16_n_0\, I1 => \ascii[5]_i_17_n_0\, O => \ascii_reg[5]_i_9_n_0\, S => ps2_code(2) ); break_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FF00FFFF00000800" ) port map ( I0 => ps2_code(7), I1 => break_i_2_n_0, I2 => ps2_code(2), I3 => Q(0), I4 => Q(1), I5 => break, O => break_reg ); break_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000200000" ) port map ( I0 => ps2_code(6), I1 => ps2_code(0), I2 => ps2_code(4), I3 => ps2_code(3), I4 => ps2_code(5), I5 => ps2_code(1), O => break_i_2_n_0 ); caps_lock_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFEFFFFF00100000" ) port map ( I0 => Q(0), I1 => break, I2 => caps_lock_i_2_n_0, I3 => ps2_code(7), I4 => Q(1), I5 => caps_lock_reg_0, O => caps_lock_reg ); caps_lock_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000010000" ) port map ( I0 => ps2_code(1), I1 => ps2_code(5), I2 => shift_r_i_3_n_0, I3 => ps2_code(0), I4 => ps2_code(6), I5 => ps2_code(2), O => caps_lock_i_2_n_0 ); control_l_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFF7F00000040" ) port map ( I0 => break, I1 => Q(1), I2 => control_l_i_2_n_0, I3 => ps2_code(7), I4 => Q(0), I5 => control_l_reg_0, O => control_l_reg ); control_l_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000001000000000" ) port map ( I0 => ps2_code(1), I1 => e0_code, I2 => control_r_i_3_n_0, I3 => ps2_code(5), I4 => ps2_code(6), I5 => ps2_code(2), O => control_l_i_2_n_0 ); control_r_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFF7F00000040" ) port map ( I0 => break, I1 => Q(1), I2 => control_r_i_2_n_0, I3 => ps2_code(7), I4 => Q(0), I5 => control_r_reg_0, O => control_r_reg ); control_r_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000004000000000" ) port map ( I0 => ps2_code(1), I1 => e0_code, I2 => control_r_i_3_n_0, I3 => ps2_code(5), I4 => ps2_code(6), I5 => ps2_code(2), O => control_r_i_2_n_0 ); control_r_i_3: unisim.vcomponents.LUT3 generic map( INIT => X"04" ) port map ( I0 => ps2_code(3), I1 => ps2_code(4), I2 => ps2_code(0), O => control_r_i_3_n_0 ); \count_idle[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => ps2_clk_int, O => clear ); \count_idle[0]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"DF" ) port map ( I0 => count_idle_reg(10), I1 => \count_idle[0]_i_4_n_0\, I2 => count_idle_reg(12), O => \count_idle[0]_i_2_n_0\ ); \count_idle[0]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF7FFFFFFFFFF" ) port map ( I0 => count_idle_reg(7), I1 => count_idle_reg(5), I2 => \count_idle[0]_i_9_n_0\, I3 => count_idle_reg(4), I4 => count_idle_reg(9), I5 => count_idle_reg(8), O => \count_idle[0]_i_4_n_0\ ); \count_idle[0]_i_8\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => count_idle_reg(0), O => \count_idle[0]_i_8_n_0\ ); \count_idle[0]_i_9\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFDFFFFFFFF" ) port map ( I0 => count_idle_reg(0), I1 => count_idle_reg(2), I2 => count_idle_reg(6), I3 => count_idle_reg(11), I4 => count_idle_reg(3), I5 => count_idle_reg(1), O => \count_idle[0]_i_9_n_0\ ); \count_idle_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \count_idle[0]_i_2_n_0\, D => \count_idle_reg[0]_i_3_n_7\, Q => count_idle_reg(0), R => clear ); \count_idle_reg[0]_i_3\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \count_idle_reg[0]_i_3_n_0\, CO(2 downto 0) => \NLW_count_idle_reg[0]_i_3_CO_UNCONNECTED\(2 downto 0), CYINIT => '0', DI(3 downto 0) => B"0001", O(3) => \count_idle_reg[0]_i_3_n_4\, O(2) => \count_idle_reg[0]_i_3_n_5\, O(1) => \count_idle_reg[0]_i_3_n_6\, O(0) => \count_idle_reg[0]_i_3_n_7\, S(3 downto 1) => count_idle_reg(3 downto 1), S(0) => \count_idle[0]_i_8_n_0\ ); \count_idle_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \count_idle[0]_i_2_n_0\, D => \count_idle_reg[8]_i_1_n_5\, Q => count_idle_reg(10), R => clear ); \count_idle_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \count_idle[0]_i_2_n_0\, D => \count_idle_reg[8]_i_1_n_4\, Q => count_idle_reg(11), R => clear ); \count_idle_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \count_idle[0]_i_2_n_0\, D => \count_idle_reg[12]_i_1_n_7\, Q => count_idle_reg(12), R => clear ); \count_idle_reg[12]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \count_idle_reg[8]_i_1_n_0\, CO(3 downto 0) => \NLW_count_idle_reg[12]_i_1_CO_UNCONNECTED\(3 downto 0), CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 1) => \NLW_count_idle_reg[12]_i_1_O_UNCONNECTED\(3 downto 1), O(0) => \count_idle_reg[12]_i_1_n_7\, S(3 downto 1) => B"000", S(0) => count_idle_reg(12) ); \count_idle_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \count_idle[0]_i_2_n_0\, D => \count_idle_reg[0]_i_3_n_6\, Q => count_idle_reg(1), R => clear ); \count_idle_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \count_idle[0]_i_2_n_0\, D => \count_idle_reg[0]_i_3_n_5\, Q => count_idle_reg(2), R => clear ); \count_idle_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \count_idle[0]_i_2_n_0\, D => \count_idle_reg[0]_i_3_n_4\, Q => count_idle_reg(3), R => clear ); \count_idle_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \count_idle[0]_i_2_n_0\, D => \count_idle_reg[4]_i_1_n_7\, Q => count_idle_reg(4), R => clear ); \count_idle_reg[4]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \count_idle_reg[0]_i_3_n_0\, CO(3) => \count_idle_reg[4]_i_1_n_0\, CO(2 downto 0) => \NLW_count_idle_reg[4]_i_1_CO_UNCONNECTED\(2 downto 0), CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \count_idle_reg[4]_i_1_n_4\, O(2) => \count_idle_reg[4]_i_1_n_5\, O(1) => \count_idle_reg[4]_i_1_n_6\, O(0) => \count_idle_reg[4]_i_1_n_7\, S(3 downto 0) => count_idle_reg(7 downto 4) ); \count_idle_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \count_idle[0]_i_2_n_0\, D => \count_idle_reg[4]_i_1_n_6\, Q => count_idle_reg(5), R => clear ); \count_idle_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \count_idle[0]_i_2_n_0\, D => \count_idle_reg[4]_i_1_n_5\, Q => count_idle_reg(6), R => clear ); \count_idle_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \count_idle[0]_i_2_n_0\, D => \count_idle_reg[4]_i_1_n_4\, Q => count_idle_reg(7), R => clear ); \count_idle_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \count_idle[0]_i_2_n_0\, D => \count_idle_reg[8]_i_1_n_7\, Q => count_idle_reg(8), R => clear ); \count_idle_reg[8]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \count_idle_reg[4]_i_1_n_0\, CO(3) => \count_idle_reg[8]_i_1_n_0\, CO(2 downto 0) => \NLW_count_idle_reg[8]_i_1_CO_UNCONNECTED\(2 downto 0), CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \count_idle_reg[8]_i_1_n_4\, O(2) => \count_idle_reg[8]_i_1_n_5\, O(1) => \count_idle_reg[8]_i_1_n_6\, O(0) => \count_idle_reg[8]_i_1_n_7\, S(3 downto 0) => count_idle_reg(11 downto 8) ); \count_idle_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \count_idle[0]_i_2_n_0\, D => \count_idle_reg[8]_i_1_n_6\, Q => count_idle_reg(9), R => clear ); e0_code_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FF00FFFF00000800" ) port map ( I0 => ps2_code(7), I1 => e0_code_i_2_n_0, I2 => ps2_code(2), I3 => Q(0), I4 => Q(1), I5 => e0_code, O => e0_code_reg ); e0_code_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000020000" ) port map ( I0 => ps2_code(6), I1 => ps2_code(0), I2 => ps2_code(4), I3 => ps2_code(3), I4 => ps2_code(5), I5 => ps2_code(1), O => e0_code_i_2_n_0 ); ps2_clk_int_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => '1', D => PS2Clk_IBUF, Q => ps2_clk_int, R => '0' ); ps2_code_new_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"8000" ) port map ( I0 => count_idle_reg(10), I1 => ps2_code_new_i_2_n_0, I2 => count_idle_reg(8), I3 => count_idle_reg(12), O => ps2_code_new0 ); ps2_code_new_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"4000000000000000" ) port map ( I0 => count_idle_reg(9), I1 => count_idle_reg(4), I2 => ps2_code_new_i_3_n_0, I3 => count_idle_reg(1), I4 => count_idle_reg(5), I5 => count_idle_reg(7), O => ps2_code_new_i_2_n_0 ); ps2_code_new_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"0000001000000000" ) port map ( I0 => count_idle_reg(3), I1 => count_idle_reg(11), I2 => ps2_code_new_i_4_n_0, I3 => count_idle_reg(6), I4 => count_idle_reg(2), I5 => count_idle_reg(0), O => ps2_code_new_i_3_n_0 ); ps2_code_new_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"FF96FF6969009600" ) port map ( I0 => ps2_word(9), I1 => ps2_word(7), I2 => ps2_word(8), I3 => ps2_code_new_i_5_n_0, I4 => ps2_word(5), I5 => ps2_code_new_i_6_n_0, O => ps2_code_new_i_4_n_0 ); ps2_code_new_i_5: unisim.vcomponents.LUT6 generic map( INIT => X"6996000096690000" ) port map ( I0 => ps2_word(6), I1 => ps2_word(3), I2 => ps2_word(4), I3 => ps2_word(1), I4 => ps2_code_new_i_7_n_0, I5 => ps2_word(2), O => ps2_code_new_i_5_n_0 ); ps2_code_new_i_6: unisim.vcomponents.LUT6 generic map( INIT => X"9669000069960000" ) port map ( I0 => ps2_word(6), I1 => ps2_word(3), I2 => ps2_word(4), I3 => ps2_word(1), I4 => ps2_code_new_i_7_n_0, I5 => ps2_word(2), O => ps2_code_new_i_6_n_0 ); ps2_code_new_i_7: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => ps2_word(10), I1 => ps2_word(0), O => ps2_code_new_i_7_n_0 ); ps2_code_new_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => '1', D => ps2_code_new0, Q => \^ps2_code_new\, R => '0' ); \ps2_code_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => ps2_code_new0, D => ps2_word(1), Q => ps2_code(0), R => '0' ); \ps2_code_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => ps2_code_new0, D => ps2_word(2), Q => ps2_code(1), R => '0' ); \ps2_code_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => ps2_code_new0, D => ps2_word(3), Q => ps2_code(2), R => '0' ); \ps2_code_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => ps2_code_new0, D => ps2_word(4), Q => ps2_code(3), R => '0' ); \ps2_code_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => ps2_code_new0, D => ps2_word(5), Q => ps2_code(4), R => '0' ); \ps2_code_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => ps2_code_new0, D => ps2_word(6), Q => ps2_code(5), R => '0' ); \ps2_code_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => ps2_code_new0, D => ps2_word(7), Q => ps2_code(6), R => '0' ); \ps2_code_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => ps2_code_new0, D => ps2_word(8), Q => ps2_code(7), R => '0' ); ps2_data_int_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => '1', D => PS2Data_IBUF, Q => ps2_data_int, R => '0' ); \ps2_word_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '1' ) port map ( C => ps2_clk_int, CE => '1', D => ps2_word(1), Q => ps2_word(0), R => '0' ); \ps2_word_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '1' ) port map ( C => ps2_clk_int, CE => '1', D => ps2_data_int, Q => ps2_word(10), R => '0' ); \ps2_word_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '1' ) port map ( C => ps2_clk_int, CE => '1', D => ps2_word(2), Q => ps2_word(1), R => '0' ); \ps2_word_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '1' ) port map ( C => ps2_clk_int, CE => '1', D => ps2_word(3), Q => ps2_word(2), R => '0' ); \ps2_word_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '1' ) port map ( C => ps2_clk_int, CE => '1', D => ps2_word(4), Q => ps2_word(3), R => '0' ); \ps2_word_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '1' ) port map ( C => ps2_clk_int, CE => '1', D => ps2_word(5), Q => ps2_word(4), R => '0' ); \ps2_word_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '1' ) port map ( C => ps2_clk_int, CE => '1', D => ps2_word(6), Q => ps2_word(5), R => '0' ); \ps2_word_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '1' ) port map ( C => ps2_clk_int, CE => '1', D => ps2_word(7), Q => ps2_word(6), R => '0' ); \ps2_word_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '1' ) port map ( C => ps2_clk_int, CE => '1', D => ps2_word(8), Q => ps2_word(7), R => '0' ); \ps2_word_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '1' ) port map ( C => ps2_clk_int, CE => '1', D => ps2_word(9), Q => ps2_word(8), R => '0' ); \ps2_word_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '1' ) port map ( C => ps2_clk_int, CE => '1', D => ps2_word(10), Q => ps2_word(9), R => '0' ); shift_l_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFF7F00000040" ) port map ( I0 => break, I1 => Q(1), I2 => shift_l_i_2_n_0, I3 => ps2_code(7), I4 => Q(0), I5 => shift_l, O => shift_l_reg ); shift_l_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000020" ) port map ( I0 => ps2_code(1), I1 => ps2_code(5), I2 => \ascii[4]_i_5_n_0\, I3 => ps2_code(0), I4 => ps2_code(6), I5 => ps2_code(2), O => shift_l_i_2_n_0 ); shift_r_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFF7F00000040" ) port map ( I0 => break, I1 => Q(1), I2 => shift_r_i_2_n_0, I3 => ps2_code(7), I4 => Q(0), I5 => shift_r, O => shift_r_reg ); shift_r_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000000001000000" ) port map ( I0 => ps2_code(1), I1 => ps2_code(5), I2 => shift_r_i_3_n_0, I3 => ps2_code(0), I4 => ps2_code(6), I5 => ps2_code(2), O => shift_r_i_2_n_0 ); shift_r_i_3: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => ps2_code(3), I1 => ps2_code(4), O => shift_r_i_3_n_0 ); \state[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"000004F4" ) port map ( I0 => prev_ps2_code_new, I1 => \^ps2_code_new\, I2 => Q(1), I3 => break, I4 => Q(0), O => D(0) ); \state[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"00D00FD0" ) port map ( I0 => ps2_code(7), I1 => \state[1]_i_2_n_0\, I2 => Q(0), I3 => Q(1), I4 => break, O => D(1) ); \state[1]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFBFFFF" ) port map ( I0 => ps2_code(1), I1 => ps2_code(5), I2 => ps2_code(3), I3 => ps2_code(0), I4 => ps2_code(6), I5 => ps2_code(2), O => \state[1]_i_2_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity ClockDivider is port ( clkIn : in STD_LOGIC; clk108M : out STD_LOGIC; clk10M : out STD_LOGIC ); attribute CORE_GENERATION_INFO : string; attribute CORE_GENERATION_INFO of ClockDivider : entity is "ClockDivider,clk_wiz_v5_2_1,{component_name=ClockDivider,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}"; end ClockDivider; architecture STRUCTURE of ClockDivider is begin inst: entity work.ClockDivider_ClockDivider_clk_wiz port map ( clk108M => clk108M, clk10M => clk10M, clkIn => clkIn ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity FrameBuffer_blk_mem_gen_prim_width is port ( \doutb[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); clka : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width"; end FrameBuffer_blk_mem_gen_prim_width; architecture STRUCTURE of FrameBuffer_blk_mem_gen_prim_width is begin \prim_init.ram\: entity work.FrameBuffer_blk_mem_gen_prim_wrapper_init port map ( addra(13 downto 0) => addra(13 downto 0), addrb(13 downto 0) => addrb(13 downto 0), clka => clka, clkb => clkb, dina(7 downto 0) => dina(7 downto 0), \doutb[7]\(7 downto 0) => \doutb[7]\(7 downto 0), wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \FrameBuffer_blk_mem_gen_prim_width__parameterized0\ is port ( \doutb[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); clka : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \FrameBuffer_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width"; end \FrameBuffer_blk_mem_gen_prim_width__parameterized0\; architecture STRUCTURE of \FrameBuffer_blk_mem_gen_prim_width__parameterized0\ is begin \prim_init.ram\: entity work.\FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized0\ port map ( addra(13 downto 0) => addra(13 downto 0), addrb(13 downto 0) => addrb(13 downto 0), clka => clka, clkb => clkb, dina(7 downto 0) => dina(7 downto 0), \doutb[7]\(7 downto 0) => \doutb[7]\(7 downto 0), wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \FrameBuffer_blk_mem_gen_prim_width__parameterized1\ is port ( DOBDO : out STD_LOGIC_VECTOR ( 7 downto 0 ); clka : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \FrameBuffer_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width"; end \FrameBuffer_blk_mem_gen_prim_width__parameterized1\; architecture STRUCTURE of \FrameBuffer_blk_mem_gen_prim_width__parameterized1\ is begin \prim_init.ram\: entity work.\FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized1\ port map ( DOBDO(7 downto 0) => DOBDO(7 downto 0), addra(13 downto 0) => addra(13 downto 0), addrb(13 downto 0) => addrb(13 downto 0), clka => clka, clkb => clkb, dina(7 downto 0) => dina(7 downto 0), wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity ps2_keyboard_to_ascii is port ( \next_s_reg[1]\ : out STD_LOGIC; \next_s_reg[0]\ : out STD_LOGIC; \counter_reg[0]\ : out STD_LOGIC; \fb_in_dat_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 ); \counter_reg[12]\ : out STD_LOGIC; PS2Clk_IBUF : in STD_LOGIC; clk_BUFG : in STD_LOGIC; PS2Data_IBUF : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 1 downto 0 ); \current_s_reg[0]\ : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); \counter_reg[0]_0\ : in STD_LOGIC; \counter_reg[0]_1\ : in STD_LOGIC; \counter_reg[0]_2\ : in STD_LOGIC; \counter_reg[0]_3\ : in STD_LOGIC; \counter_reg[0]_4\ : in STD_LOGIC; \counter_reg[0]_5\ : in STD_LOGIC; \counter_reg[0]_6\ : in STD_LOGIC; \counter_reg[4]\ : in STD_LOGIC; \counter_reg[4]_0\ : in STD_LOGIC ); end ps2_keyboard_to_ascii; architecture STRUCTURE of ps2_keyboard_to_ascii is signal ascii_code : STD_LOGIC_VECTOR ( 6 downto 0 ); signal ascii_new : STD_LOGIC; signal ascii_new_i_1_n_0 : STD_LOGIC; signal ascii_new_i_2_n_0 : STD_LOGIC; signal ascii_new_i_3_n_0 : STD_LOGIC; signal ascii_new_i_4_n_0 : STD_LOGIC; signal ascii_new_i_5_n_0 : STD_LOGIC; signal ascii_new_i_6_n_0 : STD_LOGIC; signal ascii_new_i_7_n_0 : STD_LOGIC; signal ascii_new_i_8_n_0 : STD_LOGIC; signal ascii_new_i_9_n_0 : STD_LOGIC; signal \ascii_reg_n_0_[0]\ : STD_LOGIC; signal \ascii_reg_n_0_[1]\ : STD_LOGIC; signal \ascii_reg_n_0_[2]\ : STD_LOGIC; signal \ascii_reg_n_0_[3]\ : STD_LOGIC; signal \ascii_reg_n_0_[4]\ : STD_LOGIC; signal \ascii_reg_n_0_[5]\ : STD_LOGIC; signal \ascii_reg_n_0_[6]\ : STD_LOGIC; signal \ascii_reg_n_0_[7]\ : STD_LOGIC; signal break : STD_LOGIC; signal caps_lock_reg_n_0 : STD_LOGIC; signal control_l_reg_n_0 : STD_LOGIC; signal control_r_reg_n_0 : STD_LOGIC; signal e0_code : STD_LOGIC; signal prev_ps2_code_new : STD_LOGIC; signal ps2_code_new : STD_LOGIC; signal ps2_keyboard_0_n_1 : STD_LOGIC; signal ps2_keyboard_0_n_10 : STD_LOGIC; signal ps2_keyboard_0_n_11 : STD_LOGIC; signal ps2_keyboard_0_n_12 : STD_LOGIC; signal ps2_keyboard_0_n_13 : STD_LOGIC; signal ps2_keyboard_0_n_14 : STD_LOGIC; signal ps2_keyboard_0_n_15 : STD_LOGIC; signal ps2_keyboard_0_n_16 : STD_LOGIC; signal ps2_keyboard_0_n_17 : STD_LOGIC; signal ps2_keyboard_0_n_18 : STD_LOGIC; signal ps2_keyboard_0_n_2 : STD_LOGIC; signal ps2_keyboard_0_n_3 : STD_LOGIC; signal ps2_keyboard_0_n_4 : STD_LOGIC; signal ps2_keyboard_0_n_5 : STD_LOGIC; signal ps2_keyboard_0_n_6 : STD_LOGIC; signal ps2_keyboard_0_n_7 : STD_LOGIC; signal ps2_keyboard_0_n_8 : STD_LOGIC; signal ps2_keyboard_0_n_9 : STD_LOGIC; signal \repeat_counter[0]_i_10_n_0\ : STD_LOGIC; signal \repeat_counter[0]_i_11_n_0\ : STD_LOGIC; signal \repeat_counter[0]_i_12_n_0\ : STD_LOGIC; signal \repeat_counter[0]_i_1_n_0\ : STD_LOGIC; signal \repeat_counter[0]_i_3_n_0\ : STD_LOGIC; signal \repeat_counter[0]_i_4_n_0\ : STD_LOGIC; signal \repeat_counter[0]_i_5_n_0\ : STD_LOGIC; signal \repeat_counter[0]_i_6_n_0\ : STD_LOGIC; signal \repeat_counter[0]_i_7_n_0\ : STD_LOGIC; signal \repeat_counter[0]_i_8_n_0\ : STD_LOGIC; signal \repeat_counter[0]_i_9_n_0\ : STD_LOGIC; signal \repeat_counter[12]_i_2_n_0\ : STD_LOGIC; signal \repeat_counter[12]_i_3_n_0\ : STD_LOGIC; signal \repeat_counter[12]_i_4_n_0\ : STD_LOGIC; signal \repeat_counter[12]_i_5_n_0\ : STD_LOGIC; signal \repeat_counter[16]_i_2_n_0\ : STD_LOGIC; signal \repeat_counter[16]_i_3_n_0\ : STD_LOGIC; signal \repeat_counter[16]_i_4_n_0\ : STD_LOGIC; signal \repeat_counter[16]_i_5_n_0\ : STD_LOGIC; signal \repeat_counter[20]_i_2_n_0\ : STD_LOGIC; signal \repeat_counter[4]_i_2_n_0\ : STD_LOGIC; signal \repeat_counter[4]_i_3_n_0\ : STD_LOGIC; signal \repeat_counter[4]_i_4_n_0\ : STD_LOGIC; signal \repeat_counter[4]_i_5_n_0\ : STD_LOGIC; signal \repeat_counter[8]_i_2_n_0\ : STD_LOGIC; signal \repeat_counter[8]_i_3_n_0\ : STD_LOGIC; signal \repeat_counter[8]_i_4_n_0\ : STD_LOGIC; signal \repeat_counter[8]_i_5_n_0\ : STD_LOGIC; signal repeat_counter_reg : STD_LOGIC_VECTOR ( 20 downto 0 ); signal \repeat_counter_reg[0]_i_2_n_0\ : STD_LOGIC; signal \repeat_counter_reg[0]_i_2_n_4\ : STD_LOGIC; signal \repeat_counter_reg[0]_i_2_n_5\ : STD_LOGIC; signal \repeat_counter_reg[0]_i_2_n_6\ : STD_LOGIC; signal \repeat_counter_reg[0]_i_2_n_7\ : STD_LOGIC; signal \repeat_counter_reg[12]_i_1_n_0\ : STD_LOGIC; signal \repeat_counter_reg[12]_i_1_n_4\ : STD_LOGIC; signal \repeat_counter_reg[12]_i_1_n_5\ : STD_LOGIC; signal \repeat_counter_reg[12]_i_1_n_6\ : STD_LOGIC; signal \repeat_counter_reg[12]_i_1_n_7\ : STD_LOGIC; signal \repeat_counter_reg[16]_i_1_n_0\ : STD_LOGIC; signal \repeat_counter_reg[16]_i_1_n_4\ : STD_LOGIC; signal \repeat_counter_reg[16]_i_1_n_5\ : STD_LOGIC; signal \repeat_counter_reg[16]_i_1_n_6\ : STD_LOGIC; signal \repeat_counter_reg[16]_i_1_n_7\ : STD_LOGIC; signal \repeat_counter_reg[20]_i_1_n_7\ : STD_LOGIC; signal \repeat_counter_reg[4]_i_1_n_0\ : STD_LOGIC; signal \repeat_counter_reg[4]_i_1_n_4\ : STD_LOGIC; signal \repeat_counter_reg[4]_i_1_n_5\ : STD_LOGIC; signal \repeat_counter_reg[4]_i_1_n_6\ : STD_LOGIC; signal \repeat_counter_reg[4]_i_1_n_7\ : STD_LOGIC; signal \repeat_counter_reg[8]_i_1_n_0\ : STD_LOGIC; signal \repeat_counter_reg[8]_i_1_n_4\ : STD_LOGIC; signal \repeat_counter_reg[8]_i_1_n_5\ : STD_LOGIC; signal \repeat_counter_reg[8]_i_1_n_6\ : STD_LOGIC; signal \repeat_counter_reg[8]_i_1_n_7\ : STD_LOGIC; signal shift_l : STD_LOGIC; signal shift_r : STD_LOGIC; signal state : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \NLW_repeat_counter_reg[0]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_repeat_counter_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_repeat_counter_reg[16]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_repeat_counter_reg[20]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_repeat_counter_reg[20]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_repeat_counter_reg[4]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_repeat_counter_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); begin \ascii_code_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => ascii_new_i_1_n_0, D => \ascii_reg_n_0_[0]\, Q => ascii_code(0), R => '0' ); \ascii_code_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => ascii_new_i_1_n_0, D => \ascii_reg_n_0_[1]\, Q => ascii_code(1), R => '0' ); \ascii_code_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => ascii_new_i_1_n_0, D => \ascii_reg_n_0_[2]\, Q => ascii_code(2), R => '0' ); \ascii_code_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => ascii_new_i_1_n_0, D => \ascii_reg_n_0_[3]\, Q => ascii_code(3), R => '0' ); \ascii_code_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => ascii_new_i_1_n_0, D => \ascii_reg_n_0_[4]\, Q => ascii_code(4), R => '0' ); \ascii_code_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => ascii_new_i_1_n_0, D => \ascii_reg_n_0_[5]\, Q => ascii_code(5), R => '0' ); \ascii_code_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => ascii_new_i_1_n_0, D => \ascii_reg_n_0_[6]\, Q => ascii_code(6), R => '0' ); ascii_new_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"0000A80800000000" ) port map ( I0 => state(1), I1 => ascii_new_i_2_n_0, I2 => repeat_counter_reg(16), I3 => ascii_new_i_3_n_0, I4 => \ascii_reg_n_0_[7]\, I5 => state(0), O => ascii_new_i_1_n_0 ); ascii_new_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"FF00FF01FF00FE00" ) port map ( I0 => repeat_counter_reg(19), I1 => repeat_counter_reg(12), I2 => repeat_counter_reg(11), I3 => ascii_new_i_3_n_0, I4 => repeat_counter_reg(10), I5 => ascii_new_i_4_n_0, O => ascii_new_i_2_n_0 ); ascii_new_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFFE" ) port map ( I0 => \ascii_reg_n_0_[3]\, I1 => \ascii_reg_n_0_[5]\, I2 => ascii_new_i_5_n_0, I3 => \ascii_reg_n_0_[0]\, I4 => \ascii_reg_n_0_[4]\, I5 => \ascii_reg_n_0_[6]\, O => ascii_new_i_3_n_0 ); ascii_new_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"EFFFFFFF40000000" ) port map ( I0 => repeat_counter_reg(7), I1 => ascii_new_i_6_n_0, I2 => repeat_counter_reg(2), I3 => repeat_counter_reg(0), I4 => repeat_counter_reg(18), I5 => ascii_new_i_3_n_0, O => ascii_new_i_4_n_0 ); ascii_new_i_5: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \ascii_reg_n_0_[2]\, I1 => \ascii_reg_n_0_[1]\, O => ascii_new_i_5_n_0 ); ascii_new_i_6: unisim.vcomponents.LUT6 generic map( INIT => X"EFFFFFFF40000000" ) port map ( I0 => repeat_counter_reg(5), I1 => ascii_new_i_7_n_0, I2 => repeat_counter_reg(6), I3 => repeat_counter_reg(17), I4 => repeat_counter_reg(1), I5 => ascii_new_i_3_n_0, O => ascii_new_i_6_n_0 ); ascii_new_i_7: unisim.vcomponents.LUT6 generic map( INIT => X"BFFFFFFF80000000" ) port map ( I0 => ascii_new_i_8_n_0, I1 => repeat_counter_reg(9), I2 => repeat_counter_reg(4), I3 => repeat_counter_reg(14), I4 => repeat_counter_reg(15), I5 => ascii_new_i_3_n_0, O => ascii_new_i_7_n_0 ); ascii_new_i_8: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFF8000" ) port map ( I0 => repeat_counter_reg(13), I1 => repeat_counter_reg(20), I2 => repeat_counter_reg(3), I3 => repeat_counter_reg(8), I4 => ascii_new_i_9_n_0, I5 => \ascii_reg_n_0_[6]\, O => ascii_new_i_8_n_0 ); ascii_new_i_9: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFFE" ) port map ( I0 => \ascii_reg_n_0_[4]\, I1 => \ascii_reg_n_0_[0]\, I2 => \ascii_reg_n_0_[2]\, I3 => \ascii_reg_n_0_[1]\, I4 => \ascii_reg_n_0_[5]\, I5 => \ascii_reg_n_0_[3]\, O => ascii_new_i_9_n_0 ); ascii_new_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => '1', D => ascii_new_i_1_n_0, Q => ascii_new, R => '0' ); \ascii_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_BUFG, CE => ps2_keyboard_0_n_18, D => ps2_keyboard_0_n_17, Q => \ascii_reg_n_0_[0]\, R => '0' ); \ascii_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_BUFG, CE => ps2_keyboard_0_n_18, D => ps2_keyboard_0_n_16, Q => \ascii_reg_n_0_[1]\, R => '0' ); \ascii_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_BUFG, CE => ps2_keyboard_0_n_18, D => ps2_keyboard_0_n_15, Q => \ascii_reg_n_0_[2]\, R => '0' ); \ascii_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_BUFG, CE => ps2_keyboard_0_n_18, D => ps2_keyboard_0_n_14, Q => \ascii_reg_n_0_[3]\, R => '0' ); \ascii_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_BUFG, CE => ps2_keyboard_0_n_18, D => ps2_keyboard_0_n_13, Q => \ascii_reg_n_0_[4]\, R => '0' ); \ascii_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_BUFG, CE => ps2_keyboard_0_n_18, D => ps2_keyboard_0_n_12, Q => \ascii_reg_n_0_[5]\, R => '0' ); \ascii_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_BUFG, CE => ps2_keyboard_0_n_18, D => ps2_keyboard_0_n_11, Q => \ascii_reg_n_0_[6]\, R => '0' ); \ascii_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_BUFG, CE => '1', D => ps2_keyboard_0_n_8, Q => \ascii_reg_n_0_[7]\, R => '0' ); break_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => '1', D => ps2_keyboard_0_n_1, Q => break, R => '0' ); caps_lock_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => '1', D => ps2_keyboard_0_n_7, Q => caps_lock_reg_n_0, R => '0' ); control_l_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => '1', D => ps2_keyboard_0_n_6, Q => control_l_reg_n_0, R => '0' ); control_r_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => '1', D => ps2_keyboard_0_n_5, Q => control_r_reg_n_0, R => '0' ); \counter[12]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"0003A0F3" ) port map ( I0 => ascii_new, I1 => \counter_reg[4]\, I2 => Q(1), I3 => Q(0), I4 => \counter_reg[4]_0\, O => \counter_reg[12]\ ); \counter[13]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"8F" ) port map ( I0 => Q(1), I1 => ascii_new, I2 => Q(0), O => \counter_reg[0]\ ); e0_code_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => '1', D => ps2_keyboard_0_n_4, Q => e0_code, R => '0' ); \fb_in_dat[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"8380" ) port map ( I0 => ascii_code(0), I1 => Q(0), I2 => Q(1), I3 => \counter_reg[0]_0\, O => \fb_in_dat_reg[6]\(0) ); \fb_in_dat[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"8380" ) port map ( I0 => ascii_code(1), I1 => Q(0), I2 => Q(1), I3 => \counter_reg[0]_1\, O => \fb_in_dat_reg[6]\(1) ); \fb_in_dat[2]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"8380" ) port map ( I0 => ascii_code(2), I1 => Q(0), I2 => Q(1), I3 => \counter_reg[0]_2\, O => \fb_in_dat_reg[6]\(2) ); \fb_in_dat[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"8380" ) port map ( I0 => ascii_code(3), I1 => Q(0), I2 => Q(1), I3 => \counter_reg[0]_3\, O => \fb_in_dat_reg[6]\(3) ); \fb_in_dat[4]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"8380" ) port map ( I0 => ascii_code(4), I1 => Q(0), I2 => Q(1), I3 => \counter_reg[0]_4\, O => \fb_in_dat_reg[6]\(4) ); \fb_in_dat[5]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"8380" ) port map ( I0 => ascii_code(5), I1 => Q(0), I2 => Q(1), I3 => \counter_reg[0]_5\, O => \fb_in_dat_reg[6]\(5) ); \fb_in_dat[6]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"8380" ) port map ( I0 => ascii_code(6), I1 => Q(0), I2 => Q(1), I3 => \counter_reg[0]_6\, O => \fb_in_dat_reg[6]\(6) ); \next_s[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"EEE0EEEE" ) port map ( I0 => D(0), I1 => \current_s_reg[0]\, I2 => Q(0), I3 => Q(1), I4 => ascii_new, O => \next_s_reg[0]\ ); \next_s[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"EEEEEEFE" ) port map ( I0 => D(1), I1 => \current_s_reg[0]\, I2 => ascii_new, I3 => Q(1), I4 => Q(0), O => \next_s_reg[1]\ ); prev_ps2_code_new_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_BUFG, CE => '1', D => ps2_code_new, Q => prev_ps2_code_new, R => '0' ); ps2_keyboard_0: entity work.ps2_keyboard port map ( D(1) => ps2_keyboard_0_n_9, D(0) => ps2_keyboard_0_n_10, E(0) => ps2_keyboard_0_n_18, PS2Clk_IBUF => PS2Clk_IBUF, PS2Data_IBUF => PS2Data_IBUF, Q(1 downto 0) => state(1 downto 0), \ascii_reg[6]\(6) => ps2_keyboard_0_n_11, \ascii_reg[6]\(5) => ps2_keyboard_0_n_12, \ascii_reg[6]\(4) => ps2_keyboard_0_n_13, \ascii_reg[6]\(3) => ps2_keyboard_0_n_14, \ascii_reg[6]\(2) => ps2_keyboard_0_n_15, \ascii_reg[6]\(1) => ps2_keyboard_0_n_16, \ascii_reg[6]\(0) => ps2_keyboard_0_n_17, \ascii_reg[7]\ => ps2_keyboard_0_n_8, \ascii_reg[7]_0\ => \ascii_reg_n_0_[7]\, break => break, break_reg => ps2_keyboard_0_n_1, caps_lock_reg => ps2_keyboard_0_n_7, caps_lock_reg_0 => caps_lock_reg_n_0, clk_BUFG => clk_BUFG, control_l_reg => ps2_keyboard_0_n_6, control_l_reg_0 => control_l_reg_n_0, control_r_reg => ps2_keyboard_0_n_5, control_r_reg_0 => control_r_reg_n_0, e0_code => e0_code, e0_code_reg => ps2_keyboard_0_n_4, prev_ps2_code_new => prev_ps2_code_new, ps2_code_new => ps2_code_new, shift_l => shift_l, shift_l_reg => ps2_keyboard_0_n_2, shift_r => shift_r, shift_r_reg => ps2_keyboard_0_n_3 ); \repeat_counter[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"00A80000" ) port map ( I0 => state(1), I1 => repeat_counter_reg(16), I2 => \repeat_counter[0]_i_3_n_0\, I3 => \ascii_reg_n_0_[7]\, I4 => state(0), O => \repeat_counter[0]_i_1_n_0\ ); \repeat_counter[0]_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000001" ) port map ( I0 => \ascii_reg_n_0_[3]\, I1 => \ascii_reg_n_0_[5]\, I2 => ascii_new_i_5_n_0, I3 => \ascii_reg_n_0_[0]\, I4 => \ascii_reg_n_0_[4]\, I5 => \ascii_reg_n_0_[6]\, O => \repeat_counter[0]_i_10_n_0\ ); \repeat_counter[0]_i_11\: unisim.vcomponents.LUT6 generic map( INIT => X"F7FFFFFFFFFFFFFF" ) port map ( I0 => repeat_counter_reg(6), I1 => repeat_counter_reg(14), I2 => \repeat_counter[0]_i_12_n_0\, I3 => repeat_counter_reg(4), I4 => repeat_counter_reg(15), I5 => repeat_counter_reg(17), O => \repeat_counter[0]_i_11_n_0\ ); \repeat_counter[0]_i_12\: unisim.vcomponents.LUT6 generic map( INIT => X"F7FFFFFFFFFFFFFF" ) port map ( I0 => repeat_counter_reg(8), I1 => repeat_counter_reg(20), I2 => ascii_new_i_3_n_0, I3 => repeat_counter_reg(13), I4 => repeat_counter_reg(3), I5 => repeat_counter_reg(9), O => \repeat_counter[0]_i_12_n_0\ ); \repeat_counter[0]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFFE" ) port map ( I0 => repeat_counter_reg(12), I1 => repeat_counter_reg(10), I2 => \repeat_counter[0]_i_9_n_0\, I3 => repeat_counter_reg(7), I4 => repeat_counter_reg(11), I5 => repeat_counter_reg(19), O => \repeat_counter[0]_i_3_n_0\ ); \repeat_counter[0]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \repeat_counter[0]_i_10_n_0\, I1 => repeat_counter_reg(0), O => \repeat_counter[0]_i_4_n_0\ ); \repeat_counter[0]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \repeat_counter[0]_i_10_n_0\, I1 => repeat_counter_reg(3), O => \repeat_counter[0]_i_5_n_0\ ); \repeat_counter[0]_i_6\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \repeat_counter[0]_i_10_n_0\, I1 => repeat_counter_reg(2), O => \repeat_counter[0]_i_6_n_0\ ); \repeat_counter[0]_i_7\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \repeat_counter[0]_i_10_n_0\, I1 => repeat_counter_reg(1), O => \repeat_counter[0]_i_7_n_0\ ); \repeat_counter[0]_i_8\: unisim.vcomponents.LUT2 generic map( INIT => X"4" ) port map ( I0 => repeat_counter_reg(0), I1 => \repeat_counter[0]_i_10_n_0\, O => \repeat_counter[0]_i_8_n_0\ ); \repeat_counter[0]_i_9\: unisim.vcomponents.LUT6 generic map( INIT => X"FFF7FFFFFFFFFFFF" ) port map ( I0 => repeat_counter_reg(0), I1 => repeat_counter_reg(1), I2 => \repeat_counter[0]_i_11_n_0\, I3 => repeat_counter_reg(5), I4 => repeat_counter_reg(2), I5 => repeat_counter_reg(18), O => \repeat_counter[0]_i_9_n_0\ ); \repeat_counter[12]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \repeat_counter[0]_i_10_n_0\, I1 => repeat_counter_reg(15), O => \repeat_counter[12]_i_2_n_0\ ); \repeat_counter[12]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \repeat_counter[0]_i_10_n_0\, I1 => repeat_counter_reg(14), O => \repeat_counter[12]_i_3_n_0\ ); \repeat_counter[12]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \repeat_counter[0]_i_10_n_0\, I1 => repeat_counter_reg(13), O => \repeat_counter[12]_i_4_n_0\ ); \repeat_counter[12]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \repeat_counter[0]_i_10_n_0\, I1 => repeat_counter_reg(12), O => \repeat_counter[12]_i_5_n_0\ ); \repeat_counter[16]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \repeat_counter[0]_i_10_n_0\, I1 => repeat_counter_reg(19), O => \repeat_counter[16]_i_2_n_0\ ); \repeat_counter[16]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \repeat_counter[0]_i_10_n_0\, I1 => repeat_counter_reg(18), O => \repeat_counter[16]_i_3_n_0\ ); \repeat_counter[16]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \repeat_counter[0]_i_10_n_0\, I1 => repeat_counter_reg(17), O => \repeat_counter[16]_i_4_n_0\ ); \repeat_counter[16]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \repeat_counter[0]_i_10_n_0\, I1 => repeat_counter_reg(16), O => \repeat_counter[16]_i_5_n_0\ ); \repeat_counter[20]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \repeat_counter[0]_i_10_n_0\, I1 => repeat_counter_reg(20), O => \repeat_counter[20]_i_2_n_0\ ); \repeat_counter[4]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \repeat_counter[0]_i_10_n_0\, I1 => repeat_counter_reg(7), O => \repeat_counter[4]_i_2_n_0\ ); \repeat_counter[4]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \repeat_counter[0]_i_10_n_0\, I1 => repeat_counter_reg(6), O => \repeat_counter[4]_i_3_n_0\ ); \repeat_counter[4]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \repeat_counter[0]_i_10_n_0\, I1 => repeat_counter_reg(5), O => \repeat_counter[4]_i_4_n_0\ ); \repeat_counter[4]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \repeat_counter[0]_i_10_n_0\, I1 => repeat_counter_reg(4), O => \repeat_counter[4]_i_5_n_0\ ); \repeat_counter[8]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \repeat_counter[0]_i_10_n_0\, I1 => repeat_counter_reg(11), O => \repeat_counter[8]_i_2_n_0\ ); \repeat_counter[8]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \repeat_counter[0]_i_10_n_0\, I1 => repeat_counter_reg(10), O => \repeat_counter[8]_i_3_n_0\ ); \repeat_counter[8]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \repeat_counter[0]_i_10_n_0\, I1 => repeat_counter_reg(9), O => \repeat_counter[8]_i_4_n_0\ ); \repeat_counter[8]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \repeat_counter[0]_i_10_n_0\, I1 => repeat_counter_reg(8), O => \repeat_counter[8]_i_5_n_0\ ); \repeat_counter_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \repeat_counter[0]_i_1_n_0\, D => \repeat_counter_reg[0]_i_2_n_7\, Q => repeat_counter_reg(0), R => '0' ); \repeat_counter_reg[0]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \repeat_counter_reg[0]_i_2_n_0\, CO(2 downto 0) => \NLW_repeat_counter_reg[0]_i_2_CO_UNCONNECTED\(2 downto 0), CYINIT => '0', DI(3 downto 1) => B"000", DI(0) => \repeat_counter[0]_i_4_n_0\, O(3) => \repeat_counter_reg[0]_i_2_n_4\, O(2) => \repeat_counter_reg[0]_i_2_n_5\, O(1) => \repeat_counter_reg[0]_i_2_n_6\, O(0) => \repeat_counter_reg[0]_i_2_n_7\, S(3) => \repeat_counter[0]_i_5_n_0\, S(2) => \repeat_counter[0]_i_6_n_0\, S(1) => \repeat_counter[0]_i_7_n_0\, S(0) => \repeat_counter[0]_i_8_n_0\ ); \repeat_counter_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \repeat_counter[0]_i_1_n_0\, D => \repeat_counter_reg[8]_i_1_n_5\, Q => repeat_counter_reg(10), R => '0' ); \repeat_counter_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \repeat_counter[0]_i_1_n_0\, D => \repeat_counter_reg[8]_i_1_n_4\, Q => repeat_counter_reg(11), R => '0' ); \repeat_counter_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \repeat_counter[0]_i_1_n_0\, D => \repeat_counter_reg[12]_i_1_n_7\, Q => repeat_counter_reg(12), R => '0' ); \repeat_counter_reg[12]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \repeat_counter_reg[8]_i_1_n_0\, CO(3) => \repeat_counter_reg[12]_i_1_n_0\, CO(2 downto 0) => \NLW_repeat_counter_reg[12]_i_1_CO_UNCONNECTED\(2 downto 0), CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \repeat_counter_reg[12]_i_1_n_4\, O(2) => \repeat_counter_reg[12]_i_1_n_5\, O(1) => \repeat_counter_reg[12]_i_1_n_6\, O(0) => \repeat_counter_reg[12]_i_1_n_7\, S(3) => \repeat_counter[12]_i_2_n_0\, S(2) => \repeat_counter[12]_i_3_n_0\, S(1) => \repeat_counter[12]_i_4_n_0\, S(0) => \repeat_counter[12]_i_5_n_0\ ); \repeat_counter_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \repeat_counter[0]_i_1_n_0\, D => \repeat_counter_reg[12]_i_1_n_6\, Q => repeat_counter_reg(13), R => '0' ); \repeat_counter_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \repeat_counter[0]_i_1_n_0\, D => \repeat_counter_reg[12]_i_1_n_5\, Q => repeat_counter_reg(14), R => '0' ); \repeat_counter_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \repeat_counter[0]_i_1_n_0\, D => \repeat_counter_reg[12]_i_1_n_4\, Q => repeat_counter_reg(15), R => '0' ); \repeat_counter_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \repeat_counter[0]_i_1_n_0\, D => \repeat_counter_reg[16]_i_1_n_7\, Q => repeat_counter_reg(16), R => '0' ); \repeat_counter_reg[16]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \repeat_counter_reg[12]_i_1_n_0\, CO(3) => \repeat_counter_reg[16]_i_1_n_0\, CO(2 downto 0) => \NLW_repeat_counter_reg[16]_i_1_CO_UNCONNECTED\(2 downto 0), CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \repeat_counter_reg[16]_i_1_n_4\, O(2) => \repeat_counter_reg[16]_i_1_n_5\, O(1) => \repeat_counter_reg[16]_i_1_n_6\, O(0) => \repeat_counter_reg[16]_i_1_n_7\, S(3) => \repeat_counter[16]_i_2_n_0\, S(2) => \repeat_counter[16]_i_3_n_0\, S(1) => \repeat_counter[16]_i_4_n_0\, S(0) => \repeat_counter[16]_i_5_n_0\ ); \repeat_counter_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \repeat_counter[0]_i_1_n_0\, D => \repeat_counter_reg[16]_i_1_n_6\, Q => repeat_counter_reg(17), R => '0' ); \repeat_counter_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \repeat_counter[0]_i_1_n_0\, D => \repeat_counter_reg[16]_i_1_n_5\, Q => repeat_counter_reg(18), R => '0' ); \repeat_counter_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \repeat_counter[0]_i_1_n_0\, D => \repeat_counter_reg[16]_i_1_n_4\, Q => repeat_counter_reg(19), R => '0' ); \repeat_counter_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \repeat_counter[0]_i_1_n_0\, D => \repeat_counter_reg[0]_i_2_n_6\, Q => repeat_counter_reg(1), R => '0' ); \repeat_counter_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \repeat_counter[0]_i_1_n_0\, D => \repeat_counter_reg[20]_i_1_n_7\, Q => repeat_counter_reg(20), R => '0' ); \repeat_counter_reg[20]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \repeat_counter_reg[16]_i_1_n_0\, CO(3 downto 0) => \NLW_repeat_counter_reg[20]_i_1_CO_UNCONNECTED\(3 downto 0), CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 1) => \NLW_repeat_counter_reg[20]_i_1_O_UNCONNECTED\(3 downto 1), O(0) => \repeat_counter_reg[20]_i_1_n_7\, S(3 downto 1) => B"000", S(0) => \repeat_counter[20]_i_2_n_0\ ); \repeat_counter_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \repeat_counter[0]_i_1_n_0\, D => \repeat_counter_reg[0]_i_2_n_5\, Q => repeat_counter_reg(2), R => '0' ); \repeat_counter_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \repeat_counter[0]_i_1_n_0\, D => \repeat_counter_reg[0]_i_2_n_4\, Q => repeat_counter_reg(3), R => '0' ); \repeat_counter_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \repeat_counter[0]_i_1_n_0\, D => \repeat_counter_reg[4]_i_1_n_7\, Q => repeat_counter_reg(4), R => '0' ); \repeat_counter_reg[4]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \repeat_counter_reg[0]_i_2_n_0\, CO(3) => \repeat_counter_reg[4]_i_1_n_0\, CO(2 downto 0) => \NLW_repeat_counter_reg[4]_i_1_CO_UNCONNECTED\(2 downto 0), CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \repeat_counter_reg[4]_i_1_n_4\, O(2) => \repeat_counter_reg[4]_i_1_n_5\, O(1) => \repeat_counter_reg[4]_i_1_n_6\, O(0) => \repeat_counter_reg[4]_i_1_n_7\, S(3) => \repeat_counter[4]_i_2_n_0\, S(2) => \repeat_counter[4]_i_3_n_0\, S(1) => \repeat_counter[4]_i_4_n_0\, S(0) => \repeat_counter[4]_i_5_n_0\ ); \repeat_counter_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \repeat_counter[0]_i_1_n_0\, D => \repeat_counter_reg[4]_i_1_n_6\, Q => repeat_counter_reg(5), R => '0' ); \repeat_counter_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \repeat_counter[0]_i_1_n_0\, D => \repeat_counter_reg[4]_i_1_n_5\, Q => repeat_counter_reg(6), R => '0' ); \repeat_counter_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \repeat_counter[0]_i_1_n_0\, D => \repeat_counter_reg[4]_i_1_n_4\, Q => repeat_counter_reg(7), R => '0' ); \repeat_counter_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \repeat_counter[0]_i_1_n_0\, D => \repeat_counter_reg[8]_i_1_n_7\, Q => repeat_counter_reg(8), R => '0' ); \repeat_counter_reg[8]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \repeat_counter_reg[4]_i_1_n_0\, CO(3) => \repeat_counter_reg[8]_i_1_n_0\, CO(2 downto 0) => \NLW_repeat_counter_reg[8]_i_1_CO_UNCONNECTED\(2 downto 0), CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \repeat_counter_reg[8]_i_1_n_4\, O(2) => \repeat_counter_reg[8]_i_1_n_5\, O(1) => \repeat_counter_reg[8]_i_1_n_6\, O(0) => \repeat_counter_reg[8]_i_1_n_7\, S(3) => \repeat_counter[8]_i_2_n_0\, S(2) => \repeat_counter[8]_i_3_n_0\, S(1) => \repeat_counter[8]_i_4_n_0\, S(0) => \repeat_counter[8]_i_5_n_0\ ); \repeat_counter_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \repeat_counter[0]_i_1_n_0\, D => \repeat_counter_reg[8]_i_1_n_6\, Q => repeat_counter_reg(9), R => '0' ); shift_l_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => '1', D => ps2_keyboard_0_n_2, Q => shift_l, R => '0' ); shift_r_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => '1', D => ps2_keyboard_0_n_3, Q => shift_r, R => '0' ); \state_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => '1', D => ps2_keyboard_0_n_10, Q => state(0), R => '0' ); \state_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => '1', D => ps2_keyboard_0_n_9, Q => state(1), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity FrameBuffer_blk_mem_gen_generic_cstr is port ( doutb : out STD_LOGIC_VECTOR ( 7 downto 0 ); clka : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr"; end FrameBuffer_blk_mem_gen_generic_cstr; architecture STRUCTURE of FrameBuffer_blk_mem_gen_generic_cstr is signal ram_doutb : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \ramloop[1].ram.r_n_0\ : STD_LOGIC; signal \ramloop[1].ram.r_n_1\ : STD_LOGIC; signal \ramloop[1].ram.r_n_2\ : STD_LOGIC; signal \ramloop[1].ram.r_n_3\ : STD_LOGIC; signal \ramloop[1].ram.r_n_4\ : STD_LOGIC; signal \ramloop[1].ram.r_n_5\ : STD_LOGIC; signal \ramloop[1].ram.r_n_6\ : STD_LOGIC; signal \ramloop[1].ram.r_n_7\ : STD_LOGIC; signal \ramloop[2].ram.r_n_0\ : STD_LOGIC; signal \ramloop[2].ram.r_n_1\ : STD_LOGIC; signal \ramloop[2].ram.r_n_2\ : STD_LOGIC; signal \ramloop[2].ram.r_n_3\ : STD_LOGIC; signal \ramloop[2].ram.r_n_4\ : STD_LOGIC; signal \ramloop[2].ram.r_n_5\ : STD_LOGIC; signal \ramloop[2].ram.r_n_6\ : STD_LOGIC; signal \ramloop[2].ram.r_n_7\ : STD_LOGIC; begin \has_mux_b.B\: entity work.\FrameBuffer_blk_mem_gen_mux__parameterized0\ port map ( \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(7) => \ramloop[1].ram.r_n_0\, \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(6) => \ramloop[1].ram.r_n_1\, \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(5) => \ramloop[1].ram.r_n_2\, \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(4) => \ramloop[1].ram.r_n_3\, \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(3) => \ramloop[1].ram.r_n_4\, \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(2) => \ramloop[1].ram.r_n_5\, \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(1) => \ramloop[1].ram.r_n_6\, \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(0) => \ramloop[1].ram.r_n_7\, \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(7 downto 0) => ram_doutb(7 downto 0), DOBDO(7) => \ramloop[2].ram.r_n_0\, DOBDO(6) => \ramloop[2].ram.r_n_1\, DOBDO(5) => \ramloop[2].ram.r_n_2\, DOBDO(4) => \ramloop[2].ram.r_n_3\, DOBDO(3) => \ramloop[2].ram.r_n_4\, DOBDO(2) => \ramloop[2].ram.r_n_5\, DOBDO(1) => \ramloop[2].ram.r_n_6\, DOBDO(0) => \ramloop[2].ram.r_n_7\, addrb(2 downto 0) => addrb(13 downto 11), clkb => clkb, doutb(7 downto 0) => doutb(7 downto 0) ); \ramloop[0].ram.r\: entity work.FrameBuffer_blk_mem_gen_prim_width port map ( addra(13 downto 0) => addra(13 downto 0), addrb(13 downto 0) => addrb(13 downto 0), clka => clka, clkb => clkb, dina(7 downto 0) => dina(7 downto 0), \doutb[7]\(7 downto 0) => ram_doutb(7 downto 0), wea(0) => wea(0) ); \ramloop[1].ram.r\: entity work.\FrameBuffer_blk_mem_gen_prim_width__parameterized0\ port map ( addra(13 downto 0) => addra(13 downto 0), addrb(13 downto 0) => addrb(13 downto 0), clka => clka, clkb => clkb, dina(7 downto 0) => dina(7 downto 0), \doutb[7]\(7) => \ramloop[1].ram.r_n_0\, \doutb[7]\(6) => \ramloop[1].ram.r_n_1\, \doutb[7]\(5) => \ramloop[1].ram.r_n_2\, \doutb[7]\(4) => \ramloop[1].ram.r_n_3\, \doutb[7]\(3) => \ramloop[1].ram.r_n_4\, \doutb[7]\(2) => \ramloop[1].ram.r_n_5\, \doutb[7]\(1) => \ramloop[1].ram.r_n_6\, \doutb[7]\(0) => \ramloop[1].ram.r_n_7\, wea(0) => wea(0) ); \ramloop[2].ram.r\: entity work.\FrameBuffer_blk_mem_gen_prim_width__parameterized1\ port map ( DOBDO(7) => \ramloop[2].ram.r_n_0\, DOBDO(6) => \ramloop[2].ram.r_n_1\, DOBDO(5) => \ramloop[2].ram.r_n_2\, DOBDO(4) => \ramloop[2].ram.r_n_3\, DOBDO(3) => \ramloop[2].ram.r_n_4\, DOBDO(2) => \ramloop[2].ram.r_n_5\, DOBDO(1) => \ramloop[2].ram.r_n_6\, DOBDO(0) => \ramloop[2].ram.r_n_7\, addra(13 downto 0) => addra(13 downto 0), addrb(13 downto 0) => addrb(13 downto 0), clka => clka, clkb => clkb, dina(7 downto 0) => dina(7 downto 0), wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity FrameBuffer_blk_mem_gen_top is port ( doutb : out STD_LOGIC_VECTOR ( 7 downto 0 ); clka : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_top : entity is "blk_mem_gen_top"; end FrameBuffer_blk_mem_gen_top; architecture STRUCTURE of FrameBuffer_blk_mem_gen_top is begin \valid.cstr\: entity work.FrameBuffer_blk_mem_gen_generic_cstr port map ( addra(13 downto 0) => addra(13 downto 0), addrb(13 downto 0) => addrb(13 downto 0), clka => clka, clkb => clkb, dina(7 downto 0) => dina(7 downto 0), doutb(7 downto 0) => doutb(7 downto 0), wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity FrameBuffer_blk_mem_gen_v8_3_1_synth is port ( doutb : out STD_LOGIC_VECTOR ( 7 downto 0 ); clka : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_v8_3_1_synth : entity is "blk_mem_gen_v8_3_1_synth"; end FrameBuffer_blk_mem_gen_v8_3_1_synth; architecture STRUCTURE of FrameBuffer_blk_mem_gen_v8_3_1_synth is begin \gnativebmg.native_blk_mem_gen\: entity work.FrameBuffer_blk_mem_gen_top port map ( addra(13 downto 0) => addra(13 downto 0), addrb(13 downto 0) => addrb(13 downto 0), clka => clka, clkb => clkb, dina(7 downto 0) => dina(7 downto 0), doutb(7 downto 0) => doutb(7 downto 0), wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity FrameBuffer_blk_mem_gen_v8_3_1 is port ( clka : in STD_LOGIC; rsta : in STD_LOGIC; ena : in STD_LOGIC; regcea : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); douta : out STD_LOGIC_VECTOR ( 7 downto 0 ); clkb : in STD_LOGIC; rstb : in STD_LOGIC; enb : in STD_LOGIC; regceb : in STD_LOGIC; web : in STD_LOGIC_VECTOR ( 0 to 0 ); addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 7 downto 0 ); doutb : out STD_LOGIC_VECTOR ( 7 downto 0 ); injectsbiterr : in STD_LOGIC; injectdbiterr : in STD_LOGIC; eccpipece : in STD_LOGIC; sbiterr : out STD_LOGIC; dbiterr : out STD_LOGIC; rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 ); sleep : in STD_LOGIC; deepsleep : in STD_LOGIC; shutdown : in STD_LOGIC; rsta_busy : out STD_LOGIC; rstb_busy : out STD_LOGIC; s_aclk : in STD_LOGIC; s_aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; s_axi_injectsbiterr : in STD_LOGIC; s_axi_injectdbiterr : in STD_LOGIC; s_axi_sbiterr : out STD_LOGIC; s_axi_dbiterr : out STD_LOGIC; s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 ) ); attribute C_ADDRA_WIDTH : integer; attribute C_ADDRA_WIDTH of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 14; attribute C_ADDRB_WIDTH : integer; attribute C_ADDRB_WIDTH of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 14; attribute C_ALGORITHM : integer; attribute C_ALGORITHM of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 4; attribute C_AXI_SLAVE_TYPE : integer; attribute C_AXI_SLAVE_TYPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_AXI_TYPE : integer; attribute C_AXI_TYPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1; attribute C_BYTE_SIZE : integer; attribute C_BYTE_SIZE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 8; attribute C_COMMON_CLK : integer; attribute C_COMMON_CLK of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_COUNT_18K_BRAM : string; attribute C_COUNT_18K_BRAM of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "1"; attribute C_COUNT_36K_BRAM : string; attribute C_COUNT_36K_BRAM of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "2"; attribute C_CTRL_ECC_ALGO : string; attribute C_CTRL_ECC_ALGO of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "NONE"; attribute C_DEFAULT_DATA : string; attribute C_DEFAULT_DATA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "20"; attribute C_DISABLE_WARN_BHV_COLL : integer; attribute C_DISABLE_WARN_BHV_COLL of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_DISABLE_WARN_BHV_RANGE : integer; attribute C_DISABLE_WARN_BHV_RANGE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_ELABORATION_DIR : string; attribute C_ELABORATION_DIR of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "./"; attribute C_ENABLE_32BIT_ADDRESS : integer; attribute C_ENABLE_32BIT_ADDRESS of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_EN_DEEPSLEEP_PIN : integer; attribute C_EN_DEEPSLEEP_PIN of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_EN_ECC_PIPE : integer; attribute C_EN_ECC_PIPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_EN_RDADDRA_CHG : integer; attribute C_EN_RDADDRA_CHG of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_EN_RDADDRB_CHG : integer; attribute C_EN_RDADDRB_CHG of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_EN_SAFETY_CKT : integer; attribute C_EN_SAFETY_CKT of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_EN_SHUTDOWN_PIN : integer; attribute C_EN_SHUTDOWN_PIN of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_EN_SLEEP_PIN : integer; attribute C_EN_SLEEP_PIN of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_EST_POWER_SUMMARY : string; attribute C_EST_POWER_SUMMARY of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "Estimated Power for IP : 4.58651 mW"; attribute C_FAMILY : string; attribute C_FAMILY of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "artix7"; attribute C_HAS_AXI_ID : integer; attribute C_HAS_AXI_ID of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_ENA : integer; attribute C_HAS_ENA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_ENB : integer; attribute C_HAS_ENB of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_INJECTERR : integer; attribute C_HAS_INJECTERR of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_MEM_OUTPUT_REGS_A : integer; attribute C_HAS_MEM_OUTPUT_REGS_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_MEM_OUTPUT_REGS_B : integer; attribute C_HAS_MEM_OUTPUT_REGS_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_MUX_OUTPUT_REGS_A : integer; attribute C_HAS_MUX_OUTPUT_REGS_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_MUX_OUTPUT_REGS_B : integer; attribute C_HAS_MUX_OUTPUT_REGS_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_REGCEA : integer; attribute C_HAS_REGCEA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_REGCEB : integer; attribute C_HAS_REGCEB of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_RSTA : integer; attribute C_HAS_RSTA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_RSTB : integer; attribute C_HAS_RSTB of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; attribute C_HAS_SOFTECC_INPUT_REGS_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; attribute C_HAS_SOFTECC_OUTPUT_REGS_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_INITA_VAL : string; attribute C_INITA_VAL of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "0"; attribute C_INITB_VAL : string; attribute C_INITB_VAL of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "0"; attribute C_INIT_FILE : string; attribute C_INIT_FILE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "FrameBuffer.mem"; attribute C_INIT_FILE_NAME : string; attribute C_INIT_FILE_NAME of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "FrameBuffer.mif"; attribute C_INTERFACE_TYPE : integer; attribute C_INTERFACE_TYPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_LOAD_INIT_FILE : integer; attribute C_LOAD_INIT_FILE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1; attribute C_MEM_TYPE : integer; attribute C_MEM_TYPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1; attribute C_MUX_PIPELINE_STAGES : integer; attribute C_MUX_PIPELINE_STAGES of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_PRIM_TYPE : integer; attribute C_PRIM_TYPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1; attribute C_READ_DEPTH_A : integer; attribute C_READ_DEPTH_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 10240; attribute C_READ_DEPTH_B : integer; attribute C_READ_DEPTH_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 10240; attribute C_READ_WIDTH_A : integer; attribute C_READ_WIDTH_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 8; attribute C_READ_WIDTH_B : integer; attribute C_READ_WIDTH_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 8; attribute C_RSTRAM_A : integer; attribute C_RSTRAM_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_RSTRAM_B : integer; attribute C_RSTRAM_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_RST_PRIORITY_A : string; attribute C_RST_PRIORITY_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "CE"; attribute C_RST_PRIORITY_B : string; attribute C_RST_PRIORITY_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "CE"; attribute C_SIM_COLLISION_CHECK : string; attribute C_SIM_COLLISION_CHECK of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "ALL"; attribute C_USE_BRAM_BLOCK : integer; attribute C_USE_BRAM_BLOCK of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_USE_BYTE_WEA : integer; attribute C_USE_BYTE_WEA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1; attribute C_USE_BYTE_WEB : integer; attribute C_USE_BYTE_WEB of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1; attribute C_USE_DEFAULT_DATA : integer; attribute C_USE_DEFAULT_DATA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1; attribute C_USE_ECC : integer; attribute C_USE_ECC of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_USE_SOFTECC : integer; attribute C_USE_SOFTECC of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_USE_URAM : integer; attribute C_USE_URAM of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_WEA_WIDTH : integer; attribute C_WEA_WIDTH of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1; attribute C_WEB_WIDTH : integer; attribute C_WEB_WIDTH of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1; attribute C_WRITE_DEPTH_A : integer; attribute C_WRITE_DEPTH_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 10240; attribute C_WRITE_DEPTH_B : integer; attribute C_WRITE_DEPTH_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 10240; attribute C_WRITE_MODE_A : string; attribute C_WRITE_MODE_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "READ_FIRST"; attribute C_WRITE_MODE_B : string; attribute C_WRITE_MODE_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "WRITE_FIRST"; attribute C_WRITE_WIDTH_A : integer; attribute C_WRITE_WIDTH_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 8; attribute C_WRITE_WIDTH_B : integer; attribute C_WRITE_WIDTH_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 8; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "artix7"; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "blk_mem_gen_v8_3_1"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "yes"; end FrameBuffer_blk_mem_gen_v8_3_1; architecture STRUCTURE of FrameBuffer_blk_mem_gen_v8_3_1 is begin dbiterr <= 'Z'; rsta_busy <= 'Z'; rstb_busy <= 'Z'; s_axi_arready <= 'Z'; s_axi_awready <= 'Z'; s_axi_bvalid <= 'Z'; s_axi_dbiterr <= 'Z'; s_axi_rlast <= 'Z'; s_axi_rvalid <= 'Z'; s_axi_sbiterr <= 'Z'; s_axi_wready <= 'Z'; sbiterr <= 'Z'; douta(0) <= 'Z'; douta(1) <= 'Z'; douta(2) <= 'Z'; douta(3) <= 'Z'; douta(4) <= 'Z'; douta(5) <= 'Z'; douta(6) <= 'Z'; douta(7) <= 'Z'; rdaddrecc(0) <= 'Z'; rdaddrecc(1) <= 'Z'; rdaddrecc(2) <= 'Z'; rdaddrecc(3) <= 'Z'; rdaddrecc(4) <= 'Z'; rdaddrecc(5) <= 'Z'; rdaddrecc(6) <= 'Z'; rdaddrecc(7) <= 'Z'; rdaddrecc(8) <= 'Z'; rdaddrecc(9) <= 'Z'; rdaddrecc(10) <= 'Z'; rdaddrecc(11) <= 'Z'; rdaddrecc(12) <= 'Z'; rdaddrecc(13) <= 'Z'; s_axi_bid(0) <= 'Z'; s_axi_bid(1) <= 'Z'; s_axi_bid(2) <= 'Z'; s_axi_bid(3) <= 'Z'; s_axi_bresp(0) <= 'Z'; s_axi_bresp(1) <= 'Z'; s_axi_rdaddrecc(0) <= 'Z'; s_axi_rdaddrecc(1) <= 'Z'; s_axi_rdaddrecc(2) <= 'Z'; s_axi_rdaddrecc(3) <= 'Z'; s_axi_rdaddrecc(4) <= 'Z'; s_axi_rdaddrecc(5) <= 'Z'; s_axi_rdaddrecc(6) <= 'Z'; s_axi_rdaddrecc(7) <= 'Z'; s_axi_rdaddrecc(8) <= 'Z'; s_axi_rdaddrecc(9) <= 'Z'; s_axi_rdaddrecc(10) <= 'Z'; s_axi_rdaddrecc(11) <= 'Z'; s_axi_rdaddrecc(12) <= 'Z'; s_axi_rdaddrecc(13) <= 'Z'; s_axi_rdata(0) <= 'Z'; s_axi_rdata(1) <= 'Z'; s_axi_rdata(2) <= 'Z'; s_axi_rdata(3) <= 'Z'; s_axi_rdata(4) <= 'Z'; s_axi_rdata(5) <= 'Z'; s_axi_rdata(6) <= 'Z'; s_axi_rdata(7) <= 'Z'; s_axi_rid(0) <= 'Z'; s_axi_rid(1) <= 'Z'; s_axi_rid(2) <= 'Z'; s_axi_rid(3) <= 'Z'; s_axi_rresp(0) <= 'Z'; s_axi_rresp(1) <= 'Z'; inst_blk_mem_gen: entity work.FrameBuffer_blk_mem_gen_v8_3_1_synth port map ( addra(13 downto 0) => addra(13 downto 0), addrb(13 downto 0) => addrb(13 downto 0), clka => clka, clkb => clkb, dina(7 downto 0) => dina(7 downto 0), doutb(7 downto 0) => doutb(7 downto 0), wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity FrameBuffer is port ( clka : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); clkb : in STD_LOGIC; addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); doutb : out STD_LOGIC_VECTOR ( 7 downto 0 ) ); attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of FrameBuffer : entity is "FrameBuffer,blk_mem_gen_v8_3_1,{}"; attribute CORE_GENERATION_INFO : string; attribute CORE_GENERATION_INFO of FrameBuffer : entity is "FrameBuffer,blk_mem_gen_v8_3_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=8,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=FrameBuffer.mif,C_INIT_FILE=FrameBuffer.mem,C_USE_DEFAULT_DATA=1,C_DEFAULT_DATA=20,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=1,C_WEA_WIDTH=1,C_WRITE_MODE_A=READ_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=10240,C_READ_DEPTH_A=10240,C_ADDRA_WIDTH=14,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=1,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=10240,C_READ_DEPTH_B=10240,C_ADDRB_WIDTH=14,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=2,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 4.58651 mW}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of FrameBuffer : entity is "yes"; attribute x_core_info : string; attribute x_core_info of FrameBuffer : entity is "blk_mem_gen_v8_3_1,Vivado 2015.4"; end FrameBuffer; architecture STRUCTURE of FrameBuffer is signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_deepsleep_UNCONNECTED : STD_LOGIC; signal NLW_U0_eccpipece_UNCONNECTED : STD_LOGIC; signal NLW_U0_ena_UNCONNECTED : STD_LOGIC; signal NLW_U0_enb_UNCONNECTED : STD_LOGIC; signal NLW_U0_injectdbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_injectsbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_regcea_UNCONNECTED : STD_LOGIC; signal NLW_U0_regceb_UNCONNECTED : STD_LOGIC; signal NLW_U0_rsta_UNCONNECTED : STD_LOGIC; signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC; signal NLW_U0_rstb_UNCONNECTED : STD_LOGIC; signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_aclk_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_aresetn_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_arvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_awvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_bready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_injectdbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_injectsbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_rready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_wlast_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_wvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_shutdown_UNCONNECTED : STD_LOGIC; signal NLW_U0_sleep_UNCONNECTED : STD_LOGIC; signal NLW_U0_dinb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 ); signal NLW_U0_s_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_U0_s_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_U0_s_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_s_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_U0_s_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_U0_s_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_U0_s_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_U0_s_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_s_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_U0_s_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 ); signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_U0_s_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_U0_s_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_web_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); attribute C_ADDRA_WIDTH : integer; attribute C_ADDRA_WIDTH of U0 : label is 14; attribute C_ADDRB_WIDTH : integer; attribute C_ADDRB_WIDTH of U0 : label is 14; attribute C_ALGORITHM : integer; attribute C_ALGORITHM of U0 : label is 1; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of U0 : label is 4; attribute C_AXI_SLAVE_TYPE : integer; attribute C_AXI_SLAVE_TYPE of U0 : label is 0; attribute C_AXI_TYPE : integer; attribute C_AXI_TYPE of U0 : label is 1; attribute C_BYTE_SIZE : integer; attribute C_BYTE_SIZE of U0 : label is 8; attribute C_COMMON_CLK : integer; attribute C_COMMON_CLK of U0 : label is 0; attribute C_COUNT_18K_BRAM : string; attribute C_COUNT_18K_BRAM of U0 : label is "1"; attribute C_COUNT_36K_BRAM : string; attribute C_COUNT_36K_BRAM of U0 : label is "2"; attribute C_CTRL_ECC_ALGO : string; attribute C_CTRL_ECC_ALGO of U0 : label is "NONE"; attribute C_DEFAULT_DATA : string; attribute C_DEFAULT_DATA of U0 : label is "20"; attribute C_DISABLE_WARN_BHV_COLL : integer; attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0; attribute C_DISABLE_WARN_BHV_RANGE : integer; attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0; attribute C_ELABORATION_DIR : string; attribute C_ELABORATION_DIR of U0 : label is "./"; attribute C_ENABLE_32BIT_ADDRESS : integer; attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0; attribute C_EN_DEEPSLEEP_PIN : integer; attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0; attribute C_EN_ECC_PIPE : integer; attribute C_EN_ECC_PIPE of U0 : label is 0; attribute C_EN_RDADDRA_CHG : integer; attribute C_EN_RDADDRA_CHG of U0 : label is 0; attribute C_EN_RDADDRB_CHG : integer; attribute C_EN_RDADDRB_CHG of U0 : label is 0; attribute C_EN_SAFETY_CKT : integer; attribute C_EN_SAFETY_CKT of U0 : label is 0; attribute C_EN_SHUTDOWN_PIN : integer; attribute C_EN_SHUTDOWN_PIN of U0 : label is 0; attribute C_EN_SLEEP_PIN : integer; attribute C_EN_SLEEP_PIN of U0 : label is 0; attribute C_EST_POWER_SUMMARY : string; attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 4.58651 mW"; attribute C_FAMILY : string; attribute C_FAMILY of U0 : label is "artix7"; attribute C_HAS_AXI_ID : integer; attribute C_HAS_AXI_ID of U0 : label is 0; attribute C_HAS_ENA : integer; attribute C_HAS_ENA of U0 : label is 0; attribute C_HAS_ENB : integer; attribute C_HAS_ENB of U0 : label is 0; attribute C_HAS_INJECTERR : integer; attribute C_HAS_INJECTERR of U0 : label is 0; attribute C_HAS_MEM_OUTPUT_REGS_A : integer; attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0; attribute C_HAS_MEM_OUTPUT_REGS_B : integer; attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0; attribute C_HAS_MUX_OUTPUT_REGS_A : integer; attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0; attribute C_HAS_MUX_OUTPUT_REGS_B : integer; attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0; attribute C_HAS_REGCEA : integer; attribute C_HAS_REGCEA of U0 : label is 0; attribute C_HAS_REGCEB : integer; attribute C_HAS_REGCEB of U0 : label is 0; attribute C_HAS_RSTA : integer; attribute C_HAS_RSTA of U0 : label is 0; attribute C_HAS_RSTB : integer; attribute C_HAS_RSTB of U0 : label is 0; attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0; attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0; attribute C_INITA_VAL : string; attribute C_INITA_VAL of U0 : label is "0"; attribute C_INITB_VAL : string; attribute C_INITB_VAL of U0 : label is "0"; attribute C_INIT_FILE : string; attribute C_INIT_FILE of U0 : label is "FrameBuffer.mem"; attribute C_INIT_FILE_NAME : string; attribute C_INIT_FILE_NAME of U0 : label is "FrameBuffer.mif"; attribute C_INTERFACE_TYPE : integer; attribute C_INTERFACE_TYPE of U0 : label is 0; attribute C_LOAD_INIT_FILE : integer; attribute C_LOAD_INIT_FILE of U0 : label is 1; attribute C_MEM_TYPE : integer; attribute C_MEM_TYPE of U0 : label is 1; attribute C_MUX_PIPELINE_STAGES : integer; attribute C_MUX_PIPELINE_STAGES of U0 : label is 0; attribute C_PRIM_TYPE : integer; attribute C_PRIM_TYPE of U0 : label is 1; attribute C_READ_DEPTH_A : integer; attribute C_READ_DEPTH_A of U0 : label is 10240; attribute C_READ_DEPTH_B : integer; attribute C_READ_DEPTH_B of U0 : label is 10240; attribute C_READ_WIDTH_A : integer; attribute C_READ_WIDTH_A of U0 : label is 8; attribute C_READ_WIDTH_B : integer; attribute C_READ_WIDTH_B of U0 : label is 8; attribute C_RSTRAM_A : integer; attribute C_RSTRAM_A of U0 : label is 0; attribute C_RSTRAM_B : integer; attribute C_RSTRAM_B of U0 : label is 0; attribute C_RST_PRIORITY_A : string; attribute C_RST_PRIORITY_A of U0 : label is "CE"; attribute C_RST_PRIORITY_B : string; attribute C_RST_PRIORITY_B of U0 : label is "CE"; attribute C_SIM_COLLISION_CHECK : string; attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL"; attribute C_USE_BRAM_BLOCK : integer; attribute C_USE_BRAM_BLOCK of U0 : label is 0; attribute C_USE_BYTE_WEA : integer; attribute C_USE_BYTE_WEA of U0 : label is 1; attribute C_USE_BYTE_WEB : integer; attribute C_USE_BYTE_WEB of U0 : label is 1; attribute C_USE_DEFAULT_DATA : integer; attribute C_USE_DEFAULT_DATA of U0 : label is 1; attribute C_USE_ECC : integer; attribute C_USE_ECC of U0 : label is 0; attribute C_USE_SOFTECC : integer; attribute C_USE_SOFTECC of U0 : label is 0; attribute C_USE_URAM : integer; attribute C_USE_URAM of U0 : label is 0; attribute C_WEA_WIDTH : integer; attribute C_WEA_WIDTH of U0 : label is 1; attribute C_WEB_WIDTH : integer; attribute C_WEB_WIDTH of U0 : label is 1; attribute C_WRITE_DEPTH_A : integer; attribute C_WRITE_DEPTH_A of U0 : label is 10240; attribute C_WRITE_DEPTH_B : integer; attribute C_WRITE_DEPTH_B of U0 : label is 10240; attribute C_WRITE_MODE_A : string; attribute C_WRITE_MODE_A of U0 : label is "READ_FIRST"; attribute C_WRITE_MODE_B : string; attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST"; attribute C_WRITE_WIDTH_A : integer; attribute C_WRITE_WIDTH_A of U0 : label is 8; attribute C_WRITE_WIDTH_B : integer; attribute C_WRITE_WIDTH_B of U0 : label is 8; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of U0 : label is "artix7"; attribute DONT_TOUCH : boolean; attribute DONT_TOUCH of U0 : label is std.standard.true; attribute downgradeipidentifiedwarnings of U0 : label is "yes"; begin U0: entity work.FrameBuffer_blk_mem_gen_v8_3_1 port map ( addra(13 downto 0) => addra(13 downto 0), addrb(13 downto 0) => addrb(13 downto 0), clka => clka, clkb => clkb, dbiterr => NLW_U0_dbiterr_UNCONNECTED, deepsleep => NLW_U0_deepsleep_UNCONNECTED, dina(7 downto 0) => dina(7 downto 0), dinb(7 downto 0) => NLW_U0_dinb_UNCONNECTED(7 downto 0), douta(7 downto 0) => NLW_U0_douta_UNCONNECTED(7 downto 0), doutb(7 downto 0) => doutb(7 downto 0), eccpipece => NLW_U0_eccpipece_UNCONNECTED, ena => NLW_U0_ena_UNCONNECTED, enb => NLW_U0_enb_UNCONNECTED, injectdbiterr => NLW_U0_injectdbiterr_UNCONNECTED, injectsbiterr => NLW_U0_injectsbiterr_UNCONNECTED, rdaddrecc(13 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(13 downto 0), regcea => NLW_U0_regcea_UNCONNECTED, regceb => NLW_U0_regceb_UNCONNECTED, rsta => NLW_U0_rsta_UNCONNECTED, rsta_busy => NLW_U0_rsta_busy_UNCONNECTED, rstb => NLW_U0_rstb_UNCONNECTED, rstb_busy => NLW_U0_rstb_busy_UNCONNECTED, s_aclk => NLW_U0_s_aclk_UNCONNECTED, s_aresetn => NLW_U0_s_aresetn_UNCONNECTED, s_axi_araddr(31 downto 0) => NLW_U0_s_axi_araddr_UNCONNECTED(31 downto 0), s_axi_arburst(1 downto 0) => NLW_U0_s_axi_arburst_UNCONNECTED(1 downto 0), s_axi_arid(3 downto 0) => NLW_U0_s_axi_arid_UNCONNECTED(3 downto 0), s_axi_arlen(7 downto 0) => NLW_U0_s_axi_arlen_UNCONNECTED(7 downto 0), s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED, s_axi_arsize(2 downto 0) => NLW_U0_s_axi_arsize_UNCONNECTED(2 downto 0), s_axi_arvalid => NLW_U0_s_axi_arvalid_UNCONNECTED, s_axi_awaddr(31 downto 0) => NLW_U0_s_axi_awaddr_UNCONNECTED(31 downto 0), s_axi_awburst(1 downto 0) => NLW_U0_s_axi_awburst_UNCONNECTED(1 downto 0), s_axi_awid(3 downto 0) => NLW_U0_s_axi_awid_UNCONNECTED(3 downto 0), s_axi_awlen(7 downto 0) => NLW_U0_s_axi_awlen_UNCONNECTED(7 downto 0), s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED, s_axi_awsize(2 downto 0) => NLW_U0_s_axi_awsize_UNCONNECTED(2 downto 0), s_axi_awvalid => NLW_U0_s_axi_awvalid_UNCONNECTED, s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0), s_axi_bready => NLW_U0_s_axi_bready_UNCONNECTED, s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0), s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED, s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED, s_axi_injectdbiterr => NLW_U0_s_axi_injectdbiterr_UNCONNECTED, s_axi_injectsbiterr => NLW_U0_s_axi_injectsbiterr_UNCONNECTED, s_axi_rdaddrecc(13 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(13 downto 0), s_axi_rdata(7 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(7 downto 0), s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0), s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED, s_axi_rready => NLW_U0_s_axi_rready_UNCONNECTED, s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0), s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED, s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED, s_axi_wdata(7 downto 0) => NLW_U0_s_axi_wdata_UNCONNECTED(7 downto 0), s_axi_wlast => NLW_U0_s_axi_wlast_UNCONNECTED, s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED, s_axi_wstrb(0) => NLW_U0_s_axi_wstrb_UNCONNECTED(0), s_axi_wvalid => NLW_U0_s_axi_wvalid_UNCONNECTED, sbiterr => NLW_U0_sbiterr_UNCONNECTED, shutdown => NLW_U0_shutdown_UNCONNECTED, sleep => NLW_U0_sleep_UNCONNECTED, wea(0) => wea(0), web(0) => NLW_U0_web_UNCONNECTED(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity top is port ( vgaRed : out STD_LOGIC_VECTOR ( 3 downto 0 ); vgaGreen : out STD_LOGIC_VECTOR ( 3 downto 0 ); vgaBlue : out STD_LOGIC_VECTOR ( 3 downto 0 ); Hsync : out STD_LOGIC; Vsync : out STD_LOGIC; led : out STD_LOGIC_VECTOR ( 15 downto 0 ); sw : in STD_LOGIC_VECTOR ( 15 downto 0 ); clk : in STD_LOGIC; btnC : in STD_LOGIC; btnU : in STD_LOGIC; btnL : in STD_LOGIC; btnR : in STD_LOGIC; btnD : in STD_LOGIC; PS2Clk : in STD_LOGIC; PS2Data : in STD_LOGIC; RsRx : inout STD_LOGIC; RsTx : inout STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of top : entity is true; attribute ECO_CHECKSUM : string; attribute ECO_CHECKSUM of top : entity is "d678d57b"; attribute POWER_OPT_BRAM_CDC : integer; attribute POWER_OPT_BRAM_CDC of top : entity is 0; attribute POWER_OPT_BRAM_SR_ADDR : integer; attribute POWER_OPT_BRAM_SR_ADDR of top : entity is 0; attribute POWER_OPT_LOOPED_NET_PERCENTAGE : integer; attribute POWER_OPT_LOOPED_NET_PERCENTAGE of top : entity is 0; end top; architecture STRUCTURE of top is signal Hsync_OBUF : STD_LOGIC; signal PS2Clk_IBUF : STD_LOGIC; signal PS2Data_IBUF : STD_LOGIC; signal Vsync_OBUF : STD_LOGIC; signal addra : STD_LOGIC_VECTOR ( 13 downto 0 ); signal btnC_IBUF : STD_LOGIC; signal btnD_IBUF : STD_LOGIC; signal btnL_IBUF : STD_LOGIC; signal btnR_IBUF : STD_LOGIC; signal btnU_IBUF : STD_LOGIC; signal clk108M : STD_LOGIC; signal clk10M : STD_LOGIC; signal clk_1_i_1_n_0 : STD_LOGIC; signal clk_1_i_2_n_0 : STD_LOGIC; signal clk_1_i_3_n_0 : STD_LOGIC; signal clk_1_i_4_n_0 : STD_LOGIC; signal clk_1_i_5_n_0 : STD_LOGIC; signal clk_1_reg_n_0 : STD_LOGIC; signal clk_BUFG : STD_LOGIC; signal clk_IBUF : STD_LOGIC; signal \counter[0]__0_i_1_n_0\ : STD_LOGIC; signal \counter[0]_i_1_n_0\ : STD_LOGIC; signal \counter[10]_i_1_n_0\ : STD_LOGIC; signal \counter[13]_i_2_n_0\ : STD_LOGIC; signal \counter[13]_i_3_n_0\ : STD_LOGIC; signal \counter[13]_i_4_n_0\ : STD_LOGIC; signal \counter[13]_i_6_n_0\ : STD_LOGIC; signal \counter[13]_i_7_n_0\ : STD_LOGIC; signal \counter[1]_i_1_n_0\ : STD_LOGIC; signal \counter[22]_i_10_n_0\ : STD_LOGIC; signal \counter[22]_i_11_n_0\ : STD_LOGIC; signal \counter[22]_i_12_n_0\ : STD_LOGIC; signal \counter[22]_i_13_n_0\ : STD_LOGIC; signal \counter[22]_i_14_n_0\ : STD_LOGIC; signal \counter[22]_i_15_n_0\ : STD_LOGIC; signal \counter[22]_i_16_n_0\ : STD_LOGIC; signal \counter[22]_i_17_n_0\ : STD_LOGIC; signal \counter[22]_i_18_n_0\ : STD_LOGIC; signal \counter[22]_i_19_n_0\ : STD_LOGIC; signal \counter[22]_i_1_n_0\ : STD_LOGIC; signal \counter[22]_i_20_n_0\ : STD_LOGIC; signal \counter[22]_i_21_n_0\ : STD_LOGIC; signal \counter[22]_i_22_n_0\ : STD_LOGIC; signal \counter[22]_i_7_n_0\ : STD_LOGIC; signal \counter[2]_i_1_n_0\ : STD_LOGIC; signal \counter[4]_i_1_n_0\ : STD_LOGIC; signal \counter[5]_i_1_n_0\ : STD_LOGIC; signal \counter[6]_i_1_n_0\ : STD_LOGIC; signal \counter[7]_i_1_n_0\ : STD_LOGIC; signal \counter[8]_i_1_n_0\ : STD_LOGIC; signal \counter[9]_i_1_n_0\ : STD_LOGIC; signal \counter_reg[0]__0_n_0\ : STD_LOGIC; signal \counter_reg[10]__0_n_0\ : STD_LOGIC; signal \counter_reg[11]__0_n_0\ : STD_LOGIC; signal \counter_reg[12]__0_i_1_n_0\ : STD_LOGIC; signal \counter_reg[12]__0_i_1_n_4\ : STD_LOGIC; signal \counter_reg[12]__0_i_1_n_5\ : STD_LOGIC; signal \counter_reg[12]__0_i_1_n_6\ : STD_LOGIC; signal \counter_reg[12]__0_i_1_n_7\ : STD_LOGIC; signal \counter_reg[12]__0_n_0\ : STD_LOGIC; signal \counter_reg[12]_i_2_n_0\ : STD_LOGIC; signal \counter_reg[12]_i_2_n_4\ : STD_LOGIC; signal \counter_reg[12]_i_2_n_5\ : STD_LOGIC; signal \counter_reg[12]_i_2_n_6\ : STD_LOGIC; signal \counter_reg[12]_i_2_n_7\ : STD_LOGIC; signal \counter_reg[13]__0_n_0\ : STD_LOGIC; signal \counter_reg[13]_i_5_n_7\ : STD_LOGIC; signal \counter_reg[16]_i_1_n_0\ : STD_LOGIC; signal \counter_reg[16]_i_1_n_4\ : STD_LOGIC; signal \counter_reg[16]_i_1_n_5\ : STD_LOGIC; signal \counter_reg[16]_i_1_n_6\ : STD_LOGIC; signal \counter_reg[16]_i_1_n_7\ : STD_LOGIC; signal \counter_reg[1]__0_n_0\ : STD_LOGIC; signal \counter_reg[20]_i_1_n_0\ : STD_LOGIC; signal \counter_reg[20]_i_1_n_4\ : STD_LOGIC; signal \counter_reg[20]_i_1_n_5\ : STD_LOGIC; signal \counter_reg[20]_i_1_n_6\ : STD_LOGIC; signal \counter_reg[20]_i_1_n_7\ : STD_LOGIC; signal \counter_reg[22]_i_2_n_6\ : STD_LOGIC; signal \counter_reg[22]_i_2_n_7\ : STD_LOGIC; signal \counter_reg[22]_i_3_n_3\ : STD_LOGIC; signal \counter_reg[22]_i_6_n_0\ : STD_LOGIC; signal \counter_reg[22]_i_9_n_0\ : STD_LOGIC; signal \counter_reg[2]__0_n_0\ : STD_LOGIC; signal \counter_reg[3]__0_n_0\ : STD_LOGIC; signal \counter_reg[3]_i_1_n_0\ : STD_LOGIC; signal \counter_reg[3]_i_1_n_4\ : STD_LOGIC; signal \counter_reg[3]_i_1_n_5\ : STD_LOGIC; signal \counter_reg[3]_i_1_n_6\ : STD_LOGIC; signal \counter_reg[3]_i_1_n_7\ : STD_LOGIC; signal \counter_reg[4]__0_i_1_n_0\ : STD_LOGIC; signal \counter_reg[4]__0_i_1_n_4\ : STD_LOGIC; signal \counter_reg[4]__0_i_1_n_5\ : STD_LOGIC; signal \counter_reg[4]__0_i_1_n_6\ : STD_LOGIC; signal \counter_reg[4]__0_i_1_n_7\ : STD_LOGIC; signal \counter_reg[4]__0_n_0\ : STD_LOGIC; signal \counter_reg[5]__0_n_0\ : STD_LOGIC; signal \counter_reg[6]__0_n_0\ : STD_LOGIC; signal \counter_reg[7]__0_n_0\ : STD_LOGIC; signal \counter_reg[8]__0_i_1_n_0\ : STD_LOGIC; signal \counter_reg[8]__0_i_1_n_4\ : STD_LOGIC; signal \counter_reg[8]__0_i_1_n_5\ : STD_LOGIC; signal \counter_reg[8]__0_i_1_n_6\ : STD_LOGIC; signal \counter_reg[8]__0_i_1_n_7\ : STD_LOGIC; signal \counter_reg[8]__0_n_0\ : STD_LOGIC; signal \counter_reg[8]_i_2_n_0\ : STD_LOGIC; signal \counter_reg[8]_i_2_n_4\ : STD_LOGIC; signal \counter_reg[8]_i_2_n_5\ : STD_LOGIC; signal \counter_reg[8]_i_2_n_6\ : STD_LOGIC; signal \counter_reg[8]_i_2_n_7\ : STD_LOGIC; signal \counter_reg[9]__0_n_0\ : STD_LOGIC; signal \counter_reg_n_0_[0]\ : STD_LOGIC; signal \counter_reg_n_0_[10]\ : STD_LOGIC; signal \counter_reg_n_0_[11]\ : STD_LOGIC; signal \counter_reg_n_0_[12]\ : STD_LOGIC; signal \counter_reg_n_0_[13]\ : STD_LOGIC; signal \counter_reg_n_0_[14]\ : STD_LOGIC; signal \counter_reg_n_0_[15]\ : STD_LOGIC; signal \counter_reg_n_0_[16]\ : STD_LOGIC; signal \counter_reg_n_0_[17]\ : STD_LOGIC; signal \counter_reg_n_0_[18]\ : STD_LOGIC; signal \counter_reg_n_0_[19]\ : STD_LOGIC; signal \counter_reg_n_0_[1]\ : STD_LOGIC; signal \counter_reg_n_0_[20]\ : STD_LOGIC; signal \counter_reg_n_0_[21]\ : STD_LOGIC; signal \counter_reg_n_0_[22]\ : STD_LOGIC; signal \counter_reg_n_0_[2]\ : STD_LOGIC; signal \counter_reg_n_0_[3]\ : STD_LOGIC; signal \counter_reg_n_0_[4]\ : STD_LOGIC; signal \counter_reg_n_0_[5]\ : STD_LOGIC; signal \counter_reg_n_0_[6]\ : STD_LOGIC; signal \counter_reg_n_0_[7]\ : STD_LOGIC; signal \counter_reg_n_0_[8]\ : STD_LOGIC; signal \counter_reg_n_0_[9]\ : STD_LOGIC; signal current_s : STD_LOGIC_VECTOR ( 1 downto 0 ); signal dina : STD_LOGIC_VECTOR ( 7 downto 0 ); signal doutb : STD_LOGIC_VECTOR ( 7 downto 0 ); signal fbOutAddr : STD_LOGIC_VECTOR ( 13 downto 0 ); signal fb_in_addr0 : STD_LOGIC_VECTOR ( 13 downto 0 ); signal \fb_in_addr[0]_i_1_n_0\ : STD_LOGIC; signal \fb_in_addr[10]_i_1_n_0\ : STD_LOGIC; signal \fb_in_addr[11]_i_1_n_0\ : STD_LOGIC; signal \fb_in_addr[11]_i_3_n_0\ : STD_LOGIC; signal \fb_in_addr[11]_i_4_n_0\ : STD_LOGIC; signal \fb_in_addr[11]_i_5_n_0\ : STD_LOGIC; signal \fb_in_addr[11]_i_6_n_0\ : STD_LOGIC; signal \fb_in_addr[11]_i_7_n_0\ : STD_LOGIC; signal \fb_in_addr[11]_i_8_n_0\ : STD_LOGIC; signal \fb_in_addr[11]_i_9_n_0\ : STD_LOGIC; signal \fb_in_addr[12]_i_1_n_0\ : STD_LOGIC; signal \fb_in_addr[13]_i_1_n_0\ : STD_LOGIC; signal \fb_in_addr[13]_i_3_n_0\ : STD_LOGIC; signal \fb_in_addr[13]_i_4_n_0\ : STD_LOGIC; signal \fb_in_addr[1]_i_1_n_0\ : STD_LOGIC; signal \fb_in_addr[2]_i_1_n_0\ : STD_LOGIC; signal \fb_in_addr[3]_i_1_n_0\ : STD_LOGIC; signal \fb_in_addr[3]_i_3_n_0\ : STD_LOGIC; signal \fb_in_addr[3]_i_4_n_0\ : STD_LOGIC; signal \fb_in_addr[3]_i_5_n_0\ : STD_LOGIC; signal \fb_in_addr[3]_i_6_n_0\ : STD_LOGIC; signal \fb_in_addr[3]_i_7_n_0\ : STD_LOGIC; signal \fb_in_addr[4]_i_1_n_0\ : STD_LOGIC; signal \fb_in_addr[5]_i_1_n_0\ : STD_LOGIC; signal \fb_in_addr[6]_i_1_n_0\ : STD_LOGIC; signal \fb_in_addr[7]_i_1_n_0\ : STD_LOGIC; signal \fb_in_addr[7]_i_3_n_0\ : STD_LOGIC; signal \fb_in_addr[7]_i_4_n_0\ : STD_LOGIC; signal \fb_in_addr[7]_i_5_n_0\ : STD_LOGIC; signal \fb_in_addr[7]_i_6_n_0\ : STD_LOGIC; signal \fb_in_addr[7]_i_7_n_0\ : STD_LOGIC; signal \fb_in_addr[7]_i_8_n_0\ : STD_LOGIC; signal \fb_in_addr[8]_i_1_n_0\ : STD_LOGIC; signal \fb_in_addr[9]_i_1_n_0\ : STD_LOGIC; signal \fb_in_addr_reg[11]_i_2_n_0\ : STD_LOGIC; signal \fb_in_addr_reg[3]_i_2_n_0\ : STD_LOGIC; signal \fb_in_addr_reg[7]_i_2_n_0\ : STD_LOGIC; signal fb_in_dat : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \g0_b0__0_n_0\ : STD_LOGIC; signal \g0_b1__0_n_0\ : STD_LOGIC; signal \g0_b2__0_n_0\ : STD_LOGIC; signal \g0_b3__0_n_0\ : STD_LOGIC; signal \g0_b4__0_n_0\ : STD_LOGIC; signal \g0_b5__0_n_0\ : STD_LOGIC; signal \g0_b6__0_i_1_n_0\ : STD_LOGIC; signal \g0_b6__0_i_2_n_0\ : STD_LOGIC; signal \g0_b6__0_i_3_n_0\ : STD_LOGIC; signal \g0_b6__0_i_4_n_0\ : STD_LOGIC; signal \g0_b6__0_i_5_n_0\ : STD_LOGIC; signal \g0_b6__0_i_6_n_0\ : STD_LOGIC; signal \g0_b6__0_i_7_n_0\ : STD_LOGIC; signal \g0_b6__0_n_0\ : STD_LOGIC; signal keyboard0_n_0 : STD_LOGIC; signal keyboard0_n_1 : STD_LOGIC; signal keyboard0_n_10 : STD_LOGIC; signal keyboard0_n_2 : STD_LOGIC; signal next_s : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \next_s[1]_i_2_n_0\ : STD_LOGIC; signal \sw[0]\ : STD_LOGIC; signal \sw[0]_IBUF\ : STD_LOGIC; signal \sw[10]\ : STD_LOGIC; signal \sw[10]_IBUF\ : STD_LOGIC; signal \sw[11]\ : STD_LOGIC; signal \sw[11]_IBUF\ : STD_LOGIC; signal \sw[12]\ : STD_LOGIC; signal \sw[12]_IBUF\ : STD_LOGIC; signal \sw[13]\ : STD_LOGIC; signal \sw[13]_IBUF\ : STD_LOGIC; signal \sw[14]\ : STD_LOGIC; signal \sw[14]_IBUF\ : STD_LOGIC; signal \sw[15]\ : STD_LOGIC; signal \sw[15]_IBUF\ : STD_LOGIC; signal \sw[1]\ : STD_LOGIC; signal \sw[1]_IBUF\ : STD_LOGIC; signal \sw[2]\ : STD_LOGIC; signal \sw[2]_IBUF\ : STD_LOGIC; signal \sw[3]\ : STD_LOGIC; signal \sw[3]_IBUF\ : STD_LOGIC; signal \sw[4]\ : STD_LOGIC; signal \sw[4]_IBUF\ : STD_LOGIC; signal \sw[5]\ : STD_LOGIC; signal \sw[5]_IBUF\ : STD_LOGIC; signal \sw[6]\ : STD_LOGIC; signal \sw[6]_IBUF\ : STD_LOGIC; signal \sw[7]\ : STD_LOGIC; signal \sw[7]_IBUF\ : STD_LOGIC; signal \sw[8]\ : STD_LOGIC; signal \sw[8]_IBUF\ : STD_LOGIC; signal \sw[9]\ : STD_LOGIC; signal \sw[9]_IBUF\ : STD_LOGIC; signal vgaBlue_OBUF : STD_LOGIC_VECTOR ( 0 to 0 ); signal \PS2Clk^Mid\ : STD_LOGIC; signal \PS2Data^Mid\ : STD_LOGIC; signal \NLW_counter_reg[12]__0_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_counter_reg[12]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_counter_reg[13]_i_5_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_counter_reg[13]_i_5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_counter_reg[16]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_counter_reg[20]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_counter_reg[22]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_counter_reg[22]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_counter_reg[22]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_counter_reg[22]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_counter_reg[22]_i_6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_counter_reg[22]_i_6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_counter_reg[22]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_counter_reg[22]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_counter_reg[3]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_counter_reg[4]__0_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_counter_reg[8]__0_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_counter_reg[8]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_fb_in_addr_reg[11]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_fb_in_addr_reg[13]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_fb_in_addr_reg[13]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_fb_in_addr_reg[3]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_fb_in_addr_reg[7]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); attribute OPT_INSERTED : boolean; attribute OPT_INSERTED of btnC_IBUF_inst : label is std.standard.true; attribute OPT_INSERTED of btnD_IBUF_inst : label is std.standard.true; attribute OPT_INSERTED of btnL_IBUF_inst : label is std.standard.true; attribute OPT_INSERTED of btnR_IBUF_inst : label is std.standard.true; attribute OPT_INSERTED of btnU_IBUF_inst : label is std.standard.true; attribute OPT_INSERTED of clk_IBUF_inst : label is std.standard.true; attribute syn_black_box : string; attribute syn_black_box of clock0 : label is "TRUE"; attribute syn_black_box of frameBuffer0 : label is "TRUE"; attribute x_core_info : string; attribute x_core_info of frameBuffer0 : label is "blk_mem_gen_v8_3_1,Vivado 2015.4"; attribute OPT_INSERTED of \sw[0]_IBUF_inst\ : label is std.standard.true; attribute OPT_INSERTED of \sw[10]_IBUF_inst\ : label is std.standard.true; attribute OPT_INSERTED of \sw[11]_IBUF_inst\ : label is std.standard.true; attribute OPT_INSERTED of \sw[12]_IBUF_inst\ : label is std.standard.true; attribute OPT_INSERTED of \sw[13]_IBUF_inst\ : label is std.standard.true; attribute OPT_INSERTED of \sw[14]_IBUF_inst\ : label is std.standard.true; attribute OPT_INSERTED of \sw[15]_IBUF_inst\ : label is std.standard.true; attribute OPT_INSERTED of \sw[1]_IBUF_inst\ : label is std.standard.true; attribute OPT_INSERTED of \sw[2]_IBUF_inst\ : label is std.standard.true; attribute OPT_INSERTED of \sw[3]_IBUF_inst\ : label is std.standard.true; attribute OPT_INSERTED of \sw[4]_IBUF_inst\ : label is std.standard.true; attribute OPT_INSERTED of \sw[5]_IBUF_inst\ : label is std.standard.true; attribute OPT_INSERTED of \sw[6]_IBUF_inst\ : label is std.standard.true; attribute OPT_INSERTED of \sw[7]_IBUF_inst\ : label is std.standard.true; attribute OPT_INSERTED of \sw[8]_IBUF_inst\ : label is std.standard.true; attribute OPT_INSERTED of \sw[9]_IBUF_inst\ : label is std.standard.true; begin \PS2Clk^Mid\ <= PS2Clk; \PS2Data^Mid\ <= PS2Data; \sw[0]\ <= sw(0); \sw[10]\ <= sw(10); \sw[11]\ <= sw(11); \sw[12]\ <= sw(12); \sw[13]\ <= sw(13); \sw[14]\ <= sw(14); \sw[15]\ <= sw(15); \sw[1]\ <= sw(1); \sw[2]\ <= sw(2); \sw[3]\ <= sw(3); \sw[4]\ <= sw(4); \sw[5]\ <= sw(5); \sw[6]\ <= sw(6); \sw[7]\ <= sw(7); \sw[8]\ <= sw(8); \sw[9]\ <= sw(9); \pullup_PS2Clk^Midinst\: unisim.vcomponents.PULLUP port map ( O => \PS2Clk^Mid\ ); \pullup_PS2Data^Midinst\: unisim.vcomponents.PULLUP port map ( O => \PS2Data^Mid\ ); led(0) <= 'Z'; led(1) <= 'Z'; led(2) <= 'Z'; led(3) <= 'Z'; led(4) <= 'Z'; led(5) <= 'Z'; led(6) <= 'Z'; led(7) <= 'Z'; led(8) <= 'Z'; led(9) <= 'Z'; led(10) <= 'Z'; led(11) <= 'Z'; led(12) <= 'Z'; led(13) <= 'Z'; led(14) <= 'Z'; led(15) <= 'Z'; Hsync_OBUF_inst: unisim.vcomponents.OBUF port map ( I => Hsync_OBUF, O => Hsync ); PS2Clk_IBUF_inst: unisim.vcomponents.IBUF port map ( I => \PS2Clk^Mid\, O => PS2Clk_IBUF ); PS2Data_IBUF_inst: unisim.vcomponents.IBUF port map ( I => \PS2Data^Mid\, O => PS2Data_IBUF ); Vsync_OBUF_inst: unisim.vcomponents.OBUF port map ( I => Vsync_OBUF, O => Vsync ); btnC_IBUF_inst: unisim.vcomponents.IBUF port map ( I => btnC, O => btnC_IBUF ); btnD_IBUF_inst: unisim.vcomponents.IBUF port map ( I => btnD, O => btnD_IBUF ); btnL_IBUF_inst: unisim.vcomponents.IBUF port map ( I => btnL, O => btnL_IBUF ); btnR_IBUF_inst: unisim.vcomponents.IBUF port map ( I => btnR, O => btnR_IBUF ); btnU_IBUF_inst: unisim.vcomponents.IBUF port map ( I => btnU, O => btnU_IBUF ); clk_1_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"2AAAAAAAD5555555" ) port map ( I0 => \counter_reg[22]_i_3_n_3\, I1 => clk_1_i_2_n_0, I2 => clk_1_i_3_n_0, I3 => clk_1_i_4_n_0, I4 => clk_1_i_5_n_0, I5 => clk_1_reg_n_0, O => clk_1_i_1_n_0 ); clk_1_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000001" ) port map ( I0 => \counter_reg[16]_i_1_n_6\, I1 => \counter_reg[16]_i_1_n_5\, I2 => \counter_reg[12]__0_i_1_n_4\, I3 => \counter_reg[16]_i_1_n_7\, I4 => \counter_reg[20]_i_1_n_7\, I5 => \counter_reg[16]_i_1_n_4\, O => clk_1_i_2_n_0 ); clk_1_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"0000000100000000" ) port map ( I0 => \counter_reg[20]_i_1_n_4\, I1 => \counter_reg[22]_i_2_n_7\, I2 => \counter_reg[20]_i_1_n_6\, I3 => \counter_reg[20]_i_1_n_5\, I4 => \counter_reg[22]_i_2_n_6\, I5 => \counter_reg[0]__0_n_0\, O => clk_1_i_3_n_0 ); clk_1_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000001" ) port map ( I0 => \counter_reg[8]__0_i_1_n_4\, I1 => \counter_reg[12]__0_i_1_n_7\, I2 => \counter_reg[8]__0_i_1_n_6\, I3 => \counter_reg[8]__0_i_1_n_5\, I4 => \counter_reg[12]__0_i_1_n_5\, I5 => \counter_reg[12]__0_i_1_n_6\, O => clk_1_i_4_n_0 ); clk_1_i_5: unisim.vcomponents.LUT5 generic map( INIT => X"00000001" ) port map ( I0 => \counter_reg[4]__0_i_1_n_7\, I1 => \counter_reg[4]__0_i_1_n_6\, I2 => \counter_reg[4]__0_i_1_n_5\, I3 => \counter_reg[8]__0_i_1_n_7\, I4 => \counter_reg[4]__0_i_1_n_4\, O => clk_1_i_5_n_0 ); clk_1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => clk_1_i_1_n_0, Q => clk_1_reg_n_0, R => '0' ); clk_BUFG_inst: unisim.vcomponents.BUFG port map ( I => clk_IBUF, O => clk_BUFG ); clk_IBUF_inst: unisim.vcomponents.IBUF port map ( I => clk, O => clk_IBUF ); clock0: entity work.ClockDivider port map ( clk108M => clk108M, clk10M => clk10M, clkIn => clk_BUFG ); \counter[0]__0_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \counter_reg[0]__0_n_0\, O => \counter[0]__0_i_1_n_0\ ); \counter[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \counter_reg_n_0_[0]\, O => \counter[0]_i_1_n_0\ ); \counter[10]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFF01FF0FFF01" ) port map ( I0 => \counter[13]_i_3_n_0\, I1 => current_s(1), I2 => \counter[13]_i_4_n_0\, I3 => \next_s[1]_i_2_n_0\, I4 => \counter_reg[12]_i_2_n_6\, I5 => \counter[13]_i_6_n_0\, O => \counter[10]_i_1_n_0\ ); \counter[13]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFF01FF0FFF01" ) port map ( I0 => \counter[13]_i_3_n_0\, I1 => current_s(1), I2 => \counter[13]_i_4_n_0\, I3 => \next_s[1]_i_2_n_0\, I4 => \counter_reg[13]_i_5_n_7\, I5 => \counter[13]_i_6_n_0\, O => \counter[13]_i_2_n_0\ ); \counter[13]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFFFE" ) port map ( I0 => \counter_reg_n_0_[4]\, I1 => \counter_reg_n_0_[2]\, I2 => \counter_reg_n_0_[1]\, I3 => \counter[13]_i_7_n_0\, I4 => \g0_b6__0_i_6_n_0\, O => \counter[13]_i_3_n_0\ ); \counter[13]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"4F" ) port map ( I0 => \counter[13]_i_3_n_0\, I1 => current_s(1), I2 => current_s(0), O => \counter[13]_i_4_n_0\ ); \counter[13]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"32" ) port map ( I0 => \g0_b6__0_i_1_n_0\, I1 => current_s(0), I2 => current_s(1), O => \counter[13]_i_6_n_0\ ); \counter[13]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"FFDF" ) port map ( I0 => \counter_reg_n_0_[13]\, I1 => \counter_reg_n_0_[0]\, I2 => \counter_reg_n_0_[11]\, I3 => \counter_reg_n_0_[3]\, O => \counter[13]_i_7_n_0\ ); \counter[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFF01FF0FFF01" ) port map ( I0 => \counter[13]_i_3_n_0\, I1 => current_s(1), I2 => \counter[13]_i_4_n_0\, I3 => \next_s[1]_i_2_n_0\, I4 => \counter_reg[3]_i_1_n_7\, I5 => \counter[13]_i_6_n_0\, O => \counter[1]_i_1_n_0\ ); \counter[22]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \counter_reg[22]_i_3_n_3\, O => \counter[22]_i_1_n_0\ ); \counter[22]_i_10\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => \counter_reg_n_0_[18]\, I1 => \counter_reg_n_0_[19]\, O => \counter[22]_i_10_n_0\ ); \counter[22]_i_11\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \counter_reg_n_0_[14]\, I1 => \counter_reg_n_0_[15]\, O => \counter[22]_i_11_n_0\ ); \counter[22]_i_12\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \counter_reg_n_0_[20]\, I1 => \counter_reg_n_0_[21]\, O => \counter[22]_i_12_n_0\ ); \counter[22]_i_13\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \counter_reg_n_0_[18]\, I1 => \counter_reg_n_0_[19]\, O => \counter[22]_i_13_n_0\ ); \counter[22]_i_14\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \counter_reg_n_0_[16]\, I1 => \counter_reg_n_0_[17]\, O => \counter[22]_i_14_n_0\ ); \counter[22]_i_15\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \counter_reg_n_0_[14]\, I1 => \counter_reg_n_0_[15]\, O => \counter[22]_i_15_n_0\ ); \counter[22]_i_16\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \counter_reg[11]__0_n_0\, O => \counter[22]_i_16_n_0\ ); \counter[22]_i_17\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => \counter_reg[8]__0_n_0\, I1 => \counter_reg[9]__0_n_0\, O => \counter[22]_i_17_n_0\ ); \counter[22]_i_18\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \counter_reg[6]__0_n_0\, I1 => \counter_reg[7]__0_n_0\, O => \counter[22]_i_18_n_0\ ); \counter[22]_i_19\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \counter_reg[12]__0_n_0\, I1 => \counter_reg[13]__0_n_0\, O => \counter[22]_i_19_n_0\ ); \counter[22]_i_20\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \counter_reg[11]__0_n_0\, I1 => \counter_reg[10]__0_n_0\, O => \counter[22]_i_20_n_0\ ); \counter[22]_i_21\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \counter_reg[8]__0_n_0\, I1 => \counter_reg[9]__0_n_0\, O => \counter[22]_i_21_n_0\ ); \counter[22]_i_22\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \counter_reg[6]__0_n_0\, I1 => \counter_reg[7]__0_n_0\, O => \counter[22]_i_22_n_0\ ); \counter[22]_i_7\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \counter_reg_n_0_[22]\, O => \counter[22]_i_7_n_0\ ); \counter[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFF01FF0FFF01" ) port map ( I0 => \counter[13]_i_3_n_0\, I1 => current_s(1), I2 => \counter[13]_i_4_n_0\, I3 => \next_s[1]_i_2_n_0\, I4 => \counter_reg[3]_i_1_n_6\, I5 => \counter[13]_i_6_n_0\, O => \counter[2]_i_1_n_0\ ); \counter[4]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFF01FF0FFF01" ) port map ( I0 => \counter[13]_i_3_n_0\, I1 => current_s(1), I2 => \counter[13]_i_4_n_0\, I3 => \next_s[1]_i_2_n_0\, I4 => \counter_reg[3]_i_1_n_4\, I5 => \counter[13]_i_6_n_0\, O => \counter[4]_i_1_n_0\ ); \counter[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFF01FF0FFF01" ) port map ( I0 => \counter[13]_i_3_n_0\, I1 => current_s(1), I2 => \counter[13]_i_4_n_0\, I3 => \next_s[1]_i_2_n_0\, I4 => \counter_reg[8]_i_2_n_7\, I5 => \counter[13]_i_6_n_0\, O => \counter[5]_i_1_n_0\ ); \counter[6]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFF01FF0FFF01" ) port map ( I0 => \counter[13]_i_3_n_0\, I1 => current_s(1), I2 => \counter[13]_i_4_n_0\, I3 => \next_s[1]_i_2_n_0\, I4 => \counter_reg[8]_i_2_n_6\, I5 => \counter[13]_i_6_n_0\, O => \counter[6]_i_1_n_0\ ); \counter[7]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFF01FF0FFF01" ) port map ( I0 => \counter[13]_i_3_n_0\, I1 => current_s(1), I2 => \counter[13]_i_4_n_0\, I3 => \next_s[1]_i_2_n_0\, I4 => \counter_reg[8]_i_2_n_5\, I5 => \counter[13]_i_6_n_0\, O => \counter[7]_i_1_n_0\ ); \counter[8]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFF01FF0FFF01" ) port map ( I0 => \counter[13]_i_3_n_0\, I1 => current_s(1), I2 => \counter[13]_i_4_n_0\, I3 => \next_s[1]_i_2_n_0\, I4 => \counter_reg[8]_i_2_n_4\, I5 => \counter[13]_i_6_n_0\, O => \counter[8]_i_1_n_0\ ); \counter[9]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFF01FF0FFF01" ) port map ( I0 => \counter[13]_i_3_n_0\, I1 => current_s(1), I2 => \counter[13]_i_4_n_0\, I3 => \next_s[1]_i_2_n_0\, I4 => \counter_reg[12]_i_2_n_7\, I5 => \counter[13]_i_6_n_0\, O => \counter[9]_i_1_n_0\ ); \counter_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \counter[0]_i_1_n_0\, Q => \counter_reg_n_0_[0]\, R => keyboard0_n_10 ); \counter_reg[0]__0\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter[0]__0_i_1_n_0\, Q => \counter_reg[0]__0_n_0\, R => \counter[22]_i_1_n_0\ ); \counter_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \counter[10]_i_1_n_0\, Q => \counter_reg_n_0_[10]\, R => '0' ); \counter_reg[10]__0\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[12]__0_i_1_n_6\, Q => \counter_reg[10]__0_n_0\, R => \counter[22]_i_1_n_0\ ); \counter_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \counter_reg[12]_i_2_n_5\, Q => \counter_reg_n_0_[11]\, R => keyboard0_n_10 ); \counter_reg[11]__0\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[12]__0_i_1_n_5\, Q => \counter_reg[11]__0_n_0\, R => \counter[22]_i_1_n_0\ ); \counter_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \counter_reg[12]_i_2_n_4\, Q => \counter_reg_n_0_[12]\, R => keyboard0_n_10 ); \counter_reg[12]__0\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[12]__0_i_1_n_4\, Q => \counter_reg[12]__0_n_0\, R => \counter[22]_i_1_n_0\ ); \counter_reg[12]__0_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \counter_reg[8]__0_i_1_n_0\, CO(3) => \counter_reg[12]__0_i_1_n_0\, CO(2 downto 0) => \NLW_counter_reg[12]__0_i_1_CO_UNCONNECTED\(2 downto 0), CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \counter_reg[12]__0_i_1_n_4\, O(2) => \counter_reg[12]__0_i_1_n_5\, O(1) => \counter_reg[12]__0_i_1_n_6\, O(0) => \counter_reg[12]__0_i_1_n_7\, S(3) => \counter_reg[12]__0_n_0\, S(2) => \counter_reg[11]__0_n_0\, S(1) => \counter_reg[10]__0_n_0\, S(0) => \counter_reg[9]__0_n_0\ ); \counter_reg[12]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => \counter_reg[8]_i_2_n_0\, CO(3) => \counter_reg[12]_i_2_n_0\, CO(2 downto 0) => \NLW_counter_reg[12]_i_2_CO_UNCONNECTED\(2 downto 0), CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \counter_reg[12]_i_2_n_4\, O(2) => \counter_reg[12]_i_2_n_5\, O(1) => \counter_reg[12]_i_2_n_6\, O(0) => \counter_reg[12]_i_2_n_7\, S(3) => \counter_reg_n_0_[12]\, S(2) => \counter_reg_n_0_[11]\, S(1) => \counter_reg_n_0_[10]\, S(0) => \counter_reg_n_0_[9]\ ); \counter_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \counter[13]_i_2_n_0\, Q => \counter_reg_n_0_[13]\, R => '0' ); \counter_reg[13]__0\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[16]_i_1_n_7\, Q => \counter_reg[13]__0_n_0\, R => \counter[22]_i_1_n_0\ ); \counter_reg[13]_i_5\: unisim.vcomponents.CARRY4 port map ( CI => \counter_reg[12]_i_2_n_0\, CO(3 downto 0) => \NLW_counter_reg[13]_i_5_CO_UNCONNECTED\(3 downto 0), CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 1) => \NLW_counter_reg[13]_i_5_O_UNCONNECTED\(3 downto 1), O(0) => \counter_reg[13]_i_5_n_7\, S(3 downto 1) => B"000", S(0) => \counter_reg_n_0_[13]\ ); \counter_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[16]_i_1_n_6\, Q => \counter_reg_n_0_[14]\, R => \counter[22]_i_1_n_0\ ); \counter_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[16]_i_1_n_5\, Q => \counter_reg_n_0_[15]\, R => \counter[22]_i_1_n_0\ ); \counter_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[16]_i_1_n_4\, Q => \counter_reg_n_0_[16]\, R => \counter[22]_i_1_n_0\ ); \counter_reg[16]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \counter_reg[12]__0_i_1_n_0\, CO(3) => \counter_reg[16]_i_1_n_0\, CO(2 downto 0) => \NLW_counter_reg[16]_i_1_CO_UNCONNECTED\(2 downto 0), CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \counter_reg[16]_i_1_n_4\, O(2) => \counter_reg[16]_i_1_n_5\, O(1) => \counter_reg[16]_i_1_n_6\, O(0) => \counter_reg[16]_i_1_n_7\, S(3) => \counter_reg_n_0_[16]\, S(2) => \counter_reg_n_0_[15]\, S(1) => \counter_reg_n_0_[14]\, S(0) => \counter_reg[13]__0_n_0\ ); \counter_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[20]_i_1_n_7\, Q => \counter_reg_n_0_[17]\, R => \counter[22]_i_1_n_0\ ); \counter_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[20]_i_1_n_6\, Q => \counter_reg_n_0_[18]\, R => \counter[22]_i_1_n_0\ ); \counter_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[20]_i_1_n_5\, Q => \counter_reg_n_0_[19]\, R => \counter[22]_i_1_n_0\ ); \counter_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \counter[1]_i_1_n_0\, Q => \counter_reg_n_0_[1]\, R => '0' ); \counter_reg[1]__0\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[4]__0_i_1_n_7\, Q => \counter_reg[1]__0_n_0\, R => \counter[22]_i_1_n_0\ ); \counter_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[20]_i_1_n_4\, Q => \counter_reg_n_0_[20]\, R => \counter[22]_i_1_n_0\ ); \counter_reg[20]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \counter_reg[16]_i_1_n_0\, CO(3) => \counter_reg[20]_i_1_n_0\, CO(2 downto 0) => \NLW_counter_reg[20]_i_1_CO_UNCONNECTED\(2 downto 0), CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \counter_reg[20]_i_1_n_4\, O(2) => \counter_reg[20]_i_1_n_5\, O(1) => \counter_reg[20]_i_1_n_6\, O(0) => \counter_reg[20]_i_1_n_7\, S(3) => \counter_reg_n_0_[20]\, S(2) => \counter_reg_n_0_[19]\, S(1) => \counter_reg_n_0_[18]\, S(0) => \counter_reg_n_0_[17]\ ); \counter_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[22]_i_2_n_7\, Q => \counter_reg_n_0_[21]\, R => \counter[22]_i_1_n_0\ ); \counter_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[22]_i_2_n_6\, Q => \counter_reg_n_0_[22]\, R => \counter[22]_i_1_n_0\ ); \counter_reg[22]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => \counter_reg[20]_i_1_n_0\, CO(3 downto 0) => \NLW_counter_reg[22]_i_2_CO_UNCONNECTED\(3 downto 0), CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 2) => \NLW_counter_reg[22]_i_2_O_UNCONNECTED\(3 downto 2), O(1) => \counter_reg[22]_i_2_n_6\, O(0) => \counter_reg[22]_i_2_n_7\, S(3 downto 2) => B"00", S(1) => \counter_reg_n_0_[22]\, S(0) => \counter_reg_n_0_[21]\ ); \counter_reg[22]_i_3\: unisim.vcomponents.CARRY4 port map ( CI => \counter_reg[22]_i_6_n_0\, CO(3 downto 1) => \NLW_counter_reg[22]_i_3_CO_UNCONNECTED\(3 downto 1), CO(0) => \counter_reg[22]_i_3_n_3\, CYINIT => '0', DI(3 downto 1) => B"000", DI(0) => \counter[22]_i_7_n_0\, O(3 downto 0) => \NLW_counter_reg[22]_i_3_O_UNCONNECTED\(3 downto 0), S(3 downto 1) => B"000", S(0) => \counter_reg_n_0_[22]\ ); \counter_reg[22]_i_6\: unisim.vcomponents.CARRY4 port map ( CI => \counter_reg[22]_i_9_n_0\, CO(3) => \counter_reg[22]_i_6_n_0\, CO(2 downto 0) => \NLW_counter_reg[22]_i_6_CO_UNCONNECTED\(2 downto 0), CYINIT => '0', DI(3) => '0', DI(2) => \counter[22]_i_10_n_0\, DI(1) => '0', DI(0) => \counter[22]_i_11_n_0\, O(3 downto 0) => \NLW_counter_reg[22]_i_6_O_UNCONNECTED\(3 downto 0), S(3) => \counter[22]_i_12_n_0\, S(2) => \counter[22]_i_13_n_0\, S(1) => \counter[22]_i_14_n_0\, S(0) => \counter[22]_i_15_n_0\ ); \counter_reg[22]_i_9\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \counter_reg[22]_i_9_n_0\, CO(2 downto 0) => \NLW_counter_reg[22]_i_9_CO_UNCONNECTED\(2 downto 0), CYINIT => '0', DI(3) => '0', DI(2) => \counter[22]_i_16_n_0\, DI(1) => \counter[22]_i_17_n_0\, DI(0) => \counter[22]_i_18_n_0\, O(3 downto 0) => \NLW_counter_reg[22]_i_9_O_UNCONNECTED\(3 downto 0), S(3) => \counter[22]_i_19_n_0\, S(2) => \counter[22]_i_20_n_0\, S(1) => \counter[22]_i_21_n_0\, S(0) => \counter[22]_i_22_n_0\ ); \counter_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \counter[2]_i_1_n_0\, Q => \counter_reg_n_0_[2]\, R => '0' ); \counter_reg[2]__0\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[4]__0_i_1_n_6\, Q => \counter_reg[2]__0_n_0\, R => \counter[22]_i_1_n_0\ ); \counter_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \counter_reg[3]_i_1_n_5\, Q => \counter_reg_n_0_[3]\, R => keyboard0_n_10 ); \counter_reg[3]__0\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[4]__0_i_1_n_5\, Q => \counter_reg[3]__0_n_0\, R => \counter[22]_i_1_n_0\ ); \counter_reg[3]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \counter_reg[3]_i_1_n_0\, CO(2 downto 0) => \NLW_counter_reg[3]_i_1_CO_UNCONNECTED\(2 downto 0), CYINIT => \counter_reg_n_0_[0]\, DI(3 downto 0) => B"0000", O(3) => \counter_reg[3]_i_1_n_4\, O(2) => \counter_reg[3]_i_1_n_5\, O(1) => \counter_reg[3]_i_1_n_6\, O(0) => \counter_reg[3]_i_1_n_7\, S(3) => \counter_reg_n_0_[4]\, S(2) => \counter_reg_n_0_[3]\, S(1) => \counter_reg_n_0_[2]\, S(0) => \counter_reg_n_0_[1]\ ); \counter_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \counter[4]_i_1_n_0\, Q => \counter_reg_n_0_[4]\, R => '0' ); \counter_reg[4]__0\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[4]__0_i_1_n_4\, Q => \counter_reg[4]__0_n_0\, R => \counter[22]_i_1_n_0\ ); \counter_reg[4]__0_i_1\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \counter_reg[4]__0_i_1_n_0\, CO(2 downto 0) => \NLW_counter_reg[4]__0_i_1_CO_UNCONNECTED\(2 downto 0), CYINIT => \counter_reg[0]__0_n_0\, DI(3 downto 0) => B"0000", O(3) => \counter_reg[4]__0_i_1_n_4\, O(2) => \counter_reg[4]__0_i_1_n_5\, O(1) => \counter_reg[4]__0_i_1_n_6\, O(0) => \counter_reg[4]__0_i_1_n_7\, S(3) => \counter_reg[4]__0_n_0\, S(2) => \counter_reg[3]__0_n_0\, S(1) => \counter_reg[2]__0_n_0\, S(0) => \counter_reg[1]__0_n_0\ ); \counter_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \counter[5]_i_1_n_0\, Q => \counter_reg_n_0_[5]\, R => '0' ); \counter_reg[5]__0\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[8]__0_i_1_n_7\, Q => \counter_reg[5]__0_n_0\, R => \counter[22]_i_1_n_0\ ); \counter_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \counter[6]_i_1_n_0\, Q => \counter_reg_n_0_[6]\, R => '0' ); \counter_reg[6]__0\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[8]__0_i_1_n_6\, Q => \counter_reg[6]__0_n_0\, R => \counter[22]_i_1_n_0\ ); \counter_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \counter[7]_i_1_n_0\, Q => \counter_reg_n_0_[7]\, R => '0' ); \counter_reg[7]__0\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[8]__0_i_1_n_5\, Q => \counter_reg[7]__0_n_0\, R => \counter[22]_i_1_n_0\ ); \counter_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \counter[8]_i_1_n_0\, Q => \counter_reg_n_0_[8]\, R => '0' ); \counter_reg[8]__0\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[8]__0_i_1_n_4\, Q => \counter_reg[8]__0_n_0\, R => \counter[22]_i_1_n_0\ ); \counter_reg[8]__0_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \counter_reg[4]__0_i_1_n_0\, CO(3) => \counter_reg[8]__0_i_1_n_0\, CO(2 downto 0) => \NLW_counter_reg[8]__0_i_1_CO_UNCONNECTED\(2 downto 0), CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \counter_reg[8]__0_i_1_n_4\, O(2) => \counter_reg[8]__0_i_1_n_5\, O(1) => \counter_reg[8]__0_i_1_n_6\, O(0) => \counter_reg[8]__0_i_1_n_7\, S(3) => \counter_reg[8]__0_n_0\, S(2) => \counter_reg[7]__0_n_0\, S(1) => \counter_reg[6]__0_n_0\, S(0) => \counter_reg[5]__0_n_0\ ); \counter_reg[8]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => \counter_reg[3]_i_1_n_0\, CO(3) => \counter_reg[8]_i_2_n_0\, CO(2 downto 0) => \NLW_counter_reg[8]_i_2_CO_UNCONNECTED\(2 downto 0), CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \counter_reg[8]_i_2_n_4\, O(2) => \counter_reg[8]_i_2_n_5\, O(1) => \counter_reg[8]_i_2_n_6\, O(0) => \counter_reg[8]_i_2_n_7\, S(3) => \counter_reg_n_0_[8]\, S(2) => \counter_reg_n_0_[7]\, S(1) => \counter_reg_n_0_[6]\, S(0) => \counter_reg_n_0_[5]\ ); \counter_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \counter[9]_i_1_n_0\, Q => \counter_reg_n_0_[9]\, R => '0' ); \counter_reg[9]__0\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[12]__0_i_1_n_7\, Q => \counter_reg[9]__0_n_0\, R => \counter[22]_i_1_n_0\ ); \current_s_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => '1', D => next_s(0), Q => current_s(0), R => '0' ); \current_s_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => '1', D => next_s(1), Q => current_s(1), R => '0' ); \fb_in_addr[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"11F100E0" ) port map ( I0 => current_s(1), I1 => current_s(0), I2 => \counter[13]_i_3_n_0\, I3 => \counter_reg_n_0_[0]\, I4 => fb_in_addr0(0), O => \fb_in_addr[0]_i_1_n_0\ ); \fb_in_addr[10]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"CCCA0FFA" ) port map ( I0 => fb_in_addr0(10), I1 => \counter_reg[12]_i_2_n_6\, I2 => current_s(0), I3 => current_s(1), I4 => \counter[13]_i_3_n_0\, O => \fb_in_addr[10]_i_1_n_0\ ); \fb_in_addr[11]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"F111E000" ) port map ( I0 => current_s(1), I1 => current_s(0), I2 => \counter[13]_i_3_n_0\, I3 => \counter_reg[12]_i_2_n_5\, I4 => fb_in_addr0(11), O => \fb_in_addr[11]_i_1_n_0\ ); \fb_in_addr[11]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \counter_reg[12]_i_2_n_5\, I1 => \g0_b6__0_i_1_n_0\, O => \fb_in_addr[11]_i_3_n_0\ ); \fb_in_addr[11]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \counter_reg[12]_i_2_n_6\, I1 => \g0_b6__0_i_1_n_0\, O => \fb_in_addr[11]_i_4_n_0\ ); \fb_in_addr[11]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \counter_reg[8]_i_2_n_4\, I1 => \g0_b6__0_i_1_n_0\, O => \fb_in_addr[11]_i_5_n_0\ ); \fb_in_addr[11]_i_6\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => \g0_b6__0_i_1_n_0\, I1 => \counter_reg[12]_i_2_n_5\, O => \fb_in_addr[11]_i_6_n_0\ ); \fb_in_addr[11]_i_7\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => \g0_b6__0_i_1_n_0\, I1 => \counter_reg[12]_i_2_n_6\, O => \fb_in_addr[11]_i_7_n_0\ ); \fb_in_addr[11]_i_8\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \counter_reg[12]_i_2_n_7\, I1 => \g0_b6__0_i_1_n_0\, O => \fb_in_addr[11]_i_8_n_0\ ); \fb_in_addr[11]_i_9\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => \g0_b6__0_i_1_n_0\, I1 => \counter_reg[8]_i_2_n_4\, O => \fb_in_addr[11]_i_9_n_0\ ); \fb_in_addr[12]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"F111E000" ) port map ( I0 => current_s(1), I1 => current_s(0), I2 => \counter[13]_i_3_n_0\, I3 => \counter_reg[12]_i_2_n_4\, I4 => fb_in_addr0(12), O => \fb_in_addr[12]_i_1_n_0\ ); \fb_in_addr[13]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"CCCA0FFA" ) port map ( I0 => fb_in_addr0(13), I1 => \counter_reg[13]_i_5_n_7\, I2 => current_s(0), I3 => current_s(1), I4 => \counter[13]_i_3_n_0\, O => \fb_in_addr[13]_i_1_n_0\ ); \fb_in_addr[13]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \counter_reg[13]_i_5_n_7\, I1 => \g0_b6__0_i_1_n_0\, O => \fb_in_addr[13]_i_3_n_0\ ); \fb_in_addr[13]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \counter_reg[12]_i_2_n_4\, I1 => \g0_b6__0_i_1_n_0\, O => \fb_in_addr[13]_i_4_n_0\ ); \fb_in_addr[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"CCCA0FFA" ) port map ( I0 => fb_in_addr0(1), I1 => \counter_reg[3]_i_1_n_7\, I2 => current_s(0), I3 => current_s(1), I4 => \counter[13]_i_3_n_0\, O => \fb_in_addr[1]_i_1_n_0\ ); \fb_in_addr[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"CCCA0FFA" ) port map ( I0 => fb_in_addr0(2), I1 => \counter_reg[3]_i_1_n_6\, I2 => current_s(0), I3 => current_s(1), I4 => \counter[13]_i_3_n_0\, O => \fb_in_addr[2]_i_1_n_0\ ); \fb_in_addr[3]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"F111E000" ) port map ( I0 => current_s(1), I1 => current_s(0), I2 => \counter[13]_i_3_n_0\, I3 => \counter_reg[3]_i_1_n_5\, I4 => fb_in_addr0(3), O => \fb_in_addr[3]_i_1_n_0\ ); \fb_in_addr[3]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \counter_reg[3]_i_1_n_7\, I1 => \g0_b6__0_i_1_n_0\, O => \fb_in_addr[3]_i_3_n_0\ ); \fb_in_addr[3]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \g0_b6__0_i_1_n_0\, I1 => \counter_reg[3]_i_1_n_5\, O => \fb_in_addr[3]_i_4_n_0\ ); \fb_in_addr[3]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \g0_b6__0_i_1_n_0\, I1 => \counter_reg[3]_i_1_n_6\, O => \fb_in_addr[3]_i_5_n_0\ ); \fb_in_addr[3]_i_6\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => \g0_b6__0_i_1_n_0\, I1 => \counter_reg[3]_i_1_n_7\, O => \fb_in_addr[3]_i_6_n_0\ ); \fb_in_addr[3]_i_7\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \g0_b6__0_i_1_n_0\, I1 => \counter_reg_n_0_[0]\, O => \fb_in_addr[3]_i_7_n_0\ ); \fb_in_addr[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"CCCA0FFA" ) port map ( I0 => fb_in_addr0(4), I1 => \counter_reg[3]_i_1_n_4\, I2 => current_s(0), I3 => current_s(1), I4 => \counter[13]_i_3_n_0\, O => \fb_in_addr[4]_i_1_n_0\ ); \fb_in_addr[5]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"CCCA0FFA" ) port map ( I0 => fb_in_addr0(5), I1 => \counter_reg[8]_i_2_n_7\, I2 => current_s(0), I3 => current_s(1), I4 => \counter[13]_i_3_n_0\, O => \fb_in_addr[5]_i_1_n_0\ ); \fb_in_addr[6]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"CCCA0FFA" ) port map ( I0 => fb_in_addr0(6), I1 => \counter_reg[8]_i_2_n_6\, I2 => current_s(0), I3 => current_s(1), I4 => \counter[13]_i_3_n_0\, O => \fb_in_addr[6]_i_1_n_0\ ); \fb_in_addr[7]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"CCCA0FFA" ) port map ( I0 => fb_in_addr0(7), I1 => \counter_reg[8]_i_2_n_5\, I2 => current_s(0), I3 => current_s(1), I4 => \counter[13]_i_3_n_0\, O => \fb_in_addr[7]_i_1_n_0\ ); \fb_in_addr[7]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \counter_reg[8]_i_2_n_6\, I1 => \g0_b6__0_i_1_n_0\, O => \fb_in_addr[7]_i_3_n_0\ ); \fb_in_addr[7]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \counter_reg[8]_i_2_n_7\, I1 => \g0_b6__0_i_1_n_0\, O => \fb_in_addr[7]_i_4_n_0\ ); \fb_in_addr[7]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \counter_reg[8]_i_2_n_5\, I1 => \g0_b6__0_i_1_n_0\, O => \fb_in_addr[7]_i_5_n_0\ ); \fb_in_addr[7]_i_6\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => \g0_b6__0_i_1_n_0\, I1 => \counter_reg[8]_i_2_n_6\, O => \fb_in_addr[7]_i_6_n_0\ ); \fb_in_addr[7]_i_7\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => \g0_b6__0_i_1_n_0\, I1 => \counter_reg[8]_i_2_n_7\, O => \fb_in_addr[7]_i_7_n_0\ ); \fb_in_addr[7]_i_8\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \counter_reg[3]_i_1_n_4\, I1 => \g0_b6__0_i_1_n_0\, O => \fb_in_addr[7]_i_8_n_0\ ); \fb_in_addr[8]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"CCCA0FFA" ) port map ( I0 => fb_in_addr0(8), I1 => \counter_reg[8]_i_2_n_4\, I2 => current_s(0), I3 => current_s(1), I4 => \counter[13]_i_3_n_0\, O => \fb_in_addr[8]_i_1_n_0\ ); \fb_in_addr[9]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"CCCA0FFA" ) port map ( I0 => fb_in_addr0(9), I1 => \counter_reg[12]_i_2_n_7\, I2 => current_s(0), I3 => current_s(1), I4 => \counter[13]_i_3_n_0\, O => \fb_in_addr[9]_i_1_n_0\ ); \fb_in_addr_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \fb_in_addr[0]_i_1_n_0\, Q => addra(0), R => '0' ); \fb_in_addr_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \fb_in_addr[10]_i_1_n_0\, Q => addra(10), R => '0' ); \fb_in_addr_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \fb_in_addr[11]_i_1_n_0\, Q => addra(11), R => '0' ); \fb_in_addr_reg[11]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => \fb_in_addr_reg[7]_i_2_n_0\, CO(3) => \fb_in_addr_reg[11]_i_2_n_0\, CO(2 downto 0) => \NLW_fb_in_addr_reg[11]_i_2_CO_UNCONNECTED\(2 downto 0), CYINIT => '0', DI(3) => \fb_in_addr[11]_i_3_n_0\, DI(2) => \fb_in_addr[11]_i_4_n_0\, DI(1) => '0', DI(0) => \fb_in_addr[11]_i_5_n_0\, O(3 downto 0) => fb_in_addr0(11 downto 8), S(3) => \fb_in_addr[11]_i_6_n_0\, S(2) => \fb_in_addr[11]_i_7_n_0\, S(1) => \fb_in_addr[11]_i_8_n_0\, S(0) => \fb_in_addr[11]_i_9_n_0\ ); \fb_in_addr_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \fb_in_addr[12]_i_1_n_0\, Q => addra(12), R => '0' ); \fb_in_addr_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \fb_in_addr[13]_i_1_n_0\, Q => addra(13), R => '0' ); \fb_in_addr_reg[13]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => \fb_in_addr_reg[11]_i_2_n_0\, CO(3 downto 0) => \NLW_fb_in_addr_reg[13]_i_2_CO_UNCONNECTED\(3 downto 0), CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 2) => \NLW_fb_in_addr_reg[13]_i_2_O_UNCONNECTED\(3 downto 2), O(1 downto 0) => fb_in_addr0(13 downto 12), S(3 downto 2) => B"00", S(1) => \fb_in_addr[13]_i_3_n_0\, S(0) => \fb_in_addr[13]_i_4_n_0\ ); \fb_in_addr_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \fb_in_addr[1]_i_1_n_0\, Q => addra(1), R => '0' ); \fb_in_addr_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \fb_in_addr[2]_i_1_n_0\, Q => addra(2), R => '0' ); \fb_in_addr_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \fb_in_addr[3]_i_1_n_0\, Q => addra(3), R => '0' ); \fb_in_addr_reg[3]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \fb_in_addr_reg[3]_i_2_n_0\, CO(2 downto 0) => \NLW_fb_in_addr_reg[3]_i_2_CO_UNCONNECTED\(2 downto 0), CYINIT => '0', DI(3 downto 2) => B"00", DI(1) => \fb_in_addr[3]_i_3_n_0\, DI(0) => '0', O(3 downto 0) => fb_in_addr0(3 downto 0), S(3) => \fb_in_addr[3]_i_4_n_0\, S(2) => \fb_in_addr[3]_i_5_n_0\, S(1) => \fb_in_addr[3]_i_6_n_0\, S(0) => \fb_in_addr[3]_i_7_n_0\ ); \fb_in_addr_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \fb_in_addr[4]_i_1_n_0\, Q => addra(4), R => '0' ); \fb_in_addr_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \fb_in_addr[5]_i_1_n_0\, Q => addra(5), R => '0' ); \fb_in_addr_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \fb_in_addr[6]_i_1_n_0\, Q => addra(6), R => '0' ); \fb_in_addr_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \fb_in_addr[7]_i_1_n_0\, Q => addra(7), R => '0' ); \fb_in_addr_reg[7]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => \fb_in_addr_reg[3]_i_2_n_0\, CO(3) => \fb_in_addr_reg[7]_i_2_n_0\, CO(2 downto 0) => \NLW_fb_in_addr_reg[7]_i_2_CO_UNCONNECTED\(2 downto 0), CYINIT => '0', DI(3) => '0', DI(2) => \fb_in_addr[7]_i_3_n_0\, DI(1) => \fb_in_addr[7]_i_4_n_0\, DI(0) => '0', O(3 downto 0) => fb_in_addr0(7 downto 4), S(3) => \fb_in_addr[7]_i_5_n_0\, S(2) => \fb_in_addr[7]_i_6_n_0\, S(1) => \fb_in_addr[7]_i_7_n_0\, S(0) => \fb_in_addr[7]_i_8_n_0\ ); \fb_in_addr_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \fb_in_addr[8]_i_1_n_0\, Q => addra(8), R => '0' ); \fb_in_addr_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \fb_in_addr[9]_i_1_n_0\, Q => addra(9), R => '0' ); \fb_in_dat[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => clk_1_reg_n_0, I1 => current_s(1), I2 => current_s(0), O => fb_in_dat(7) ); \fb_in_dat_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => fb_in_dat(0), Q => dina(0), R => '0' ); \fb_in_dat_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => fb_in_dat(1), Q => dina(1), R => '0' ); \fb_in_dat_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => fb_in_dat(2), Q => dina(2), R => '0' ); \fb_in_dat_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => fb_in_dat(3), Q => dina(3), R => '0' ); \fb_in_dat_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => fb_in_dat(4), Q => dina(4), R => '0' ); \fb_in_dat_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => fb_in_dat(5), Q => dina(5), R => '0' ); \fb_in_dat_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => fb_in_dat(6), Q => dina(6), R => '0' ); \fb_in_dat_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => fb_in_dat(7), Q => dina(7), R => '0' ); frameBuffer0: entity work.FrameBuffer port map ( addra(13 downto 0) => addra(13 downto 0), addrb(13 downto 0) => fbOutAddr(13 downto 0), clka => clk_BUFG, clkb => clk108M, dina(7 downto 0) => dina(7 downto 0), doutb(7 downto 0) => doutb(7 downto 0), wea(0) => '1' ); \g0_b0__0\: unisim.vcomponents.LUT6 generic map( INIT => X"000F40F40FBBBFB0" ) port map ( I0 => \counter_reg_n_0_[0]\, I1 => \g0_b6__0_i_1_n_0\, I2 => \g0_b6__0_i_2_n_0\, I3 => \g0_b6__0_i_3_n_0\, I4 => \g0_b6__0_i_4_n_0\, I5 => \g0_b6__0_i_5_n_0\, O => \g0_b0__0_n_0\ ); \g0_b1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"04F0B4F400B40F40" ) port map ( I0 => \counter_reg_n_0_[0]\, I1 => \g0_b6__0_i_1_n_0\, I2 => \g0_b6__0_i_2_n_0\, I3 => \g0_b6__0_i_3_n_0\, I4 => \g0_b6__0_i_4_n_0\, I5 => \g0_b6__0_i_5_n_0\, O => \g0_b1__0_n_0\ ); \g0_b2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"04FFBFB4B40400B0" ) port map ( I0 => \counter_reg_n_0_[0]\, I1 => \g0_b6__0_i_1_n_0\, I2 => \g0_b6__0_i_2_n_0\, I3 => \g0_b6__0_i_3_n_0\, I4 => \g0_b6__0_i_4_n_0\, I5 => \g0_b6__0_i_5_n_0\, O => \g0_b2__0_n_0\ ); \g0_b3__0\: unisim.vcomponents.LUT6 generic map( INIT => X"04F0F4B40BBF0000" ) port map ( I0 => \counter_reg_n_0_[0]\, I1 => \g0_b6__0_i_1_n_0\, I2 => \g0_b6__0_i_2_n_0\, I3 => \g0_b6__0_i_3_n_0\, I4 => \g0_b6__0_i_4_n_0\, I5 => \g0_b6__0_i_5_n_0\, O => \g0_b3__0_n_0\ ); \g0_b4__0\: unisim.vcomponents.LUT6 generic map( INIT => X"00040B00BB0B0F4B" ) port map ( I0 => \counter_reg_n_0_[0]\, I1 => \g0_b6__0_i_1_n_0\, I2 => \g0_b6__0_i_2_n_0\, I3 => \g0_b6__0_i_3_n_0\, I4 => \g0_b6__0_i_4_n_0\, I5 => \g0_b6__0_i_5_n_0\, O => \g0_b4__0_n_0\ ); \g0_b5__0\: unisim.vcomponents.LUT6 generic map( INIT => X"04FFFFFFFFFFFFF0" ) port map ( I0 => \counter_reg_n_0_[0]\, I1 => \g0_b6__0_i_1_n_0\, I2 => \g0_b6__0_i_2_n_0\, I3 => \g0_b6__0_i_3_n_0\, I4 => \g0_b6__0_i_4_n_0\, I5 => \g0_b6__0_i_5_n_0\, O => \g0_b5__0_n_0\ ); \g0_b6__0\: unisim.vcomponents.LUT6 generic map( INIT => X"000FFFF4BFBFBFFB" ) port map ( I0 => \counter_reg_n_0_[0]\, I1 => \g0_b6__0_i_1_n_0\, I2 => \g0_b6__0_i_2_n_0\, I3 => \g0_b6__0_i_3_n_0\, I4 => \g0_b6__0_i_4_n_0\, I5 => \g0_b6__0_i_5_n_0\, O => \g0_b6__0_n_0\ ); \g0_b6__0_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"000000000000007F" ) port map ( I0 => \counter_reg_n_0_[4]\, I1 => \counter_reg_n_0_[2]\, I2 => \counter_reg_n_0_[3]\, I3 => \counter_reg_n_0_[11]\, I4 => \counter_reg_n_0_[13]\, I5 => \g0_b6__0_i_6_n_0\, O => \g0_b6__0_i_1_n_0\ ); \g0_b6__0_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"84" ) port map ( I0 => \counter_reg_n_0_[0]\, I1 => \g0_b6__0_i_1_n_0\, I2 => \counter_reg[3]_i_1_n_7\, O => \g0_b6__0_i_2_n_0\ ); \g0_b6__0_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"D020" ) port map ( I0 => \counter_reg[3]_i_1_n_7\, I1 => \counter_reg_n_0_[0]\, I2 => \g0_b6__0_i_1_n_0\, I3 => \counter_reg[3]_i_1_n_6\, O => \g0_b6__0_i_3_n_0\ ); \g0_b6__0_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"A060A0A0" ) port map ( I0 => \counter_reg[3]_i_1_n_5\, I1 => \counter_reg[3]_i_1_n_6\, I2 => \g0_b6__0_i_1_n_0\, I3 => \counter_reg_n_0_[0]\, I4 => \counter_reg[3]_i_1_n_7\, O => \g0_b6__0_i_4_n_0\ ); \g0_b6__0_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"D0F0F0F020000000" ) port map ( I0 => \counter_reg[3]_i_1_n_7\, I1 => \counter_reg_n_0_[0]\, I2 => \g0_b6__0_i_1_n_0\, I3 => \counter_reg[3]_i_1_n_6\, I4 => \counter_reg[3]_i_1_n_5\, I5 => \counter_reg[3]_i_1_n_4\, O => \g0_b6__0_i_5_n_0\ ); \g0_b6__0_i_6\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => \g0_b6__0_i_7_n_0\, I1 => \counter_reg_n_0_[7]\, I2 => \counter_reg_n_0_[9]\, I3 => \counter_reg_n_0_[8]\, O => \g0_b6__0_i_6_n_0\ ); \g0_b6__0_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => \counter_reg_n_0_[6]\, I1 => \counter_reg_n_0_[5]\, I2 => \counter_reg_n_0_[10]\, I3 => \counter_reg_n_0_[12]\, O => \g0_b6__0_i_7_n_0\ ); keyboard0: entity work.ps2_keyboard_to_ascii port map ( D(1 downto 0) => next_s(1 downto 0), PS2Clk_IBUF => PS2Clk_IBUF, PS2Data_IBUF => PS2Data_IBUF, Q(1 downto 0) => current_s(1 downto 0), clk_BUFG => clk_BUFG, \counter_reg[0]\ => keyboard0_n_2, \counter_reg[0]_0\ => \g0_b0__0_n_0\, \counter_reg[0]_1\ => \g0_b1__0_n_0\, \counter_reg[0]_2\ => \g0_b2__0_n_0\, \counter_reg[0]_3\ => \g0_b3__0_n_0\, \counter_reg[0]_4\ => \g0_b4__0_n_0\, \counter_reg[0]_5\ => \g0_b5__0_n_0\, \counter_reg[0]_6\ => \g0_b6__0_n_0\, \counter_reg[12]\ => keyboard0_n_10, \counter_reg[4]\ => \g0_b6__0_i_1_n_0\, \counter_reg[4]_0\ => \counter[13]_i_3_n_0\, \current_s_reg[0]\ => \next_s[1]_i_2_n_0\, \fb_in_dat_reg[6]\(6 downto 0) => fb_in_dat(6 downto 0), \next_s_reg[0]\ => keyboard0_n_1, \next_s_reg[1]\ => keyboard0_n_0 ); \next_s[1]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"04" ) port map ( I0 => current_s(0), I1 => current_s(1), I2 => \counter[13]_i_3_n_0\, O => \next_s[1]_i_2_n_0\ ); \next_s_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => '1', D => keyboard0_n_1, Q => next_s(0), R => '0' ); \next_s_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => '1', D => keyboard0_n_0, Q => next_s(1), R => '0' ); \sw[0]_IBUF_inst\: unisim.vcomponents.IBUF port map ( I => \sw[0]\, O => \sw[0]_IBUF\ ); \sw[10]_IBUF_inst\: unisim.vcomponents.IBUF port map ( I => \sw[10]\, O => \sw[10]_IBUF\ ); \sw[11]_IBUF_inst\: unisim.vcomponents.IBUF port map ( I => \sw[11]\, O => \sw[11]_IBUF\ ); \sw[12]_IBUF_inst\: unisim.vcomponents.IBUF port map ( I => \sw[12]\, O => \sw[12]_IBUF\ ); \sw[13]_IBUF_inst\: unisim.vcomponents.IBUF port map ( I => \sw[13]\, O => \sw[13]_IBUF\ ); \sw[14]_IBUF_inst\: unisim.vcomponents.IBUF port map ( I => \sw[14]\, O => \sw[14]_IBUF\ ); \sw[15]_IBUF_inst\: unisim.vcomponents.IBUF port map ( I => \sw[15]\, O => \sw[15]_IBUF\ ); \sw[1]_IBUF_inst\: unisim.vcomponents.IBUF port map ( I => \sw[1]\, O => \sw[1]_IBUF\ ); \sw[2]_IBUF_inst\: unisim.vcomponents.IBUF port map ( I => \sw[2]\, O => \sw[2]_IBUF\ ); \sw[3]_IBUF_inst\: unisim.vcomponents.IBUF port map ( I => \sw[3]\, O => \sw[3]_IBUF\ ); \sw[4]_IBUF_inst\: unisim.vcomponents.IBUF port map ( I => \sw[4]\, O => \sw[4]_IBUF\ ); \sw[5]_IBUF_inst\: unisim.vcomponents.IBUF port map ( I => \sw[5]\, O => \sw[5]_IBUF\ ); \sw[6]_IBUF_inst\: unisim.vcomponents.IBUF port map ( I => \sw[6]\, O => \sw[6]_IBUF\ ); \sw[7]_IBUF_inst\: unisim.vcomponents.IBUF port map ( I => \sw[7]\, O => \sw[7]_IBUF\ ); \sw[8]_IBUF_inst\: unisim.vcomponents.IBUF port map ( I => \sw[8]\, O => \sw[8]_IBUF\ ); \sw[9]_IBUF_inst\: unisim.vcomponents.IBUF port map ( I => \sw[9]\, O => \sw[9]_IBUF\ ); vga0: entity work.Vga port map ( D(7 downto 0) => doutb(7 downto 0), Hsync_OBUF => Hsync_OBUF, Vsync_OBUF => Vsync_OBUF, addrb(13 downto 0) => fbOutAddr(13 downto 0), clk108M => clk108M, vgaBlue_OBUF(0) => vgaBlue_OBUF(0) ); \vgaBlue_OBUF[0]_inst\: unisim.vcomponents.OBUF port map ( I => vgaBlue_OBUF(0), O => vgaBlue(0) ); \vgaBlue_OBUF[1]_inst\: unisim.vcomponents.OBUF port map ( I => vgaBlue_OBUF(0), O => vgaBlue(1) ); \vgaBlue_OBUF[2]_inst\: unisim.vcomponents.OBUF port map ( I => vgaBlue_OBUF(0), O => vgaBlue(2) ); \vgaBlue_OBUF[3]_inst\: unisim.vcomponents.OBUF port map ( I => vgaBlue_OBUF(0), O => vgaBlue(3) ); \vgaGreen_OBUF[0]_inst\: unisim.vcomponents.OBUF port map ( I => vgaBlue_OBUF(0), O => vgaGreen(0) ); \vgaGreen_OBUF[1]_inst\: unisim.vcomponents.OBUF port map ( I => vgaBlue_OBUF(0), O => vgaGreen(1) ); \vgaGreen_OBUF[2]_inst\: unisim.vcomponents.OBUF port map ( I => vgaBlue_OBUF(0), O => vgaGreen(2) ); \vgaGreen_OBUF[3]_inst\: unisim.vcomponents.OBUF port map ( I => vgaBlue_OBUF(0), O => vgaGreen(3) ); \vgaRed_OBUF[0]_inst\: unisim.vcomponents.OBUF port map ( I => vgaBlue_OBUF(0), O => vgaRed(0) ); \vgaRed_OBUF[1]_inst\: unisim.vcomponents.OBUF port map ( I => vgaBlue_OBUF(0), O => vgaRed(1) ); \vgaRed_OBUF[2]_inst\: unisim.vcomponents.OBUF port map ( I => vgaBlue_OBUF(0), O => vgaRed(2) ); \vgaRed_OBUF[3]_inst\: unisim.vcomponents.OBUF port map ( I => vgaBlue_OBUF(0), O => vgaRed(3) ); end STRUCTURE;	mit
MarkBlanco/FPGA_Sandbox	RecComp/Lab3/led_controller/led_controller.cache/ip/2017.3/38a92fb39758d0fa/led_controller_design_rst_ps7_0_100M_0_sim_netlist.vhdl	1	35714	-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017 -- Date : Tue Oct 17 15:19:41 2017 -- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS -- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ led_controller_design_rst_ps7_0_100M_0_sim_netlist.vhdl -- Design : led_controller_design_rst_ps7_0_100M_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is port ( lpf_asr_reg : out STD_LOGIC; scndry_out : out STD_LOGIC; lpf_asr : in STD_LOGIC; asr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 ); p_1_in : in STD_LOGIC; p_2_in : in STD_LOGIC; aux_reset_in : in STD_LOGIC; slowest_sync_clk : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is signal asr_d1 : STD_LOGIC; signal s_level_out_d1_cdc_to : STD_LOGIC; signal s_level_out_d2 : STD_LOGIC; signal s_level_out_d3 : STD_LOGIC; signal \^scndry_out\ : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; attribute box_type : string; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; begin scndry_out <= \^scndry_out\; \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => asr_d1, Q => s_level_out_d1_cdc_to, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => aux_reset_in, O => asr_d1 ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d1_cdc_to, Q => s_level_out_d2, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d3, Q => \^scndry_out\, R => '0' ); lpf_asr_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"EAAAAAA8" ) port map ( I0 => lpf_asr, I1 => asr_lpf(0), I2 => \^scndry_out\, I3 => p_1_in, I4 => p_2_in, O => lpf_asr_reg ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 is port ( lpf_exr_reg : out STD_LOGIC; scndry_out : out STD_LOGIC; lpf_exr : in STD_LOGIC; p_3_out : in STD_LOGIC_VECTOR ( 2 downto 0 ); mb_debug_sys_rst : in STD_LOGIC; ext_reset_in : in STD_LOGIC; slowest_sync_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 : entity is "cdc_sync"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 is signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\ : STD_LOGIC; signal s_level_out_d1_cdc_to : STD_LOGIC; signal s_level_out_d2 : STD_LOGIC; signal s_level_out_d3 : STD_LOGIC; signal \^scndry_out\ : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; attribute box_type : string; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; begin scndry_out <= \^scndry_out\; \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\, Q => s_level_out_d1_cdc_to, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => mb_debug_sys_rst, I1 => ext_reset_in, O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\ ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d1_cdc_to, Q => s_level_out_d2, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d3, Q => \^scndry_out\, R => '0' ); lpf_exr_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"EAAAAAA8" ) port map ( I0 => lpf_exr, I1 => p_3_out(0), I2 => \^scndry_out\, I3 => p_3_out(1), I4 => p_3_out(2), O => lpf_exr_reg ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n is port ( Q : out STD_LOGIC_VECTOR ( 5 downto 0 ); seq_clr : in STD_LOGIC; seq_cnt_en : in STD_LOGIC; slowest_sync_clk : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n is signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 ); signal clear : STD_LOGIC; signal q_int0 : STD_LOGIC_VECTOR ( 5 downto 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \q_int[4]_i_1\ : label is "soft_lutpair0"; begin Q(5 downto 0) <= \^q\(5 downto 0); \q_int[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(0), O => q_int0(0) ); \q_int[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^q\(0), I1 => \^q\(1), O => q_int0(1) ); \q_int[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \^q\(0), I1 => \^q\(1), I2 => \^q\(2), O => q_int0(2) ); \q_int[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => \^q\(2), I3 => \^q\(3), O => q_int0(3) ); \q_int[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(2), I1 => \^q\(0), I2 => \^q\(1), I3 => \^q\(3), I4 => \^q\(4), O => q_int0(4) ); \q_int[5]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => seq_clr, O => clear ); \q_int[5]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \^q\(3), I1 => \^q\(1), I2 => \^q\(0), I3 => \^q\(2), I4 => \^q\(4), I5 => \^q\(5), O => q_int0(5) ); \q_int_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(0), Q => \^q\(0), R => clear ); \q_int_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(1), Q => \^q\(1), R => clear ); \q_int_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(2), Q => \^q\(2), R => clear ); \q_int_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(3), Q => \^q\(3), R => clear ); \q_int_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(4), Q => \^q\(4), R => clear ); \q_int_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(5), Q => \^q\(5), R => clear ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf is port ( lpf_int : out STD_LOGIC; slowest_sync_clk : in STD_LOGIC; dcm_locked : in STD_LOGIC; aux_reset_in : in STD_LOGIC; mb_debug_sys_rst : in STD_LOGIC; ext_reset_in : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf is signal \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\ : STD_LOGIC; signal \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\ : STD_LOGIC; signal Q : STD_LOGIC; signal asr_lpf : STD_LOGIC_VECTOR ( 0 to 0 ); signal lpf_asr : STD_LOGIC; signal lpf_exr : STD_LOGIC; signal \lpf_int0__0\ : STD_LOGIC; signal p_1_in : STD_LOGIC; signal p_2_in : STD_LOGIC; signal p_3_in1_in : STD_LOGIC; signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 ); attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of POR_SRL_I : label is "SRL16"; attribute box_type : string; attribute box_type of POR_SRL_I : label is "PRIMITIVE"; attribute srl_name : string; attribute srl_name of POR_SRL_I : label is "U0/\EXT_LPF/POR_SRL_I "; begin \ACTIVE_LOW_AUX.ACT_LO_AUX\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync port map ( asr_lpf(0) => asr_lpf(0), aux_reset_in => aux_reset_in, lpf_asr => lpf_asr, lpf_asr_reg => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\, p_1_in => p_1_in, p_2_in => p_2_in, scndry_out => p_3_in1_in, slowest_sync_clk => slowest_sync_clk ); \ACTIVE_LOW_EXT.ACT_LO_EXT\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 port map ( ext_reset_in => ext_reset_in, lpf_exr => lpf_exr, lpf_exr_reg => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\, mb_debug_sys_rst => mb_debug_sys_rst, p_3_out(2 downto 0) => p_3_out(2 downto 0), scndry_out => p_3_out(3), slowest_sync_clk => slowest_sync_clk ); \AUX_LPF[1].asr_lpf_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_in1_in, Q => p_2_in, R => '0' ); \AUX_LPF[2].asr_lpf_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_2_in, Q => p_1_in, R => '0' ); \AUX_LPF[3].asr_lpf_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_1_in, Q => asr_lpf(0), R => '0' ); \EXT_LPF[1].exr_lpf_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(3), Q => p_3_out(2), R => '0' ); \EXT_LPF[2].exr_lpf_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(2), Q => p_3_out(1), R => '0' ); \EXT_LPF[3].exr_lpf_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(1), Q => p_3_out(0), R => '0' ); POR_SRL_I: unisim.vcomponents.SRL16E generic map( INIT => X"FFFF" ) port map ( A0 => '1', A1 => '1', A2 => '1', A3 => '1', CE => '1', CLK => slowest_sync_clk, D => '0', Q => Q ); lpf_asr_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\, Q => lpf_asr, R => '0' ); lpf_exr_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\, Q => lpf_exr, R => '0' ); lpf_int0: unisim.vcomponents.LUT4 generic map( INIT => X"FFEF" ) port map ( I0 => Q, I1 => lpf_asr, I2 => dcm_locked, I3 => lpf_exr, O => \lpf_int0__0\ ); lpf_int_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \lpf_int0__0\, Q => lpf_int, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr is port ( MB_out : out STD_LOGIC; Bsr_out : out STD_LOGIC; Pr_out : out STD_LOGIC; \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : out STD_LOGIC; \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : out STD_LOGIC; lpf_int : in STD_LOGIC; slowest_sync_clk : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr is signal \^bsr_out\ : STD_LOGIC; signal Core_i_1_n_0 : STD_LOGIC; signal \^mb_out\ : STD_LOGIC; signal \^pr_out\ : STD_LOGIC; signal \bsr_dec_reg_n_0_[0]\ : STD_LOGIC; signal \bsr_dec_reg_n_0_[2]\ : STD_LOGIC; signal bsr_i_1_n_0 : STD_LOGIC; signal \core_dec[0]_i_1_n_0\ : STD_LOGIC; signal \core_dec[2]_i_1_n_0\ : STD_LOGIC; signal \core_dec_reg_n_0_[0]\ : STD_LOGIC; signal \core_dec_reg_n_0_[1]\ : STD_LOGIC; signal from_sys_i_1_n_0 : STD_LOGIC; signal p_0_in : STD_LOGIC; signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 ); signal p_5_out : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \pr_dec0__0\ : STD_LOGIC; signal \pr_dec_reg_n_0_[0]\ : STD_LOGIC; signal \pr_dec_reg_n_0_[2]\ : STD_LOGIC; signal pr_i_1_n_0 : STD_LOGIC; signal seq_clr : STD_LOGIC; signal seq_cnt : STD_LOGIC_VECTOR ( 5 downto 0 ); signal seq_cnt_en : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of Core_i_1 : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \bsr_dec[2]_i_1\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of bsr_i_1 : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \core_dec[0]_i_1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \core_dec[2]_i_1\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of from_sys_i_1 : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \pr_dec[0]_i_1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of pr_i_1 : label is "soft_lutpair4"; begin Bsr_out <= \^bsr_out\; MB_out <= \^mb_out\; Pr_out <= \^pr_out\; \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^bsr_out\, O => \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ ); \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^pr_out\, O => \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ ); Core_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^mb_out\, I1 => p_0_in, O => Core_i_1_n_0 ); Core_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => '1', D => Core_i_1_n_0, Q => \^mb_out\, S => lpf_int ); SEQ_COUNTER: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n port map ( Q(5 downto 0) => seq_cnt(5 downto 0), seq_clr => seq_clr, seq_cnt_en => seq_cnt_en, slowest_sync_clk => slowest_sync_clk ); \bsr_dec[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0804" ) port map ( I0 => seq_cnt_en, I1 => seq_cnt(3), I2 => seq_cnt(5), I3 => seq_cnt(4), O => p_5_out(0) ); \bsr_dec[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \core_dec_reg_n_0_[1]\, I1 => \bsr_dec_reg_n_0_[0]\, O => p_5_out(2) ); \bsr_dec_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_5_out(0), Q => \bsr_dec_reg_n_0_[0]\, R => '0' ); \bsr_dec_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_5_out(2), Q => \bsr_dec_reg_n_0_[2]\, R => '0' ); bsr_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^bsr_out\, I1 => \bsr_dec_reg_n_0_[2]\, O => bsr_i_1_n_0 ); bsr_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => '1', D => bsr_i_1_n_0, Q => \^bsr_out\, S => lpf_int ); \core_dec[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"8040" ) port map ( I0 => seq_cnt(4), I1 => seq_cnt(3), I2 => seq_cnt(5), I3 => seq_cnt_en, O => \core_dec[0]_i_1_n_0\ ); \core_dec[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \core_dec_reg_n_0_[1]\, I1 => \core_dec_reg_n_0_[0]\, O => \core_dec[2]_i_1_n_0\ ); \core_dec_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \core_dec[0]_i_1_n_0\, Q => \core_dec_reg_n_0_[0]\, R => '0' ); \core_dec_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \pr_dec0__0\, Q => \core_dec_reg_n_0_[1]\, R => '0' ); \core_dec_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \core_dec[2]_i_1_n_0\, Q => p_0_in, R => '0' ); from_sys_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^mb_out\, I1 => seq_cnt_en, O => from_sys_i_1_n_0 ); from_sys_reg: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => from_sys_i_1_n_0, Q => seq_cnt_en, S => lpf_int ); pr_dec0: unisim.vcomponents.LUT4 generic map( INIT => X"0210" ) port map ( I0 => seq_cnt(0), I1 => seq_cnt(1), I2 => seq_cnt(2), I3 => seq_cnt_en, O => \pr_dec0__0\ ); \pr_dec[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"1080" ) port map ( I0 => seq_cnt_en, I1 => seq_cnt(5), I2 => seq_cnt(3), I3 => seq_cnt(4), O => p_3_out(0) ); \pr_dec[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \core_dec_reg_n_0_[1]\, I1 => \pr_dec_reg_n_0_[0]\, O => p_3_out(2) ); \pr_dec_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(0), Q => \pr_dec_reg_n_0_[0]\, R => '0' ); \pr_dec_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(2), Q => \pr_dec_reg_n_0_[2]\, R => '0' ); pr_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^pr_out\, I1 => \pr_dec_reg_n_0_[2]\, O => pr_i_1_n_0 ); pr_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => '1', D => pr_i_1_n_0, Q => \^pr_out\, S => lpf_int ); seq_clr_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => '1', Q => seq_clr, R => lpf_int ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset is port ( slowest_sync_clk : in STD_LOGIC; ext_reset_in : in STD_LOGIC; aux_reset_in : in STD_LOGIC; mb_debug_sys_rst : in STD_LOGIC; dcm_locked : in STD_LOGIC; mb_reset : out STD_LOGIC; bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute C_AUX_RESET_HIGH : string; attribute C_AUX_RESET_HIGH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "1'b0"; attribute C_AUX_RST_WIDTH : integer; attribute C_AUX_RST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 4; attribute C_EXT_RESET_HIGH : string; attribute C_EXT_RESET_HIGH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "1'b0"; attribute C_EXT_RST_WIDTH : integer; attribute C_EXT_RST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 4; attribute C_FAMILY : string; attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "zynq"; attribute C_NUM_BUS_RST : integer; attribute C_NUM_BUS_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1; attribute C_NUM_INTERCONNECT_ARESETN : integer; attribute C_NUM_INTERCONNECT_ARESETN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1; attribute C_NUM_PERP_ARESETN : integer; attribute C_NUM_PERP_ARESETN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1; attribute C_NUM_PERP_RST : integer; attribute C_NUM_PERP_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset is signal Bsr_out : STD_LOGIC; signal MB_out : STD_LOGIC; signal Pr_out : STD_LOGIC; signal SEQ_n_3 : STD_LOGIC; signal SEQ_n_4 : STD_LOGIC; signal lpf_int : STD_LOGIC; attribute box_type : string; attribute box_type of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : label is "PRIMITIVE"; attribute box_type of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : label is "PRIMITIVE"; attribute box_type of \BSR_OUT_DFF[0].FDRE_BSR\ : label is "PRIMITIVE"; attribute box_type of FDRE_inst : label is "PRIMITIVE"; attribute box_type of \PR_OUT_DFF[0].FDRE_PER\ : label is "PRIMITIVE"; attribute equivalent_register_removal : string; attribute equivalent_register_removal of bus_struct_reset : signal is "no"; attribute equivalent_register_removal of interconnect_aresetn : signal is "no"; attribute equivalent_register_removal of peripheral_aresetn : signal is "no"; attribute equivalent_register_removal of peripheral_reset : signal is "no"; begin \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => SEQ_n_3, Q => interconnect_aresetn(0), R => '0' ); \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => SEQ_n_4, Q => peripheral_aresetn(0), R => '0' ); \BSR_OUT_DFF[0].FDRE_BSR\: unisim.vcomponents.FDRE generic map( INIT => '1', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => Bsr_out, Q => bus_struct_reset(0), R => '0' ); EXT_LPF: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf port map ( aux_reset_in => aux_reset_in, dcm_locked => dcm_locked, ext_reset_in => ext_reset_in, lpf_int => lpf_int, mb_debug_sys_rst => mb_debug_sys_rst, slowest_sync_clk => slowest_sync_clk ); FDRE_inst: unisim.vcomponents.FDRE generic map( INIT => '1', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => MB_out, Q => mb_reset, R => '0' ); \PR_OUT_DFF[0].FDRE_PER\: unisim.vcomponents.FDRE generic map( INIT => '1', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => Pr_out, Q => peripheral_reset(0), R => '0' ); SEQ: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr port map ( \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ => SEQ_n_3, \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ => SEQ_n_4, Bsr_out => Bsr_out, MB_out => MB_out, Pr_out => Pr_out, lpf_int => lpf_int, slowest_sync_clk => slowest_sync_clk ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is port ( slowest_sync_clk : in STD_LOGIC; ext_reset_in : in STD_LOGIC; aux_reset_in : in STD_LOGIC; mb_debug_sys_rst : in STD_LOGIC; dcm_locked : in STD_LOGIC; mb_reset : out STD_LOGIC; bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "led_controller_design_rst_ps7_0_100M_0,proc_sys_reset,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; attribute x_core_info : string; attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "proc_sys_reset,Vivado 2017.3"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is attribute C_AUX_RESET_HIGH : string; attribute C_AUX_RESET_HIGH of U0 : label is "1'b0"; attribute C_AUX_RST_WIDTH : integer; attribute C_AUX_RST_WIDTH of U0 : label is 4; attribute C_EXT_RESET_HIGH : string; attribute C_EXT_RESET_HIGH of U0 : label is "1'b0"; attribute C_EXT_RST_WIDTH : integer; attribute C_EXT_RST_WIDTH of U0 : label is 4; attribute C_FAMILY : string; attribute C_FAMILY of U0 : label is "zynq"; attribute C_NUM_BUS_RST : integer; attribute C_NUM_BUS_RST of U0 : label is 1; attribute C_NUM_INTERCONNECT_ARESETN : integer; attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1; attribute C_NUM_PERP_ARESETN : integer; attribute C_NUM_PERP_ARESETN of U0 : label is 1; attribute C_NUM_PERP_RST : integer; attribute C_NUM_PERP_RST of U0 : label is 1; attribute x_interface_info : string; attribute x_interface_info of aux_reset_in : signal is "xilinx.com:signal:reset:1.0 aux_reset RST"; attribute x_interface_parameter : string; attribute x_interface_parameter of aux_reset_in : signal is "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW"; attribute x_interface_info of ext_reset_in : signal is "xilinx.com:signal:reset:1.0 ext_reset RST"; attribute x_interface_parameter of ext_reset_in : signal is "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW"; attribute x_interface_info of mb_debug_sys_rst : signal is "xilinx.com:signal:reset:1.0 dbg_reset RST"; attribute x_interface_parameter of mb_debug_sys_rst : signal is "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH"; attribute x_interface_info of mb_reset : signal is "xilinx.com:signal:reset:1.0 mb_rst RST"; attribute x_interface_parameter of mb_reset : signal is "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR"; attribute x_interface_info of slowest_sync_clk : signal is "xilinx.com:signal:clock:1.0 clock CLK"; attribute x_interface_parameter of slowest_sync_clk : signal is "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN led_controller_design_processing_system7_0_0_FCLK_CLK0"; attribute x_interface_info of bus_struct_reset : signal is "xilinx.com:signal:reset:1.0 bus_struct_reset RST"; attribute x_interface_parameter of bus_struct_reset : signal is "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT"; attribute x_interface_info of interconnect_aresetn : signal is "xilinx.com:signal:reset:1.0 interconnect_low_rst RST"; attribute x_interface_parameter of interconnect_aresetn : signal is "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT"; attribute x_interface_info of peripheral_aresetn : signal is "xilinx.com:signal:reset:1.0 peripheral_low_rst RST"; attribute x_interface_parameter of peripheral_aresetn : signal is "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL"; attribute x_interface_info of peripheral_reset : signal is "xilinx.com:signal:reset:1.0 peripheral_high_rst RST"; attribute x_interface_parameter of peripheral_reset : signal is "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL"; begin U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset port map ( aux_reset_in => aux_reset_in, bus_struct_reset(0) => bus_struct_reset(0), dcm_locked => dcm_locked, ext_reset_in => ext_reset_in, interconnect_aresetn(0) => interconnect_aresetn(0), mb_debug_sys_rst => mb_debug_sys_rst, mb_reset => mb_reset, peripheral_aresetn(0) => peripheral_aresetn(0), peripheral_reset(0) => peripheral_reset(0), slowest_sync_clk => slowest_sync_clk ); end STRUCTURE;	mit
MarkBlanco/FPGA_Sandbox	RecComp/Lab3/ip_repo/zed_audio_ctrl/zed_audio_ctrl.srcs/sources_1/imports/i2s_audio/axi_lite_ipif.vhd	3	13994	------------------------------------------------------------------- -- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. -- -- -- -- This file contains confidential and proprietary information -- -- of Xilinx, Inc. and is protected under U.S. and -- -- international copyright and other intellectual property -- -- laws. -- -- -- -- DISCLAIMER -- -- This disclaimer is not a license and does not grant any -- -- rights to the materials distributed herewith. Except as -- -- otherwise provided in a valid license issued to you by -- -- Xilinx, and to the maximum extent permitted by applicable -- -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- -- (2) Xilinx shall not be liable (whether in contract or tort, -- -- including negligence, or under any other theory of -- -- liability) for any loss or damage of any kind or nature -- -- related to, arising under or in connection with these -- -- materials, including for any direct, or any indirect, -- -- special, incidental, or consequential loss or damage -- -- (including loss of data, profits, goodwill, or any type of -- -- loss or damage suffered as a result of any action brought -- -- by a third party) even if such damage or loss was -- -- reasonably foreseeable or Xilinx had been advised of the -- -- possibility of the same. -- -- -- -- CRITICAL APPLICATIONS -- -- Xilinx products are not designed or intended to be fail- -- -- safe, or for use in any application requiring fail-safe -- -- performance, such as life-support or safety devices or -- -- systems, Class III medical devices, nuclear facilities, -- -- applications related to the deployment of airbags, or any -- -- other applications that could lead to death, personal -- -- injury, or severe property or environmental damage -- -- (individually and collectively, "Critical -- -- Applications"). Customer assumes the sole risk and -- -- liability of any use of Xilinx products in Critical -- -- Applications, subject only to applicable laws and -- -- regulations governing limitations on product liability. -- -- -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- -- PART OF THIS FILE AT ALL TIMES. -- ------------------------------------------------------------------- -- ************************************************************************ -- ------------------------------------------------------------------------------- -- Filename: axi_lite_ipif.vhd -- Version: v1.01.a -- Description: This is the top level design file for the axi_lite_ipif -- function. It provides a standardized slave interface -- between the IP and the AXI. This version supports -- single read/write transfers only. It does not provide -- address pipelining or simultaneous read and write -- operations. ------------------------------------------------------------------------------- -- Structure: This section shows the hierarchical structure of axi_lite_ipif. -- -- --axi_lite_ipif.vhd -- --slave_attachment.vhd -- --address_decoder.vhd ------------------------------------------------------------------------------- -- Author: BSB -- -- History: -- -- BSB 05/20/10 -- First version -- ~~~~~~ -- - Created the first version v1.00.a -- ^^^^^^ -- ~~~~~~ -- SK 06/09/10 -- v1.01.a -- 1. updated to reduce the utilization -- Closed CR #574507 -- 2. Optimized the state machine code -- 3. Optimized the address decoder logic to generate the CE's with common logic -- 4. Address GAP decoding logic is removed and timeout counter is made active -- for all transactions. -- ^^^^^^ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_cmb" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; use work.common_types.all; ------------------------------------------------------------------------------- -- Definition of Generics ------------------------------------------------------------------------------- -- C_S_AXI_DATA_WIDTH -- AXI data bus width -- C_S_AXI_ADDR_WIDTH -- AXI address bus width -- C_S_AXI_MIN_SIZE -- Minimum address range of the IP -- C_USE_WSTRB -- Use write strobs or not -- C_DPHASE_TIMEOUT -- Data phase time out counter -- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range -- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range -- C_FAMILY -- Target FPGA family ------------------------------------------------------------------------------- -- Definition of Ports ------------------------------------------------------------------------------- -- S_AXI_ACLK -- AXI Clock -- S_AXI_ARESETN -- AXI Reset -- S_AXI_AWADDR -- AXI Write address -- S_AXI_AWVALID -- Write address valid -- S_AXI_AWREADY -- Write address ready -- S_AXI_WDATA -- Write data -- S_AXI_WSTRB -- Write strobes -- S_AXI_WVALID -- Write valid -- S_AXI_WREADY -- Write ready -- S_AXI_BRESP -- Write response -- S_AXI_BVALID -- Write response valid -- S_AXI_BREADY -- Response ready -- S_AXI_ARADDR -- Read address -- S_AXI_ARVALID -- Read address valid -- S_AXI_ARREADY -- Read address ready -- S_AXI_RDATA -- Read data -- S_AXI_RRESP -- Read response -- S_AXI_RVALID -- Read valid -- S_AXI_RREADY -- Read ready -- Bus2IP_Clk -- Synchronization clock provided to User IP -- Bus2IP_Reset -- Active high reset for use by the User IP -- Bus2IP_Addr -- Desired address of read or write operation -- Bus2IP_RNW -- Read or write indicator for the transaction -- Bus2IP_BE -- Byte enables for the data bus -- Bus2IP_CS -- Chip select for the transcations -- Bus2IP_RdCE -- Chip enables for the read -- Bus2IP_WrCE -- Chip enables for the write -- Bus2IP_Data -- Write data bus to the User IP -- IP2Bus_Data -- Input Read Data bus from the User IP -- IP2Bus_WrAck -- Active high Write Data qualifier from the IP -- IP2Bus_RdAck -- Active high Read Data qualifier from the IP -- IP2Bus_Error -- Error signal from the IP ------------------------------------------------------------------------------- entity axi_lite_ipif is generic ( C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32; C_S_AXI_ADDR_WIDTH : integer := 32; C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF"; C_USE_WSTRB : integer := 0; C_DPHASE_TIMEOUT : integer range 0 to 512 := 8; C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := -- not used ( X"0000_0000_7000_0000", -- IP user0 base address X"0000_0000_7000_00FF", -- IP user0 high address X"0000_0000_7000_0100", -- IP user1 base address X"0000_0000_7000_01FF" -- IP user1 high address ); C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := -- not used ( 4, -- User0 CE Number 12 -- User1 CE Number ); C_FAMILY : string := "virtex6" ); port ( --System signals S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; S_AXI_AWADDR : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_AWREADY : out std_logic; S_AXI_WDATA : in std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_WSTRB : in std_logic_vector ((C_S_AXI_DATA_WIDTH/8)-1 downto 0); S_AXI_WVALID : in std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_RREADY : in std_logic; -- Controls to the IP/IPIF modules Bus2IP_Clk : out std_logic; Bus2IP_Resetn : out std_logic; Bus2IP_Addr : out std_logic_vector ((C_S_AXI_ADDR_WIDTH-1) downto 0); Bus2IP_RNW : out std_logic; Bus2IP_BE : out std_logic_vector (((C_S_AXI_DATA_WIDTH/8)-1) downto 0); Bus2IP_CS : out std_logic_vector (((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1) downto 0); Bus2IP_RdCE : out std_logic_vector ((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0); Bus2IP_WrCE : out std_logic_vector ((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0); Bus2IP_Data : out std_logic_vector ((C_S_AXI_DATA_WIDTH-1) downto 0); IP2Bus_Data : in std_logic_vector ((C_S_AXI_DATA_WIDTH-1) downto 0); IP2Bus_WrAck : in std_logic; IP2Bus_RdAck : in std_logic; IP2Bus_Error : in std_logic ); end axi_lite_ipif; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture imp of axi_lite_ipif is ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin ------------------------------------------------------------------------------- -- Slave Attachment ------------------------------------------------------------------------------- I_SLAVE_ATTACHMENT: entity work.slave_attachment generic map( C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY, C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY, C_IPIF_ABUS_WIDTH => C_S_AXI_ADDR_WIDTH, C_IPIF_DBUS_WIDTH => C_S_AXI_DATA_WIDTH, C_USE_WSTRB => C_USE_WSTRB, C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT, C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE, C_FAMILY => C_FAMILY ) port map( -- AXI signals S_AXI_ACLK => S_AXI_ACLK, S_AXI_ARESETN => S_AXI_ARESETN, S_AXI_AWADDR => S_AXI_AWADDR, S_AXI_AWVALID => S_AXI_AWVALID, S_AXI_AWREADY => S_AXI_AWREADY, S_AXI_WDATA => S_AXI_WDATA, S_AXI_WSTRB => S_AXI_WSTRB, S_AXI_WVALID => S_AXI_WVALID, S_AXI_WREADY => S_AXI_WREADY, S_AXI_BRESP => S_AXI_BRESP, S_AXI_BVALID => S_AXI_BVALID, S_AXI_BREADY => S_AXI_BREADY, S_AXI_ARADDR => S_AXI_ARADDR, S_AXI_ARVALID => S_AXI_ARVALID, S_AXI_ARREADY => S_AXI_ARREADY, S_AXI_RDATA => S_AXI_RDATA, S_AXI_RRESP => S_AXI_RRESP, S_AXI_RVALID => S_AXI_RVALID, S_AXI_RREADY => S_AXI_RREADY, -- IPIC signals Bus2IP_Clk => Bus2IP_Clk, Bus2IP_Resetn => Bus2IP_Resetn, Bus2IP_Addr => Bus2IP_Addr, Bus2IP_RNW => Bus2IP_RNW, Bus2IP_BE => Bus2IP_BE, Bus2IP_CS => Bus2IP_CS, Bus2IP_RdCE => Bus2IP_RdCE, Bus2IP_WrCE => Bus2IP_WrCE, Bus2IP_Data => Bus2IP_Data, IP2Bus_Data => IP2Bus_Data, IP2Bus_WrAck => IP2Bus_WrAck, IP2Bus_RdAck => IP2Bus_RdAck, IP2Bus_Error => IP2Bus_Error ); end imp;	mit
MarkBlanco/FPGA_Sandbox	RecComp/Lab3/lab3_project.xpr/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_bram_ctrl_0_2/synth/design_1_axi_bram_ctrl_0_2.vhd	1	17300	-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:axi_bram_ctrl:4.0 -- IP Revision: 12 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY axi_bram_ctrl_v4_0_12; USE axi_bram_ctrl_v4_0_12.axi_bram_ctrl; ENTITY design_1_axi_bram_ctrl_0_2 IS PORT ( s_axi_aclk : IN STD_LOGIC; s_axi_aresetn : IN STD_LOGIC; s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awlock : IN STD_LOGIC; s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arlock : IN STD_LOGIC; s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; bram_rst_a : OUT STD_LOGIC; bram_clk_a : OUT STD_LOGIC; bram_en_a : OUT STD_LOGIC; bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); bram_addr_a : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0) ); END design_1_axi_bram_ctrl_0_2; ARCHITECTURE design_1_axi_bram_ctrl_0_2_arch OF design_1_axi_bram_ctrl_0_2 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_bram_ctrl_0_2_arch: ARCHITECTURE IS "yes"; COMPONENT axi_bram_ctrl IS GENERIC ( C_BRAM_INST_MODE : STRING; C_MEMORY_DEPTH : INTEGER; C_BRAM_ADDR_WIDTH : INTEGER; C_S_AXI_ADDR_WIDTH : INTEGER; C_S_AXI_DATA_WIDTH : INTEGER; C_S_AXI_ID_WIDTH : INTEGER; C_S_AXI_PROTOCOL : STRING; C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER; C_SINGLE_PORT_BRAM : INTEGER; C_FAMILY : STRING; C_SELECT_XPM : INTEGER; C_S_AXI_CTRL_ADDR_WIDTH : INTEGER; C_S_AXI_CTRL_DATA_WIDTH : INTEGER; C_ECC : INTEGER; C_ECC_TYPE : INTEGER; C_FAULT_INJECT : INTEGER; C_ECC_ONOFF_RESET_VALUE : INTEGER ); PORT ( s_axi_aclk : IN STD_LOGIC; s_axi_aresetn : IN STD_LOGIC; ecc_interrupt : OUT STD_LOGIC; ecc_ue : OUT STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awlock : IN STD_LOGIC; s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arlock : IN STD_LOGIC; s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; s_axi_ctrl_awvalid : IN STD_LOGIC; s_axi_ctrl_awready : OUT STD_LOGIC; s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_ctrl_wvalid : IN STD_LOGIC; s_axi_ctrl_wready : OUT STD_LOGIC; s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_ctrl_bvalid : OUT STD_LOGIC; s_axi_ctrl_bready : IN STD_LOGIC; s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_ctrl_arvalid : IN STD_LOGIC; s_axi_ctrl_arready : OUT STD_LOGIC; s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_ctrl_rvalid : OUT STD_LOGIC; s_axi_ctrl_rready : IN STD_LOGIC; bram_rst_a : OUT STD_LOGIC; bram_clk_a : OUT STD_LOGIC; bram_en_a : OUT STD_LOGIC; bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); bram_addr_a : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0); bram_rst_b : OUT STD_LOGIC; bram_clk_b : OUT STD_LOGIC; bram_en_b : OUT STD_LOGIC; bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); bram_addr_b : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT axi_bram_ctrl; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF design_1_axi_bram_ctrl_0_2_arch: ARCHITECTURE IS "axi_bram_ctrl,Vivado 2017.3"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_bram_ctrl_0_2_arch : ARCHITECTURE IS "design_1_axi_bram_ctrl_0_2,axi_bram_ctrl,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_bram_ctrl_0_2_arch: ARCHITECTURE IS "design_1_axi_bram_ctrl_0_2,axi_bram_ctrl,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_bram_ctrl,x_ipVersion=4.0,x_ipCoreRevision=12,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_BRAM_INST_MODE=EXTERNAL,C_MEMORY_DEPTH=2048,C_BRAM_ADDR_WIDTH=11,C_S_AXI_ADDR_WIDTH=13,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ID_WIDTH=1,C_S_AXI_PROTOCOL=AXI4,C_S_AXI_SUPPORTS_NARROW_BURST=0,C_SINGLE_PORT_BRAM=1,C_FAMILY=zynq,C_SELECT_XPM=0,C_S_AXI_CTRL_ADDR_WIDTH=32,C_S_AXI_CTRL_DATA_WIDTH=32,C_ECC" & "=0,C_ECC_TYPE=0,C_FAULT_INJECT=0,C_ECC_ONOFF_RESET_VALUE=0}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_PARAMETER : STRING; ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT"; ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN"; ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR"; ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE"; ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN"; ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK"; ATTRIBUTE X_INTERFACE_PARAMETER OF bram_rst_a: SIGNAL IS "XIL_INTERFACENAME BRAM_PORTA, MASTER_TYPE BRAM_CTRL, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, READ_WRITE_MODE READ_WRITE"; ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN"; ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 13, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR"; ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST"; ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME CLKIF, ASSOCIATED_BUSIF S_AXI:S_AXI_CTRL, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK"; BEGIN U0 : axi_bram_ctrl GENERIC MAP ( C_BRAM_INST_MODE => "EXTERNAL", C_MEMORY_DEPTH => 2048, C_BRAM_ADDR_WIDTH => 11, C_S_AXI_ADDR_WIDTH => 13, C_S_AXI_DATA_WIDTH => 32, C_S_AXI_ID_WIDTH => 1, C_S_AXI_PROTOCOL => "AXI4", C_S_AXI_SUPPORTS_NARROW_BURST => 0, C_SINGLE_PORT_BRAM => 1, C_FAMILY => "zynq", C_SELECT_XPM => 0, C_S_AXI_CTRL_ADDR_WIDTH => 32, C_S_AXI_CTRL_DATA_WIDTH => 32, C_ECC => 0, C_ECC_TYPE => 0, C_FAULT_INJECT => 0, C_ECC_ONOFF_RESET_VALUE => 0 ) PORT MAP ( s_axi_aclk => s_axi_aclk, s_axi_aresetn => s_axi_aresetn, s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awaddr => s_axi_awaddr, s_axi_awlen => s_axi_awlen, s_axi_awsize => s_axi_awsize, s_axi_awburst => s_axi_awburst, s_axi_awlock => s_axi_awlock, s_axi_awcache => s_axi_awcache, s_axi_awprot => s_axi_awprot, s_axi_awvalid => s_axi_awvalid, s_axi_awready => s_axi_awready, s_axi_wdata => s_axi_wdata, s_axi_wstrb => s_axi_wstrb, s_axi_wlast => s_axi_wlast, s_axi_wvalid => s_axi_wvalid, s_axi_wready => s_axi_wready, s_axi_bresp => s_axi_bresp, s_axi_bvalid => s_axi_bvalid, s_axi_bready => s_axi_bready, s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_araddr => s_axi_araddr, s_axi_arlen => s_axi_arlen, s_axi_arsize => s_axi_arsize, s_axi_arburst => s_axi_arburst, s_axi_arlock => s_axi_arlock, s_axi_arcache => s_axi_arcache, s_axi_arprot => s_axi_arprot, s_axi_arvalid => s_axi_arvalid, s_axi_arready => s_axi_arready, s_axi_rdata => s_axi_rdata, s_axi_rresp => s_axi_rresp, s_axi_rlast => s_axi_rlast, s_axi_rvalid => s_axi_rvalid, s_axi_rready => s_axi_rready, s_axi_ctrl_awvalid => '0', s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_ctrl_wvalid => '0', s_axi_ctrl_bready => '0', s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_ctrl_arvalid => '0', s_axi_ctrl_rready => '0', bram_rst_a => bram_rst_a, bram_clk_a => bram_clk_a, bram_en_a => bram_en_a, bram_we_a => bram_we_a, bram_addr_a => bram_addr_a, bram_wrdata_a => bram_wrdata_a, bram_rddata_a => bram_rddata_a, bram_rddata_b => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)) ); END design_1_axi_bram_ctrl_0_2_arch;	mit
MarkBlanco/FPGA_Sandbox	RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_processing_system7_0_0/ip_design_processing_system7_0_0_stub.vhdl	1	5959	-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017 -- Date : Wed Oct 18 15:15:21 2017 -- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS -- Command : write_vhdl -force -mode synth_stub -- /home/mark/Documents/Repos/FPGA_Sandbox/RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_processing_system7_0_0/ip_design_processing_system7_0_0_stub.vhdl -- Design : ip_design_processing_system7_0_0 -- Purpose : Stub declaration of top-level module interface -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity ip_design_processing_system7_0_0 is Port ( I2C0_SDA_I : in STD_LOGIC; I2C0_SDA_O : out STD_LOGIC; I2C0_SDA_T : out STD_LOGIC; I2C0_SCL_I : in STD_LOGIC; I2C0_SCL_O : out STD_LOGIC; I2C0_SCL_T : out STD_LOGIC; TTC0_WAVE0_OUT : out STD_LOGIC; TTC0_WAVE1_OUT : out STD_LOGIC; TTC0_WAVE2_OUT : out STD_LOGIC; USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); USB0_VBUS_PWRSELECT : out STD_LOGIC; USB0_VBUS_PWRFAULT : in STD_LOGIC; M_AXI_GP0_ARVALID : out STD_LOGIC; M_AXI_GP0_AWVALID : out STD_LOGIC; M_AXI_GP0_BREADY : out STD_LOGIC; M_AXI_GP0_RREADY : out STD_LOGIC; M_AXI_GP0_WLAST : out STD_LOGIC; M_AXI_GP0_WVALID : out STD_LOGIC; M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ACLK : in STD_LOGIC; M_AXI_GP0_ARREADY : in STD_LOGIC; M_AXI_GP0_AWREADY : in STD_LOGIC; M_AXI_GP0_BVALID : in STD_LOGIC; M_AXI_GP0_RLAST : in STD_LOGIC; M_AXI_GP0_RVALID : in STD_LOGIC; M_AXI_GP0_WREADY : in STD_LOGIC; M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); FCLK_CLK0 : out STD_LOGIC; FCLK_CLK1 : out STD_LOGIC; FCLK_RESET0_N : out STD_LOGIC; MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 ); DDR_CAS_n : inout STD_LOGIC; DDR_CKE : inout STD_LOGIC; DDR_Clk_n : inout STD_LOGIC; DDR_Clk : inout STD_LOGIC; DDR_CS_n : inout STD_LOGIC; DDR_DRSTB : inout STD_LOGIC; DDR_ODT : inout STD_LOGIC; DDR_RAS_n : inout STD_LOGIC; DDR_WEB : inout STD_LOGIC; DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_VRN : inout STD_LOGIC; DDR_VRP : inout STD_LOGIC; DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 ); PS_SRSTB : inout STD_LOGIC; PS_CLK : inout STD_LOGIC; PS_PORB : inout STD_LOGIC ); end ip_design_processing_system7_0_0; architecture stub of ip_design_processing_system7_0_0 is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; attribute black_box_pad_pin of stub : architecture is "I2C0_SDA_I,I2C0_SDA_O,I2C0_SDA_T,I2C0_SCL_I,I2C0_SCL_O,I2C0_SCL_T,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_CLK1,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "processing_system7_v5_5_processing_system7,Vivado 2017.3"; begin end;	mit
khaledhassan/vhdl-examples	adder_tree/adder.vhd	1	2067	-- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net> -- This software is distributed under the terms of the MIT License shown below. -- -- Permission is hereby granted, free of charge, to any person obtaining a copy -- of this software and associated documentation files (the "Software"), to -- deal in the Software without restriction, including without limitation the -- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or -- sell copies of the Software, and to permit persons to whom the Software is -- furnished to do so, subject to the following conditions: -- -- The above copyright notice and this permission notice shall be included in -- all copies or substantial portions of the Software. -- -- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -- IN THE SOFTWARE. -- Implements an adder of variable width with carry signals. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity adder is generic ( WIDTH : positive := 8 ); port ( input1 : in std_logic_vector(WIDTH-1 downto 0); input2 : in std_logic_vector(WIDTH-1 downto 0); c_in : in std_logic; output : out std_logic_vector(WIDTH-1 downto 0); c_out : out std_logic ); end; architecture BHV of adder is signal full_sum : std_logic_vector(WIDTH downto 0); signal c_in_vec : std_logic_vector(0 downto 0); begin c_in_vec(0) <= c_in; full_sum <= std_logic_vector( resize(unsigned(input1), WIDTH+1) + resize(unsigned(input2), WIDTH+1) + resize(unsigned(c_in_vec), WIDTH+1) ); output <= full_sum(WIDTH-1 downto 0); c_out <= full_sum(WIDTH); end BHV;	mit
MarkBlanco/FPGA_Sandbox	RecComp/Lab1/my_lab_1/my_lab_1.ip_user_files/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_gpio_1_0/sim/zqynq_lab_1_design_axi_gpio_1_0.vhd	1	9004	-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:axi_gpio:2.0 -- IP Revision: 15 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY axi_gpio_v2_0_15; USE axi_gpio_v2_0_15.axi_gpio; ENTITY zqynq_lab_1_design_axi_gpio_1_0 IS PORT ( s_axi_aclk : IN STD_LOGIC; s_axi_aresetn : IN STD_LOGIC; s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; ip2intc_irpt : OUT STD_LOGIC; gpio_io_i : IN STD_LOGIC_VECTOR(4 DOWNTO 0) ); END zqynq_lab_1_design_axi_gpio_1_0; ARCHITECTURE zqynq_lab_1_design_axi_gpio_1_0_arch OF zqynq_lab_1_design_axi_gpio_1_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF zqynq_lab_1_design_axi_gpio_1_0_arch: ARCHITECTURE IS "yes"; COMPONENT axi_gpio IS GENERIC ( C_FAMILY : STRING; C_S_AXI_ADDR_WIDTH : INTEGER; C_S_AXI_DATA_WIDTH : INTEGER; C_GPIO_WIDTH : INTEGER; C_GPIO2_WIDTH : INTEGER; C_ALL_INPUTS : INTEGER; C_ALL_INPUTS_2 : INTEGER; C_ALL_OUTPUTS : INTEGER; C_ALL_OUTPUTS_2 : INTEGER; C_INTERRUPT_PRESENT : INTEGER; C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0); C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0); C_IS_DUAL : INTEGER; C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) ); PORT ( s_axi_aclk : IN STD_LOGIC; s_axi_aresetn : IN STD_LOGIC; s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; ip2intc_irpt : OUT STD_LOGIC; gpio_io_i : IN STD_LOGIC_VECTOR(4 DOWNTO 0); gpio_io_o : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); gpio_io_t : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0); gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT axi_gpio; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY"; ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT"; ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I"; BEGIN U0 : axi_gpio GENERIC MAP ( C_FAMILY => "zynq", C_S_AXI_ADDR_WIDTH => 9, C_S_AXI_DATA_WIDTH => 32, C_GPIO_WIDTH => 5, C_GPIO2_WIDTH => 32, C_ALL_INPUTS => 1, C_ALL_INPUTS_2 => 0, C_ALL_OUTPUTS => 0, C_ALL_OUTPUTS_2 => 0, C_INTERRUPT_PRESENT => 1, C_DOUT_DEFAULT => X"00000000", C_TRI_DEFAULT => X"FFFFFFFF", C_IS_DUAL => 0, C_DOUT_DEFAULT_2 => X"00000000", C_TRI_DEFAULT_2 => X"FFFFFFFF" ) PORT MAP ( s_axi_aclk => s_axi_aclk, s_axi_aresetn => s_axi_aresetn, s_axi_awaddr => s_axi_awaddr, s_axi_awvalid => s_axi_awvalid, s_axi_awready => s_axi_awready, s_axi_wdata => s_axi_wdata, s_axi_wstrb => s_axi_wstrb, s_axi_wvalid => s_axi_wvalid, s_axi_wready => s_axi_wready, s_axi_bresp => s_axi_bresp, s_axi_bvalid => s_axi_bvalid, s_axi_bready => s_axi_bready, s_axi_araddr => s_axi_araddr, s_axi_arvalid => s_axi_arvalid, s_axi_arready => s_axi_arready, s_axi_rdata => s_axi_rdata, s_axi_rresp => s_axi_rresp, s_axi_rvalid => s_axi_rvalid, s_axi_rready => s_axi_rready, ip2intc_irpt => ip2intc_irpt, gpio_io_i => gpio_io_i, gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)) ); END zqynq_lab_1_design_axi_gpio_1_0_arch;	mit
dawsonjon/FPGA-TX	synthesis/cmod_a7_15/tx/serial_in.vhd	3	3303	-------------------------------------------------------------------------------- --- --- SERIAL INPUT --- --- :Author: Jonathan P Dawson --- :Date: 17/10/2013 --- :email: [email protected] --- :license: MIT --- :Copyright: Copyright (C) Jonathan P Dawson 2013 --- --- A Serial Input Component --- -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; entity serial_input is generic( clock_frequency : integer; baud_rate : integer ); port( clk : in std_logic; rst : in std_logic; rx : in std_logic; out1 : out std_logic_vector(7 downto 0); out1_stb : out std_logic; out1_ack : in std_logic ); end entity serial_input; architecture rtl of serial_input is component fifo is generic( width : integer; depth : integer ); port( clk : in std_logic; rst : in std_logic; input : in std_logic_vector(width-1 downto 0); input_stb : in std_logic; input_ack : out std_logic; output : out std_logic_vector(width-1 downto 0); output_stb : out std_logic; output_ack : in std_logic ); end component fifo; constant bit_clocks : integer := integer(round(real(clock_frequency)/real(baud_rate)))-1; constant bit_clocks_1_5 : integer := integer(round(real(clock_frequency)/real(baud_rate) * 1.5))-1; signal bit_count : integer range 0 to 8; signal bit_spacing : integer range 0 to bit_clocks_1_5; type serial_in_state_type is (idle, get_byte, output_data, wait_done); signal state : serial_in_state_type; signal rx_d, rx_d2 : std_logic; signal data : std_logic_vector(8 downto 0); signal int_out1 : std_logic_vector(7 downto 0); signal int_out1_stb : std_logic; signal int_out1_ack : std_logic; begin fifo_1 : fifo generic map( width => 8, depth => 16384 ) port map( clk => clk, rst => rst, input => int_out1, input_stb => int_out1_stb, input_ack => int_out1_ack, output => out1, output_stb => out1_stb, output_ack => out1_ack ); process begin wait until rising_edge(clk); rx_d <= rx; rx_d2 <= rx_d; case state is when idle => if rx_d2 = '0' then state <= get_byte; bit_spacing <= bit_clocks_1_5; bit_count <= 8; end if; when get_byte => if bit_spacing = 0 then data <= rx_d2 & data(8 downto 1); if bit_count = 0 then int_out1_stb <= '1'; state <= output_data; else bit_spacing <= bit_clocks; bit_count <= bit_count - 1; end if; else bit_spacing <= bit_spacing - 1; end if; when output_data => if int_out1_ack = '1' then int_out1_stb <= '0'; state <= wait_done; end if; when wait_done => if rx_d2 = '1' then state <= idle; end if; when others => state <= idle; end case; if rst = '1' then state <= idle; int_out1_stb <= '0'; end if; end process; int_out1 <= data(7 downto 0); end architecture rtl;	mit
MarkBlanco/FPGA_Sandbox	RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ipshared/b19f/hdl/vhdl/lms_pcore.vhd	2	10165	-- ------------------------------------------------------------- -- -- File Name: hdl_prj\hdlsrc\lms\lms_pcore.vhd -- Created: 2015-06-19 16:39:46 -- -- Generated by MATLAB 8.5 and HDL Coder 3.6 -- -- -- ------------------------------------------------------------- -- Rate and Clocking Details -- ------------------------------------------------------------- -- Model base rate: -1 -- Target subsystem base rate: -1 -- -- ------------------------------------------------------------- -- ------------------------------------------------------------- -- -- Module: lms_pcore -- Source Path: lms_pcore -- Hierarchy Level: 0 -- -- ------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.numeric_std.ALL; ENTITY lms_pcore IS PORT( IPCORE_CLK : IN std_logic; -- ufix1 IPCORE_RESETN : IN std_logic; -- ufix1 AXI4_Lite_ACLK : IN std_logic; -- ufix1 AXI4_Lite_ARESETN : IN std_logic; -- ufix1 AXI4_Lite_AWADDR : IN std_logic_vector(15 DOWNTO 0); -- ufix16 AXI4_Lite_AWVALID : IN std_logic; -- ufix1 AXI4_Lite_WDATA : IN std_logic_vector(31 DOWNTO 0); -- ufix32 AXI4_Lite_WSTRB : IN std_logic_vector(3 DOWNTO 0); -- ufix4 AXI4_Lite_WVALID : IN std_logic; -- ufix1 AXI4_Lite_BREADY : IN std_logic; -- ufix1 AXI4_Lite_ARADDR : IN std_logic_vector(15 DOWNTO 0); -- ufix16 AXI4_Lite_ARVALID : IN std_logic; -- ufix1 AXI4_Lite_RREADY : IN std_logic; -- ufix1 AXI4_Lite_AWREADY : OUT std_logic; -- ufix1 AXI4_Lite_WREADY : OUT std_logic; -- ufix1 AXI4_Lite_BRESP : OUT std_logic_vector(1 DOWNTO 0); -- ufix2 AXI4_Lite_BVALID : OUT std_logic; -- ufix1 AXI4_Lite_ARREADY : OUT std_logic; -- ufix1 AXI4_Lite_RDATA : OUT std_logic_vector(31 DOWNTO 0); -- ufix32 AXI4_Lite_RRESP : OUT std_logic_vector(1 DOWNTO 0); -- ufix2 AXI4_Lite_RVALID : OUT std_logic -- ufix1 ); END lms_pcore; ARCHITECTURE rtl OF lms_pcore IS -- Component Declarations COMPONENT lms_pcore_dut PORT( clk : IN std_logic; -- ufix1 reset : IN std_logic; dut_enable : IN std_logic; -- ufix1 x_k : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14 d_k : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14 ce_out : OUT std_logic; -- ufix1 e_k : OUT std_logic_vector(15 DOWNTO 0) -- sfix16_En14 ); END COMPONENT; COMPONENT lms_pcore_cop PORT( clk : IN std_logic; -- ufix1 reset : IN std_logic; in_strobe : IN std_logic; -- ufix1 cop_enable : IN std_logic; -- ufix1 out_ready : OUT std_logic; -- ufix1 dut_enable : OUT std_logic; -- ufix1 reg_strobe : OUT std_logic -- ufix1 ); END COMPONENT; COMPONENT lms_pcore_axi_lite PORT( reset : IN std_logic; AXI4_Lite_ACLK : IN std_logic; -- ufix1 AXI4_Lite_ARESETN : IN std_logic; -- ufix1 AXI4_Lite_AWADDR : IN std_logic_vector(15 DOWNTO 0); -- ufix16 AXI4_Lite_AWVALID : IN std_logic; -- ufix1 AXI4_Lite_WDATA : IN std_logic_vector(31 DOWNTO 0); -- ufix32 AXI4_Lite_WSTRB : IN std_logic_vector(3 DOWNTO 0); -- ufix4 AXI4_Lite_WVALID : IN std_logic; -- ufix1 AXI4_Lite_BREADY : IN std_logic; -- ufix1 AXI4_Lite_ARADDR : IN std_logic_vector(15 DOWNTO 0); -- ufix16 AXI4_Lite_ARVALID : IN std_logic; -- ufix1 AXI4_Lite_RREADY : IN std_logic; -- ufix1 read_cop_out_ready : IN std_logic; -- ufix1 cop_reg_strobe : IN std_logic; -- ufix1 read_e_k : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14 AXI4_Lite_AWREADY : OUT std_logic; -- ufix1 AXI4_Lite_WREADY : OUT std_logic; -- ufix1 AXI4_Lite_BRESP : OUT std_logic_vector(1 DOWNTO 0); -- ufix2 AXI4_Lite_BVALID : OUT std_logic; -- ufix1 AXI4_Lite_ARREADY : OUT std_logic; -- ufix1 AXI4_Lite_RDATA : OUT std_logic_vector(31 DOWNTO 0); -- ufix32 AXI4_Lite_RRESP : OUT std_logic_vector(1 DOWNTO 0); -- ufix2 AXI4_Lite_RVALID : OUT std_logic; -- ufix1 write_axi_enable : OUT std_logic; -- ufix1 strobe_cop_in_strobe : OUT std_logic; -- ufix1 write_x_k : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14 write_d_k : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14 reset_internal : OUT std_logic -- ufix1 ); END COMPONENT; -- Component Configuration Statements FOR ALL : lms_pcore_dut USE ENTITY work.lms_pcore_dut(rtl); FOR ALL : lms_pcore_cop USE ENTITY work.lms_pcore_cop(rtl); FOR ALL : lms_pcore_axi_lite USE ENTITY work.lms_pcore_axi_lite(rtl); -- Signals SIGNAL reset : std_logic; SIGNAL reset_cm : std_logic; -- ufix1 SIGNAL cop_dut_enable : std_logic; -- ufix1 SIGNAL write_x_k : std_logic_vector(15 DOWNTO 0); -- ufix16 SIGNAL write_d_k : std_logic_vector(15 DOWNTO 0); -- ufix16 SIGNAL ce_out_sig : std_logic; -- ufix1 SIGNAL e_k_sig : std_logic_vector(15 DOWNTO 0); -- ufix16 SIGNAL reset_internal : std_logic; -- ufix1 SIGNAL strobe_cop_in_strobe : std_logic; -- ufix1 SIGNAL write_axi_enable : std_logic; -- ufix1 SIGNAL cop_out_ready : std_logic; -- ufix1 SIGNAL cop_reg_strobe : std_logic; -- ufix1 SIGNAL AXI4_Lite_BRESP_tmp : std_logic_vector(1 DOWNTO 0); -- ufix2 SIGNAL AXI4_Lite_RDATA_tmp : std_logic_vector(31 DOWNTO 0); -- ufix32 SIGNAL AXI4_Lite_RRESP_tmp : std_logic_vector(1 DOWNTO 0); -- ufix2 BEGIN u_lms_pcore_dut_inst : lms_pcore_dut PORT MAP( clk => IPCORE_CLK, -- ufix1 reset => reset, dut_enable => cop_dut_enable, -- ufix1 x_k => write_x_k, -- sfix16_En14 d_k => write_d_k, -- sfix16_En14 ce_out => ce_out_sig, -- ufix1 e_k => e_k_sig -- sfix16_En14 ); u_lms_pcore_cop_inst : lms_pcore_cop PORT MAP( clk => IPCORE_CLK, -- ufix1 reset => reset, in_strobe => strobe_cop_in_strobe, -- ufix1 cop_enable => write_axi_enable, -- ufix1 out_ready => cop_out_ready, -- ufix1 dut_enable => cop_dut_enable, -- ufix1 reg_strobe => cop_reg_strobe -- ufix1 ); u_lms_pcore_axi_lite_inst : lms_pcore_axi_lite PORT MAP( reset => reset, AXI4_Lite_ACLK => AXI4_Lite_ACLK, -- ufix1 AXI4_Lite_ARESETN => AXI4_Lite_ARESETN, -- ufix1 AXI4_Lite_AWADDR => AXI4_Lite_AWADDR, -- ufix16 AXI4_Lite_AWVALID => AXI4_Lite_AWVALID, -- ufix1 AXI4_Lite_WDATA => AXI4_Lite_WDATA, -- ufix32 AXI4_Lite_WSTRB => AXI4_Lite_WSTRB, -- ufix4 AXI4_Lite_WVALID => AXI4_Lite_WVALID, -- ufix1 AXI4_Lite_BREADY => AXI4_Lite_BREADY, -- ufix1 AXI4_Lite_ARADDR => AXI4_Lite_ARADDR, -- ufix16 AXI4_Lite_ARVALID => AXI4_Lite_ARVALID, -- ufix1 AXI4_Lite_RREADY => AXI4_Lite_RREADY, -- ufix1 read_cop_out_ready => cop_out_ready, -- ufix1 cop_reg_strobe => strobe_cop_in_strobe, -- ufix1 read_e_k => e_k_sig, -- sfix16_En14 AXI4_Lite_AWREADY => AXI4_Lite_AWREADY, -- ufix1 AXI4_Lite_WREADY => AXI4_Lite_WREADY, -- ufix1 AXI4_Lite_BRESP => AXI4_Lite_BRESP_tmp, -- ufix2 AXI4_Lite_BVALID => AXI4_Lite_BVALID, -- ufix1 AXI4_Lite_ARREADY => AXI4_Lite_ARREADY, -- ufix1 AXI4_Lite_RDATA => AXI4_Lite_RDATA_tmp, -- ufix32 AXI4_Lite_RRESP => AXI4_Lite_RRESP_tmp, -- ufix2 AXI4_Lite_RVALID => AXI4_Lite_RVALID, -- ufix1 write_axi_enable => write_axi_enable, -- ufix1 strobe_cop_in_strobe => strobe_cop_in_strobe, -- ufix1 write_x_k => write_x_k, -- sfix16_En14 write_d_k => write_d_k, -- sfix16_En14 reset_internal => reset_internal -- ufix1 ); reset_cm <= NOT IPCORE_RESETN; reset <= reset_cm OR reset_internal; AXI4_Lite_BRESP <= AXI4_Lite_BRESP_tmp; AXI4_Lite_RDATA <= AXI4_Lite_RDATA_tmp; AXI4_Lite_RRESP <= AXI4_Lite_RRESP_tmp; END rtl;	mit
MarkBlanco/FPGA_Sandbox	RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_bram_ctrl_0_0/zqynq_lab_1_design_axi_bram_ctrl_0_0_sim_netlist.vhdl	1	291825	-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017 -- Date : Sat Sep 23 13:25:27 2017 -- Host : DarkCube running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -- c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_bram_ctrl_0_0/zqynq_lab_1_design_axi_bram_ctrl_0_0_sim_netlist.vhdl -- Design : zqynq_lab_1_design_axi_bram_ctrl_0_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zqynq_lab_1_design_axi_bram_ctrl_0_0_SRL_FIFO is port ( bvalid_cnt_inc : out STD_LOGIC; bid_gets_fifo_load_d1_reg : out STD_LOGIC; bid_gets_fifo_load : out STD_LOGIC; axi_wdata_full_cmb114_out : out STD_LOGIC; \axi_bid_int_reg[0]\ : out STD_LOGIC; s_axi_aresetn : in STD_LOGIC; s_axi_aclk : in STD_LOGIC; \bvalid_cnt_reg[2]\ : in STD_LOGIC; wr_addr_sm_cs : in STD_LOGIC; \bvalid_cnt_reg[2]_0\ : in STD_LOGIC; \GEN_AWREADY.axi_aresetn_d2_reg\ : in STD_LOGIC; axi_awaddr_full : in STD_LOGIC; bram_addr_ld_en : in STD_LOGIC; bid_gets_fifo_load_d1 : in STD_LOGIC; s_axi_bready : in STD_LOGIC; axi_bvalid_int_reg : in STD_LOGIC; bvalid_cnt : in STD_LOGIC_VECTOR ( 2 downto 0 ); \bvalid_cnt_reg[1]\ : in STD_LOGIC; aw_active : in STD_LOGIC; s_axi_awready : in STD_LOGIC; s_axi_awvalid : in STD_LOGIC; curr_awlen_reg_1_or_2 : in STD_LOGIC; axi_awlen_pipe_1_or_2 : in STD_LOGIC; \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ : in STD_LOGIC; last_data_ack_mod : in STD_LOGIC; axi_awid_pipe : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 ); \out\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); axi_wr_burst : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wlast : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_bram_ctrl_0_0_SRL_FIFO : entity is "SRL_FIFO"; end zqynq_lab_1_design_axi_bram_ctrl_0_0_SRL_FIFO; architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0_SRL_FIFO is signal \Addr_Counters[0].FDRE_I_n_0\ : STD_LOGIC; signal \Addr_Counters[1].FDRE_I_n_0\ : STD_LOGIC; signal \Addr_Counters[2].FDRE_I_n_0\ : STD_LOGIC; signal \Addr_Counters[3].FDRE_I_n_0\ : STD_LOGIC; signal \Addr_Counters[3].XORCY_I_i_1_n_0\ : STD_LOGIC; signal CI : STD_LOGIC; signal D : STD_LOGIC; signal Data_Exists_DFF_i_2_n_0 : STD_LOGIC; signal Data_Exists_DFF_i_3_n_0 : STD_LOGIC; signal S : STD_LOGIC; signal S0_out : STD_LOGIC; signal S1_out : STD_LOGIC; signal addr_cy_1 : STD_LOGIC; signal addr_cy_2 : STD_LOGIC; signal addr_cy_3 : STD_LOGIC; signal \axi_bid_int[0]_i_2_n_0\ : STD_LOGIC; signal axi_bvalid_int_i_4_n_0 : STD_LOGIC; signal axi_bvalid_int_i_5_n_0 : STD_LOGIC; signal axi_bvalid_int_i_6_n_0 : STD_LOGIC; signal \^axi_wdata_full_cmb114_out\ : STD_LOGIC; signal bid_fifo_ld : STD_LOGIC; signal bid_fifo_not_empty : STD_LOGIC; signal bid_fifo_rd : STD_LOGIC; signal \^bid_gets_fifo_load\ : STD_LOGIC; signal bid_gets_fifo_load_d1_i_3_n_0 : STD_LOGIC; signal \^bid_gets_fifo_load_d1_reg\ : STD_LOGIC; signal \^bvalid_cnt_inc\ : STD_LOGIC; signal sum_A_0 : STD_LOGIC; signal sum_A_1 : STD_LOGIC; signal sum_A_2 : STD_LOGIC; signal sum_A_3 : STD_LOGIC; signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute BOX_TYPE : string; attribute BOX_TYPE of \Addr_Counters[0].FDRE_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute XILINX_TRANSFORM_PINMAP : string; attribute XILINX_TRANSFORM_PINMAP of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "LO:O"; attribute BOX_TYPE of \Addr_Counters[1].FDRE_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \Addr_Counters[2].FDRE_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \Addr_Counters[3].FDRE_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of Data_Exists_DFF : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of Data_Exists_DFF : label is "FDR"; attribute BOX_TYPE of \FIFO_RAM[0].SRL16E_I\ : label is "PRIMITIVE"; attribute srl_bus_name : string; attribute srl_bus_name of \FIFO_RAM[0].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM "; attribute srl_name : string; attribute srl_name of \FIFO_RAM[0].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[0].SRL16E_I "; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of axi_bvalid_int_i_3 : label is "soft_lutpair44"; attribute SOFT_HLUTNM of bid_gets_fifo_load_d1_i_3 : label is "soft_lutpair44"; begin axi_wdata_full_cmb114_out <= \^axi_wdata_full_cmb114_out\; bid_gets_fifo_load <= \^bid_gets_fifo_load\; bid_gets_fifo_load_d1_reg <= \^bid_gets_fifo_load_d1_reg\; bvalid_cnt_inc <= \^bvalid_cnt_inc\; \Addr_Counters[0].FDRE_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => bid_fifo_not_empty, D => sum_A_3, Q => \Addr_Counters[0].FDRE_I_n_0\, R => s_axi_aresetn ); \Addr_Counters[0].MUXCY_L_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED\(3), CO(2) => addr_cy_1, CO(1) => addr_cy_2, CO(0) => addr_cy_3, CYINIT => CI, DI(3) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED\(3), DI(2) => \Addr_Counters[2].FDRE_I_n_0\, DI(1) => \Addr_Counters[1].FDRE_I_n_0\, DI(0) => \Addr_Counters[0].FDRE_I_n_0\, O(3) => sum_A_0, O(2) => sum_A_1, O(1) => sum_A_2, O(0) => sum_A_3, S(3) => \Addr_Counters[3].XORCY_I_i_1_n_0\, S(2) => S0_out, S(1) => S1_out, S(0) => S ); \Addr_Counters[0].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000FFFFFFFE0000" ) port map ( I0 => \Addr_Counters[1].FDRE_I_n_0\, I1 => \Addr_Counters[3].FDRE_I_n_0\, I2 => \Addr_Counters[2].FDRE_I_n_0\, I3 => bram_addr_ld_en, I4 => \axi_bid_int[0]_i_2_n_0\, I5 => \Addr_Counters[0].FDRE_I_n_0\, O => S ); \Addr_Counters[0].MUXCY_L_I_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"8AAAAAAAAAAAAAAA" ) port map ( I0 => bram_addr_ld_en, I1 => \axi_bid_int[0]_i_2_n_0\, I2 => \Addr_Counters[0].FDRE_I_n_0\, I3 => \Addr_Counters[1].FDRE_I_n_0\, I4 => \Addr_Counters[3].FDRE_I_n_0\, I5 => \Addr_Counters[2].FDRE_I_n_0\, O => CI ); \Addr_Counters[1].FDRE_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => bid_fifo_not_empty, D => sum_A_2, Q => \Addr_Counters[1].FDRE_I_n_0\, R => s_axi_aresetn ); \Addr_Counters[1].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000FFFFFFFE0000" ) port map ( I0 => \Addr_Counters[0].FDRE_I_n_0\, I1 => \Addr_Counters[3].FDRE_I_n_0\, I2 => \Addr_Counters[2].FDRE_I_n_0\, I3 => bram_addr_ld_en, I4 => \axi_bid_int[0]_i_2_n_0\, I5 => \Addr_Counters[1].FDRE_I_n_0\, O => S1_out ); \Addr_Counters[2].FDRE_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => bid_fifo_not_empty, D => sum_A_1, Q => \Addr_Counters[2].FDRE_I_n_0\, R => s_axi_aresetn ); \Addr_Counters[2].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000FFFFFFFE0000" ) port map ( I0 => \Addr_Counters[0].FDRE_I_n_0\, I1 => \Addr_Counters[1].FDRE_I_n_0\, I2 => \Addr_Counters[3].FDRE_I_n_0\, I3 => bram_addr_ld_en, I4 => \axi_bid_int[0]_i_2_n_0\, I5 => \Addr_Counters[2].FDRE_I_n_0\, O => S0_out ); \Addr_Counters[3].FDRE_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => bid_fifo_not_empty, D => sum_A_0, Q => \Addr_Counters[3].FDRE_I_n_0\, R => s_axi_aresetn ); \Addr_Counters[3].XORCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000FFFFFFFE0000" ) port map ( I0 => \Addr_Counters[0].FDRE_I_n_0\, I1 => \Addr_Counters[1].FDRE_I_n_0\, I2 => \Addr_Counters[2].FDRE_I_n_0\, I3 => bram_addr_ld_en, I4 => \axi_bid_int[0]_i_2_n_0\, I5 => \Addr_Counters[3].FDRE_I_n_0\, O => \Addr_Counters[3].XORCY_I_i_1_n_0\ ); Data_Exists_DFF: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => D, Q => bid_fifo_not_empty, R => s_axi_aresetn ); Data_Exists_DFF_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"FE0A" ) port map ( I0 => bram_addr_ld_en, I1 => Data_Exists_DFF_i_2_n_0, I2 => Data_Exists_DFF_i_3_n_0, I3 => bid_fifo_not_empty, O => D ); Data_Exists_DFF_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"000000000000FFFD" ) port map ( I0 => \^bvalid_cnt_inc\, I1 => bvalid_cnt(2), I2 => bvalid_cnt(0), I3 => bvalid_cnt(1), I4 => \^bid_gets_fifo_load_d1_reg\, I5 => bid_gets_fifo_load_d1, O => Data_Exists_DFF_i_2_n_0 ); Data_Exists_DFF_i_3: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => \Addr_Counters[0].FDRE_I_n_0\, I1 => \Addr_Counters[1].FDRE_I_n_0\, I2 => \Addr_Counters[3].FDRE_I_n_0\, I3 => \Addr_Counters[2].FDRE_I_n_0\, O => Data_Exists_DFF_i_3_n_0 ); \FIFO_RAM[0].SRL16E_I\: unisim.vcomponents.SRL16E generic map( INIT => X"0000", IS_CLK_INVERTED => '0' ) port map ( A0 => \Addr_Counters[0].FDRE_I_n_0\, A1 => \Addr_Counters[1].FDRE_I_n_0\, A2 => \Addr_Counters[2].FDRE_I_n_0\, A3 => \Addr_Counters[3].FDRE_I_n_0\, CE => CI, CLK => s_axi_aclk, D => bid_fifo_ld, Q => bid_fifo_rd ); \FIFO_RAM[0].SRL16E_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axi_awid_pipe, I1 => axi_awaddr_full, I2 => s_axi_awid(0), O => bid_fifo_ld ); \axi_bid_int[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"ACAFACA0" ) port map ( I0 => bid_fifo_ld, I1 => bid_fifo_rd, I2 => \^bid_gets_fifo_load\, I3 => \axi_bid_int[0]_i_2_n_0\, I4 => s_axi_bid(0), O => \axi_bid_int_reg[0]\ ); \axi_bid_int[0]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"A888AAAAA8888888" ) port map ( I0 => bid_fifo_not_empty, I1 => bid_gets_fifo_load_d1, I2 => s_axi_bready, I3 => axi_bvalid_int_reg, I4 => bid_gets_fifo_load_d1_i_3_n_0, I5 => \^bvalid_cnt_inc\, O => \axi_bid_int[0]_i_2_n_0\ ); axi_bvalid_int_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"000055FD00000000" ) port map ( I0 => \out\(2), I1 => \^axi_wdata_full_cmb114_out\, I2 => axi_bvalid_int_i_4_n_0, I3 => axi_wr_burst, I4 => \out\(1), I5 => axi_bvalid_int_i_5_n_0, O => \^bvalid_cnt_inc\ ); axi_bvalid_int_i_3: unisim.vcomponents.LUT5 generic map( INIT => X"FE000000" ) port map ( I0 => bvalid_cnt(1), I1 => bvalid_cnt(0), I2 => bvalid_cnt(2), I3 => axi_bvalid_int_reg, I4 => s_axi_bready, O => \^bid_gets_fifo_load_d1_reg\ ); axi_bvalid_int_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"1F11000000000000" ) port map ( I0 => axi_bvalid_int_i_6_n_0, I1 => \bvalid_cnt_reg[2]\, I2 => wr_addr_sm_cs, I3 => \bvalid_cnt_reg[2]_0\, I4 => \GEN_AWREADY.axi_aresetn_d2_reg\, I5 => axi_awaddr_full, O => axi_bvalid_int_i_4_n_0 ); axi_bvalid_int_i_5: unisim.vcomponents.LUT5 generic map( INIT => X"74446444" ) port map ( I0 => \out\(0), I1 => \out\(2), I2 => s_axi_wvalid, I3 => s_axi_wlast, I4 => \^axi_wdata_full_cmb114_out\, O => axi_bvalid_int_i_5_n_0 ); axi_bvalid_int_i_6: unisim.vcomponents.LUT5 generic map( INIT => X"FEFFFFFF" ) port map ( I0 => curr_awlen_reg_1_or_2, I1 => axi_awlen_pipe_1_or_2, I2 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\, I3 => axi_awaddr_full, I4 => last_data_ack_mod, O => axi_bvalid_int_i_6_n_0 ); axi_wready_int_mod_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"7F7F7F007F007F00" ) port map ( I0 => bvalid_cnt(1), I1 => bvalid_cnt(0), I2 => bvalid_cnt(2), I3 => aw_active, I4 => s_axi_awready, I5 => s_axi_awvalid, O => \^axi_wdata_full_cmb114_out\ ); bid_gets_fifo_load_d1_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"00000800AA00AA00" ) port map ( I0 => bram_addr_ld_en, I1 => \^bid_gets_fifo_load_d1_reg\, I2 => bid_fifo_not_empty, I3 => \^bvalid_cnt_inc\, I4 => \bvalid_cnt_reg[1]\, I5 => bid_gets_fifo_load_d1_i_3_n_0, O => \^bid_gets_fifo_load\ ); bid_gets_fifo_load_d1_i_3: unisim.vcomponents.LUT3 generic map( INIT => X"FE" ) port map ( I0 => bvalid_cnt(2), I1 => bvalid_cnt(0), I2 => bvalid_cnt(1), O => bid_gets_fifo_load_d1_i_3_n_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst is port ( SR : out STD_LOGIC_VECTOR ( 0 to 0 ); bram_addr_ld_en_mod : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); D : out STD_LOGIC_VECTOR ( 13 downto 0 ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ : out STD_LOGIC; bram_addr_ld_en : out STD_LOGIC; \save_init_bram_addr_ld_reg[15]_0\ : out STD_LOGIC; \save_init_bram_addr_ld_reg[15]_1\ : out STD_LOGIC; \save_init_bram_addr_ld_reg[15]_2\ : out STD_LOGIC; \wrap_burst_total_reg[0]_0\ : out STD_LOGIC; \wrap_burst_total_reg[2]_0\ : out STD_LOGIC; curr_fixed_burst_reg_reg : out STD_LOGIC; curr_wrap_burst_reg_reg : out STD_LOGIC; curr_fixed_burst_reg : in STD_LOGIC; bram_addr_inc : in STD_LOGIC; bram_addr_rst_cmb : in STD_LOGIC; s_axi_aresetn : in STD_LOGIC; \out\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_wvalid : in STD_LOGIC; bram_addr_a : in STD_LOGIC_VECTOR ( 9 downto 0 ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0\ : in STD_LOGIC; \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ : in STD_LOGIC; \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\ : in STD_LOGIC; axi_awaddr_full : in STD_LOGIC; s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 ); \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\ : in STD_LOGIC; \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\ : in STD_LOGIC; \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\ : in STD_LOGIC; \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\ : in STD_LOGIC; \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\ : in STD_LOGIC; \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\ : in STD_LOGIC; \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\ : in STD_LOGIC; \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\ : in STD_LOGIC; \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\ : in STD_LOGIC; \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\ : in STD_LOGIC; \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\ : in STD_LOGIC; \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\ : in STD_LOGIC; \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\ : in STD_LOGIC; \GEN_AWREADY.axi_aresetn_d2_reg\ : in STD_LOGIC; wr_addr_sm_cs : in STD_LOGIC; last_data_ack_mod : in STD_LOGIC; bvalid_cnt : in STD_LOGIC_VECTOR ( 2 downto 0 ); aw_active : in STD_LOGIC; s_axi_awvalid : in STD_LOGIC; \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ : in STD_LOGIC; axi_awlen_pipe_1_or_2 : in STD_LOGIC; curr_awlen_reg_1_or_2 : in STD_LOGIC; curr_wrap_burst_reg : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); axi_awsize_pipe : in STD_LOGIC_VECTOR ( 0 to 0 ); curr_fixed_burst : in STD_LOGIC; curr_wrap_burst : in STD_LOGIC; s_axi_aresetn_0 : in STD_LOGIC; s_axi_aclk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst : entity is "wrap_brst"; end zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst; architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst is signal \^d\ : STD_LOGIC_VECTOR ( 13 downto 0 ); signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\ : STD_LOGIC; signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\ : STD_LOGIC; signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0\ : STD_LOGIC; signal \^gen_dual_addr_cnt.bram_addr_int_reg[8]\ : STD_LOGIC; signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal bram_addr_ld : STD_LOGIC_VECTOR ( 9 downto 1 ); signal \^bram_addr_ld_en\ : STD_LOGIC; signal \^bram_addr_ld_en_mod\ : STD_LOGIC; signal save_init_bram_addr_ld : STD_LOGIC_VECTOR ( 15 downto 3 ); signal \save_init_bram_addr_ld[3]_i_2__0_n_0\ : STD_LOGIC; signal \save_init_bram_addr_ld[4]_i_2__0_n_0\ : STD_LOGIC; signal \save_init_bram_addr_ld[5]_i_2__0_n_0\ : STD_LOGIC; signal \^save_init_bram_addr_ld_reg[15]_0\ : STD_LOGIC; signal \^save_init_bram_addr_ld_reg[15]_1\ : STD_LOGIC; signal \^save_init_bram_addr_ld_reg[15]_2\ : STD_LOGIC; signal wrap_burst_total : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \wrap_burst_total[0]_i_1__0_n_0\ : STD_LOGIC; signal \wrap_burst_total[0]_i_2__0_n_0\ : STD_LOGIC; signal \wrap_burst_total[0]_i_4__0_n_0\ : STD_LOGIC; signal \wrap_burst_total[0]_i_5_n_0\ : STD_LOGIC; signal \wrap_burst_total[1]_i_1__0_n_0\ : STD_LOGIC; signal \wrap_burst_total[2]_i_1__0_n_0\ : STD_LOGIC; signal \wrap_burst_total[2]_i_2__0_n_0\ : STD_LOGIC; signal \^wrap_burst_total_reg[0]_0\ : STD_LOGIC; signal \^wrap_burst_total_reg[2]_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7\ : label is "soft_lutpair48"; attribute SOFT_HLUTNM of \curr_fixed_burst_reg_i_1__0\ : label is "soft_lutpair48"; attribute SOFT_HLUTNM of \save_init_bram_addr_ld[3]_i_2__0\ : label is "soft_lutpair49"; attribute SOFT_HLUTNM of \save_init_bram_addr_ld[4]_i_2__0\ : label is "soft_lutpair49"; attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_3__0\ : label is "soft_lutpair46"; attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_4__0\ : label is "soft_lutpair45"; attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_5\ : label is "soft_lutpair47"; attribute SOFT_HLUTNM of \wrap_burst_total[1]_i_1__0\ : label is "soft_lutpair45"; attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_2__0\ : label is "soft_lutpair46"; attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_3__0\ : label is "soft_lutpair47"; begin D(13 downto 0) <= \^d\(13 downto 0); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[8]\; SR(0) <= \^sr\(0); bram_addr_ld_en <= \^bram_addr_ld_en\; bram_addr_ld_en_mod <= \^bram_addr_ld_en_mod\; \save_init_bram_addr_ld_reg[15]_0\ <= \^save_init_bram_addr_ld_reg[15]_0\; \save_init_bram_addr_ld_reg[15]_1\ <= \^save_init_bram_addr_ld_reg[15]_1\; \save_init_bram_addr_ld_reg[15]_2\ <= \^save_init_bram_addr_ld_reg[15]_2\; \wrap_burst_total_reg[0]_0\ <= \^wrap_burst_total_reg[0]_0\; \wrap_burst_total_reg[2]_0\ <= \^wrap_burst_total_reg[2]_0\; \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"BB8BBBBB88B88888" ) port map ( I0 => bram_addr_ld(8), I1 => \^bram_addr_ld_en_mod\, I2 => bram_addr_a(6), I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\, I4 => bram_addr_a(7), I5 => bram_addr_a(8), O => \^d\(8) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAABAAAAAAAAAAAA" ) port map ( I0 => \^bram_addr_ld_en_mod\, I1 => curr_fixed_burst_reg, I2 => \out\(1), I3 => \out\(2), I4 => \out\(0), I5 => s_axi_wvalid, O => E(0) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"B88BB8B8" ) port map ( I0 => bram_addr_ld(9), I1 => \^bram_addr_ld_en_mod\, I2 => bram_addr_a(9), I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0\, I4 => bram_addr_a(8), O => \^d\(9) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => save_init_bram_addr_ld(12), I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\, I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\, I3 => axi_awaddr_full, I4 => s_axi_awaddr(10), O => \^d\(10) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[13]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => save_init_bram_addr_ld(13), I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\, I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\, I3 => axi_awaddr_full, I4 => s_axi_awaddr(11), O => \^d\(11) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[14]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => save_init_bram_addr_ld(14), I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\, I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\, I3 => axi_awaddr_full, I4 => s_axi_awaddr(12), O => \^d\(12) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"4500FFFF" ) port map ( I0 => \^bram_addr_ld_en_mod\, I1 => curr_fixed_burst_reg, I2 => bram_addr_inc, I3 => bram_addr_rst_cmb, I4 => s_axi_aresetn, O => \^sr\(0) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"AAABAAAAAAAAAAAA" ) port map ( I0 => \^bram_addr_ld_en\, I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\, I2 => \out\(1), I3 => \out\(2), I4 => \out\(0), I5 => s_axi_wvalid, O => \^bram_addr_ld_en_mod\ ); \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => save_init_bram_addr_ld(15), I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\, I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\, I3 => axi_awaddr_full, I4 => s_axi_awaddr(13), O => \^d\(13) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"55555555FFFFFFDF" ) port map ( I0 => curr_wrap_burst_reg, I1 => wrap_burst_total(1), I2 => wrap_burst_total(2), I3 => wrap_burst_total(0), I4 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\, I5 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0\, O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\ ); \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \^bram_addr_ld_en\, I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\, O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\ ); \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8\: unisim.vcomponents.LUT6 generic map( INIT => X"000000008F00C000" ) port map ( I0 => bram_addr_a(2), I1 => bram_addr_a(1), I2 => wrap_burst_total(1), I3 => bram_addr_a(0), I4 => wrap_burst_total(0), I5 => wrap_burst_total(2), O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0\ ); \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"B800B800B800FFFF" ) port map ( I0 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\, I1 => axi_awaddr_full, I2 => s_axi_awaddr(0), I3 => \^bram_addr_ld_en\, I4 => \^bram_addr_ld_en_mod\, I5 => bram_addr_a(0), O => \^d\(0) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"8BB8" ) port map ( I0 => bram_addr_ld(1), I1 => \^bram_addr_ld_en_mod\, I2 => bram_addr_a(1), I3 => bram_addr_a(0), O => \^d\(1) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"8BB8B8B8" ) port map ( I0 => bram_addr_ld(2), I1 => \^bram_addr_ld_en_mod\, I2 => bram_addr_a(2), I3 => bram_addr_a(0), I4 => bram_addr_a(1), O => \^d\(2) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"8BB8B8B8B8B8B8B8" ) port map ( I0 => bram_addr_ld(3), I1 => \^bram_addr_ld_en_mod\, I2 => bram_addr_a(3), I3 => bram_addr_a(2), I4 => bram_addr_a(0), I5 => bram_addr_a(1), O => \^d\(3) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[6]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"B88B" ) port map ( I0 => bram_addr_ld(4), I1 => \^bram_addr_ld_en_mod\, I2 => bram_addr_a(4), I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\, O => \^d\(4) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[7]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B88BB8B8" ) port map ( I0 => bram_addr_ld(5), I1 => \^bram_addr_ld_en_mod\, I2 => bram_addr_a(5), I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\, I4 => bram_addr_a(4), O => \^d\(5) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"B8B88BB8B8B8B8B8" ) port map ( I0 => bram_addr_ld(6), I1 => \^bram_addr_ld_en_mod\, I2 => bram_addr_a(6), I3 => bram_addr_a(4), I4 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\, I5 => bram_addr_a(5), O => \^d\(6) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_2__0\: unisim.vcomponents.LUT4 generic map( INIT => X"7FFF" ) port map ( I0 => bram_addr_a(1), I1 => bram_addr_a(0), I2 => bram_addr_a(2), I3 => bram_addr_a(3), O => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\ ); \GEN_DUAL_ADDR_CNT.bram_addr_int[9]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B88BB8B8" ) port map ( I0 => bram_addr_ld(7), I1 => \^bram_addr_ld_en_mod\, I2 => bram_addr_a(7), I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\, I4 => bram_addr_a(6), O => \^d\(7) ); \curr_fixed_burst_reg_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"00E2" ) port map ( I0 => curr_fixed_burst_reg, I1 => \^bram_addr_ld_en\, I2 => curr_fixed_burst, I3 => \^sr\(0), O => curr_fixed_burst_reg_reg ); \curr_wrap_burst_reg_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"00E2" ) port map ( I0 => curr_wrap_burst_reg, I1 => \^bram_addr_ld_en\, I2 => curr_wrap_burst, I3 => \^sr\(0), O => curr_wrap_burst_reg_reg ); \save_init_bram_addr_ld[10]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => save_init_bram_addr_ld(10), I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\, I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\, I3 => axi_awaddr_full, I4 => s_axi_awaddr(8), O => bram_addr_ld(8) ); \save_init_bram_addr_ld[11]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => save_init_bram_addr_ld(11), I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\, I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\, I3 => axi_awaddr_full, I4 => s_axi_awaddr(9), O => bram_addr_ld(9) ); \save_init_bram_addr_ld[15]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0808080808AA0808" ) port map ( I0 => \GEN_AWREADY.axi_aresetn_d2_reg\, I1 => \^save_init_bram_addr_ld_reg[15]_0\, I2 => wr_addr_sm_cs, I3 => \^save_init_bram_addr_ld_reg[15]_1\, I4 => last_data_ack_mod, I5 => \^save_init_bram_addr_ld_reg[15]_2\, O => \^bram_addr_ld_en\ ); \save_init_bram_addr_ld[15]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"007F007F007F0000" ) port map ( I0 => bvalid_cnt(2), I1 => bvalid_cnt(0), I2 => bvalid_cnt(1), I3 => aw_active, I4 => axi_awaddr_full, I5 => s_axi_awvalid, O => \^save_init_bram_addr_ld_reg[15]_0\ ); \save_init_bram_addr_ld[15]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"80" ) port map ( I0 => bvalid_cnt(2), I1 => bvalid_cnt(0), I2 => bvalid_cnt(1), O => \^save_init_bram_addr_ld_reg[15]_1\ ); \save_init_bram_addr_ld[15]_i_4\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFD" ) port map ( I0 => axi_awaddr_full, I1 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\, I2 => axi_awlen_pipe_1_or_2, I3 => curr_awlen_reg_1_or_2, O => \^save_init_bram_addr_ld_reg[15]_2\ ); \save_init_bram_addr_ld[3]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \save_init_bram_addr_ld[3]_i_2__0_n_0\, I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\, I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\, I3 => axi_awaddr_full, I4 => s_axi_awaddr(1), O => bram_addr_ld(1) ); \save_init_bram_addr_ld[3]_i_2__0\: unisim.vcomponents.LUT4 generic map( INIT => X"C80C" ) port map ( I0 => wrap_burst_total(0), I1 => save_init_bram_addr_ld(3), I2 => wrap_burst_total(1), I3 => wrap_burst_total(2), O => \save_init_bram_addr_ld[3]_i_2__0_n_0\ ); \save_init_bram_addr_ld[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \save_init_bram_addr_ld[4]_i_2__0_n_0\, I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\, I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\, I3 => axi_awaddr_full, I4 => s_axi_awaddr(2), O => bram_addr_ld(2) ); \save_init_bram_addr_ld[4]_i_2__0\: unisim.vcomponents.LUT4 generic map( INIT => X"A28A" ) port map ( I0 => save_init_bram_addr_ld(4), I1 => wrap_burst_total(0), I2 => wrap_burst_total(2), I3 => wrap_burst_total(1), O => \save_init_bram_addr_ld[4]_i_2__0_n_0\ ); \save_init_bram_addr_ld[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"8F808F8F8F808080" ) port map ( I0 => save_init_bram_addr_ld(5), I1 => \save_init_bram_addr_ld[5]_i_2__0_n_0\, I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\, I3 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\, I4 => axi_awaddr_full, I5 => s_axi_awaddr(3), O => bram_addr_ld(3) ); \save_init_bram_addr_ld[5]_i_2__0\: unisim.vcomponents.LUT3 generic map( INIT => X"FB" ) port map ( I0 => wrap_burst_total(0), I1 => wrap_burst_total(2), I2 => wrap_burst_total(1), O => \save_init_bram_addr_ld[5]_i_2__0_n_0\ ); \save_init_bram_addr_ld[6]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => save_init_bram_addr_ld(6), I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\, I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\, I3 => axi_awaddr_full, I4 => s_axi_awaddr(4), O => bram_addr_ld(4) ); \save_init_bram_addr_ld[7]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => save_init_bram_addr_ld(7), I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\, I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\, I3 => axi_awaddr_full, I4 => s_axi_awaddr(5), O => bram_addr_ld(5) ); \save_init_bram_addr_ld[8]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => save_init_bram_addr_ld(8), I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\, I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\, I3 => axi_awaddr_full, I4 => s_axi_awaddr(6), O => bram_addr_ld(6) ); \save_init_bram_addr_ld[9]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => save_init_bram_addr_ld(9), I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\, I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\, I3 => axi_awaddr_full, I4 => s_axi_awaddr(7), O => bram_addr_ld(7) ); \save_init_bram_addr_ld_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => bram_addr_ld(8), Q => save_init_bram_addr_ld(10), R => s_axi_aresetn_0 ); \save_init_bram_addr_ld_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => bram_addr_ld(9), Q => save_init_bram_addr_ld(11), R => s_axi_aresetn_0 ); \save_init_bram_addr_ld_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \^d\(10), Q => save_init_bram_addr_ld(12), R => s_axi_aresetn_0 ); \save_init_bram_addr_ld_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \^d\(11), Q => save_init_bram_addr_ld(13), R => s_axi_aresetn_0 ); \save_init_bram_addr_ld_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \^d\(12), Q => save_init_bram_addr_ld(14), R => s_axi_aresetn_0 ); \save_init_bram_addr_ld_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \^d\(13), Q => save_init_bram_addr_ld(15), R => s_axi_aresetn_0 ); \save_init_bram_addr_ld_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => bram_addr_ld(1), Q => save_init_bram_addr_ld(3), R => s_axi_aresetn_0 ); \save_init_bram_addr_ld_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => bram_addr_ld(2), Q => save_init_bram_addr_ld(4), R => s_axi_aresetn_0 ); \save_init_bram_addr_ld_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => bram_addr_ld(3), Q => save_init_bram_addr_ld(5), R => s_axi_aresetn_0 ); \save_init_bram_addr_ld_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => bram_addr_ld(4), Q => save_init_bram_addr_ld(6), R => s_axi_aresetn_0 ); \save_init_bram_addr_ld_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => bram_addr_ld(5), Q => save_init_bram_addr_ld(7), R => s_axi_aresetn_0 ); \save_init_bram_addr_ld_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => bram_addr_ld(6), Q => save_init_bram_addr_ld(8), R => s_axi_aresetn_0 ); \save_init_bram_addr_ld_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => bram_addr_ld(7), Q => save_init_bram_addr_ld(9), R => s_axi_aresetn_0 ); \wrap_burst_total[0]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"F909090900000000" ) port map ( I0 => \wrap_burst_total[0]_i_2__0_n_0\, I1 => \^wrap_burst_total_reg[0]_0\, I2 => \wrap_burst_total[0]_i_4__0_n_0\, I3 => Q(1), I4 => Q(2), I5 => \wrap_burst_total[0]_i_5_n_0\, O => \wrap_burst_total[0]_i_1__0_n_0\ ); \wrap_burst_total[0]_i_2__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => Q(2), I1 => axi_awaddr_full, I2 => s_axi_awlen(2), O => \wrap_burst_total[0]_i_2__0_n_0\ ); \wrap_burst_total[0]_i_3__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => Q(1), I1 => axi_awaddr_full, I2 => s_axi_awlen(1), O => \^wrap_burst_total_reg[0]_0\ ); \wrap_burst_total[0]_i_4__0\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => axi_awaddr_full, I1 => axi_awsize_pipe(0), O => \wrap_burst_total[0]_i_4__0_n_0\ ); \wrap_burst_total[0]_i_5\: unisim.vcomponents.LUT5 generic map( INIT => X"000ACC0A" ) port map ( I0 => s_axi_awlen(0), I1 => Q(0), I2 => s_axi_awlen(3), I3 => axi_awaddr_full, I4 => Q(3), O => \wrap_burst_total[0]_i_5_n_0\ ); \wrap_burst_total[1]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"000008F3" ) port map ( I0 => Q(2), I1 => axi_awaddr_full, I2 => axi_awsize_pipe(0), I3 => \^wrap_burst_total_reg[2]_0\, I4 => \wrap_burst_total[2]_i_2__0_n_0\, O => \wrap_burst_total[1]_i_1__0_n_0\ ); \wrap_burst_total[2]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"5000000044004400" ) port map ( I0 => \wrap_burst_total[2]_i_2__0_n_0\, I1 => s_axi_awlen(2), I2 => Q(2), I3 => \^wrap_burst_total_reg[2]_0\, I4 => axi_awsize_pipe(0), I5 => axi_awaddr_full, O => \wrap_burst_total[2]_i_1__0_n_0\ ); \wrap_burst_total[2]_i_2__0\: unisim.vcomponents.LUT5 generic map( INIT => X"335FFF5F" ) port map ( I0 => s_axi_awlen(1), I1 => Q(1), I2 => s_axi_awlen(0), I3 => axi_awaddr_full, I4 => Q(0), O => \wrap_burst_total[2]_i_2__0_n_0\ ); \wrap_burst_total[2]_i_3__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => Q(3), I1 => axi_awaddr_full, I2 => s_axi_awlen(3), O => \^wrap_burst_total_reg[2]_0\ ); \wrap_burst_total_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \wrap_burst_total[0]_i_1__0_n_0\, Q => wrap_burst_total(0), R => s_axi_aresetn_0 ); \wrap_burst_total_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \wrap_burst_total[1]_i_1__0_n_0\, Q => wrap_burst_total(1), R => s_axi_aresetn_0 ); \wrap_burst_total_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \wrap_burst_total[2]_i_1__0_n_0\, Q => wrap_burst_total(2), R => s_axi_aresetn_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst_0 is port ( \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ : out STD_LOGIC; SR : out STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_burst_total_reg[0]_0\ : out STD_LOGIC; \wrap_burst_total_reg[0]_1\ : out STD_LOGIC; \wrap_burst_total_reg[0]_2\ : out STD_LOGIC; \wrap_burst_total_reg[0]_3\ : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 1 downto 0 ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0\ : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 13 downto 0 ); bram_addr_ld_en : out STD_LOGIC; \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ : out STD_LOGIC; \rd_data_sm_cs_reg[1]\ : out STD_LOGIC; \save_init_bram_addr_ld_reg[15]_0\ : out STD_LOGIC; \save_init_bram_addr_ld_reg[15]_1\ : out STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 3 downto 0 ); axi_rvalid_int_reg : in STD_LOGIC; s_axi_rready : in STD_LOGIC; end_brst_rd : in STD_LOGIC; brst_zero : in STD_LOGIC; s_axi_aresetn : in STD_LOGIC; \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); axi_arsize_pipe : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); axi_araddr_full : in STD_LOGIC; curr_fixed_burst_reg : in STD_LOGIC; s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 ); \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\ : in STD_LOGIC; \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\ : in STD_LOGIC; \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\ : in STD_LOGIC; \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\ : in STD_LOGIC; \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\ : in STD_LOGIC; \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\ : in STD_LOGIC; \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\ : in STD_LOGIC; \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\ : in STD_LOGIC; \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\ : in STD_LOGIC; \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\ : in STD_LOGIC; \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ : in STD_LOGIC; \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\ : in STD_LOGIC; \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\ : in STD_LOGIC; \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\ : in STD_LOGIC; \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\ : in STD_LOGIC; \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\ : in STD_LOGIC; curr_wrap_burst_reg : in STD_LOGIC; axi_rd_burst_two_reg : in STD_LOGIC; axi_rd_burst : in STD_LOGIC; axi_aresetn_d2 : in STD_LOGIC; last_bram_addr : in STD_LOGIC; rd_addr_sm_cs : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC; no_ar_ack : in STD_LOGIC; pend_rd_op : in STD_LOGIC; ar_active : in STD_LOGIC; axi_b2b_brst : in STD_LOGIC; axi_arsize_pipe_max : in STD_LOGIC; disable_b2b_brst : in STD_LOGIC; \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\ : in STD_LOGIC; axi_arlen_pipe_1_or_2 : in STD_LOGIC; s_axi_aclk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst_0 : entity is "wrap_brst"; end zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst_0; architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst_0 is signal \^d\ : STD_LOGIC_VECTOR ( 13 downto 0 ); signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0\ : STD_LOGIC; signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0\ : STD_LOGIC; signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\ : STD_LOGIC; signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\ : STD_LOGIC; signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0\ : STD_LOGIC; signal \^gen_dual_addr_cnt.bram_addr_int_reg[11]\ : STD_LOGIC; signal \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\ : STD_LOGIC; signal \^gen_dual_addr_cnt.bram_addr_int_reg[6]\ : STD_LOGIC; signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^bram_addr_ld_en\ : STD_LOGIC; signal \^rd_data_sm_cs_reg[1]\ : STD_LOGIC; signal \save_init_bram_addr_ld[10]_i_1__0_n_0\ : STD_LOGIC; signal \save_init_bram_addr_ld[11]_i_1__0_n_0\ : STD_LOGIC; signal \save_init_bram_addr_ld[15]_i_2__0_n_0\ : STD_LOGIC; signal \save_init_bram_addr_ld[15]_i_3__0_n_0\ : STD_LOGIC; signal \save_init_bram_addr_ld[3]_i_1__0_n_0\ : STD_LOGIC; signal \save_init_bram_addr_ld[3]_i_2_n_0\ : STD_LOGIC; signal \save_init_bram_addr_ld[4]_i_1__0_n_0\ : STD_LOGIC; signal \save_init_bram_addr_ld[4]_i_2_n_0\ : STD_LOGIC; signal \save_init_bram_addr_ld[5]_i_1__0_n_0\ : STD_LOGIC; signal \save_init_bram_addr_ld[5]_i_2_n_0\ : STD_LOGIC; signal \save_init_bram_addr_ld[6]_i_1__0_n_0\ : STD_LOGIC; signal \save_init_bram_addr_ld[7]_i_1__0_n_0\ : STD_LOGIC; signal \save_init_bram_addr_ld[8]_i_1__0_n_0\ : STD_LOGIC; signal \save_init_bram_addr_ld[9]_i_1__0_n_0\ : STD_LOGIC; signal \^save_init_bram_addr_ld_reg[15]_0\ : STD_LOGIC; signal \^save_init_bram_addr_ld_reg[15]_1\ : STD_LOGIC; signal \save_init_bram_addr_ld_reg_n_0_[10]\ : STD_LOGIC; signal \save_init_bram_addr_ld_reg_n_0_[11]\ : STD_LOGIC; signal \save_init_bram_addr_ld_reg_n_0_[12]\ : STD_LOGIC; signal \save_init_bram_addr_ld_reg_n_0_[13]\ : STD_LOGIC; signal \save_init_bram_addr_ld_reg_n_0_[14]\ : STD_LOGIC; signal \save_init_bram_addr_ld_reg_n_0_[15]\ : STD_LOGIC; signal \save_init_bram_addr_ld_reg_n_0_[3]\ : STD_LOGIC; signal \save_init_bram_addr_ld_reg_n_0_[4]\ : STD_LOGIC; signal \save_init_bram_addr_ld_reg_n_0_[5]\ : STD_LOGIC; signal \save_init_bram_addr_ld_reg_n_0_[6]\ : STD_LOGIC; signal \save_init_bram_addr_ld_reg_n_0_[7]\ : STD_LOGIC; signal \save_init_bram_addr_ld_reg_n_0_[8]\ : STD_LOGIC; signal \save_init_bram_addr_ld_reg_n_0_[9]\ : STD_LOGIC; signal \wrap_burst_total[0]_i_1_n_0\ : STD_LOGIC; signal \wrap_burst_total[0]_i_5__0_n_0\ : STD_LOGIC; signal \wrap_burst_total[1]_i_1_n_0\ : STD_LOGIC; signal \wrap_burst_total[2]_i_1_n_0\ : STD_LOGIC; signal \wrap_burst_total[2]_i_2_n_0\ : STD_LOGIC; signal \^wrap_burst_total_reg[0]_0\ : STD_LOGIC; signal \^wrap_burst_total_reg[0]_1\ : STD_LOGIC; signal \^wrap_burst_total_reg[0]_2\ : STD_LOGIC; signal \^wrap_burst_total_reg[0]_3\ : STD_LOGIC; signal \wrap_burst_total_reg_n_0_[0]\ : STD_LOGIC; signal \wrap_burst_total_reg_n_0_[1]\ : STD_LOGIC; signal \wrap_burst_total_reg_n_0_[2]\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1__0\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \save_init_bram_addr_ld[15]_i_4__0\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \save_init_bram_addr_ld[3]_i_2\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \save_init_bram_addr_ld[5]_i_2\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_2\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_3\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_4\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_5__0\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_2\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_3\ : label is "soft_lutpair4"; begin D(13 downto 0) <= \^d\(13 downto 0); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[11]\; \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\; \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[6]\; SR(0) <= \^sr\(0); bram_addr_ld_en <= \^bram_addr_ld_en\; \rd_data_sm_cs_reg[1]\ <= \^rd_data_sm_cs_reg[1]\; \save_init_bram_addr_ld_reg[15]_0\ <= \^save_init_bram_addr_ld_reg[15]_0\; \save_init_bram_addr_ld_reg[15]_1\ <= \^save_init_bram_addr_ld_reg[15]_1\; \wrap_burst_total_reg[0]_0\ <= \^wrap_burst_total_reg[0]_0\; \wrap_burst_total_reg[0]_1\ <= \^wrap_burst_total_reg[0]_1\; \wrap_burst_total_reg[0]_2\ <= \^wrap_burst_total_reg[0]_2\; \wrap_burst_total_reg[0]_3\ <= \^wrap_burst_total_reg[0]_3\; \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"DF20FFFFDF200000" ) port map ( I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(6), I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\, I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(7), I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(8), I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\, I5 => \save_init_bram_addr_ld[10]_i_1__0_n_0\, O => \^d\(8) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"5D" ) port map ( I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\, I1 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\, I2 => curr_fixed_burst_reg, O => E(0) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_2__0\: unisim.vcomponents.LUT5 generic map( INIT => X"9AFF9A00" ) port map ( I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(9), I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\, I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(8), I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\, I4 => \save_init_bram_addr_ld[11]_i_1__0_n_0\, O => \^d\(9) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"E0F0E0FFE0F0E0F0" ) port map ( I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0\, I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0\, I2 => \^rd_data_sm_cs_reg[1]\, I3 => Q(1), I4 => Q(3), I5 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\, O => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\ ); \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => axi_rd_burst_two_reg, I1 => Q(0), O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0\ ); \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"0D00000000000000" ) port map ( I0 => end_brst_rd, I1 => axi_b2b_brst, I2 => brst_zero, I3 => axi_rvalid_int_reg, I4 => s_axi_rready, I5 => Q(0), O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0\ ); \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \save_init_bram_addr_ld_reg_n_0_[12]\, I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\, I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\, I3 => axi_araddr_full, I4 => s_axi_araddr(10), O => \^d\(10) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[13]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \save_init_bram_addr_ld_reg_n_0_[13]\, I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\, I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\, I3 => axi_araddr_full, I4 => s_axi_araddr(11), O => \^d\(11) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[14]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \save_init_bram_addr_ld_reg_n_0_[14]\, I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\, I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\, I3 => axi_araddr_full, I4 => s_axi_araddr(12), O => \^d\(12) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\, O => E(1) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_2__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \save_init_bram_addr_ld_reg_n_0_[15]\, I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\, I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\, I3 => axi_araddr_full, I4 => s_axi_araddr(13), O => \^d\(13) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \^bram_addr_ld_en\, I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\, O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\ ); \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0\: unisim.vcomponents.LUT5 generic map( INIT => X"88A80000" ) port map ( I0 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\, I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0\, I2 => \save_init_bram_addr_ld[5]_i_2_n_0\, I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\, I4 => curr_wrap_burst_reg, O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\ ); \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0\: unisim.vcomponents.LUT6 generic map( INIT => X"000000008F00A000" ) port map ( I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1), I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2), I2 => \wrap_burst_total_reg_n_0_[1]\, I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0), I4 => \wrap_burst_total_reg_n_0_[0]\, I5 => \wrap_burst_total_reg_n_0_[2]\, O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0\ ); \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"00000000A808FD5D" ) port map ( I0 => \^bram_addr_ld_en\, I1 => s_axi_araddr(0), I2 => axi_araddr_full, I3 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\, I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0), I5 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\, O => \^d\(0) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[3]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"6F60" ) port map ( I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1), I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0), I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\, I3 => \save_init_bram_addr_ld[3]_i_1__0_n_0\, O => \^d\(1) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"6AFF6A00" ) port map ( I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2), I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0), I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1), I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\, I4 => \save_init_bram_addr_ld[4]_i_1__0_n_0\, O => \^d\(2) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[5]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"6AAAFFFF6AAA0000" ) port map ( I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(3), I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2), I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0), I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1), I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\, I5 => \save_init_bram_addr_ld[5]_i_1__0_n_0\, O => \^d\(3) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[6]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"9F90" ) port map ( I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(4), I1 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\, I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\, I3 => \save_init_bram_addr_ld[6]_i_1__0_n_0\, O => \^d\(4) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[7]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"9AFF9A00" ) port map ( I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(5), I1 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\, I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(4), I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\, I4 => \save_init_bram_addr_ld[7]_i_1__0_n_0\, O => \^d\(5) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"A6AAFFFFA6AA0000" ) port map ( I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(6), I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(4), I2 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\, I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(5), I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\, I5 => \save_init_bram_addr_ld[8]_i_1__0_n_0\, O => \^d\(6) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"7FFF" ) port map ( I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1), I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0), I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2), I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(3), O => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\ ); \GEN_DUAL_ADDR_CNT.bram_addr_int[9]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"9AFF9A00" ) port map ( I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(7), I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\, I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(6), I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\, I4 => \save_init_bram_addr_ld[9]_i_1__0_n_0\, O => \^d\(7) ); bram_en_int_i_8: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000004000" ) port map ( I0 => Q(0), I1 => Q(2), I2 => axi_rvalid_int_reg, I3 => s_axi_rready, I4 => end_brst_rd, I5 => brst_zero, O => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\ ); bram_rst_b_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => s_axi_aresetn, O => \^sr\(0) ); \rd_data_sm_cs[1]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"0302030203020300" ) port map ( I0 => Q(0), I1 => Q(3), I2 => Q(2), I3 => Q(1), I4 => axi_rd_burst_two_reg, I5 => axi_rd_burst, O => \^rd_data_sm_cs_reg[1]\ ); \save_init_bram_addr_ld[10]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \save_init_bram_addr_ld_reg_n_0_[10]\, I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\, I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\, I3 => axi_araddr_full, I4 => s_axi_araddr(8), O => \save_init_bram_addr_ld[10]_i_1__0_n_0\ ); \save_init_bram_addr_ld[11]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \save_init_bram_addr_ld_reg_n_0_[11]\, I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\, I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\, I3 => axi_araddr_full, I4 => s_axi_araddr(9), O => \save_init_bram_addr_ld[11]_i_1__0_n_0\ ); \save_init_bram_addr_ld[15]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"8888888A88888888" ) port map ( I0 => axi_aresetn_d2, I1 => \save_init_bram_addr_ld[15]_i_2__0_n_0\, I2 => \save_init_bram_addr_ld[15]_i_3__0_n_0\, I3 => \^save_init_bram_addr_ld_reg[15]_0\, I4 => \^save_init_bram_addr_ld_reg[15]_1\, I5 => last_bram_addr, O => \^bram_addr_ld_en\ ); \save_init_bram_addr_ld[15]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000054" ) port map ( I0 => rd_addr_sm_cs, I1 => axi_araddr_full, I2 => s_axi_arvalid, I3 => no_ar_ack, I4 => pend_rd_op, I5 => ar_active, O => \save_init_bram_addr_ld[15]_i_2__0_n_0\ ); \save_init_bram_addr_ld[15]_i_3__0\: unisim.vcomponents.LUT3 generic map( INIT => X"2A" ) port map ( I0 => brst_zero, I1 => s_axi_rready, I2 => axi_rvalid_int_reg, O => \save_init_bram_addr_ld[15]_i_3__0_n_0\ ); \save_init_bram_addr_ld[15]_i_4__0\: unisim.vcomponents.LUT4 generic map( INIT => X"0040" ) port map ( I0 => Q(3), I1 => Q(2), I2 => Q(1), I3 => Q(0), O => \^save_init_bram_addr_ld_reg[15]_0\ ); \save_init_bram_addr_ld[15]_i_5\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFDFFFF" ) port map ( I0 => axi_arsize_pipe_max, I1 => disable_b2b_brst, I2 => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\, I3 => axi_arlen_pipe_1_or_2, I4 => axi_araddr_full, O => \^save_init_bram_addr_ld_reg[15]_1\ ); \save_init_bram_addr_ld[3]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \save_init_bram_addr_ld[3]_i_2_n_0\, I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\, I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\, I3 => axi_araddr_full, I4 => s_axi_araddr(1), O => \save_init_bram_addr_ld[3]_i_1__0_n_0\ ); \save_init_bram_addr_ld[3]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"A282" ) port map ( I0 => \save_init_bram_addr_ld_reg_n_0_[3]\, I1 => \wrap_burst_total_reg_n_0_[1]\, I2 => \wrap_burst_total_reg_n_0_[2]\, I3 => \wrap_burst_total_reg_n_0_[0]\, O => \save_init_bram_addr_ld[3]_i_2_n_0\ ); \save_init_bram_addr_ld[4]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \save_init_bram_addr_ld[4]_i_2_n_0\, I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\, I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\, I3 => axi_araddr_full, I4 => s_axi_araddr(2), O => \save_init_bram_addr_ld[4]_i_1__0_n_0\ ); \save_init_bram_addr_ld[4]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"A28A" ) port map ( I0 => \save_init_bram_addr_ld_reg_n_0_[4]\, I1 => \wrap_burst_total_reg_n_0_[0]\, I2 => \wrap_burst_total_reg_n_0_[2]\, I3 => \wrap_burst_total_reg_n_0_[1]\, O => \save_init_bram_addr_ld[4]_i_2_n_0\ ); \save_init_bram_addr_ld[5]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"2F202F2F2F202020" ) port map ( I0 => \save_init_bram_addr_ld_reg_n_0_[5]\, I1 => \save_init_bram_addr_ld[5]_i_2_n_0\, I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\, I3 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\, I4 => axi_araddr_full, I5 => s_axi_araddr(3), O => \save_init_bram_addr_ld[5]_i_1__0_n_0\ ); \save_init_bram_addr_ld[5]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"04" ) port map ( I0 => \wrap_burst_total_reg_n_0_[0]\, I1 => \wrap_burst_total_reg_n_0_[2]\, I2 => \wrap_burst_total_reg_n_0_[1]\, O => \save_init_bram_addr_ld[5]_i_2_n_0\ ); \save_init_bram_addr_ld[6]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \save_init_bram_addr_ld_reg_n_0_[6]\, I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\, I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\, I3 => axi_araddr_full, I4 => s_axi_araddr(4), O => \save_init_bram_addr_ld[6]_i_1__0_n_0\ ); \save_init_bram_addr_ld[7]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \save_init_bram_addr_ld_reg_n_0_[7]\, I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\, I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\, I3 => axi_araddr_full, I4 => s_axi_araddr(5), O => \save_init_bram_addr_ld[7]_i_1__0_n_0\ ); \save_init_bram_addr_ld[8]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \save_init_bram_addr_ld_reg_n_0_[8]\, I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\, I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\, I3 => axi_araddr_full, I4 => s_axi_araddr(6), O => \save_init_bram_addr_ld[8]_i_1__0_n_0\ ); \save_init_bram_addr_ld[9]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \save_init_bram_addr_ld_reg_n_0_[9]\, I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\, I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\, I3 => axi_araddr_full, I4 => s_axi_araddr(7), O => \save_init_bram_addr_ld[9]_i_1__0_n_0\ ); \save_init_bram_addr_ld_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \save_init_bram_addr_ld[10]_i_1__0_n_0\, Q => \save_init_bram_addr_ld_reg_n_0_[10]\, R => \^sr\(0) ); \save_init_bram_addr_ld_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \save_init_bram_addr_ld[11]_i_1__0_n_0\, Q => \save_init_bram_addr_ld_reg_n_0_[11]\, R => \^sr\(0) ); \save_init_bram_addr_ld_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \^d\(10), Q => \save_init_bram_addr_ld_reg_n_0_[12]\, R => \^sr\(0) ); \save_init_bram_addr_ld_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \^d\(11), Q => \save_init_bram_addr_ld_reg_n_0_[13]\, R => \^sr\(0) ); \save_init_bram_addr_ld_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \^d\(12), Q => \save_init_bram_addr_ld_reg_n_0_[14]\, R => \^sr\(0) ); \save_init_bram_addr_ld_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \^d\(13), Q => \save_init_bram_addr_ld_reg_n_0_[15]\, R => \^sr\(0) ); \save_init_bram_addr_ld_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \save_init_bram_addr_ld[3]_i_1__0_n_0\, Q => \save_init_bram_addr_ld_reg_n_0_[3]\, R => \^sr\(0) ); \save_init_bram_addr_ld_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \save_init_bram_addr_ld[4]_i_1__0_n_0\, Q => \save_init_bram_addr_ld_reg_n_0_[4]\, R => \^sr\(0) ); \save_init_bram_addr_ld_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \save_init_bram_addr_ld[5]_i_1__0_n_0\, Q => \save_init_bram_addr_ld_reg_n_0_[5]\, R => \^sr\(0) ); \save_init_bram_addr_ld_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \save_init_bram_addr_ld[6]_i_1__0_n_0\, Q => \save_init_bram_addr_ld_reg_n_0_[6]\, R => \^sr\(0) ); \save_init_bram_addr_ld_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \save_init_bram_addr_ld[7]_i_1__0_n_0\, Q => \save_init_bram_addr_ld_reg_n_0_[7]\, R => \^sr\(0) ); \save_init_bram_addr_ld_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \save_init_bram_addr_ld[8]_i_1__0_n_0\, Q => \save_init_bram_addr_ld_reg_n_0_[8]\, R => \^sr\(0) ); \save_init_bram_addr_ld_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \save_init_bram_addr_ld[9]_i_1__0_n_0\, Q => \save_init_bram_addr_ld_reg_n_0_[9]\, R => \^sr\(0) ); \wrap_burst_total[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"00000000A000C300" ) port map ( I0 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(2), I1 => \^wrap_burst_total_reg[0]_0\, I2 => \^wrap_burst_total_reg[0]_1\, I3 => \^wrap_burst_total_reg[0]_2\, I4 => \wrap_burst_total[0]_i_5__0_n_0\, I5 => \^wrap_burst_total_reg[0]_3\, O => \wrap_burst_total[0]_i_1_n_0\ ); \wrap_burst_total[0]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(2), I1 => axi_araddr_full, I2 => s_axi_arlen(2), O => \^wrap_burst_total_reg[0]_0\ ); \wrap_burst_total[0]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(1), I1 => axi_araddr_full, I2 => s_axi_arlen(1), O => \^wrap_burst_total_reg[0]_1\ ); \wrap_burst_total[0]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(0), I1 => axi_araddr_full, I2 => s_axi_arlen(0), O => \^wrap_burst_total_reg[0]_2\ ); \wrap_burst_total[0]_i_5__0\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => axi_araddr_full, I1 => axi_arsize_pipe(0), O => \wrap_burst_total[0]_i_5__0_n_0\ ); \wrap_burst_total[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"220A880A000A880A" ) port map ( I0 => \wrap_burst_total[2]_i_2_n_0\, I1 => axi_arsize_pipe(0), I2 => s_axi_arlen(3), I3 => axi_araddr_full, I4 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(3), I5 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(2), O => \wrap_burst_total[1]_i_1_n_0\ ); \wrap_burst_total[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"A000888800000000" ) port map ( I0 => \wrap_burst_total[2]_i_2_n_0\, I1 => s_axi_arlen(2), I2 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(2), I3 => axi_arsize_pipe(0), I4 => axi_araddr_full, I5 => \^wrap_burst_total_reg[0]_3\, O => \wrap_burst_total[2]_i_1_n_0\ ); \wrap_burst_total[2]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"CCA000A0" ) port map ( I0 => s_axi_arlen(1), I1 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(1), I2 => s_axi_arlen(0), I3 => axi_araddr_full, I4 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(0), O => \wrap_burst_total[2]_i_2_n_0\ ); \wrap_burst_total[2]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(3), I1 => axi_araddr_full, I2 => s_axi_arlen(3), O => \^wrap_burst_total_reg[0]_3\ ); \wrap_burst_total_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \wrap_burst_total[0]_i_1_n_0\, Q => \wrap_burst_total_reg_n_0_[0]\, R => \^sr\(0) ); \wrap_burst_total_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \wrap_burst_total[1]_i_1_n_0\, Q => \wrap_burst_total_reg_n_0_[1]\, R => \^sr\(0) ); \wrap_burst_total_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \wrap_burst_total[2]_i_1_n_0\, Q => \wrap_burst_total_reg_n_0_[2]\, R => \^sr\(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zqynq_lab_1_design_axi_bram_ctrl_0_0_rd_chnl is port ( bram_rst_a : out STD_LOGIC; s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 ); bram_en_b : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 13 downto 0 ); s_axi_arready : out STD_LOGIC; s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 ); s_axi_aclk : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 ); \GEN_AWREADY.axi_aresetn_d2_reg\ : in STD_LOGIC; s_axi_aresetn : in STD_LOGIC; s_axi_rready : in STD_LOGIC; s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); axi_aresetn_d2 : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC; axi_aresetn_re_reg : in STD_LOGIC; s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_bram_ctrl_0_0_rd_chnl : entity is "rd_chnl"; end zqynq_lab_1_design_axi_bram_ctrl_0_0_rd_chnl; architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0_rd_chnl is signal \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0\ : STD_LOGIC; signal \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0\ : STD_LOGIC; signal \/i__n_0\ : STD_LOGIC; signal \FSM_sequential_rlast_sm_cs[0]_i_1_n_0\ : STD_LOGIC; signal \FSM_sequential_rlast_sm_cs[1]_i_1_n_0\ : STD_LOGIC; signal \FSM_sequential_rlast_sm_cs[2]_i_1_n_0\ : STD_LOGIC; signal \GEN_ARREADY.axi_arready_int_i_1_n_0\ : STD_LOGIC; signal \GEN_ARREADY.axi_early_arready_int_i_2_n_0\ : STD_LOGIC; signal \GEN_ARREADY.axi_early_arready_int_i_3_n_0\ : STD_LOGIC; signal \GEN_ARREADY.axi_early_arready_int_i_4_n_0\ : STD_LOGIC; signal \GEN_AR_DUAL.ar_active_i_1_n_0\ : STD_LOGIC; signal \GEN_AR_DUAL.ar_active_i_2_n_0\ : STD_LOGIC; signal \GEN_AR_DUAL.ar_active_i_3_n_0\ : STD_LOGIC; signal \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0\ : STD_LOGIC; signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\ : STD_LOGIC; signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\ : STD_LOGIC; signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\ : STD_LOGIC; signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\ : STD_LOGIC; signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\ : STD_LOGIC; signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\ : STD_LOGIC; signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\ : STD_LOGIC; signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\ : STD_LOGIC; signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\ : STD_LOGIC; signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\ : STD_LOGIC; signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\ : STD_LOGIC; signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\ : STD_LOGIC; signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\ : STD_LOGIC; signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\ : STD_LOGIC; signal \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0\ : STD_LOGIC; signal \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0\ : STD_LOGIC; signal \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\ : STD_LOGIC; signal \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\ : STD_LOGIC; signal \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\ : STD_LOGIC; signal \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0\ : STD_LOGIC; signal \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0\ : STD_LOGIC; signal \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0\ : STD_LOGIC; signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\ : STD_LOGIC; signal \GEN_RID.axi_rid_int[0]_i_1_n_0\ : STD_LOGIC; signal \GEN_RID.axi_rid_int[0]_i_2_n_0\ : STD_LOGIC; signal \GEN_RID.axi_rid_temp2[0]_i_1_n_0\ : STD_LOGIC; signal \GEN_RID.axi_rid_temp2_full_i_1_n_0\ : STD_LOGIC; signal \GEN_RID.axi_rid_temp2_reg_n_0_[0]\ : STD_LOGIC; signal \GEN_RID.axi_rid_temp[0]_i_1_n_0\ : STD_LOGIC; signal \GEN_RID.axi_rid_temp[0]_i_3_n_0\ : STD_LOGIC; signal \GEN_RID.axi_rid_temp_full_i_1_n_0\ : STD_LOGIC; signal I_WRAP_BRST_n_0 : STD_LOGIC; signal I_WRAP_BRST_n_10 : STD_LOGIC; signal I_WRAP_BRST_n_11 : STD_LOGIC; signal I_WRAP_BRST_n_12 : STD_LOGIC; signal I_WRAP_BRST_n_13 : STD_LOGIC; signal I_WRAP_BRST_n_14 : STD_LOGIC; signal I_WRAP_BRST_n_15 : STD_LOGIC; signal I_WRAP_BRST_n_16 : STD_LOGIC; signal I_WRAP_BRST_n_17 : STD_LOGIC; signal I_WRAP_BRST_n_18 : STD_LOGIC; signal I_WRAP_BRST_n_19 : STD_LOGIC; signal I_WRAP_BRST_n_2 : STD_LOGIC; signal I_WRAP_BRST_n_20 : STD_LOGIC; signal I_WRAP_BRST_n_21 : STD_LOGIC; signal I_WRAP_BRST_n_22 : STD_LOGIC; signal I_WRAP_BRST_n_24 : STD_LOGIC; signal I_WRAP_BRST_n_25 : STD_LOGIC; signal I_WRAP_BRST_n_26 : STD_LOGIC; signal I_WRAP_BRST_n_27 : STD_LOGIC; signal I_WRAP_BRST_n_3 : STD_LOGIC; signal I_WRAP_BRST_n_4 : STD_LOGIC; signal I_WRAP_BRST_n_5 : STD_LOGIC; signal I_WRAP_BRST_n_7 : STD_LOGIC; signal I_WRAP_BRST_n_8 : STD_LOGIC; signal I_WRAP_BRST_n_9 : STD_LOGIC; signal \^q\ : STD_LOGIC_VECTOR ( 13 downto 0 ); signal act_rd_burst : STD_LOGIC; signal act_rd_burst_i_1_n_0 : STD_LOGIC; signal act_rd_burst_i_3_n_0 : STD_LOGIC; signal act_rd_burst_i_4_n_0 : STD_LOGIC; signal act_rd_burst_i_5_n_0 : STD_LOGIC; signal act_rd_burst_set : STD_LOGIC; signal act_rd_burst_two : STD_LOGIC; signal act_rd_burst_two_i_1_n_0 : STD_LOGIC; signal ar_active : STD_LOGIC; signal araddr_pipe_ld43_out : STD_LOGIC; signal axi_araddr_full : STD_LOGIC; signal axi_arburst_pipe : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_arid_pipe : STD_LOGIC; signal axi_arlen_pipe : STD_LOGIC_VECTOR ( 7 downto 0 ); signal axi_arlen_pipe_1_or_2 : STD_LOGIC; signal axi_arready_int : STD_LOGIC; signal axi_arsize_pipe : STD_LOGIC_VECTOR ( 1 to 1 ); signal axi_arsize_pipe_max : STD_LOGIC; signal axi_arsize_pipe_max_i_1_n_0 : STD_LOGIC; signal axi_b2b_brst : STD_LOGIC; signal axi_b2b_brst_i_1_n_0 : STD_LOGIC; signal axi_b2b_brst_i_2_n_0 : STD_LOGIC; signal axi_early_arready_int : STD_LOGIC; signal axi_rd_burst : STD_LOGIC; signal axi_rd_burst_i_1_n_0 : STD_LOGIC; signal axi_rd_burst_i_2_n_0 : STD_LOGIC; signal axi_rd_burst_i_3_n_0 : STD_LOGIC; signal axi_rd_burst_two : STD_LOGIC; signal axi_rd_burst_two_i_1_n_0 : STD_LOGIC; signal axi_rd_burst_two_reg_n_0 : STD_LOGIC; signal axi_rid_temp : STD_LOGIC; signal axi_rid_temp2 : STD_LOGIC; signal axi_rid_temp2_full : STD_LOGIC; signal axi_rid_temp_full : STD_LOGIC; signal axi_rid_temp_full_d1 : STD_LOGIC; signal axi_rlast_int_i_1_n_0 : STD_LOGIC; signal axi_rlast_set : STD_LOGIC; signal axi_rvalid_clr_ok : STD_LOGIC; signal axi_rvalid_clr_ok_i_1_n_0 : STD_LOGIC; signal axi_rvalid_clr_ok_i_2_n_0 : STD_LOGIC; signal axi_rvalid_clr_ok_i_3_n_0 : STD_LOGIC; signal axi_rvalid_int_i_1_n_0 : STD_LOGIC; signal axi_rvalid_set : STD_LOGIC; signal axi_rvalid_set_cmb : STD_LOGIC; signal bram_addr_ld_en : STD_LOGIC; signal bram_addr_ld_en_mod : STD_LOGIC; signal \^bram_en_b\ : STD_LOGIC; signal bram_en_int_i_10_n_0 : STD_LOGIC; signal bram_en_int_i_11_n_0 : STD_LOGIC; signal bram_en_int_i_12_n_0 : STD_LOGIC; signal bram_en_int_i_13_n_0 : STD_LOGIC; signal bram_en_int_i_1_n_0 : STD_LOGIC; signal bram_en_int_i_2_n_0 : STD_LOGIC; signal bram_en_int_i_3_n_0 : STD_LOGIC; signal bram_en_int_i_4_n_0 : STD_LOGIC; signal bram_en_int_i_5_n_0 : STD_LOGIC; signal bram_en_int_i_6_n_0 : STD_LOGIC; signal bram_en_int_i_7_n_0 : STD_LOGIC; signal bram_en_int_i_9_n_0 : STD_LOGIC; signal \^bram_rst_a\ : STD_LOGIC; signal brst_cnt : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \brst_cnt[0]_i_1_n_0\ : STD_LOGIC; signal \brst_cnt[1]_i_1_n_0\ : STD_LOGIC; signal \brst_cnt[2]_i_1_n_0\ : STD_LOGIC; signal \brst_cnt[3]_i_1_n_0\ : STD_LOGIC; signal \brst_cnt[4]_i_1_n_0\ : STD_LOGIC; signal \brst_cnt[4]_i_2_n_0\ : STD_LOGIC; signal \brst_cnt[5]_i_1_n_0\ : STD_LOGIC; signal \brst_cnt[6]_i_1_n_0\ : STD_LOGIC; signal \brst_cnt[6]_i_2_n_0\ : STD_LOGIC; signal \brst_cnt[7]_i_1_n_0\ : STD_LOGIC; signal \brst_cnt[7]_i_2_n_0\ : STD_LOGIC; signal \brst_cnt[7]_i_3_n_0\ : STD_LOGIC; signal \brst_cnt[7]_i_4_n_0\ : STD_LOGIC; signal brst_cnt_max : STD_LOGIC; signal brst_cnt_max_d1 : STD_LOGIC; signal brst_one : STD_LOGIC; signal brst_one_i_1_n_0 : STD_LOGIC; signal brst_one_i_2_n_0 : STD_LOGIC; signal brst_zero : STD_LOGIC; signal brst_zero_i_1_n_0 : STD_LOGIC; signal brst_zero_i_2_n_0 : STD_LOGIC; signal curr_fixed_burst : STD_LOGIC; signal curr_fixed_burst_reg : STD_LOGIC; signal curr_wrap_burst : STD_LOGIC; signal curr_wrap_burst_reg : STD_LOGIC; signal disable_b2b_brst : STD_LOGIC; signal disable_b2b_brst_cmb : STD_LOGIC; signal disable_b2b_brst_i_2_n_0 : STD_LOGIC; signal disable_b2b_brst_i_3_n_0 : STD_LOGIC; signal disable_b2b_brst_i_4_n_0 : STD_LOGIC; signal end_brst_rd : STD_LOGIC; signal end_brst_rd_clr : STD_LOGIC; signal end_brst_rd_clr_i_1_n_0 : STD_LOGIC; signal end_brst_rd_i_1_n_0 : STD_LOGIC; signal last_bram_addr : STD_LOGIC; signal last_bram_addr0 : STD_LOGIC; signal last_bram_addr_i_2_n_0 : STD_LOGIC; signal last_bram_addr_i_3_n_0 : STD_LOGIC; signal last_bram_addr_i_4_n_0 : STD_LOGIC; signal last_bram_addr_i_5_n_0 : STD_LOGIC; signal last_bram_addr_i_6_n_0 : STD_LOGIC; signal last_bram_addr_i_7_n_0 : STD_LOGIC; signal last_bram_addr_i_8_n_0 : STD_LOGIC; signal last_bram_addr_i_9_n_0 : STD_LOGIC; signal no_ar_ack : STD_LOGIC; signal no_ar_ack_i_1_n_0 : STD_LOGIC; signal p_0_in13_in : STD_LOGIC; signal p_13_out : STD_LOGIC; signal p_48_out : STD_LOGIC; signal p_4_out : STD_LOGIC; signal p_9_out : STD_LOGIC; signal pend_rd_op : STD_LOGIC; signal pend_rd_op_i_1_n_0 : STD_LOGIC; signal pend_rd_op_i_2_n_0 : STD_LOGIC; signal pend_rd_op_i_3_n_0 : STD_LOGIC; signal pend_rd_op_i_4_n_0 : STD_LOGIC; signal pend_rd_op_i_5_n_0 : STD_LOGIC; signal pend_rd_op_i_6_n_0 : STD_LOGIC; signal pend_rd_op_i_7_n_0 : STD_LOGIC; signal pend_rd_op_i_8_n_0 : STD_LOGIC; signal rd_addr_sm_cs : STD_LOGIC; signal rd_adv_buf67_out : STD_LOGIC; signal rd_data_sm_cs : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \rd_data_sm_cs[0]_i_1_n_0\ : STD_LOGIC; signal \rd_data_sm_cs[0]_i_2_n_0\ : STD_LOGIC; signal \rd_data_sm_cs[0]_i_3_n_0\ : STD_LOGIC; signal \rd_data_sm_cs[0]_i_4_n_0\ : STD_LOGIC; signal \rd_data_sm_cs[1]_i_1_n_0\ : STD_LOGIC; signal \rd_data_sm_cs[1]_i_2_n_0\ : STD_LOGIC; signal \rd_data_sm_cs[2]_i_1_n_0\ : STD_LOGIC; signal \rd_data_sm_cs[2]_i_2_n_0\ : STD_LOGIC; signal \rd_data_sm_cs[2]_i_3_n_0\ : STD_LOGIC; signal \rd_data_sm_cs[2]_i_4_n_0\ : STD_LOGIC; signal \rd_data_sm_cs[2]_i_5_n_0\ : STD_LOGIC; signal \rd_data_sm_cs[3]_i_2_n_0\ : STD_LOGIC; signal \rd_data_sm_cs[3]_i_3_n_0\ : STD_LOGIC; signal \rd_data_sm_cs[3]_i_4_n_0\ : STD_LOGIC; signal \rd_data_sm_cs[3]_i_5_n_0\ : STD_LOGIC; signal \rd_data_sm_cs[3]_i_6_n_0\ : STD_LOGIC; signal \rd_data_sm_cs[3]_i_7_n_0\ : STD_LOGIC; signal rd_data_sm_ns : STD_LOGIC; signal rd_skid_buf : STD_LOGIC_VECTOR ( 31 downto 0 ); signal rd_skid_buf_ld : STD_LOGIC; signal rd_skid_buf_ld_cmb : STD_LOGIC; signal rd_skid_buf_ld_reg : STD_LOGIC; signal rddata_mux_sel : STD_LOGIC; signal rddata_mux_sel_cmb : STD_LOGIC; signal rddata_mux_sel_i_1_n_0 : STD_LOGIC; signal rddata_mux_sel_i_3_n_0 : STD_LOGIC; signal rlast_sm_cs : STD_LOGIC_VECTOR ( 2 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of rlast_sm_cs : signal is "yes"; signal \^s_axi_rid\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^s_axi_rlast\ : STD_LOGIC; signal \^s_axi_rvalid\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \FSM_sequential_rlast_sm_cs[2]_i_2\ : label is "soft_lutpair14"; attribute KEEP : string; attribute KEEP of \FSM_sequential_rlast_sm_cs_reg[0]\ : label is "yes"; attribute KEEP of \FSM_sequential_rlast_sm_cs_reg[1]\ : label is "yes"; attribute KEEP of \FSM_sequential_rlast_sm_cs_reg[2]\ : label is "yes"; attribute SOFT_HLUTNM of \GEN_ARREADY.axi_arready_int_i_1\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \GEN_ARREADY.axi_early_arready_int_i_3\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \GEN_AR_DUAL.ar_active_i_3\ : label is "soft_lutpair15"; attribute SOFT_HLUTNM of \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3\ : label is "soft_lutpair27"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1\ : label is "soft_lutpair23"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1\ : label is "soft_lutpair32"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1\ : label is "soft_lutpair29"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1\ : label is "soft_lutpair34"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1\ : label is "soft_lutpair34"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1\ : label is "soft_lutpair35"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1\ : label is "soft_lutpair36"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1\ : label is "soft_lutpair37"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1\ : label is "soft_lutpair38"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1\ : label is "soft_lutpair37"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1\ : label is "soft_lutpair38"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1\ : label is "soft_lutpair25"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1\ : label is "soft_lutpair39"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1\ : label is "soft_lutpair40"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1\ : label is "soft_lutpair41"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1\ : label is "soft_lutpair42"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1\ : label is "soft_lutpair42"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1\ : label is "soft_lutpair41"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1\ : label is "soft_lutpair40"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1\ : label is "soft_lutpair39"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1\ : label is "soft_lutpair36"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1\ : label is "soft_lutpair35"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1\ : label is "soft_lutpair23"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1\ : label is "soft_lutpair30"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3\ : label is "soft_lutpair33"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_5\ : label is "soft_lutpair16"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1\ : label is "soft_lutpair28"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1\ : label is "soft_lutpair29"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1\ : label is "soft_lutpair30"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1\ : label is "soft_lutpair32"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1\ : label is "soft_lutpair33"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1\ : label is "soft_lutpair25"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1\ : label is "soft_lutpair28"; attribute SOFT_HLUTNM of \GEN_RID.axi_rid_int[0]_i_2\ : label is "soft_lutpair21"; attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp[0]_i_2\ : label is "soft_lutpair26"; attribute SOFT_HLUTNM of act_rd_burst_i_4 : label is "soft_lutpair14"; attribute SOFT_HLUTNM of act_rd_burst_i_5 : label is "soft_lutpair43"; attribute SOFT_HLUTNM of axi_rd_burst_two_i_2 : label is "soft_lutpair13"; attribute SOFT_HLUTNM of axi_rvalid_clr_ok_i_2 : label is "soft_lutpair8"; attribute SOFT_HLUTNM of axi_rvalid_set_i_1 : label is "soft_lutpair19"; attribute SOFT_HLUTNM of bram_en_int_i_10 : label is "soft_lutpair9"; attribute SOFT_HLUTNM of bram_en_int_i_11 : label is "soft_lutpair15"; attribute SOFT_HLUTNM of bram_en_int_i_13 : label is "soft_lutpair22"; attribute SOFT_HLUTNM of bram_en_int_i_6 : label is "soft_lutpair16"; attribute SOFT_HLUTNM of bram_en_int_i_9 : label is "soft_lutpair18"; attribute SOFT_HLUTNM of \brst_cnt[4]_i_2\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \brst_cnt[6]_i_1\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of \brst_cnt[6]_i_2\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \brst_cnt[7]_i_3\ : label is "soft_lutpair26"; attribute SOFT_HLUTNM of \brst_cnt[7]_i_4\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of brst_one_i_2 : label is "soft_lutpair31"; attribute SOFT_HLUTNM of brst_zero_i_1 : label is "soft_lutpair18"; attribute SOFT_HLUTNM of brst_zero_i_2 : label is "soft_lutpair13"; attribute SOFT_HLUTNM of curr_fixed_burst_reg_i_1 : label is "soft_lutpair6"; attribute SOFT_HLUTNM of curr_wrap_burst_reg_i_1 : label is "soft_lutpair6"; attribute SOFT_HLUTNM of disable_b2b_brst_i_2 : label is "soft_lutpair43"; attribute SOFT_HLUTNM of last_bram_addr_i_2 : label is "soft_lutpair31"; attribute SOFT_HLUTNM of last_bram_addr_i_7 : label is "soft_lutpair10"; attribute SOFT_HLUTNM of last_bram_addr_i_9 : label is "soft_lutpair11"; attribute SOFT_HLUTNM of pend_rd_op_i_5 : label is "soft_lutpair27"; attribute SOFT_HLUTNM of pend_rd_op_i_6 : label is "soft_lutpair22"; attribute SOFT_HLUTNM of pend_rd_op_i_7 : label is "soft_lutpair20"; attribute SOFT_HLUTNM of \rd_data_sm_cs[0]_i_3\ : label is "soft_lutpair24"; attribute SOFT_HLUTNM of \rd_data_sm_cs[1]_i_2\ : label is "soft_lutpair24"; attribute SOFT_HLUTNM of \rd_data_sm_cs[2]_i_3\ : label is "soft_lutpair17"; attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_4\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_5\ : label is "soft_lutpair19"; attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_6\ : label is "soft_lutpair20"; attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_7\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of rddata_mux_sel_i_1 : label is "soft_lutpair17"; attribute SOFT_HLUTNM of s_axi_arready_INST_0 : label is "soft_lutpair21"; begin Q(13 downto 0) <= \^q\(13 downto 0); bram_en_b <= \^bram_en_b\; bram_rst_a <= \^bram_rst_a\; s_axi_rid(0) <= \^s_axi_rid\(0); s_axi_rlast <= \^s_axi_rlast\; s_axi_rvalid <= \^s_axi_rvalid\; \/FSM_sequential_rlast_sm_cs[0]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"0011001300130013" ) port map ( I0 => axi_rd_burst, I1 => rlast_sm_cs(1), I2 => act_rd_burst_two, I3 => axi_rd_burst_two_reg_n_0, I4 => \^s_axi_rvalid\, I5 => s_axi_rready, O => \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0\ ); \/FSM_sequential_rlast_sm_cs[1]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"003F007F003F0055" ) port map ( I0 => axi_rd_burst, I1 => s_axi_rready, I2 => \^s_axi_rvalid\, I3 => rlast_sm_cs(1), I4 => axi_rd_burst_two_reg_n_0, I5 => act_rd_burst_two, O => \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0\ ); \/i_\: unisim.vcomponents.LUT6 generic map( INIT => X"F000F111F000E000" ) port map ( I0 => rlast_sm_cs(2), I1 => rlast_sm_cs(1), I2 => \^s_axi_rvalid\, I3 => s_axi_rready, I4 => rlast_sm_cs(0), I5 => last_bram_addr, O => \/i__n_0\ ); \/i___0\: unisim.vcomponents.LUT6 generic map( INIT => X"00008080000F8080" ) port map ( I0 => s_axi_rready, I1 => \^s_axi_rvalid\, I2 => rlast_sm_cs(0), I3 => rlast_sm_cs(1), I4 => rlast_sm_cs(2), I5 => \^s_axi_rlast\, O => axi_rlast_set ); \FSM_sequential_rlast_sm_cs[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"01FF0100" ) port map ( I0 => rlast_sm_cs(2), I1 => rlast_sm_cs(0), I2 => \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0\, I3 => \/i__n_0\, I4 => rlast_sm_cs(0), O => \FSM_sequential_rlast_sm_cs[0]_i_1_n_0\ ); \FSM_sequential_rlast_sm_cs[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"01FF0100" ) port map ( I0 => rlast_sm_cs(2), I1 => rlast_sm_cs(0), I2 => \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0\, I3 => \/i__n_0\, I4 => rlast_sm_cs(1), O => \FSM_sequential_rlast_sm_cs[1]_i_1_n_0\ ); \FSM_sequential_rlast_sm_cs[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"00A4FFFF00A40000" ) port map ( I0 => rlast_sm_cs(1), I1 => p_0_in13_in, I2 => rlast_sm_cs(0), I3 => rlast_sm_cs(2), I4 => \/i__n_0\, I5 => rlast_sm_cs(2), O => \FSM_sequential_rlast_sm_cs[2]_i_1_n_0\ ); \FSM_sequential_rlast_sm_cs[2]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => axi_rd_burst_two_reg_n_0, I1 => axi_rd_burst, O => p_0_in13_in ); \FSM_sequential_rlast_sm_cs_reg[0]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => \FSM_sequential_rlast_sm_cs[0]_i_1_n_0\, Q => rlast_sm_cs(0), R => \^bram_rst_a\ ); \FSM_sequential_rlast_sm_cs_reg[1]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => \FSM_sequential_rlast_sm_cs[1]_i_1_n_0\, Q => rlast_sm_cs(1), R => \^bram_rst_a\ ); \FSM_sequential_rlast_sm_cs_reg[2]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => \FSM_sequential_rlast_sm_cs[2]_i_1_n_0\, Q => rlast_sm_cs(2), R => \^bram_rst_a\ ); \GEN_ARREADY.axi_arready_int_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAEEE" ) port map ( I0 => p_9_out, I1 => axi_arready_int, I2 => s_axi_arvalid, I3 => axi_araddr_full, I4 => araddr_pipe_ld43_out, O => \GEN_ARREADY.axi_arready_int_i_1_n_0\ ); \GEN_ARREADY.axi_arready_int_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"BAAA" ) port map ( I0 => axi_aresetn_re_reg, I1 => axi_early_arready_int, I2 => axi_araddr_full, I3 => bram_addr_ld_en, O => p_9_out ); \GEN_ARREADY.axi_arready_int_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \GEN_ARREADY.axi_arready_int_i_1_n_0\, Q => axi_arready_int, R => \^bram_rst_a\ ); \GEN_ARREADY.axi_early_arready_int_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000200" ) port map ( I0 => \GEN_ARREADY.axi_early_arready_int_i_2_n_0\, I1 => \GEN_ARREADY.axi_early_arready_int_i_3_n_0\, I2 => rd_data_sm_cs(3), I3 => brst_one, I4 => axi_arready_int, I5 => \GEN_ARREADY.axi_early_arready_int_i_4_n_0\, O => p_48_out ); \GEN_ARREADY.axi_early_arready_int_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"03C4000400C40004" ) port map ( I0 => axi_rd_burst_two_reg_n_0, I1 => rd_data_sm_cs(1), I2 => rd_data_sm_cs(0), I3 => rd_data_sm_cs(2), I4 => rd_adv_buf67_out, I5 => bram_en_int_i_9_n_0, O => \GEN_ARREADY.axi_early_arready_int_i_2_n_0\ ); \GEN_ARREADY.axi_early_arready_int_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => axi_araddr_full, I1 => s_axi_arvalid, O => \GEN_ARREADY.axi_early_arready_int_i_3_n_0\ ); \GEN_ARREADY.axi_early_arready_int_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"AAEAAAEAFFFFAAEA" ) port map ( I0 => I_WRAP_BRST_n_27, I1 => \rd_data_sm_cs[3]_i_6_n_0\, I2 => rd_data_sm_cs(1), I3 => rd_data_sm_cs(0), I4 => brst_zero, I5 => rd_adv_buf67_out, O => \GEN_ARREADY.axi_early_arready_int_i_4_n_0\ ); \GEN_ARREADY.axi_early_arready_int_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => p_48_out, Q => axi_early_arready_int, R => \^bram_rst_a\ ); \GEN_AR_DUAL.ar_active_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0FBFBFBF0F0F0F0" ) port map ( I0 => \GEN_AR_DUAL.ar_active_i_2_n_0\, I1 => \rd_data_sm_cs[2]_i_3_n_0\, I2 => bram_addr_ld_en, I3 => \rd_data_sm_cs[2]_i_5_n_0\, I4 => rd_adv_buf67_out, I5 => ar_active, O => \GEN_AR_DUAL.ar_active_i_1_n_0\ ); \GEN_AR_DUAL.ar_active_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"B0FFBFFFB0FFBF0F" ) port map ( I0 => \GEN_AR_DUAL.ar_active_i_3_n_0\, I1 => I_WRAP_BRST_n_27, I2 => rd_data_sm_cs(0), I3 => rd_data_sm_cs(1), I4 => axi_rd_burst_two_reg_n_0, I5 => axi_rd_burst, O => \GEN_AR_DUAL.ar_active_i_2_n_0\ ); \GEN_AR_DUAL.ar_active_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"0DFFFFFF" ) port map ( I0 => end_brst_rd, I1 => axi_b2b_brst, I2 => brst_zero, I3 => s_axi_rready, I4 => \^s_axi_rvalid\, O => \GEN_AR_DUAL.ar_active_i_3_n_0\ ); \GEN_AR_DUAL.ar_active_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \GEN_AR_DUAL.ar_active_i_1_n_0\, Q => ar_active, R => \GEN_AWREADY.axi_aresetn_d2_reg\ ); \GEN_AR_DUAL.rd_addr_sm_cs_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"10001000F0F01000" ) port map ( I0 => rd_addr_sm_cs, I1 => axi_araddr_full, I2 => s_axi_arvalid, I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\, I4 => last_bram_addr, I5 => \GEN_ARREADY.axi_early_arready_int_i_4_n_0\, O => \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0\ ); \GEN_AR_DUAL.rd_addr_sm_cs_reg\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0\, Q => rd_addr_sm_cs, R => \GEN_AWREADY.axi_aresetn_d2_reg\ ); \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_araddr(8), Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\, R => '0' ); \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_araddr(9), Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\, R => '0' ); \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_araddr(10), Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\, R => '0' ); \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_araddr(11), Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\, R => '0' ); \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_araddr(12), Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\, R => '0' ); \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_araddr(13), Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\, R => '0' ); \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_araddr(0), Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\, R => '0' ); \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_araddr(1), Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\, R => '0' ); \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_araddr(2), Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\, R => '0' ); \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_araddr(3), Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\, R => '0' ); \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_araddr(4), Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\, R => '0' ); \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_araddr(5), Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\, R => '0' ); \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_araddr(6), Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\, R => '0' ); \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_araddr(7), Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\, R => '0' ); \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"00C08888CCCC8888" ) port map ( I0 => araddr_pipe_ld43_out, I1 => s_axi_aresetn, I2 => s_axi_arvalid, I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\, I4 => axi_araddr_full, I5 => bram_addr_ld_en, O => \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0\ ); \GEN_AR_PIPE_DUAL.axi_araddr_full_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0\, Q => axi_araddr_full, R => '0' ); \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"03AA" ) port map ( I0 => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\, I1 => s_axi_arburst(0), I2 => s_axi_arburst(1), I3 => araddr_pipe_ld43_out, O => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0\ ); \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0\, Q => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\, R => '0' ); \GEN_AR_PIPE_DUAL.axi_arburst_pipe_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_arburst(0), Q => axi_arburst_pipe(0), R => '0' ); \GEN_AR_PIPE_DUAL.axi_arburst_pipe_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_arburst(1), Q => axi_arburst_pipe(1), R => '0' ); \GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_arid(0), Q => axi_arid_pipe, R => '0' ); \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"220022002A002200" ) port map ( I0 => axi_aresetn_d2, I1 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\, I2 => rd_addr_sm_cs, I3 => s_axi_arvalid, I4 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\, I5 => axi_araddr_full, O => araddr_pipe_ld43_out ); \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFF70FFFFFFFF" ) port map ( I0 => \^s_axi_rvalid\, I1 => s_axi_rready, I2 => brst_zero, I3 => I_WRAP_BRST_n_26, I4 => I_WRAP_BRST_n_27, I5 => last_bram_addr, O => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\ ); \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"FE" ) port map ( I0 => no_ar_ack, I1 => pend_rd_op, I2 => ar_active, O => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\ ); \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => s_axi_arlen(1), I1 => s_axi_arlen(7), I2 => s_axi_arlen(4), I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0\, O => p_13_out ); \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => s_axi_arlen(6), I1 => s_axi_arlen(2), I2 => s_axi_arlen(5), I3 => s_axi_arlen(3), O => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0\ ); \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => p_13_out, Q => axi_arlen_pipe_1_or_2, R => '0' ); \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_arlen(0), Q => axi_arlen_pipe(0), R => '0' ); \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_arlen(1), Q => axi_arlen_pipe(1), R => '0' ); \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_arlen(2), Q => axi_arlen_pipe(2), R => '0' ); \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_arlen(3), Q => axi_arlen_pipe(3), R => '0' ); \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_arlen(4), Q => axi_arlen_pipe(4), R => '0' ); \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_arlen(5), Q => axi_arlen_pipe(5), R => '0' ); \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_arlen(6), Q => axi_arlen_pipe(6), R => '0' ); \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_arlen(7), Q => axi_arlen_pipe(7), R => '0' ); \GEN_AR_PIPE_DUAL.axi_arsize_pipe_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => '1', Q => axi_arsize_pipe(1), R => '0' ); \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"00000000BAAA0000" ) port map ( I0 => brst_cnt_max, I1 => pend_rd_op, I2 => ar_active, I3 => brst_zero, I4 => s_axi_aresetn, I5 => bram_addr_ld_en, O => \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0\ ); \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0\, Q => brst_cnt_max, R => '0' ); \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFFFFFFFFFF" ) port map ( I0 => \^q\(4), I1 => \^q\(1), I2 => \^q\(0), I3 => \^q\(2), I4 => \^q\(3), I5 => \^q\(5), O => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0\ ); \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"F7FFFFFF" ) port map ( I0 => \^q\(6), I1 => \^q\(4), I2 => I_WRAP_BRST_n_24, I3 => \^q\(5), I4 => \^q\(7), O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0\ ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => I_WRAP_BRST_n_7, D => I_WRAP_BRST_n_14, Q => \^q\(8), R => '0' ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => I_WRAP_BRST_n_7, D => I_WRAP_BRST_n_13, Q => \^q\(9), R => '0' ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => bram_addr_ld_en_mod, D => I_WRAP_BRST_n_12, Q => \^q\(10), R => '0' ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => bram_addr_ld_en_mod, D => I_WRAP_BRST_n_11, Q => \^q\(11), R => '0' ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => bram_addr_ld_en_mod, D => I_WRAP_BRST_n_10, Q => \^q\(12), R => '0' ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => bram_addr_ld_en_mod, D => I_WRAP_BRST_n_9, Q => \^q\(13), R => '0' ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => I_WRAP_BRST_n_7, D => I_WRAP_BRST_n_22, Q => \^q\(0), R => '0' ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => I_WRAP_BRST_n_7, D => I_WRAP_BRST_n_21, Q => \^q\(1), R => '0' ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => I_WRAP_BRST_n_7, D => I_WRAP_BRST_n_20, Q => \^q\(2), R => '0' ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => I_WRAP_BRST_n_7, D => I_WRAP_BRST_n_19, Q => \^q\(3), R => '0' ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => I_WRAP_BRST_n_7, D => I_WRAP_BRST_n_18, Q => \^q\(4), R => '0' ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => I_WRAP_BRST_n_7, D => I_WRAP_BRST_n_17, Q => \^q\(5), R => '0' ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => I_WRAP_BRST_n_7, D => I_WRAP_BRST_n_16, Q => \^q\(6), R => '0' ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => I_WRAP_BRST_n_7, D => I_WRAP_BRST_n_15, Q => \^q\(7), R => '0' ); \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(0), I1 => bram_rddata_b(0), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\, Q => s_axi_rdata(0), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(10), I1 => bram_rddata_b(10), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\, Q => s_axi_rdata(10), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(11), I1 => bram_rddata_b(11), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\, Q => s_axi_rdata(11), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(12), I1 => bram_rddata_b(12), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\, Q => s_axi_rdata(12), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(13), I1 => bram_rddata_b(13), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\, Q => s_axi_rdata(13), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(14), I1 => bram_rddata_b(14), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\, Q => s_axi_rdata(14), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(15), I1 => bram_rddata_b(15), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\, Q => s_axi_rdata(15), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(16), I1 => bram_rddata_b(16), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\, Q => s_axi_rdata(16), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(17), I1 => bram_rddata_b(17), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\, Q => s_axi_rdata(17), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(18), I1 => bram_rddata_b(18), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\, Q => s_axi_rdata(18), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(19), I1 => bram_rddata_b(19), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\, Q => s_axi_rdata(19), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(1), I1 => bram_rddata_b(1), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0\, Q => s_axi_rdata(1), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(20), I1 => bram_rddata_b(20), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\, Q => s_axi_rdata(20), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(21), I1 => bram_rddata_b(21), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\, Q => s_axi_rdata(21), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(22), I1 => bram_rddata_b(22), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\, Q => s_axi_rdata(22), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(23), I1 => bram_rddata_b(23), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\, Q => s_axi_rdata(23), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(24), I1 => bram_rddata_b(24), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\, Q => s_axi_rdata(24), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(25), I1 => bram_rddata_b(25), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\, Q => s_axi_rdata(25), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(26), I1 => bram_rddata_b(26), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\, Q => s_axi_rdata(26), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(27), I1 => bram_rddata_b(27), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\, Q => s_axi_rdata(27), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(28), I1 => bram_rddata_b(28), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\, Q => s_axi_rdata(28), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(29), I1 => bram_rddata_b(29), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\, Q => s_axi_rdata(29), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(2), I1 => bram_rddata_b(2), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\, Q => s_axi_rdata(2), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(30), I1 => bram_rddata_b(30), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int_reg[30]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\, Q => s_axi_rdata(30), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"08FF" ) port map ( I0 => s_axi_rready, I1 => \^s_axi_rlast\, I2 => axi_b2b_brst, I3 => s_axi_aresetn, O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"1414545410000404" ) port map ( I0 => rd_data_sm_cs(3), I1 => rd_data_sm_cs(1), I2 => rd_data_sm_cs(2), I3 => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4_n_0\, I4 => rd_data_sm_cs(0), I5 => rd_adv_buf67_out, O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(31), I1 => bram_rddata_b(31), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => act_rd_burst, I1 => act_rd_burst_two, O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^s_axi_rvalid\, I1 => s_axi_rready, O => rd_adv_buf67_out ); \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int_reg[31]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\, Q => s_axi_rdata(31), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(3), I1 => bram_rddata_b(3), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\, Q => s_axi_rdata(3), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(4), I1 => bram_rddata_b(4), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\, Q => s_axi_rdata(4), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(5), I1 => bram_rddata_b(5), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\, Q => s_axi_rdata(5), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(6), I1 => bram_rddata_b(6), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\, Q => s_axi_rdata(6), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(7), I1 => bram_rddata_b(7), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\, Q => s_axi_rdata(7), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(8), I1 => bram_rddata_b(8), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\, Q => s_axi_rdata(8), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(9), I1 => bram_rddata_b(9), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\, Q => s_axi_rdata(9), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.rd_skid_buf[31]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAAABAAAAAA" ) port map ( I0 => rd_skid_buf_ld_reg, I1 => rd_data_sm_cs(1), I2 => rd_data_sm_cs(3), I3 => rd_adv_buf67_out, I4 => rd_data_sm_cs(2), I5 => rd_data_sm_cs(0), O => rd_skid_buf_ld ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(0), Q => rd_skid_buf(0), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(10), Q => rd_skid_buf(10), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(11), Q => rd_skid_buf(11), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(12), Q => rd_skid_buf(12), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(13), Q => rd_skid_buf(13), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(14), Q => rd_skid_buf(14), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(15), Q => rd_skid_buf(15), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(16), Q => rd_skid_buf(16), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(17), Q => rd_skid_buf(17), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(18), Q => rd_skid_buf(18), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(19), Q => rd_skid_buf(19), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(1), Q => rd_skid_buf(1), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(20), Q => rd_skid_buf(20), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(21), Q => rd_skid_buf(21), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(22), Q => rd_skid_buf(22), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(23), Q => rd_skid_buf(23), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(24), Q => rd_skid_buf(24), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(25), Q => rd_skid_buf(25), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(26), Q => rd_skid_buf(26), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(27), Q => rd_skid_buf(27), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(28), Q => rd_skid_buf(28), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(29), Q => rd_skid_buf(29), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(2), Q => rd_skid_buf(2), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[30]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(30), Q => rd_skid_buf(30), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[31]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(31), Q => rd_skid_buf(31), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(3), Q => rd_skid_buf(3), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(4), Q => rd_skid_buf(4), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(5), Q => rd_skid_buf(5), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(6), Q => rd_skid_buf(6), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(7), Q => rd_skid_buf(7), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(8), Q => rd_skid_buf(8), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(9), Q => rd_skid_buf(9), R => \^bram_rst_a\ ); \GEN_RID.axi_rid_int[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"E200E200F0000000" ) port map ( I0 => \^s_axi_rid\(0), I1 => axi_rvalid_set, I2 => axi_rid_temp, I3 => s_axi_aresetn, I4 => axi_b2b_brst, I5 => \GEN_RID.axi_rid_int[0]_i_2_n_0\, O => \GEN_RID.axi_rid_int[0]_i_1_n_0\ ); \GEN_RID.axi_rid_int[0]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => s_axi_rready, I1 => \^s_axi_rlast\, O => \GEN_RID.axi_rid_int[0]_i_2_n_0\ ); \GEN_RID.axi_rid_int_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \GEN_RID.axi_rid_int[0]_i_1_n_0\, Q => \^s_axi_rid\(0), R => '0' ); \GEN_RID.axi_rid_temp2[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"B8FFFFFFB8000000" ) port map ( I0 => axi_arid_pipe, I1 => axi_araddr_full, I2 => s_axi_arid(0), I3 => axi_rid_temp_full, I4 => bram_addr_ld_en, I5 => \GEN_RID.axi_rid_temp2_reg_n_0_[0]\, O => \GEN_RID.axi_rid_temp2[0]_i_1_n_0\ ); \GEN_RID.axi_rid_temp2_full_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"08080000C8C800C0" ) port map ( I0 => bram_addr_ld_en, I1 => s_axi_aresetn, I2 => axi_rid_temp2_full, I3 => axi_rid_temp_full_d1, I4 => axi_rid_temp_full, I5 => p_4_out, O => \GEN_RID.axi_rid_temp2_full_i_1_n_0\ ); \GEN_RID.axi_rid_temp2_full_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \GEN_RID.axi_rid_temp2_full_i_1_n_0\, Q => axi_rid_temp2_full, R => '0' ); \GEN_RID.axi_rid_temp2_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \GEN_RID.axi_rid_temp2[0]_i_1_n_0\, Q => \GEN_RID.axi_rid_temp2_reg_n_0_[0]\, R => \^bram_rst_a\ ); \GEN_RID.axi_rid_temp[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"CFAACFCFC0AAC0C0" ) port map ( I0 => axi_rid_temp2, I1 => \GEN_RID.axi_rid_temp2_reg_n_0_[0]\, I2 => \GEN_RID.axi_rid_temp[0]_i_3_n_0\, I3 => axi_rid_temp_full, I4 => bram_addr_ld_en, I5 => axi_rid_temp, O => \GEN_RID.axi_rid_temp[0]_i_1_n_0\ ); \GEN_RID.axi_rid_temp[0]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axi_arid_pipe, I1 => axi_araddr_full, I2 => s_axi_arid(0), O => axi_rid_temp2 ); \GEN_RID.axi_rid_temp[0]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"AA08AAAAAA08AA08" ) port map ( I0 => axi_rid_temp2_full, I1 => axi_rid_temp_full_d1, I2 => axi_rid_temp_full, I3 => axi_rvalid_set, I4 => \GEN_RID.axi_rid_int[0]_i_2_n_0\, I5 => axi_b2b_brst, O => \GEN_RID.axi_rid_temp[0]_i_3_n_0\ ); \GEN_RID.axi_rid_temp_full_d1_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => axi_rid_temp_full, Q => axi_rid_temp_full_d1, R => \^bram_rst_a\ ); \GEN_RID.axi_rid_temp_full_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0F0F0E000F0A0A0" ) port map ( I0 => bram_addr_ld_en, I1 => axi_rid_temp_full_d1, I2 => s_axi_aresetn, I3 => p_4_out, I4 => axi_rid_temp_full, I5 => axi_rid_temp2_full, O => \GEN_RID.axi_rid_temp_full_i_1_n_0\ ); \GEN_RID.axi_rid_temp_full_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"EAAA" ) port map ( I0 => axi_rvalid_set, I1 => s_axi_rready, I2 => \^s_axi_rlast\, I3 => axi_b2b_brst, O => p_4_out ); \GEN_RID.axi_rid_temp_full_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \GEN_RID.axi_rid_temp_full_i_1_n_0\, Q => axi_rid_temp_full, R => '0' ); \GEN_RID.axi_rid_temp_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \GEN_RID.axi_rid_temp[0]_i_1_n_0\, Q => axi_rid_temp, R => \^bram_rst_a\ ); I_WRAP_BRST: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst_0 port map ( D(13) => I_WRAP_BRST_n_9, D(12) => I_WRAP_BRST_n_10, D(11) => I_WRAP_BRST_n_11, D(10) => I_WRAP_BRST_n_12, D(9) => I_WRAP_BRST_n_13, D(8) => I_WRAP_BRST_n_14, D(7) => I_WRAP_BRST_n_15, D(6) => I_WRAP_BRST_n_16, D(5) => I_WRAP_BRST_n_17, D(4) => I_WRAP_BRST_n_18, D(3) => I_WRAP_BRST_n_19, D(2) => I_WRAP_BRST_n_20, D(1) => I_WRAP_BRST_n_21, D(0) => I_WRAP_BRST_n_22, E(1) => bram_addr_ld_en_mod, E(0) => I_WRAP_BRST_n_7, \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\, \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\, \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\, \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\, \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\, \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\, \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\, \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\, \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\, \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\, \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\, \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\, \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\, \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\, \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\ => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\, \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(3 downto 0) => axi_arlen_pipe(3 downto 0), \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ => I_WRAP_BRST_n_0, \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0\ => I_WRAP_BRST_n_8, \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(9 downto 0) => \^q\(9 downto 0), \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ => I_WRAP_BRST_n_24, \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0\, \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0\, Q(3 downto 0) => rd_data_sm_cs(3 downto 0), SR(0) => \^bram_rst_a\, ar_active => ar_active, axi_araddr_full => axi_araddr_full, axi_aresetn_d2 => axi_aresetn_d2, axi_arlen_pipe_1_or_2 => axi_arlen_pipe_1_or_2, axi_arsize_pipe(0) => axi_arsize_pipe(1), axi_arsize_pipe_max => axi_arsize_pipe_max, axi_b2b_brst => axi_b2b_brst, axi_rd_burst => axi_rd_burst, axi_rd_burst_two_reg => axi_rd_burst_two_reg_n_0, axi_rvalid_int_reg => \^s_axi_rvalid\, bram_addr_ld_en => bram_addr_ld_en, brst_zero => brst_zero, curr_fixed_burst_reg => curr_fixed_burst_reg, curr_wrap_burst_reg => curr_wrap_burst_reg, disable_b2b_brst => disable_b2b_brst, end_brst_rd => end_brst_rd, last_bram_addr => last_bram_addr, no_ar_ack => no_ar_ack, pend_rd_op => pend_rd_op, rd_addr_sm_cs => rd_addr_sm_cs, \rd_data_sm_cs_reg[1]\ => I_WRAP_BRST_n_25, s_axi_aclk => s_axi_aclk, s_axi_araddr(13 downto 0) => s_axi_araddr(13 downto 0), s_axi_aresetn => s_axi_aresetn, s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0), s_axi_arvalid => s_axi_arvalid, s_axi_rready => s_axi_rready, \save_init_bram_addr_ld_reg[15]_0\ => I_WRAP_BRST_n_26, \save_init_bram_addr_ld_reg[15]_1\ => I_WRAP_BRST_n_27, \wrap_burst_total_reg[0]_0\ => I_WRAP_BRST_n_2, \wrap_burst_total_reg[0]_1\ => I_WRAP_BRST_n_3, \wrap_burst_total_reg[0]_2\ => I_WRAP_BRST_n_4, \wrap_burst_total_reg[0]_3\ => I_WRAP_BRST_n_5 ); act_rd_burst_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"000000002EEE22E2" ) port map ( I0 => act_rd_burst, I1 => act_rd_burst_set, I2 => bram_addr_ld_en, I3 => axi_rd_burst_two, I4 => axi_rd_burst, I5 => act_rd_burst_i_3_n_0, O => act_rd_burst_i_1_n_0 ); act_rd_burst_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"A8A888A888888888" ) port map ( I0 => \rd_data_sm_cs[2]_i_3_n_0\, I1 => act_rd_burst_i_4_n_0, I2 => act_rd_burst_i_5_n_0, I3 => axi_rd_burst_i_2_n_0, I4 => I_WRAP_BRST_n_4, I5 => bram_addr_ld_en, O => act_rd_burst_set ); act_rd_burst_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"20000040FFFFFFFF" ) port map ( I0 => rd_data_sm_cs(2), I1 => rd_data_sm_cs(3), I2 => \rd_data_sm_cs[3]_i_7_n_0\, I3 => rd_data_sm_cs(1), I4 => rd_data_sm_cs(0), I5 => s_axi_aresetn, O => act_rd_burst_i_3_n_0 ); act_rd_burst_i_4: unisim.vcomponents.LUT5 generic map( INIT => X"5500FC00" ) port map ( I0 => bram_en_int_i_12_n_0, I1 => axi_rd_burst_two_reg_n_0, I2 => axi_rd_burst, I3 => rd_data_sm_cs(0), I4 => rd_data_sm_cs(1), O => act_rd_burst_i_4_n_0 ); act_rd_burst_i_5: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => rd_data_sm_cs(1), I1 => rd_data_sm_cs(0), O => act_rd_burst_i_5_n_0 ); act_rd_burst_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => act_rd_burst_i_1_n_0, Q => act_rd_burst, R => '0' ); act_rd_burst_two_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"00000000E2EEE222" ) port map ( I0 => act_rd_burst_two, I1 => act_rd_burst_set, I2 => axi_rd_burst_two, I3 => bram_addr_ld_en, I4 => axi_rd_burst_two_reg_n_0, I5 => act_rd_burst_i_3_n_0, O => act_rd_burst_two_i_1_n_0 ); act_rd_burst_two_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => act_rd_burst_two_i_1_n_0, Q => act_rd_burst_two, R => '0' ); axi_arsize_pipe_max_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => araddr_pipe_ld43_out, I1 => axi_arsize_pipe_max, O => axi_arsize_pipe_max_i_1_n_0 ); axi_arsize_pipe_max_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => axi_arsize_pipe_max_i_1_n_0, Q => axi_arsize_pipe_max, R => \^bram_rst_a\ ); axi_b2b_brst_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"F000F074F0F0F074" ) port map ( I0 => I_WRAP_BRST_n_27, I1 => axi_b2b_brst_i_2_n_0, I2 => axi_b2b_brst, I3 => rd_data_sm_cs(3), I4 => rd_data_sm_cs(2), I5 => disable_b2b_brst_i_2_n_0, O => axi_b2b_brst_i_1_n_0 ); axi_b2b_brst_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"00000000AA080000" ) port map ( I0 => \rd_data_sm_cs[0]_i_3_n_0\, I1 => end_brst_rd, I2 => axi_b2b_brst, I3 => brst_zero, I4 => rd_adv_buf67_out, I5 => I_WRAP_BRST_n_27, O => axi_b2b_brst_i_2_n_0 ); axi_b2b_brst_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => axi_b2b_brst_i_1_n_0, Q => axi_b2b_brst, R => \^bram_rst_a\ ); axi_rd_burst_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"303000A0" ) port map ( I0 => axi_rd_burst, I1 => axi_rd_burst_i_2_n_0, I2 => s_axi_aresetn, I3 => brst_zero, I4 => bram_addr_ld_en, O => axi_rd_burst_i_1_n_0 ); axi_rd_burst_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000000001000111" ) port map ( I0 => I_WRAP_BRST_n_2, I1 => I_WRAP_BRST_n_5, I2 => axi_arlen_pipe(1), I3 => axi_araddr_full, I4 => s_axi_arlen(1), I5 => axi_rd_burst_i_3_n_0, O => axi_rd_burst_i_2_n_0 ); axi_rd_burst_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFBBFCB8" ) port map ( I0 => axi_arlen_pipe(5), I1 => axi_araddr_full, I2 => s_axi_arlen(5), I3 => axi_arlen_pipe(4), I4 => s_axi_arlen(4), I5 => last_bram_addr_i_9_n_0, O => axi_rd_burst_i_3_n_0 ); axi_rd_burst_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => axi_rd_burst_i_1_n_0, Q => axi_rd_burst, R => '0' ); axi_rd_burst_two_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"C0C000A0" ) port map ( I0 => axi_rd_burst_two_reg_n_0, I1 => axi_rd_burst_two, I2 => s_axi_aresetn, I3 => brst_zero, I4 => bram_addr_ld_en, O => axi_rd_burst_two_i_1_n_0 ); axi_rd_burst_two_i_2: unisim.vcomponents.LUT4 generic map( INIT => X"A808" ) port map ( I0 => axi_rd_burst_i_2_n_0, I1 => s_axi_arlen(0), I2 => axi_araddr_full, I3 => axi_arlen_pipe(0), O => axi_rd_burst_two ); axi_rd_burst_two_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => axi_rd_burst_two_i_1_n_0, Q => axi_rd_burst_two_reg_n_0, R => '0' ); axi_rlast_int_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"88A8" ) port map ( I0 => s_axi_aresetn, I1 => axi_rlast_set, I2 => \^s_axi_rlast\, I3 => s_axi_rready, O => axi_rlast_int_i_1_n_0 ); axi_rlast_int_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => axi_rlast_int_i_1_n_0, Q => \^s_axi_rlast\, R => '0' ); axi_rvalid_clr_ok_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"00000000FFFFEEEA" ) port map ( I0 => axi_rvalid_clr_ok, I1 => last_bram_addr, I2 => disable_b2b_brst, I3 => disable_b2b_brst_cmb, I4 => axi_rvalid_clr_ok_i_2_n_0, I5 => axi_rvalid_clr_ok_i_3_n_0, O => axi_rvalid_clr_ok_i_1_n_0 ); axi_rvalid_clr_ok_i_2: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAEAA" ) port map ( I0 => bram_addr_ld_en, I1 => rd_data_sm_cs(0), I2 => rd_data_sm_cs(1), I3 => rd_data_sm_cs(2), I4 => rd_data_sm_cs(3), O => axi_rvalid_clr_ok_i_2_n_0 ); axi_rvalid_clr_ok_i_3: unisim.vcomponents.LUT3 generic map( INIT => X"4F" ) port map ( I0 => \GEN_ARREADY.axi_early_arready_int_i_4_n_0\, I1 => bram_addr_ld_en, I2 => s_axi_aresetn, O => axi_rvalid_clr_ok_i_3_n_0 ); axi_rvalid_clr_ok_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => axi_rvalid_clr_ok_i_1_n_0, Q => axi_rvalid_clr_ok, R => '0' ); axi_rvalid_int_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"00E0E0E0E0E0E0E0" ) port map ( I0 => \^s_axi_rvalid\, I1 => axi_rvalid_set, I2 => s_axi_aresetn, I3 => axi_rvalid_clr_ok, I4 => \^s_axi_rlast\, I5 => s_axi_rready, O => axi_rvalid_int_i_1_n_0 ); axi_rvalid_int_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => axi_rvalid_int_i_1_n_0, Q => \^s_axi_rvalid\, R => '0' ); axi_rvalid_set_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"0100" ) port map ( I0 => rd_data_sm_cs(2), I1 => rd_data_sm_cs(3), I2 => rd_data_sm_cs(1), I3 => rd_data_sm_cs(0), O => axi_rvalid_set_cmb ); axi_rvalid_set_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => axi_rvalid_set_cmb, Q => axi_rvalid_set, R => \^bram_rst_a\ ); bram_en_int_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFEEFFFA0022000A" ) port map ( I0 => bram_en_int_i_2_n_0, I1 => bram_en_int_i_3_n_0, I2 => bram_en_int_i_4_n_0, I3 => rd_data_sm_cs(3), I4 => rd_data_sm_cs(2), I5 => \^bram_en_b\, O => bram_en_int_i_1_n_0 ); bram_en_int_i_10: unisim.vcomponents.LUT5 generic map( INIT => X"E0000000" ) port map ( I0 => act_rd_burst, I1 => act_rd_burst_two, I2 => \^s_axi_rvalid\, I3 => s_axi_rready, I4 => bram_addr_ld_en, O => bram_en_int_i_10_n_0 ); bram_en_int_i_11: unisim.vcomponents.LUT4 generic map( INIT => X"0111" ) port map ( I0 => end_brst_rd, I1 => brst_zero, I2 => s_axi_rready, I3 => \^s_axi_rvalid\, O => bram_en_int_i_11_n_0 ); bram_en_int_i_12: unisim.vcomponents.LUT6 generic map( INIT => X"BFFFBFBFBFFFBFFF" ) port map ( I0 => I_WRAP_BRST_n_27, I1 => \^s_axi_rvalid\, I2 => s_axi_rready, I3 => brst_zero, I4 => axi_b2b_brst, I5 => end_brst_rd, O => bram_en_int_i_12_n_0 ); bram_en_int_i_13: unisim.vcomponents.LUT3 generic map( INIT => X"45" ) port map ( I0 => brst_zero, I1 => axi_b2b_brst, I2 => end_brst_rd, O => bram_en_int_i_13_n_0 ); bram_en_int_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFF4044" ) port map ( I0 => bram_en_int_i_5_n_0, I1 => rd_data_sm_cs(1), I2 => bram_en_int_i_6_n_0, I3 => rd_data_sm_cs(2), I4 => bram_en_int_i_7_n_0, I5 => I_WRAP_BRST_n_0, O => bram_en_int_i_2_n_0 ); bram_en_int_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"707370707C7F7C7C" ) port map ( I0 => bram_en_int_i_6_n_0, I1 => rd_data_sm_cs(0), I2 => rd_data_sm_cs(1), I3 => rd_adv_buf67_out, I4 => bram_en_int_i_9_n_0, I5 => bram_en_int_i_10_n_0, O => bram_en_int_i_3_n_0 ); bram_en_int_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"A0001111AAAA1111" ) port map ( I0 => rd_data_sm_cs(0), I1 => bram_addr_ld_en, I2 => bram_en_int_i_11_n_0, I3 => brst_one, I4 => rd_data_sm_cs(1), I5 => bram_en_int_i_12_n_0, O => bram_en_int_i_4_n_0 ); bram_en_int_i_5: unisim.vcomponents.LUT6 generic map( INIT => X"0044054455440544" ) port map ( I0 => rd_data_sm_cs(2), I1 => axi_rd_burst_two_reg_n_0, I2 => bram_en_int_i_9_n_0, I3 => rd_data_sm_cs(0), I4 => rd_adv_buf67_out, I5 => bram_en_int_i_13_n_0, O => bram_en_int_i_5_n_0 ); bram_en_int_i_6: unisim.vcomponents.LUT4 generic map( INIT => X"ECCC" ) port map ( I0 => pend_rd_op, I1 => bram_addr_ld_en, I2 => \^s_axi_rvalid\, I3 => s_axi_rready, O => bram_en_int_i_6_n_0 ); bram_en_int_i_7: unisim.vcomponents.LUT6 generic map( INIT => X"5554005500540000" ) port map ( I0 => rd_data_sm_cs(1), I1 => axi_rd_burst_two_reg_n_0, I2 => axi_rd_burst, I3 => rd_data_sm_cs(2), I4 => rd_data_sm_cs(0), I5 => bram_addr_ld_en, O => bram_en_int_i_7_n_0 ); bram_en_int_i_9: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => brst_zero, I1 => end_brst_rd, O => bram_en_int_i_9_n_0 ); bram_en_int_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => bram_en_int_i_1_n_0, Q => \^bram_en_b\, R => \^bram_rst_a\ ); \brst_cnt[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"D1DDD111" ) port map ( I0 => brst_cnt(0), I1 => bram_addr_ld_en, I2 => axi_arlen_pipe(0), I3 => axi_araddr_full, I4 => s_axi_arlen(0), O => \brst_cnt[0]_i_1_n_0\ ); \brst_cnt[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"B8FFB800B800B8FF" ) port map ( I0 => axi_arlen_pipe(1), I1 => axi_araddr_full, I2 => s_axi_arlen(1), I3 => bram_addr_ld_en, I4 => brst_cnt(0), I5 => brst_cnt(1), O => \brst_cnt[1]_i_1_n_0\ ); \brst_cnt[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8B8B88B" ) port map ( I0 => I_WRAP_BRST_n_2, I1 => bram_addr_ld_en, I2 => brst_cnt(2), I3 => brst_cnt(1), I4 => brst_cnt(0), O => \brst_cnt[2]_i_1_n_0\ ); \brst_cnt[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"B8B8B8B8B8B8B88B" ) port map ( I0 => I_WRAP_BRST_n_5, I1 => bram_addr_ld_en, I2 => brst_cnt(3), I3 => brst_cnt(2), I4 => brst_cnt(0), I5 => brst_cnt(1), O => \brst_cnt[3]_i_1_n_0\ ); \brst_cnt[4]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"B8FFB800B800B8FF" ) port map ( I0 => axi_arlen_pipe(4), I1 => axi_araddr_full, I2 => s_axi_arlen(4), I3 => bram_addr_ld_en, I4 => brst_cnt(4), I5 => \brst_cnt[4]_i_2_n_0\, O => \brst_cnt[4]_i_1_n_0\ ); \brst_cnt[4]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => brst_cnt(3), I1 => brst_cnt(2), I2 => brst_cnt(0), I3 => brst_cnt(1), O => \brst_cnt[4]_i_2_n_0\ ); \brst_cnt[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"B800B8FFB8FFB800" ) port map ( I0 => axi_arlen_pipe(5), I1 => axi_araddr_full, I2 => s_axi_arlen(5), I3 => bram_addr_ld_en, I4 => brst_cnt(5), I5 => \brst_cnt[7]_i_4_n_0\, O => \brst_cnt[5]_i_1_n_0\ ); \brst_cnt[6]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B88BB8B8" ) port map ( I0 => \brst_cnt[6]_i_2_n_0\, I1 => bram_addr_ld_en, I2 => brst_cnt(6), I3 => brst_cnt(5), I4 => \brst_cnt[7]_i_4_n_0\, O => \brst_cnt[6]_i_1_n_0\ ); \brst_cnt[6]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axi_arlen_pipe(6), I1 => axi_araddr_full, I2 => s_axi_arlen(6), O => \brst_cnt[6]_i_2_n_0\ ); \brst_cnt[7]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => bram_addr_ld_en, I1 => I_WRAP_BRST_n_8, O => \brst_cnt[7]_i_1_n_0\ ); \brst_cnt[7]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"B8B8B88BB8B8B8B8" ) port map ( I0 => \brst_cnt[7]_i_3_n_0\, I1 => bram_addr_ld_en, I2 => brst_cnt(7), I3 => brst_cnt(6), I4 => brst_cnt(5), I5 => \brst_cnt[7]_i_4_n_0\, O => \brst_cnt[7]_i_2_n_0\ ); \brst_cnt[7]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axi_arlen_pipe(7), I1 => axi_araddr_full, I2 => s_axi_arlen(7), O => \brst_cnt[7]_i_3_n_0\ ); \brst_cnt[7]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"00000001" ) port map ( I0 => brst_cnt(4), I1 => brst_cnt(1), I2 => brst_cnt(0), I3 => brst_cnt(2), I4 => brst_cnt(3), O => \brst_cnt[7]_i_4_n_0\ ); brst_cnt_max_d1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => brst_cnt_max, Q => brst_cnt_max_d1, R => \^bram_rst_a\ ); \brst_cnt_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \brst_cnt[7]_i_1_n_0\, D => \brst_cnt[0]_i_1_n_0\, Q => brst_cnt(0), R => \^bram_rst_a\ ); \brst_cnt_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \brst_cnt[7]_i_1_n_0\, D => \brst_cnt[1]_i_1_n_0\, Q => brst_cnt(1), R => \^bram_rst_a\ ); \brst_cnt_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \brst_cnt[7]_i_1_n_0\, D => \brst_cnt[2]_i_1_n_0\, Q => brst_cnt(2), R => \^bram_rst_a\ ); \brst_cnt_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \brst_cnt[7]_i_1_n_0\, D => \brst_cnt[3]_i_1_n_0\, Q => brst_cnt(3), R => \^bram_rst_a\ ); \brst_cnt_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \brst_cnt[7]_i_1_n_0\, D => \brst_cnt[4]_i_1_n_0\, Q => brst_cnt(4), R => \^bram_rst_a\ ); \brst_cnt_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \brst_cnt[7]_i_1_n_0\, D => \brst_cnt[5]_i_1_n_0\, Q => brst_cnt(5), R => \^bram_rst_a\ ); \brst_cnt_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \brst_cnt[7]_i_1_n_0\, D => \brst_cnt[6]_i_1_n_0\, Q => brst_cnt(6), R => \^bram_rst_a\ ); \brst_cnt_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \brst_cnt[7]_i_1_n_0\, D => \brst_cnt[7]_i_2_n_0\, Q => brst_cnt(7), R => \^bram_rst_a\ ); brst_one_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"00000000F0EE0000" ) port map ( I0 => brst_one, I1 => brst_one_i_2_n_0, I2 => axi_rd_burst_two, I3 => bram_addr_ld_en, I4 => s_axi_aresetn, I5 => last_bram_addr_i_2_n_0, O => brst_one_i_1_n_0 ); brst_one_i_2: unisim.vcomponents.LUT3 generic map( INIT => X"08" ) port map ( I0 => last_bram_addr_i_5_n_0, I1 => brst_cnt(1), I2 => brst_cnt(0), O => brst_one_i_2_n_0 ); brst_one_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => brst_one_i_1_n_0, Q => brst_one, R => '0' ); brst_zero_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"00E0" ) port map ( I0 => brst_zero, I1 => last_bram_addr_i_2_n_0, I2 => s_axi_aresetn, I3 => brst_zero_i_2_n_0, O => brst_zero_i_1_n_0 ); brst_zero_i_2: unisim.vcomponents.LUT5 generic map( INIT => X"8A80AAAA" ) port map ( I0 => bram_addr_ld_en, I1 => axi_arlen_pipe(0), I2 => axi_araddr_full, I3 => s_axi_arlen(0), I4 => axi_rd_burst_i_2_n_0, O => brst_zero_i_2_n_0 ); brst_zero_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => brst_zero_i_1_n_0, Q => brst_zero, R => '0' ); curr_fixed_burst_reg_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"00053305" ) port map ( I0 => s_axi_arburst(0), I1 => axi_arburst_pipe(0), I2 => s_axi_arburst(1), I3 => axi_araddr_full, I4 => axi_arburst_pipe(1), O => curr_fixed_burst ); curr_fixed_burst_reg_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => bram_addr_ld_en, D => curr_fixed_burst, Q => curr_fixed_burst_reg, R => \^bram_rst_a\ ); curr_wrap_burst_reg_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"000ACC0A" ) port map ( I0 => s_axi_arburst(1), I1 => axi_arburst_pipe(1), I2 => s_axi_arburst(0), I3 => axi_araddr_full, I4 => axi_arburst_pipe(0), O => curr_wrap_burst ); curr_wrap_burst_reg_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => bram_addr_ld_en, D => curr_wrap_burst, Q => curr_wrap_burst_reg, R => \^bram_rst_a\ ); disable_b2b_brst_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF000D0000" ) port map ( I0 => axi_rd_burst, I1 => axi_rd_burst_two_reg_n_0, I2 => rd_data_sm_cs(2), I3 => rd_data_sm_cs(3), I4 => disable_b2b_brst_i_2_n_0, I5 => disable_b2b_brst_i_3_n_0, O => disable_b2b_brst_cmb ); disable_b2b_brst_i_2: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => rd_data_sm_cs(0), I1 => rd_data_sm_cs(1), O => disable_b2b_brst_i_2_n_0 ); disable_b2b_brst_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"EEEEEEE00EE0EEEE" ) port map ( I0 => disable_b2b_brst_i_4_n_0, I1 => disable_b2b_brst, I2 => rd_data_sm_cs(2), I3 => rd_data_sm_cs(1), I4 => rd_data_sm_cs(0), I5 => rd_data_sm_cs(3), O => disable_b2b_brst_i_3_n_0 ); disable_b2b_brst_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"0000FE0000000000" ) port map ( I0 => brst_zero, I1 => end_brst_rd, I2 => brst_one, I3 => rd_data_sm_cs(0), I4 => rd_adv_buf67_out, I5 => \rd_data_sm_cs[2]_i_3_n_0\, O => disable_b2b_brst_i_4_n_0 ); disable_b2b_brst_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => disable_b2b_brst_cmb, Q => disable_b2b_brst, R => \^bram_rst_a\ ); end_brst_rd_clr_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFCD00002200" ) port map ( I0 => rd_data_sm_cs(0), I1 => rd_data_sm_cs(1), I2 => bram_addr_ld_en, I3 => rd_data_sm_cs(2), I4 => rd_data_sm_cs(3), I5 => end_brst_rd_clr, O => end_brst_rd_clr_i_1_n_0 ); end_brst_rd_clr_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => end_brst_rd_clr_i_1_n_0, Q => end_brst_rd_clr, R => \^bram_rst_a\ ); end_brst_rd_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"0020F020" ) port map ( I0 => brst_cnt_max, I1 => brst_cnt_max_d1, I2 => s_axi_aresetn, I3 => end_brst_rd, I4 => end_brst_rd_clr, O => end_brst_rd_i_1_n_0 ); end_brst_rd_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => end_brst_rd_i_1_n_0, Q => end_brst_rd, R => '0' ); last_bram_addr_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FAAAAAAAAAAAAFAB" ) port map ( I0 => last_bram_addr_i_2_n_0, I1 => last_bram_addr_i_3_n_0, I2 => rd_data_sm_cs(2), I3 => last_bram_addr_i_4_n_0, I4 => rd_data_sm_cs(1), I5 => rd_data_sm_cs(0), O => last_bram_addr0 ); last_bram_addr_i_2: unisim.vcomponents.LUT3 generic map( INIT => X"08" ) port map ( I0 => last_bram_addr_i_5_n_0, I1 => brst_cnt(0), I2 => brst_cnt(1), O => last_bram_addr_i_2_n_0 ); last_bram_addr_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"7F7F707F7F7F7F7F" ) port map ( I0 => p_0_in13_in, I1 => rd_adv_buf67_out, I2 => rd_data_sm_cs(3), I3 => bram_addr_ld_en, I4 => I_WRAP_BRST_n_4, I5 => axi_rd_burst_i_2_n_0, O => last_bram_addr_i_3_n_0 ); last_bram_addr_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"A888200000000000" ) port map ( I0 => rd_adv_buf67_out, I1 => bram_addr_ld_en, I2 => pend_rd_op, I3 => p_0_in13_in, I4 => last_bram_addr_i_6_n_0, I5 => \rd_data_sm_cs[3]_i_6_n_0\, O => last_bram_addr_i_4_n_0 ); last_bram_addr_i_5: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000002" ) port map ( I0 => I_WRAP_BRST_n_8, I1 => brst_cnt(7), I2 => brst_cnt(3), I3 => brst_cnt(4), I4 => brst_cnt(2), I5 => last_bram_addr_i_7_n_0, O => last_bram_addr_i_5_n_0 ); last_bram_addr_i_6: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000001" ) port map ( I0 => last_bram_addr_i_8_n_0, I1 => last_bram_addr_i_9_n_0, I2 => I_WRAP_BRST_n_3, I3 => I_WRAP_BRST_n_5, I4 => I_WRAP_BRST_n_2, I5 => I_WRAP_BRST_n_4, O => last_bram_addr_i_6_n_0 ); last_bram_addr_i_7: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => brst_cnt(6), I1 => brst_cnt(5), O => last_bram_addr_i_7_n_0 ); last_bram_addr_i_8: unisim.vcomponents.LUT5 generic map( INIT => X"FFFACCFA" ) port map ( I0 => s_axi_arlen(4), I1 => axi_arlen_pipe(4), I2 => s_axi_arlen(5), I3 => axi_araddr_full, I4 => axi_arlen_pipe(5), O => last_bram_addr_i_8_n_0 ); last_bram_addr_i_9: unisim.vcomponents.LUT5 generic map( INIT => X"FFFACCFA" ) port map ( I0 => s_axi_arlen(6), I1 => axi_arlen_pipe(6), I2 => s_axi_arlen(7), I3 => axi_araddr_full, I4 => axi_arlen_pipe(7), O => last_bram_addr_i_9_n_0 ); last_bram_addr_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => last_bram_addr0, Q => last_bram_addr, R => \^bram_rst_a\ ); no_ar_ack_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"88C8AAAAAAAAAAAA" ) port map ( I0 => no_ar_ack, I1 => rd_data_sm_cs(1), I2 => bram_addr_ld_en, I3 => rd_adv_buf67_out, I4 => \rd_data_sm_cs[3]_i_6_n_0\, I5 => rd_data_sm_cs(0), O => no_ar_ack_i_1_n_0 ); no_ar_ack_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => no_ar_ack_i_1_n_0, Q => no_ar_ack, R => \^bram_rst_a\ ); pend_rd_op_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAFFFEAAAA0002" ) port map ( I0 => pend_rd_op_i_2_n_0, I1 => pend_rd_op_i_3_n_0, I2 => rd_data_sm_cs(3), I3 => rd_data_sm_cs(2), I4 => pend_rd_op_i_4_n_0, I5 => pend_rd_op, O => pend_rd_op_i_1_n_0 ); pend_rd_op_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0FFCC8C80CCCC8C8" ) port map ( I0 => p_0_in13_in, I1 => bram_addr_ld_en, I2 => rd_data_sm_cs(1), I3 => rd_data_sm_cs(0), I4 => rd_data_sm_cs(2), I5 => pend_rd_op_i_5_n_0, O => pend_rd_op_i_2_n_0 ); pend_rd_op_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"0303070733F3FFFF" ) port map ( I0 => p_0_in13_in, I1 => rd_data_sm_cs(0), I2 => rd_data_sm_cs(1), I3 => \^s_axi_rlast\, I4 => pend_rd_op, I5 => bram_addr_ld_en, O => pend_rd_op_i_3_n_0 ); pend_rd_op_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"0000000080FFD5FF" ) port map ( I0 => rd_data_sm_cs(0), I1 => rd_adv_buf67_out, I2 => pend_rd_op, I3 => rd_data_sm_cs(1), I4 => pend_rd_op_i_6_n_0, I5 => pend_rd_op_i_7_n_0, O => pend_rd_op_i_4_n_0 ); pend_rd_op_i_5: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => ar_active, I1 => end_brst_rd, O => pend_rd_op_i_5_n_0 ); pend_rd_op_i_6: unisim.vcomponents.LUT3 generic map( INIT => X"15" ) port map ( I0 => bram_addr_ld_en, I1 => end_brst_rd, I2 => ar_active, O => pend_rd_op_i_6_n_0 ); pend_rd_op_i_7: unisim.vcomponents.LUT4 generic map( INIT => X"F1FF" ) port map ( I0 => pend_rd_op_i_8_n_0, I1 => bram_addr_ld_en, I2 => rd_data_sm_cs(3), I3 => rd_data_sm_cs(2), O => pend_rd_op_i_7_n_0 ); pend_rd_op_i_8: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFF0008888" ) port map ( I0 => pend_rd_op, I1 => \^s_axi_rlast\, I2 => ar_active, I3 => end_brst_rd, I4 => rd_data_sm_cs(0), I5 => rd_data_sm_cs(1), O => pend_rd_op_i_8_n_0 ); pend_rd_op_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => pend_rd_op_i_1_n_0, Q => pend_rd_op, R => \^bram_rst_a\ ); \rd_data_sm_cs[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF54005555" ) port map ( I0 => \rd_data_sm_cs[0]_i_2_n_0\, I1 => pend_rd_op, I2 => bram_addr_ld_en, I3 => rd_adv_buf67_out, I4 => \rd_data_sm_cs[0]_i_3_n_0\, I5 => \rd_data_sm_cs[0]_i_4_n_0\, O => \rd_data_sm_cs[0]_i_1_n_0\ ); \rd_data_sm_cs[0]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"E000E0E0FFFFFFFF" ) port map ( I0 => act_rd_burst_two, I1 => act_rd_burst, I2 => disable_b2b_brst_i_2_n_0, I3 => bram_addr_ld_en, I4 => rd_adv_buf67_out, I5 => \rd_data_sm_cs[3]_i_6_n_0\, O => \rd_data_sm_cs[0]_i_2_n_0\ ); \rd_data_sm_cs[0]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => rd_data_sm_cs(1), I1 => rd_data_sm_cs(0), O => \rd_data_sm_cs[0]_i_3_n_0\ ); \rd_data_sm_cs[0]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"001100F7001100D5" ) port map ( I0 => rd_data_sm_cs(0), I1 => rd_data_sm_cs(1), I2 => rd_adv_buf67_out, I3 => rd_data_sm_cs(2), I4 => rd_data_sm_cs(3), I5 => p_0_in13_in, O => \rd_data_sm_cs[0]_i_4_n_0\ ); \rd_data_sm_cs[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAEAAAEFFFFAAAE" ) port map ( I0 => \rd_data_sm_cs[2]_i_2_n_0\, I1 => \rd_data_sm_cs[1]_i_2_n_0\, I2 => end_brst_rd, I3 => brst_zero, I4 => I_WRAP_BRST_n_25, I5 => \rd_data_sm_cs[2]_i_4_n_0\, O => \rd_data_sm_cs[1]_i_1_n_0\ ); \rd_data_sm_cs[1]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"04" ) port map ( I0 => rd_data_sm_cs(3), I1 => rd_data_sm_cs(2), I2 => rd_data_sm_cs(0), O => \rd_data_sm_cs[1]_i_2_n_0\ ); \rd_data_sm_cs[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFEEEAEAEA" ) port map ( I0 => \rd_data_sm_cs[2]_i_2_n_0\, I1 => \rd_data_sm_cs[2]_i_3_n_0\, I2 => \rd_data_sm_cs[2]_i_4_n_0\, I3 => p_0_in13_in, I4 => disable_b2b_brst_i_2_n_0, I5 => \rd_data_sm_cs[2]_i_5_n_0\, O => \rd_data_sm_cs[2]_i_1_n_0\ ); \rd_data_sm_cs[2]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"000007000F000000" ) port map ( I0 => \rd_data_sm_cs[3]_i_7_n_0\, I1 => bram_addr_ld_en, I2 => rd_data_sm_cs(3), I3 => rd_data_sm_cs(2), I4 => rd_data_sm_cs(1), I5 => rd_data_sm_cs(0), O => \rd_data_sm_cs[2]_i_2_n_0\ ); \rd_data_sm_cs[2]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => rd_data_sm_cs(3), I1 => rd_data_sm_cs(2), O => \rd_data_sm_cs[2]_i_3_n_0\ ); \rd_data_sm_cs[2]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"C8C8C8C808C8C8C8" ) port map ( I0 => axi_rd_burst_two_reg_n_0, I1 => rd_data_sm_cs(1), I2 => rd_data_sm_cs(0), I3 => s_axi_rready, I4 => \^s_axi_rvalid\, I5 => I_WRAP_BRST_n_27, O => \rd_data_sm_cs[2]_i_4_n_0\ ); \rd_data_sm_cs[2]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"0004000400040000" ) port map ( I0 => rd_data_sm_cs(3), I1 => rd_data_sm_cs(2), I2 => rd_data_sm_cs(1), I3 => rd_data_sm_cs(0), I4 => brst_zero, I5 => end_brst_rd, O => \rd_data_sm_cs[2]_i_5_n_0\ ); \rd_data_sm_cs[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"7444777730007444" ) port map ( I0 => \rd_data_sm_cs[3]_i_3_n_0\, I1 => \rd_data_sm_cs[3]_i_4_n_0\, I2 => s_axi_rready, I3 => \^s_axi_rvalid\, I4 => \rd_data_sm_cs[3]_i_5_n_0\, I5 => bram_addr_ld_en, O => rd_data_sm_ns ); \rd_data_sm_cs[3]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"00800000AA800000" ) port map ( I0 => \rd_data_sm_cs[3]_i_6_n_0\, I1 => bram_addr_ld_en, I2 => \rd_data_sm_cs[3]_i_7_n_0\, I3 => rd_data_sm_cs(1), I4 => rd_data_sm_cs(0), I5 => rd_adv_buf67_out, O => \rd_data_sm_cs[3]_i_2_n_0\ ); \rd_data_sm_cs[3]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"00000D0000000000" ) port map ( I0 => end_brst_rd, I1 => axi_b2b_brst, I2 => brst_zero, I3 => rd_adv_buf67_out, I4 => rd_data_sm_cs(3), I5 => \rd_data_sm_cs[0]_i_3_n_0\, O => \rd_data_sm_cs[3]_i_3_n_0\ ); \rd_data_sm_cs[3]_i_4\: unisim.vcomponents.LUT4 generic map( INIT => X"BFAD" ) port map ( I0 => rd_data_sm_cs(3), I1 => rd_data_sm_cs(1), I2 => rd_data_sm_cs(2), I3 => rd_data_sm_cs(0), O => \rd_data_sm_cs[3]_i_4_n_0\ ); \rd_data_sm_cs[3]_i_5\: unisim.vcomponents.LUT4 generic map( INIT => X"0053" ) port map ( I0 => rd_data_sm_cs(3), I1 => rd_data_sm_cs(1), I2 => rd_data_sm_cs(2), I3 => rd_data_sm_cs(0), O => \rd_data_sm_cs[3]_i_5_n_0\ ); \rd_data_sm_cs[3]_i_6\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => rd_data_sm_cs(2), I1 => rd_data_sm_cs(3), O => \rd_data_sm_cs[3]_i_6_n_0\ ); \rd_data_sm_cs[3]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"8880" ) port map ( I0 => s_axi_rready, I1 => \^s_axi_rvalid\, I2 => act_rd_burst_two, I3 => act_rd_burst, O => \rd_data_sm_cs[3]_i_7_n_0\ ); \rd_data_sm_cs_reg[0]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => rd_data_sm_ns, D => \rd_data_sm_cs[0]_i_1_n_0\, Q => rd_data_sm_cs(0), R => \^bram_rst_a\ ); \rd_data_sm_cs_reg[1]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => rd_data_sm_ns, D => \rd_data_sm_cs[1]_i_1_n_0\, Q => rd_data_sm_cs(1), R => \^bram_rst_a\ ); \rd_data_sm_cs_reg[2]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => rd_data_sm_ns, D => \rd_data_sm_cs[2]_i_1_n_0\, Q => rd_data_sm_cs(2), R => \^bram_rst_a\ ); \rd_data_sm_cs_reg[3]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => rd_data_sm_ns, D => \rd_data_sm_cs[3]_i_2_n_0\, Q => rd_data_sm_cs(3), R => \^bram_rst_a\ ); rd_skid_buf_ld_reg_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"1000111111110000" ) port map ( I0 => rd_data_sm_cs(3), I1 => rd_data_sm_cs(2), I2 => \^s_axi_rvalid\, I3 => s_axi_rready, I4 => rd_data_sm_cs(1), I5 => rd_data_sm_cs(0), O => rd_skid_buf_ld_cmb ); rd_skid_buf_ld_reg_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => rd_skid_buf_ld_cmb, Q => rd_skid_buf_ld_reg, R => \^bram_rst_a\ ); rddata_mux_sel_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"FE02" ) port map ( I0 => rddata_mux_sel_cmb, I1 => rd_data_sm_cs(3), I2 => rddata_mux_sel_i_3_n_0, I3 => rddata_mux_sel, O => rddata_mux_sel_i_1_n_0 ); rddata_mux_sel_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"D208D208D208F208" ) port map ( I0 => rd_data_sm_cs(0), I1 => rd_data_sm_cs(1), I2 => rd_adv_buf67_out, I3 => rd_data_sm_cs(2), I4 => act_rd_burst, I5 => act_rd_burst_two, O => rddata_mux_sel_cmb ); rddata_mux_sel_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"A007AF07AF07AF07" ) port map ( I0 => rd_data_sm_cs(1), I1 => axi_rd_burst_two_reg_n_0, I2 => rd_data_sm_cs(0), I3 => rd_data_sm_cs(2), I4 => \^s_axi_rvalid\, I5 => s_axi_rready, O => rddata_mux_sel_i_3_n_0 ); rddata_mux_sel_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => rddata_mux_sel_i_1_n_0, Q => rddata_mux_sel, R => \^bram_rst_a\ ); s_axi_arready_INST_0: unisim.vcomponents.LUT4 generic map( INIT => X"EAAA" ) port map ( I0 => axi_arready_int, I1 => \^s_axi_rvalid\, I2 => s_axi_rready, I3 => axi_early_arready_int, O => s_axi_arready ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zqynq_lab_1_design_axi_bram_ctrl_0_0_wr_chnl is port ( axi_aresetn_d2 : out STD_LOGIC; axi_aresetn_re_reg : out STD_LOGIC; bram_en_a : out STD_LOGIC; bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_bvalid : out STD_LOGIC; \GEN_AW_DUAL.aw_active_reg_0\ : out STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 ); bram_addr_a : out STD_LOGIC_VECTOR ( 13 downto 0 ); bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_aresetn_0 : in STD_LOGIC; s_axi_aclk : in STD_LOGIC; s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 ); s_axi_aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wvalid : in STD_LOGIC; s_axi_wlast : in STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_bram_ctrl_0_0_wr_chnl : entity is "wr_chnl"; end zqynq_lab_1_design_axi_bram_ctrl_0_0_wr_chnl; architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0_wr_chnl is signal BID_FIFO_n_1 : STD_LOGIC; signal BID_FIFO_n_4 : STD_LOGIC; signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0\ : STD_LOGIC; signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0\ : STD_LOGIC; signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0\ : STD_LOGIC; signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0\ : STD_LOGIC; signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0\ : STD_LOGIC; signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0\ : STD_LOGIC; signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\ : STD_LOGIC; signal \GEN_AWREADY.axi_awready_int_i_1_n_0\ : STD_LOGIC; signal \GEN_AWREADY.axi_awready_int_i_2_n_0\ : STD_LOGIC; signal \GEN_AWREADY.axi_awready_int_i_3_n_0\ : STD_LOGIC; signal \GEN_AW_DUAL.aw_active_i_2_n_0\ : STD_LOGIC; signal \^gen_aw_dual.aw_active_reg_0\ : STD_LOGIC; signal \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0\ : STD_LOGIC; signal \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0\ : STD_LOGIC; signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\ : STD_LOGIC; signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\ : STD_LOGIC; signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\ : STD_LOGIC; signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\ : STD_LOGIC; signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\ : STD_LOGIC; signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\ : STD_LOGIC; signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\ : STD_LOGIC; signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\ : STD_LOGIC; signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\ : STD_LOGIC; signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\ : STD_LOGIC; signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\ : STD_LOGIC; signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\ : STD_LOGIC; signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\ : STD_LOGIC; signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\ : STD_LOGIC; signal \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0\ : STD_LOGIC; signal \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0\ : STD_LOGIC; signal \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\ : STD_LOGIC; signal \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\ : STD_LOGIC; signal \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\ : STD_LOGIC; signal \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0\ : STD_LOGIC; signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0\ : STD_LOGIC; signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\ : STD_LOGIC; signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0\ : STD_LOGIC; signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0\ : STD_LOGIC; signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0\ : STD_LOGIC; signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0\ : STD_LOGIC; signal \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\ : STD_LOGIC; signal \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\ : STD_LOGIC; signal \I_RD_CHNL/axi_aresetn_d1\ : STD_LOGIC; signal I_WRAP_BRST_n_0 : STD_LOGIC; signal I_WRAP_BRST_n_10 : STD_LOGIC; signal I_WRAP_BRST_n_11 : STD_LOGIC; signal I_WRAP_BRST_n_12 : STD_LOGIC; signal I_WRAP_BRST_n_13 : STD_LOGIC; signal I_WRAP_BRST_n_14 : STD_LOGIC; signal I_WRAP_BRST_n_15 : STD_LOGIC; signal I_WRAP_BRST_n_16 : STD_LOGIC; signal I_WRAP_BRST_n_17 : STD_LOGIC; signal I_WRAP_BRST_n_19 : STD_LOGIC; signal I_WRAP_BRST_n_2 : STD_LOGIC; signal I_WRAP_BRST_n_20 : STD_LOGIC; signal I_WRAP_BRST_n_21 : STD_LOGIC; signal I_WRAP_BRST_n_22 : STD_LOGIC; signal I_WRAP_BRST_n_23 : STD_LOGIC; signal I_WRAP_BRST_n_24 : STD_LOGIC; signal I_WRAP_BRST_n_25 : STD_LOGIC; signal I_WRAP_BRST_n_7 : STD_LOGIC; signal I_WRAP_BRST_n_8 : STD_LOGIC; signal I_WRAP_BRST_n_9 : STD_LOGIC; signal aw_active : STD_LOGIC; signal \^axi_aresetn_d2\ : STD_LOGIC; signal axi_aresetn_re : STD_LOGIC; signal \^axi_aresetn_re_reg\ : STD_LOGIC; signal axi_awaddr_full : STD_LOGIC; signal axi_awburst_pipe : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_awid_pipe : STD_LOGIC; signal axi_awlen_pipe : STD_LOGIC_VECTOR ( 7 downto 0 ); signal axi_awlen_pipe_1_or_2 : STD_LOGIC; signal axi_awsize_pipe : STD_LOGIC_VECTOR ( 1 to 1 ); signal axi_bvalid_int_i_1_n_0 : STD_LOGIC; signal axi_wdata_full_cmb : STD_LOGIC; signal axi_wdata_full_cmb114_out : STD_LOGIC; signal axi_wdata_full_reg : STD_LOGIC; signal axi_wr_burst : STD_LOGIC; signal axi_wr_burst_cmb : STD_LOGIC; signal axi_wr_burst_cmb0 : STD_LOGIC; signal axi_wr_burst_i_1_n_0 : STD_LOGIC; signal axi_wr_burst_i_3_n_0 : STD_LOGIC; signal axi_wready_int_mod_i_1_n_0 : STD_LOGIC; signal axi_wready_int_mod_i_3_n_0 : STD_LOGIC; signal bid_gets_fifo_load : STD_LOGIC; signal bid_gets_fifo_load_d1 : STD_LOGIC; signal bid_gets_fifo_load_d1_i_2_n_0 : STD_LOGIC; signal \^bram_addr_a\ : STD_LOGIC_VECTOR ( 13 downto 0 ); signal bram_addr_inc : STD_LOGIC; signal bram_addr_ld : STD_LOGIC_VECTOR ( 13 downto 10 ); signal bram_addr_ld_en : STD_LOGIC; signal bram_addr_ld_en_mod : STD_LOGIC; signal bram_addr_rst_cmb : STD_LOGIC; signal bram_en_cmb : STD_LOGIC; signal bvalid_cnt : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \bvalid_cnt[0]_i_1_n_0\ : STD_LOGIC; signal \bvalid_cnt[1]_i_1_n_0\ : STD_LOGIC; signal \bvalid_cnt[2]_i_1_n_0\ : STD_LOGIC; signal bvalid_cnt_inc : STD_LOGIC; signal bvalid_cnt_inc11_out : STD_LOGIC; signal clr_bram_we : STD_LOGIC; signal clr_bram_we_cmb : STD_LOGIC; signal curr_awlen_reg_1_or_2 : STD_LOGIC; signal curr_awlen_reg_1_or_20 : STD_LOGIC; signal curr_awlen_reg_1_or_2_i_2_n_0 : STD_LOGIC; signal curr_fixed_burst : STD_LOGIC; signal curr_fixed_burst_reg : STD_LOGIC; signal curr_wrap_burst : STD_LOGIC; signal curr_wrap_burst_reg : STD_LOGIC; signal delay_aw_active_clr : STD_LOGIC; signal last_data_ack_mod : STD_LOGIC; signal p_18_out : STD_LOGIC; signal p_9_out : STD_LOGIC; signal \^s_axi_awready\ : STD_LOGIC; signal \^s_axi_bid\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^s_axi_bvalid\ : STD_LOGIC; signal \^s_axi_wready\ : STD_LOGIC; signal wr_addr_sm_cs : STD_LOGIC; signal wr_data_sm_cs : STD_LOGIC_VECTOR ( 2 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of wr_data_sm_cs : signal is "yes"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1\ : label is "soft_lutpair53"; attribute SOFT_HLUTNM of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_3\ : label is "soft_lutpair51"; attribute SOFT_HLUTNM of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1\ : label is "soft_lutpair53"; attribute KEEP : string; attribute KEEP of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[0]\ : label is "yes"; attribute KEEP of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[1]\ : label is "yes"; attribute KEEP of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[2]\ : label is "yes"; attribute SOFT_HLUTNM of \GEN_AW_DUAL.last_data_ack_mod_i_1\ : label is "soft_lutpair52"; attribute SOFT_HLUTNM of \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2\ : label is "soft_lutpair52"; attribute SOFT_HLUTNM of bid_gets_fifo_load_d1_i_2 : label is "soft_lutpair51"; attribute SOFT_HLUTNM of curr_fixed_burst_reg_i_2 : label is "soft_lutpair50"; attribute SOFT_HLUTNM of curr_wrap_burst_reg_i_2 : label is "soft_lutpair50"; begin \GEN_AW_DUAL.aw_active_reg_0\ <= \^gen_aw_dual.aw_active_reg_0\; axi_aresetn_d2 <= \^axi_aresetn_d2\; axi_aresetn_re_reg <= \^axi_aresetn_re_reg\; bram_addr_a(13 downto 0) <= \^bram_addr_a\(13 downto 0); s_axi_awready <= \^s_axi_awready\; s_axi_bid(0) <= \^s_axi_bid\(0); s_axi_bvalid <= \^s_axi_bvalid\; s_axi_wready <= \^s_axi_wready\; BID_FIFO: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_0_SRL_FIFO port map ( \GEN_AWREADY.axi_aresetn_d2_reg\ => \^axi_aresetn_d2\, \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\, aw_active => aw_active, axi_awaddr_full => axi_awaddr_full, axi_awid_pipe => axi_awid_pipe, axi_awlen_pipe_1_or_2 => axi_awlen_pipe_1_or_2, \axi_bid_int_reg[0]\ => BID_FIFO_n_4, axi_bvalid_int_reg => \^s_axi_bvalid\, axi_wdata_full_cmb114_out => axi_wdata_full_cmb114_out, axi_wr_burst => axi_wr_burst, bid_gets_fifo_load => bid_gets_fifo_load, bid_gets_fifo_load_d1 => bid_gets_fifo_load_d1, bid_gets_fifo_load_d1_reg => BID_FIFO_n_1, bram_addr_ld_en => bram_addr_ld_en, bvalid_cnt(2 downto 0) => bvalid_cnt(2 downto 0), bvalid_cnt_inc => bvalid_cnt_inc, \bvalid_cnt_reg[1]\ => bid_gets_fifo_load_d1_i_2_n_0, \bvalid_cnt_reg[2]\ => I_WRAP_BRST_n_20, \bvalid_cnt_reg[2]_0\ => I_WRAP_BRST_n_19, curr_awlen_reg_1_or_2 => curr_awlen_reg_1_or_2, last_data_ack_mod => last_data_ack_mod, \out\(2 downto 0) => wr_data_sm_cs(2 downto 0), s_axi_aclk => s_axi_aclk, s_axi_aresetn => s_axi_aresetn_0, s_axi_awid(0) => s_axi_awid(0), s_axi_awready => \^s_axi_awready\, s_axi_awvalid => s_axi_awvalid, s_axi_bid(0) => \^s_axi_bid\(0), s_axi_bready => s_axi_bready, s_axi_wlast => s_axi_wlast, s_axi_wvalid => s_axi_wvalid, wr_addr_sm_cs => wr_addr_sm_cs ); \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0\, I1 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\, I2 => wr_data_sm_cs(0), O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0\ ); \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"05051F1A" ) port map ( I0 => wr_data_sm_cs(1), I1 => axi_wr_burst_cmb0, I2 => wr_data_sm_cs(0), I3 => axi_wdata_full_cmb114_out, I4 => wr_data_sm_cs(2), O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0\ ); \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"5515" ) port map ( I0 => I_WRAP_BRST_n_21, I1 => bvalid_cnt(2), I2 => bvalid_cnt(1), I3 => bvalid_cnt(0), O => axi_wr_burst_cmb0 ); \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0\, I1 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\, I2 => wr_data_sm_cs(1), O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0\ ); \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"0000554000555540" ) port map ( I0 => wr_data_sm_cs(1), I1 => s_axi_wlast, I2 => axi_wdata_full_cmb114_out, I3 => wr_data_sm_cs(0), I4 => wr_data_sm_cs(2), I5 => axi_wr_burst, O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0\ ); \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0\, I1 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\, I2 => wr_data_sm_cs(2), O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0\ ); \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"44010001" ) port map ( I0 => wr_data_sm_cs(2), I1 => wr_data_sm_cs(1), I2 => axi_wdata_full_cmb114_out, I3 => wr_data_sm_cs(0), I4 => s_axi_wvalid, O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0\ ); \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"7774777774744444" ) port map ( I0 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\, I1 => wr_data_sm_cs(2), I2 => wr_data_sm_cs(1), I3 => s_axi_wlast, I4 => wr_data_sm_cs(0), I5 => s_axi_wvalid, O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\ ); \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[0]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0\, Q => wr_data_sm_cs(0), R => s_axi_aresetn_0 ); \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[1]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0\, Q => wr_data_sm_cs(1), R => s_axi_aresetn_0 ); \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[2]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0\, Q => wr_data_sm_cs(2), R => s_axi_aresetn_0 ); \GEN_AWREADY.axi_aresetn_d1_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => s_axi_aresetn, Q => \I_RD_CHNL/axi_aresetn_d1\, R => '0' ); \GEN_AWREADY.axi_aresetn_d2_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \I_RD_CHNL/axi_aresetn_d1\, Q => \^axi_aresetn_d2\, R => '0' ); \GEN_AWREADY.axi_aresetn_re_reg_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => s_axi_aresetn, I1 => \I_RD_CHNL/axi_aresetn_d1\, O => axi_aresetn_re ); \GEN_AWREADY.axi_aresetn_re_reg_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => axi_aresetn_re, Q => \^axi_aresetn_re_reg\, R => '0' ); \GEN_AWREADY.axi_awready_int_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFBFBFFFFFAA00" ) port map ( I0 => axi_awaddr_full, I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\, I2 => \^axi_aresetn_d2\, I3 => bram_addr_ld_en, I4 => \^axi_aresetn_re_reg\, I5 => \^s_axi_awready\, O => \GEN_AWREADY.axi_awready_int_i_1_n_0\ ); \GEN_AWREADY.axi_awready_int_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"5444444400000000" ) port map ( I0 => \GEN_AWREADY.axi_awready_int_i_3_n_0\, I1 => aw_active, I2 => bvalid_cnt(1), I3 => bvalid_cnt(0), I4 => bvalid_cnt(2), I5 => s_axi_awvalid, O => \GEN_AWREADY.axi_awready_int_i_2_n_0\ ); \GEN_AWREADY.axi_awready_int_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"AABABABABABABABA" ) port map ( I0 => wr_addr_sm_cs, I1 => I_WRAP_BRST_n_21, I2 => last_data_ack_mod, I3 => bvalid_cnt(2), I4 => bvalid_cnt(0), I5 => bvalid_cnt(1), O => \GEN_AWREADY.axi_awready_int_i_3_n_0\ ); \GEN_AWREADY.axi_awready_int_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \GEN_AWREADY.axi_awready_int_i_1_n_0\, Q => \^s_axi_awready\, R => s_axi_aresetn_0 ); \GEN_AW_DUAL.aw_active_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^axi_aresetn_d2\, O => \^gen_aw_dual.aw_active_reg_0\ ); \GEN_AW_DUAL.aw_active_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF7FFFFFF0000" ) port map ( I0 => wr_data_sm_cs(1), I1 => wr_data_sm_cs(0), I2 => wr_data_sm_cs(2), I3 => delay_aw_active_clr, I4 => bram_addr_ld_en, I5 => aw_active, O => \GEN_AW_DUAL.aw_active_i_2_n_0\ ); \GEN_AW_DUAL.aw_active_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \GEN_AW_DUAL.aw_active_i_2_n_0\, Q => aw_active, R => \^gen_aw_dual.aw_active_reg_0\ ); \GEN_AW_DUAL.last_data_ack_mod_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"80" ) port map ( I0 => \^s_axi_wready\, I1 => s_axi_wlast, I2 => s_axi_wvalid, O => p_18_out ); \GEN_AW_DUAL.last_data_ack_mod_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => p_18_out, Q => last_data_ack_mod, R => s_axi_aresetn_0 ); \GEN_AW_DUAL.wr_addr_sm_cs_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0010001000100000" ) port map ( I0 => \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0\, I1 => wr_addr_sm_cs, I2 => s_axi_awvalid, I3 => axi_awaddr_full, I4 => I_WRAP_BRST_n_20, I5 => aw_active, O => \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0\ ); \GEN_AW_DUAL.wr_addr_sm_cs_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000040" ) port map ( I0 => I_WRAP_BRST_n_20, I1 => last_data_ack_mod, I2 => axi_awaddr_full, I3 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\, I4 => axi_awlen_pipe_1_or_2, I5 => curr_awlen_reg_1_or_2, O => \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0\ ); \GEN_AW_DUAL.wr_addr_sm_cs_reg\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0\, Q => wr_addr_sm_cs, R => \^gen_aw_dual.aw_active_reg_0\ ); \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awaddr(8), Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\, R => '0' ); \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awaddr(9), Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\, R => '0' ); \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awaddr(10), Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\, R => '0' ); \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awaddr(11), Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\, R => '0' ); \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awaddr(12), Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\, R => '0' ); \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awaddr(13), Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\, R => '0' ); \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awaddr(0), Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\, R => '0' ); \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awaddr(1), Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\, R => '0' ); \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awaddr(2), Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\, R => '0' ); \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awaddr(3), Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\, R => '0' ); \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awaddr(4), Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\, R => '0' ); \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awaddr(5), Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\, R => '0' ); \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awaddr(6), Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\, R => '0' ); \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awaddr(7), Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\, R => '0' ); \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"4000EA00" ) port map ( I0 => axi_awaddr_full, I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\, I2 => \^axi_aresetn_d2\, I3 => s_axi_aresetn, I4 => bram_addr_ld_en, O => \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0\ ); \GEN_AW_PIPE_DUAL.axi_awaddr_full_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0\, Q => axi_awaddr_full, R => '0' ); \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"BF00BF00BF00FF40" ) port map ( I0 => axi_awaddr_full, I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\, I2 => \^axi_aresetn_d2\, I3 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\, I4 => s_axi_awburst(0), I5 => s_axi_awburst(1), O => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0\ ); \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0\, Q => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\, R => '0' ); \GEN_AW_PIPE_DUAL.axi_awburst_pipe_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awburst(0), Q => axi_awburst_pipe(0), R => '0' ); \GEN_AW_PIPE_DUAL.axi_awburst_pipe_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awburst(1), Q => axi_awburst_pipe(1), R => '0' ); \GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awid(0), Q => axi_awid_pipe, R => '0' ); \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"40" ) port map ( I0 => axi_awaddr_full, I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\, I2 => \^axi_aresetn_d2\, O => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\ ); \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0002" ) port map ( I0 => \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\, I1 => s_axi_awlen(3), I2 => s_axi_awlen(2), I3 => s_axi_awlen(1), O => p_9_out ); \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => s_axi_awlen(4), I1 => s_axi_awlen(6), I2 => s_axi_awlen(7), I3 => s_axi_awlen(5), O => \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\ ); \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => p_9_out, Q => axi_awlen_pipe_1_or_2, R => '0' ); \GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awlen(0), Q => axi_awlen_pipe(0), R => '0' ); \GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awlen(1), Q => axi_awlen_pipe(1), R => '0' ); \GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awlen(2), Q => axi_awlen_pipe(2), R => '0' ); \GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awlen(3), Q => axi_awlen_pipe(3), R => '0' ); \GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awlen(4), Q => axi_awlen_pipe(4), R => '0' ); \GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awlen(5), Q => axi_awlen_pipe(5), R => '0' ); \GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awlen(6), Q => axi_awlen_pipe(6), R => '0' ); \GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awlen(7), Q => axi_awlen_pipe(7), R => '0' ); \GEN_AW_PIPE_DUAL.axi_awsize_pipe_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => '1', Q => axi_awsize_pipe(1), R => '0' ); \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFFFFFFFFFF" ) port map ( I0 => \^bram_addr_a\(4), I1 => \^bram_addr_a\(1), I2 => \^bram_addr_a\(0), I3 => \^bram_addr_a\(2), I4 => \^bram_addr_a\(3), I5 => \^bram_addr_a\(5), O => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0\ ); \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0\: unisim.vcomponents.LUT5 generic map( INIT => X"F7FFFFFF" ) port map ( I0 => \^bram_addr_a\(6), I1 => \^bram_addr_a\(4), I2 => I_WRAP_BRST_n_17, I3 => \^bram_addr_a\(5), I4 => \^bram_addr_a\(7), O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0\ ); \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4\: unisim.vcomponents.LUT4 generic map( INIT => X"1000" ) port map ( I0 => wr_data_sm_cs(1), I1 => wr_data_sm_cs(2), I2 => wr_data_sm_cs(0), I3 => s_axi_wvalid, O => bram_addr_inc ); \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5\: unisim.vcomponents.LUT4 generic map( INIT => X"1000" ) port map ( I0 => s_axi_wvalid, I1 => wr_data_sm_cs(2), I2 => wr_data_sm_cs(0), I3 => wr_data_sm_cs(1), O => bram_addr_rst_cmb ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => I_WRAP_BRST_n_2, D => I_WRAP_BRST_n_8, Q => \^bram_addr_a\(8), R => I_WRAP_BRST_n_0 ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => I_WRAP_BRST_n_2, D => I_WRAP_BRST_n_7, Q => \^bram_addr_a\(9), R => I_WRAP_BRST_n_0 ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => bram_addr_ld_en_mod, D => bram_addr_ld(10), Q => \^bram_addr_a\(10), R => I_WRAP_BRST_n_0 ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => bram_addr_ld_en_mod, D => bram_addr_ld(11), Q => \^bram_addr_a\(11), R => I_WRAP_BRST_n_0 ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => bram_addr_ld_en_mod, D => bram_addr_ld(12), Q => \^bram_addr_a\(12), R => I_WRAP_BRST_n_0 ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => bram_addr_ld_en_mod, D => bram_addr_ld(13), Q => \^bram_addr_a\(13), R => I_WRAP_BRST_n_0 ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => I_WRAP_BRST_n_2, D => I_WRAP_BRST_n_16, Q => \^bram_addr_a\(0), R => I_WRAP_BRST_n_0 ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => I_WRAP_BRST_n_2, D => I_WRAP_BRST_n_15, Q => \^bram_addr_a\(1), R => I_WRAP_BRST_n_0 ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => I_WRAP_BRST_n_2, D => I_WRAP_BRST_n_14, Q => \^bram_addr_a\(2), R => I_WRAP_BRST_n_0 ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => I_WRAP_BRST_n_2, D => I_WRAP_BRST_n_13, Q => \^bram_addr_a\(3), R => I_WRAP_BRST_n_0 ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => I_WRAP_BRST_n_2, D => I_WRAP_BRST_n_12, Q => \^bram_addr_a\(4), R => I_WRAP_BRST_n_0 ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => I_WRAP_BRST_n_2, D => I_WRAP_BRST_n_11, Q => \^bram_addr_a\(5), R => I_WRAP_BRST_n_0 ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => I_WRAP_BRST_n_2, D => I_WRAP_BRST_n_10, Q => \^bram_addr_a\(6), R => I_WRAP_BRST_n_0 ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => I_WRAP_BRST_n_2, D => I_WRAP_BRST_n_9, Q => \^bram_addr_a\(7), R => I_WRAP_BRST_n_0 ); \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.axi_wdata_full_reg_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"15FF1500" ) port map ( I0 => axi_wdata_full_cmb114_out, I1 => axi_awaddr_full, I2 => bram_addr_ld_en, I3 => wr_data_sm_cs(2), I4 => axi_wready_int_mod_i_3_n_0, O => axi_wdata_full_cmb ); \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.axi_wdata_full_reg_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => axi_wdata_full_cmb, Q => axi_wdata_full_reg, R => s_axi_aresetn_0 ); \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"4777477444444444" ) port map ( I0 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\, I1 => wr_data_sm_cs(2), I2 => wr_data_sm_cs(1), I3 => wr_data_sm_cs(0), I4 => axi_wdata_full_cmb114_out, I5 => s_axi_wvalid, O => bram_en_cmb ); \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"15" ) port map ( I0 => axi_wdata_full_cmb114_out, I1 => axi_awaddr_full, I2 => bram_addr_ld_en, O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\ ); \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => bram_en_cmb, Q => bram_en_a, R => s_axi_aresetn_0 ); \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0010001000101110" ) port map ( I0 => wr_data_sm_cs(0), I1 => wr_data_sm_cs(1), I2 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0\, I3 => wr_data_sm_cs(2), I4 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\, I5 => axi_wr_burst, O => clr_bram_we_cmb ); \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"80" ) port map ( I0 => axi_wdata_full_cmb114_out, I1 => s_axi_wlast, I2 => s_axi_wvalid, O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0\ ); \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => clr_bram_we_cmb, Q => clr_bram_we, R => s_axi_aresetn_0 ); \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FEAAFEFF02AA0200" ) port map ( I0 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0\, I1 => axi_wr_burst, I2 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\, I3 => wr_data_sm_cs(2), I4 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0\, I5 => delay_aw_active_clr, O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0\ ); \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"0000222E" ) port map ( I0 => s_axi_wlast, I1 => wr_data_sm_cs(2), I2 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\, I3 => wr_data_sm_cs(0), I4 => wr_data_sm_cs(1), O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0\ ); \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"8B338B0088008800" ) port map ( I0 => delay_aw_active_clr, I1 => wr_data_sm_cs(1), I2 => axi_wr_burst_cmb0, I3 => wr_data_sm_cs(0), I4 => axi_wdata_full_cmb114_out, I5 => bvalid_cnt_inc11_out, O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0\ ); \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => s_axi_wvalid, I1 => s_axi_wlast, O => bvalid_cnt_inc11_out ); \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0\, Q => delay_aw_active_clr, R => s_axi_aresetn_0 ); \GEN_WRDATA[0].bram_wrdata_int_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(0), Q => bram_wrdata_a(0), R => '0' ); \GEN_WRDATA[10].bram_wrdata_int_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(10), Q => bram_wrdata_a(10), R => '0' ); \GEN_WRDATA[11].bram_wrdata_int_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(11), Q => bram_wrdata_a(11), R => '0' ); \GEN_WRDATA[12].bram_wrdata_int_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(12), Q => bram_wrdata_a(12), R => '0' ); \GEN_WRDATA[13].bram_wrdata_int_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(13), Q => bram_wrdata_a(13), R => '0' ); \GEN_WRDATA[14].bram_wrdata_int_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(14), Q => bram_wrdata_a(14), R => '0' ); \GEN_WRDATA[15].bram_wrdata_int_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(15), Q => bram_wrdata_a(15), R => '0' ); \GEN_WRDATA[16].bram_wrdata_int_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(16), Q => bram_wrdata_a(16), R => '0' ); \GEN_WRDATA[17].bram_wrdata_int_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(17), Q => bram_wrdata_a(17), R => '0' ); \GEN_WRDATA[18].bram_wrdata_int_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(18), Q => bram_wrdata_a(18), R => '0' ); \GEN_WRDATA[19].bram_wrdata_int_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(19), Q => bram_wrdata_a(19), R => '0' ); \GEN_WRDATA[1].bram_wrdata_int_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(1), Q => bram_wrdata_a(1), R => '0' ); \GEN_WRDATA[20].bram_wrdata_int_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(20), Q => bram_wrdata_a(20), R => '0' ); \GEN_WRDATA[21].bram_wrdata_int_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(21), Q => bram_wrdata_a(21), R => '0' ); \GEN_WRDATA[22].bram_wrdata_int_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(22), Q => bram_wrdata_a(22), R => '0' ); \GEN_WRDATA[23].bram_wrdata_int_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(23), Q => bram_wrdata_a(23), R => '0' ); \GEN_WRDATA[24].bram_wrdata_int_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(24), Q => bram_wrdata_a(24), R => '0' ); \GEN_WRDATA[25].bram_wrdata_int_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(25), Q => bram_wrdata_a(25), R => '0' ); \GEN_WRDATA[26].bram_wrdata_int_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(26), Q => bram_wrdata_a(26), R => '0' ); \GEN_WRDATA[27].bram_wrdata_int_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(27), Q => bram_wrdata_a(27), R => '0' ); \GEN_WRDATA[28].bram_wrdata_int_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(28), Q => bram_wrdata_a(28), R => '0' ); \GEN_WRDATA[29].bram_wrdata_int_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(29), Q => bram_wrdata_a(29), R => '0' ); \GEN_WRDATA[2].bram_wrdata_int_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(2), Q => bram_wrdata_a(2), R => '0' ); \GEN_WRDATA[30].bram_wrdata_int_reg[30]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(30), Q => bram_wrdata_a(30), R => '0' ); \GEN_WRDATA[31].bram_wrdata_int_reg[31]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(31), Q => bram_wrdata_a(31), R => '0' ); \GEN_WRDATA[3].bram_wrdata_int_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(3), Q => bram_wrdata_a(3), R => '0' ); \GEN_WRDATA[4].bram_wrdata_int_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(4), Q => bram_wrdata_a(4), R => '0' ); \GEN_WRDATA[5].bram_wrdata_int_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(5), Q => bram_wrdata_a(5), R => '0' ); \GEN_WRDATA[6].bram_wrdata_int_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(6), Q => bram_wrdata_a(6), R => '0' ); \GEN_WRDATA[7].bram_wrdata_int_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(7), Q => bram_wrdata_a(7), R => '0' ); \GEN_WRDATA[8].bram_wrdata_int_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(8), Q => bram_wrdata_a(8), R => '0' ); \GEN_WRDATA[9].bram_wrdata_int_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(9), Q => bram_wrdata_a(9), R => '0' ); \GEN_WR_NO_ECC.bram_we_int[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"D0FF" ) port map ( I0 => s_axi_wvalid, I1 => wr_data_sm_cs(2), I2 => clr_bram_we, I3 => s_axi_aresetn, O => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\ ); \GEN_WR_NO_ECC.bram_we_int[3]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => s_axi_wvalid, I1 => wr_data_sm_cs(2), O => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\ ); \GEN_WR_NO_ECC.bram_we_int_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wstrb(0), Q => bram_we_a(0), R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\ ); \GEN_WR_NO_ECC.bram_we_int_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wstrb(1), Q => bram_we_a(1), R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\ ); \GEN_WR_NO_ECC.bram_we_int_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wstrb(2), Q => bram_we_a(2), R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\ ); \GEN_WR_NO_ECC.bram_we_int_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wstrb(3), Q => bram_we_a(3), R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\ ); I_WRAP_BRST: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst port map ( D(13 downto 10) => bram_addr_ld(13 downto 10), D(9) => I_WRAP_BRST_n_7, D(8) => I_WRAP_BRST_n_8, D(7) => I_WRAP_BRST_n_9, D(6) => I_WRAP_BRST_n_10, D(5) => I_WRAP_BRST_n_11, D(4) => I_WRAP_BRST_n_12, D(3) => I_WRAP_BRST_n_13, D(2) => I_WRAP_BRST_n_14, D(1) => I_WRAP_BRST_n_15, D(0) => I_WRAP_BRST_n_16, E(0) => I_WRAP_BRST_n_2, \GEN_AWREADY.axi_aresetn_d2_reg\ => \^axi_aresetn_d2\, \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\, \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\, \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\, \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\, \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\, \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\, \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\, \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\, \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\, \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\, \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\, \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\, \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\, \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\, \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\, \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0\, \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ => I_WRAP_BRST_n_17, \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0\, Q(3 downto 0) => axi_awlen_pipe(3 downto 0), SR(0) => I_WRAP_BRST_n_0, aw_active => aw_active, axi_awaddr_full => axi_awaddr_full, axi_awlen_pipe_1_or_2 => axi_awlen_pipe_1_or_2, axi_awsize_pipe(0) => axi_awsize_pipe(1), bram_addr_a(9 downto 0) => \^bram_addr_a\(9 downto 0), bram_addr_inc => bram_addr_inc, bram_addr_ld_en => bram_addr_ld_en, bram_addr_ld_en_mod => bram_addr_ld_en_mod, bram_addr_rst_cmb => bram_addr_rst_cmb, bvalid_cnt(2 downto 0) => bvalid_cnt(2 downto 0), curr_awlen_reg_1_or_2 => curr_awlen_reg_1_or_2, curr_fixed_burst => curr_fixed_burst, curr_fixed_burst_reg => curr_fixed_burst_reg, curr_fixed_burst_reg_reg => I_WRAP_BRST_n_24, curr_wrap_burst => curr_wrap_burst, curr_wrap_burst_reg => curr_wrap_burst_reg, curr_wrap_burst_reg_reg => I_WRAP_BRST_n_25, last_data_ack_mod => last_data_ack_mod, \out\(2 downto 0) => wr_data_sm_cs(2 downto 0), s_axi_aclk => s_axi_aclk, s_axi_aresetn => s_axi_aresetn, s_axi_aresetn_0 => s_axi_aresetn_0, s_axi_awaddr(13 downto 0) => s_axi_awaddr(13 downto 0), s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0), s_axi_awvalid => s_axi_awvalid, s_axi_wvalid => s_axi_wvalid, \save_init_bram_addr_ld_reg[15]_0\ => I_WRAP_BRST_n_19, \save_init_bram_addr_ld_reg[15]_1\ => I_WRAP_BRST_n_20, \save_init_bram_addr_ld_reg[15]_2\ => I_WRAP_BRST_n_21, wr_addr_sm_cs => wr_addr_sm_cs, \wrap_burst_total_reg[0]_0\ => I_WRAP_BRST_n_22, \wrap_burst_total_reg[2]_0\ => I_WRAP_BRST_n_23 ); \axi_bid_int_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => BID_FIFO_n_4, Q => \^s_axi_bid\(0), R => s_axi_aresetn_0 ); axi_bvalid_int_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAAAAAA8A88" ) port map ( I0 => s_axi_aresetn, I1 => bvalid_cnt_inc, I2 => BID_FIFO_n_1, I3 => bvalid_cnt(0), I4 => bvalid_cnt(2), I5 => bvalid_cnt(1), O => axi_bvalid_int_i_1_n_0 ); axi_bvalid_int_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => axi_bvalid_int_i_1_n_0, Q => \^s_axi_bvalid\, R => '0' ); axi_wr_burst_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axi_wr_burst_cmb, I1 => axi_wr_burst_i_3_n_0, I2 => axi_wr_burst, O => axi_wr_burst_i_1_n_0 ); axi_wr_burst_i_2: unisim.vcomponents.LUT5 generic map( INIT => X"3088FCBB" ) port map ( I0 => s_axi_wvalid, I1 => wr_data_sm_cs(1), I2 => axi_wr_burst_cmb0, I3 => wr_data_sm_cs(0), I4 => s_axi_wlast, O => axi_wr_burst_cmb ); axi_wr_burst_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"00000000AAAAA222" ) port map ( I0 => s_axi_wvalid, I1 => wr_data_sm_cs(0), I2 => axi_wr_burst_cmb0, I3 => s_axi_wlast, I4 => wr_data_sm_cs(1), I5 => wr_data_sm_cs(2), O => axi_wr_burst_i_3_n_0 ); axi_wr_burst_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => axi_wr_burst_i_1_n_0, Q => axi_wr_burst, R => s_axi_aresetn_0 ); axi_wready_int_mod_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"EA00EAFF00000000" ) port map ( I0 => axi_wdata_full_cmb114_out, I1 => axi_awaddr_full, I2 => bram_addr_ld_en, I3 => wr_data_sm_cs(2), I4 => axi_wready_int_mod_i_3_n_0, I5 => s_axi_aresetn, O => axi_wready_int_mod_i_1_n_0 ); axi_wready_int_mod_i_3: unisim.vcomponents.LUT5 generic map( INIT => X"F8F9F0F0" ) port map ( I0 => wr_data_sm_cs(1), I1 => wr_data_sm_cs(0), I2 => axi_wdata_full_reg, I3 => axi_wdata_full_cmb114_out, I4 => s_axi_wvalid, O => axi_wready_int_mod_i_3_n_0 ); axi_wready_int_mod_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => axi_wready_int_mod_i_1_n_0, Q => \^s_axi_wready\, R => '0' ); bid_gets_fifo_load_d1_i_2: unisim.vcomponents.LUT3 generic map( INIT => X"EF" ) port map ( I0 => bvalid_cnt(1), I1 => bvalid_cnt(2), I2 => bvalid_cnt(0), O => bid_gets_fifo_load_d1_i_2_n_0 ); bid_gets_fifo_load_d1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => bid_gets_fifo_load, Q => bid_gets_fifo_load_d1, R => s_axi_aresetn_0 ); \bvalid_cnt[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"95956A6A95956AAA" ) port map ( I0 => bvalid_cnt_inc, I1 => s_axi_bready, I2 => \^s_axi_bvalid\, I3 => bvalid_cnt(2), I4 => bvalid_cnt(0), I5 => bvalid_cnt(1), O => \bvalid_cnt[0]_i_1_n_0\ ); \bvalid_cnt[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"D5D5BFBF2A2A4000" ) port map ( I0 => bvalid_cnt_inc, I1 => s_axi_bready, I2 => \^s_axi_bvalid\, I3 => bvalid_cnt(2), I4 => bvalid_cnt(0), I5 => bvalid_cnt(1), O => \bvalid_cnt[1]_i_1_n_0\ ); \bvalid_cnt[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"D52AFF00FF00BF00" ) port map ( I0 => bvalid_cnt_inc, I1 => s_axi_bready, I2 => \^s_axi_bvalid\, I3 => bvalid_cnt(2), I4 => bvalid_cnt(0), I5 => bvalid_cnt(1), O => \bvalid_cnt[2]_i_1_n_0\ ); \bvalid_cnt_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \bvalid_cnt[0]_i_1_n_0\, Q => bvalid_cnt(0), R => s_axi_aresetn_0 ); \bvalid_cnt_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \bvalid_cnt[1]_i_1_n_0\, Q => bvalid_cnt(1), R => s_axi_aresetn_0 ); \bvalid_cnt_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \bvalid_cnt[2]_i_1_n_0\, Q => bvalid_cnt(2), R => s_axi_aresetn_0 ); curr_awlen_reg_1_or_2_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000151" ) port map ( I0 => I_WRAP_BRST_n_23, I1 => s_axi_awlen(2), I2 => axi_awaddr_full, I3 => axi_awlen_pipe(2), I4 => I_WRAP_BRST_n_22, I5 => curr_awlen_reg_1_or_2_i_2_n_0, O => curr_awlen_reg_1_or_20 ); curr_awlen_reg_1_or_2_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"F5F5F5F5F5F5F5C5" ) port map ( I0 => \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\, I1 => axi_awlen_pipe(5), I2 => axi_awaddr_full, I3 => axi_awlen_pipe(6), I4 => axi_awlen_pipe(7), I5 => axi_awlen_pipe(4), O => curr_awlen_reg_1_or_2_i_2_n_0 ); curr_awlen_reg_1_or_2_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => bram_addr_ld_en, D => curr_awlen_reg_1_or_20, Q => curr_awlen_reg_1_or_2, R => s_axi_aresetn_0 ); curr_fixed_burst_reg_i_2: unisim.vcomponents.LUT5 generic map( INIT => X"00053305" ) port map ( I0 => s_axi_awburst(1), I1 => axi_awburst_pipe(1), I2 => s_axi_awburst(0), I3 => axi_awaddr_full, I4 => axi_awburst_pipe(0), O => curr_fixed_burst ); curr_fixed_burst_reg_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => I_WRAP_BRST_n_24, Q => curr_fixed_burst_reg, R => '0' ); curr_wrap_burst_reg_i_2: unisim.vcomponents.LUT5 generic map( INIT => X"000ACC0A" ) port map ( I0 => s_axi_awburst(1), I1 => axi_awburst_pipe(1), I2 => s_axi_awburst(0), I3 => axi_awaddr_full, I4 => axi_awburst_pipe(0), O => curr_wrap_burst ); curr_wrap_burst_reg_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => I_WRAP_BRST_n_25, Q => curr_wrap_burst_reg, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zqynq_lab_1_design_axi_bram_ctrl_0_0_full_axi is port ( s_axi_rvalid : out STD_LOGIC; s_axi_rlast : out STD_LOGIC; s_axi_bvalid : out STD_LOGIC; s_axi_awready : out STD_LOGIC; bram_rst_a : out STD_LOGIC; bram_addr_a : out STD_LOGIC_VECTOR ( 13 downto 0 ); bram_en_a : out STD_LOGIC; bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 ); bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 ); bram_addr_b : out STD_LOGIC_VECTOR ( 13 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wready : out STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 ); bram_en_b : out STD_LOGIC; s_axi_aresetn : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wlast : in STD_LOGIC; s_axi_rready : in STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_aclk : in STD_LOGIC; s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 ); s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 ); s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 ); bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_bram_ctrl_0_0_full_axi : entity is "full_axi"; end zqynq_lab_1_design_axi_bram_ctrl_0_0_full_axi; architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0_full_axi is signal I_WR_CHNL_n_36 : STD_LOGIC; signal axi_aresetn_d2 : STD_LOGIC; signal axi_aresetn_re_reg : STD_LOGIC; signal \^bram_rst_a\ : STD_LOGIC; begin bram_rst_a <= \^bram_rst_a\; I_RD_CHNL: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_0_rd_chnl port map ( \GEN_AWREADY.axi_aresetn_d2_reg\ => I_WR_CHNL_n_36, Q(13 downto 0) => bram_addr_b(13 downto 0), axi_aresetn_d2 => axi_aresetn_d2, axi_aresetn_re_reg => axi_aresetn_re_reg, bram_en_b => bram_en_b, bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0), bram_rst_a => \^bram_rst_a\, s_axi_aclk => s_axi_aclk, s_axi_araddr(13 downto 0) => s_axi_araddr(13 downto 0), s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), s_axi_aresetn => s_axi_aresetn, s_axi_arid(0) => s_axi_arid(0), s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0), s_axi_arready => s_axi_arready, s_axi_arvalid => s_axi_arvalid, s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0), s_axi_rid(0) => s_axi_rid(0), s_axi_rlast => s_axi_rlast, s_axi_rready => s_axi_rready, s_axi_rvalid => s_axi_rvalid ); I_WR_CHNL: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_0_wr_chnl port map ( \GEN_AW_DUAL.aw_active_reg_0\ => I_WR_CHNL_n_36, axi_aresetn_d2 => axi_aresetn_d2, axi_aresetn_re_reg => axi_aresetn_re_reg, bram_addr_a(13 downto 0) => bram_addr_a(13 downto 0), bram_en_a => bram_en_a, bram_we_a(3 downto 0) => bram_we_a(3 downto 0), bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0), s_axi_aclk => s_axi_aclk, s_axi_aresetn => s_axi_aresetn, s_axi_aresetn_0 => \^bram_rst_a\, s_axi_awaddr(13 downto 0) => s_axi_awaddr(13 downto 0), s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), s_axi_awid(0) => s_axi_awid(0), s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0), s_axi_awready => s_axi_awready, s_axi_awvalid => s_axi_awvalid, s_axi_bid(0) => s_axi_bid(0), s_axi_bready => s_axi_bready, s_axi_bvalid => s_axi_bvalid, s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0), s_axi_wlast => s_axi_wlast, s_axi_wready => s_axi_wready, s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0), s_axi_wvalid => s_axi_wvalid ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl_top is port ( s_axi_rvalid : out STD_LOGIC; s_axi_rlast : out STD_LOGIC; s_axi_bvalid : out STD_LOGIC; s_axi_awready : out STD_LOGIC; bram_rst_a : out STD_LOGIC; bram_addr_a : out STD_LOGIC_VECTOR ( 13 downto 0 ); bram_en_a : out STD_LOGIC; bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 ); bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 ); bram_addr_b : out STD_LOGIC_VECTOR ( 13 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wready : out STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 ); bram_en_b : out STD_LOGIC; s_axi_aresetn : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wlast : in STD_LOGIC; s_axi_rready : in STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_aclk : in STD_LOGIC; s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 ); s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 ); s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 ); bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl_top : entity is "axi_bram_ctrl_top"; end zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl_top; architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl_top is begin \GEN_AXI4.I_FULL_AXI\: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_0_full_axi port map ( bram_addr_a(13 downto 0) => bram_addr_a(13 downto 0), bram_addr_b(13 downto 0) => bram_addr_b(13 downto 0), bram_en_a => bram_en_a, bram_en_b => bram_en_b, bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0), bram_rst_a => bram_rst_a, bram_we_a(3 downto 0) => bram_we_a(3 downto 0), bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0), s_axi_aclk => s_axi_aclk, s_axi_araddr(13 downto 0) => s_axi_araddr(13 downto 0), s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), s_axi_aresetn => s_axi_aresetn, s_axi_arid(0) => s_axi_arid(0), s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0), s_axi_arready => s_axi_arready, s_axi_arvalid => s_axi_arvalid, s_axi_awaddr(13 downto 0) => s_axi_awaddr(13 downto 0), s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), s_axi_awid(0) => s_axi_awid(0), s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0), s_axi_awready => s_axi_awready, s_axi_awvalid => s_axi_awvalid, s_axi_bid(0) => s_axi_bid(0), s_axi_bready => s_axi_bready, s_axi_bvalid => s_axi_bvalid, s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0), s_axi_rid(0) => s_axi_rid(0), s_axi_rlast => s_axi_rlast, s_axi_rready => s_axi_rready, s_axi_rvalid => s_axi_rvalid, s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0), s_axi_wlast => s_axi_wlast, s_axi_wready => s_axi_wready, s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0), s_axi_wvalid => s_axi_wvalid ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl is port ( s_axi_aclk : in STD_LOGIC; s_axi_aresetn : in STD_LOGIC; ecc_interrupt : out STD_LOGIC; ecc_ue : out STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 15 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awlock : in STD_LOGIC; s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 15 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arlock : in STD_LOGIC; s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; s_axi_ctrl_awvalid : in STD_LOGIC; s_axi_ctrl_awready : out STD_LOGIC; s_axi_ctrl_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_ctrl_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_ctrl_wvalid : in STD_LOGIC; s_axi_ctrl_wready : out STD_LOGIC; s_axi_ctrl_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_ctrl_bvalid : out STD_LOGIC; s_axi_ctrl_bready : in STD_LOGIC; s_axi_ctrl_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_ctrl_arvalid : in STD_LOGIC; s_axi_ctrl_arready : out STD_LOGIC; s_axi_ctrl_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_ctrl_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_ctrl_rvalid : out STD_LOGIC; s_axi_ctrl_rready : in STD_LOGIC; bram_rst_a : out STD_LOGIC; bram_clk_a : out STD_LOGIC; bram_en_a : out STD_LOGIC; bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 ); bram_addr_a : out STD_LOGIC_VECTOR ( 15 downto 0 ); bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 ); bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 ); bram_rst_b : out STD_LOGIC; bram_clk_b : out STD_LOGIC; bram_en_b : out STD_LOGIC; bram_we_b : out STD_LOGIC_VECTOR ( 3 downto 0 ); bram_addr_b : out STD_LOGIC_VECTOR ( 15 downto 0 ); bram_wrdata_b : out STD_LOGIC_VECTOR ( 31 downto 0 ); bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 ) ); attribute C_BRAM_ADDR_WIDTH : integer; attribute C_BRAM_ADDR_WIDTH of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 14; attribute C_BRAM_INST_MODE : string; attribute C_BRAM_INST_MODE of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is "EXTERNAL"; attribute C_ECC : integer; attribute C_ECC of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 0; attribute C_ECC_ONOFF_RESET_VALUE : integer; attribute C_ECC_ONOFF_RESET_VALUE of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 0; attribute C_ECC_TYPE : integer; attribute C_ECC_TYPE of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 0; attribute C_FAMILY : string; attribute C_FAMILY of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is "zynq"; attribute C_FAULT_INJECT : integer; attribute C_FAULT_INJECT of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 0; attribute C_MEMORY_DEPTH : integer; attribute C_MEMORY_DEPTH of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 16384; attribute C_SELECT_XPM : integer; attribute C_SELECT_XPM of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 0; attribute C_SINGLE_PORT_BRAM : integer; attribute C_SINGLE_PORT_BRAM of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 0; attribute C_S_AXI_ADDR_WIDTH : integer; attribute C_S_AXI_ADDR_WIDTH of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 16; attribute C_S_AXI_CTRL_ADDR_WIDTH : integer; attribute C_S_AXI_CTRL_ADDR_WIDTH of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 32; attribute C_S_AXI_CTRL_DATA_WIDTH : integer; attribute C_S_AXI_CTRL_DATA_WIDTH of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 32; attribute C_S_AXI_DATA_WIDTH : integer; attribute C_S_AXI_DATA_WIDTH of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 32; attribute C_S_AXI_ID_WIDTH : integer; attribute C_S_AXI_ID_WIDTH of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 1; attribute C_S_AXI_PROTOCOL : string; attribute C_S_AXI_PROTOCOL of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is "AXI4"; attribute C_S_AXI_SUPPORTS_NARROW_BURST : integer; attribute C_S_AXI_SUPPORTS_NARROW_BURST of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 0; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is "axi_bram_ctrl"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is "yes"; end zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl; architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl is signal \<const0>\ : STD_LOGIC; signal \^bram_addr_a\ : STD_LOGIC_VECTOR ( 15 downto 2 ); signal \^bram_addr_b\ : STD_LOGIC_VECTOR ( 15 downto 2 ); signal \^bram_rst_a\ : STD_LOGIC; signal \^s_axi_aclk\ : STD_LOGIC; begin \^s_axi_aclk\ <= s_axi_aclk; bram_addr_a(15 downto 2) <= \^bram_addr_a\(15 downto 2); bram_addr_a(1) <= \<const0>\; bram_addr_a(0) <= \<const0>\; bram_addr_b(15 downto 2) <= \^bram_addr_b\(15 downto 2); bram_addr_b(1) <= \<const0>\; bram_addr_b(0) <= \<const0>\; bram_clk_a <= \^s_axi_aclk\; bram_clk_b <= \^s_axi_aclk\; bram_rst_a <= \^bram_rst_a\; bram_rst_b <= \^bram_rst_a\; bram_we_b(3) <= \<const0>\; bram_we_b(2) <= \<const0>\; bram_we_b(1) <= \<const0>\; bram_we_b(0) <= \<const0>\; bram_wrdata_b(31) <= \<const0>\; bram_wrdata_b(30) <= \<const0>\; bram_wrdata_b(29) <= \<const0>\; bram_wrdata_b(28) <= \<const0>\; bram_wrdata_b(27) <= \<const0>\; bram_wrdata_b(26) <= \<const0>\; bram_wrdata_b(25) <= \<const0>\; bram_wrdata_b(24) <= \<const0>\; bram_wrdata_b(23) <= \<const0>\; bram_wrdata_b(22) <= \<const0>\; bram_wrdata_b(21) <= \<const0>\; bram_wrdata_b(20) <= \<const0>\; bram_wrdata_b(19) <= \<const0>\; bram_wrdata_b(18) <= \<const0>\; bram_wrdata_b(17) <= \<const0>\; bram_wrdata_b(16) <= \<const0>\; bram_wrdata_b(15) <= \<const0>\; bram_wrdata_b(14) <= \<const0>\; bram_wrdata_b(13) <= \<const0>\; bram_wrdata_b(12) <= \<const0>\; bram_wrdata_b(11) <= \<const0>\; bram_wrdata_b(10) <= \<const0>\; bram_wrdata_b(9) <= \<const0>\; bram_wrdata_b(8) <= \<const0>\; bram_wrdata_b(7) <= \<const0>\; bram_wrdata_b(6) <= \<const0>\; bram_wrdata_b(5) <= \<const0>\; bram_wrdata_b(4) <= \<const0>\; bram_wrdata_b(3) <= \<const0>\; bram_wrdata_b(2) <= \<const0>\; bram_wrdata_b(1) <= \<const0>\; bram_wrdata_b(0) <= \<const0>\; ecc_interrupt <= \<const0>\; ecc_ue <= \<const0>\; s_axi_bresp(1) <= \<const0>\; s_axi_bresp(0) <= \<const0>\; s_axi_ctrl_arready <= \<const0>\; s_axi_ctrl_awready <= \<const0>\; s_axi_ctrl_bresp(1) <= \<const0>\; s_axi_ctrl_bresp(0) <= \<const0>\; s_axi_ctrl_bvalid <= \<const0>\; s_axi_ctrl_rdata(31) <= \<const0>\; s_axi_ctrl_rdata(30) <= \<const0>\; s_axi_ctrl_rdata(29) <= \<const0>\; s_axi_ctrl_rdata(28) <= \<const0>\; s_axi_ctrl_rdata(27) <= \<const0>\; s_axi_ctrl_rdata(26) <= \<const0>\; s_axi_ctrl_rdata(25) <= \<const0>\; s_axi_ctrl_rdata(24) <= \<const0>\; s_axi_ctrl_rdata(23) <= \<const0>\; s_axi_ctrl_rdata(22) <= \<const0>\; s_axi_ctrl_rdata(21) <= \<const0>\; s_axi_ctrl_rdata(20) <= \<const0>\; s_axi_ctrl_rdata(19) <= \<const0>\; s_axi_ctrl_rdata(18) <= \<const0>\; s_axi_ctrl_rdata(17) <= \<const0>\; s_axi_ctrl_rdata(16) <= \<const0>\; s_axi_ctrl_rdata(15) <= \<const0>\; s_axi_ctrl_rdata(14) <= \<const0>\; s_axi_ctrl_rdata(13) <= \<const0>\; s_axi_ctrl_rdata(12) <= \<const0>\; s_axi_ctrl_rdata(11) <= \<const0>\; s_axi_ctrl_rdata(10) <= \<const0>\; s_axi_ctrl_rdata(9) <= \<const0>\; s_axi_ctrl_rdata(8) <= \<const0>\; s_axi_ctrl_rdata(7) <= \<const0>\; s_axi_ctrl_rdata(6) <= \<const0>\; s_axi_ctrl_rdata(5) <= \<const0>\; s_axi_ctrl_rdata(4) <= \<const0>\; s_axi_ctrl_rdata(3) <= \<const0>\; s_axi_ctrl_rdata(2) <= \<const0>\; s_axi_ctrl_rdata(1) <= \<const0>\; s_axi_ctrl_rdata(0) <= \<const0>\; s_axi_ctrl_rresp(1) <= \<const0>\; s_axi_ctrl_rresp(0) <= \<const0>\; s_axi_ctrl_rvalid <= \<const0>\; s_axi_ctrl_wready <= \<const0>\; s_axi_rresp(1) <= \<const0>\; s_axi_rresp(0) <= \<const0>\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); \gext_inst.abcv4_0_ext_inst\: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl_top port map ( bram_addr_a(13 downto 0) => \^bram_addr_a\(15 downto 2), bram_addr_b(13 downto 0) => \^bram_addr_b\(15 downto 2), bram_en_a => bram_en_a, bram_en_b => bram_en_b, bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0), bram_rst_a => \^bram_rst_a\, bram_we_a(3 downto 0) => bram_we_a(3 downto 0), bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0), s_axi_aclk => \^s_axi_aclk\, s_axi_araddr(13 downto 0) => s_axi_araddr(15 downto 2), s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), s_axi_aresetn => s_axi_aresetn, s_axi_arid(0) => s_axi_arid(0), s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0), s_axi_arready => s_axi_arready, s_axi_arvalid => s_axi_arvalid, s_axi_awaddr(13 downto 0) => s_axi_awaddr(15 downto 2), s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), s_axi_awid(0) => s_axi_awid(0), s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0), s_axi_awready => s_axi_awready, s_axi_awvalid => s_axi_awvalid, s_axi_bid(0) => s_axi_bid(0), s_axi_bready => s_axi_bready, s_axi_bvalid => s_axi_bvalid, s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0), s_axi_rid(0) => s_axi_rid(0), s_axi_rlast => s_axi_rlast, s_axi_rready => s_axi_rready, s_axi_rvalid => s_axi_rvalid, s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0), s_axi_wlast => s_axi_wlast, s_axi_wready => s_axi_wready, s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0), s_axi_wvalid => s_axi_wvalid ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zqynq_lab_1_design_axi_bram_ctrl_0_0 is port ( s_axi_aclk : in STD_LOGIC; s_axi_aresetn : in STD_LOGIC; s_axi_awaddr : in STD_LOGIC_VECTOR ( 15 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awlock : in STD_LOGIC; s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_araddr : in STD_LOGIC_VECTOR ( 15 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arlock : in STD_LOGIC; s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; bram_rst_a : out STD_LOGIC; bram_clk_a : out STD_LOGIC; bram_en_a : out STD_LOGIC; bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 ); bram_addr_a : out STD_LOGIC_VECTOR ( 15 downto 0 ); bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 ); bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 ); bram_rst_b : out STD_LOGIC; bram_clk_b : out STD_LOGIC; bram_en_b : out STD_LOGIC; bram_we_b : out STD_LOGIC_VECTOR ( 3 downto 0 ); bram_addr_b : out STD_LOGIC_VECTOR ( 15 downto 0 ); bram_wrdata_b : out STD_LOGIC_VECTOR ( 31 downto 0 ); bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of zqynq_lab_1_design_axi_bram_ctrl_0_0 : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of zqynq_lab_1_design_axi_bram_ctrl_0_0 : entity is "zqynq_lab_1_design_axi_bram_ctrl_0_0,axi_bram_ctrl,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of zqynq_lab_1_design_axi_bram_ctrl_0_0 : entity is "yes"; attribute x_core_info : string; attribute x_core_info of zqynq_lab_1_design_axi_bram_ctrl_0_0 : entity is "axi_bram_ctrl,Vivado 2017.2"; end zqynq_lab_1_design_axi_bram_ctrl_0_0; architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0 is signal NLW_U0_ecc_interrupt_UNCONNECTED : STD_LOGIC; signal NLW_U0_ecc_ue_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_ctrl_arready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_ctrl_awready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_ctrl_wready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_s_axi_ctrl_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_U0_s_axi_ctrl_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_U0_s_axi_ctrl_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); attribute C_BRAM_ADDR_WIDTH : integer; attribute C_BRAM_ADDR_WIDTH of U0 : label is 14; attribute C_BRAM_INST_MODE : string; attribute C_BRAM_INST_MODE of U0 : label is "EXTERNAL"; attribute C_ECC : integer; attribute C_ECC of U0 : label is 0; attribute C_ECC_ONOFF_RESET_VALUE : integer; attribute C_ECC_ONOFF_RESET_VALUE of U0 : label is 0; attribute C_ECC_TYPE : integer; attribute C_ECC_TYPE of U0 : label is 0; attribute C_FAMILY : string; attribute C_FAMILY of U0 : label is "zynq"; attribute C_FAULT_INJECT : integer; attribute C_FAULT_INJECT of U0 : label is 0; attribute C_MEMORY_DEPTH : integer; attribute C_MEMORY_DEPTH of U0 : label is 16384; attribute C_SELECT_XPM : integer; attribute C_SELECT_XPM of U0 : label is 0; attribute C_SINGLE_PORT_BRAM : integer; attribute C_SINGLE_PORT_BRAM of U0 : label is 0; attribute C_S_AXI_ADDR_WIDTH : integer; attribute C_S_AXI_ADDR_WIDTH of U0 : label is 16; attribute C_S_AXI_CTRL_ADDR_WIDTH : integer; attribute C_S_AXI_CTRL_ADDR_WIDTH of U0 : label is 32; attribute C_S_AXI_CTRL_DATA_WIDTH : integer; attribute C_S_AXI_CTRL_DATA_WIDTH of U0 : label is 32; attribute C_S_AXI_DATA_WIDTH : integer; attribute C_S_AXI_DATA_WIDTH of U0 : label is 32; attribute C_S_AXI_ID_WIDTH : integer; attribute C_S_AXI_ID_WIDTH of U0 : label is 1; attribute C_S_AXI_PROTOCOL : string; attribute C_S_AXI_PROTOCOL of U0 : label is "AXI4"; attribute C_S_AXI_SUPPORTS_NARROW_BURST : integer; attribute C_S_AXI_SUPPORTS_NARROW_BURST of U0 : label is 0; attribute downgradeipidentifiedwarnings of U0 : label is "yes"; begin U0: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl port map ( bram_addr_a(15 downto 0) => bram_addr_a(15 downto 0), bram_addr_b(15 downto 0) => bram_addr_b(15 downto 0), bram_clk_a => bram_clk_a, bram_clk_b => bram_clk_b, bram_en_a => bram_en_a, bram_en_b => bram_en_b, bram_rddata_a(31 downto 0) => bram_rddata_a(31 downto 0), bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0), bram_rst_a => bram_rst_a, bram_rst_b => bram_rst_b, bram_we_a(3 downto 0) => bram_we_a(3 downto 0), bram_we_b(3 downto 0) => bram_we_b(3 downto 0), bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0), bram_wrdata_b(31 downto 0) => bram_wrdata_b(31 downto 0), ecc_interrupt => NLW_U0_ecc_interrupt_UNCONNECTED, ecc_ue => NLW_U0_ecc_ue_UNCONNECTED, s_axi_aclk => s_axi_aclk, s_axi_araddr(15 downto 0) => s_axi_araddr(15 downto 0), s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0), s_axi_aresetn => s_axi_aresetn, s_axi_arid(0) => '0', s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0), s_axi_arlock => s_axi_arlock, s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), s_axi_arready => s_axi_arready, s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0), s_axi_arvalid => s_axi_arvalid, s_axi_awaddr(15 downto 0) => s_axi_awaddr(15 downto 0), s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0), s_axi_awid(0) => '0', s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0), s_axi_awlock => s_axi_awlock, s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), s_axi_awready => s_axi_awready, s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0), s_axi_awvalid => s_axi_awvalid, s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0), s_axi_bready => s_axi_bready, s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0), s_axi_bvalid => s_axi_bvalid, s_axi_ctrl_araddr(31 downto 0) => B"00000000000000000000000000000000", s_axi_ctrl_arready => NLW_U0_s_axi_ctrl_arready_UNCONNECTED, s_axi_ctrl_arvalid => '0', s_axi_ctrl_awaddr(31 downto 0) => B"00000000000000000000000000000000", s_axi_ctrl_awready => NLW_U0_s_axi_ctrl_awready_UNCONNECTED, s_axi_ctrl_awvalid => '0', s_axi_ctrl_bready => '0', s_axi_ctrl_bresp(1 downto 0) => NLW_U0_s_axi_ctrl_bresp_UNCONNECTED(1 downto 0), s_axi_ctrl_bvalid => NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED, s_axi_ctrl_rdata(31 downto 0) => NLW_U0_s_axi_ctrl_rdata_UNCONNECTED(31 downto 0), s_axi_ctrl_rready => '0', s_axi_ctrl_rresp(1 downto 0) => NLW_U0_s_axi_ctrl_rresp_UNCONNECTED(1 downto 0), s_axi_ctrl_rvalid => NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED, s_axi_ctrl_wdata(31 downto 0) => B"00000000000000000000000000000000", s_axi_ctrl_wready => NLW_U0_s_axi_ctrl_wready_UNCONNECTED, s_axi_ctrl_wvalid => '0', s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0), s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0), s_axi_rlast => s_axi_rlast, s_axi_rready => s_axi_rready, s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0), s_axi_rvalid => s_axi_rvalid, s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0), s_axi_wlast => s_axi_wlast, s_axi_wready => s_axi_wready, s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0), s_axi_wvalid => s_axi_wvalid ); end STRUCTURE;	mit
khaledhassan/vhdl-examples	register/register.vhd	1	1950	-- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net> -- This software is distributed under the terms of the MIT License shown below. -- -- Permission is hereby granted, free of charge, to any person obtaining a copy -- of this software and associated documentation files (the "Software"), to -- deal in the Software without restriction, including without limitation the -- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or -- sell copies of the Software, and to permit persons to whom the Software is -- furnished to do so, subject to the following conditions: -- -- The above copyright notice and this permission notice shall be included in -- all copies or substantial portions of the Software. -- -- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -- IN THE SOFTWARE. -- Implements a synchronous register of a given width with a load signal. library ieee; use ieee.std_logic_1164.all; entity reg is generic ( WIDTH : positive := 1 ); port ( clk : in std_logic; rst : in std_logic; load : in std_logic; input : in std_logic_vector(WIDTH-1 downto 0); output : out std_logic_vector(WIDTH-1 downto 0) ); end reg; architecture BHV of reg is begin process(clk, rst) begin if(rst = '1') then output <= (others => '0'); elsif(rising_edge(clk)) then if(load = '1') then output <= input; end if; end if; end process; end BHV;	mit
MarkBlanco/FPGA_Sandbox	RecComp/Lab1/embedded_lab_1/embedded_lab_1.cache/ip/2017.2/387128e4034068b3/zynq_design_1_processing_system7_0_2_stub.vhdl	1	5748	-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017 -- Date : Tue Sep 19 00:29:47 2017 -- Host : DarkCube running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_processing_system7_0_2_stub.vhdl -- Design : zynq_design_1_processing_system7_0_2 -- Purpose : Stub declaration of top-level module interface -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is Port ( TTC0_WAVE0_OUT : out STD_LOGIC; TTC0_WAVE1_OUT : out STD_LOGIC; TTC0_WAVE2_OUT : out STD_LOGIC; USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); USB0_VBUS_PWRSELECT : out STD_LOGIC; USB0_VBUS_PWRFAULT : in STD_LOGIC; M_AXI_GP0_ARVALID : out STD_LOGIC; M_AXI_GP0_AWVALID : out STD_LOGIC; M_AXI_GP0_BREADY : out STD_LOGIC; M_AXI_GP0_RREADY : out STD_LOGIC; M_AXI_GP0_WLAST : out STD_LOGIC; M_AXI_GP0_WVALID : out STD_LOGIC; M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ACLK : in STD_LOGIC; M_AXI_GP0_ARREADY : in STD_LOGIC; M_AXI_GP0_AWREADY : in STD_LOGIC; M_AXI_GP0_BVALID : in STD_LOGIC; M_AXI_GP0_RLAST : in STD_LOGIC; M_AXI_GP0_RVALID : in STD_LOGIC; M_AXI_GP0_WREADY : in STD_LOGIC; M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); FCLK_CLK0 : out STD_LOGIC; FCLK_RESET0_N : out STD_LOGIC; MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 ); DDR_CAS_n : inout STD_LOGIC; DDR_CKE : inout STD_LOGIC; DDR_Clk_n : inout STD_LOGIC; DDR_Clk : inout STD_LOGIC; DDR_CS_n : inout STD_LOGIC; DDR_DRSTB : inout STD_LOGIC; DDR_ODT : inout STD_LOGIC; DDR_RAS_n : inout STD_LOGIC; DDR_WEB : inout STD_LOGIC; DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_VRN : inout STD_LOGIC; DDR_VRP : inout STD_LOGIC; DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 ); PS_SRSTB : inout STD_LOGIC; PS_CLK : inout STD_LOGIC; PS_PORB : inout STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; attribute black_box_pad_pin of stub : architecture is "TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "processing_system7_v5_5_processing_system7,Vivado 2017.2"; begin end;	mit
MarkBlanco/FPGA_Sandbox	RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_xbar_0/ip_design_xbar_0_stub.vhdl	1	4109	-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017 -- Date : Tue Oct 17 19:50:59 2017 -- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS -- Command : write_vhdl -force -mode synth_stub -- /home/mark/Documents/Repos/FPGA_Sandbox/RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_xbar_0/ip_design_xbar_0_stub.vhdl -- Design : ip_design_xbar_0 -- Purpose : Stub declaration of top-level module interface -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity ip_design_xbar_0 is Port ( aclk : in STD_LOGIC; aresetn : in STD_LOGIC; s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awaddr : out STD_LOGIC_VECTOR ( 191 downto 0 ); m_axi_awprot : out STD_LOGIC_VECTOR ( 17 downto 0 ); m_axi_awvalid : out STD_LOGIC_VECTOR ( 5 downto 0 ); m_axi_awready : in STD_LOGIC_VECTOR ( 5 downto 0 ); m_axi_wdata : out STD_LOGIC_VECTOR ( 191 downto 0 ); m_axi_wstrb : out STD_LOGIC_VECTOR ( 23 downto 0 ); m_axi_wvalid : out STD_LOGIC_VECTOR ( 5 downto 0 ); m_axi_wready : in STD_LOGIC_VECTOR ( 5 downto 0 ); m_axi_bresp : in STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_bvalid : in STD_LOGIC_VECTOR ( 5 downto 0 ); m_axi_bready : out STD_LOGIC_VECTOR ( 5 downto 0 ); m_axi_araddr : out STD_LOGIC_VECTOR ( 191 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 17 downto 0 ); m_axi_arvalid : out STD_LOGIC_VECTOR ( 5 downto 0 ); m_axi_arready : in STD_LOGIC_VECTOR ( 5 downto 0 ); m_axi_rdata : in STD_LOGIC_VECTOR ( 191 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_rvalid : in STD_LOGIC_VECTOR ( 5 downto 0 ); m_axi_rready : out STD_LOGIC_VECTOR ( 5 downto 0 ) ); end ip_design_xbar_0; architecture stub of ip_design_xbar_0 is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axi_awaddr[31:0],s_axi_awprot[2:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_araddr[31:0],s_axi_arprot[2:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awaddr[191:0],m_axi_awprot[17:0],m_axi_awvalid[5:0],m_axi_awready[5:0],m_axi_wdata[191:0],m_axi_wstrb[23:0],m_axi_wvalid[5:0],m_axi_wready[5:0],m_axi_bresp[11:0],m_axi_bvalid[5:0],m_axi_bready[5:0],m_axi_araddr[191:0],m_axi_arprot[17:0],m_axi_arvalid[5:0],m_axi_arready[5:0],m_axi_rdata[191:0],m_axi_rresp[11:0],m_axi_rvalid[5:0],m_axi_rready[5:0]"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "axi_crossbar_v2_1_15_axi_crossbar,Vivado 2017.3"; begin end;	mit
MarkBlanco/FPGA_Sandbox	RecComp/Lab2/ug871-design-files/Interface_Synthesis/lab4/axi_interfaces_prj/solution2/impl/ip/hdl/vhdl/axi_interfaces.vhd	3	116677	-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2017.2 -- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity axi_interfaces is generic ( C_S_AXI_AXILITES_ADDR_WIDTH : INTEGER := 4; C_S_AXI_AXILITES_DATA_WIDTH : INTEGER := 32 ); port ( ap_clk : IN STD_LOGIC; ap_rst_n : IN STD_LOGIC; d_o_0_TREADY : IN STD_LOGIC; d_o_1_TREADY : IN STD_LOGIC; d_o_2_TREADY : IN STD_LOGIC; d_o_3_TREADY : IN STD_LOGIC; d_o_4_TREADY : IN STD_LOGIC; d_o_5_TREADY : IN STD_LOGIC; d_o_6_TREADY : IN STD_LOGIC; d_o_7_TREADY : IN STD_LOGIC; d_o_0_TDATA : OUT STD_LOGIC_VECTOR (15 downto 0); d_o_0_TVALID : OUT STD_LOGIC; d_o_1_TDATA : OUT STD_LOGIC_VECTOR (15 downto 0); d_o_1_TVALID : OUT STD_LOGIC; d_o_2_TDATA : OUT STD_LOGIC_VECTOR (15 downto 0); d_o_2_TVALID : OUT STD_LOGIC; d_o_3_TDATA : OUT STD_LOGIC_VECTOR (15 downto 0); d_o_3_TVALID : OUT STD_LOGIC; d_o_4_TDATA : OUT STD_LOGIC_VECTOR (15 downto 0); d_o_4_TVALID : OUT STD_LOGIC; d_o_5_TDATA : OUT STD_LOGIC_VECTOR (15 downto 0); d_o_5_TVALID : OUT STD_LOGIC; d_o_6_TDATA : OUT STD_LOGIC_VECTOR (15 downto 0); d_o_6_TVALID : OUT STD_LOGIC; d_o_7_TDATA : OUT STD_LOGIC_VECTOR (15 downto 0); d_o_7_TVALID : OUT STD_LOGIC; d_i_0_TDATA : IN STD_LOGIC_VECTOR (15 downto 0); d_i_0_TVALID : IN STD_LOGIC; d_i_0_TREADY : OUT STD_LOGIC; d_i_1_TDATA : IN STD_LOGIC_VECTOR (15 downto 0); d_i_1_TVALID : IN STD_LOGIC; d_i_1_TREADY : OUT STD_LOGIC; d_i_2_TDATA : IN STD_LOGIC_VECTOR (15 downto 0); d_i_2_TVALID : IN STD_LOGIC; d_i_2_TREADY : OUT STD_LOGIC; d_i_3_TDATA : IN STD_LOGIC_VECTOR (15 downto 0); d_i_3_TVALID : IN STD_LOGIC; d_i_3_TREADY : OUT STD_LOGIC; d_i_4_TDATA : IN STD_LOGIC_VECTOR (15 downto 0); d_i_4_TVALID : IN STD_LOGIC; d_i_4_TREADY : OUT STD_LOGIC; d_i_5_TDATA : IN STD_LOGIC_VECTOR (15 downto 0); d_i_5_TVALID : IN STD_LOGIC; d_i_5_TREADY : OUT STD_LOGIC; d_i_6_TDATA : IN STD_LOGIC_VECTOR (15 downto 0); d_i_6_TVALID : IN STD_LOGIC; d_i_6_TREADY : OUT STD_LOGIC; d_i_7_TDATA : IN STD_LOGIC_VECTOR (15 downto 0); d_i_7_TVALID : IN STD_LOGIC; d_i_7_TREADY : OUT STD_LOGIC; s_axi_AXILiteS_AWVALID : IN STD_LOGIC; s_axi_AXILiteS_AWREADY : OUT STD_LOGIC; s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0); s_axi_AXILiteS_WVALID : IN STD_LOGIC; s_axi_AXILiteS_WREADY : OUT STD_LOGIC; s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0); s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH/8-1 downto 0); s_axi_AXILiteS_ARVALID : IN STD_LOGIC; s_axi_AXILiteS_ARREADY : OUT STD_LOGIC; s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0); s_axi_AXILiteS_RVALID : OUT STD_LOGIC; s_axi_AXILiteS_RREADY : IN STD_LOGIC; s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0); s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0); s_axi_AXILiteS_BVALID : OUT STD_LOGIC; s_axi_AXILiteS_BREADY : IN STD_LOGIC; s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0); interrupt : OUT STD_LOGIC ); end; architecture behav of axi_interfaces is attribute CORE_GENERATION_INFO : STRING; attribute CORE_GENERATION_INFO of behav : architecture is "axi_interfaces,hls_ip_2017_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7k160tfbg484-1,HLS_INPUT_CLOCK=4.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=4.162500,HLS_SYN_LAT=5,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=2139,HLS_SYN_LUT=1196}"; constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (1 downto 0) := "01"; constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (1 downto 0) := "10"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_boolean_1 : BOOLEAN := true; constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_boolean_0 : BOOLEAN := false; constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00"; constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10"; constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11"; constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01"; constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20; constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000"; constant ap_const_lv6_8 : STD_LOGIC_VECTOR (5 downto 0) := "001000"; constant ap_const_lv6_20 : STD_LOGIC_VECTOR (5 downto 0) := "100000"; signal ap_rst_n_inv : STD_LOGIC; signal ap_start : STD_LOGIC; signal ap_done : STD_LOGIC; signal ap_idle : STD_LOGIC; signal ap_CS_fsm : STD_LOGIC_VECTOR (1 downto 0) := "01"; attribute fsm_encoding : string; attribute fsm_encoding of ap_CS_fsm : signal is "none"; signal ap_CS_fsm_state1 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none"; signal ap_ready : STD_LOGIC; signal exitcond_fu_246_p2 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage0 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none"; signal ap_enable_reg_pp0_iter0 : STD_LOGIC; signal ap_block_state2_pp0_stage0_iter0 : BOOLEAN; signal d_i_0_0_vld_out : STD_LOGIC; signal d_i_1_0_vld_out : STD_LOGIC; signal d_i_2_0_vld_out : STD_LOGIC; signal d_i_3_0_vld_out : STD_LOGIC; signal d_i_4_0_vld_out : STD_LOGIC; signal d_i_5_0_vld_out : STD_LOGIC; signal d_i_6_0_vld_out : STD_LOGIC; signal d_i_7_0_vld_out : STD_LOGIC; signal ap_block_state4_pp0_stage0_iter1 : BOOLEAN; signal d_o_0_1_ack_in : STD_LOGIC; signal d_o_1_1_ack_in : STD_LOGIC; signal d_o_2_1_ack_in : STD_LOGIC; signal d_o_3_1_ack_in : STD_LOGIC; signal d_o_4_1_ack_in : STD_LOGIC; signal d_o_5_1_ack_in : STD_LOGIC; signal d_o_6_1_ack_in : STD_LOGIC; signal d_o_7_1_ack_in : STD_LOGIC; signal ap_block_state4_io : BOOLEAN; signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0'; signal ap_block_state3_pp0_stage0_iter2 : BOOLEAN; signal ap_block_state3_io : BOOLEAN; signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0'; signal ap_block_pp0_stage0_flag00011001 : BOOLEAN; signal d_o_0_1_data_out : STD_LOGIC_VECTOR (15 downto 0); signal d_o_0_1_vld_in : STD_LOGIC; signal d_o_0_1_vld_out : STD_LOGIC; signal d_o_0_1_ack_out : STD_LOGIC; signal d_o_0_1_payload_A : STD_LOGIC_VECTOR (15 downto 0); signal d_o_0_1_payload_B : STD_LOGIC_VECTOR (15 downto 0); signal d_o_0_1_sel_rd : STD_LOGIC := '0'; signal d_o_0_1_sel_wr : STD_LOGIC := '0'; signal d_o_0_1_sel : STD_LOGIC; signal d_o_0_1_load_A : STD_LOGIC; signal d_o_0_1_load_B : STD_LOGIC; signal d_o_0_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00"; signal d_o_0_1_state_cmp_full : STD_LOGIC; signal d_o_1_1_data_out : STD_LOGIC_VECTOR (15 downto 0); signal d_o_1_1_vld_in : STD_LOGIC; signal d_o_1_1_vld_out : STD_LOGIC; signal d_o_1_1_ack_out : STD_LOGIC; signal d_o_1_1_payload_A : STD_LOGIC_VECTOR (15 downto 0); signal d_o_1_1_payload_B : STD_LOGIC_VECTOR (15 downto 0); signal d_o_1_1_sel_rd : STD_LOGIC := '0'; signal d_o_1_1_sel_wr : STD_LOGIC := '0'; signal d_o_1_1_sel : STD_LOGIC; signal d_o_1_1_load_A : STD_LOGIC; signal d_o_1_1_load_B : STD_LOGIC; signal d_o_1_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00"; signal d_o_1_1_state_cmp_full : STD_LOGIC; signal d_o_2_1_data_out : STD_LOGIC_VECTOR (15 downto 0); signal d_o_2_1_vld_in : STD_LOGIC; signal d_o_2_1_vld_out : STD_LOGIC; signal d_o_2_1_ack_out : STD_LOGIC; signal d_o_2_1_payload_A : STD_LOGIC_VECTOR (15 downto 0); signal d_o_2_1_payload_B : STD_LOGIC_VECTOR (15 downto 0); signal d_o_2_1_sel_rd : STD_LOGIC := '0'; signal d_o_2_1_sel_wr : STD_LOGIC := '0'; signal d_o_2_1_sel : STD_LOGIC; signal d_o_2_1_load_A : STD_LOGIC; signal d_o_2_1_load_B : STD_LOGIC; signal d_o_2_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00"; signal d_o_2_1_state_cmp_full : STD_LOGIC; signal d_o_3_1_data_out : STD_LOGIC_VECTOR (15 downto 0); signal d_o_3_1_vld_in : STD_LOGIC; signal d_o_3_1_vld_out : STD_LOGIC; signal d_o_3_1_ack_out : STD_LOGIC; signal d_o_3_1_payload_A : STD_LOGIC_VECTOR (15 downto 0); signal d_o_3_1_payload_B : STD_LOGIC_VECTOR (15 downto 0); signal d_o_3_1_sel_rd : STD_LOGIC := '0'; signal d_o_3_1_sel_wr : STD_LOGIC := '0'; signal d_o_3_1_sel : STD_LOGIC; signal d_o_3_1_load_A : STD_LOGIC; signal d_o_3_1_load_B : STD_LOGIC; signal d_o_3_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00"; signal d_o_3_1_state_cmp_full : STD_LOGIC; signal d_o_4_1_data_out : STD_LOGIC_VECTOR (15 downto 0); signal d_o_4_1_vld_in : STD_LOGIC; signal d_o_4_1_vld_out : STD_LOGIC; signal d_o_4_1_ack_out : STD_LOGIC; signal d_o_4_1_payload_A : STD_LOGIC_VECTOR (15 downto 0); signal d_o_4_1_payload_B : STD_LOGIC_VECTOR (15 downto 0); signal d_o_4_1_sel_rd : STD_LOGIC := '0'; signal d_o_4_1_sel_wr : STD_LOGIC := '0'; signal d_o_4_1_sel : STD_LOGIC; signal d_o_4_1_load_A : STD_LOGIC; signal d_o_4_1_load_B : STD_LOGIC; signal d_o_4_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00"; signal d_o_4_1_state_cmp_full : STD_LOGIC; signal d_o_5_1_data_out : STD_LOGIC_VECTOR (15 downto 0); signal d_o_5_1_vld_in : STD_LOGIC; signal d_o_5_1_vld_out : STD_LOGIC; signal d_o_5_1_ack_out : STD_LOGIC; signal d_o_5_1_payload_A : STD_LOGIC_VECTOR (15 downto 0); signal d_o_5_1_payload_B : STD_LOGIC_VECTOR (15 downto 0); signal d_o_5_1_sel_rd : STD_LOGIC := '0'; signal d_o_5_1_sel_wr : STD_LOGIC := '0'; signal d_o_5_1_sel : STD_LOGIC; signal d_o_5_1_load_A : STD_LOGIC; signal d_o_5_1_load_B : STD_LOGIC; signal d_o_5_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00"; signal d_o_5_1_state_cmp_full : STD_LOGIC; signal d_o_6_1_data_out : STD_LOGIC_VECTOR (15 downto 0); signal d_o_6_1_vld_in : STD_LOGIC; signal d_o_6_1_vld_out : STD_LOGIC; signal d_o_6_1_ack_out : STD_LOGIC; signal d_o_6_1_payload_A : STD_LOGIC_VECTOR (15 downto 0); signal d_o_6_1_payload_B : STD_LOGIC_VECTOR (15 downto 0); signal d_o_6_1_sel_rd : STD_LOGIC := '0'; signal d_o_6_1_sel_wr : STD_LOGIC := '0'; signal d_o_6_1_sel : STD_LOGIC; signal d_o_6_1_load_A : STD_LOGIC; signal d_o_6_1_load_B : STD_LOGIC; signal d_o_6_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00"; signal d_o_6_1_state_cmp_full : STD_LOGIC; signal d_o_7_1_data_out : STD_LOGIC_VECTOR (15 downto 0); signal d_o_7_1_vld_in : STD_LOGIC; signal d_o_7_1_vld_out : STD_LOGIC; signal d_o_7_1_ack_out : STD_LOGIC; signal d_o_7_1_payload_A : STD_LOGIC_VECTOR (15 downto 0); signal d_o_7_1_payload_B : STD_LOGIC_VECTOR (15 downto 0); signal d_o_7_1_sel_rd : STD_LOGIC := '0'; signal d_o_7_1_sel_wr : STD_LOGIC := '0'; signal d_o_7_1_sel : STD_LOGIC; signal d_o_7_1_load_A : STD_LOGIC; signal d_o_7_1_load_B : STD_LOGIC; signal d_o_7_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00"; signal d_o_7_1_state_cmp_full : STD_LOGIC; signal d_i_0_0_data_out : STD_LOGIC_VECTOR (15 downto 0); signal d_i_0_0_vld_in : STD_LOGIC; signal d_i_0_0_ack_in : STD_LOGIC; signal d_i_0_0_ack_out : STD_LOGIC; signal d_i_0_0_payload_A : STD_LOGIC_VECTOR (15 downto 0); signal d_i_0_0_payload_B : STD_LOGIC_VECTOR (15 downto 0); signal d_i_0_0_sel_rd : STD_LOGIC := '0'; signal d_i_0_0_sel_wr : STD_LOGIC := '0'; signal d_i_0_0_sel : STD_LOGIC; signal d_i_0_0_load_A : STD_LOGIC; signal d_i_0_0_load_B : STD_LOGIC; signal d_i_0_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00"; signal d_i_0_0_state_cmp_full : STD_LOGIC; signal d_i_1_0_data_out : STD_LOGIC_VECTOR (15 downto 0); signal d_i_1_0_vld_in : STD_LOGIC; signal d_i_1_0_ack_in : STD_LOGIC; signal d_i_1_0_ack_out : STD_LOGIC; signal d_i_1_0_payload_A : STD_LOGIC_VECTOR (15 downto 0); signal d_i_1_0_payload_B : STD_LOGIC_VECTOR (15 downto 0); signal d_i_1_0_sel_rd : STD_LOGIC := '0'; signal d_i_1_0_sel_wr : STD_LOGIC := '0'; signal d_i_1_0_sel : STD_LOGIC; signal d_i_1_0_load_A : STD_LOGIC; signal d_i_1_0_load_B : STD_LOGIC; signal d_i_1_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00"; signal d_i_1_0_state_cmp_full : STD_LOGIC; signal d_i_2_0_data_out : STD_LOGIC_VECTOR (15 downto 0); signal d_i_2_0_vld_in : STD_LOGIC; signal d_i_2_0_ack_in : STD_LOGIC; signal d_i_2_0_ack_out : STD_LOGIC; signal d_i_2_0_payload_A : STD_LOGIC_VECTOR (15 downto 0); signal d_i_2_0_payload_B : STD_LOGIC_VECTOR (15 downto 0); signal d_i_2_0_sel_rd : STD_LOGIC := '0'; signal d_i_2_0_sel_wr : STD_LOGIC := '0'; signal d_i_2_0_sel : STD_LOGIC; signal d_i_2_0_load_A : STD_LOGIC; signal d_i_2_0_load_B : STD_LOGIC; signal d_i_2_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00"; signal d_i_2_0_state_cmp_full : STD_LOGIC; signal d_i_3_0_data_out : STD_LOGIC_VECTOR (15 downto 0); signal d_i_3_0_vld_in : STD_LOGIC; signal d_i_3_0_ack_in : STD_LOGIC; signal d_i_3_0_ack_out : STD_LOGIC; signal d_i_3_0_payload_A : STD_LOGIC_VECTOR (15 downto 0); signal d_i_3_0_payload_B : STD_LOGIC_VECTOR (15 downto 0); signal d_i_3_0_sel_rd : STD_LOGIC := '0'; signal d_i_3_0_sel_wr : STD_LOGIC := '0'; signal d_i_3_0_sel : STD_LOGIC; signal d_i_3_0_load_A : STD_LOGIC; signal d_i_3_0_load_B : STD_LOGIC; signal d_i_3_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00"; signal d_i_3_0_state_cmp_full : STD_LOGIC; signal d_i_4_0_data_out : STD_LOGIC_VECTOR (15 downto 0); signal d_i_4_0_vld_in : STD_LOGIC; signal d_i_4_0_ack_in : STD_LOGIC; signal d_i_4_0_ack_out : STD_LOGIC; signal d_i_4_0_payload_A : STD_LOGIC_VECTOR (15 downto 0); signal d_i_4_0_payload_B : STD_LOGIC_VECTOR (15 downto 0); signal d_i_4_0_sel_rd : STD_LOGIC := '0'; signal d_i_4_0_sel_wr : STD_LOGIC := '0'; signal d_i_4_0_sel : STD_LOGIC; signal d_i_4_0_load_A : STD_LOGIC; signal d_i_4_0_load_B : STD_LOGIC; signal d_i_4_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00"; signal d_i_4_0_state_cmp_full : STD_LOGIC; signal d_i_5_0_data_out : STD_LOGIC_VECTOR (15 downto 0); signal d_i_5_0_vld_in : STD_LOGIC; signal d_i_5_0_ack_in : STD_LOGIC; signal d_i_5_0_ack_out : STD_LOGIC; signal d_i_5_0_payload_A : STD_LOGIC_VECTOR (15 downto 0); signal d_i_5_0_payload_B : STD_LOGIC_VECTOR (15 downto 0); signal d_i_5_0_sel_rd : STD_LOGIC := '0'; signal d_i_5_0_sel_wr : STD_LOGIC := '0'; signal d_i_5_0_sel : STD_LOGIC; signal d_i_5_0_load_A : STD_LOGIC; signal d_i_5_0_load_B : STD_LOGIC; signal d_i_5_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00"; signal d_i_5_0_state_cmp_full : STD_LOGIC; signal d_i_6_0_data_out : STD_LOGIC_VECTOR (15 downto 0); signal d_i_6_0_vld_in : STD_LOGIC; signal d_i_6_0_ack_in : STD_LOGIC; signal d_i_6_0_ack_out : STD_LOGIC; signal d_i_6_0_payload_A : STD_LOGIC_VECTOR (15 downto 0); signal d_i_6_0_payload_B : STD_LOGIC_VECTOR (15 downto 0); signal d_i_6_0_sel_rd : STD_LOGIC := '0'; signal d_i_6_0_sel_wr : STD_LOGIC := '0'; signal d_i_6_0_sel : STD_LOGIC; signal d_i_6_0_load_A : STD_LOGIC; signal d_i_6_0_load_B : STD_LOGIC; signal d_i_6_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00"; signal d_i_6_0_state_cmp_full : STD_LOGIC; signal d_i_7_0_data_out : STD_LOGIC_VECTOR (15 downto 0); signal d_i_7_0_vld_in : STD_LOGIC; signal d_i_7_0_ack_in : STD_LOGIC; signal d_i_7_0_ack_out : STD_LOGIC; signal d_i_7_0_payload_A : STD_LOGIC_VECTOR (15 downto 0); signal d_i_7_0_payload_B : STD_LOGIC_VECTOR (15 downto 0); signal d_i_7_0_sel_rd : STD_LOGIC := '0'; signal d_i_7_0_sel_wr : STD_LOGIC := '0'; signal d_i_7_0_sel : STD_LOGIC; signal d_i_7_0_load_A : STD_LOGIC; signal d_i_7_0_load_B : STD_LOGIC; signal d_i_7_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00"; signal d_i_7_0_state_cmp_full : STD_LOGIC; signal acc_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; signal acc_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; signal acc_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; signal acc_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; signal acc_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; signal acc_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; signal acc_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; signal acc_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; signal d_o_0_TDATA_blk_n : STD_LOGIC; signal ap_block_pp0_stage0_flag00000000 : BOOLEAN; signal d_o_1_TDATA_blk_n : STD_LOGIC; signal d_o_2_TDATA_blk_n : STD_LOGIC; signal d_o_3_TDATA_blk_n : STD_LOGIC; signal d_o_4_TDATA_blk_n : STD_LOGIC; signal d_o_5_TDATA_blk_n : STD_LOGIC; signal d_o_6_TDATA_blk_n : STD_LOGIC; signal d_o_7_TDATA_blk_n : STD_LOGIC; signal d_i_0_TDATA_blk_n : STD_LOGIC; signal d_i_1_TDATA_blk_n : STD_LOGIC; signal d_i_2_TDATA_blk_n : STD_LOGIC; signal d_i_3_TDATA_blk_n : STD_LOGIC; signal d_i_4_TDATA_blk_n : STD_LOGIC; signal d_i_5_TDATA_blk_n : STD_LOGIC; signal d_i_6_TDATA_blk_n : STD_LOGIC; signal d_i_7_TDATA_blk_n : STD_LOGIC; signal i1_reg_218 : STD_LOGIC_VECTOR (4 downto 0); signal tmp_17_fu_242_p1 : STD_LOGIC_VECTOR (4 downto 0); signal tmp_17_reg_502 : STD_LOGIC_VECTOR (4 downto 0); signal exitcond_reg_507 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_pp0_iter1_exitcond_reg_507 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_8_fu_278_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_2_1_fu_309_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_2_2_fu_340_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_2_3_fu_371_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_2_4_fu_402_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_2_5_fu_433_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_2_6_fu_464_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_2_7_fu_495_p2 : STD_LOGIC_VECTOR (15 downto 0); signal ap_block_pp0_stage0_flag00011011 : BOOLEAN; signal i1_phi_fu_222_p6 : STD_LOGIC_VECTOR (4 downto 0); signal tmp_1_fu_266_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_1_1_fu_297_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_1_2_fu_328_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_1_3_fu_359_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_1_4_fu_390_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_1_5_fu_421_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_1_6_fu_452_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_1_7_fu_483_p2 : STD_LOGIC_VECTOR (31 downto 0); signal ap_block_pp0_stage0_flag00001001 : BOOLEAN; signal i1_cast_fu_232_p1 : STD_LOGIC_VECTOR (5 downto 0); signal i_1_7_fu_236_p2 : STD_LOGIC_VECTOR (5 downto 0); signal tmp1_fu_258_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_2_fu_262_p1 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_s_fu_289_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_10_fu_293_p1 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_9_fu_320_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_11_fu_324_p1 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_3_fu_351_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_12_fu_355_p1 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_4_fu_382_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_13_fu_386_p1 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_5_fu_413_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_14_fu_417_p1 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_6_fu_444_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_15_fu_448_p1 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_7_fu_475_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_16_fu_479_p1 : STD_LOGIC_VECTOR (15 downto 0); signal ap_NS_fsm : STD_LOGIC_VECTOR (1 downto 0); signal ap_idle_pp0_0to1 : STD_LOGIC; signal ap_reset_idle_pp0 : STD_LOGIC; signal ap_idle_pp0 : STD_LOGIC; signal ap_enable_pp0 : STD_LOGIC; signal ap_condition_1051 : BOOLEAN; component axi_interfaces_AXILiteS_s_axi IS generic ( C_S_AXI_ADDR_WIDTH : INTEGER; C_S_AXI_DATA_WIDTH : INTEGER ); port ( AWVALID : IN STD_LOGIC; AWREADY : OUT STD_LOGIC; AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0); WVALID : IN STD_LOGIC; WREADY : OUT STD_LOGIC; WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0); WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0); ARVALID : IN STD_LOGIC; ARREADY : OUT STD_LOGIC; ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0); RVALID : OUT STD_LOGIC; RREADY : IN STD_LOGIC; RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0); RRESP : OUT STD_LOGIC_VECTOR (1 downto 0); BVALID : OUT STD_LOGIC; BREADY : IN STD_LOGIC; BRESP : OUT STD_LOGIC_VECTOR (1 downto 0); ACLK : IN STD_LOGIC; ARESET : IN STD_LOGIC; ACLK_EN : IN STD_LOGIC; ap_start : OUT STD_LOGIC; interrupt : OUT STD_LOGIC; ap_ready : IN STD_LOGIC; ap_done : IN STD_LOGIC; ap_idle : IN STD_LOGIC ); end component; begin axi_interfaces_AXILiteS_s_axi_U : component axi_interfaces_AXILiteS_s_axi generic map ( C_S_AXI_ADDR_WIDTH => C_S_AXI_AXILITES_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_AXILITES_DATA_WIDTH) port map ( AWVALID => s_axi_AXILiteS_AWVALID, AWREADY => s_axi_AXILiteS_AWREADY, AWADDR => s_axi_AXILiteS_AWADDR, WVALID => s_axi_AXILiteS_WVALID, WREADY => s_axi_AXILiteS_WREADY, WDATA => s_axi_AXILiteS_WDATA, WSTRB => s_axi_AXILiteS_WSTRB, ARVALID => s_axi_AXILiteS_ARVALID, ARREADY => s_axi_AXILiteS_ARREADY, ARADDR => s_axi_AXILiteS_ARADDR, RVALID => s_axi_AXILiteS_RVALID, RREADY => s_axi_AXILiteS_RREADY, RDATA => s_axi_AXILiteS_RDATA, RRESP => s_axi_AXILiteS_RRESP, BVALID => s_axi_AXILiteS_BVALID, BREADY => s_axi_AXILiteS_BREADY, BRESP => s_axi_AXILiteS_BRESP, ACLK => ap_clk, ARESET => ap_rst_n_inv, ACLK_EN => ap_const_logic_1, ap_start => ap_start, interrupt => interrupt, ap_ready => ap_ready, ap_done => ap_done, ap_idle => ap_idle); ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_CS_fsm <= ap_ST_fsm_state1; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_enable_reg_pp0_iter1 <= ap_const_logic_0; else if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0))) then ap_enable_reg_pp0_iter1 <= ap_start; elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then ap_enable_reg_pp0_iter1 <= ap_const_logic_0; end if; end if; end if; end process; ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_enable_reg_pp0_iter2 <= ap_const_logic_0; else if ((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0)) then ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then ap_enable_reg_pp0_iter2 <= ap_const_logic_0; end if; end if; end if; end process; d_i_0_0_sel_rd_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_0_0_sel_rd <= ap_const_logic_0; else if (((ap_const_logic_1 = d_i_0_0_ack_out) and (ap_const_logic_1 = d_i_0_0_vld_out))) then d_i_0_0_sel_rd <= not(d_i_0_0_sel_rd); end if; end if; end if; end process; d_i_0_0_sel_wr_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_0_0_sel_wr <= ap_const_logic_0; else if (((ap_const_logic_1 = d_i_0_0_vld_in) and (ap_const_logic_1 = d_i_0_0_ack_in))) then d_i_0_0_sel_wr <= not(d_i_0_0_sel_wr); end if; end if; end if; end process; d_i_0_0_state_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_0_0_state <= ap_const_lv2_0; else if ((((ap_const_logic_0 = d_i_0_0_vld_in) and (ap_const_logic_1 = d_i_0_0_ack_out) and (ap_const_lv2_3 = d_i_0_0_state)) or ((ap_const_logic_0 = d_i_0_0_vld_in) and (ap_const_lv2_2 = d_i_0_0_state)))) then d_i_0_0_state <= ap_const_lv2_2; elsif ((((ap_const_logic_1 = d_i_0_0_vld_in) and (ap_const_logic_0 = d_i_0_0_ack_out) and (ap_const_lv2_3 = d_i_0_0_state)) or ((ap_const_logic_0 = d_i_0_0_ack_out) and (ap_const_lv2_1 = d_i_0_0_state)))) then d_i_0_0_state <= ap_const_lv2_1; elsif ((((ap_const_logic_1 = d_i_0_0_vld_in) and (ap_const_lv2_2 = d_i_0_0_state)) or ((ap_const_logic_1 = d_i_0_0_ack_out) and (ap_const_lv2_1 = d_i_0_0_state)) or ((ap_const_lv2_3 = d_i_0_0_state) and not(((ap_const_logic_1 = d_i_0_0_vld_in) and (ap_const_logic_0 = d_i_0_0_ack_out))) and not(((ap_const_logic_0 = d_i_0_0_vld_in) and (ap_const_logic_1 = d_i_0_0_ack_out)))))) then d_i_0_0_state <= ap_const_lv2_3; else d_i_0_0_state <= ap_const_lv2_2; end if; end if; end if; end process; d_i_1_0_sel_rd_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_1_0_sel_rd <= ap_const_logic_0; else if (((ap_const_logic_1 = d_i_1_0_ack_out) and (ap_const_logic_1 = d_i_1_0_vld_out))) then d_i_1_0_sel_rd <= not(d_i_1_0_sel_rd); end if; end if; end if; end process; d_i_1_0_sel_wr_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_1_0_sel_wr <= ap_const_logic_0; else if (((ap_const_logic_1 = d_i_1_0_vld_in) and (ap_const_logic_1 = d_i_1_0_ack_in))) then d_i_1_0_sel_wr <= not(d_i_1_0_sel_wr); end if; end if; end if; end process; d_i_1_0_state_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_1_0_state <= ap_const_lv2_0; else if ((((ap_const_logic_0 = d_i_1_0_vld_in) and (ap_const_logic_1 = d_i_1_0_ack_out) and (ap_const_lv2_3 = d_i_1_0_state)) or ((ap_const_logic_0 = d_i_1_0_vld_in) and (ap_const_lv2_2 = d_i_1_0_state)))) then d_i_1_0_state <= ap_const_lv2_2; elsif ((((ap_const_logic_1 = d_i_1_0_vld_in) and (ap_const_logic_0 = d_i_1_0_ack_out) and (ap_const_lv2_3 = d_i_1_0_state)) or ((ap_const_logic_0 = d_i_1_0_ack_out) and (ap_const_lv2_1 = d_i_1_0_state)))) then d_i_1_0_state <= ap_const_lv2_1; elsif ((((ap_const_logic_1 = d_i_1_0_vld_in) and (ap_const_lv2_2 = d_i_1_0_state)) or ((ap_const_logic_1 = d_i_1_0_ack_out) and (ap_const_lv2_1 = d_i_1_0_state)) or ((ap_const_lv2_3 = d_i_1_0_state) and not(((ap_const_logic_1 = d_i_1_0_vld_in) and (ap_const_logic_0 = d_i_1_0_ack_out))) and not(((ap_const_logic_0 = d_i_1_0_vld_in) and (ap_const_logic_1 = d_i_1_0_ack_out)))))) then d_i_1_0_state <= ap_const_lv2_3; else d_i_1_0_state <= ap_const_lv2_2; end if; end if; end if; end process; d_i_2_0_sel_rd_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_2_0_sel_rd <= ap_const_logic_0; else if (((ap_const_logic_1 = d_i_2_0_ack_out) and (ap_const_logic_1 = d_i_2_0_vld_out))) then d_i_2_0_sel_rd <= not(d_i_2_0_sel_rd); end if; end if; end if; end process; d_i_2_0_sel_wr_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_2_0_sel_wr <= ap_const_logic_0; else if (((ap_const_logic_1 = d_i_2_0_vld_in) and (ap_const_logic_1 = d_i_2_0_ack_in))) then d_i_2_0_sel_wr <= not(d_i_2_0_sel_wr); end if; end if; end if; end process; d_i_2_0_state_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_2_0_state <= ap_const_lv2_0; else if ((((ap_const_logic_0 = d_i_2_0_vld_in) and (ap_const_logic_1 = d_i_2_0_ack_out) and (ap_const_lv2_3 = d_i_2_0_state)) or ((ap_const_logic_0 = d_i_2_0_vld_in) and (ap_const_lv2_2 = d_i_2_0_state)))) then d_i_2_0_state <= ap_const_lv2_2; elsif ((((ap_const_logic_1 = d_i_2_0_vld_in) and (ap_const_logic_0 = d_i_2_0_ack_out) and (ap_const_lv2_3 = d_i_2_0_state)) or ((ap_const_logic_0 = d_i_2_0_ack_out) and (ap_const_lv2_1 = d_i_2_0_state)))) then d_i_2_0_state <= ap_const_lv2_1; elsif ((((ap_const_logic_1 = d_i_2_0_vld_in) and (ap_const_lv2_2 = d_i_2_0_state)) or ((ap_const_logic_1 = d_i_2_0_ack_out) and (ap_const_lv2_1 = d_i_2_0_state)) or ((ap_const_lv2_3 = d_i_2_0_state) and not(((ap_const_logic_1 = d_i_2_0_vld_in) and (ap_const_logic_0 = d_i_2_0_ack_out))) and not(((ap_const_logic_0 = d_i_2_0_vld_in) and (ap_const_logic_1 = d_i_2_0_ack_out)))))) then d_i_2_0_state <= ap_const_lv2_3; else d_i_2_0_state <= ap_const_lv2_2; end if; end if; end if; end process; d_i_3_0_sel_rd_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_3_0_sel_rd <= ap_const_logic_0; else if (((ap_const_logic_1 = d_i_3_0_ack_out) and (ap_const_logic_1 = d_i_3_0_vld_out))) then d_i_3_0_sel_rd <= not(d_i_3_0_sel_rd); end if; end if; end if; end process; d_i_3_0_sel_wr_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_3_0_sel_wr <= ap_const_logic_0; else if (((ap_const_logic_1 = d_i_3_0_vld_in) and (ap_const_logic_1 = d_i_3_0_ack_in))) then d_i_3_0_sel_wr <= not(d_i_3_0_sel_wr); end if; end if; end if; end process; d_i_3_0_state_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_3_0_state <= ap_const_lv2_0; else if ((((ap_const_logic_0 = d_i_3_0_vld_in) and (ap_const_logic_1 = d_i_3_0_ack_out) and (ap_const_lv2_3 = d_i_3_0_state)) or ((ap_const_logic_0 = d_i_3_0_vld_in) and (ap_const_lv2_2 = d_i_3_0_state)))) then d_i_3_0_state <= ap_const_lv2_2; elsif ((((ap_const_logic_1 = d_i_3_0_vld_in) and (ap_const_logic_0 = d_i_3_0_ack_out) and (ap_const_lv2_3 = d_i_3_0_state)) or ((ap_const_logic_0 = d_i_3_0_ack_out) and (ap_const_lv2_1 = d_i_3_0_state)))) then d_i_3_0_state <= ap_const_lv2_1; elsif ((((ap_const_logic_1 = d_i_3_0_vld_in) and (ap_const_lv2_2 = d_i_3_0_state)) or ((ap_const_logic_1 = d_i_3_0_ack_out) and (ap_const_lv2_1 = d_i_3_0_state)) or ((ap_const_lv2_3 = d_i_3_0_state) and not(((ap_const_logic_1 = d_i_3_0_vld_in) and (ap_const_logic_0 = d_i_3_0_ack_out))) and not(((ap_const_logic_0 = d_i_3_0_vld_in) and (ap_const_logic_1 = d_i_3_0_ack_out)))))) then d_i_3_0_state <= ap_const_lv2_3; else d_i_3_0_state <= ap_const_lv2_2; end if; end if; end if; end process; d_i_4_0_sel_rd_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_4_0_sel_rd <= ap_const_logic_0; else if (((ap_const_logic_1 = d_i_4_0_ack_out) and (ap_const_logic_1 = d_i_4_0_vld_out))) then d_i_4_0_sel_rd <= not(d_i_4_0_sel_rd); end if; end if; end if; end process; d_i_4_0_sel_wr_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_4_0_sel_wr <= ap_const_logic_0; else if (((ap_const_logic_1 = d_i_4_0_vld_in) and (ap_const_logic_1 = d_i_4_0_ack_in))) then d_i_4_0_sel_wr <= not(d_i_4_0_sel_wr); end if; end if; end if; end process; d_i_4_0_state_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_4_0_state <= ap_const_lv2_0; else if ((((ap_const_logic_0 = d_i_4_0_vld_in) and (ap_const_logic_1 = d_i_4_0_ack_out) and (ap_const_lv2_3 = d_i_4_0_state)) or ((ap_const_logic_0 = d_i_4_0_vld_in) and (ap_const_lv2_2 = d_i_4_0_state)))) then d_i_4_0_state <= ap_const_lv2_2; elsif ((((ap_const_logic_1 = d_i_4_0_vld_in) and (ap_const_logic_0 = d_i_4_0_ack_out) and (ap_const_lv2_3 = d_i_4_0_state)) or ((ap_const_logic_0 = d_i_4_0_ack_out) and (ap_const_lv2_1 = d_i_4_0_state)))) then d_i_4_0_state <= ap_const_lv2_1; elsif ((((ap_const_logic_1 = d_i_4_0_vld_in) and (ap_const_lv2_2 = d_i_4_0_state)) or ((ap_const_logic_1 = d_i_4_0_ack_out) and (ap_const_lv2_1 = d_i_4_0_state)) or ((ap_const_lv2_3 = d_i_4_0_state) and not(((ap_const_logic_1 = d_i_4_0_vld_in) and (ap_const_logic_0 = d_i_4_0_ack_out))) and not(((ap_const_logic_0 = d_i_4_0_vld_in) and (ap_const_logic_1 = d_i_4_0_ack_out)))))) then d_i_4_0_state <= ap_const_lv2_3; else d_i_4_0_state <= ap_const_lv2_2; end if; end if; end if; end process; d_i_5_0_sel_rd_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_5_0_sel_rd <= ap_const_logic_0; else if (((ap_const_logic_1 = d_i_5_0_ack_out) and (ap_const_logic_1 = d_i_5_0_vld_out))) then d_i_5_0_sel_rd <= not(d_i_5_0_sel_rd); end if; end if; end if; end process; d_i_5_0_sel_wr_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_5_0_sel_wr <= ap_const_logic_0; else if (((ap_const_logic_1 = d_i_5_0_vld_in) and (ap_const_logic_1 = d_i_5_0_ack_in))) then d_i_5_0_sel_wr <= not(d_i_5_0_sel_wr); end if; end if; end if; end process; d_i_5_0_state_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_5_0_state <= ap_const_lv2_0; else if ((((ap_const_logic_0 = d_i_5_0_vld_in) and (ap_const_logic_1 = d_i_5_0_ack_out) and (ap_const_lv2_3 = d_i_5_0_state)) or ((ap_const_logic_0 = d_i_5_0_vld_in) and (ap_const_lv2_2 = d_i_5_0_state)))) then d_i_5_0_state <= ap_const_lv2_2; elsif ((((ap_const_logic_1 = d_i_5_0_vld_in) and (ap_const_logic_0 = d_i_5_0_ack_out) and (ap_const_lv2_3 = d_i_5_0_state)) or ((ap_const_logic_0 = d_i_5_0_ack_out) and (ap_const_lv2_1 = d_i_5_0_state)))) then d_i_5_0_state <= ap_const_lv2_1; elsif ((((ap_const_logic_1 = d_i_5_0_vld_in) and (ap_const_lv2_2 = d_i_5_0_state)) or ((ap_const_logic_1 = d_i_5_0_ack_out) and (ap_const_lv2_1 = d_i_5_0_state)) or ((ap_const_lv2_3 = d_i_5_0_state) and not(((ap_const_logic_1 = d_i_5_0_vld_in) and (ap_const_logic_0 = d_i_5_0_ack_out))) and not(((ap_const_logic_0 = d_i_5_0_vld_in) and (ap_const_logic_1 = d_i_5_0_ack_out)))))) then d_i_5_0_state <= ap_const_lv2_3; else d_i_5_0_state <= ap_const_lv2_2; end if; end if; end if; end process; d_i_6_0_sel_rd_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_6_0_sel_rd <= ap_const_logic_0; else if (((ap_const_logic_1 = d_i_6_0_ack_out) and (ap_const_logic_1 = d_i_6_0_vld_out))) then d_i_6_0_sel_rd <= not(d_i_6_0_sel_rd); end if; end if; end if; end process; d_i_6_0_sel_wr_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_6_0_sel_wr <= ap_const_logic_0; else if (((ap_const_logic_1 = d_i_6_0_vld_in) and (ap_const_logic_1 = d_i_6_0_ack_in))) then d_i_6_0_sel_wr <= not(d_i_6_0_sel_wr); end if; end if; end if; end process; d_i_6_0_state_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_6_0_state <= ap_const_lv2_0; else if ((((ap_const_logic_0 = d_i_6_0_vld_in) and (ap_const_logic_1 = d_i_6_0_ack_out) and (ap_const_lv2_3 = d_i_6_0_state)) or ((ap_const_logic_0 = d_i_6_0_vld_in) and (ap_const_lv2_2 = d_i_6_0_state)))) then d_i_6_0_state <= ap_const_lv2_2; elsif ((((ap_const_logic_1 = d_i_6_0_vld_in) and (ap_const_logic_0 = d_i_6_0_ack_out) and (ap_const_lv2_3 = d_i_6_0_state)) or ((ap_const_logic_0 = d_i_6_0_ack_out) and (ap_const_lv2_1 = d_i_6_0_state)))) then d_i_6_0_state <= ap_const_lv2_1; elsif ((((ap_const_logic_1 = d_i_6_0_vld_in) and (ap_const_lv2_2 = d_i_6_0_state)) or ((ap_const_logic_1 = d_i_6_0_ack_out) and (ap_const_lv2_1 = d_i_6_0_state)) or ((ap_const_lv2_3 = d_i_6_0_state) and not(((ap_const_logic_1 = d_i_6_0_vld_in) and (ap_const_logic_0 = d_i_6_0_ack_out))) and not(((ap_const_logic_0 = d_i_6_0_vld_in) and (ap_const_logic_1 = d_i_6_0_ack_out)))))) then d_i_6_0_state <= ap_const_lv2_3; else d_i_6_0_state <= ap_const_lv2_2; end if; end if; end if; end process; d_i_7_0_sel_rd_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_7_0_sel_rd <= ap_const_logic_0; else if (((ap_const_logic_1 = d_i_7_0_ack_out) and (ap_const_logic_1 = d_i_7_0_vld_out))) then d_i_7_0_sel_rd <= not(d_i_7_0_sel_rd); end if; end if; end if; end process; d_i_7_0_sel_wr_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_7_0_sel_wr <= ap_const_logic_0; else if (((ap_const_logic_1 = d_i_7_0_vld_in) and (ap_const_logic_1 = d_i_7_0_ack_in))) then d_i_7_0_sel_wr <= not(d_i_7_0_sel_wr); end if; end if; end if; end process; d_i_7_0_state_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_7_0_state <= ap_const_lv2_0; else if ((((ap_const_logic_0 = d_i_7_0_vld_in) and (ap_const_logic_1 = d_i_7_0_ack_out) and (ap_const_lv2_3 = d_i_7_0_state)) or ((ap_const_logic_0 = d_i_7_0_vld_in) and (ap_const_lv2_2 = d_i_7_0_state)))) then d_i_7_0_state <= ap_const_lv2_2; elsif ((((ap_const_logic_1 = d_i_7_0_vld_in) and (ap_const_logic_0 = d_i_7_0_ack_out) and (ap_const_lv2_3 = d_i_7_0_state)) or ((ap_const_logic_0 = d_i_7_0_ack_out) and (ap_const_lv2_1 = d_i_7_0_state)))) then d_i_7_0_state <= ap_const_lv2_1; elsif ((((ap_const_logic_1 = d_i_7_0_vld_in) and (ap_const_lv2_2 = d_i_7_0_state)) or ((ap_const_logic_1 = d_i_7_0_ack_out) and (ap_const_lv2_1 = d_i_7_0_state)) or ((ap_const_lv2_3 = d_i_7_0_state) and not(((ap_const_logic_1 = d_i_7_0_vld_in) and (ap_const_logic_0 = d_i_7_0_ack_out))) and not(((ap_const_logic_0 = d_i_7_0_vld_in) and (ap_const_logic_1 = d_i_7_0_ack_out)))))) then d_i_7_0_state <= ap_const_lv2_3; else d_i_7_0_state <= ap_const_lv2_2; end if; end if; end if; end process; d_o_0_1_sel_rd_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_0_1_sel_rd <= ap_const_logic_0; else if (((ap_const_logic_1 = d_o_0_1_ack_out) and (ap_const_logic_1 = d_o_0_1_vld_out))) then d_o_0_1_sel_rd <= not(d_o_0_1_sel_rd); end if; end if; end if; end process; d_o_0_1_sel_wr_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_0_1_sel_wr <= ap_const_logic_0; else if (((ap_const_logic_1 = d_o_0_1_vld_in) and (ap_const_logic_1 = d_o_0_1_ack_in))) then d_o_0_1_sel_wr <= not(d_o_0_1_sel_wr); end if; end if; end if; end process; d_o_0_1_state_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_0_1_state <= ap_const_lv2_0; else if ((((ap_const_logic_0 = d_o_0_1_vld_in) and (ap_const_logic_1 = d_o_0_1_ack_out) and (d_o_0_1_state = ap_const_lv2_3)) or ((ap_const_logic_0 = d_o_0_1_vld_in) and (d_o_0_1_state = ap_const_lv2_2)))) then d_o_0_1_state <= ap_const_lv2_2; elsif ((((ap_const_logic_1 = d_o_0_1_vld_in) and (ap_const_logic_0 = d_o_0_1_ack_out) and (d_o_0_1_state = ap_const_lv2_3)) or ((ap_const_logic_0 = d_o_0_1_ack_out) and (d_o_0_1_state = ap_const_lv2_1)))) then d_o_0_1_state <= ap_const_lv2_1; elsif ((((ap_const_logic_1 = d_o_0_1_vld_in) and (d_o_0_1_state = ap_const_lv2_2)) or ((ap_const_logic_1 = d_o_0_1_ack_out) and (d_o_0_1_state = ap_const_lv2_1)) or ((d_o_0_1_state = ap_const_lv2_3) and not(((ap_const_logic_1 = d_o_0_1_vld_in) and (ap_const_logic_0 = d_o_0_1_ack_out))) and not(((ap_const_logic_0 = d_o_0_1_vld_in) and (ap_const_logic_1 = d_o_0_1_ack_out)))))) then d_o_0_1_state <= ap_const_lv2_3; else d_o_0_1_state <= ap_const_lv2_2; end if; end if; end if; end process; d_o_1_1_sel_rd_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_1_1_sel_rd <= ap_const_logic_0; else if (((ap_const_logic_1 = d_o_1_1_ack_out) and (ap_const_logic_1 = d_o_1_1_vld_out))) then d_o_1_1_sel_rd <= not(d_o_1_1_sel_rd); end if; end if; end if; end process; d_o_1_1_sel_wr_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_1_1_sel_wr <= ap_const_logic_0; else if (((ap_const_logic_1 = d_o_1_1_vld_in) and (ap_const_logic_1 = d_o_1_1_ack_in))) then d_o_1_1_sel_wr <= not(d_o_1_1_sel_wr); end if; end if; end if; end process; d_o_1_1_state_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_1_1_state <= ap_const_lv2_0; else if ((((ap_const_logic_0 = d_o_1_1_vld_in) and (ap_const_logic_1 = d_o_1_1_ack_out) and (ap_const_lv2_3 = d_o_1_1_state)) or ((ap_const_logic_0 = d_o_1_1_vld_in) and (ap_const_lv2_2 = d_o_1_1_state)))) then d_o_1_1_state <= ap_const_lv2_2; elsif ((((ap_const_logic_1 = d_o_1_1_vld_in) and (ap_const_logic_0 = d_o_1_1_ack_out) and (ap_const_lv2_3 = d_o_1_1_state)) or ((ap_const_logic_0 = d_o_1_1_ack_out) and (ap_const_lv2_1 = d_o_1_1_state)))) then d_o_1_1_state <= ap_const_lv2_1; elsif ((((ap_const_logic_1 = d_o_1_1_vld_in) and (ap_const_lv2_2 = d_o_1_1_state)) or ((ap_const_logic_1 = d_o_1_1_ack_out) and (ap_const_lv2_1 = d_o_1_1_state)) or ((ap_const_lv2_3 = d_o_1_1_state) and not(((ap_const_logic_1 = d_o_1_1_vld_in) and (ap_const_logic_0 = d_o_1_1_ack_out))) and not(((ap_const_logic_0 = d_o_1_1_vld_in) and (ap_const_logic_1 = d_o_1_1_ack_out)))))) then d_o_1_1_state <= ap_const_lv2_3; else d_o_1_1_state <= ap_const_lv2_2; end if; end if; end if; end process; d_o_2_1_sel_rd_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_2_1_sel_rd <= ap_const_logic_0; else if (((ap_const_logic_1 = d_o_2_1_ack_out) and (ap_const_logic_1 = d_o_2_1_vld_out))) then d_o_2_1_sel_rd <= not(d_o_2_1_sel_rd); end if; end if; end if; end process; d_o_2_1_sel_wr_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_2_1_sel_wr <= ap_const_logic_0; else if (((ap_const_logic_1 = d_o_2_1_vld_in) and (ap_const_logic_1 = d_o_2_1_ack_in))) then d_o_2_1_sel_wr <= not(d_o_2_1_sel_wr); end if; end if; end if; end process; d_o_2_1_state_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_2_1_state <= ap_const_lv2_0; else if ((((ap_const_logic_0 = d_o_2_1_vld_in) and (ap_const_logic_1 = d_o_2_1_ack_out) and (ap_const_lv2_3 = d_o_2_1_state)) or ((ap_const_logic_0 = d_o_2_1_vld_in) and (ap_const_lv2_2 = d_o_2_1_state)))) then d_o_2_1_state <= ap_const_lv2_2; elsif ((((ap_const_logic_1 = d_o_2_1_vld_in) and (ap_const_logic_0 = d_o_2_1_ack_out) and (ap_const_lv2_3 = d_o_2_1_state)) or ((ap_const_logic_0 = d_o_2_1_ack_out) and (ap_const_lv2_1 = d_o_2_1_state)))) then d_o_2_1_state <= ap_const_lv2_1; elsif ((((ap_const_logic_1 = d_o_2_1_vld_in) and (ap_const_lv2_2 = d_o_2_1_state)) or ((ap_const_logic_1 = d_o_2_1_ack_out) and (ap_const_lv2_1 = d_o_2_1_state)) or ((ap_const_lv2_3 = d_o_2_1_state) and not(((ap_const_logic_1 = d_o_2_1_vld_in) and (ap_const_logic_0 = d_o_2_1_ack_out))) and not(((ap_const_logic_0 = d_o_2_1_vld_in) and (ap_const_logic_1 = d_o_2_1_ack_out)))))) then d_o_2_1_state <= ap_const_lv2_3; else d_o_2_1_state <= ap_const_lv2_2; end if; end if; end if; end process; d_o_3_1_sel_rd_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_3_1_sel_rd <= ap_const_logic_0; else if (((ap_const_logic_1 = d_o_3_1_ack_out) and (ap_const_logic_1 = d_o_3_1_vld_out))) then d_o_3_1_sel_rd <= not(d_o_3_1_sel_rd); end if; end if; end if; end process; d_o_3_1_sel_wr_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_3_1_sel_wr <= ap_const_logic_0; else if (((ap_const_logic_1 = d_o_3_1_vld_in) and (ap_const_logic_1 = d_o_3_1_ack_in))) then d_o_3_1_sel_wr <= not(d_o_3_1_sel_wr); end if; end if; end if; end process; d_o_3_1_state_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_3_1_state <= ap_const_lv2_0; else if ((((ap_const_logic_0 = d_o_3_1_vld_in) and (ap_const_logic_1 = d_o_3_1_ack_out) and (ap_const_lv2_3 = d_o_3_1_state)) or ((ap_const_logic_0 = d_o_3_1_vld_in) and (ap_const_lv2_2 = d_o_3_1_state)))) then d_o_3_1_state <= ap_const_lv2_2; elsif ((((ap_const_logic_1 = d_o_3_1_vld_in) and (ap_const_logic_0 = d_o_3_1_ack_out) and (ap_const_lv2_3 = d_o_3_1_state)) or ((ap_const_logic_0 = d_o_3_1_ack_out) and (ap_const_lv2_1 = d_o_3_1_state)))) then d_o_3_1_state <= ap_const_lv2_1; elsif ((((ap_const_logic_1 = d_o_3_1_vld_in) and (ap_const_lv2_2 = d_o_3_1_state)) or ((ap_const_logic_1 = d_o_3_1_ack_out) and (ap_const_lv2_1 = d_o_3_1_state)) or ((ap_const_lv2_3 = d_o_3_1_state) and not(((ap_const_logic_1 = d_o_3_1_vld_in) and (ap_const_logic_0 = d_o_3_1_ack_out))) and not(((ap_const_logic_0 = d_o_3_1_vld_in) and (ap_const_logic_1 = d_o_3_1_ack_out)))))) then d_o_3_1_state <= ap_const_lv2_3; else d_o_3_1_state <= ap_const_lv2_2; end if; end if; end if; end process; d_o_4_1_sel_rd_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_4_1_sel_rd <= ap_const_logic_0; else if (((ap_const_logic_1 = d_o_4_1_ack_out) and (ap_const_logic_1 = d_o_4_1_vld_out))) then d_o_4_1_sel_rd <= not(d_o_4_1_sel_rd); end if; end if; end if; end process; d_o_4_1_sel_wr_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_4_1_sel_wr <= ap_const_logic_0; else if (((ap_const_logic_1 = d_o_4_1_vld_in) and (ap_const_logic_1 = d_o_4_1_ack_in))) then d_o_4_1_sel_wr <= not(d_o_4_1_sel_wr); end if; end if; end if; end process; d_o_4_1_state_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_4_1_state <= ap_const_lv2_0; else if ((((ap_const_logic_0 = d_o_4_1_vld_in) and (ap_const_logic_1 = d_o_4_1_ack_out) and (ap_const_lv2_3 = d_o_4_1_state)) or ((ap_const_logic_0 = d_o_4_1_vld_in) and (ap_const_lv2_2 = d_o_4_1_state)))) then d_o_4_1_state <= ap_const_lv2_2; elsif ((((ap_const_logic_1 = d_o_4_1_vld_in) and (ap_const_logic_0 = d_o_4_1_ack_out) and (ap_const_lv2_3 = d_o_4_1_state)) or ((ap_const_logic_0 = d_o_4_1_ack_out) and (ap_const_lv2_1 = d_o_4_1_state)))) then d_o_4_1_state <= ap_const_lv2_1; elsif ((((ap_const_logic_1 = d_o_4_1_vld_in) and (ap_const_lv2_2 = d_o_4_1_state)) or ((ap_const_logic_1 = d_o_4_1_ack_out) and (ap_const_lv2_1 = d_o_4_1_state)) or ((ap_const_lv2_3 = d_o_4_1_state) and not(((ap_const_logic_1 = d_o_4_1_vld_in) and (ap_const_logic_0 = d_o_4_1_ack_out))) and not(((ap_const_logic_0 = d_o_4_1_vld_in) and (ap_const_logic_1 = d_o_4_1_ack_out)))))) then d_o_4_1_state <= ap_const_lv2_3; else d_o_4_1_state <= ap_const_lv2_2; end if; end if; end if; end process; d_o_5_1_sel_rd_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_5_1_sel_rd <= ap_const_logic_0; else if (((ap_const_logic_1 = d_o_5_1_ack_out) and (ap_const_logic_1 = d_o_5_1_vld_out))) then d_o_5_1_sel_rd <= not(d_o_5_1_sel_rd); end if; end if; end if; end process; d_o_5_1_sel_wr_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_5_1_sel_wr <= ap_const_logic_0; else if (((ap_const_logic_1 = d_o_5_1_vld_in) and (ap_const_logic_1 = d_o_5_1_ack_in))) then d_o_5_1_sel_wr <= not(d_o_5_1_sel_wr); end if; end if; end if; end process; d_o_5_1_state_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_5_1_state <= ap_const_lv2_0; else if ((((ap_const_logic_0 = d_o_5_1_vld_in) and (ap_const_logic_1 = d_o_5_1_ack_out) and (ap_const_lv2_3 = d_o_5_1_state)) or ((ap_const_logic_0 = d_o_5_1_vld_in) and (ap_const_lv2_2 = d_o_5_1_state)))) then d_o_5_1_state <= ap_const_lv2_2; elsif ((((ap_const_logic_1 = d_o_5_1_vld_in) and (ap_const_logic_0 = d_o_5_1_ack_out) and (ap_const_lv2_3 = d_o_5_1_state)) or ((ap_const_logic_0 = d_o_5_1_ack_out) and (ap_const_lv2_1 = d_o_5_1_state)))) then d_o_5_1_state <= ap_const_lv2_1; elsif ((((ap_const_logic_1 = d_o_5_1_vld_in) and (ap_const_lv2_2 = d_o_5_1_state)) or ((ap_const_logic_1 = d_o_5_1_ack_out) and (ap_const_lv2_1 = d_o_5_1_state)) or ((ap_const_lv2_3 = d_o_5_1_state) and not(((ap_const_logic_1 = d_o_5_1_vld_in) and (ap_const_logic_0 = d_o_5_1_ack_out))) and not(((ap_const_logic_0 = d_o_5_1_vld_in) and (ap_const_logic_1 = d_o_5_1_ack_out)))))) then d_o_5_1_state <= ap_const_lv2_3; else d_o_5_1_state <= ap_const_lv2_2; end if; end if; end if; end process; d_o_6_1_sel_rd_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_6_1_sel_rd <= ap_const_logic_0; else if (((ap_const_logic_1 = d_o_6_1_ack_out) and (ap_const_logic_1 = d_o_6_1_vld_out))) then d_o_6_1_sel_rd <= not(d_o_6_1_sel_rd); end if; end if; end if; end process; d_o_6_1_sel_wr_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_6_1_sel_wr <= ap_const_logic_0; else if (((ap_const_logic_1 = d_o_6_1_vld_in) and (ap_const_logic_1 = d_o_6_1_ack_in))) then d_o_6_1_sel_wr <= not(d_o_6_1_sel_wr); end if; end if; end if; end process; d_o_6_1_state_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_6_1_state <= ap_const_lv2_0; else if ((((ap_const_logic_0 = d_o_6_1_vld_in) and (ap_const_logic_1 = d_o_6_1_ack_out) and (ap_const_lv2_3 = d_o_6_1_state)) or ((ap_const_logic_0 = d_o_6_1_vld_in) and (ap_const_lv2_2 = d_o_6_1_state)))) then d_o_6_1_state <= ap_const_lv2_2; elsif ((((ap_const_logic_1 = d_o_6_1_vld_in) and (ap_const_logic_0 = d_o_6_1_ack_out) and (ap_const_lv2_3 = d_o_6_1_state)) or ((ap_const_logic_0 = d_o_6_1_ack_out) and (ap_const_lv2_1 = d_o_6_1_state)))) then d_o_6_1_state <= ap_const_lv2_1; elsif ((((ap_const_logic_1 = d_o_6_1_vld_in) and (ap_const_lv2_2 = d_o_6_1_state)) or ((ap_const_logic_1 = d_o_6_1_ack_out) and (ap_const_lv2_1 = d_o_6_1_state)) or ((ap_const_lv2_3 = d_o_6_1_state) and not(((ap_const_logic_1 = d_o_6_1_vld_in) and (ap_const_logic_0 = d_o_6_1_ack_out))) and not(((ap_const_logic_0 = d_o_6_1_vld_in) and (ap_const_logic_1 = d_o_6_1_ack_out)))))) then d_o_6_1_state <= ap_const_lv2_3; else d_o_6_1_state <= ap_const_lv2_2; end if; end if; end if; end process; d_o_7_1_sel_rd_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_7_1_sel_rd <= ap_const_logic_0; else if (((ap_const_logic_1 = d_o_7_1_ack_out) and (ap_const_logic_1 = d_o_7_1_vld_out))) then d_o_7_1_sel_rd <= not(d_o_7_1_sel_rd); end if; end if; end if; end process; d_o_7_1_sel_wr_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_7_1_sel_wr <= ap_const_logic_0; else if (((ap_const_logic_1 = d_o_7_1_vld_in) and (ap_const_logic_1 = d_o_7_1_ack_in))) then d_o_7_1_sel_wr <= not(d_o_7_1_sel_wr); end if; end if; end if; end process; d_o_7_1_state_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_7_1_state <= ap_const_lv2_0; else if ((((ap_const_logic_0 = d_o_7_1_vld_in) and (ap_const_logic_1 = d_o_7_1_ack_out) and (ap_const_lv2_3 = d_o_7_1_state)) or ((ap_const_logic_0 = d_o_7_1_vld_in) and (ap_const_lv2_2 = d_o_7_1_state)))) then d_o_7_1_state <= ap_const_lv2_2; elsif ((((ap_const_logic_1 = d_o_7_1_vld_in) and (ap_const_logic_0 = d_o_7_1_ack_out) and (ap_const_lv2_3 = d_o_7_1_state)) or ((ap_const_logic_0 = d_o_7_1_ack_out) and (ap_const_lv2_1 = d_o_7_1_state)))) then d_o_7_1_state <= ap_const_lv2_1; elsif ((((ap_const_logic_1 = d_o_7_1_vld_in) and (ap_const_lv2_2 = d_o_7_1_state)) or ((ap_const_logic_1 = d_o_7_1_ack_out) and (ap_const_lv2_1 = d_o_7_1_state)) or ((ap_const_lv2_3 = d_o_7_1_state) and not(((ap_const_logic_1 = d_o_7_1_vld_in) and (ap_const_logic_0 = d_o_7_1_ack_out))) and not(((ap_const_logic_0 = d_o_7_1_vld_in) and (ap_const_logic_1 = d_o_7_1_ack_out)))))) then d_o_7_1_state <= ap_const_lv2_3; else d_o_7_1_state <= ap_const_lv2_2; end if; end if; end if; end process; i1_reg_218_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond_reg_507))) then i1_reg_218 <= tmp_17_reg_502; elsif ((((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_1 = exitcond_reg_507)))) then i1_reg_218 <= ap_const_lv5_0; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then acc_0 <= tmp_1_fu_266_p2; acc_1 <= tmp_1_1_fu_297_p2; acc_2 <= tmp_1_2_fu_328_p2; acc_3 <= tmp_1_3_fu_359_p2; acc_4 <= tmp_1_4_fu_390_p2; acc_5 <= tmp_1_5_fu_421_p2; acc_6 <= tmp_1_6_fu_452_p2; acc_7 <= tmp_1_7_fu_483_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then ap_reg_pp0_iter1_exitcond_reg_507 <= exitcond_reg_507; exitcond_reg_507 <= exitcond_fu_246_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_i_0_0_load_A)) then d_i_0_0_payload_A <= d_i_0_TDATA; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_i_0_0_load_B)) then d_i_0_0_payload_B <= d_i_0_TDATA; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_i_1_0_load_A)) then d_i_1_0_payload_A <= d_i_1_TDATA; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_i_1_0_load_B)) then d_i_1_0_payload_B <= d_i_1_TDATA; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_i_2_0_load_A)) then d_i_2_0_payload_A <= d_i_2_TDATA; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_i_2_0_load_B)) then d_i_2_0_payload_B <= d_i_2_TDATA; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_i_3_0_load_A)) then d_i_3_0_payload_A <= d_i_3_TDATA; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_i_3_0_load_B)) then d_i_3_0_payload_B <= d_i_3_TDATA; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_i_4_0_load_A)) then d_i_4_0_payload_A <= d_i_4_TDATA; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_i_4_0_load_B)) then d_i_4_0_payload_B <= d_i_4_TDATA; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_i_5_0_load_A)) then d_i_5_0_payload_A <= d_i_5_TDATA; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_i_5_0_load_B)) then d_i_5_0_payload_B <= d_i_5_TDATA; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_i_6_0_load_A)) then d_i_6_0_payload_A <= d_i_6_TDATA; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_i_6_0_load_B)) then d_i_6_0_payload_B <= d_i_6_TDATA; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_i_7_0_load_A)) then d_i_7_0_payload_A <= d_i_7_TDATA; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_i_7_0_load_B)) then d_i_7_0_payload_B <= d_i_7_TDATA; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_o_0_1_load_A)) then d_o_0_1_payload_A <= tmp_8_fu_278_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_o_0_1_load_B)) then d_o_0_1_payload_B <= tmp_8_fu_278_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_o_1_1_load_A)) then d_o_1_1_payload_A <= tmp_2_1_fu_309_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_o_1_1_load_B)) then d_o_1_1_payload_B <= tmp_2_1_fu_309_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_o_2_1_load_A)) then d_o_2_1_payload_A <= tmp_2_2_fu_340_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_o_2_1_load_B)) then d_o_2_1_payload_B <= tmp_2_2_fu_340_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_o_3_1_load_A)) then d_o_3_1_payload_A <= tmp_2_3_fu_371_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_o_3_1_load_B)) then d_o_3_1_payload_B <= tmp_2_3_fu_371_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_o_4_1_load_A)) then d_o_4_1_payload_A <= tmp_2_4_fu_402_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_o_4_1_load_B)) then d_o_4_1_payload_B <= tmp_2_4_fu_402_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_o_5_1_load_A)) then d_o_5_1_payload_A <= tmp_2_5_fu_433_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_o_5_1_load_B)) then d_o_5_1_payload_B <= tmp_2_5_fu_433_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_o_6_1_load_A)) then d_o_6_1_payload_A <= tmp_2_6_fu_464_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_o_6_1_load_B)) then d_o_6_1_payload_B <= tmp_2_6_fu_464_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_o_7_1_load_A)) then d_o_7_1_payload_A <= tmp_2_7_fu_495_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_o_7_1_load_B)) then d_o_7_1_payload_B <= tmp_2_7_fu_495_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then tmp_17_reg_502 <= tmp_17_fu_242_p1; end if; end if; end process; ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, ap_block_pp0_stage0_flag00011011, ap_reset_idle_pp0) begin case ap_CS_fsm is when ap_ST_fsm_state1 => if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then ap_NS_fsm <= ap_ST_fsm_pp0_stage0; else ap_NS_fsm <= ap_ST_fsm_state1; end if; when ap_ST_fsm_pp0_stage0 => if ((ap_reset_idle_pp0 = ap_const_logic_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage0; elsif (((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_reset_idle_pp0))) then ap_NS_fsm <= ap_ST_fsm_state1; else ap_NS_fsm <= ap_ST_fsm_pp0_stage0; end if; when others => ap_NS_fsm <= "XX"; end case; end process; ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(1); ap_CS_fsm_state1 <= ap_CS_fsm(0); ap_block_pp0_stage0_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage0_flag00001001_assign_proc : process(d_i_0_0_vld_out, d_i_1_0_vld_out, d_i_2_0_vld_out, d_i_3_0_vld_out, d_i_4_0_vld_out, d_i_5_0_vld_out, d_i_6_0_vld_out, d_i_7_0_vld_out, d_o_0_1_ack_in, d_o_1_1_ack_in, d_o_2_1_ack_in, d_o_3_1_ack_in, d_o_4_1_ack_in, d_o_5_1_ack_in, d_o_6_1_ack_in, d_o_7_1_ack_in, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2) begin ap_block_pp0_stage0_flag00001001 <= ((((ap_const_logic_0 = d_i_0_0_vld_out) or (ap_const_logic_0 = d_i_1_0_vld_out) or (ap_const_logic_0 = d_i_2_0_vld_out) or (ap_const_logic_0 = d_i_3_0_vld_out) or (ap_const_logic_0 = d_i_4_0_vld_out) or (ap_const_logic_0 = d_i_5_0_vld_out) or (ap_const_logic_0 = d_i_6_0_vld_out) or (ap_const_logic_0 = d_i_7_0_vld_out)) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or (((ap_const_logic_0 = d_o_0_1_ack_in) or (ap_const_logic_0 = d_o_1_1_ack_in) or (ap_const_logic_0 = d_o_2_1_ack_in) or (ap_const_logic_0 = d_o_3_1_ack_in) or (ap_const_logic_0 = d_o_4_1_ack_in) or (ap_const_logic_0 = d_o_5_1_ack_in) or (ap_const_logic_0 = d_o_6_1_ack_in) or (ap_const_logic_0 = d_o_7_1_ack_in)) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))); end process; ap_block_pp0_stage0_flag00011001_assign_proc : process(d_i_0_0_vld_out, d_i_1_0_vld_out, d_i_2_0_vld_out, d_i_3_0_vld_out, d_i_4_0_vld_out, d_i_5_0_vld_out, d_i_6_0_vld_out, d_i_7_0_vld_out, d_o_0_1_ack_in, d_o_1_1_ack_in, d_o_2_1_ack_in, d_o_3_1_ack_in, d_o_4_1_ack_in, d_o_5_1_ack_in, d_o_6_1_ack_in, d_o_7_1_ack_in, ap_block_state4_io, ap_enable_reg_pp0_iter1, ap_block_state3_io, ap_enable_reg_pp0_iter2) begin ap_block_pp0_stage0_flag00011001 <= ((((ap_const_logic_0 = d_i_0_0_vld_out) or (ap_const_logic_0 = d_i_1_0_vld_out) or (ap_const_logic_0 = d_i_2_0_vld_out) or (ap_const_logic_0 = d_i_3_0_vld_out) or (ap_const_logic_0 = d_i_4_0_vld_out) or (ap_const_logic_0 = d_i_5_0_vld_out) or (ap_const_logic_0 = d_i_6_0_vld_out) or (ap_const_logic_0 = d_i_7_0_vld_out) or (ap_const_boolean_1 = ap_block_state4_io)) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or (((ap_const_logic_0 = d_o_0_1_ack_in) or (ap_const_logic_0 = d_o_1_1_ack_in) or (ap_const_logic_0 = d_o_2_1_ack_in) or (ap_const_logic_0 = d_o_3_1_ack_in) or (ap_const_logic_0 = d_o_4_1_ack_in) or (ap_const_logic_0 = d_o_5_1_ack_in) or (ap_const_logic_0 = d_o_6_1_ack_in) or (ap_const_logic_0 = d_o_7_1_ack_in) or (ap_const_boolean_1 = ap_block_state3_io)) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))); end process; ap_block_pp0_stage0_flag00011011_assign_proc : process(d_i_0_0_vld_out, d_i_1_0_vld_out, d_i_2_0_vld_out, d_i_3_0_vld_out, d_i_4_0_vld_out, d_i_5_0_vld_out, d_i_6_0_vld_out, d_i_7_0_vld_out, d_o_0_1_ack_in, d_o_1_1_ack_in, d_o_2_1_ack_in, d_o_3_1_ack_in, d_o_4_1_ack_in, d_o_5_1_ack_in, d_o_6_1_ack_in, d_o_7_1_ack_in, ap_block_state4_io, ap_enable_reg_pp0_iter1, ap_block_state3_io, ap_enable_reg_pp0_iter2) begin ap_block_pp0_stage0_flag00011011 <= ((((ap_const_logic_0 = d_i_0_0_vld_out) or (ap_const_logic_0 = d_i_1_0_vld_out) or (ap_const_logic_0 = d_i_2_0_vld_out) or (ap_const_logic_0 = d_i_3_0_vld_out) or (ap_const_logic_0 = d_i_4_0_vld_out) or (ap_const_logic_0 = d_i_5_0_vld_out) or (ap_const_logic_0 = d_i_6_0_vld_out) or (ap_const_logic_0 = d_i_7_0_vld_out) or (ap_const_boolean_1 = ap_block_state4_io)) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or (((ap_const_logic_0 = d_o_0_1_ack_in) or (ap_const_logic_0 = d_o_1_1_ack_in) or (ap_const_logic_0 = d_o_2_1_ack_in) or (ap_const_logic_0 = d_o_3_1_ack_in) or (ap_const_logic_0 = d_o_4_1_ack_in) or (ap_const_logic_0 = d_o_5_1_ack_in) or (ap_const_logic_0 = d_o_6_1_ack_in) or (ap_const_logic_0 = d_o_7_1_ack_in) or (ap_const_boolean_1 = ap_block_state3_io)) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))); end process; ap_block_state2_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state3_io_assign_proc : process(d_o_0_1_ack_in, d_o_1_1_ack_in, d_o_2_1_ack_in, d_o_3_1_ack_in, d_o_4_1_ack_in, d_o_5_1_ack_in, d_o_6_1_ack_in, d_o_7_1_ack_in) begin ap_block_state3_io <= ((ap_const_logic_0 = d_o_0_1_ack_in) or (ap_const_logic_0 = d_o_1_1_ack_in) or (ap_const_logic_0 = d_o_2_1_ack_in) or (ap_const_logic_0 = d_o_3_1_ack_in) or (ap_const_logic_0 = d_o_4_1_ack_in) or (ap_const_logic_0 = d_o_5_1_ack_in) or (ap_const_logic_0 = d_o_6_1_ack_in) or (ap_const_logic_0 = d_o_7_1_ack_in)); end process; ap_block_state3_pp0_stage0_iter2_assign_proc : process(d_o_0_1_ack_in, d_o_1_1_ack_in, d_o_2_1_ack_in, d_o_3_1_ack_in, d_o_4_1_ack_in, d_o_5_1_ack_in, d_o_6_1_ack_in, d_o_7_1_ack_in) begin ap_block_state3_pp0_stage0_iter2 <= ((ap_const_logic_0 = d_o_0_1_ack_in) or (ap_const_logic_0 = d_o_1_1_ack_in) or (ap_const_logic_0 = d_o_2_1_ack_in) or (ap_const_logic_0 = d_o_3_1_ack_in) or (ap_const_logic_0 = d_o_4_1_ack_in) or (ap_const_logic_0 = d_o_5_1_ack_in) or (ap_const_logic_0 = d_o_6_1_ack_in) or (ap_const_logic_0 = d_o_7_1_ack_in)); end process; ap_block_state4_io_assign_proc : process(d_o_0_1_ack_in, d_o_1_1_ack_in, d_o_2_1_ack_in, d_o_3_1_ack_in, d_o_4_1_ack_in, d_o_5_1_ack_in, d_o_6_1_ack_in, d_o_7_1_ack_in) begin ap_block_state4_io <= ((ap_const_logic_0 = d_o_0_1_ack_in) or (ap_const_logic_0 = d_o_1_1_ack_in) or (ap_const_logic_0 = d_o_2_1_ack_in) or (ap_const_logic_0 = d_o_3_1_ack_in) or (ap_const_logic_0 = d_o_4_1_ack_in) or (ap_const_logic_0 = d_o_5_1_ack_in) or (ap_const_logic_0 = d_o_6_1_ack_in) or (ap_const_logic_0 = d_o_7_1_ack_in)); end process; ap_block_state4_pp0_stage0_iter1_assign_proc : process(d_i_0_0_vld_out, d_i_1_0_vld_out, d_i_2_0_vld_out, d_i_3_0_vld_out, d_i_4_0_vld_out, d_i_5_0_vld_out, d_i_6_0_vld_out, d_i_7_0_vld_out) begin ap_block_state4_pp0_stage0_iter1 <= ((ap_const_logic_0 = d_i_0_0_vld_out) or (ap_const_logic_0 = d_i_1_0_vld_out) or (ap_const_logic_0 = d_i_2_0_vld_out) or (ap_const_logic_0 = d_i_3_0_vld_out) or (ap_const_logic_0 = d_i_4_0_vld_out) or (ap_const_logic_0 = d_i_5_0_vld_out) or (ap_const_logic_0 = d_i_6_0_vld_out) or (ap_const_logic_0 = d_i_7_0_vld_out)); end process; ap_condition_1051_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000) begin ap_condition_1051 <= ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)); end process; ap_done_assign_proc : process(ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00011001, ap_reg_pp0_iter1_exitcond_reg_507) begin if (((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_1 = ap_reg_pp0_iter1_exitcond_reg_507))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1); ap_enable_reg_pp0_iter0 <= ap_start; ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1) begin if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2) begin if (((ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter1) and (ap_const_logic_0 = ap_enable_reg_pp0_iter2))) then ap_idle_pp0 <= ap_const_logic_1; else ap_idle_pp0 <= ap_const_logic_0; end if; end process; ap_idle_pp0_0to1_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1) begin if (((ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter1))) then ap_idle_pp0_0to1 <= ap_const_logic_1; else ap_idle_pp0_0to1 <= ap_const_logic_0; end if; end process; ap_ready_assign_proc : process(exitcond_fu_246_p2, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_flag00011001) begin if (((exitcond_fu_246_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; ap_reset_idle_pp0_assign_proc : process(ap_start, ap_idle_pp0_0to1) begin if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_idle_pp0_0to1))) then ap_reset_idle_pp0 <= ap_const_logic_1; else ap_reset_idle_pp0 <= ap_const_logic_0; end if; end process; ap_rst_n_inv_assign_proc : process(ap_rst_n) begin ap_rst_n_inv <= not(ap_rst_n); end process; d_i_0_0_ack_in <= d_i_0_0_state(1); d_i_0_0_ack_out_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then d_i_0_0_ack_out <= ap_const_logic_1; else d_i_0_0_ack_out <= ap_const_logic_0; end if; end process; d_i_0_0_data_out_assign_proc : process(d_i_0_0_payload_A, d_i_0_0_payload_B, d_i_0_0_sel) begin if ((ap_const_logic_1 = d_i_0_0_sel)) then d_i_0_0_data_out <= d_i_0_0_payload_B; else d_i_0_0_data_out <= d_i_0_0_payload_A; end if; end process; d_i_0_0_load_A <= (d_i_0_0_state_cmp_full and not(d_i_0_0_sel_wr)); d_i_0_0_load_B <= (d_i_0_0_sel_wr and d_i_0_0_state_cmp_full); d_i_0_0_sel <= d_i_0_0_sel_rd; d_i_0_0_state_cmp_full <= '0' when (d_i_0_0_state = ap_const_lv2_1) else '1'; d_i_0_0_vld_in <= d_i_0_TVALID; d_i_0_0_vld_out <= d_i_0_0_state(0); d_i_0_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, d_i_0_0_state, ap_block_pp0_stage0_flag00000000) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then d_i_0_TDATA_blk_n <= d_i_0_0_state(0); else d_i_0_TDATA_blk_n <= ap_const_logic_1; end if; end process; d_i_0_TREADY <= d_i_0_0_state(1); d_i_1_0_ack_in <= d_i_1_0_state(1); d_i_1_0_ack_out_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then d_i_1_0_ack_out <= ap_const_logic_1; else d_i_1_0_ack_out <= ap_const_logic_0; end if; end process; d_i_1_0_data_out_assign_proc : process(d_i_1_0_payload_A, d_i_1_0_payload_B, d_i_1_0_sel) begin if ((ap_const_logic_1 = d_i_1_0_sel)) then d_i_1_0_data_out <= d_i_1_0_payload_B; else d_i_1_0_data_out <= d_i_1_0_payload_A; end if; end process; d_i_1_0_load_A <= (d_i_1_0_state_cmp_full and not(d_i_1_0_sel_wr)); d_i_1_0_load_B <= (d_i_1_0_sel_wr and d_i_1_0_state_cmp_full); d_i_1_0_sel <= d_i_1_0_sel_rd; d_i_1_0_state_cmp_full <= '0' when (d_i_1_0_state = ap_const_lv2_1) else '1'; d_i_1_0_vld_in <= d_i_1_TVALID; d_i_1_0_vld_out <= d_i_1_0_state(0); d_i_1_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, d_i_1_0_state, ap_block_pp0_stage0_flag00000000) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then d_i_1_TDATA_blk_n <= d_i_1_0_state(0); else d_i_1_TDATA_blk_n <= ap_const_logic_1; end if; end process; d_i_1_TREADY <= d_i_1_0_state(1); d_i_2_0_ack_in <= d_i_2_0_state(1); d_i_2_0_ack_out_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then d_i_2_0_ack_out <= ap_const_logic_1; else d_i_2_0_ack_out <= ap_const_logic_0; end if; end process; d_i_2_0_data_out_assign_proc : process(d_i_2_0_payload_A, d_i_2_0_payload_B, d_i_2_0_sel) begin if ((ap_const_logic_1 = d_i_2_0_sel)) then d_i_2_0_data_out <= d_i_2_0_payload_B; else d_i_2_0_data_out <= d_i_2_0_payload_A; end if; end process; d_i_2_0_load_A <= (d_i_2_0_state_cmp_full and not(d_i_2_0_sel_wr)); d_i_2_0_load_B <= (d_i_2_0_sel_wr and d_i_2_0_state_cmp_full); d_i_2_0_sel <= d_i_2_0_sel_rd; d_i_2_0_state_cmp_full <= '0' when (d_i_2_0_state = ap_const_lv2_1) else '1'; d_i_2_0_vld_in <= d_i_2_TVALID; d_i_2_0_vld_out <= d_i_2_0_state(0); d_i_2_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, d_i_2_0_state, ap_block_pp0_stage0_flag00000000) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then d_i_2_TDATA_blk_n <= d_i_2_0_state(0); else d_i_2_TDATA_blk_n <= ap_const_logic_1; end if; end process; d_i_2_TREADY <= d_i_2_0_state(1); d_i_3_0_ack_in <= d_i_3_0_state(1); d_i_3_0_ack_out_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then d_i_3_0_ack_out <= ap_const_logic_1; else d_i_3_0_ack_out <= ap_const_logic_0; end if; end process; d_i_3_0_data_out_assign_proc : process(d_i_3_0_payload_A, d_i_3_0_payload_B, d_i_3_0_sel) begin if ((ap_const_logic_1 = d_i_3_0_sel)) then d_i_3_0_data_out <= d_i_3_0_payload_B; else d_i_3_0_data_out <= d_i_3_0_payload_A; end if; end process; d_i_3_0_load_A <= (d_i_3_0_state_cmp_full and not(d_i_3_0_sel_wr)); d_i_3_0_load_B <= (d_i_3_0_sel_wr and d_i_3_0_state_cmp_full); d_i_3_0_sel <= d_i_3_0_sel_rd; d_i_3_0_state_cmp_full <= '0' when (d_i_3_0_state = ap_const_lv2_1) else '1'; d_i_3_0_vld_in <= d_i_3_TVALID; d_i_3_0_vld_out <= d_i_3_0_state(0); d_i_3_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, d_i_3_0_state, ap_block_pp0_stage0_flag00000000) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then d_i_3_TDATA_blk_n <= d_i_3_0_state(0); else d_i_3_TDATA_blk_n <= ap_const_logic_1; end if; end process; d_i_3_TREADY <= d_i_3_0_state(1); d_i_4_0_ack_in <= d_i_4_0_state(1); d_i_4_0_ack_out_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then d_i_4_0_ack_out <= ap_const_logic_1; else d_i_4_0_ack_out <= ap_const_logic_0; end if; end process; d_i_4_0_data_out_assign_proc : process(d_i_4_0_payload_A, d_i_4_0_payload_B, d_i_4_0_sel) begin if ((ap_const_logic_1 = d_i_4_0_sel)) then d_i_4_0_data_out <= d_i_4_0_payload_B; else d_i_4_0_data_out <= d_i_4_0_payload_A; end if; end process; d_i_4_0_load_A <= (d_i_4_0_state_cmp_full and not(d_i_4_0_sel_wr)); d_i_4_0_load_B <= (d_i_4_0_sel_wr and d_i_4_0_state_cmp_full); d_i_4_0_sel <= d_i_4_0_sel_rd; d_i_4_0_state_cmp_full <= '0' when (d_i_4_0_state = ap_const_lv2_1) else '1'; d_i_4_0_vld_in <= d_i_4_TVALID; d_i_4_0_vld_out <= d_i_4_0_state(0); d_i_4_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, d_i_4_0_state, ap_block_pp0_stage0_flag00000000) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then d_i_4_TDATA_blk_n <= d_i_4_0_state(0); else d_i_4_TDATA_blk_n <= ap_const_logic_1; end if; end process; d_i_4_TREADY <= d_i_4_0_state(1); d_i_5_0_ack_in <= d_i_5_0_state(1); d_i_5_0_ack_out_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then d_i_5_0_ack_out <= ap_const_logic_1; else d_i_5_0_ack_out <= ap_const_logic_0; end if; end process; d_i_5_0_data_out_assign_proc : process(d_i_5_0_payload_A, d_i_5_0_payload_B, d_i_5_0_sel) begin if ((ap_const_logic_1 = d_i_5_0_sel)) then d_i_5_0_data_out <= d_i_5_0_payload_B; else d_i_5_0_data_out <= d_i_5_0_payload_A; end if; end process; d_i_5_0_load_A <= (d_i_5_0_state_cmp_full and not(d_i_5_0_sel_wr)); d_i_5_0_load_B <= (d_i_5_0_sel_wr and d_i_5_0_state_cmp_full); d_i_5_0_sel <= d_i_5_0_sel_rd; d_i_5_0_state_cmp_full <= '0' when (d_i_5_0_state = ap_const_lv2_1) else '1'; d_i_5_0_vld_in <= d_i_5_TVALID; d_i_5_0_vld_out <= d_i_5_0_state(0); d_i_5_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, d_i_5_0_state, ap_block_pp0_stage0_flag00000000) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then d_i_5_TDATA_blk_n <= d_i_5_0_state(0); else d_i_5_TDATA_blk_n <= ap_const_logic_1; end if; end process; d_i_5_TREADY <= d_i_5_0_state(1); d_i_6_0_ack_in <= d_i_6_0_state(1); d_i_6_0_ack_out_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then d_i_6_0_ack_out <= ap_const_logic_1; else d_i_6_0_ack_out <= ap_const_logic_0; end if; end process; d_i_6_0_data_out_assign_proc : process(d_i_6_0_payload_A, d_i_6_0_payload_B, d_i_6_0_sel) begin if ((ap_const_logic_1 = d_i_6_0_sel)) then d_i_6_0_data_out <= d_i_6_0_payload_B; else d_i_6_0_data_out <= d_i_6_0_payload_A; end if; end process; d_i_6_0_load_A <= (d_i_6_0_state_cmp_full and not(d_i_6_0_sel_wr)); d_i_6_0_load_B <= (d_i_6_0_sel_wr and d_i_6_0_state_cmp_full); d_i_6_0_sel <= d_i_6_0_sel_rd; d_i_6_0_state_cmp_full <= '0' when (d_i_6_0_state = ap_const_lv2_1) else '1'; d_i_6_0_vld_in <= d_i_6_TVALID; d_i_6_0_vld_out <= d_i_6_0_state(0); d_i_6_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, d_i_6_0_state, ap_block_pp0_stage0_flag00000000) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then d_i_6_TDATA_blk_n <= d_i_6_0_state(0); else d_i_6_TDATA_blk_n <= ap_const_logic_1; end if; end process; d_i_6_TREADY <= d_i_6_0_state(1); d_i_7_0_ack_in <= d_i_7_0_state(1); d_i_7_0_ack_out_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then d_i_7_0_ack_out <= ap_const_logic_1; else d_i_7_0_ack_out <= ap_const_logic_0; end if; end process; d_i_7_0_data_out_assign_proc : process(d_i_7_0_payload_A, d_i_7_0_payload_B, d_i_7_0_sel) begin if ((ap_const_logic_1 = d_i_7_0_sel)) then d_i_7_0_data_out <= d_i_7_0_payload_B; else d_i_7_0_data_out <= d_i_7_0_payload_A; end if; end process; d_i_7_0_load_A <= (d_i_7_0_state_cmp_full and not(d_i_7_0_sel_wr)); d_i_7_0_load_B <= (d_i_7_0_sel_wr and d_i_7_0_state_cmp_full); d_i_7_0_sel <= d_i_7_0_sel_rd; d_i_7_0_state_cmp_full <= '0' when (d_i_7_0_state = ap_const_lv2_1) else '1'; d_i_7_0_vld_in <= d_i_7_TVALID; d_i_7_0_vld_out <= d_i_7_0_state(0); d_i_7_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, d_i_7_0_state, ap_block_pp0_stage0_flag00000000) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then d_i_7_TDATA_blk_n <= d_i_7_0_state(0); else d_i_7_TDATA_blk_n <= ap_const_logic_1; end if; end process; d_i_7_TREADY <= d_i_7_0_state(1); d_o_0_1_ack_in <= d_o_0_1_state(1); d_o_0_1_ack_out <= d_o_0_TREADY; d_o_0_1_data_out_assign_proc : process(d_o_0_1_payload_A, d_o_0_1_payload_B, d_o_0_1_sel) begin if ((ap_const_logic_1 = d_o_0_1_sel)) then d_o_0_1_data_out <= d_o_0_1_payload_B; else d_o_0_1_data_out <= d_o_0_1_payload_A; end if; end process; d_o_0_1_load_A <= (d_o_0_1_state_cmp_full and not(d_o_0_1_sel_wr)); d_o_0_1_load_B <= (d_o_0_1_sel_wr and d_o_0_1_state_cmp_full); d_o_0_1_sel <= d_o_0_1_sel_rd; d_o_0_1_state_cmp_full <= '0' when (d_o_0_1_state = ap_const_lv2_1) else '1'; d_o_0_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then d_o_0_1_vld_in <= ap_const_logic_1; else d_o_0_1_vld_in <= ap_const_logic_0; end if; end process; d_o_0_1_vld_out <= d_o_0_1_state(0); d_o_0_TDATA <= d_o_0_1_data_out; d_o_0_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, d_o_0_1_state, ap_block_pp0_stage0_flag00000000) begin if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)))) then d_o_0_TDATA_blk_n <= d_o_0_1_state(1); else d_o_0_TDATA_blk_n <= ap_const_logic_1; end if; end process; d_o_0_TVALID <= d_o_0_1_state(0); d_o_1_1_ack_in <= d_o_1_1_state(1); d_o_1_1_ack_out <= d_o_1_TREADY; d_o_1_1_data_out_assign_proc : process(d_o_1_1_payload_A, d_o_1_1_payload_B, d_o_1_1_sel) begin if ((ap_const_logic_1 = d_o_1_1_sel)) then d_o_1_1_data_out <= d_o_1_1_payload_B; else d_o_1_1_data_out <= d_o_1_1_payload_A; end if; end process; d_o_1_1_load_A <= (d_o_1_1_state_cmp_full and not(d_o_1_1_sel_wr)); d_o_1_1_load_B <= (d_o_1_1_sel_wr and d_o_1_1_state_cmp_full); d_o_1_1_sel <= d_o_1_1_sel_rd; d_o_1_1_state_cmp_full <= '0' when (d_o_1_1_state = ap_const_lv2_1) else '1'; d_o_1_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then d_o_1_1_vld_in <= ap_const_logic_1; else d_o_1_1_vld_in <= ap_const_logic_0; end if; end process; d_o_1_1_vld_out <= d_o_1_1_state(0); d_o_1_TDATA <= d_o_1_1_data_out; d_o_1_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, d_o_1_1_state, ap_block_pp0_stage0_flag00000000) begin if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)))) then d_o_1_TDATA_blk_n <= d_o_1_1_state(1); else d_o_1_TDATA_blk_n <= ap_const_logic_1; end if; end process; d_o_1_TVALID <= d_o_1_1_state(0); d_o_2_1_ack_in <= d_o_2_1_state(1); d_o_2_1_ack_out <= d_o_2_TREADY; d_o_2_1_data_out_assign_proc : process(d_o_2_1_payload_A, d_o_2_1_payload_B, d_o_2_1_sel) begin if ((ap_const_logic_1 = d_o_2_1_sel)) then d_o_2_1_data_out <= d_o_2_1_payload_B; else d_o_2_1_data_out <= d_o_2_1_payload_A; end if; end process; d_o_2_1_load_A <= (d_o_2_1_state_cmp_full and not(d_o_2_1_sel_wr)); d_o_2_1_load_B <= (d_o_2_1_sel_wr and d_o_2_1_state_cmp_full); d_o_2_1_sel <= d_o_2_1_sel_rd; d_o_2_1_state_cmp_full <= '0' when (d_o_2_1_state = ap_const_lv2_1) else '1'; d_o_2_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then d_o_2_1_vld_in <= ap_const_logic_1; else d_o_2_1_vld_in <= ap_const_logic_0; end if; end process; d_o_2_1_vld_out <= d_o_2_1_state(0); d_o_2_TDATA <= d_o_2_1_data_out; d_o_2_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, d_o_2_1_state, ap_block_pp0_stage0_flag00000000) begin if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)))) then d_o_2_TDATA_blk_n <= d_o_2_1_state(1); else d_o_2_TDATA_blk_n <= ap_const_logic_1; end if; end process; d_o_2_TVALID <= d_o_2_1_state(0); d_o_3_1_ack_in <= d_o_3_1_state(1); d_o_3_1_ack_out <= d_o_3_TREADY; d_o_3_1_data_out_assign_proc : process(d_o_3_1_payload_A, d_o_3_1_payload_B, d_o_3_1_sel) begin if ((ap_const_logic_1 = d_o_3_1_sel)) then d_o_3_1_data_out <= d_o_3_1_payload_B; else d_o_3_1_data_out <= d_o_3_1_payload_A; end if; end process; d_o_3_1_load_A <= (d_o_3_1_state_cmp_full and not(d_o_3_1_sel_wr)); d_o_3_1_load_B <= (d_o_3_1_sel_wr and d_o_3_1_state_cmp_full); d_o_3_1_sel <= d_o_3_1_sel_rd; d_o_3_1_state_cmp_full <= '0' when (d_o_3_1_state = ap_const_lv2_1) else '1'; d_o_3_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then d_o_3_1_vld_in <= ap_const_logic_1; else d_o_3_1_vld_in <= ap_const_logic_0; end if; end process; d_o_3_1_vld_out <= d_o_3_1_state(0); d_o_3_TDATA <= d_o_3_1_data_out; d_o_3_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, d_o_3_1_state, ap_block_pp0_stage0_flag00000000) begin if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)))) then d_o_3_TDATA_blk_n <= d_o_3_1_state(1); else d_o_3_TDATA_blk_n <= ap_const_logic_1; end if; end process; d_o_3_TVALID <= d_o_3_1_state(0); d_o_4_1_ack_in <= d_o_4_1_state(1); d_o_4_1_ack_out <= d_o_4_TREADY; d_o_4_1_data_out_assign_proc : process(d_o_4_1_payload_A, d_o_4_1_payload_B, d_o_4_1_sel) begin if ((ap_const_logic_1 = d_o_4_1_sel)) then d_o_4_1_data_out <= d_o_4_1_payload_B; else d_o_4_1_data_out <= d_o_4_1_payload_A; end if; end process; d_o_4_1_load_A <= (d_o_4_1_state_cmp_full and not(d_o_4_1_sel_wr)); d_o_4_1_load_B <= (d_o_4_1_sel_wr and d_o_4_1_state_cmp_full); d_o_4_1_sel <= d_o_4_1_sel_rd; d_o_4_1_state_cmp_full <= '0' when (d_o_4_1_state = ap_const_lv2_1) else '1'; d_o_4_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then d_o_4_1_vld_in <= ap_const_logic_1; else d_o_4_1_vld_in <= ap_const_logic_0; end if; end process; d_o_4_1_vld_out <= d_o_4_1_state(0); d_o_4_TDATA <= d_o_4_1_data_out; d_o_4_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, d_o_4_1_state, ap_block_pp0_stage0_flag00000000) begin if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)))) then d_o_4_TDATA_blk_n <= d_o_4_1_state(1); else d_o_4_TDATA_blk_n <= ap_const_logic_1; end if; end process; d_o_4_TVALID <= d_o_4_1_state(0); d_o_5_1_ack_in <= d_o_5_1_state(1); d_o_5_1_ack_out <= d_o_5_TREADY; d_o_5_1_data_out_assign_proc : process(d_o_5_1_payload_A, d_o_5_1_payload_B, d_o_5_1_sel) begin if ((ap_const_logic_1 = d_o_5_1_sel)) then d_o_5_1_data_out <= d_o_5_1_payload_B; else d_o_5_1_data_out <= d_o_5_1_payload_A; end if; end process; d_o_5_1_load_A <= (d_o_5_1_state_cmp_full and not(d_o_5_1_sel_wr)); d_o_5_1_load_B <= (d_o_5_1_sel_wr and d_o_5_1_state_cmp_full); d_o_5_1_sel <= d_o_5_1_sel_rd; d_o_5_1_state_cmp_full <= '0' when (d_o_5_1_state = ap_const_lv2_1) else '1'; d_o_5_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then d_o_5_1_vld_in <= ap_const_logic_1; else d_o_5_1_vld_in <= ap_const_logic_0; end if; end process; d_o_5_1_vld_out <= d_o_5_1_state(0); d_o_5_TDATA <= d_o_5_1_data_out; d_o_5_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, d_o_5_1_state, ap_block_pp0_stage0_flag00000000) begin if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)))) then d_o_5_TDATA_blk_n <= d_o_5_1_state(1); else d_o_5_TDATA_blk_n <= ap_const_logic_1; end if; end process; d_o_5_TVALID <= d_o_5_1_state(0); d_o_6_1_ack_in <= d_o_6_1_state(1); d_o_6_1_ack_out <= d_o_6_TREADY; d_o_6_1_data_out_assign_proc : process(d_o_6_1_payload_A, d_o_6_1_payload_B, d_o_6_1_sel) begin if ((ap_const_logic_1 = d_o_6_1_sel)) then d_o_6_1_data_out <= d_o_6_1_payload_B; else d_o_6_1_data_out <= d_o_6_1_payload_A; end if; end process; d_o_6_1_load_A <= (d_o_6_1_state_cmp_full and not(d_o_6_1_sel_wr)); d_o_6_1_load_B <= (d_o_6_1_sel_wr and d_o_6_1_state_cmp_full); d_o_6_1_sel <= d_o_6_1_sel_rd; d_o_6_1_state_cmp_full <= '0' when (d_o_6_1_state = ap_const_lv2_1) else '1'; d_o_6_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then d_o_6_1_vld_in <= ap_const_logic_1; else d_o_6_1_vld_in <= ap_const_logic_0; end if; end process; d_o_6_1_vld_out <= d_o_6_1_state(0); d_o_6_TDATA <= d_o_6_1_data_out; d_o_6_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, d_o_6_1_state, ap_block_pp0_stage0_flag00000000) begin if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)))) then d_o_6_TDATA_blk_n <= d_o_6_1_state(1); else d_o_6_TDATA_blk_n <= ap_const_logic_1; end if; end process; d_o_6_TVALID <= d_o_6_1_state(0); d_o_7_1_ack_in <= d_o_7_1_state(1); d_o_7_1_ack_out <= d_o_7_TREADY; d_o_7_1_data_out_assign_proc : process(d_o_7_1_payload_A, d_o_7_1_payload_B, d_o_7_1_sel) begin if ((ap_const_logic_1 = d_o_7_1_sel)) then d_o_7_1_data_out <= d_o_7_1_payload_B; else d_o_7_1_data_out <= d_o_7_1_payload_A; end if; end process; d_o_7_1_load_A <= (d_o_7_1_state_cmp_full and not(d_o_7_1_sel_wr)); d_o_7_1_load_B <= (d_o_7_1_sel_wr and d_o_7_1_state_cmp_full); d_o_7_1_sel <= d_o_7_1_sel_rd; d_o_7_1_state_cmp_full <= '0' when (d_o_7_1_state = ap_const_lv2_1) else '1'; d_o_7_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then d_o_7_1_vld_in <= ap_const_logic_1; else d_o_7_1_vld_in <= ap_const_logic_0; end if; end process; d_o_7_1_vld_out <= d_o_7_1_state(0); d_o_7_TDATA <= d_o_7_1_data_out; d_o_7_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, d_o_7_1_state, ap_block_pp0_stage0_flag00000000) begin if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)))) then d_o_7_TDATA_blk_n <= d_o_7_1_state(1); else d_o_7_TDATA_blk_n <= ap_const_logic_1; end if; end process; d_o_7_TVALID <= d_o_7_1_state(0); exitcond_fu_246_p2 <= "1" when (i_1_7_fu_236_p2 = ap_const_lv6_20) else "0"; i1_cast_fu_232_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i1_phi_fu_222_p6),6)); i1_phi_fu_222_p6_assign_proc : process(i1_reg_218, tmp_17_reg_502, exitcond_reg_507, ap_condition_1051) begin if ((ap_condition_1051 = ap_const_boolean_1)) then if ((ap_const_lv1_1 = exitcond_reg_507)) then i1_phi_fu_222_p6 <= ap_const_lv5_0; elsif ((ap_const_lv1_0 = exitcond_reg_507)) then i1_phi_fu_222_p6 <= tmp_17_reg_502; else i1_phi_fu_222_p6 <= i1_reg_218; end if; else i1_phi_fu_222_p6 <= i1_reg_218; end if; end process; i_1_7_fu_236_p2 <= std_logic_vector(unsigned(ap_const_lv6_8) + unsigned(i1_cast_fu_232_p1)); tmp1_fu_258_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_0_0_data_out),32)); tmp_10_fu_293_p1 <= acc_1(16 - 1 downto 0); tmp_11_fu_324_p1 <= acc_2(16 - 1 downto 0); tmp_12_fu_355_p1 <= acc_3(16 - 1 downto 0); tmp_13_fu_386_p1 <= acc_4(16 - 1 downto 0); tmp_14_fu_417_p1 <= acc_5(16 - 1 downto 0); tmp_15_fu_448_p1 <= acc_6(16 - 1 downto 0); tmp_16_fu_479_p1 <= acc_7(16 - 1 downto 0); tmp_17_fu_242_p1 <= i_1_7_fu_236_p2(5 - 1 downto 0); tmp_1_1_fu_297_p2 <= std_logic_vector(signed(tmp_s_fu_289_p1) + signed(acc_1)); tmp_1_2_fu_328_p2 <= std_logic_vector(signed(tmp_9_fu_320_p1) + signed(acc_2)); tmp_1_3_fu_359_p2 <= std_logic_vector(signed(tmp_3_fu_351_p1) + signed(acc_3)); tmp_1_4_fu_390_p2 <= std_logic_vector(signed(tmp_4_fu_382_p1) + signed(acc_4)); tmp_1_5_fu_421_p2 <= std_logic_vector(signed(tmp_5_fu_413_p1) + signed(acc_5)); tmp_1_6_fu_452_p2 <= std_logic_vector(signed(tmp_6_fu_444_p1) + signed(acc_6)); tmp_1_7_fu_483_p2 <= std_logic_vector(signed(tmp_7_fu_475_p1) + signed(acc_7)); tmp_1_fu_266_p2 <= std_logic_vector(signed(tmp1_fu_258_p1) + signed(acc_0)); tmp_2_1_fu_309_p2 <= std_logic_vector(unsigned(tmp_10_fu_293_p1) + unsigned(d_i_1_0_data_out)); tmp_2_2_fu_340_p2 <= std_logic_vector(unsigned(tmp_11_fu_324_p1) + unsigned(d_i_2_0_data_out)); tmp_2_3_fu_371_p2 <= std_logic_vector(unsigned(tmp_12_fu_355_p1) + unsigned(d_i_3_0_data_out)); tmp_2_4_fu_402_p2 <= std_logic_vector(unsigned(tmp_13_fu_386_p1) + unsigned(d_i_4_0_data_out)); tmp_2_5_fu_433_p2 <= std_logic_vector(unsigned(tmp_14_fu_417_p1) + unsigned(d_i_5_0_data_out)); tmp_2_6_fu_464_p2 <= std_logic_vector(unsigned(tmp_15_fu_448_p1) + unsigned(d_i_6_0_data_out)); tmp_2_7_fu_495_p2 <= std_logic_vector(unsigned(tmp_16_fu_479_p1) + unsigned(d_i_7_0_data_out)); tmp_2_fu_262_p1 <= acc_0(16 - 1 downto 0); tmp_3_fu_351_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_3_0_data_out),32)); tmp_4_fu_382_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_4_0_data_out),32)); tmp_5_fu_413_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_5_0_data_out),32)); tmp_6_fu_444_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_6_0_data_out),32)); tmp_7_fu_475_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_7_0_data_out),32)); tmp_8_fu_278_p2 <= std_logic_vector(unsigned(tmp_2_fu_262_p1) + unsigned(d_i_0_0_data_out)); tmp_9_fu_320_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_2_0_data_out),32)); tmp_s_fu_289_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_1_0_data_out),32)); end behav;	mit
VerkhovtsovPavel/BSUIR_Labs	Labs/POCP/POCP-4/src/REGn.vhd	1	674	library ieee; use ieee.std_logic_1164.all; entity REGn is generic (n : integer := 4); port( Din : in std_logic_vector(n-1 downto 0); EN : in std_logic; Dout : out std_logic_vector(n-1 downto 0) ); end REGn; architecture behavior of REGn is signal reg : std_logic_vector(n-1 downto 0); begin main : process(Din, EN) begin if EN='1' then reg <= Din; end if; end process; Dout <= reg; end behavior; architecture structual of REGn is component DEL port(D, E : in std_logic; Q: out std_logic); end component DEL; begin G_1 : for I in 0 to N-1 generate DEL_I : DEL port map (Din(I), EN, Dout(I)); end generate; end architecture structual;	mit
MarkBlanco/FPGA_Sandbox	RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ipshared/cb07/hdl/axi_gpio_v2_0_vh_rfs.vhd	3	76385	------------------------------------------------------------------------------- -- gpio_core - entity/architecture pair ------------------------------------------------------------------------------- -- ************************************************************************* -- DISCLAIMER OF LIABILITY -- -- This file contains proprietary and confidential information of -- Xilinx, Inc. ("Xilinx"), that is distributed under a license -- from Xilinx, and may be used, copied and/or disclosed only -- pursuant to the terms of a valid license agreement with Xilinx. -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION -- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER -- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT -- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, -- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx -- does not warrant that functions included in the Materials will -- meet the requirements of Licensee, or that the operation of the -- Materials will be uninterrupted or error-free, or that defects -- in the Materials will be corrected. Furthermore, Xilinx does -- not warrant or make any representations regarding use, or the -- results of the use, of the Materials in terms of correctness, -- accuracy, reliability or otherwise. -- -- Xilinx products are not designed or intended to be fail-safe, -- or for use in any application requiring fail-safe performance, -- such as life-support or safety devices or systems, Class III -- medical devices, nuclear facilities, applications related to -- the deployment of airbags, or any other applications that could -- lead to death, personal injury or severe property or -- environmental damage (individually and collectively, "critical -- applications"). Customer assumes the sole risk and liability -- of any use of Xilinx products in critical applications, -- subject only to applicable laws and regulations governing -- limitations on product liability. -- -- Copyright 2009 Xilinx, Inc. -- All rights reserved. -- -- This disclaimer and copyright notice must be retained as part -- of this file at all times. -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: gpio_core.vhd -- Version: v1.01a -- Description: General Purpose I/O for AXI Interface -- ------------------------------------------------------------------------------- -- Structure: -- axi_gpio.vhd -- -- axi_lite_ipif.vhd -- -- interrupt_control.vhd -- -- gpio_core.vhd -- ------------------------------------------------------------------------------- -- -- Author: KSB -- History: -- ~~~~~~~~~~~~~~ -- KSB 09/15/09 -- ^^^^^^^^^^^^^^ -- ~~~~~~~~~~~~~~ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_cmb" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; library lib_cdc_v1_0_2; ------------------------------------------------------------------------------- -- Definition of Generics : -- ------------------------------------------------------------------------------- -- C_DW -- Data width of PLB BUS. -- C_AW -- Address width of PLB BUS. -- C_GPIO_WIDTH -- GPIO Data Bus width. -- C_GPIO2_WIDTH -- GPIO2 Data Bus width. -- C_INTERRUPT_PRESENT -- GPIO Interrupt. -- C_DOUT_DEFAULT -- GPIO_DATA Register reset value. -- C_TRI_DEFAULT -- GPIO_TRI Register reset value. -- C_IS_DUAL -- Dual Channel GPIO. -- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value. -- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value. -- C_FAMILY -- XILINX FPGA family ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Definition of Ports -- ------------------------------------------------------------------------------- -- Clk -- Input clock -- Rst -- Reset -- ABus_Reg -- Bus to IP address -- BE_Reg -- Bus to IP byte enables -- DBus_Reg -- Bus to IP data bus -- RNW_Reg -- Bus to IP read write control -- GPIO_DBus -- IP to Bus data bus -- GPIO_xferAck -- GPIO transfer acknowledge -- GPIO_intr -- GPIO channel 1 interrupt to IPIC -- GPIO2_intr -- GPIO channel 2 interrupt to IPIC -- GPIO_Select -- GPIO select -- -- GPIO_IO_I -- Channel 1 General purpose I/O in port -- GPIO_IO_O -- Channel 1 General purpose I/O out port -- GPIO_IO_T -- Channel 1 General purpose I/O TRI-STATE control port -- GPIO2_IO_I -- Channel 2 General purpose I/O in port -- GPIO2_IO_O -- Channel 2 General purpose I/O out port -- GPIO2_IO_T -- Channel 2 General purpose I/O TRI-STATE control port ------------------------------------------------------------------------------- entity GPIO_Core is generic ( C_DW : integer := 32; C_AW : integer := 32; C_GPIO_WIDTH : integer := 32; C_GPIO2_WIDTH : integer := 32; C_MAX_GPIO_WIDTH : integer := 32; C_INTERRUPT_PRESENT : integer := 0; C_DOUT_DEFAULT : std_logic_vector (0 to 31) := X"0000_0000"; C_TRI_DEFAULT : std_logic_vector (0 to 31) := X"FFFF_FFFF"; C_IS_DUAL : integer := 0; C_ALL_OUTPUTS : integer range 0 to 1 := 0;--2/28/2013 C_ALL_OUTPUTS_2 : integer range 0 to 1 := 0;--2/28/2013 C_ALL_INPUTS : integer range 0 to 1 := 0; C_ALL_INPUTS_2 : integer range 0 to 1 := 0; C_DOUT_DEFAULT_2 : std_logic_vector (0 to 31) := X"0000_0000"; C_TRI_DEFAULT_2 : std_logic_vector (0 to 31) := X"FFFF_FFFF"; C_FAMILY : string := "virtex7" ); port ( Clk : in std_logic; Rst : in std_logic; ABus_Reg : in std_logic_vector(0 to C_AW-1); BE_Reg : in std_logic_vector(0 to C_DW/8-1); DBus_Reg : in std_logic_vector(0 to C_MAX_GPIO_WIDTH-1); RNW_Reg : in std_logic; GPIO_DBus : out std_logic_vector(0 to C_DW-1); GPIO_xferAck : out std_logic; GPIO_intr : out std_logic; GPIO2_intr : out std_logic; GPIO_Select : in std_logic; GPIO_IO_I : in std_logic_vector(0 to C_GPIO_WIDTH-1); GPIO_IO_O : out std_logic_vector(0 to C_GPIO_WIDTH-1); GPIO_IO_T : out std_logic_vector(0 to C_GPIO_WIDTH-1); GPIO2_IO_I : in std_logic_vector(0 to C_GPIO2_WIDTH-1); GPIO2_IO_O : out std_logic_vector(0 to C_GPIO2_WIDTH-1); GPIO2_IO_T : out std_logic_vector(0 to C_GPIO2_WIDTH-1) ); end entity GPIO_Core; ------------------------------------------------------------------------------- -- Architecture section ------------------------------------------------------------------------------- architecture IMP of GPIO_Core is -- Pragma Added to supress synth warnings attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes"; ---------------------------------------------------------------------- -- Function for Reduction OR ---------------------------------------------------------------------- function or_reduce(l : std_logic_vector) return std_logic is variable v : std_logic := '0'; begin for i in l'range loop v := v or l(i); end loop; return v; end; --------------------------------------------------------------------- -- End of Function ------------------------------------------------------------------- --constant GPIO_G_W : integer = C_GPIO_WIDTH when (C_GPIO_WIDTH > C_GPIO2_WIDTH) else C_GPIO2_; signal gpio_Data_Select : std_logic_vector(0 to C_IS_DUAL); signal gpio_OE_Select : std_logic_vector(0 to C_IS_DUAL); signal Read_Reg_Rst : STD_LOGIC; signal Read_Reg_In : std_logic_vector(0 to C_GPIO_WIDTH-1); signal Read_Reg_CE : std_logic_vector(0 to C_GPIO_WIDTH-1); signal gpio_Data_Out : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_DOUT_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1); signal gpio_Data_In : std_logic_vector(0 to C_GPIO_WIDTH-1); signal gpio_in_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1); signal gpio_in_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1); signal gpio_io_i_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1); signal gpio_io_i_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1); signal gpio_OE : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_TRI_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1); signal GPIO_DBus_i : std_logic_vector(0 to C_DW-1); signal gpio_data_in_xor : std_logic_vector(0 to C_GPIO_WIDTH-1); signal gpio_data_in_xor_reg : std_logic_vector(0 to C_GPIO_WIDTH-1); signal or_ints : std_logic_vector(0 to 0); signal or_ints2 : std_logic_vector(0 to 0); signal iGPIO_xferAck : STD_LOGIC; signal gpio_xferAck_Reg : STD_LOGIC; signal dout_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1); signal tri_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1); signal reset_zeros : std_logic_vector(0 to C_GPIO_WIDTH-1); signal dout2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal tri2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal reset2_zeros : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio_reg_en : std_logic; begin -- architecture IMP reset_zeros <= (others => '0'); reset2_zeros <= (others => '0'); TIE_DEFAULTS_GENERATE : if C_DW >= C_GPIO_WIDTH generate SELECT_BITS_GENERATE : for i in 0 to C_GPIO_WIDTH-1 generate dout_default_i(i) <= C_DOUT_DEFAULT(i-C_GPIO_WIDTH+C_DW); tri_default_i(i) <= C_TRI_DEFAULT(i-C_GPIO_WIDTH+C_DW); end generate SELECT_BITS_GENERATE; end generate TIE_DEFAULTS_GENERATE; TIE_DEFAULTS_2_GENERATE : if C_DW >= C_GPIO2_WIDTH generate SELECT_BITS_2_GENERATE : for i in 0 to C_GPIO2_WIDTH-1 generate dout2_default_i(i) <= C_DOUT_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW); tri2_default_i(i) <= C_TRI_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW); end generate SELECT_BITS_2_GENERATE; end generate TIE_DEFAULTS_2_GENERATE; Read_Reg_Rst <= iGPIO_xferAck or gpio_xferAck_Reg or (not GPIO_Select) or (GPIO_Select and not RNW_Reg); gpio_reg_en <= GPIO_Select when (ABus_Reg(0) = '0') else '0'; ----------------------------------------------------------------------------- -- XFER_ACK_PROCESS ----------------------------------------------------------------------------- -- Generation of Transfer Ack signal for one clock pulse ----------------------------------------------------------------------------- XFER_ACK_PROCESS : process (Clk) is begin if (Clk'EVENT and Clk = '1') then if (Rst = '1') then iGPIO_xferAck <= '0'; else iGPIO_xferAck <= GPIO_Select and not gpio_xferAck_Reg; if iGPIO_xferAck = '1' then iGPIO_xferAck <= '0'; end if; end if; end if; end process XFER_ACK_PROCESS; ----------------------------------------------------------------------------- -- DELAYED_XFER_ACK_PROCESS ----------------------------------------------------------------------------- -- Single Reg stage to make Transfer Ack period one clock pulse wide ----------------------------------------------------------------------------- DELAYED_XFER_ACK_PROCESS : process (Clk) is begin if (Clk'EVENT and Clk = '1') then if (Rst = '1') then gpio_xferAck_Reg <= '0'; else gpio_xferAck_Reg <= iGPIO_xferAck; end if; end if; end process DELAYED_XFER_ACK_PROCESS; GPIO_xferAck <= iGPIO_xferAck; ----------------------------------------------------------------------------- -- Drive GPIO interrupts to '0' when interrupt not present ----------------------------------------------------------------------------- DONT_GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate gpio_intr <= '0'; gpio2_intr <= '0'; end generate DONT_GEN_INTERRUPT; ---------------------------------------------------------------------------- -- When only one channel is used, the additional logic for the second -- channel ports is not present ----------------------------------------------------------------------------- Not_Dual : if (C_IS_DUAL = 0) generate GPIO2_IO_O <= C_DOUT_DEFAULT(0 to C_GPIO2_WIDTH-1); GPIO2_IO_T <= C_TRI_DEFAULT_2(0 to C_GPIO2_WIDTH-1); ALLOUT_ND : if (C_ALL_OUTPUTS = 1) generate READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate ---------------------------------------------------------------------------- -- XFER_ACK_PROCESS ---------------------------------------------------------------------------- -- Generation of Transfer Ack signal for one clock pulse ---------------------------------------------------------------------------- GPIO_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0'; else GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i); end if; end if; end process; end generate READ_REG_GEN; end generate ALLOUT_ND; ALLIN1_ND : if (C_ALL_INPUTS = 1) generate READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate ---------------------------------------------------------------------------- -- XFER_ACK_PROCESS ---------------------------------------------------------------------------- -- Generation of Transfer Ack signal for one clock pulse ---------------------------------------------------------------------------- GPIO_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0'; else GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i); end if; end if; end process; end generate READ_REG_GEN; end generate ALLIN1_ND; ALLOUT0_ND : if (C_ALL_OUTPUTS = 0 and C_ALL_INPUTS = 0) generate READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate ---------------------------------------------------------------------------- -- XFER_ACK_PROCESS ---------------------------------------------------------------------------- -- Generation of Transfer Ack signal for one clock pulse ---------------------------------------------------------------------------- GPIO_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0'; else if (gpio_OE(i) = '0' and gpio_OE_Select(0) = '0')then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i); else GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i); end if; --GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i) when (gpio_OE(i) = '1') else Read_Reg_In(i); end if; end if; end process; end generate READ_REG_GEN; end generate ALLOUT0_ND; TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0'); end generate TIE_DBUS_GENERATE; ----------------------------------------------------------------------------- -- GPIO_DBUS_PROCESS ----------------------------------------------------------------------------- -- This process generates the GPIO DATA BUS from the GPIO_DBUS_I based on -- the channel select signals ----------------------------------------------------------------------------- GPIO_DBus <= GPIO_DBus_i; ----------------------------------------------------------------------------- -- REG_SELECT_PROCESS ----------------------------------------------------------------------------- -- GPIO REGISTER selection decoder for single channel configuration ----------------------------------------------------------------------------- --REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is begin gpio_Data_Select(0) <= '0'; gpio_OE_Select(0) <= '0'; --if GPIO_Select = '1' then if gpio_reg_en = '1' then if (ABus_Reg(5) = '0') then case ABus_Reg(6) is -- bit A29 when '0' => gpio_Data_Select(0) <= '1'; when '1' => gpio_OE_Select(0) <= '1'; -- coverage off when others => null; -- coverage on end case; end if; end if; end process REG_SELECT_PROCESS; INPUT_DOUBLE_REGS3 : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 0, C_VECTOR_WIDTH => C_GPIO_WIDTH, C_MTBF_STAGES => 4 ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => '0', prmry_vect_in => GPIO_IO_I, scndry_aclk => Clk, scndry_resetn => '0', scndry_out => open, scndry_vect_out => gpio_io_i_d2 ); --------------------------------------------------------------------------- -- GPIO_INDATA_BIRDIR_PROCESS --------------------------------------------------------------------------- -- Reading of channel 1 data from Bidirectional GPIO port -- to GPIO_DATA REGISTER --------------------------------------------------------------------------- GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is begin if Clk = '1' and Clk'EVENT then -- gpio_io_i_d1 <= GPIO_IO_I; -- gpio_io_i_d2 <= gpio_io_i_d1; gpio_Data_In <= gpio_io_i_d2; end if; end process GPIO_INDATA_BIRDIR_PROCESS; --------------------------------------------------------------------------- -- GPIO_OUTDATA_PROCESS --------------------------------------------------------------------------- -- Writing to Channel 1 GPIO_DATA REGISTER --------------------------------------------------------------------------- GPIO_OUTDATA_PROCESS : process(Clk) is begin if Clk = '1' and Clk'EVENT then if (Rst = '1') then gpio_Data_Out <= dout_default_i; elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then for i in 0 to C_GPIO_WIDTH-1 loop gpio_Data_Out(i) <= DBus_Reg(i); end loop; end if; end if; end process GPIO_OUTDATA_PROCESS; --------------------------------------------------------------------------- -- READ_MUX_PROCESS --------------------------------------------------------------------------- -- Selects GPIO_TRI control or GPIO_DATA Register to be read --------------------------------------------------------------------------- READ_MUX_PROCESS : process (gpio_Data_In, gpio_Data_Select, gpio_OE, gpio_OE_Select,gpio_Data_Out) is begin Read_Reg_In <= (others => '0'); if gpio_Data_Select(0) = '1' then Read_Reg_In <= gpio_Data_In; --Read_Reg_In <= gpio_Data_In; elsif gpio_OE_Select(0) = '1' then Read_Reg_In <= gpio_OE; end if; end process READ_MUX_PROCESS; --------------------------------------------------------------------------- -- GPIO_OE_PROCESS --------------------------------------------------------------------------- -- Writing to Channel 1 GPIO_TRI Control REGISTER --------------------------------------------------------------------------- GPIO_OE_PROCESS : process(Clk) is begin if Clk = '1' and Clk'EVENT then if (Rst = '1') then gpio_OE <= tri_default_i; elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then for i in 0 to C_GPIO_WIDTH-1 loop gpio_OE(i) <= DBus_Reg(i); end loop; end if; end if; end process GPIO_OE_PROCESS; GPIO_IO_O <= gpio_Data_Out; GPIO_IO_T <= gpio_OE; ---------------------------------------------------------------------------- -- INTERRUPT IS PRESENT ---------------------------------------------------------------------------- -- When the C_INTERRUPT_PRESENT=1, the interrupt is driven based on whether -- there is a change in the data coming in at the GPIO_IO_I port or GPIO_In -- port ---------------------------------------------------------------------------- GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 1) generate gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2; ------------------------------------------------------------------------- -- An interrupt conditon exists if there is a change on any bit. ------------------------------------------------------------------------- or_ints(0) <= or_reduce(gpio_data_in_xor_reg); ------------------------------------------------------------------------- -- Registering Interrupt condition ------------------------------------------------------------------------- REGISTER_XOR_INTR : process (Clk) is begin if (Clk'EVENT and Clk = '1') then if (Rst = '1') then gpio_data_in_xor_reg <= reset_zeros; GPIO_intr <= '0'; else gpio_data_in_xor_reg <= gpio_data_in_xor; GPIO_intr <= or_ints(0); end if; end if; end process REGISTER_XOR_INTR; gpio2_intr <= '0'; -- Channel 2 interrupt is driven low end generate GEN_INTERRUPT; end generate Not_Dual; ---)(------------------------------------------------------------------------ -- When both the channels are used, the additional logic for the second -- channel ports ----------------------------------------------------------------------------- Dual : if (C_IS_DUAL = 1) generate signal gpio2_Data_In : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio2_in_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio2_in_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio2_io_i_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio2_io_i_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio2_data_in_xor : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio2_data_in_xor_reg : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio2_Data_Out : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_DOUT_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1); signal gpio2_OE : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_TRI_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1); signal Read_Reg2_In : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal Read_Reg2_CE : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal GPIO2_DBus_i : std_logic_vector(0 to C_DW-1); begin ALLOUT0_ND_G0 : if (C_ALL_OUTPUTS = 0 and C_ALL_INPUTS = 0) generate READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate ---------------------------------------------------------------------------- -- XFER_ACK_PROCESS ---------------------------------------------------------------------------- -- Generation of Transfer Ack signal for one clock pulse ---------------------------------------------------------------------------- GPIO_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0'; else if (gpio_OE(i) = '0' and gpio_OE_Select(0) = '0') then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i); else GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i); end if; --GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i) when (gpio_OE(i) = '1') else Read_Reg_In(i); end if; end if; end process; end generate READ_REG_GEN; end generate ALLOUT0_ND_G0; ALLIN0_ND_G0 : if (C_ALL_INPUTS = 1) generate READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate ---------------------------------------------------------------------------- -- XFER_ACK_PROCESS ---------------------------------------------------------------------------- -- Generation of Transfer Ack signal for one clock pulse ---------------------------------------------------------------------------- GPIO_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0'; else GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i); end if; end if; end process; end generate READ_REG_GEN; end generate ALLIN0_ND_G0; ALLOUT0_ND_G1 : if (C_ALL_OUTPUTS = 1) generate READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate begin -------------------------------------------------------------------------- -- GPIO_DBUS_I_PROCESS -------------------------------------------------------------------------- -- This process generates the GPIO CHANNEL1 DATA BUS -------------------------------------------------------------------------- GPIO_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0'; else GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i); end if; end if; end process; end generate READ_REG_GEN; end generate ALLOUT0_ND_G1; TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0'); end generate TIE_DBUS_GENERATE; ALLIN0_ND_G2 : if (C_ALL_OUTPUTS_2 = 0 and C_ALL_INPUTS_2 = 1) generate READ_REG2_GEN : for i in 0 to C_GPIO2_WIDTH-1 generate -------------------------------------------------------------------------- -- GPIO2_DBUS_I_PROCESS -------------------------------------------------------------------------- -- This process generates the GPIO CHANNEL2 DATA BUS -------------------------------------------------------------------------- GPIO2_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= '0'; else GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= Read_Reg2_In(i); --GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i) when (gpio_OE(i) = '1') else Read_Reg_In(i); end if; end if; end process; end generate READ_REG2_GEN; end generate ALLIN0_ND_G2; ALLOUT0_ND_G2 : if (C_ALL_OUTPUTS_2 = 0 and C_ALL_INPUTS_2 = 0) generate READ_REG2_GEN : for i in 0 to C_GPIO2_WIDTH-1 generate -------------------------------------------------------------------------- -- GPIO2_DBUS_I_PROCESS -------------------------------------------------------------------------- -- This process generates the GPIO CHANNEL2 DATA BUS -------------------------------------------------------------------------- GPIO2_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= '0'; else if (gpio2_OE(i) = '0' and gpio_OE_Select(1) = '0') then GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= gpio2_Data_Out(i); else GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= Read_Reg2_In(i); end if; -- GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= gpio2_Data_Out(i) when (gpio2_OE(i) = '1') else Read_Reg2_In(i); --GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i) when (gpio_OE(i) = '1') else Read_Reg_In(i); end if; end if; end process; end generate READ_REG2_GEN; end generate ALLOUT0_ND_G2; ALLOUT1_ND_G2 : if (C_ALL_OUTPUTS_2 = 1) generate READ_REG2_GEN : for i in 0 to C_GPIO2_WIDTH-1 generate -------------------------------------------------------------------------- -- GPIO2_DBUS_I_PROCESS -------------------------------------------------------------------------- -- This process generates the GPIO CHANNEL2 DATA BUS -------------------------------------------------------------------------- GPIO2_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= '0'; else GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= gpio2_Data_Out(i); end if; end if; end process; end generate READ_REG2_GEN; end generate ALLOUT1_ND_G2; TIE_DBUS2_GENERATE : if C_DW > C_GPIO2_WIDTH generate GPIO2_DBus_i(0 to C_DW-C_GPIO2_WIDTH-1) <= (others => '0'); end generate TIE_DBUS2_GENERATE; --------------------------------------------------------------------------- -- GPIO_DBUS_PROCESS --------------------------------------------------------------------------- -- This process generates the GPIO DATA BUS from the GPIO_DBUS_I and -- GPIO2_DBUS_I based on which channel is selected --------------------------------------------------------------------------- GPIO_DBus <= GPIO_DBus_i when (((gpio_Data_Select(0) = '1') or (gpio_OE_Select(0) = '1')) and (RNW_Reg = '1')) else GPIO2_DBus_i; ----------------------------------------------------------------------------- -- DUAL_REG_SELECT_PROCESS ----------------------------------------------------------------------------- -- GPIO REGISTER selection decoder for Dual channel configuration ----------------------------------------------------------------------------- --DUAL_REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is DUAL_REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is variable ABus_reg_select : std_logic_vector(0 to 1); begin ABus_reg_select := ABus_Reg(5 to 6); gpio_Data_Select <= (others => '0'); gpio_OE_Select <= (others => '0'); --if GPIO_Select = '1' then if gpio_reg_en = '1' then -- case ABus_Reg(28 to 29) is -- bit A28,A29 for dual case ABus_reg_select is -- bit A28,A29 for dual when "00" => gpio_Data_Select(0) <= '1'; when "01" => gpio_OE_Select(0) <= '1'; when "10" => gpio_Data_Select(1) <= '1'; when "11" => gpio_OE_Select(1) <= '1'; -- coverage off when others => null; -- coverage on end case; end if; end process DUAL_REG_SELECT_PROCESS; --------------------------------------------------------------------------- -- GPIO_INDATA_BIRDIR_PROCESS --------------------------------------------------------------------------- -- Reading of channel 1 data from Bidirectional GPIO port -- to GPIO_DATA REGISTER --------------------------------------------------------------------------- INPUT_DOUBLE_REGS4 : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 0, C_VECTOR_WIDTH => C_GPIO_WIDTH, C_MTBF_STAGES => 4 ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => '0', prmry_vect_in => GPIO_IO_I, scndry_aclk => Clk, scndry_resetn => '0', scndry_out => open, scndry_vect_out => gpio_io_i_d2 ); GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is begin if Clk = '1' and Clk'EVENT then -- gpio_io_i_d1 <= GPIO_IO_I; -- gpio_io_i_d2 <= gpio_io_i_d1; --if (C_ALL_OUTPUTS = '1') then -- gpio_Data_In <= gpio_Data_Out; -- else gpio_Data_In <= gpio_io_i_d2; -- end if; end if; end process GPIO_INDATA_BIRDIR_PROCESS; INPUT_DOUBLE_REGS5 : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 0, C_VECTOR_WIDTH => C_GPIO2_WIDTH, C_MTBF_STAGES => 4 ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => '0', prmry_vect_in => GPIO2_IO_I, scndry_aclk => Clk, scndry_resetn => '0', scndry_out => open, scndry_vect_out => gpio2_io_i_d2 ); --------------------------------------------------------------------------- -- GPIO2_INDATA_BIRDIR_PROCESS --------------------------------------------------------------------------- -- Reading of channel 2 data from Bidirectional GPIO2 port -- to GPIO2_DATA REGISTER --------------------------------------------------------------------------- GPIO2_INDATA_BIRDIR_PROCESS : process(Clk) is begin if Clk = '1' and Clk'EVENT then -- gpio2_io_i_d1 <= GPIO2_IO_I; -- gpio2_io_i_d2 <= gpio2_io_i_d1; -- if (C_ALL_OUTPUTS = '1') then -- gpio2_Data_In <= gpio2_Data_Out; -- else gpio2_Data_In <= gpio2_io_i_d2; -- end if; end if; end process GPIO2_INDATA_BIRDIR_PROCESS; --------------------------------------------------------------------------- -- GPIO_OUTDATA_PROCESS_0_0 --------------------------------------------------------------------------- -- Writing to Channel 1 GPIO_DATA REGISTER --------------------------------------------------------------------------- GPIO_OUTDATA_PROCESS_0_0 : process(Clk) is begin if Clk = '1' and Clk'EVENT then if (Rst = '1') then gpio_Data_Out <= dout_default_i; elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then for i in 0 to C_GPIO_WIDTH-1 loop gpio_Data_Out(i) <= DBus_Reg(i); end loop; end if; end if; end process GPIO_OUTDATA_PROCESS_0_0; --------------------------------------------------------------------------- -- GPIO_OE_PROCESS_0_0 --------------------------------------------------------------------------- -- Writing to Channel 1 GPIO_TRI Control REGISTER --------------------------------------------------------------------------- GPIO_OE_PROCESS : process(Clk) is begin if Clk = '1' and Clk'EVENT then if (Rst = '1') then gpio_OE <= tri_default_i; elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then for i in 0 to C_GPIO_WIDTH-1 loop gpio_OE(i) <= DBus_Reg(i); -- end if; end loop; end if; end if; end process GPIO_OE_PROCESS; --------------------------------------------------------------------------- -- GPIO2_OUTDATA_PROCESS_0_0 --------------------------------------------------------------------------- -- Writing to Channel 2 GPIO2_DATA REGISTER --------------------------------------------------------------------------- GPIO2_OUTDATA_PROCESS_0_0 : process(Clk) is begin if Clk = '1' and Clk'EVENT then if (Rst = '1') then gpio2_Data_Out <= dout2_default_i; elsif gpio_Data_Select(1) = '1' and RNW_Reg = '0' then for i in 0 to C_GPIO2_WIDTH-1 loop gpio2_Data_Out(i) <= DBus_Reg(i); -- end if; end loop; end if; end if; end process GPIO2_OUTDATA_PROCESS_0_0; --------------------------------------------------------------------------- -- GPIO2_OE_PROCESS_0_0 --------------------------------------------------------------------------- -- Writing to Channel 2 GPIO2_TRI Control REGISTER --------------------------------------------------------------------------- GPIO2_OE_PROCESS_0_0 : process(Clk) is begin if Clk = '1' and Clk'EVENT then if (Rst = '1') then gpio2_OE <= tri2_default_i; elsif gpio_OE_Select(1) = '1' and RNW_Reg = '0' then for i in 0 to C_GPIO2_WIDTH-1 loop gpio2_OE(i) <= DBus_Reg(i); end loop; end if; end if; end process GPIO2_OE_PROCESS_0_0; GPIO_IO_O <= gpio_Data_Out; GPIO_IO_T <= gpio_OE; GPIO2_IO_O <= gpio2_Data_Out; GPIO2_IO_T <= gpio2_OE; --------------------------------------------------------------------------- -- READ_MUX_PROCESS_0_0 --------------------------------------------------------------------------- -- Selects among Channel 1 GPIO_DATA ,GPIO_TRI and Channel 2 GPIO2_DATA -- GPIO2_TRI REGISTERS for reading --------------------------------------------------------------------------- READ_MUX_PROCESS_0_0 : process (gpio2_Data_In, gpio2_OE, gpio_Data_In, gpio_Data_Select, gpio_OE, gpio_OE_Select,gpio_Data_Out,gpio2_Data_Out) is begin Read_Reg_In <= (others => '0'); Read_Reg2_In <= (others => '0'); if gpio_Data_Select(0) = '1' then Read_Reg_In <= gpio_Data_In; --Read_Reg_In <= gpio_Data_In; elsif gpio_OE_Select(0) = '1' then Read_Reg_In <= gpio_OE; elsif gpio_Data_Select(1) = '1' then Read_Reg2_In <= gpio2_Data_In; --Read_Reg2_In <= gpio2_Data_In; --Read_Reg2_In<= gpio2_Data_In; elsif gpio_OE_Select(1) = '1' then Read_Reg2_In <= gpio2_OE; end if; end process READ_MUX_PROCESS_0_0; --------------------------------------------------------------------------- -- INTERRUPT IS PRESENT --------------------------------------------------------------------------- gen_interrupt_dual : if (C_INTERRUPT_PRESENT = 1) generate gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2; gpio2_data_in_xor <= gpio2_Data_In xor gpio2_io_i_d2; ------------------------------------------------------------------------- -- An interrupt conditon exists if there is a change any bit. ------------------------------------------------------------------------- or_ints(0) <= or_reduce(gpio_data_in_xor_reg); or_ints2(0) <= or_reduce(gpio2_data_in_xor_reg); ------------------------------------------------------------------------- -- Registering Interrupt condition ------------------------------------------------------------------------- REGISTER_XORs_INTRs : process (Clk) is begin if (Clk'EVENT and Clk = '1') then if (Rst = '1') then gpio_data_in_xor_reg <= reset_zeros; gpio2_data_in_xor_reg <= reset2_zeros; GPIO_intr <= '0'; GPIO2_intr <= '0'; else gpio_data_in_xor_reg <= gpio_data_in_xor; gpio2_data_in_xor_reg <= gpio2_data_in_xor; GPIO_intr <= or_ints(0); GPIO2_intr <= or_ints2(0); end if; end if; end process REGISTER_XORs_INTRs; end generate gen_interrupt_dual; end generate Dual; end architecture IMP; ------------------------------------------------------------------------------- -- AXI_GPIO - entity/architecture pair ------------------------------------------------------------------------------- -- -- ************************************************************************ -- DISCLAIMER OF LIABILITY -- -- This file contains proprietary and confidential information of -- Xilinx, Inc. ("Xilinx"), that is distributed under a license -- from Xilinx, and may be used, copied and/or disclosed only -- pursuant to the terms of a valid license agreement with Xilinx. -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION -- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER -- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT -- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, -- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx -- does not warrant that functions included in the Materials will -- meet the requirements of Licensee, or that the operation of the -- Materials will be uninterrupted or error-free, or that defects -- in the Materials will be corrected. Furthermore, Xilinx does -- not warrant or make any representations regarding use, or the -- results of the use, of the Materials in terms of correctness, -- accuracy, reliability or otherwise. -- -- Xilinx products are not designed or intended to be fail-safe, -- or for use in any application requiring fail-safe performance, -- such as life-support or safety devices or systems, Class III -- medical devices, nuclear facilities, applications related to -- the deployment of airbags, or any other applications that could -- lead to death, personal injury or severe property or -- environmental damage (individually and collectively, "critical -- applications"). Customer assumes the sole risk and liability -- of any use of Xilinx products in critical applications, -- subject only to applicable laws and regulations governing -- limitations on product liability. -- -- Copyright 2009 Xilinx, Inc. -- All rights reserved. -- -- This disclaimer and copyright notice must be retained as part -- of this file at all times. -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_gpio.vhd -- Version: v2.0 -- Description: General Purpose I/O for AXI Interface -- ------------------------------------------------------------------------------- -- Structure: -- axi_gpio.vhd -- -- axi_lite_ipif.vhd -- -- interrupt_control.vhd -- -- gpio_core.vhd ------------------------------------------------------------------------------- -- Author: KSB -- History: -- ~~~~~~~~~~~~~~ -- KSB 07/28/09 -- ^^^^^^^^^^^^^^ -- First version of axi_gpio. Based on xps_gpio 2.00a -- -- KSB 05/20/10 -- ^^^^^^^^^^^^^^ -- Updated for holes in address range -- ~~~~~~~~~~~~~~ -- VB 09/23/10 -- ^^^^^^^^^^^^^^ -- Updated for axi_lite_ipfi_v1_01_a -- ~~~~~~~~~~~~~~ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_cmb" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; use std.textio.all; ------------------------------------------------------------------------------- -- AXI common package of the proc common library is used for different -- function declarations ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- axi_gpio_v2_0_15 library is used for axi4 component declarations ------------------------------------------------------------------------------- library axi_lite_ipif_v3_0_4; use axi_lite_ipif_v3_0_4.ipif_pkg.calc_num_ce; use axi_lite_ipif_v3_0_4.ipif_pkg.INTEGER_ARRAY_TYPE; use axi_lite_ipif_v3_0_4.ipif_pkg.SLV64_ARRAY_TYPE; ------------------------------------------------------------------------------- -- axi_gpio_v2_0_15 library is used for interrupt controller component -- declarations ------------------------------------------------------------------------------- library interrupt_control_v3_1_4; ------------------------------------------------------------------------------- -- axi_gpio_v2_0_15 library is used for axi_gpio component declarations ------------------------------------------------------------------------------- library axi_gpio_v2_0_15; ------------------------------------------------------------------------------- -- Defination of Generics : -- ------------------------------------------------------------------------------- -- AXI generics -- C_BASEADDR -- Base address of the core -- C_HIGHADDR -- Permits alias of address space -- by making greater than xFFF -- C_S_AXI_ADDR_WIDTH -- Width of AXI Address interface (in bits) -- C_S_AXI_DATA_WIDTH -- Width of the AXI Data interface (in bits) -- C_FAMILY -- XILINX FPGA family -- C_INSTANCE -- Instance name ot the core in the EDK system -- C_GPIO_WIDTH -- GPIO Data Bus width. -- C_ALL_INPUTS -- Inputs Only. -- C_INTERRUPT_PRESENT -- GPIO Interrupt. -- C_IS_BIDIR -- Selects gpio_io_i as input. -- C_DOUT_DEFAULT -- GPIO_DATA Register reset value. -- C_TRI_DEFAULT -- GPIO_TRI Register reset value. -- C_IS_DUAL -- Dual Channel GPIO. -- C_ALL_INPUTS_2 -- Channel2 Inputs only. -- C_IS_BIDIR_2 -- Selects gpio2_io_i as input. -- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value. -- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value. ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Defination of Ports -- ------------------------------------------------------------------------------- -- AXI signals -- s_axi_awaddr -- AXI Write address -- s_axi_awvalid -- Write address valid -- s_axi_awready -- Write address ready -- s_axi_wdata -- Write data -- s_axi_wstrb -- Write strobes -- s_axi_wvalid -- Write valid -- s_axi_wready -- Write ready -- s_axi_bresp -- Write response -- s_axi_bvalid -- Write response valid -- s_axi_bready -- Response ready -- s_axi_araddr -- Read address -- s_axi_arvalid -- Read address valid -- s_axi_arready -- Read address ready -- s_axi_rdata -- Read data -- s_axi_rresp -- Read response -- s_axi_rvalid -- Read valid -- s_axi_rready -- Read ready -- GPIO Signals -- gpio_io_i -- Channel 1 General purpose I/O in port -- gpio_io_o -- Channel 1 General purpose I/O out port -- gpio_io_t -- Channel 1 General purpose I/O -- TRI-STATE control port -- gpio2_io_i -- Channel 2 General purpose I/O in port -- gpio2_io_o -- Channel 2 General purpose I/O out port -- gpio2_io_t -- Channel 2 General purpose I/O -- TRI-STATE control port -- System Signals -- s_axi_aclk -- AXI Clock -- s_axi_aresetn -- AXI Reset -- ip2intc_irpt -- AXI GPIO Interrupt ------------------------------------------------------------------------------- entity axi_gpio is generic ( -- -- System Parameter C_FAMILY : string := "virtex7"; -- -- AXI Parameters C_S_AXI_ADDR_WIDTH : integer range 9 to 9 := 9; C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32; -- -- GPIO Parameter C_GPIO_WIDTH : integer range 1 to 32 := 32; C_GPIO2_WIDTH : integer range 1 to 32 := 32; C_ALL_INPUTS : integer range 0 to 1 := 0; C_ALL_INPUTS_2 : integer range 0 to 1 := 0; C_ALL_OUTPUTS : integer range 0 to 1 := 0;--2/28/2013 C_ALL_OUTPUTS_2 : integer range 0 to 1 := 0;--2/28/2013 C_INTERRUPT_PRESENT : integer range 0 to 1 := 0; C_DOUT_DEFAULT : std_logic_vector (31 downto 0) := X"0000_0000"; C_TRI_DEFAULT : std_logic_vector (31 downto 0) := X"FFFF_FFFF"; C_IS_DUAL : integer range 0 to 1 := 0; C_DOUT_DEFAULT_2 : std_logic_vector (31 downto 0) := X"0000_0000"; C_TRI_DEFAULT_2 : std_logic_vector (31 downto 0) := X"FFFF_FFFF" ); port ( -- AXI interface Signals -------------------------------------------------- s_axi_aclk : in std_logic; s_axi_aresetn : in std_logic; s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); s_axi_awvalid : in std_logic; s_axi_awready : out std_logic; s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); s_axi_wvalid : in std_logic; s_axi_wready : out std_logic; s_axi_bresp : out std_logic_vector(1 downto 0); s_axi_bvalid : out std_logic; s_axi_bready : in std_logic; s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); s_axi_arvalid : in std_logic; s_axi_arready : out std_logic; s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); s_axi_rresp : out std_logic_vector(1 downto 0); s_axi_rvalid : out std_logic; s_axi_rready : in std_logic; -- Interrupt--------------------------------------------------------------- ip2intc_irpt : out std_logic; -- GPIO Signals------------------------------------------------------------ gpio_io_i : in std_logic_vector(C_GPIO_WIDTH-1 downto 0); gpio_io_o : out std_logic_vector(C_GPIO_WIDTH-1 downto 0); gpio_io_t : out std_logic_vector(C_GPIO_WIDTH-1 downto 0); gpio2_io_i : in std_logic_vector(C_GPIO2_WIDTH-1 downto 0); gpio2_io_o : out std_logic_vector(C_GPIO2_WIDTH-1 downto 0); gpio2_io_t : out std_logic_vector(C_GPIO2_WIDTH-1 downto 0) ); ------------------------------------------------------------------------------- -- fan-out attributes for XST ------------------------------------------------------------------------------- attribute MAX_FANOUT : string; attribute MAX_FANOUT of s_axi_aclk : signal is "10000"; attribute MAX_FANOUT of s_axi_aresetn : signal is "10000"; ------------------------------------------------------------------------------- -- Attributes for MPD file ------------------------------------------------------------------------------- attribute IP_GROUP : string ; attribute IP_GROUP of axi_gpio : entity is "LOGICORE"; attribute SIGIS : string ; attribute SIGIS of s_axi_aclk : signal is "Clk"; attribute SIGIS of s_axi_aresetn : signal is "Rst"; attribute SIGIS of ip2intc_irpt : signal is "INTR_LEVEL_HIGH"; end entity axi_gpio; ------------------------------------------------------------------------------- -- Architecture Section ------------------------------------------------------------------------------- architecture imp of axi_gpio is -- Pragma Added to supress synth warnings attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes"; ------------------------------------------------------------------------------- -- constant added for webtalk information ------------------------------------------------------------------------------- --function chr(sl: std_logic) return character is -- variable c: character; -- begin -- case sl is -- when '0' => c:= '0'; -- when '1' => c:= '1'; -- when 'Z' => c:= 'Z'; -- when 'U' => c:= 'U'; -- when 'X' => c:= 'X'; -- when 'W' => c:= 'W'; -- when 'L' => c:= 'L'; -- when 'H' => c:= 'H'; -- when '-' => c:= '-'; -- end case; -- return c; -- end chr; -- --function str(slv: std_logic_vector) return string is -- variable result : string (1 to slv'length); -- variable r : integer; -- begin -- r := 1; -- for i in slv'range loop -- result(r) := chr(slv(i)); -- r := r + 1; -- end loop; -- return result; -- end str; type bo2na_type is array (boolean) of natural; -- boolean to --natural conversion constant bo2na : bo2na_type := (false => 0, true => 1); ------------------------------------------------------------------------------- -- Function Declarations ------------------------------------------------------------------------------- type BOOLEAN_ARRAY_TYPE is array(natural range <>) of boolean; ---------------------------------------------------------------------------- -- This function returns the number of elements that are true in -- a boolean array. ---------------------------------------------------------------------------- function num_set( ba : BOOLEAN_ARRAY_TYPE ) return natural is variable n : natural := 0; begin for i in ba'range loop n := n + bo2na(ba(i)); end loop; return n; end; ---------------------------------------------------------------------------- -- This function returns a num_ce integer array that is constructed by -- taking only those elements of superset num_ce integer array -- that will be defined by the current case. -- The superset num_ce array is given by parameter num_ce_by_ard. -- The current case the ard elements that will be used is given -- by parameter defined_ards. ---------------------------------------------------------------------------- function qual_ard_num_ce_array( defined_ards : BOOLEAN_ARRAY_TYPE; num_ce_by_ard : INTEGER_ARRAY_TYPE ) return INTEGER_ARRAY_TYPE is variable res : INTEGER_ARRAY_TYPE(num_set(defined_ards)-1 downto 0); variable i : natural := 0; variable j : natural := defined_ards'left; begin while i /= res'length loop -- coverage off while defined_ards(j) = false loop j := j+1; end loop; -- coverage on res(i) := num_ce_by_ard(j); i := i+1; j := j+1; end loop; return res; end; ---------------------------------------------------------------------------- -- This function returns a addr_range array that is constructed by -- taking only those elements of superset addr_range array -- that will be defined by the current case. -- The superset addr_range array is given by parameter addr_range_by_ard. -- The current case the ard elements that will be used is given -- by parameter defined_ards. ---------------------------------------------------------------------------- function qual_ard_addr_range_array( defined_ards : BOOLEAN_ARRAY_TYPE; addr_range_by_ard : SLV64_ARRAY_TYPE ) return SLV64_ARRAY_TYPE is variable res : SLV64_ARRAY_TYPE(0 to 2num_set(defined_ards)-1); variable i : natural := 0; variable j : natural := defined_ards'left; begin while i /= res'length loop -- coverage off while defined_ards(j) = false loop j := j+1; end loop; -- coverage on res(i) := addr_range_by_ard(2j); res(i+1) := addr_range_by_ard((2j)+1); i := i+2; j := j+1; end loop; return res; end; function qual_ard_ce_valid( defined_ards : BOOLEAN_ARRAY_TYPE ) return std_logic_vector is variable res : std_logic_vector(0 to 31); begin res := (others => '0'); if defined_ards(defined_ards'right) then res(0 to 3) := "1111"; res(12) := '1'; res(13) := '1'; res(15) := '1'; else res(0 to 3) := "1111"; end if; return res; end; ---------------------------------------------------------------------------- -- This function returns the maximum width amongst the two GPIO Channels -- and if there is only one channel, it returns just the width of that -- channel. ---------------------------------------------------------------------------- function max_width( dual_channel : INTEGER; channel1_width : INTEGER; channel2_width : INTEGER ) return INTEGER is begin if (dual_channel = 0) then return channel1_width; else if (channel1_width > channel2_width) then return channel1_width; else return channel2_width; end if; end if; end; ------------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- constant C_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF"; constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0'); constant INTR_TYPE : integer := 5; constant INTR_BASEADDR : std_logic_vector(0 to 31):= X"00000100"; constant INTR_HIGHADDR : std_logic_vector(0 to 31):= X"000001FF"; constant GPIO_HIGHADDR : std_logic_vector(0 to 31):= X"0000000F"; constant MAX_GPIO_WIDTH : integer := max_width (C_IS_DUAL,C_GPIO_WIDTH,C_GPIO2_WIDTH); constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := qual_ard_addr_range_array( (true,C_INTERRUPT_PRESENT=1), (ZERO_ADDR_PAD & X"00000000", ZERO_ADDR_PAD & GPIO_HIGHADDR, ZERO_ADDR_PAD & INTR_BASEADDR, ZERO_ADDR_PAD & INTR_HIGHADDR ) ); constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := qual_ard_num_ce_array( (true,C_INTERRUPT_PRESENT=1), (4,16) ); constant ARD_CE_VALID : std_logic_vector(0 to 31) := qual_ard_ce_valid( (true,C_INTERRUPT_PRESENT=1) ); constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE(0 to 0+bo2na(C_IS_DUAL=1)) := (others => 5); constant C_USE_WSTRB : integer := 0; constant C_DPHASE_TIMEOUT : integer := 8; ------------------------------------------------------------------------------- -- Signal and Type Declarations ------------------------------------------------------------------------------- signal ip2bus_intrevent : std_logic_vector(0 to 1); signal GPIO_xferAck_i : std_logic; signal Bus2IP_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal Bus2IP1_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal Bus2IP2_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); -- IPIC Used Signals signal ip2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal bus2ip_addr : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1); signal bus2ip_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal bus2ip_rnw : std_logic; signal bus2ip_cs : std_logic_vector(0 to 0 + bo2na (C_INTERRUPT_PRESENT=1)); signal bus2ip_rdce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1); signal bus2ip_wrce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1); signal Intrpt_bus2ip_rdce : std_logic_vector(0 to 15); signal Intrpt_bus2ip_wrce : std_logic_vector(0 to 15); signal intr_wr_ce_or_reduce : std_logic; signal intr_rd_ce_or_reduce : std_logic; signal ip2Bus_RdAck_intr_reg_hole : std_logic; signal ip2Bus_RdAck_intr_reg_hole_d1 : std_logic; signal ip2Bus_WrAck_intr_reg_hole : std_logic; signal ip2Bus_WrAck_intr_reg_hole_d1 : std_logic; signal bus2ip_be : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH / 8) - 1); signal bus2ip_clk : std_logic; signal bus2ip_reset : std_logic; signal bus2ip_resetn : std_logic; signal intr2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal intr2bus_wrack : std_logic; signal intr2bus_rdack : std_logic; signal intr2bus_error : std_logic; signal ip2bus_data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal ip2bus_data_i_D1 : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal ip2bus_wrack_i : std_logic; signal ip2bus_wrack_i_D1 : std_logic; signal ip2bus_rdack_i : std_logic; signal ip2bus_rdack_i_D1 : std_logic; signal ip2bus_error_i : std_logic; signal IP2INTC_Irpt_i : std_logic; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- begin -- architecture IMP AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0_4.axi_lite_ipif generic map ( C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH, C_S_AXI_MIN_SIZE => C_AXI_MIN_SIZE, C_USE_WSTRB => C_USE_WSTRB, C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT, C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY, C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY, C_FAMILY => C_FAMILY ) port map ( S_AXI_ACLK => s_axi_aclk, S_AXI_ARESETN => s_axi_aresetn, S_AXI_AWADDR => s_axi_awaddr, S_AXI_AWVALID => s_axi_awvalid, S_AXI_AWREADY => s_axi_awready, S_AXI_WDATA => s_axi_wdata, S_AXI_WSTRB => s_axi_wstrb, S_AXI_WVALID => s_axi_wvalid, S_AXI_WREADY => s_axi_wready, S_AXI_BRESP => s_axi_bresp, S_AXI_BVALID => s_axi_bvalid, S_AXI_BREADY => s_axi_bready, S_AXI_ARADDR => s_axi_araddr, S_AXI_ARVALID => s_axi_arvalid, S_AXI_ARREADY => s_axi_arready, S_AXI_RDATA => s_axi_rdata, S_AXI_RRESP => s_axi_rresp, S_AXI_RVALID => s_axi_rvalid, S_AXI_RREADY => s_axi_rready, -- IP Interconnect (IPIC) port signals Bus2IP_Clk => bus2ip_clk, Bus2IP_Resetn => bus2ip_resetn, IP2Bus_Data => ip2bus_data_i_D1, IP2Bus_WrAck => ip2bus_wrack_i_D1, IP2Bus_RdAck => ip2bus_rdack_i_D1, --IP2Bus_WrAck => ip2bus_wrack_i, --IP2Bus_RdAck => ip2bus_rdack_i, IP2Bus_Error => ip2bus_error_i, Bus2IP_Addr => bus2ip_addr, Bus2IP_Data => bus2ip_data, Bus2IP_RNW => bus2ip_rnw, Bus2IP_BE => bus2ip_be, Bus2IP_CS => bus2ip_cs, Bus2IP_RdCE => bus2ip_rdce, Bus2IP_WrCE => bus2ip_wrce ); ip2bus_data_i <= intr2bus_data or ip2bus_data; ip2bus_wrack_i <= intr2bus_wrack or (GPIO_xferAck_i and not(bus2ip_rnw)) or ip2Bus_WrAck_intr_reg_hole;-- Holes in Address range ip2bus_rdack_i <= intr2bus_rdack or (GPIO_xferAck_i and bus2ip_rnw) or ip2Bus_RdAck_intr_reg_hole; -- Holes in Address range I_WRACK_RDACK_DELAYS: process(Bus2IP_Clk) is begin if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then if (bus2ip_reset = '1') then ip2bus_wrack_i_D1 <= '0'; ip2bus_rdack_i_D1 <= '0'; ip2bus_data_i_D1 <= (others => '0'); else ip2bus_wrack_i_D1 <= ip2bus_wrack_i; ip2bus_rdack_i_D1 <= ip2bus_rdack_i; ip2bus_data_i_D1 <= ip2bus_data_i; end if; end if; end process I_WRACK_RDACK_DELAYS; ip2bus_error_i <= intr2bus_error; ---------------------- --REG_RESET_FROM_IPIF: convert active low to active hig reset to rest of -- the core. ---------------------- REG_RESET_FROM_IPIF: process (s_axi_aclk) is begin if(s_axi_aclk'event and s_axi_aclk = '1') then bus2ip_reset <= not(bus2ip_resetn); end if; end process REG_RESET_FROM_IPIF; --------------------------------------------------------------------------- -- Interrupts --------------------------------------------------------------------------- INTR_CTRLR_GEN : if (C_INTERRUPT_PRESENT = 1) generate constant NUM_IPIF_IRPT_SRC : natural := 1; constant NUM_CE : integer := 16; signal errack_reserved : std_logic_vector(0 to 1); signal ipif_lvl_interrupts : std_logic_vector(0 to NUM_IPIF_IRPT_SRC-1); begin ipif_lvl_interrupts <= (others => '0'); errack_reserved <= (others => '0'); --- Addr 0X11c, 0X120, 0X128 valid addresses, remaining are holes Intrpt_bus2ip_rdce <= "0000000" & bus2ip_rdce(11) & bus2ip_rdce(12) & '0' & bus2ip_rdce(14) & "00000"; Intrpt_bus2ip_wrce <= "0000000" & bus2ip_wrce(11) & bus2ip_wrce(12) & '0' & bus2ip_wrce(14) & "00000"; intr_rd_ce_or_reduce <= or_reduce(bus2ip_rdce(4 to 10)) or Bus2IP_RdCE(13) or or_reduce(Bus2IP_RdCE(15 to 19)); intr_wr_ce_or_reduce <= or_reduce(bus2ip_wrce(4 to 10)) or bus2ip_wrce(13) or or_reduce(bus2ip_wrce(15 to 19)); I_READ_ACK_INTR_HOLES: process(Bus2IP_Clk) is begin if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then if (bus2ip_reset = '1') then ip2Bus_RdAck_intr_reg_hole <= '0'; ip2Bus_RdAck_intr_reg_hole_d1 <= '0'; else ip2Bus_RdAck_intr_reg_hole_d1 <= intr_rd_ce_or_reduce; ip2Bus_RdAck_intr_reg_hole <= intr_rd_ce_or_reduce and (not ip2Bus_RdAck_intr_reg_hole_d1); end if; end if; end process I_READ_ACK_INTR_HOLES; I_WRITE_ACK_INTR_HOLES: process(Bus2IP_Clk) is begin if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then if (bus2ip_reset = '1') then ip2Bus_WrAck_intr_reg_hole <= '0'; ip2Bus_WrAck_intr_reg_hole_d1 <= '0'; else ip2Bus_WrAck_intr_reg_hole_d1 <= intr_wr_ce_or_reduce; ip2Bus_WrAck_intr_reg_hole <= intr_wr_ce_or_reduce and (not ip2Bus_WrAck_intr_reg_hole_d1); end if; end if; end process I_WRITE_ACK_INTR_HOLES; INTERRUPT_CONTROL_I : entity interrupt_control_v3_1_4.interrupt_control generic map ( C_NUM_CE => NUM_CE, C_NUM_IPIF_IRPT_SRC => NUM_IPIF_IRPT_SRC, C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY, C_INCLUDE_DEV_PENCODER => false, C_INCLUDE_DEV_ISC => false, C_IPIF_DWIDTH => C_S_AXI_DATA_WIDTH ) port map ( -- Inputs From the IPIF Bus Bus2IP_Clk => Bus2IP_Clk, Bus2IP_Reset => bus2ip_reset, Bus2IP_Data => bus2ip_data, Bus2IP_BE => bus2ip_be, Interrupt_RdCE => Intrpt_bus2ip_rdce, Interrupt_WrCE => Intrpt_bus2ip_wrce, -- Interrupt inputs from the IPIF sources that will -- get registered in this design IPIF_Reg_Interrupts => errack_reserved, -- Level Interrupt inputs from the IPIF sources IPIF_Lvl_Interrupts => ipif_lvl_interrupts, -- Inputs from the IP Interface IP2Bus_IntrEvent => ip2bus_intrevent(IP_INTR_MODE_ARRAY'range), -- Final Device Interrupt Output Intr2Bus_DevIntr => IP2INTC_Irpt_i, -- Status Reply Outputs to the Bus Intr2Bus_DBus => intr2bus_data, Intr2Bus_WrAck => intr2bus_wrack, Intr2Bus_RdAck => intr2bus_rdack, Intr2Bus_Error => intr2bus_error, Intr2Bus_Retry => open, Intr2Bus_ToutSup => open ); -- registering interrupt I_INTR_DELAY: process(Bus2IP_Clk) is begin if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then if (bus2ip_reset = '1') then ip2intc_irpt <= '0'; else ip2intc_irpt <= IP2INTC_Irpt_i; end if; end if; end process I_INTR_DELAY; end generate INTR_CTRLR_GEN; ----------------------------------------------------------------------- -- Assigning the intr2bus signal to zero's when interrupt is not -- present ----------------------------------------------------------------------- REMOVE_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate intr2bus_data <= (others => '0'); ip2intc_irpt <= '0'; intr2bus_error <= '0'; intr2bus_rdack <= '0'; intr2bus_wrack <= '0'; ip2Bus_WrAck_intr_reg_hole <= '0'; ip2Bus_RdAck_intr_reg_hole <= '0'; end generate REMOVE_INTERRUPT; gpio_core_1 : entity axi_gpio_v2_0_15.gpio_core generic map ( C_DW => C_S_AXI_DATA_WIDTH, C_AW => C_S_AXI_ADDR_WIDTH, C_GPIO_WIDTH => C_GPIO_WIDTH, C_GPIO2_WIDTH => C_GPIO2_WIDTH, C_MAX_GPIO_WIDTH => MAX_GPIO_WIDTH, C_INTERRUPT_PRESENT => C_INTERRUPT_PRESENT, C_DOUT_DEFAULT => C_DOUT_DEFAULT, C_TRI_DEFAULT => C_TRI_DEFAULT, C_IS_DUAL => C_IS_DUAL, C_ALL_OUTPUTS => C_ALL_OUTPUTS, C_ALL_INPUTS => C_ALL_INPUTS, C_ALL_INPUTS_2 => C_ALL_INPUTS_2, C_ALL_OUTPUTS_2 => C_ALL_OUTPUTS_2, C_DOUT_DEFAULT_2 => C_DOUT_DEFAULT_2, C_TRI_DEFAULT_2 => C_TRI_DEFAULT_2, C_FAMILY => C_FAMILY ) port map ( Clk => Bus2IP_Clk, Rst => bus2ip_reset, ABus_Reg => Bus2IP_Addr, BE_Reg => Bus2IP_BE(0 to C_S_AXI_DATA_WIDTH/8-1), DBus_Reg => Bus2IP_Data_i(0 to MAX_GPIO_WIDTH-1), RNW_Reg => Bus2IP_RNW, GPIO_DBus => IP2Bus_Data(0 to C_S_AXI_DATA_WIDTH-1), GPIO_xferAck => GPIO_xferAck_i, GPIO_Select => bus2ip_cs(0), GPIO_intr => ip2bus_intrevent(0), GPIO2_intr => ip2bus_intrevent(1), GPIO_IO_I => gpio_io_i, GPIO_IO_O => gpio_io_o, GPIO_IO_T => gpio_io_t, GPIO2_IO_I => gpio2_io_i, GPIO2_IO_O => gpio2_io_o, GPIO2_IO_T => gpio2_io_t ); Bus2IP_Data_i <= Bus2IP1_Data_i when bus2ip_cs(0) = '1' and bus2ip_addr (5) = '0'else Bus2IP2_Data_i; BUS_CONV_ch1 : for i in 0 to C_GPIO_WIDTH-1 generate Bus2IP1_Data_i(i) <= Bus2IP_Data(i+ C_S_AXI_DATA_WIDTH-C_GPIO_WIDTH); end generate BUS_CONV_ch1; BUS_CONV_ch2 : for i in 0 to C_GPIO2_WIDTH-1 generate Bus2IP2_Data_i(i) <= Bus2IP_Data(i+ C_S_AXI_DATA_WIDTH-C_GPIO2_WIDTH); end generate BUS_CONV_ch2; end architecture imp;	mit
MarkBlanco/FPGA_Sandbox	RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_6/impl/ip/tmp.srcs/sources_1/ip/convolve_kernel_ap_fmul_6_max_dsp_32/synth/convolve_kernel_ap_fmul_6_max_dsp_32.vhd	3	12822	-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:floating_point:7.1 -- IP Revision: 4 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY floating_point_v7_1_4; USE floating_point_v7_1_4.floating_point_v7_1_4; ENTITY convolve_kernel_ap_fmul_6_max_dsp_32 IS PORT ( aclk : IN STD_LOGIC; aclken : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_b_tvalid : IN STD_LOGIC; s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_result_tvalid : OUT STD_LOGIC; m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END convolve_kernel_ap_fmul_6_max_dsp_32; ARCHITECTURE convolve_kernel_ap_fmul_6_max_dsp_32_arch OF convolve_kernel_ap_fmul_6_max_dsp_32 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF convolve_kernel_ap_fmul_6_max_dsp_32_arch: ARCHITECTURE IS "yes"; COMPONENT floating_point_v7_1_4 IS GENERIC ( C_XDEVICEFAMILY : STRING; C_HAS_ADD : INTEGER; C_HAS_SUBTRACT : INTEGER; C_HAS_MULTIPLY : INTEGER; C_HAS_DIVIDE : INTEGER; C_HAS_SQRT : INTEGER; C_HAS_COMPARE : INTEGER; C_HAS_FIX_TO_FLT : INTEGER; C_HAS_FLT_TO_FIX : INTEGER; C_HAS_FLT_TO_FLT : INTEGER; C_HAS_RECIP : INTEGER; C_HAS_RECIP_SQRT : INTEGER; C_HAS_ABSOLUTE : INTEGER; C_HAS_LOGARITHM : INTEGER; C_HAS_EXPONENTIAL : INTEGER; C_HAS_FMA : INTEGER; C_HAS_FMS : INTEGER; C_HAS_ACCUMULATOR_A : INTEGER; C_HAS_ACCUMULATOR_S : INTEGER; C_A_WIDTH : INTEGER; C_A_FRACTION_WIDTH : INTEGER; C_B_WIDTH : INTEGER; C_B_FRACTION_WIDTH : INTEGER; C_C_WIDTH : INTEGER; C_C_FRACTION_WIDTH : INTEGER; C_RESULT_WIDTH : INTEGER; C_RESULT_FRACTION_WIDTH : INTEGER; C_COMPARE_OPERATION : INTEGER; C_LATENCY : INTEGER; C_OPTIMIZATION : INTEGER; C_MULT_USAGE : INTEGER; C_BRAM_USAGE : INTEGER; C_RATE : INTEGER; C_ACCUM_INPUT_MSB : INTEGER; C_ACCUM_MSB : INTEGER; C_ACCUM_LSB : INTEGER; C_HAS_UNDERFLOW : INTEGER; C_HAS_OVERFLOW : INTEGER; C_HAS_INVALID_OP : INTEGER; C_HAS_DIVIDE_BY_ZERO : INTEGER; C_HAS_ACCUM_OVERFLOW : INTEGER; C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER; C_HAS_ACLKEN : INTEGER; C_HAS_ARESETN : INTEGER; C_THROTTLE_SCHEME : INTEGER; C_HAS_A_TUSER : INTEGER; C_HAS_A_TLAST : INTEGER; C_HAS_B : INTEGER; C_HAS_B_TUSER : INTEGER; C_HAS_B_TLAST : INTEGER; C_HAS_C : INTEGER; C_HAS_C_TUSER : INTEGER; C_HAS_C_TLAST : INTEGER; C_HAS_OPERATION : INTEGER; C_HAS_OPERATION_TUSER : INTEGER; C_HAS_OPERATION_TLAST : INTEGER; C_HAS_RESULT_TUSER : INTEGER; C_HAS_RESULT_TLAST : INTEGER; C_TLAST_RESOLUTION : INTEGER; C_A_TDATA_WIDTH : INTEGER; C_A_TUSER_WIDTH : INTEGER; C_B_TDATA_WIDTH : INTEGER; C_B_TUSER_WIDTH : INTEGER; C_C_TDATA_WIDTH : INTEGER; C_C_TUSER_WIDTH : INTEGER; C_OPERATION_TDATA_WIDTH : INTEGER; C_OPERATION_TUSER_WIDTH : INTEGER; C_RESULT_TDATA_WIDTH : INTEGER; C_RESULT_TUSER_WIDTH : INTEGER; C_FIXED_DATA_UNSIGNED : INTEGER ); PORT ( aclk : IN STD_LOGIC; aclken : IN STD_LOGIC; aresetn : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tready : OUT STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_a_tlast : IN STD_LOGIC; s_axis_b_tvalid : IN STD_LOGIC; s_axis_b_tready : OUT STD_LOGIC; s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_b_tlast : IN STD_LOGIC; s_axis_c_tvalid : IN STD_LOGIC; s_axis_c_tready : OUT STD_LOGIC; s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_c_tlast : IN STD_LOGIC; s_axis_operation_tvalid : IN STD_LOGIC; s_axis_operation_tready : OUT STD_LOGIC; s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_operation_tlast : IN STD_LOGIC; m_axis_result_tvalid : OUT STD_LOGIC; m_axis_result_tready : IN STD_LOGIC; m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_result_tlast : OUT STD_LOGIC ); END COMPONENT floating_point_v7_1_4; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF convolve_kernel_ap_fmul_6_max_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_4,Vivado 2017.2"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF convolve_kernel_ap_fmul_6_max_dsp_32_arch : ARCHITECTURE IS "convolve_kernel_ap_fmul_6_max_dsp_32,floating_point_v7_1_4,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF convolve_kernel_ap_fmul_6_max_dsp_32_arch: ARCHITECTURE IS "convolve_kernel_ap_fmul_6_max_dsp_32,floating_point_v7_1_4,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=" & "0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=6,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_" & "THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK"; ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA"; BEGIN U0 : floating_point_v7_1_4 GENERIC MAP ( C_XDEVICEFAMILY => "zynq", C_HAS_ADD => 0, C_HAS_SUBTRACT => 0, C_HAS_MULTIPLY => 1, C_HAS_DIVIDE => 0, C_HAS_SQRT => 0, C_HAS_COMPARE => 0, C_HAS_FIX_TO_FLT => 0, C_HAS_FLT_TO_FIX => 0, C_HAS_FLT_TO_FLT => 0, C_HAS_RECIP => 0, C_HAS_RECIP_SQRT => 0, C_HAS_ABSOLUTE => 0, C_HAS_LOGARITHM => 0, C_HAS_EXPONENTIAL => 0, C_HAS_FMA => 0, C_HAS_FMS => 0, C_HAS_ACCUMULATOR_A => 0, C_HAS_ACCUMULATOR_S => 0, C_A_WIDTH => 32, C_A_FRACTION_WIDTH => 24, C_B_WIDTH => 32, C_B_FRACTION_WIDTH => 24, C_C_WIDTH => 32, C_C_FRACTION_WIDTH => 24, C_RESULT_WIDTH => 32, C_RESULT_FRACTION_WIDTH => 24, C_COMPARE_OPERATION => 8, C_LATENCY => 6, C_OPTIMIZATION => 1, C_MULT_USAGE => 3, C_BRAM_USAGE => 0, C_RATE => 1, C_ACCUM_INPUT_MSB => 32, C_ACCUM_MSB => 32, C_ACCUM_LSB => -31, C_HAS_UNDERFLOW => 0, C_HAS_OVERFLOW => 0, C_HAS_INVALID_OP => 0, C_HAS_DIVIDE_BY_ZERO => 0, C_HAS_ACCUM_OVERFLOW => 0, C_HAS_ACCUM_INPUT_OVERFLOW => 0, C_HAS_ACLKEN => 1, C_HAS_ARESETN => 0, C_THROTTLE_SCHEME => 3, C_HAS_A_TUSER => 0, C_HAS_A_TLAST => 0, C_HAS_B => 1, C_HAS_B_TUSER => 0, C_HAS_B_TLAST => 0, C_HAS_C => 0, C_HAS_C_TUSER => 0, C_HAS_C_TLAST => 0, C_HAS_OPERATION => 0, C_HAS_OPERATION_TUSER => 0, C_HAS_OPERATION_TLAST => 0, C_HAS_RESULT_TUSER => 0, C_HAS_RESULT_TLAST => 0, C_TLAST_RESOLUTION => 0, C_A_TDATA_WIDTH => 32, C_A_TUSER_WIDTH => 1, C_B_TDATA_WIDTH => 32, C_B_TUSER_WIDTH => 1, C_C_TDATA_WIDTH => 32, C_C_TUSER_WIDTH => 1, C_OPERATION_TDATA_WIDTH => 8, C_OPERATION_TUSER_WIDTH => 1, C_RESULT_TDATA_WIDTH => 32, C_RESULT_TUSER_WIDTH => 1, C_FIXED_DATA_UNSIGNED => 0 ) PORT MAP ( aclk => aclk, aclken => aclken, aresetn => '1', s_axis_a_tvalid => s_axis_a_tvalid, s_axis_a_tdata => s_axis_a_tdata, s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_a_tlast => '0', s_axis_b_tvalid => s_axis_b_tvalid, s_axis_b_tdata => s_axis_b_tdata, s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_b_tlast => '0', s_axis_c_tvalid => '0', s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_c_tlast => '0', s_axis_operation_tvalid => '0', s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_operation_tlast => '0', m_axis_result_tvalid => m_axis_result_tvalid, m_axis_result_tready => '0', m_axis_result_tdata => m_axis_result_tdata ); END convolve_kernel_ap_fmul_6_max_dsp_32_arch;	mit
kloboves/sicxe	vhdl/seg7.vhd	1	6838	library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; -- Data bit connections on display: -- -- --0-- -- \| \| -- 1 2 -- \| \| -- --3-- -- \| \| -- 4 5 -- \| \| -- --6-- [7] (dot) entity seg7 is Port ( clock_i : in std_logic; reset_i : in std_logic; -- special display modes error_i : in std_logic; stop_i : in std_logic; -- register access data_i : in std_logic_vector(7 downto 0); write_mode_i : in std_logic; write_raw_i : std_logic_vector(3 downto 0); write_hex_i : std_logic_vector(1 downto 0); -- display output cathode_o : out std_logic_vector(7 downto 0); anode_o : out std_logic_vector(3 downto 0) ); end seg7; architecture behavioral of seg7 is -- registers signal reg_mode : std_logic_vector(1 downto 0); signal reg_raw : std_logic_vector(31 downto 0); signal reg_hex : std_logic_vector(15 downto 0); -- delay counter signal delay_counter : std_logic_vector(14 downto 0); signal delay_counter_done : std_logic; -- current digit signal digit_counter : std_logic_vector(1 downto 0); signal digit_raw : std_logic_vector(7 downto 0); signal digit_hex : std_logic_vector(3 downto 0); -- output signal cathode : std_logic_vector(7 downto 0); signal anode : std_logic_vector(3 downto 0); signal cathode_delay1 : std_logic_vector(7 downto 0); signal anode_delay1 : std_logic_vector(3 downto 0); begin -- registers reg_proc : process(clock_i) begin if (rising_edge(clock_i)) then if (reset_i = '1') then reg_mode <= (others => '0'); reg_raw <= (others => '0'); reg_hex <= (others => '0'); else reg_mode <= reg_mode; reg_raw <= reg_raw; reg_hex <= reg_hex; if (write_mode_i = '1') then reg_mode <= data_i(1 downto 0); end if; if (write_raw_i(3) = '1') then reg_raw(31 downto 24) <= data_i; end if; if (write_raw_i(2) = '1') then reg_raw(23 downto 16) <= data_i; end if; if (write_raw_i(1) = '1') then reg_raw(15 downto 8) <= data_i; end if; if (write_raw_i(0) = '1') then reg_raw(7 downto 0) <= data_i; end if; if (write_hex_i(1) = '1') then reg_hex(15 downto 8) <= data_i; end if; if (write_hex_i(0) = '1') then reg_hex(7 downto 0) <= data_i; end if; end if; end if; end process; -- delay counter delay_counter_proc : process(clock_i) begin if (rising_edge(clock_i)) then if (reset_i = '1') then delay_counter <= (others => '0'); else if (delay_counter = "111111111111111") then delay_counter <= (others => '0'); else delay_counter <= delay_counter + 1; end if; end if; end if; end process; delay_counter_done_proc : process(delay_counter) begin if (delay_counter = "111111111111111") then delay_counter_done <= '1'; else delay_counter_done <= '0'; end if; end process; -- current digit digit_counter_proc : process(clock_i) begin if (rising_edge(clock_i)) then if (reset_i = '1') then digit_counter <= (others => '0'); else if (delay_counter_done = '1') then digit_counter <= digit_counter + 1; else digit_counter <= digit_counter; end if; end if; end if; end process; digit_proc : process(digit_counter, reg_raw, reg_hex) begin case (digit_counter) is when "00" => digit_raw <= reg_raw(7 downto 0); digit_hex <= reg_hex(3 downto 0); when "01" => digit_raw <= reg_raw(15 downto 8); digit_hex <= reg_hex(7 downto 4); when "10" => digit_raw <= reg_raw(23 downto 16); digit_hex <= reg_hex(11 downto 8); when "11" => digit_raw <= reg_raw(31 downto 24); digit_hex <= reg_hex(15 downto 12); when others => digit_raw <= (others => '0'); digit_hex <= (others => '0'); end case; end process; -- output cathode_o <= cathode_delay1; anode_o <= anode_delay1; delay_proc : process(clock_i) begin if (rising_edge(clock_i)) then if (reset_i = '1') then cathode_delay1 <= (others => '0'); anode_delay1 <= (others => '1'); else cathode_delay1 <= cathode; anode_delay1 <= anode; end if; end if; end process; anode_proc : process(digit_counter) begin case (digit_counter) is when "00" => anode <= "1110"; when "01" => anode <= "1101"; when "10" => anode <= "1011"; when "11" => anode <= "0111"; when others => anode <= (others => '1'); end case; end process; cathode_proc : process(error_i, stop_i, digit_counter, reg_mode, digit_raw, digit_hex) begin if (error_i = '1') then case (digit_counter) is when "00" => cathode <= "11111111"; -- blank when "01" => cathode <= "11100111"; -- r when "10" => cathode <= "11100111"; -- r when "11" => cathode <= "10100100"; -- E when others => cathode <= (others => '1'); end case; elsif (stop_i = '1') then case (digit_counter) is when "00" => cathode <= "11100000"; -- P when "01" => cathode <= "10001000"; -- O when "10" => cathode <= "10100101"; -- t when "11" => cathode <= "10010100"; -- S when others => cathode <= (others => '1'); end case; else if (reg_mode = "00") then cathode <= not digit_raw; else if ((reg_mode = "01" and (digit_counter = "10" or digit_counter = "11")) or (reg_mode = "10" and (digit_counter = "00" or digit_counter = "01"))) then cathode <= not digit_raw; else case digit_hex is when "0000" => cathode <= "10001000"; when "0001" => cathode <= "11011011"; when "0010" => cathode <= "10100010"; when "0011" => cathode <= "10010010"; when "0100" => cathode <= "11010001"; when "0101" => cathode <= "10010100"; when "0110" => cathode <= "10000100"; when "0111" => cathode <= "11011010"; when "1000" => cathode <= "10000000"; when "1001" => cathode <= "10010000"; when "1010" => cathode <= "11000000"; when "1011" => cathode <= "10000101"; when "1100" => cathode <= "10101100"; when "1101" => cathode <= "10000011"; when "1110" => cathode <= "10100100"; when "1111" => cathode <= "11100100"; when others => cathode <= (others => '1'); end case; end if; end if; end if; end process; end behavioral;	mit
kloboves/sicxe	vhdl/gio_device.vhd	1	4795	library ieee; use ieee.std_logic_1164.all; entity gio_device is Port ( clock_i : in std_logic; reset_i : in std_logic; -- device access switches_data_o : out std_logic_vector(7 downto 0); buttons_data_o : out std_logic_vector(7 downto 0); event_o : out std_logic; data_i : in std_logic_vector(7 downto 0); write_leds_i : std_logic; -- physical connections leds_o : out std_logic_vector(7 downto 0); switches_i : in std_logic_vector(7 downto 0); buttons_i : in std_logic_vector(1 downto 0) ); end gio_device; architecture behavioral of gio_device is component debouncer Port ( clock_i : in std_logic; reset_i : in std_logic; input_i : in std_logic; output_o : out std_logic; change_on_o : out std_logic; change_off_o : out std_logic ); end component; -- leds signal reg_leds : std_logic_vector(7 downto 0); -- switches and buttons signal switches : std_logic_vector(7 downto 0); signal buttons : std_logic_vector(1 downto 0); -- events signal switches_event1 : std_logic_vector(7 downto 0); signal switches_event2 : std_logic_vector(7 downto 0); signal buttons_event1 : std_logic_vector(1 downto 0); signal buttons_event2 : std_logic_vector(1 downto 0); begin leds_proc : process(clock_i) begin if (rising_edge(clock_i)) then if (reset_i = '1') then reg_leds <= (others => '0'); else if (write_leds_i = '1') then reg_leds <= data_i; else reg_leds <= reg_leds; end if; end if; end if; end process; leds_o <= reg_leds; switches_data_o <= switches; buttons_data_o <= "000000" & buttons; event_o <= switches_event1(0) or switches_event1(1) or switches_event1(2) or switches_event1(3) or switches_event1(4) or switches_event1(5) or switches_event1(6) or switches_event1(7) or switches_event2(0) or switches_event2(1) or switches_event2(2) or switches_event2(3) or switches_event2(4) or switches_event2(5) or switches_event2(6) or switches_event2(7) or buttons_event1(0) or buttons_event1(1) or buttons_event2(0) or buttons_event2(1); sw0_debounce_cmpt : debouncer port map ( clock_i => clock_i, reset_i => reset_i, input_i => switches_i(0), output_o => switches(0), change_on_o => switches_event1(0), change_off_o => switches_event2(0) ); sw1_debounce_cmpt : debouncer port map ( clock_i => clock_i, reset_i => reset_i, input_i => switches_i(1), output_o => switches(1), change_on_o => switches_event1(1), change_off_o => switches_event2(1) ); sw2_debounce_cmpt : debouncer port map ( clock_i => clock_i, reset_i => reset_i, input_i => switches_i(2), output_o => switches(2), change_on_o => switches_event1(2), change_off_o => switches_event2(2) ); sw3_debounce_cmpt : debouncer port map ( clock_i => clock_i, reset_i => reset_i, input_i => switches_i(3), output_o => switches(3), change_on_o => switches_event1(3), change_off_o => switches_event2(3) ); sw4_debounce_cmpt : debouncer port map ( clock_i => clock_i, reset_i => reset_i, input_i => switches_i(4), output_o => switches(4), change_on_o => switches_event1(4), change_off_o => switches_event2(4) ); sw5_debounce_cmpt : debouncer port map ( clock_i => clock_i, reset_i => reset_i, input_i => switches_i(5), output_o => switches(5), change_on_o => switches_event1(5), change_off_o => switches_event2(5) ); sw6_debounce_cmpt : debouncer port map ( clock_i => clock_i, reset_i => reset_i, input_i => switches_i(6), output_o => switches(6), change_on_o => switches_event1(6), change_off_o => switches_event2(6) ); sw7_debounce_cmpt : debouncer port map ( clock_i => clock_i, reset_i => reset_i, input_i => switches_i(7), output_o => switches(7), change_on_o => switches_event1(7), change_off_o => switches_event2(7) ); btn0_debounce_cmpt : debouncer port map ( clock_i => clock_i, reset_i => reset_i, input_i => buttons_i(0), output_o => buttons(0), change_on_o => buttons_event1(0), change_off_o => buttons_event2(0) ); btn1_debounce_cmpt : debouncer port map ( clock_i => clock_i, reset_i => reset_i, input_i => buttons_i(1), output_o => buttons(1), change_on_o => buttons_event1(1), change_off_o => buttons_event2(1) ); end behavioral;	mit
nathdwek/vhdltree	test/dummy_project/.vhd	7	7	--test	mit
MarkBlanco/FPGA_Sandbox	RecComp/Lab3/ip_repo/zed_audio_ctrl/zed_audio_ctrl.srcs/sources_1/imports/i2s_audio/slave_attachment.vhd	7	21369	------------------------------------------------------------------- -- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. -- -- -- -- This file contains confidential and proprietary information -- -- of Xilinx, Inc. and is protected under U.S. and -- -- international copyright and other intellectual property -- -- laws. -- -- -- -- DISCLAIMER -- -- This disclaimer is not a license and does not grant any -- -- rights to the materials distributed herewith. Except as -- -- otherwise provided in a valid license issued to you by -- -- Xilinx, and to the maximum extent permitted by applicable -- -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- -- (2) Xilinx shall not be liable (whether in contract or tort, -- -- including negligence, or under any other theory of -- -- liability) for any loss or damage of any kind or nature -- -- related to, arising under or in connection with these -- -- materials, including for any direct, or any indirect, -- -- special, incidental, or consequential loss or damage -- -- (including loss of data, profits, goodwill, or any type of -- -- loss or damage suffered as a result of any action brought -- -- by a third party) even if such damage or loss was -- -- reasonably foreseeable or Xilinx had been advised of the -- -- possibility of the same. -- -- -- -- CRITICAL APPLICATIONS -- -- Xilinx products are not designed or intended to be fail- -- -- safe, or for use in any application requiring fail-safe -- -- performance, such as life-support or safety devices or -- -- systems, Class III medical devices, nuclear facilities, -- -- applications related to the deployment of airbags, or any -- -- other applications that could lead to death, personal -- -- injury, or severe property or environmental damage -- -- (individually and collectively, "Critical -- -- Applications"). Customer assumes the sole risk and -- -- liability of any use of Xilinx products in Critical -- -- Applications, subject only to applicable laws and -- -- regulations governing limitations on product liability. -- -- -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- -- PART OF THIS FILE AT ALL TIMES. -- ------------------------------------------------------------------- -- ************************************************************************ -- ------------------------------------------------------------------------------- -- Filename: slave_attachment.vhd -- Version: v1.01.a -- Description: AXI slave attachment supporting single transfers ------------------------------------------------------------------------------- -- Structure: This section shows the hierarchical structure of axi_lite_ipif. -- -- --axi_lite_ipif.vhd -- --slave_attachment.vhd -- --address_decoder.vhd ------------------------------------------------------------------------------- -- Author: BSB -- -- History: -- -- BSB 05/20/10 -- First version -- ~~~~~~ -- - Created the first version v1.00.a -- ^^^^^^ -- ~~~~~~ -- SK 06/09/10 -- updated to reduce the utilization -- 1. State machine is re-designed -- 2. R and B channels are registered and AW, AR, W channels are non-registered -- 3. Address decoding is done only for the required address bits and not complete -- 32 bits -- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux -- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg -- function. -- ^^^^^^ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- access_cs machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_cmb" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_misc.all; use work.common_types.all; ------------------------------------------------------------------------------- -- Definition of Generics ------------------------------------------------------------------------------- -- C_IPIF_ABUS_WIDTH -- IPIF Address bus width -- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width -- C_S_AXI_MIN_SIZE -- Minimum address range of the IP -- C_USE_WSTRB -- Use write strobs or not -- C_DPHASE_TIMEOUT -- Data phase time out counter -- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range -- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range -- C_FAMILY -- Target FPGA family ------------------------------------------------------------------------------- -- Definition of Ports ------------------------------------------------------------------------------- -- S_AXI_ACLK -- AXI Clock -- S_AXI_ARESET -- AXI Reset -- S_AXI_AWADDR -- AXI Write address -- S_AXI_AWVALID -- Write address valid -- S_AXI_AWREADY -- Write address ready -- S_AXI_WDATA -- Write data -- S_AXI_WSTRB -- Write strobes -- S_AXI_WVALID -- Write valid -- S_AXI_WREADY -- Write ready -- S_AXI_BRESP -- Write response -- S_AXI_BVALID -- Write response valid -- S_AXI_BREADY -- Response ready -- S_AXI_ARADDR -- Read address -- S_AXI_ARVALID -- Read address valid -- S_AXI_ARREADY -- Read address ready -- S_AXI_RDATA -- Read data -- S_AXI_RRESP -- Read response -- S_AXI_RVALID -- Read valid -- S_AXI_RREADY -- Read ready -- Bus2IP_Clk -- Synchronization clock provided to User IP -- Bus2IP_Reset -- Active high reset for use by the User IP -- Bus2IP_Addr -- Desired address of read or write operation -- Bus2IP_RNW -- Read or write indicator for the transaction -- Bus2IP_BE -- Byte enables for the data bus -- Bus2IP_CS -- Chip select for the transcations -- Bus2IP_RdCE -- Chip enables for the read -- Bus2IP_WrCE -- Chip enables for the write -- Bus2IP_Data -- Write data bus to the User IP -- IP2Bus_Data -- Input Read Data bus from the User IP -- IP2Bus_WrAck -- Active high Write Data qualifier from the IP -- IP2Bus_RdAck -- Active high Read Data qualifier from the IP -- IP2Bus_Error -- Error signal from the IP ------------------------------------------------------------------------------- entity slave_attachment is generic ( C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := ( X"0000_0000_7000_0000", -- IP user0 base address X"0000_0000_7000_00FF", -- IP user0 high address X"0000_0000_7000_0100", -- IP user1 base address X"0000_0000_7000_01FF" -- IP user1 high address ); C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := ( 1, -- User0 CE Number 8 -- User1 CE Number ); C_IPIF_ABUS_WIDTH : integer := 32; C_IPIF_DBUS_WIDTH : integer := 32; C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF"; C_USE_WSTRB : integer := 0; C_DPHASE_TIMEOUT : integer range 0 to 512 := 16; C_FAMILY : string := "virtex6" ); port( -- AXI signals S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; S_AXI_AWADDR : in std_logic_vector (C_IPIF_ABUS_WIDTH-1 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_AWREADY : out std_logic; S_AXI_WDATA : in std_logic_vector (C_IPIF_DBUS_WIDTH-1 downto 0); S_AXI_WSTRB : in std_logic_vector ((C_IPIF_DBUS_WIDTH/8)-1 downto 0); S_AXI_WVALID : in std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector (C_IPIF_ABUS_WIDTH-1 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector (C_IPIF_DBUS_WIDTH-1 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_RREADY : in std_logic; -- Controls to the IP/IPIF modules Bus2IP_Clk : out std_logic; Bus2IP_Resetn : out std_logic; Bus2IP_Addr : out std_logic_vector (C_IPIF_ABUS_WIDTH-1 downto 0); Bus2IP_RNW : out std_logic; Bus2IP_BE : out std_logic_vector (((C_IPIF_DBUS_WIDTH/8) - 1) downto 0); Bus2IP_CS : out std_logic_vector (((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0); Bus2IP_RdCE : out std_logic_vector ((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0); Bus2IP_WrCE : out std_logic_vector ((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0); Bus2IP_Data : out std_logic_vector ((C_IPIF_DBUS_WIDTH-1) downto 0); IP2Bus_Data : in std_logic_vector ((C_IPIF_DBUS_WIDTH-1) downto 0); IP2Bus_WrAck : in std_logic; IP2Bus_RdAck : in std_logic; IP2Bus_Error : in std_logic ); end entity slave_attachment; ------------------------------------------------------------------------------- architecture imp of slave_attachment is ------------------------------------------------------------------------------- -- Get_Addr_Bits: Function Declarations ------------------------------------------------------------------------------- function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is variable i : integer := 0; begin for i in 31 downto 0 loop if y(i)='1' then return (i); end if; end loop; return -1; end function Get_Addr_Bits; ------------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2; constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY); constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE); constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1; constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto (C_ADDR_DECODE_BITS+1)) := (others=>'0'); ------------------------------------------------------------------------------- -- Signal and Type Declarations ------------------------------------------------------------------------------- signal s_axi_bvalid_i : std_logic:= '0'; signal s_axi_arready_i : std_logic; signal s_axi_rvalid_i : std_logic:= '0'; signal start : std_logic; -- Intermediate IPIC signals signal bus2ip_addr_i : std_logic_vector ((C_IPIF_ABUS_WIDTH-1) downto 0); signal timeout : std_logic; signal rd_done,wr_done : std_logic; signal rst : std_logic; signal temp_i : std_logic; type BUS_ACCESS_STATES is ( SM_IDLE, SM_READ, SM_WRITE, SM_RESP ); signal state : BUS_ACCESS_STATES; signal cs_for_gaps_i : std_logic; signal bus2ip_rnw_i : std_logic; signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0'); signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0'); signal s_axi_rdata_i : std_logic_vector (C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0'); ------------------------------------------------------------------------------- -- begin the architecture logic ------------------------------------------------------------------------------- begin ------------------------------------------------------------------------------- -- Address registered ------------------------------------------------------------------------------- Bus2IP_Clk <= S_AXI_ACLK; Bus2IP_Resetn <= S_AXI_ARESETN; bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1' else '0'; BUS2IP_RNW <= bus2ip_rnw_i; Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0')) else (others => '1'); Bus2IP_Data <= S_AXI_WDATA; Bus2IP_Addr <= bus2ip_addr_i; -- For AXI Lite interface, interconnect will duplicate the addresses on both the -- read and write channel. so onlyone address is used for decoding as well as -- passing it to IP. bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0) when (S_AXI_ARVALID='1') else ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0); -------------------------------------------------------------------------------- -- start signal will be used to latch the incoming address start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID)) when (state = SM_IDLE) else '0'; -- x_done signals are used to release the hold from AXI, it will generate "ready" -- signal on the read and write address channels. rd_done <= IP2Bus_RdAck or timeout; wr_done <= IP2Bus_WrAck or timeout; temp_i <= rd_done or wr_done; ------------------------------------------------------------------------------- -- Address Decoder Component Instance -- -- This component decodes the specified base address pairs and outputs the -- specified number of chip enables and the target bus size. ------------------------------------------------------------------------------- I_DECODER : entity work.address_decoder generic map ( C_BUS_AWIDTH => C_NUM_DECODE_BITS, C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE, C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY, C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY, C_FAMILY => "nofamily" ) port map ( Bus_clk => S_AXI_ACLK, Bus_rst => S_AXI_ARESETN, Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0), Address_Valid_Erly => start, Bus_RNW => S_AXI_ARVALID, Bus_RNW_Erly => S_AXI_ARVALID, CS_CE_ld_enable => start, Clear_CS_CE_Reg => temp_i, RW_CE_ld_enable => start, CS_for_gaps => open, -- Decode output signals CS_Out => Bus2IP_CS, RdCE_Out => Bus2IP_RdCE, WrCE_Out => Bus2IP_WrCE ); -- REGISTERING_RESET_P: Invert the reset coming from AXI ----------------------- REGISTERING_RESET_P : process (S_AXI_ACLK) is begin if S_AXI_ACLK'event and S_AXI_ACLK = '1' then rst <= not S_AXI_ARESETN; end if; end process REGISTERING_RESET_P; ------------------------------------------------------------------------------- -- AXI Transaction Controller ------------------------------------------------------------------------------- -- Access_Control: As per suggestion to optimize the core, the below state machine -- is re-coded. Latches are removed from original suggestions Access_Control : process (S_AXI_ACLK) is begin if S_AXI_ACLK'event and S_AXI_ACLK = '1' then if rst = '1' then state <= SM_IDLE; else case state is when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write state <= SM_READ; elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then state <= SM_WRITE; else state <= SM_IDLE; end if; when SM_READ => if rd_done = '1' then state <= SM_RESP; else state <= SM_READ; end if; when SM_WRITE=> if (wr_done = '1') then state <= SM_RESP; else state <= SM_WRITE; end if; when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or (s_axi_rvalid_i and S_AXI_RREADY)) = '1' then state <= SM_IDLE; else state <= SM_RESP; end if; -- coverage off when others => state <= SM_IDLE; -- coverage on end case; end if; end if; end process Access_Control; ------------------------------------------------------------------------------- -- AXI Transaction Controller signals registered ------------------------------------------------------------------------------- -- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI ----------------------- S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is begin if S_AXI_ACLK'event and S_AXI_ACLK = '1' then if (rst = '1') then s_axi_rresp_i <= (others => '0'); s_axi_rdata_i <= (others => '0'); elsif state = SM_READ then s_axi_rresp_i <= (IP2Bus_Error) & '0'; s_axi_rdata_i <= IP2Bus_Data; end if; end if; end process S_AXI_RDATA_RESP_P; S_AXI_RRESP <= s_axi_rresp_i; S_AXI_RDATA <= s_axi_rdata_i; ----------------------------- -- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel ---------------------- S_AXI_RVALID_I_P : process (S_AXI_ACLK) is begin if S_AXI_ACLK'event and S_AXI_ACLK = '1' then if (rst = '1') then s_axi_rvalid_i <= '0'; elsif ((state = SM_READ) and rd_done = '1') then s_axi_rvalid_i <= '1'; elsif (S_AXI_RREADY = '1') then s_axi_rvalid_i <= '0'; end if; end if; end process S_AXI_RVALID_I_P; -- -- S_AXI_BRESP_P: Below process provides logic for write response -- ----------------- S_AXI_BRESP_P : process (S_AXI_ACLK) is begin if S_AXI_ACLK'event and S_AXI_ACLK = '1' then if (rst = '1') then s_axi_bresp_i <= (others => '0'); elsif (state = SM_WRITE) then s_axi_bresp_i <= (IP2Bus_Error) & '0'; end if; end if; end process S_AXI_BRESP_P; S_AXI_BRESP <= s_axi_bresp_i; --S_AXI_BVALID_I_P: below process provides logic for valid write response signal ------------------- S_AXI_BVALID_I_P : process (S_AXI_ACLK) is begin if S_AXI_ACLK'event and S_AXI_ACLK = '1' then if rst = '1' then s_axi_bvalid_i <= '0'; elsif ((state = SM_WRITE) and wr_done = '1') then s_axi_bvalid_i <= '1'; elsif (S_AXI_BREADY = '1') then s_axi_bvalid_i <= '0'; end if; end if; end process S_AXI_BVALID_I_P; ----------------------------------------------------------------------------- -- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero. -------------- INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT)); signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0); -- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout -- condition to be captured as a carry into this "extra" bit. begin DPTO_CNT_P : process (S_AXI_ACLK) is begin if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then if ((state = SM_IDLE) or (state = SM_RESP)) then dpto_cnt <= (others=>'0'); else dpto_cnt <= dpto_cnt + 1; end if; end if; end process DPTO_CNT_P; timeout <= dpto_cnt(COUNTER_WIDTH); end generate INCLUDE_DPHASE_TIMER; EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate timeout <= '0'; end generate EXCLUDE_DPHASE_TIMER; ----------------------------------------------------------------------------- S_AXI_BVALID <= s_axi_bvalid_i; S_AXI_RVALID <= s_axi_rvalid_i; ----------------------------------------------------------------------------- S_AXI_ARREADY <= rd_done; S_AXI_AWREADY <= wr_done; S_AXI_WREADY <= wr_done; ------------------------------------------------------------------------------- end imp;	mit
MarkBlanco/FPGA_Sandbox	RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ipshared/1288/zed_audio_ctrl.srcs/sources_1/imports/i2s_audio/slave_attachment.vhd	7	21369	------------------------------------------------------------------- -- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. -- -- -- -- This file contains confidential and proprietary information -- -- of Xilinx, Inc. and is protected under U.S. and -- -- international copyright and other intellectual property -- -- laws. -- -- -- -- DISCLAIMER -- -- This disclaimer is not a license and does not grant any -- -- rights to the materials distributed herewith. Except as -- -- otherwise provided in a valid license issued to you by -- -- Xilinx, and to the maximum extent permitted by applicable -- -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- -- (2) Xilinx shall not be liable (whether in contract or tort, -- -- including negligence, or under any other theory of -- -- liability) for any loss or damage of any kind or nature -- -- related to, arising under or in connection with these -- -- materials, including for any direct, or any indirect, -- -- special, incidental, or consequential loss or damage -- -- (including loss of data, profits, goodwill, or any type of -- -- loss or damage suffered as a result of any action brought -- -- by a third party) even if such damage or loss was -- -- reasonably foreseeable or Xilinx had been advised of the -- -- possibility of the same. -- -- -- -- CRITICAL APPLICATIONS -- -- Xilinx products are not designed or intended to be fail- -- -- safe, or for use in any application requiring fail-safe -- -- performance, such as life-support or safety devices or -- -- systems, Class III medical devices, nuclear facilities, -- -- applications related to the deployment of airbags, or any -- -- other applications that could lead to death, personal -- -- injury, or severe property or environmental damage -- -- (individually and collectively, "Critical -- -- Applications"). Customer assumes the sole risk and -- -- liability of any use of Xilinx products in Critical -- -- Applications, subject only to applicable laws and -- -- regulations governing limitations on product liability. -- -- -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- -- PART OF THIS FILE AT ALL TIMES. -- ------------------------------------------------------------------- -- ************************************************************************ -- ------------------------------------------------------------------------------- -- Filename: slave_attachment.vhd -- Version: v1.01.a -- Description: AXI slave attachment supporting single transfers ------------------------------------------------------------------------------- -- Structure: This section shows the hierarchical structure of axi_lite_ipif. -- -- --axi_lite_ipif.vhd -- --slave_attachment.vhd -- --address_decoder.vhd ------------------------------------------------------------------------------- -- Author: BSB -- -- History: -- -- BSB 05/20/10 -- First version -- ~~~~~~ -- - Created the first version v1.00.a -- ^^^^^^ -- ~~~~~~ -- SK 06/09/10 -- updated to reduce the utilization -- 1. State machine is re-designed -- 2. R and B channels are registered and AW, AR, W channels are non-registered -- 3. Address decoding is done only for the required address bits and not complete -- 32 bits -- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux -- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg -- function. -- ^^^^^^ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- access_cs machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_cmb" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port "_i" -- device pins: "_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_misc.all; use work.common_types.all; ------------------------------------------------------------------------------- -- Definition of Generics ------------------------------------------------------------------------------- -- C_IPIF_ABUS_WIDTH -- IPIF Address bus width -- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width -- C_S_AXI_MIN_SIZE -- Minimum address range of the IP -- C_USE_WSTRB -- Use write strobs or not -- C_DPHASE_TIMEOUT -- Data phase time out counter -- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range -- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range -- C_FAMILY -- Target FPGA family ------------------------------------------------------------------------------- -- Definition of Ports ------------------------------------------------------------------------------- -- S_AXI_ACLK -- AXI Clock -- S_AXI_ARESET -- AXI Reset -- S_AXI_AWADDR -- AXI Write address -- S_AXI_AWVALID -- Write address valid -- S_AXI_AWREADY -- Write address ready -- S_AXI_WDATA -- Write data -- S_AXI_WSTRB -- Write strobes -- S_AXI_WVALID -- Write valid -- S_AXI_WREADY -- Write ready -- S_AXI_BRESP -- Write response -- S_AXI_BVALID -- Write response valid -- S_AXI_BREADY -- Response ready -- S_AXI_ARADDR -- Read address -- S_AXI_ARVALID -- Read address valid -- S_AXI_ARREADY -- Read address ready -- S_AXI_RDATA -- Read data -- S_AXI_RRESP -- Read response -- S_AXI_RVALID -- Read valid -- S_AXI_RREADY -- Read ready -- Bus2IP_Clk -- Synchronization clock provided to User IP -- Bus2IP_Reset -- Active high reset for use by the User IP -- Bus2IP_Addr -- Desired address of read or write operation -- Bus2IP_RNW -- Read or write indicator for the transaction -- Bus2IP_BE -- Byte enables for the data bus -- Bus2IP_CS -- Chip select for the transcations -- Bus2IP_RdCE -- Chip enables for the read -- Bus2IP_WrCE -- Chip enables for the write -- Bus2IP_Data -- Write data bus to the User IP -- IP2Bus_Data -- Input Read Data bus from the User IP -- IP2Bus_WrAck -- Active high Write Data qualifier from the IP -- IP2Bus_RdAck -- Active high Read Data qualifier from the IP -- IP2Bus_Error -- Error signal from the IP ------------------------------------------------------------------------------- entity slave_attachment is generic ( C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := ( X"0000_0000_7000_0000", -- IP user0 base address X"0000_0000_7000_00FF", -- IP user0 high address X"0000_0000_7000_0100", -- IP user1 base address X"0000_0000_7000_01FF" -- IP user1 high address ); C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := ( 1, -- User0 CE Number 8 -- User1 CE Number ); C_IPIF_ABUS_WIDTH : integer := 32; C_IPIF_DBUS_WIDTH : integer := 32; C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF"; C_USE_WSTRB : integer := 0; C_DPHASE_TIMEOUT : integer range 0 to 512 := 16; C_FAMILY : string := "virtex6" ); port( -- AXI signals S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; S_AXI_AWADDR : in std_logic_vector (C_IPIF_ABUS_WIDTH-1 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_AWREADY : out std_logic; S_AXI_WDATA : in std_logic_vector (C_IPIF_DBUS_WIDTH-1 downto 0); S_AXI_WSTRB : in std_logic_vector ((C_IPIF_DBUS_WIDTH/8)-1 downto 0); S_AXI_WVALID : in std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector (C_IPIF_ABUS_WIDTH-1 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector (C_IPIF_DBUS_WIDTH-1 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_RREADY : in std_logic; -- Controls to the IP/IPIF modules Bus2IP_Clk : out std_logic; Bus2IP_Resetn : out std_logic; Bus2IP_Addr : out std_logic_vector (C_IPIF_ABUS_WIDTH-1 downto 0); Bus2IP_RNW : out std_logic; Bus2IP_BE : out std_logic_vector (((C_IPIF_DBUS_WIDTH/8) - 1) downto 0); Bus2IP_CS : out std_logic_vector (((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0); Bus2IP_RdCE : out std_logic_vector ((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0); Bus2IP_WrCE : out std_logic_vector ((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0); Bus2IP_Data : out std_logic_vector ((C_IPIF_DBUS_WIDTH-1) downto 0); IP2Bus_Data : in std_logic_vector ((C_IPIF_DBUS_WIDTH-1) downto 0); IP2Bus_WrAck : in std_logic; IP2Bus_RdAck : in std_logic; IP2Bus_Error : in std_logic ); end entity slave_attachment; ------------------------------------------------------------------------------- architecture imp of slave_attachment is ------------------------------------------------------------------------------- -- Get_Addr_Bits: Function Declarations ------------------------------------------------------------------------------- function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is variable i : integer := 0; begin for i in 31 downto 0 loop if y(i)='1' then return (i); end if; end loop; return -1; end function Get_Addr_Bits; ------------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2; constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY); constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE); constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1; constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto (C_ADDR_DECODE_BITS+1)) := (others=>'0'); ------------------------------------------------------------------------------- -- Signal and Type Declarations ------------------------------------------------------------------------------- signal s_axi_bvalid_i : std_logic:= '0'; signal s_axi_arready_i : std_logic; signal s_axi_rvalid_i : std_logic:= '0'; signal start : std_logic; -- Intermediate IPIC signals signal bus2ip_addr_i : std_logic_vector ((C_IPIF_ABUS_WIDTH-1) downto 0); signal timeout : std_logic; signal rd_done,wr_done : std_logic; signal rst : std_logic; signal temp_i : std_logic; type BUS_ACCESS_STATES is ( SM_IDLE, SM_READ, SM_WRITE, SM_RESP ); signal state : BUS_ACCESS_STATES; signal cs_for_gaps_i : std_logic; signal bus2ip_rnw_i : std_logic; signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0'); signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0'); signal s_axi_rdata_i : std_logic_vector (C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0'); ------------------------------------------------------------------------------- -- begin the architecture logic ------------------------------------------------------------------------------- begin ------------------------------------------------------------------------------- -- Address registered ------------------------------------------------------------------------------- Bus2IP_Clk <= S_AXI_ACLK; Bus2IP_Resetn <= S_AXI_ARESETN; bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1' else '0'; BUS2IP_RNW <= bus2ip_rnw_i; Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0')) else (others => '1'); Bus2IP_Data <= S_AXI_WDATA; Bus2IP_Addr <= bus2ip_addr_i; -- For AXI Lite interface, interconnect will duplicate the addresses on both the -- read and write channel. so onlyone address is used for decoding as well as -- passing it to IP. bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0) when (S_AXI_ARVALID='1') else ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0); -------------------------------------------------------------------------------- -- start signal will be used to latch the incoming address start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID)) when (state = SM_IDLE) else '0'; -- x_done signals are used to release the hold from AXI, it will generate "ready" -- signal on the read and write address channels. rd_done <= IP2Bus_RdAck or timeout; wr_done <= IP2Bus_WrAck or timeout; temp_i <= rd_done or wr_done; ------------------------------------------------------------------------------- -- Address Decoder Component Instance -- -- This component decodes the specified base address pairs and outputs the -- specified number of chip enables and the target bus size. ------------------------------------------------------------------------------- I_DECODER : entity work.address_decoder generic map ( C_BUS_AWIDTH => C_NUM_DECODE_BITS, C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE, C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY, C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY, C_FAMILY => "nofamily" ) port map ( Bus_clk => S_AXI_ACLK, Bus_rst => S_AXI_ARESETN, Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0), Address_Valid_Erly => start, Bus_RNW => S_AXI_ARVALID, Bus_RNW_Erly => S_AXI_ARVALID, CS_CE_ld_enable => start, Clear_CS_CE_Reg => temp_i, RW_CE_ld_enable => start, CS_for_gaps => open, -- Decode output signals CS_Out => Bus2IP_CS, RdCE_Out => Bus2IP_RdCE, WrCE_Out => Bus2IP_WrCE ); -- REGISTERING_RESET_P: Invert the reset coming from AXI ----------------------- REGISTERING_RESET_P : process (S_AXI_ACLK) is begin if S_AXI_ACLK'event and S_AXI_ACLK = '1' then rst <= not S_AXI_ARESETN; end if; end process REGISTERING_RESET_P; ------------------------------------------------------------------------------- -- AXI Transaction Controller ------------------------------------------------------------------------------- -- Access_Control: As per suggestion to optimize the core, the below state machine -- is re-coded. Latches are removed from original suggestions Access_Control : process (S_AXI_ACLK) is begin if S_AXI_ACLK'event and S_AXI_ACLK = '1' then if rst = '1' then state <= SM_IDLE; else case state is when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write state <= SM_READ; elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then state <= SM_WRITE; else state <= SM_IDLE; end if; when SM_READ => if rd_done = '1' then state <= SM_RESP; else state <= SM_READ; end if; when SM_WRITE=> if (wr_done = '1') then state <= SM_RESP; else state <= SM_WRITE; end if; when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or (s_axi_rvalid_i and S_AXI_RREADY)) = '1' then state <= SM_IDLE; else state <= SM_RESP; end if; -- coverage off when others => state <= SM_IDLE; -- coverage on end case; end if; end if; end process Access_Control; ------------------------------------------------------------------------------- -- AXI Transaction Controller signals registered ------------------------------------------------------------------------------- -- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI ----------------------- S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is begin if S_AXI_ACLK'event and S_AXI_ACLK = '1' then if (rst = '1') then s_axi_rresp_i <= (others => '0'); s_axi_rdata_i <= (others => '0'); elsif state = SM_READ then s_axi_rresp_i <= (IP2Bus_Error) & '0'; s_axi_rdata_i <= IP2Bus_Data; end if; end if; end process S_AXI_RDATA_RESP_P; S_AXI_RRESP <= s_axi_rresp_i; S_AXI_RDATA <= s_axi_rdata_i; ----------------------------- -- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel ---------------------- S_AXI_RVALID_I_P : process (S_AXI_ACLK) is begin if S_AXI_ACLK'event and S_AXI_ACLK = '1' then if (rst = '1') then s_axi_rvalid_i <= '0'; elsif ((state = SM_READ) and rd_done = '1') then s_axi_rvalid_i <= '1'; elsif (S_AXI_RREADY = '1') then s_axi_rvalid_i <= '0'; end if; end if; end process S_AXI_RVALID_I_P; -- -- S_AXI_BRESP_P: Below process provides logic for write response -- ----------------- S_AXI_BRESP_P : process (S_AXI_ACLK) is begin if S_AXI_ACLK'event and S_AXI_ACLK = '1' then if (rst = '1') then s_axi_bresp_i <= (others => '0'); elsif (state = SM_WRITE) then s_axi_bresp_i <= (IP2Bus_Error) & '0'; end if; end if; end process S_AXI_BRESP_P; S_AXI_BRESP <= s_axi_bresp_i; --S_AXI_BVALID_I_P: below process provides logic for valid write response signal ------------------- S_AXI_BVALID_I_P : process (S_AXI_ACLK) is begin if S_AXI_ACLK'event and S_AXI_ACLK = '1' then if rst = '1' then s_axi_bvalid_i <= '0'; elsif ((state = SM_WRITE) and wr_done = '1') then s_axi_bvalid_i <= '1'; elsif (S_AXI_BREADY = '1') then s_axi_bvalid_i <= '0'; end if; end if; end process S_AXI_BVALID_I_P; ----------------------------------------------------------------------------- -- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero. -------------- INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT)); signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0); -- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout -- condition to be captured as a carry into this "extra" bit. begin DPTO_CNT_P : process (S_AXI_ACLK) is begin if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then if ((state = SM_IDLE) or (state = SM_RESP)) then dpto_cnt <= (others=>'0'); else dpto_cnt <= dpto_cnt + 1; end if; end if; end process DPTO_CNT_P; timeout <= dpto_cnt(COUNTER_WIDTH); end generate INCLUDE_DPHASE_TIMER; EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate timeout <= '0'; end generate EXCLUDE_DPHASE_TIMER; ----------------------------------------------------------------------------- S_AXI_BVALID <= s_axi_bvalid_i; S_AXI_RVALID <= s_axi_rvalid_i; ----------------------------------------------------------------------------- S_AXI_ARREADY <= rd_done; S_AXI_AWREADY <= wr_done; S_AXI_WREADY <= wr_done; ------------------------------------------------------------------------------- end imp;	mit
VerkhovtsovPavel/BSUIR_Labs	Labs/POCP/POCP-6/src/RegFile.vhd	2	1417	library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; entity RegFile is generic ( INITREG: std_logic_vector := "0000"; a: integer := 2); port ( INIT: in std_logic; WDP: in std_logic_vector(INITREG'range); WA: in std_logic_vector(a-1 downto 0); RA: in std_logic_vector(a-1 downto 0); WE: in std_logic; RDP: out std_logic_vector(INITREG'range)); end RegFile; architecture Beh of RegFile is component RegN is generic ( initreg: std_logic_vector := "1001"); port ( Din: in std_logic_vector(initreg'range); EN: in std_logic; INIT: in std_logic; CLK: in std_logic; OE: in std_logic; Dout: out std_logic_vector(initreg'range)); end component; signal wen: std_logic_vector(2a-1 downto 0); signal ren: std_logic_vector(2a-1 downto 0); signal readd: std_logic_vector (initreg'range); Begin WAD: process (WA) begin for i in 0 to 2a - 1 loop if i = conv_integer(WA) then wen (i) <= '1'; else wen (i) <= '0'; end if; end loop; end process; RAD: process (RA) begin for i in 0 to 2a - 1 loop if i = conv_integer(RA) then ren (i) <= '1'; else ren (i) <= '0'; end if; end loop; end process; Regi: for i in 2**a - 1 downto 0 generate Regi: Regn generic map (initreg) port map (WDP, wen(i), init, we, ren(i), readd); end generate; RDP <= readd; End Beh;	mit
MarkBlanco/FPGA_Sandbox	RecComp/Lab3/lab3_project_default.xpr/project_1/project_1.ipdefs/ip_0/hdl/vhdl/convolve_kernel_fbkb.vhd	1	3167	-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2017.2 -- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. -- -- ============================================================== Library ieee; use ieee.std_logic_1164.all; entity convolve_kernel_fbkb is generic ( ID : integer := 0; NUM_STAGE : integer := 5; din0_WIDTH : integer := 32; din1_WIDTH : integer := 32; dout_WIDTH : integer := 32 ); port ( clk : in std_logic; reset : in std_logic; ce : in std_logic; din0 : in std_logic_vector(din0_WIDTH-1 downto 0); din1 : in std_logic_vector(din1_WIDTH-1 downto 0); dout : out std_logic_vector(dout_WIDTH-1 downto 0) ); end entity; architecture arch of convolve_kernel_fbkb is --------------------- Component --------------------- component convolve_kernel_ap_fadd_3_full_dsp_32 is port ( aclk : in std_logic; aclken : in std_logic; s_axis_a_tvalid : in std_logic; s_axis_a_tdata : in std_logic_vector(31 downto 0); s_axis_b_tvalid : in std_logic; s_axis_b_tdata : in std_logic_vector(31 downto 0); m_axis_result_tvalid : out std_logic; m_axis_result_tdata : out std_logic_vector(31 downto 0) ); end component; --------------------- Local signal ------------------ signal aclk : std_logic; signal aclken : std_logic; signal a_tvalid : std_logic; signal a_tdata : std_logic_vector(31 downto 0); signal b_tvalid : std_logic; signal b_tdata : std_logic_vector(31 downto 0); signal r_tvalid : std_logic; signal r_tdata : std_logic_vector(31 downto 0); signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0); signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0); begin --------------------- Instantiation ----------------- convolve_kernel_ap_fadd_3_full_dsp_32_u : component convolve_kernel_ap_fadd_3_full_dsp_32 port map ( aclk => aclk, aclken => aclken, s_axis_a_tvalid => a_tvalid, s_axis_a_tdata => a_tdata, s_axis_b_tvalid => b_tvalid, s_axis_b_tdata => b_tdata, m_axis_result_tvalid => r_tvalid, m_axis_result_tdata => r_tdata ); --------------------- Assignment -------------------- aclk <= clk; aclken <= ce; a_tvalid <= '1'; a_tdata <= din0_buf1; b_tvalid <= '1'; b_tdata <= din1_buf1; dout <= r_tdata; --------------------- Input buffer ------------------ process (clk) begin if clk'event and clk = '1' then if ce = '1' then din0_buf1 <= din0; din1_buf1 <= din1; end if; end if; end process; end architecture;	mit
VerkhovtsovPavel/BSUIR_Labs	Labs/POCP/POCP-6/src/FIFO.vhd	1	1506	library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; entity FIFO is generic( -- øèíà àäðåñà m: integer := 2; -- øèíà äàííûõ n: integer := 2 ); port ( -- ñèíõðîíèçàöèÿ CLK: in std_logic; -- ñèãíàë óïðàâëåíèÿ ÷òåíèåì/çàïèñüþ WR: in std_logic; -- äâóíàïðàâëåííàÿ øèíà äàííûõ DB: inout std_logic_vector (n-1 downto 0); EMPTY: out std_logic; FULL: out std_logic ); end FIFO; architecture Beh of FIFO is -- òèï õðàíèìîãî ñëîâà subtype word is std_logic_vector (n-1 downto 0); -- íåïîñðåäñòâåííî òèï õðàíèëèùà äàííûõ type tram is array (0 to 2m - 1) of word; signal sRAM: tram; signal head: integer := 0; constant Limit: integer := 2 m -1; Begin SH: process (CLK) begin if rising_edge(CLK) then if (WR = '0') then if (head <= Limit) then head <= head + 1; end if; elsif (WR = '1') then if (head > 0) then head <= head - 1; end if; end if; end if; if (head = 0) then empty <= '1'; full <= '0'; elsif (head = Limit + 1) then empty <= '0'; full <= '1'; else empty <= '0'; full <= '0'; end if; end process; WRP: process (head) begin if WR = '0' then if (head > 0 and head <= Limit + 1) then sRAM(head - 1) <= DB; end if; end if; end process; RDP: process(head) begin if WR = '1' then if (head >= 0 and head <= Limit) then DB <= sRAM (head); end if; else DB <= (others => 'Z'); end if; end process; end Beh;	mit
MarkBlanco/FPGA_Sandbox	RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_bram_ctrl_0_bram_0/synth/zqynq_lab_1_design_axi_bram_ctrl_0_bram_0.vhd	1	15765	-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3 -- IP Revision: 6 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY blk_mem_gen_v8_3_6; USE blk_mem_gen_v8_3_6.blk_mem_gen_v8_3_6; ENTITY zqynq_lab_1_design_axi_bram_ctrl_0_bram_0 IS PORT ( clka : IN STD_LOGIC; rsta : IN STD_LOGIC; ena : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); clkb : IN STD_LOGIC; rstb : IN STD_LOGIC; enb : IN STD_LOGIC; web : IN STD_LOGIC_VECTOR(3 DOWNTO 0); addrb : IN STD_LOGIC_VECTOR(31 DOWNTO 0); dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0); doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END zqynq_lab_1_design_axi_bram_ctrl_0_bram_0; ARCHITECTURE zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_arch OF zqynq_lab_1_design_axi_bram_ctrl_0_bram_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_arch: ARCHITECTURE IS "yes"; COMPONENT blk_mem_gen_v8_3_6 IS GENERIC ( C_FAMILY : STRING; C_XDEVICEFAMILY : STRING; C_ELABORATION_DIR : STRING; C_INTERFACE_TYPE : INTEGER; C_AXI_TYPE : INTEGER; C_AXI_SLAVE_TYPE : INTEGER; C_USE_BRAM_BLOCK : INTEGER; C_ENABLE_32BIT_ADDRESS : INTEGER; C_CTRL_ECC_ALGO : STRING; C_HAS_AXI_ID : INTEGER; C_AXI_ID_WIDTH : INTEGER; C_MEM_TYPE : INTEGER; C_BYTE_SIZE : INTEGER; C_ALGORITHM : INTEGER; C_PRIM_TYPE : INTEGER; C_LOAD_INIT_FILE : INTEGER; C_INIT_FILE_NAME : STRING; C_INIT_FILE : STRING; C_USE_DEFAULT_DATA : INTEGER; C_DEFAULT_DATA : STRING; C_HAS_RSTA : INTEGER; C_RST_PRIORITY_A : STRING; C_RSTRAM_A : INTEGER; C_INITA_VAL : STRING; C_HAS_ENA : INTEGER; C_HAS_REGCEA : INTEGER; C_USE_BYTE_WEA : INTEGER; C_WEA_WIDTH : INTEGER; C_WRITE_MODE_A : STRING; C_WRITE_WIDTH_A : INTEGER; C_READ_WIDTH_A : INTEGER; C_WRITE_DEPTH_A : INTEGER; C_READ_DEPTH_A : INTEGER; C_ADDRA_WIDTH : INTEGER; C_HAS_RSTB : INTEGER; C_RST_PRIORITY_B : STRING; C_RSTRAM_B : INTEGER; C_INITB_VAL : STRING; C_HAS_ENB : INTEGER; C_HAS_REGCEB : INTEGER; C_USE_BYTE_WEB : INTEGER; C_WEB_WIDTH : INTEGER; C_WRITE_MODE_B : STRING; C_WRITE_WIDTH_B : INTEGER; C_READ_WIDTH_B : INTEGER; C_WRITE_DEPTH_B : INTEGER; C_READ_DEPTH_B : INTEGER; C_ADDRB_WIDTH : INTEGER; C_HAS_MEM_OUTPUT_REGS_A : INTEGER; C_HAS_MEM_OUTPUT_REGS_B : INTEGER; C_HAS_MUX_OUTPUT_REGS_A : INTEGER; C_HAS_MUX_OUTPUT_REGS_B : INTEGER; C_MUX_PIPELINE_STAGES : INTEGER; C_HAS_SOFTECC_INPUT_REGS_A : INTEGER; C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER; C_USE_SOFTECC : INTEGER; C_USE_ECC : INTEGER; C_EN_ECC_PIPE : INTEGER; C_HAS_INJECTERR : INTEGER; C_SIM_COLLISION_CHECK : STRING; C_COMMON_CLK : INTEGER; C_DISABLE_WARN_BHV_COLL : INTEGER; C_EN_SLEEP_PIN : INTEGER; C_USE_URAM : INTEGER; C_EN_RDADDRA_CHG : INTEGER; C_EN_RDADDRB_CHG : INTEGER; C_EN_DEEPSLEEP_PIN : INTEGER; C_EN_SHUTDOWN_PIN : INTEGER; C_EN_SAFETY_CKT : INTEGER; C_DISABLE_WARN_BHV_RANGE : INTEGER; C_COUNT_36K_BRAM : STRING; C_COUNT_18K_BRAM : STRING; C_EST_POWER_SUMMARY : STRING ); PORT ( clka : IN STD_LOGIC; rsta : IN STD_LOGIC; ena : IN STD_LOGIC; regcea : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); clkb : IN STD_LOGIC; rstb : IN STD_LOGIC; enb : IN STD_LOGIC; regceb : IN STD_LOGIC; web : IN STD_LOGIC_VECTOR(3 DOWNTO 0); addrb : IN STD_LOGIC_VECTOR(31 DOWNTO 0); dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0); doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); injectsbiterr : IN STD_LOGIC; injectdbiterr : IN STD_LOGIC; eccpipece : IN STD_LOGIC; sbiterr : OUT STD_LOGIC; dbiterr : OUT STD_LOGIC; rdaddrecc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); sleep : IN STD_LOGIC; deepsleep : IN STD_LOGIC; shutdown : IN STD_LOGIC; rsta_busy : OUT STD_LOGIC; rstb_busy : OUT STD_LOGIC; s_aclk : IN STD_LOGIC; s_aresetn : IN STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; s_axi_injectsbiterr : IN STD_LOGIC; s_axi_injectdbiterr : IN STD_LOGIC; s_axi_sbiterr : OUT STD_LOGIC; s_axi_dbiterr : OUT STD_LOGIC; s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT blk_mem_gen_v8_3_6; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_6,Vivado 2017.2"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_arch : ARCHITECTURE IS "zqynq_lab_1_design_axi_bram_ctrl_0_bram_0,blk_mem_gen_v8_3_6,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_arch: ARCHITECTURE IS "zqynq_lab_1_design_axi_bram_ctrl_0_bram_0,blk_mem_gen_v8_3_6,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=1,C_ENABLE_32BIT_ADDRESS=1,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=2,C_BYTE_SIZE=8,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=" & "0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=NONE,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=1,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=1,C_WEA_WIDTH=4,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=32,C_READ_WIDTH_A=32,C_WRITE_DEPTH_A=16384,C_READ_DEPTH_A=16384,C_ADDRA_WIDTH=32,C_HAS_RSTB=1,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=1,C_WEB_WIDTH=4,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=32,C" & "_READ_WIDTH_B=32,C_WRITE_DEPTH_B=16384,C_READ_DEPTH_B=16384,C_ADDRB_WIDTH=32,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=" & "0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=16,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 20.388 mW}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK"; ATTRIBUTE X_INTERFACE_INFO OF rsta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST"; ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN"; ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE"; ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR"; ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN"; ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT"; ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK"; ATTRIBUTE X_INTERFACE_INFO OF rstb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB RST"; ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN"; ATTRIBUTE X_INTERFACE_INFO OF web: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE"; ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR"; ATTRIBUTE X_INTERFACE_INFO OF dinb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN"; ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT"; BEGIN U0 : blk_mem_gen_v8_3_6 GENERIC MAP ( C_FAMILY => "zynq", C_XDEVICEFAMILY => "zynq", C_ELABORATION_DIR => "./", C_INTERFACE_TYPE => 0, C_AXI_TYPE => 1, C_AXI_SLAVE_TYPE => 0, C_USE_BRAM_BLOCK => 1, C_ENABLE_32BIT_ADDRESS => 1, C_CTRL_ECC_ALGO => "NONE", C_HAS_AXI_ID => 0, C_AXI_ID_WIDTH => 4, C_MEM_TYPE => 2, C_BYTE_SIZE => 8, C_ALGORITHM => 1, C_PRIM_TYPE => 1, C_LOAD_INIT_FILE => 0, C_INIT_FILE_NAME => "no_coe_file_loaded", C_INIT_FILE => "NONE", C_USE_DEFAULT_DATA => 0, C_DEFAULT_DATA => "0", C_HAS_RSTA => 1, C_RST_PRIORITY_A => "CE", C_RSTRAM_A => 0, C_INITA_VAL => "0", C_HAS_ENA => 1, C_HAS_REGCEA => 0, C_USE_BYTE_WEA => 1, C_WEA_WIDTH => 4, C_WRITE_MODE_A => "WRITE_FIRST", C_WRITE_WIDTH_A => 32, C_READ_WIDTH_A => 32, C_WRITE_DEPTH_A => 16384, C_READ_DEPTH_A => 16384, C_ADDRA_WIDTH => 32, C_HAS_RSTB => 1, C_RST_PRIORITY_B => "CE", C_RSTRAM_B => 0, C_INITB_VAL => "0", C_HAS_ENB => 1, C_HAS_REGCEB => 0, C_USE_BYTE_WEB => 1, C_WEB_WIDTH => 4, C_WRITE_MODE_B => "WRITE_FIRST", C_WRITE_WIDTH_B => 32, C_READ_WIDTH_B => 32, C_WRITE_DEPTH_B => 16384, C_READ_DEPTH_B => 16384, C_ADDRB_WIDTH => 32, C_HAS_MEM_OUTPUT_REGS_A => 0, C_HAS_MEM_OUTPUT_REGS_B => 0, C_HAS_MUX_OUTPUT_REGS_A => 0, C_HAS_MUX_OUTPUT_REGS_B => 0, C_MUX_PIPELINE_STAGES => 0, C_HAS_SOFTECC_INPUT_REGS_A => 0, C_HAS_SOFTECC_OUTPUT_REGS_B => 0, C_USE_SOFTECC => 0, C_USE_ECC => 0, C_EN_ECC_PIPE => 0, C_HAS_INJECTERR => 0, C_SIM_COLLISION_CHECK => "ALL", C_COMMON_CLK => 0, C_DISABLE_WARN_BHV_COLL => 0, C_EN_SLEEP_PIN => 0, C_USE_URAM => 0, C_EN_RDADDRA_CHG => 0, C_EN_RDADDRB_CHG => 0, C_EN_DEEPSLEEP_PIN => 0, C_EN_SHUTDOWN_PIN => 0, C_EN_SAFETY_CKT => 0, C_DISABLE_WARN_BHV_RANGE => 0, C_COUNT_36K_BRAM => "16", C_COUNT_18K_BRAM => "0", C_EST_POWER_SUMMARY => "Estimated Power for IP : 20.388 mW" ) PORT MAP ( clka => clka, rsta => rsta, ena => ena, regcea => '0', wea => wea, addra => addra, dina => dina, douta => douta, clkb => clkb, rstb => rstb, enb => enb, regceb => '0', web => web, addrb => addrb, dinb => dinb, doutb => doutb, injectsbiterr => '0', injectdbiterr => '0', eccpipece => '0', sleep => '0', deepsleep => '0', shutdown => '0', s_aclk => '0', s_aresetn => '0', s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_awvalid => '0', s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_wlast => '0', s_axi_wvalid => '0', s_axi_bready => '0', s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_arvalid => '0', s_axi_rready => '0', s_axi_injectsbiterr => '0', s_axi_injectdbiterr => '0' ); END zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_arch;	mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_0_0/fifo_generator_v11_0/ramfifo/rd_status_flags_as.vhd

19

15251

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mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/proc_sys_reset_v5_0/hdl/src/vhdl/lpf.vhd

7

15991

------------------------------------------------------------------------------- -- lpf - entity/architecture pair ------------------------------------------------------------------------------- -- -- ************************************************************************ -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This file contains proprietary and confidential information of ** -- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license ** -- ** from Xilinx, and may be used, copied and/or disclosed only ** -- ** pursuant to the terms of a valid license agreement with Xilinx. ** -- ** ** -- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION ** -- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER ** -- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT ** -- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, ** -- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx ** -- ** does not warrant that functions included in the Materials will ** -- ** meet the requirements of Licensee, or that the operation of the ** -- ** Materials will be uninterrupted or error-free, or that defects ** -- ** in the Materials will be corrected. Furthermore, Xilinx does ** -- ** not warrant or make any representations regarding use, or the ** -- ** results of the use, of the Materials in terms of correctness, ** -- ** accuracy, reliability or otherwise. ** -- ** ** -- ** Xilinx products are not designed or intended to be fail-safe, ** -- ** or for use in any application requiring fail-safe performance, ** -- ** such as life-support or safety devices or systems, Class III ** -- ** medical devices, nuclear facilities, applications related to ** -- ** the deployment of airbags, or any other applications that could ** -- ** lead to death, personal injury or severe property or ** -- ** environmental damage (individually and collectively, "critical ** -- ** applications"). Customer assumes the sole risk and liability ** -- ** of any use of Xilinx products in critical applications, ** -- ** subject only to applicable laws and regulations governing ** -- ** limitations on product liability. ** -- ** ** -- ** Copyright 2012 Xilinx, Inc. ** -- ** All rights reserved. ** -- ** ** -- ** This disclaimer and copyright notice must be retained as part ** -- ** of this file at all times. ** -- ************************************************************************ -- ------------------------------------------------------------------------------- -- Filename: lpf.vhd -- Version: v4.00a -- Description: Parameterizeable top level processor reset module. -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: This section should show the hierarchical structure of the -- designs.Separate lines with blank lines if necessary to improve -- readability. -- -- proc_sys_reset.vhd -- upcnt_n.vhd -- lpf.vhd -- sequence.vhd ------------------------------------------------------------------------------- -- Author: Kurt Conover -- History: -- Kurt Conover 11/08/01 -- First Release -- -- KC 02/25/2002 -- Added Dcm_locked as an input -- -- Added Power on reset srl_time_out -- -- KC 08/26/2003 -- Added attribute statements for power on -- reset SRL -- -- ~~~~~~~ -- SK 03/11/10 -- ^^^^^^^ -- 1. Updated the core so support the active low "Interconnect_aresetn" and -- "Peripheral_aresetn" signals. -- ^^^^^^^ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; library Unisim; use Unisim.all; ------------------------------------------------------------------------------- -- Port Declaration ------------------------------------------------------------------------------- -- Definition of Generics: -- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting -- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting -- C_EXT_RESET_HIGH -- External Reset Active High or Active Low -- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low -- -- Definition of Ports: -- Slowest_sync_clk -- Clock -- External_System_Reset -- External Reset Input -- Auxiliary_System_Reset -- Auxiliary Reset Input -- Dcm_locked -- DCM Locked, hold system in reset until 1 -- Lpf_reset -- Low Pass Filtered Output -- ------------------------------------------------------------------------------- entity lpf is generic( C_EXT_RST_WIDTH : Integer; C_AUX_RST_WIDTH : Integer; C_EXT_RESET_HIGH : std_logic; C_AUX_RESET_HIGH : std_logic ); port( MB_Debug_Sys_Rst : in std_logic; Dcm_locked : in std_logic; External_System_Reset : in std_logic; Auxiliary_System_Reset : in std_logic; Slowest_Sync_Clk : in std_logic; Lpf_reset : out std_logic ); end lpf; architecture imp of lpf is component SRL16 is -- synthesis translate_off generic ( INIT : bit_vector ); -- synthesis translate_on port (D : in std_logic; CLK : in std_logic; A0 : in std_logic; A1 : in std_logic; A2 : in std_logic; A3 : in std_logic; Q : out std_logic); end component SRL16; constant CLEAR : std_logic := '0'; signal exr_d1 : std_logic := '0'; -- delayed External_System_Reset signal exr_lpf : std_logic_vector(0 to C_EXT_RST_WIDTH - 1) := (others => '0'); -- LPF DFF signal asr_d1 : std_logic := '0'; -- delayed Auxiliary_System_Reset signal asr_lpf : std_logic_vector(0 to C_AUX_RST_WIDTH - 1) := (others => '0'); -- LPF DFF signal exr_and : std_logic := '0'; -- varible input width "and" gate signal exr_nand : std_logic := '0'; -- vaiable input width "and" gate signal asr_and : std_logic := '0'; -- varible input width "and" gate signal asr_nand : std_logic := '0'; -- vaiable input width "and" gate signal lpf_int : std_logic := '0'; -- internal Lpf_reset signal lpf_exr : std_logic := '0'; signal lpf_asr : std_logic := '0'; signal srl_time_out : std_logic; attribute INIT : string; attribute INIT of POR_SRL_I: label is "FFFF"; begin Lpf_reset <= lpf_int; ------------------------------------------------------------------------------- -- Power On Reset Generation ------------------------------------------------------------------------------- -- This generates a reset for the first 16 clocks after a power up ------------------------------------------------------------------------------- POR_SRL_I: SRL16 -- synthesis translate_off generic map ( INIT => X"FFFF") -- synthesis translate_on port map ( D => '0', CLK => Slowest_sync_clk, A0 => '1', A1 => '1', A2 => '1', A3 => '1', Q => srl_time_out); ------------------------------------------------------------------------------- -- LPF_OUTPUT_PROCESS ------------------------------------------------------------------------------- -- This generates the reset pulse and the count enable to core reset counter -- --ACTIVE_HIGH_LPF_EXT: if (C_EXT_RESET_HIGH = '1') generate --begin LPF_OUTPUT_PROCESS: process (Slowest_sync_clk) begin if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then lpf_int <= lpf_exr or lpf_asr or srl_time_out or not Dcm_locked; end if; end process LPF_OUTPUT_PROCESS; --end generate ACTIVE_HIGH_LPF_EXT; --ACTIVE_LOW_LPF_EXT: if (C_EXT_RESET_HIGH = '0') generate --begin --LPF_OUTPUT_PROCESS: process (Slowest_sync_clk) -- begin -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then -- lpf_int <= not (lpf_exr or -- lpf_asr or -- srl_time_out)or -- not Dcm_locked; -- end if; -- end process; --end generate ACTIVE_LOW_LPF_EXT; EXR_OUTPUT_PROCESS: process (Slowest_sync_clk) begin if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then if exr_and = '1' then lpf_exr <= '1'; elsif (exr_and = '0' and exr_nand = '1') then lpf_exr <= '0'; end if; end if; end process EXR_OUTPUT_PROCESS; ASR_OUTPUT_PROCESS: process (Slowest_sync_clk) begin if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then if asr_and = '1' then lpf_asr <= '1'; elsif (asr_and = '0' and asr_nand = '1') then lpf_asr <= '0'; end if; end if; end process ASR_OUTPUT_PROCESS; ------------------------------------------------------------------------------- -- This If-generate selects an active high input for External System Reset ------------------------------------------------------------------------------- ACTIVE_HIGH_EXT: if (C_EXT_RESET_HIGH /= '0') generate begin ----------------------------------- ACT_HI_EXT:process(Slowest_Sync_Clk) begin if (Slowest_Sync_Clk'event and Slowest_Sync_Clk = '1') then exr_d1 <= External_System_Reset or MB_Debug_Sys_Rst; exr_lpf(0) <= exr_d1; end if; end process; ----------------------------------- end generate ACTIVE_HIGH_EXT; ------------------------------------------------------------------------------- -- This If-generate selects an active low input for External System Reset ------------------------------------------------------------------------------- ACTIVE_LOW_EXT: if (C_EXT_RESET_HIGH = '0') generate begin ------------------------------------- ACT_LO_EXT: process(Slowest_Sync_Clk) begin if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then exr_d1 <= not External_System_Reset or MB_Debug_Sys_Rst; exr_lpf(0) <= exr_d1; end if; end process; ------------------------------------- end generate ACTIVE_LOW_EXT; ------------------------------------------------------------------------------- -- This If-generate selects an active high input for Auxiliary System Reset ------------------------------------------------------------------------------- ACTIVE_HIGH_AUX: if (C_AUX_RESET_HIGH /= '0') generate begin ------------------------------------- ACT_HI_AUX: process(Slowest_Sync_Clk) begin if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then asr_d1 <= Auxiliary_System_Reset; asr_lpf(0) <= asr_d1; end if; end process; ------------------------------------- end generate ACTIVE_HIGH_AUX; ------------------------------------------------------------------------------- -- This If-generate selects an active low input for Auxiliary System Reset ------------------------------------------------------------------------------- ACTIVE_LOW_AUX: if (C_AUX_RESET_HIGH = '0') generate begin ------------------------------------- ACT_LO_AUX: process(Slowest_Sync_Clk) begin if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then asr_d1 <= not Auxiliary_System_Reset; asr_lpf(0) <= asr_d1; end if; end process; ------------------------------------- end generate ACTIVE_LOW_AUX; ------------------------------------------------------------------------------- -- This For-generate creates the low pass filter D-Flip Flops ------------------------------------------------------------------------------- EXT_LPF: for i in 1 to C_EXT_RST_WIDTH - 1 generate begin ---------------------------------------- EXT_LPF_DFF : process (Slowest_Sync_Clk) begin if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then exr_lpf(i) <= exr_lpf(i-1); end if; end process; ---------------------------------------- end generate EXT_LPF; ------------------------------------------------------------------------------------------ -- Implement the 'AND' function on the for the LPF ------------------------------------------------------------------------------------------ EXT_LPF_AND : process (exr_lpf) Variable loop_and : std_logic; Variable loop_nand : std_logic; Begin loop_and := '1'; loop_nand := '1'; for j in 0 to C_EXT_RST_WIDTH - 1 loop loop_and := loop_and and exr_lpf(j); loop_nand := loop_nand and not exr_lpf(j); End loop; exr_and <= loop_and; exr_nand <= loop_nand; end process; ------------------------------------------------------------------------------- -- This For-generate creates the low pass filter D-Flip Flops ------------------------------------------------------------------------------- AUX_LPF: for k in 1 to C_AUX_RST_WIDTH - 1 generate begin ---------------------------------------- AUX_LPF_DFF : process (Slowest_Sync_Clk) begin if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then asr_lpf(k) <= asr_lpf(k-1); end if; end process; ---------------------------------------- end generate AUX_LPF; ------------------------------------------------------------------------------------------ -- Implement the 'AND' function on the for the LPF ------------------------------------------------------------------------------------------ AUX_LPF_AND : process (asr_lpf) Variable aux_loop_and : std_logic; Variable aux_loop_nand : std_logic; Begin aux_loop_and := '1'; aux_loop_nand := '1'; for m in 0 to C_AUX_RST_WIDTH - 1 loop aux_loop_and := aux_loop_and and asr_lpf(m); aux_loop_nand := aux_loop_nand and not asr_lpf(m); End loop; asr_and <= aux_loop_and; asr_nand <= aux_loop_nand; end process; end imp;

mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/proc_common_v4_0/hdl/src/vhdl/mux_onehot_f.vhd

15

12692

------------------------------------------------------------------------------- -- $Id: mux_onehot_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $ ------------------------------------------------------------------------------- -- mux_onehot_f - arch and entity ------------------------------------------------------------------------------- -- -- ************************************************************************* -- ** ** -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This text/file contains proprietary, confidential ** -- ** information of Xilinx, Inc., is distributed under ** -- ** license from Xilinx, Inc., and may be used, copied ** -- ** and/or disclosed only pursuant to the terms of a valid ** -- ** license agreement with Xilinx, Inc. Xilinx hereby ** -- ** grants you a license to use this text/file solely for ** -- ** design, simulation, implementation and creation of ** -- ** design files limited to Xilinx devices or technologies. ** -- ** Use with non-Xilinx devices or technologies is expressly ** -- ** prohibited and immediately terminates your license unless ** -- ** covered by a separate agreement. ** -- ** ** -- ** Xilinx is providing this design, code, or information ** -- ** "as-is" solely for use in developing programs and ** -- ** solutions for Xilinx devices, with no obligation on the ** -- ** part of Xilinx to provide support. By providing this design, ** -- ** code, or information as one possible implementation of ** -- ** this feature, application or standard, Xilinx is making no ** -- ** representation that this implementation is free from any ** -- ** claims of infringement. You are responsible for obtaining ** -- ** any rights you may require for your implementation. ** -- ** Xilinx expressly disclaims any warranty whatsoever with ** -- ** respect to the adequacy of the implementation, including ** -- ** but not limited to any warranties or representations that this ** -- ** implementation is free from claims of infringement, implied ** -- ** warranties of merchantability or fitness for a particular ** -- ** purpose. ** -- ** ** -- ** Xilinx products are not intended for use in life support ** -- ** appliances, devices, or systems. Use in such applications is ** -- ** expressly prohibited. ** -- ** ** -- ** Any modifications that are made to the Source Code are ** -- ** done at the users sole risk and will be unsupported. ** -- ** The Xilinx Support Hotline does not have access to source ** -- ** code and therefore cannot answer specific questions related ** -- ** to source HDL. The Xilinx Hotline support of original source ** -- ** code IP shall only address issues and questions related ** -- ** to the standard Netlist version of the core (and thus ** -- ** indirectly, the original core source). ** -- ** ** -- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** This copyright and support notice must be retained as part ** -- ** of this text at all times. ** -- ** ** -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: mux_onehot_f.vhd -- -- Description: Parameterizable multiplexer with one hot select lines. -- -- Please refer to the entity interface while reading the -- remainder of this description. -- -- If n is the index of the single select line of S(0 to C_NB-1) -- that is asserted, then -- -- Y(0 to C_DW-1) <= D(n*C_DW to n*C_DW + C_DW -1) -- -- That is, Y selects the nth group of C_DW consecutive -- bits of D. -- -- Note that C_NB = 1 is handled as a special case in which -- Y <= D, without regard to the select line, S. -- -- The Implementation depends on the C_FAMILY parameter. -- If the target family supports the needed primitives, -- a carry-chain structure will be implemented. Otherwise, -- an implementation dependent on synthesis inferral will -- be generated. -- ------------------------------------------------------------------------------- -- Structure: -- mux_onehot_f -- family_support -------------------------------------------------------------------------------- -- Author: FLO -- History: -- FLO 11/30/05 -- First version derived from mux_onehot.vhd -- -- by BLT and ALS. -- -- ~~~~~~ -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Changed proc_common library version to v4_0 -- - Incorporated new disclaimer header -- ^^^^^^ -- --------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_cmb" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; ------------------------------------------------------------------------------- -- Generic and Port Declaration ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Definition of Generics and Ports -- -- C_DW: Data width of buses entering the mux. Valid range is 1 to 256. -- C_NB: Number of data buses entering the mux. Valid range is 1 to 64. -- -- input D -- input data bus -- input S -- input select bus -- output Y -- output bus -- -- The input data is represented by a one-dimensional bus that is made up -- of all of the data buses concatenated together. For example, a 4 to 1 -- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by: -- -- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1, -- Bus3Data0, Bus3Data1) -- -- Y = (Bus0Data0, Bus0Data1) if S(0)=1 else -- (Bus1Data0, Bus1Data1) if S(1)=1 else -- (Bus2Data0, Bus2Data1) if S(2)=1 else -- (Bus3Data0, Bus3Data1) if S(3)=1 -- -- Only one bit of S should be asserted at a time. -- ------------------------------------------------------------------------------- library proc_common_v4_0; use proc_common_v4_0.family_support.all; -- 'supported' function, etc. -- entity mux_onehot_f is generic( C_DW: integer := 32; C_NB: integer := 5; C_FAMILY : string := "virtexe"); port( D: in std_logic_vector(0 to C_DW*C_NB-1); S: in std_logic_vector(0 to C_NB-1); Y: out std_logic_vector(0 to C_DW-1)); end mux_onehot_f; library unisim; use unisim.all; -- Make unisim entities available for default binding. architecture imp of mux_onehot_f is constant NLS : natural := native_lut_size(fam_as_string => C_FAMILY, no_lut_return_val => 2*C_NB); function lut_val(D, S : std_logic_vector) return std_logic is variable rn : std_logic := '0'; begin for i in D'range loop rn := rn or (S(i) and D(i)); end loop; return not rn; end; function min(i, j : integer) return integer is begin if i < j then return i; else return j; end if; end; ----------------------------------------------------------------------------- -- Signal and Type Declarations ------------------------------------------------------------------------------- signal Dreord: std_logic_vector(0 to C_DW*C_NB-1); signal sel: std_logic_vector(0 to C_DW*C_NB-1); ------------------------------------------------------------------------------- -- Component Declarations ------------------------------------------------------------------------------- component MUXCY port ( O : out std_ulogic; CI : in std_ulogic; DI : in std_ulogic; S : in std_ulogic ); end component; begin -- Reorder data buses WA_GEN : if C_DW > 0 generate -- XST WA REORD: process( D ) variable m,n: integer; begin for m in 0 to C_DW-1 loop for n in 0 to C_NB-1 loop Dreord( m*C_NB+n) <= D( n*C_DW+m ); end loop; end loop; end process REORD; end generate; ------------------------------------------------------------------------------- -- REPSELS_PROCESS ------------------------------------------------------------------------------- -- The one-hot select bus contains 1-bit for each bus. To more easily -- parameterize the carry chains and reduce loading on the select bus, these -- signals are replicated into a bus that replicates the select bits for the -- data width of the busses ------------------------------------------------------------------------------- REPSELS_PROCESS : process ( S ) variable i, j : integer; begin -- loop through all data bits and busses for i in 0 to C_DW-1 loop for j in 0 to C_NB-1 loop sel(i*C_NB+j) <= S(j); end loop; end loop; end process REPSELS_PROCESS; GEN: if C_NB > 1 generate constant BPL : positive := NLS / 2; -- Buses per LUT is the native lut -- size divided by two.signals per bus. constant NUMLUTS : positive := (C_NB+(BPL-1))/BPL; begin DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate signal cyout : std_logic_vector(0 to NUMLUTS); signal lutout : std_logic_vector(0 to NUMLUTS-1); begin cyout(0) <= '0'; NUM_BUSES_GEN: for j in 0 to NUMLUTS - 1 generate constant BTL : positive := min(BPL, C_NB - j*BPL); -- Number of Buses This Lut (for last LUT this may be less than BPL) begin lutout(j) <= lut_val(D => Dreord(i*C_NB+j*BPL to i*C_NB+j*BPL+BTL-1), S => sel(i*C_NB+j*BPL to i*C_NB+j*BPL+BTL-1) ); MUXCY_GEN : if NUMLUTS > 1 generate MUXCY_I : component MUXCY port map (CI=>cyout(j), DI=> '1', S=>lutout(j), O=>cyout(j+1)); end generate; end generate; Y(i) <= cyout(NUMLUTS) when NUMLUTS > 1 else not lutout(0); -- If just one -- LUT, then take value from -- lutout rather than cyout. end generate; end generate; ONE_GEN: if C_NB = 1 generate Y <= D; end generate; end imp;

mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_0_0/blk_mem_gen_v8_1/blk_mem_gen_top.vhd

27

71839

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block UXXDHK9d3YtwspCksVg3cn1OQkWFk3QQ1bnN8kcpv130B5dMgVD8+qx+9EwjTR0JFb8FYrcL/7dg lIwdmlKGHQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block lGlirTrah5ntgtsTqcFN8kWYeCxRHbehSLZqyiEvescJE+ORKShYIOu42/ExCc8hSawNVl9qCirT UlThiM+Fc1evKMQYzaFIzbKiio/Xw8rjRfhTJKjaxdK3T87LnrHcsuSrci+tl+anpBCM3X47tPxD oNmgZzATBY/NVtZsbvA= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block UAOAU0ylQuQrszr15mLZsCg4shnqFlxQBAKcqwUoJfM+lTESkAcOosPqKsRH4IbbLlaKiP2HCFU1 aKEFZccPWIgd9WlvneNU3oFbpPCOyV9eZTCX4e5jNTf/7OwRRATKc0mjpd4lxBL9xFrSwNaUKgs1 3vjH77tdesEDAIn5GZ1C/7l3wjwnB4tAiaRNqLY90lB834tlc4mPcP6x8L3rhv5EXfqU4jyJC8B1 4zsO/vH5+VVa1595cRZ3xWXEGVMvmWhY+6TDUJCMhztjp+p4kbQ87UqJz9ddvZWB4hRfjo99Os6I PqyD9P7zikHIa7jafFMtZu0Vj7u4HDelVYnPyw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block qRFhWXCy25iIpt8SG9Mt+xW3HRp/MFye1jJpn72azeuP+g/A4uHCFxvcKVhzcuE8lYDqFZ9IBM4P ZjcyPOhURivBaWk0KosUyfzbkORd8yS5XcayTSj5/d+90PPk5PXVCLjTrcMbg0+NO3tiyKtPpLQJ f+Ih38e2az80fHBgiqo= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block tjh0p4bhQQ++Enuq/zxHJnIk+bY5nNzFWlWKnTVXUtnLIlVGko6ShpeQRaCrGzeMC58aHThmj0Rv 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mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/basic_sfifo_fg.vhd

12

55233

------------------------------------------------------------------------------- -- basic_sfifo_fg.vhd ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: basic_sfifo_fg.vhd -- -- Description: -- This HDL file implements a basic synchronous (single clock) fifo using the -- FIFO Generator tool. It is intended to offer a simple interface to the user -- with the complexity of the FIFO Generator interface hidden from the user. -- -- Note that in normal op mode (not First Word Fall Through FWFT) the data count -- output goes to zero when the FIFO goes full. This the way FIFO Generator works. -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- basic_sfifo_fg.vhd -- | -- |-- fifo_generator_v8_2 -- ------------------------------------------------------------------------------- -- Revision History: -- -- -- Author: DET -- Revision: $Revision: 1.0 $ -- Date: $3/07/2011$ -- -- History: -- DET 3/07/2011 Initial Version -- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library fifo_generator_v11_0; use fifo_generator_v11_0.all; library proc_common_v4_0; use proc_common_v4_0.proc_common_pkg.all; use proc_common_v4_0.proc_common_pkg.log2; --use proc_common_v4_0.coregen_comp_defs.all; -- synopsys translate_off --library XilinxCoreLib; --use XilinxCoreLib.all; -- synopsys translate_on ------------------------------------------------------------------------------- entity basic_sfifo_fg is generic ( C_DWIDTH : Integer := 32 ; -- FIFO data Width (Read and write data ports are symetric) C_DEPTH : Integer := 512 ; -- FIFO Depth (set to power of 2) C_HAS_DATA_COUNT : integer := 1 ; -- 0 = Data Count output not needed -- 1 = Data Count output needed C_DATA_COUNT_WIDTH : integer := 10 ; -- Data Count bit width (Max value is log2(C_DEPTH)) C_IMPLEMENTATION_TYPE : integer range 0 to 1 := 0; -- 0 = Common Clock BRAM / Distributed RAM (Synchronous FIFO) -- 1 = Common Clock Shift Register (Synchronous FIFO) C_MEMORY_TYPE : integer := 1; -- 0 = Any -- 1 = BRAM -- 2 = Distributed Memory -- 3 = Shift Registers C_PRELOAD_REGS : integer := 1; -- 0 = normal -- 1 = FWFT C_PRELOAD_LATENCY : integer := 0; -- 0 = FWFT -- 1 = normal C_USE_FWFT_DATA_COUNT : integer := 0; -- 0 = normal -- 1 for FWFT C_SYNCHRONIZER_STAGE : integer := 2; -- valid values are 0 to 8; C_FAMILY : string := "virtex6" ); port ( CLK : IN std_logic := '0'; DIN : IN std_logic_vector(C_DWIDTH-1 DOWNTO 0) := (OTHERS => '0'); RD_EN : IN std_logic := '0'; SRST : IN std_logic := '0'; WR_EN : IN std_logic := '0'; DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0); DOUT : OUT std_logic_vector(C_DWIDTH-1 DOWNTO 0); EMPTY : OUT std_logic; FULL : OUT std_logic ); end entity basic_sfifo_fg; architecture implementation of basic_sfifo_fg is -- Constant Declarations ---------------------------------------------- Constant POINTER_WIDTH : integer := log2(C_DEPTH); -- Constant zeros for programmable threshold inputs signal PROG_RDTHRESH_ZEROS : std_logic_vector(POINTER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); signal PROG_WRTHRESH_ZEROS : std_logic_vector(POINTER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- Signals --Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE" signal ALMOST_FULL : std_logic; signal WR_ACK : std_logic; signal OVERFLOW : std_logic; signal VALID : std_logic; signal UNDERFLOW : std_logic; signal ALMOST_EMPTY : std_logic; signal RD_DATA_COUNT : std_logic_vector(C_DATA_COUNT_WIDTH-1 downto 0); signal WR_DATA_COUNT : std_logic_vector(C_DATA_COUNT_WIDTH-1 downto 0); signal PROG_FULL : std_logic; signal PROG_EMPTY : std_logic; signal SBITERR : std_logic; signal DBITERR : std_logic; signal S_AXI_AWREADY : std_logic; signal S_AXI_WREADY : std_logic; signal S_AXI_BID : std_logic_vector(3 DOWNTO 0); signal S_AXI_BRESP : std_logic_vector(2-1 DOWNTO 0); signal S_AXI_BUSER : std_logic_vector(0 downto 0); signal S_AXI_BVALID : std_logic; -- AXI Full/Lite Master Write Channel (Read side) signal M_AXI_AWID : std_logic_vector(3 DOWNTO 0); signal M_AXI_AWADDR : std_logic_vector(31 DOWNTO 0); signal M_AXI_AWLEN : std_logic_vector(8-1 DOWNTO 0); signal M_AXI_AWSIZE : std_logic_vector(3-1 DOWNTO 0); signal M_AXI_AWBURST : std_logic_vector(2-1 DOWNTO 0); signal M_AXI_AWLOCK : std_logic_vector(2-1 DOWNTO 0); signal M_AXI_AWCACHE : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_AWPROT : std_logic_vector(3-1 DOWNTO 0); signal M_AXI_AWQOS : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_AWREGION : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_AWUSER : std_logic_vector(0 downto 0); signal M_AXI_AWVALID : std_logic; signal M_AXI_WID : std_logic_vector(3 DOWNTO 0); signal M_AXI_WDATA : std_logic_vector(63 DOWNTO 0); signal M_AXI_WSTRB : std_logic_vector(7 DOWNTO 0); signal M_AXI_WLAST : std_logic; signal M_AXI_WUSER : std_logic_vector(0 downto 0); signal M_AXI_WVALID : std_logic; signal M_AXI_BREADY : std_logic; -- AXI Full/Lite Slave Read Channel (Write side) signal S_AXI_ARREADY : std_logic; signal S_AXI_RID : std_logic_vector(3 DOWNTO 0); signal S_AXI_RDATA : std_logic_vector(63 DOWNTO 0); signal S_AXI_RRESP : std_logic_vector(2-1 DOWNTO 0); signal S_AXI_RLAST : std_logic; signal S_AXI_RUSER : std_logic_vector(0 downto 0); signal S_AXI_RVALID : std_logic; -- AXI Full/Lite Master Read Channel (Read side) signal M_AXI_ARID : std_logic_vector(3 DOWNTO 0); signal M_AXI_ARADDR : std_logic_vector(31 DOWNTO 0); signal M_AXI_ARLEN : std_logic_vector(8-1 DOWNTO 0); signal M_AXI_ARSIZE : std_logic_vector(3-1 DOWNTO 0); signal M_AXI_ARBURST : std_logic_vector(2-1 DOWNTO 0); signal M_AXI_ARLOCK : std_logic_vector(2-1 DOWNTO 0); signal M_AXI_ARCACHE : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_ARPROT : std_logic_vector(3-1 DOWNTO 0); signal M_AXI_ARQOS : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_ARREGION : std_logic_vector(4-1 DOWNTO 0); signal M_AXI_ARUSER : std_logic_vector(0 downto 0); signal M_AXI_ARVALID : std_logic; signal M_AXI_RREADY : std_logic; -- AXI Streaming Slave Signals (Write side) signal S_AXIS_TREADY : std_logic; -- AXI Streaming Master Signals (Read side) signal M_AXIS_TVALID : std_logic; signal M_AXIS_TDATA : std_logic_vector(63 DOWNTO 0); signal M_AXIS_TSTRB : std_logic_vector(3 DOWNTO 0); signal M_AXIS_TKEEP : std_logic_vector(3 DOWNTO 0); signal M_AXIS_TLAST : std_logic; signal M_AXIS_TID : std_logic_vector(7 DOWNTO 0); signal M_AXIS_TDEST : std_logic_vector(3 DOWNTO 0); signal M_AXIS_TUSER : std_logic_vector(3 DOWNTO 0); -- AXI Full/Lite Write Address Channel Signals signal AXI_AW_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AW_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AW_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AW_SBITERR : std_logic; signal AXI_AW_DBITERR : std_logic; signal AXI_AW_OVERFLOW : std_logic; signal AXI_AW_UNDERFLOW : std_logic; signal AXI_AW_PROG_FULL : STD_LOGIC; signal AXI_AW_PROG_EMPTY : STD_LOGIC; -- AXI Full/Lite Write Data Channel Signals signal AXI_W_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_W_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_W_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_W_SBITERR : std_logic; signal AXI_W_DBITERR : std_logic; signal AXI_W_OVERFLOW : std_logic; signal AXI_W_UNDERFLOW : std_logic; signal AXI_W_PROG_FULL : STD_LOGIC; signal AXI_W_PROG_EMPTY : STD_LOGIC; -- AXI Full/Lite Write Response Channel Signals signal AXI_B_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_B_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_B_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_B_SBITERR : std_logic; signal AXI_B_DBITERR : std_logic; signal AXI_B_OVERFLOW : std_logic; signal AXI_B_UNDERFLOW : std_logic; signal AXI_B_PROG_FULL : STD_LOGIC; signal AXI_B_PROG_EMPTY : STD_LOGIC; -- AXI Full/Lite Read Address Channel Signals signal AXI_AR_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AR_WR_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AR_RD_DATA_COUNT : std_logic_vector(4 DOWNTO 0); signal AXI_AR_SBITERR : std_logic; signal AXI_AR_DBITERR : std_logic; signal AXI_AR_OVERFLOW : std_logic; signal AXI_AR_UNDERFLOW : std_logic; signal AXI_AR_PROG_FULL : STD_LOGIC; signal AXI_AR_PROG_EMPTY : STD_LOGIC; -- AXI Full/Lite Read Data Channel Signals signal AXI_R_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_R_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_R_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXI_R_SBITERR : std_logic; signal AXI_R_DBITERR : std_logic; signal AXI_R_OVERFLOW : std_logic; signal AXI_R_UNDERFLOW : std_logic; signal AXI_R_PROG_FULL : STD_LOGIC; signal AXI_R_PROG_EMPTY : STD_LOGIC; -- AXI Streaming FIFO Related Signals signal AXIS_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXIS_WR_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXIS_RD_DATA_COUNT : std_logic_vector(10 DOWNTO 0); signal AXIS_SBITERR : std_logic; signal AXIS_DBITERR : std_logic; signal AXIS_OVERFLOW : std_logic; signal AXIS_UNDERFLOW : std_logic; signal AXIS_PROG_FULL : STD_LOGIC; signal AXIS_PROG_EMPTY : STD_LOGIC; begin --(architecture implementation) ------------------------------------------------------------------------------- -- Instantiate the generalized FIFO Generator instance -- -- NOTE: -- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!! -- This is a Coregen FIFO Generator Call module for -- BRAM implementations of a basic Sync FIFO -- ------------------------------------------------------------------------------- I_BASIC_SFIFO : entity fifo_generator_v11_0.fifo_generator_v11_0 generic map( C_COMMON_CLOCK => 1, C_COUNT_TYPE => 0, C_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH, C_DEFAULT_VALUE => "BlankString", C_DIN_WIDTH => C_DWIDTH, C_DOUT_RST_VAL => "0", C_DOUT_WIDTH => C_DWIDTH, C_ENABLE_RLOCS => 0, -- n0 C_FAMILY => C_FAMILY, C_HAS_ALMOST_EMPTY => 0, -- n0 C_HAS_ALMOST_FULL => 0, -- n0 C_HAS_BACKUP => 0, -- n0 C_HAS_DATA_COUNT => C_HAS_DATA_COUNT, C_HAS_MEMINIT_FILE => 0, -- n0 C_HAS_OVERFLOW => 0, -- n0 C_HAS_RD_DATA_COUNT => 0, -- n0 C_HAS_RD_RST => 0, -- n0 C_HAS_RST => 0, -- n0 C_HAS_SRST => 1, -- yes C_HAS_UNDERFLOW => 0, -- n0 C_HAS_VALID => 0, -- n0 C_HAS_WR_ACK => 0, -- n0 C_HAS_WR_DATA_COUNT => 0, -- n0 C_HAS_WR_RST => 0, -- n0 C_IMPLEMENTATION_TYPE => 0, -- Common clock BRAM C_INIT_WR_PNTR_VAL => 0, C_MEMORY_TYPE => C_MEMORY_TYPE, C_MIF_FILE_NAME => "BlankString", C_OPTIMIZATION_MODE => 0, C_OVERFLOW_LOW => 0, C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, C_PRELOAD_REGS => C_PRELOAD_REGS, C_PRIM_FIFO_TYPE => "512x36", C_PROG_EMPTY_THRESH_ASSERT_VAL => 0, C_PROG_EMPTY_THRESH_NEGATE_VAL => 0, C_PROG_EMPTY_TYPE => 0, C_PROG_FULL_THRESH_ASSERT_VAL => 0, C_PROG_FULL_THRESH_NEGATE_VAL => 0, C_PROG_FULL_TYPE => 0, C_RD_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH, C_RD_DEPTH => C_DEPTH, C_RD_FREQ => 1, C_RD_PNTR_WIDTH => POINTER_WIDTH, C_UNDERFLOW_LOW => 0, C_USE_DOUT_RST => 1, C_USE_EMBEDDED_REG => 0, C_USE_FIFO16_FLAGS => 0, C_USE_FWFT_DATA_COUNT => C_USE_FWFT_DATA_COUNT, C_VALID_LOW => 0, C_WR_ACK_LOW => 0, C_WR_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH, C_WR_DEPTH => C_DEPTH, C_WR_FREQ => 1, C_WR_PNTR_WIDTH => POINTER_WIDTH, C_WR_RESPONSE_LATENCY => 1, C_USE_ECC => 0, C_FULL_FLAGS_RST_VAL => 0, C_ENABLE_RST_SYNC => 1, C_ERROR_INJECTION_TYPE => 0, C_SYNCHRONIZER_STAGE => C_SYNCHRONIZER_STAGE, C_HAS_INT_CLK => 0, C_MSGON_VAL => 1, -- AXI Interface related parameters start here C_INTERFACE_TYPE => 0, -- : integer := 0; -- 0: Native Interface; 1: AXI Interface C_AXI_TYPE => 0, -- : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite C_HAS_AXI_WR_CHANNEL => 0, -- : integer := 0; C_HAS_AXI_RD_CHANNEL => 0, -- : integer := 0; C_HAS_SLAVE_CE => 0, -- : integer := 0; C_HAS_MASTER_CE => 0, -- : integer := 0; C_ADD_NGC_CONSTRAINT => 0, -- : integer := 0; C_USE_COMMON_OVERFLOW => 0, -- : integer := 0; C_USE_COMMON_UNDERFLOW => 0, -- : integer := 0; C_USE_DEFAULT_SETTINGS => 0, -- : integer := 0; -- AXI Full/Lite C_AXI_ID_WIDTH => 4 , -- : integer := 0; C_AXI_ADDR_WIDTH => 32, -- : integer := 0; C_AXI_DATA_WIDTH => 64, -- : integer := 0; C_AXI_LEN_WIDTH => 8, -- : integer := 8; C_AXI_LOCK_WIDTH => 2, -- : integer := 2; C_HAS_AXI_ID => 0, -- : integer := 0; C_HAS_AXI_AWUSER => 0 , -- : integer := 0; C_HAS_AXI_WUSER => 0 , -- : integer := 0; C_HAS_AXI_BUSER => 0 , -- : integer := 0; C_HAS_AXI_ARUSER => 0 , -- : integer := 0; C_HAS_AXI_RUSER => 0 , -- : integer := 0; C_AXI_ARUSER_WIDTH => 1 , -- : integer := 0; C_AXI_AWUSER_WIDTH => 1 , -- : integer := 0; C_AXI_WUSER_WIDTH => 1 , -- : integer := 0; C_AXI_BUSER_WIDTH => 1 , -- : integer := 0; C_AXI_RUSER_WIDTH => 1 , -- : integer := 0; -- AXI Streaming C_HAS_AXIS_TDATA => 0 , -- : integer := 0; C_HAS_AXIS_TID => 0 , -- : integer := 0; C_HAS_AXIS_TDEST => 0 , -- : integer := 0; C_HAS_AXIS_TUSER => 0 , -- : integer := 0; C_HAS_AXIS_TREADY => 1 , -- : integer := 0; C_HAS_AXIS_TLAST => 0 , -- : integer := 0; C_HAS_AXIS_TSTRB => 0 , -- : integer := 0; C_HAS_AXIS_TKEEP => 0 , -- : integer := 0; C_AXIS_TDATA_WIDTH => 64, -- : integer := 1; C_AXIS_TID_WIDTH => 8 , -- : integer := 1; C_AXIS_TDEST_WIDTH => 4 , -- : integer := 1; C_AXIS_TUSER_WIDTH => 4 , -- : integer := 1; C_AXIS_TSTRB_WIDTH => 4 , -- : integer := 1; C_AXIS_TKEEP_WIDTH => 4 , -- : integer := 1; -- AXI Channel Type -- WACH --> Write Address Channel -- WDCH --> Write Data Channel -- WRCH --> Write Response Channel -- RACH --> Read Address Channel -- RDCH --> Read Data Channel -- AXIS --> AXI Streaming C_WACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic C_WDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_WRCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_RACH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_RDCH_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_AXIS_TYPE => 0, -- : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie -- AXI Implementation Type -- 1 = Common Clock Block RAM FIFO -- 2 = Common Clock Distributed RAM FIFO -- 11 = Independent Clock Block RAM FIFO -- 12 = Independent Clock Distributed RAM FIFO C_IMPLEMENTATION_TYPE_WACH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_WDCH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_WRCH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_RACH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_RDCH => 1, -- : integer := 0; C_IMPLEMENTATION_TYPE_AXIS => 1, -- : integer := 0; -- AXI FIFO Type -- 0 = Data FIFO -- 1 = Packet FIFO -- 2 = Low Latency Data FIFO C_APPLICATION_TYPE_WACH => 0, -- : integer := 0; C_APPLICATION_TYPE_WDCH => 0, -- : integer := 0; C_APPLICATION_TYPE_WRCH => 0, -- : integer := 0; C_APPLICATION_TYPE_RACH => 0, -- : integer := 0; C_APPLICATION_TYPE_RDCH => 0, -- : integer := 0; C_APPLICATION_TYPE_AXIS => 0, -- : integer := 0; -- Enable ECC -- 0 = ECC disabled -- 1 = ECC enabled C_USE_ECC_WACH => 0, -- : integer := 0; C_USE_ECC_WDCH => 0, -- : integer := 0; C_USE_ECC_WRCH => 0, -- : integer := 0; C_USE_ECC_RACH => 0, -- : integer := 0; C_USE_ECC_RDCH => 0, -- : integer := 0; C_USE_ECC_AXIS => 0, -- : integer := 0; -- ECC Error Injection Type -- 0 = No Error Injection -- 1 = Single Bit Error Injection -- 2 = Double Bit Error Injection -- 3 = Single Bit and Double Bit Error Injection C_ERROR_INJECTION_TYPE_WACH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_WDCH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_WRCH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_RACH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_RDCH => 0, -- : integer := 0; C_ERROR_INJECTION_TYPE_AXIS => 0, -- : integer := 0; -- Input Data Width -- Accumulation of all AXI input signal's width C_DIN_WIDTH_WACH => 32, -- : integer := 1; C_DIN_WIDTH_WDCH => 64, -- : integer := 1; C_DIN_WIDTH_WRCH => 2 , -- : integer := 1; C_DIN_WIDTH_RACH => 32, -- : integer := 1; C_DIN_WIDTH_RDCH => 64, -- : integer := 1; C_DIN_WIDTH_AXIS => 1 , -- : integer := 1; C_WR_DEPTH_WACH => 16 , -- : integer := 16; C_WR_DEPTH_WDCH => 1024, -- : integer := 16; C_WR_DEPTH_WRCH => 16 , -- : integer := 16; C_WR_DEPTH_RACH => 16 , -- : integer := 16; C_WR_DEPTH_RDCH => 1024, -- : integer := 16; C_WR_DEPTH_AXIS => 1024, -- : integer := 16; C_WR_PNTR_WIDTH_WACH => 4 , -- : integer := 4; C_WR_PNTR_WIDTH_WDCH => 10, -- : integer := 4; C_WR_PNTR_WIDTH_WRCH => 4 , -- : integer := 4; C_WR_PNTR_WIDTH_RACH => 4 , -- : integer := 4; C_WR_PNTR_WIDTH_RDCH => 10, -- : integer := 4; C_WR_PNTR_WIDTH_AXIS => 10, -- : integer := 4; C_HAS_DATA_COUNTS_WACH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_WDCH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_WRCH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_RACH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_RDCH => 0, -- : integer := 0; C_HAS_DATA_COUNTS_AXIS => 0, -- : integer := 0; C_HAS_PROG_FLAGS_WACH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_WDCH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_WRCH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_RACH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_RDCH => 0, -- : integer := 0; C_HAS_PROG_FLAGS_AXIS => 0, -- : integer := 0; C_PROG_FULL_TYPE_WACH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_WDCH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_WRCH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_RACH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_RDCH => 5 , -- : integer := 0; C_PROG_FULL_TYPE_AXIS => 5 , -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023, -- : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023, -- : integer := 0; C_PROG_EMPTY_TYPE_WACH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_WDCH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_WRCH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_RACH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_RDCH => 5 , -- : integer := 0; C_PROG_EMPTY_TYPE_AXIS => 5 , -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022, -- : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022, -- : integer := 0; C_REG_SLICE_MODE_WACH => 0, -- : integer := 0; C_REG_SLICE_MODE_WDCH => 0, -- : integer := 0; C_REG_SLICE_MODE_WRCH => 0, -- : integer := 0; C_REG_SLICE_MODE_RACH => 0, -- : integer := 0; C_REG_SLICE_MODE_RDCH => 0, -- : integer := 0; C_REG_SLICE_MODE_AXIS => 0 -- : integer := 0 ) port map( backup => '0', backup_marker => '0', clk => CLK, rst => '0', srst => SRST, wr_clk => '0', wr_rst => '0', rd_clk => '0', rd_rst => '0', din => DIN, -- uses this one wr_en => WR_EN, -- uses this one rd_en => RD_EN, -- uses this one prog_empty_thresh => PROG_RDTHRESH_ZEROS, prog_empty_thresh_assert => PROG_RDTHRESH_ZEROS, prog_empty_thresh_negate => PROG_RDTHRESH_ZEROS, prog_full_thresh => PROG_WRTHRESH_ZEROS, prog_full_thresh_assert => PROG_WRTHRESH_ZEROS, prog_full_thresh_negate => PROG_WRTHRESH_ZEROS, int_clk => '0', injectdbiterr => '0', injectsbiterr => '0', dout => DOUT, -- uses this one full => FULL, -- uses this one almost_full => ALMOST_FULL, wr_ack => WR_ACK, overflow => OVERFLOW, empty => EMPTY, -- uses this one almost_empty => ALMOST_EMPTY, valid => VALID, underflow => UNDERFLOW, data_count => DATA_COUNT, -- uses this one rd_data_count => RD_DATA_COUNT, wr_data_count => WR_DATA_COUNT, prog_full => PROG_FULL, prog_empty => PROG_EMPTY, sbiterr => SBITERR, dbiterr => DBITERR, -- AXI Global Signal m_aclk => '0', -- : IN std_logic := '0'; s_aclk => '0', -- : IN std_logic := '0'; s_aresetn => '0', -- : IN std_logic := '0'; m_aclk_en => '0', -- : IN std_logic := '0'; s_aclk_en => '0', -- : IN std_logic := '0'; -- AXI Full/Lite Slave Write Channel (write side) s_axi_awid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awaddr => "00000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awlen => "00000000", --(others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awsize => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awburst => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awlock => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awcache => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awprot => "000", --(others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awqos => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awregion => "0000", --(others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_awvalid => '0', -- : IN std_logic := '0'; s_axi_awready => S_AXI_AWREADY, -- : OUT std_logic; s_axi_wid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wstrb => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wlast => '0', -- : IN std_logic := '0'; s_axi_wuser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_wvalid => '0', -- : IN std_logic := '0'; s_axi_wready => S_AXI_WREADY, -- : OUT std_logic; s_axi_bid => S_AXI_BID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_bresp => S_AXI_BRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0); s_axi_buser => S_AXI_BUSER, -- : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0); s_axi_bvalid => S_AXI_BVALID, -- : OUT std_logic; s_axi_bready => '0', -- : IN std_logic := '0'; -- AXI Full/Lite Master Write Channel (Read side) m_axi_awid => M_AXI_AWID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); m_axi_awaddr => M_AXI_AWADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0); m_axi_awlen => M_AXI_AWLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0); m_axi_awsize => M_AXI_AWSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_awburst => M_AXI_AWBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_awlock => M_AXI_AWLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_awcache => M_AXI_AWCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_awprot => M_AXI_AWPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_awqos => M_AXI_AWQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_awregion => M_AXI_AWREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_awuser => M_AXI_AWUSER, -- : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0); m_axi_awvalid => M_AXI_AWVALID, -- : OUT std_logic; m_axi_awready => '0', -- : IN std_logic := '0'; m_axi_wid => M_AXI_WID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); m_axi_wdata => M_AXI_WDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0); m_axi_wstrb => M_AXI_WSTRB, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0); m_axi_wlast => M_AXI_WLAST, -- : OUT std_logic; m_axi_wuser => M_AXI_WUSER, -- : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0); m_axi_wvalid => M_AXI_WVALID, -- : OUT std_logic; m_axi_wready => '0', -- : IN std_logic := '0'; m_axi_bid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_bresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); m_axi_buser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_bvalid => '0', -- : IN std_logic := '0'; m_axi_bready => M_AXI_BREADY, -- : OUT std_logic; -- AXI Full/Lite Slave Read Channel (Write side) s_axi_arid => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_araddr => "00000000000000000000000000000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arlen => "00000000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arsize => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arburst => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arlock => "00", --(others => '0'), (others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arcache => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arprot => "000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arqos => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arregion => "0000", --(others => '0'), (others => '0'), -- : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); s_axi_aruser => "0", --(others => '0'), (others => '0'), -- : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axi_arvalid => '0', -- : IN std_logic := '0'; s_axi_arready => S_AXI_ARREADY, -- : OUT std_logic; s_axi_rid => S_AXI_RID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); s_axi_rdata => S_AXI_RDATA, -- : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0); s_axi_rresp => S_AXI_RRESP, -- : OUT std_logic_vector(2-1 DOWNTO 0); s_axi_rlast => S_AXI_RLAST, -- : OUT std_logic; s_axi_ruser => S_AXI_RUSER, -- : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0); s_axi_rvalid => S_AXI_RVALID, -- : OUT std_logic; s_axi_rready => '0', -- : IN std_logic := '0'; -- AXI Full/Lite Master Read Channel (Read side) m_axi_arid => M_AXI_ARID, -- : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); m_axi_araddr => M_AXI_ARADDR, -- : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0); m_axi_arlen => M_AXI_ARLEN, -- : OUT std_logic_vector(8-1 DOWNTO 0); m_axi_arsize => M_AXI_ARSIZE, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_arburst => M_AXI_ARBURST, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_arlock => M_AXI_ARLOCK, -- : OUT std_logic_vector(2-1 DOWNTO 0); m_axi_arcache => M_AXI_ARCACHE, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_arprot => M_AXI_ARPROT, -- : OUT std_logic_vector(3-1 DOWNTO 0); m_axi_arqos => M_AXI_ARQOS, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_arregion => M_AXI_ARREGION, -- : OUT std_logic_vector(4-1 DOWNTO 0); m_axi_aruser => M_AXI_ARUSER, -- : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0); m_axi_arvalid => M_AXI_ARVALID, -- : OUT std_logic; m_axi_arready => '0', -- : IN std_logic := '0'; m_axi_rid => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rresp => "00", --(others => '0'), -- : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rlast => '0', -- : IN std_logic := '0'; m_axi_ruser => "0", --(others => '0'), -- : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); m_axi_rvalid => '0', -- : IN std_logic := '0'; m_axi_rready => M_AXI_RREADY, -- : OUT std_logic; -- AXI Streaming Slave Signals (Write side) s_axis_tvalid => '0', -- : IN std_logic := '0'; s_axis_tready => S_AXIS_TREADY, -- : OUT std_logic; s_axis_tdata => "0000000000000000000000000000000000000000000000000000000000000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tstrb => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tkeep => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tlast => '0', -- : IN std_logic := '0'; s_axis_tid => "00000000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tdest => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); s_axis_tuser => "0000", --(others => '0'), -- : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- AXI Streaming Master Signals (Read side) m_axis_tvalid => M_AXIS_TVALID, -- : OUT std_logic; m_axis_tready => '0', -- : IN std_logic := '0'; m_axis_tdata => M_AXIS_TDATA, -- : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0); m_axis_tstrb => M_AXIS_TSTRB, -- : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0); m_axis_tkeep => M_AXIS_TKEEP, -- : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0); m_axis_tlast => M_AXIS_TLAST, -- : OUT std_logic; m_axis_tid => M_AXIS_TID, -- : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0); m_axis_tdest => M_AXIS_TDEST, -- : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0); m_axis_tuser => M_AXIS_TUSER, -- : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0); -- AXI Full/Lite Write Address Channel Signals axi_aw_injectsbiterr => '0', -- : IN std_logic := '0'; axi_aw_injectdbiterr => '0', -- : IN std_logic := '0'; axi_aw_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0'); axi_aw_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0'); axi_aw_data_count => AXI_AW_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0); axi_aw_wr_data_count => AXI_AW_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0); axi_aw_rd_data_count => AXI_AW_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0); axi_aw_sbiterr => AXI_AW_SBITERR, -- : OUT std_logic; axi_aw_dbiterr => AXI_AW_DBITERR, -- : OUT std_logic; axi_aw_overflow => AXI_AW_OVERFLOW, -- : OUT std_logic; axi_aw_underflow => AXI_AW_UNDERFLOW, -- : OUT std_logic; axi_aw_prog_full => AXI_AW_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_aw_prog_empty => AXI_AW_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Write Data Channel Signals axi_w_injectsbiterr => '0', -- : IN std_logic := '0'; axi_w_injectdbiterr => '0', -- : IN std_logic := '0'; axi_w_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_w_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_w_data_count => AXI_W_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0); axi_w_wr_data_count => AXI_W_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0); axi_w_rd_data_count => AXI_W_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0); axi_w_sbiterr => AXI_W_SBITERR, -- : OUT std_logic; axi_w_dbiterr => AXI_W_DBITERR, -- : OUT std_logic; axi_w_overflow => AXI_W_OVERFLOW, -- : OUT std_logic; axi_w_underflow => AXI_W_UNDERFLOW, -- : OUT std_logic; axi_w_prog_full => AXI_W_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_w_prog_empty => AXI_W_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Write Response Channel Signals axi_b_injectsbiterr => '0', -- : IN std_logic := '0'; axi_b_injectdbiterr => '0', -- : IN std_logic := '0'; axi_b_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0'); axi_b_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0'); axi_b_data_count => AXI_B_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0); axi_b_wr_data_count => AXI_B_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0); axi_b_rd_data_count => AXI_B_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0); axi_b_sbiterr => AXI_B_SBITERR, -- : OUT std_logic; axi_b_dbiterr => AXI_B_DBITERR, -- : OUT std_logic; axi_b_overflow => AXI_B_OVERFLOW, -- : OUT std_logic; axi_b_underflow => AXI_B_UNDERFLOW, -- : OUT std_logic; axi_b_prog_full => AXI_B_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_b_prog_empty => AXI_B_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Read Address Channel Signals axi_ar_injectsbiterr => '0', -- : IN std_logic := '0'; axi_ar_injectdbiterr => '0', -- : IN std_logic := '0'; axi_ar_prog_full_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0'); axi_ar_prog_empty_thresh => "0000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0'); axi_ar_data_count => AXI_AR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0); axi_ar_wr_data_count => AXI_AR_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0); axi_ar_rd_data_count => AXI_AR_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0); axi_ar_sbiterr => AXI_AR_SBITERR, -- : OUT std_logic; axi_ar_dbiterr => AXI_AR_DBITERR, -- : OUT std_logic; axi_ar_overflow => AXI_AR_OVERFLOW, -- : OUT std_logic; axi_ar_underflow => AXI_AR_UNDERFLOW, -- : OUT std_logic; axi_ar_prog_full => AXI_AR_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_ar_prog_empty => AXI_AR_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Full/Lite Read Data Channel Signals axi_r_injectsbiterr => '0', -- : IN std_logic := '0'; axi_r_injectdbiterr => '0', -- : IN std_logic := '0'; axi_r_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_r_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0'); axi_r_data_count => AXI_R_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0); axi_r_wr_data_count => AXI_R_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0); axi_r_rd_data_count => AXI_R_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0); axi_r_sbiterr => AXI_R_SBITERR, -- : OUT std_logic; axi_r_dbiterr => AXI_R_DBITERR, -- : OUT std_logic; axi_r_overflow => AXI_R_OVERFLOW, -- : OUT std_logic; axi_r_underflow => AXI_R_UNDERFLOW, -- : OUT std_logic; axi_r_prog_full => AXI_R_PROG_FULL, -- : OUT STD_LOGIC := '0'; axi_r_prog_empty => AXI_R_PROG_EMPTY, -- : OUT STD_LOGIC := '1'; -- AXI Streaming FIFO Related Signals axis_injectsbiterr => '0', -- : IN std_logic := '0'; axis_injectdbiterr => '0', -- : IN std_logic := '0'; axis_prog_full_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0'); axis_prog_empty_thresh => "0000000000", --(others => '0'), -- : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0'); axis_data_count => AXIS_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0); axis_wr_data_count => AXIS_WR_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0); axis_rd_data_count => AXIS_RD_DATA_COUNT, -- : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0); axis_sbiterr => AXIS_SBITERR, -- : OUT std_logic; axis_dbiterr => AXIS_DBITERR, -- : OUT std_logic; axis_overflow => AXIS_OVERFLOW, -- : OUT std_logic; axis_underflow => AXIS_UNDERFLOW, -- : OUT std_logic axis_prog_full => AXIS_PROG_FULL, -- : OUT STD_LOGIC := '0'; axis_prog_empty => AXIS_PROG_EMPTY -- : OUT STD_LOGIC := '1'; ); end implementation;

mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_0_0/blk_mem_gen_v8_1/blk_mem_gen_ecc_encoder.vhd

27

20893

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block Cqo+FjfIOIw/0Kghh877RN5JtWmUPj/KfIaTRt94dXWp8zshF20HfBCWrK0/KjFcQ6xaC5bYfJZ4 kTgDE7VoLA== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block P76DAxdsqqBm7Dhm+Xv4UBWtxeM3n7VV0uwUkGrQnJyruFJEvMXWtTIk68wS1svCurmxJblglPTM AUuHl8lZTHelg/xsbfqIjFFpkYurRbfQPaEBBncWEUkGXitk2MsCEJd1XKoy7X9zf5gkivM+Dtc/ HmQtcrnx7yMmBEFf0wU= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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mit

djmatt/VHDL-Lib

VHDL/Muxer/muxer.vhd

1

3482

---------------------------------------------------------------------------------------------------- -- muxer ---------------------------------------------------------------------------------------------------- -- Matthew Dallmeyer - [email protected] ---------------------------------------------------------------------------------------------------- -- PACKAGE ---------------------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library work; package muxer_pkg is --muxer componenet declaration component muxer is generic( INIT_SEL : std_logic_vector(1 downto 0) := b"10"); port( clk : in std_logic; clk_2x : in std_logic; rst : in std_logic; sig1 : in std_logic_vector; sig2 : in std_logic_vector; sigs : out std_logic_vector); end component; end package; ---------------------------------------------------------------------------------------------------- -- ENTITY ---------------------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; --This entity takes 2 input signals and interlaces them into 1 output signal. During development --it was determined that the clock inputs must be phase aligned for best results entity muxer is generic( INIT_SEL : std_logic_vector(1 downto 0) := b"10"); port( clk : in std_logic; clk_2x : in std_logic; rst : in std_logic; sig1 : in std_logic_vector; sig2 : in std_logic_vector; sigs : out std_logic_vector); end muxer; ---------------------------------------------------------------------------------------------------- -- ARCHITECTURE ---------------------------------------------------------------------------------------------------- architecture behave of muxer is signal sig1_reg : std_logic_vector(sig1'range) := (others => '0'); signal sig2_reg : std_logic_vector(sig2'range) := (others => '0'); signal selector : std_logic_vector(1 downto 0) := INIT_SEL; signal sigs_reg : std_logic_vector(sigs'range) := (others => '0'); begin --Register the inputs reg_in : process(clk) begin if(rising_edge(clk)) then if(rst = '1') then sig1_reg <= (others => '0'); sig2_reg <= (others => '0'); else sig1_reg <= sig1; sig2_reg <= sig2; end if; end if; end process; --Selection update_selection : process(clk_2x) begin if(rising_edge(clk_2x)) then if(rst = '1') then selector <= INIT_SEL; else selector <= std_logic_vector(rotate_left(unsigned(selector), 1)); end if; end if; end process; --Register the output reg_out : process(clk_2x) begin if(rising_edge(clk_2x)) then if(rst = '1') then sigs_reg <= (others => '0'); else case selector is when b"01" => sigs_reg <= sig1; when b"10" => sigs_reg <= sig2; when others => sigs_reg <= (others => '-'); end case; end if; end if; end process; sigs <= sigs_reg; end behave;

mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/proc_common_v4_0/hdl/src/vhdl/pf_counter_top.vhd

15

8369

------------------------------------------------------------------------------- -- $Id: pf_counter_top.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $ ------------------------------------------------------------------------------- -- pf_counter_top - entity/architecture pair ------------------------------------------------------------------------------- -- -- ************************************************************************* -- ** ** -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This text/file contains proprietary, confidential ** -- ** information of Xilinx, Inc., is distributed under ** -- ** license from Xilinx, Inc., and may be used, copied ** -- ** and/or disclosed only pursuant to the terms of a valid ** -- ** license agreement with Xilinx, Inc. Xilinx hereby ** -- ** grants you a license to use this text/file solely for ** -- ** design, simulation, implementation and creation of ** -- ** design files limited to Xilinx devices or technologies. ** -- ** Use with non-Xilinx devices or technologies is expressly ** -- ** prohibited and immediately terminates your license unless ** -- ** covered by a separate agreement. ** -- ** ** -- ** Xilinx is providing this design, code, or information ** -- ** "as-is" solely for use in developing programs and ** -- ** solutions for Xilinx devices, with no obligation on the ** -- ** part of Xilinx to provide support. By providing this design, ** -- ** code, or information as one possible implementation of ** -- ** this feature, application or standard, Xilinx is making no ** -- ** representation that this implementation is free from any ** -- ** claims of infringement. You are responsible for obtaining ** -- ** any rights you may require for your implementation. ** -- ** Xilinx expressly disclaims any warranty whatsoever with ** -- ** respect to the adequacy of the implementation, including ** -- ** but not limited to any warranties or representations that this ** -- ** implementation is free from claims of infringement, implied ** -- ** warranties of merchantability or fitness for a particular ** -- ** purpose. ** -- ** ** -- ** Xilinx products are not intended for use in life support ** -- ** appliances, devices, or systems. Use in such applications is ** -- ** expressly prohibited. ** -- ** ** -- ** Any modifications that are made to the Source Code are ** -- ** done at the users sole risk and will be unsupported. ** -- ** The Xilinx Support Hotline does not have access to source ** -- ** code and therefore cannot answer specific questions related ** -- ** to source HDL. The Xilinx Hotline support of original source ** -- ** code IP shall only address issues and questions related ** -- ** to the standard Netlist version of the core (and thus ** -- ** indirectly, the original core source). ** -- ** ** -- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** This copyright and support notice must be retained as part ** -- ** of this text at all times. ** -- ** ** -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: pf_counter_top.vhd -- -- Description: Implements parameterized up/down counter -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- pf_counter_top.vhd -- ------------------------------------------------------------------------------- -- Author: D. Thorpe -- Revision: $Revision: 1.1.4.1 $ -- Date: $Date: 2010/09/14 22:35:47 $ -- -- History: -- DET 2001-08-30 First Version -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Changed proc_common library version to v4_0 -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; --Use IEEE.numeric_std.all; library unisim; use unisim.vcomponents.all; library proc_common_v4_0; use proc_common_v4_0.pf_counter; ----------------------------------------------------------------------------- -- Entity section ----------------------------------------------------------------------------- entity pf_counter_top is generic ( C_COUNT_WIDTH : integer := 10 ); port ( Clk : in std_logic; Rst : in std_logic; Load_Enable : in std_logic; Load_value : in std_logic_vector(0 to C_COUNT_WIDTH-1); Count_Down : in std_logic; Count_Up : in std_logic; --Carry_Out : out std_logic; Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1) ); end entity pf_counter_top; ----------------------------------------------------------------------------- -- Architecture section ----------------------------------------------------------------------------- architecture implementation of pf_counter_top is Signal sig_cnt_enable : std_logic; Signal sig_cnt_up_n_dwn : std_logic; Signal sig_carry_out : std_logic; Signal sig_count_out : std_logic_vector(0 to C_COUNT_WIDTH-1); begin -- VHDL_RTL -- Misc signal assignments Count_Out <= sig_count_out; --Carry_Out <= sig_carry_Out; sig_cnt_enable <= Count_Up xor Count_Down; sig_cnt_up_n_dwn <= not(Count_Up); I_UP_DWN_COUNTER : entity proc_common_v4_0.pf_counter generic map ( C_COUNT_WIDTH => C_COUNT_WIDTH ) port map( Clk => Clk, -- : in std_logic; Rst => Rst, -- : in std_logic; Carry_Out => sig_carry_out, -- : out std_logic; Load_In => Load_value, -- : in std_logic_vector(0 to C_COUNT_WIDTH-1); Count_Enable => sig_cnt_enable, -- : in std_logic; Count_Load => Load_Enable, -- : in std_logic; Count_Down => sig_cnt_up_n_dwn,-- : in std_logic; Count_Out => sig_count_out -- : out std_logic_vector(0 to C_COUNT_WIDTH-1) ); end architecture implementation;

mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_1_1/blk_mem_gen_v8_1/blk_mem_gen_prim_width.vhd

27

70652

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mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_1_1/fifo_generator_v11_0/ramfifo/wr_dc_fwft_ext_as.vhd

19

13630

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block pabZO1I/O5UlEfYaQEPwd4l9eUai0bqYoMxFZDUmBPXyS95K3GW98Ld97MzJKAXXnSlf1PewGW2v 0RIeWd32HQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block MnYS98CLv6GUlLtXXj0MDq/aXJWBamrEeFXZFkhzX7OjMU68I3JzEc2/1UN3CHInfTII6cQBis+f MSPPkhHYfjWA/UnlZNCfIbUjCA7v4zzzEDOXLdUwHhey61M2PDbtjo4F0M+PSYsHQUE61FCJYZr6 +aBOwyo0CpKkCUVEbxg= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block qncW/Cwz6DQ02ZtEcvyp5WdAA4sItotGPpP0REUtLyqefQhCtJmFILcg4T0iyRUg7VuYEwIANO5+ QvHNNc39qIJv9lOesalgHBZQgvNRJnIdYWaRfS0GyacwI/2JQRwAkuAQstvDCp4RTc3l8lwP6/ls 9Kgq/wnF0FIDD2zIsqBFYPVau5gOg+E2Yv8daLhsLbgUNkGI+w4/OZjRbQGSUjwZLuzAjcC7dEzW IiD8iCe2E3P5aTpTA2tXeuvseQy8KOwVCxJQuur+f/bmnE2QrPi5PPQMRcOyc4ok7k5U/64SCKlJ oITfL/xIL/xwZa26tMPcLgkkx7p0G3RLvL/tVw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Dnf6vaqe/V3pNaiPDsCpL4mEkUhuRTF8jsptuAsYR5QlsF0hNdnCfK2+aKM5H69faCvd5mpbM0GP Pqz+qhNmOYPHdckgaTUGR5o/7QyV8YKLvzwfyDMqTu2isTv6FP6Q6welH2CNBnmC1/h5T7i+fy/Q rlaoXYJxfrB3B6n9clU= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block IMf8iBP4Q72XIQn7cHjsTbT2wNsnwrpqWy35OTpGthg9IgmIl2PQf4/c9imtaZPdkPVpIBywT+vW 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mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/proc_common_v4_0/hdl/src/vhdl/srl_fifo_rbu_f.vhd

15

16038

------------------------------------------------------------------------------- -- $Id: srl_fifo_rbu_f.vhd,v 1.1.4.2 2010/09/14 22:35:47 dougt Exp $ ------------------------------------------------------------------------------- -- srl_fifo_rbu_f - entity / architecture pair ------------------------------------------------------------------------------- -- -- ************************************************************************* -- ** ** -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This text/file contains proprietary, confidential ** -- ** information of Xilinx, Inc., is distributed under ** -- ** license from Xilinx, Inc., and may be used, copied ** -- ** and/or disclosed only pursuant to the terms of a valid ** -- ** license agreement with Xilinx, Inc. Xilinx hereby ** -- ** grants you a license to use this text/file solely for ** -- ** design, simulation, implementation and creation of ** -- ** design files limited to Xilinx devices or technologies. ** -- ** Use with non-Xilinx devices or technologies is expressly ** -- ** prohibited and immediately terminates your license unless ** -- ** covered by a separate agreement. ** -- ** ** -- ** Xilinx is providing this design, code, or information ** -- ** "as-is" solely for use in developing programs and ** -- ** solutions for Xilinx devices, with no obligation on the ** -- ** part of Xilinx to provide support. By providing this design, ** -- ** code, or information as one possible implementation of ** -- ** this feature, application or standard, Xilinx is making no ** -- ** representation that this implementation is free from any ** -- ** claims of infringement. You are responsible for obtaining ** -- ** any rights you may require for your implementation. ** -- ** Xilinx expressly disclaims any warranty whatsoever with ** -- ** respect to the adequacy of the implementation, including ** -- ** but not limited to any warranties or representations that this ** -- ** implementation is free from claims of infringement, implied ** -- ** warranties of merchantability or fitness for a particular ** -- ** purpose. ** -- ** ** -- ** Xilinx products are not intended for use in life support ** -- ** appliances, devices, or systems. Use in such applications is ** -- ** expressly prohibited. ** -- ** ** -- ** Any modifications that are made to the Source Code are ** -- ** done at the users sole risk and will be unsupported. ** -- ** The Xilinx Support Hotline does not have access to source ** -- ** code and therefore cannot answer specific questions related ** -- ** to source HDL. The Xilinx Hotline support of original source ** -- ** code IP shall only address issues and questions related ** -- ** to the standard Netlist version of the core (and thus ** -- ** indirectly, the original core source). ** -- ** ** -- ** Copyright (c) 2007-2010 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** This copyright and support notice must be retained as part ** -- ** of this text at all times. ** -- ** ** -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: srl_fifo_rbu_f.vhd -- -- Description: A small-to-medium depth FIFO with optional -- capability to back up and reread data. For -- data storage, the SRL elements native to the -- target FGPA family are used. If the FIFO depth -- exceeds the available depth of the SRL elements, -- then SRLs are cascaded and MUXFN elements are -- used to select the output of the appropriate SRL stage. -- -- Features: -- - Width and depth are arbitrary, but each doubling of -- depth, starting from the native SRL depth, adds -- a level of MUXFN. Generally, in performance-oriented -- applications, the fifo depth may need to be limited to -- not exceed the SRL cascade depth supported by local -- fast interconnect or the number of MUXFN levels. -- However, deeper fifos will correctly build. -- - Commands: read, write, and reread n. -- - Flags: empty and full. -- - The reread n command (executed by applying -- a non-zero value, n, to signal Num_To_Reread -- for one clock period) allows n -- previously read elements to be restored to the FIFO, -- limited, however, to the number of elements that have -- not been overwritten. (It is the user's responsibility -- to assure that the elements being restored are -- actually in the FIFO storage; once the depth of the -- FIFO has been written, the maximum number that can -- be restored is equal to the vacancy.) -- The reread capability does not cost extra LUTs or FFs. -- - Commands may be asserted simultaneously. -- However, if read and reread n are asserted -- simultaneously, only the read is carried out. -- - Overflow and underflow are detected and latched until -- Reset. The state of the FIFO is undefined during -- status of underflow or overflow. -- Underflow can occur only by reading the FIFO when empty. -- Overflow can occur either from a write, a reread n, -- or a combination of both that would result in more -- elements occupying the FIFO that its C_DEPTH. -- - Any of the signals FIFO_Full, Underflow, or Overflow -- left unconnected can be expected to be trimmed. -- - The Addr output is always one less than the current -- occupancy when the FIFO is non-empty, and is all ones -- otherwise. Therefore, the value <FIFO_Empty, Addr>-- -- i.e. FIFO_Empty concatenated on the left with Addr-- -- when taken as a signed value, is one less than the -- current occupancy. -- This information can be used to generate additional -- flags, if needed. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- srl_fifo_rbu_f.vhd -- dynshreg_f.vhd -- cntr_incr_decr_addn_f.vhd -- ------------------------------------------------------------------------------- -- Author: Farrell Ostler -- -- History: -- FLO 12/05/05 First Version. Derived from srl_fifo_rbu. -- ~~~~~~ -- FLO 2007-12-12 -- ^^^^^^ -- Using function clog2 now instead of log2 to eliminate superfluous warnings. -- ~~~~~~ -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Changed proc_common library version to v4_0 -- - Incorporated new disclaimer header -- ^^^^^^ -- FLO 2008-11-25 -- ^^^^^^ -- Changed to functionally equivalent code to generate FIFO_Full. The new code -- steers the current XST toward a better implementation. CR 496211. -- ~~~~~~ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- predecessor value by # clks: "*_p#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.UNSIGNED; use ieee.numeric_std.">="; use ieee.numeric_std.TO_UNSIGNED; library proc_common_v4_0; use proc_common_v4_0.proc_common_pkg.clog2; entity srl_fifo_rbu_f is generic ( C_DWIDTH : natural; C_DEPTH : positive := 16; C_FAMILY : string := "nofamily" ); port ( Clk : in std_logic; Reset : in std_logic; FIFO_Write : in std_logic; Data_In : in std_logic_vector(0 to C_DWIDTH-1); FIFO_Read : in std_logic; Data_Out : out std_logic_vector(0 to C_DWIDTH-1); FIFO_Full : out std_logic; FIFO_Empty : out std_logic; Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1); Num_To_Reread : in std_logic_vector(0 to clog2(C_DEPTH)-1); Underflow : out std_logic; Overflow : out std_logic ); end entity srl_fifo_rbu_f; architecture imp of srl_fifo_rbu_f is function bitwise_or(s: std_logic_vector) return std_logic is variable v: std_logic := '0'; begin for i in s'range loop v := v or s(i); end loop; return v; end bitwise_or; constant ADDR_BITS : integer := clog2(C_DEPTH); -- An extra bit will be carried as the empty flag. signal addr_i : std_logic_vector(ADDR_BITS downto 0); signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0); signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0); signal fifo_empty_i : std_logic; signal overflow_i : std_logic; signal underflow_i : std_logic; signal fifo_full_p1 : std_logic; begin fifo_empty_i <= addr_i(ADDR_BITS); Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0); FIFO_Empty <= fifo_empty_i; num_to_reread_zeroext <= '0' & Num_To_Reread; ---------------------------------------------------------------------------- -- The FIFO address counter. Addresses the next element to be read. -- All ones when the FIFO is empty. ---------------------------------------------------------------------------- CNTR_INCR_DECR_ADDN_F_I : entity proc_common_v4_0.cntr_incr_decr_addn_f generic map ( C_SIZE => ADDR_BITS + 1, C_FAMILY => C_FAMILY ) port map ( Clk => Clk, Reset => Reset, Incr => FIFO_Write, Decr => FIFO_Read, N_to_add => num_to_reread_zeroext, Cnt => addr_i, Cnt_p1 => addr_i_p1 ); ---------------------------------------------------------------------------- -- The dynamic shift register that holds the FIFO elements. ---------------------------------------------------------------------------- DYNSHREG_F_I : entity proc_common_v4_0.dynshreg_f generic map ( C_DEPTH => C_DEPTH, C_DWIDTH => C_DWIDTH, C_FAMILY => C_FAMILY ) port map ( Clk => Clk, Clken => FIFO_Write, Addr => addr_i(ADDR_BITS-1 downto 0), Din => Data_In, Dout => Data_Out ); ---------------------------------------------------------------------------- -- Full flag. ---------------------------------------------------------------------------- fifo_full_p1 <= '1' when ( addr_i_p1 = std_logic_vector( TO_UNSIGNED(C_DEPTH-1, ADDR_BITS+1) ) ) else '0'; FULL_PROCESS: process (Clk) begin if Clk'event and Clk='1' then if Reset='1' then FIFO_Full <= '0'; else FIFO_Full <= fifo_full_p1; end if; end if; end process; ---------------------------------------------------------------------------- -- Underflow detection. ---------------------------------------------------------------------------- UNDERFLOW_PROCESS: process (Clk) begin if Clk'event and Clk='1' then if Reset = '1' then underflow_i <= '0'; elsif underflow_i = '1' then underflow_i <= '1'; -- Underflow sticks until reset else underflow_i <= fifo_empty_i and FIFO_Read; end if; end if; end process; Underflow <= underflow_i; ---------------------------------------------------------------------------- -- Overflow detection. -- The only case of non-erroneous operation for which addr_i (including -- the high-order bit used as the empty flag) taken as an unsigned value -- may be greater than or equal to C_DEPTH is when the FIFO is empty. -- No overflow is possible when FIFO_Read, since Num_To_Reread is -- overriden in this case and the number elements can at most remain -- unchanged (that being when there is a simultaneous FIFO_Write). -- However, when there is no FIFO_Read and there is either a -- FIFO_Write or a restoration of one or more read elements, or both, then -- addr_i, extended by the carry-out bit, becoming greater than -- or equal to C_DEPTH indicates an overflow. ---------------------------------------------------------------------------- OVERFLOW_PROCESS: process (Clk) begin if Clk'event and Clk='1' then if Reset = '1' then overflow_i <= '0'; elsif overflow_i = '1' then overflow_i <= '1'; -- Overflow sticks until Reset elsif FIFO_Read = '0' and (FIFO_Write= '1' or bitwise_or(Num_To_Reread)='1') and UNSIGNED(addr_i_p1) >= C_DEPTH then overflow_i <= '1'; else overflow_i <= '0'; end if; end if; end process; Overflow <= overflow_i; end architecture imp;

mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/eval_timer.vhd

15

11230

------------------------------------------------------------------------------- -- $Id: eval_timer.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $ ------------------------------------------------------------------------------- -- eval_timer.vhd - entity/architecture pair ------------------------------------------------------------------------------- -- -- ************************************************************************* -- ** ** -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This text/file contains proprietary, confidential ** -- ** information of Xilinx, Inc., is distributed under ** -- ** license from Xilinx, Inc., and may be used, copied ** -- ** and/or disclosed only pursuant to the terms of a valid ** -- ** license agreement with Xilinx, Inc. Xilinx hereby ** -- ** grants you a license to use this text/file solely for ** -- ** design, simulation, implementation and creation of ** -- ** design files limited to Xilinx devices or technologies. ** -- ** Use with non-Xilinx devices or technologies is expressly ** -- ** prohibited and immediately terminates your license unless ** -- ** covered by a separate agreement. ** -- ** ** -- ** Xilinx is providing this design, code, or information ** -- ** "as-is" solely for use in developing programs and ** -- ** solutions for Xilinx devices, with no obligation on the ** -- ** part of Xilinx to provide support. By providing this design, ** -- ** code, or information as one possible implementation of ** -- ** this feature, application or standard, Xilinx is making no ** -- ** representation that this implementation is free from any ** -- ** claims of infringement. You are responsible for obtaining ** -- ** any rights you may require for your implementation. ** -- ** Xilinx expressly disclaims any warranty whatsoever with ** -- ** respect to the adequacy of the implementation, including ** -- ** but not limited to any warranties or representations that this ** -- ** implementation is free from claims of infringement, implied ** -- ** warranties of merchantability or fitness for a particular ** -- ** purpose. ** -- ** ** -- ** Xilinx products are not intended for use in life support ** -- ** appliances, devices, or systems. Use in such applications is ** -- ** expressly prohibited. ** -- ** ** -- ** Any modifications that are made to the Source Code are ** -- ** done at the users sole risk and will be unsupported. ** -- ** The Xilinx Support Hotline does not have access to source ** -- ** code and therefore cannot answer specific questions related ** -- ** to source HDL. The Xilinx Hotline support of original source ** -- ** code IP shall only address issues and questions related ** -- ** to the standard Netlist version of the core (and thus ** -- ** indirectly, the original core source). ** -- ** ** -- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** This copyright and support notice must be retained as part ** -- ** of this text at all times. ** -- ** ** -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: eval_timer.vhd -- Version: v1.00a -- Description: 40-bit counter that enables IP to be used in an evaluation -- mode. Once the counter expires, the eval_timeout signal -- asserts and can be used to reset the IP. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- eval_timer.vhd -- ------------------------------------------------------------------------------- -- Author: ALS -- History: -- ALS 09/12/01 -- Created from PCI eval timer -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Changed proc_common library version to v4_0 -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; library unisim; use unisim.all; library proc_common_v4_0; use proc_common_v4_0.proc_common_pkg.all; use proc_common_v4_0.all; ----------------------------------------------------------------------------- -- Entity section ----------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Definition of Generics: -- No generics -- -- Definition of Ports: -- Clk -- clock -- Rst -- active high reset -- Eval_timeout -- timer has expired ------------------------------------------------------------------------------- entity eval_timer is port ( Clk : in std_logic; Rst : in std_logic; Eval_timeout : out std_logic ); end entity eval_timer; ----------------------------------------------------------------------------- -- Architecture section ----------------------------------------------------------------------------- architecture imp of eval_timer is ----------------------------------------------------------------------------- -- Constant Declarations ----------------------------------------------------------------------------- constant NUM_BITS : integer := 8; ----------------------------------------------------------------------------- -- Signal Declarations ----------------------------------------------------------------------------- signal co : std_logic_vector(0 to 4); -- carry out signal ceo : std_logic_vector(0 to 4); -- count enable out signal ceo_d1 : std_logic_vector(0 to 4); -- registered count enable out signal zeros : std_logic_vector(NUM_BITS-1 downto 0); ----------------------------------------------------------------------------- -- Component Declarations ----------------------------------------------------------------------------- component Counter is generic( C_NUM_BITS : Integer := 9 ); port ( Clk : in std_logic; Rst : in std_logic; Load_In : in std_logic_vector(C_NUM_BITS - 1 downto 0); Count_Enable : in std_logic; Count_Load : in std_logic; Count_Down : in std_logic; Count_Out : out std_logic_vector(C_NUM_BITS - 1 downto 0); Carry_Out : out std_logic ); end component Counter; component FDRE port ( Q : out std_logic; C : in std_logic; CE : in std_logic; D : in std_logic; R : in std_logic ); end component; component FDR port ( Q : out std_logic; C : in std_logic; D : in std_logic; R : in std_logic ); end component; begin -- VHDL_RTL -- set the load value to zero zeros <= (others => '0'); -- Generate a 40-bit counter from 5 8-bit counters. Register the carry-out between counters -- to avoid timing problems. COUNTER_GEN: for i in 0 to 4 generate -- first 8-bit counter FIRST: if i = 0 generate COUNT_0_I: Counter generic map (C_NUM_BITS => NUM_BITS) port map ( Clk => Clk, Rst => Rst, Load_in => zeros, Count_Enable => '1', Count_Load => '0', Count_Down => '0', Count_out => open, Carry_Out => co(0) ); -- register the carry out to create the count enable out ceo(i) <= co(i); FDR_0_I: FDR port map ( Q => ceo_d1(i), C => Clk, D => ceo(i), R => Rst ); end generate FIRST; -- all other eight bit counters and the carry out register ALL_OTHERS: if i /= 0 generate COUNT_I: Counter generic map (C_NUM_BITS => NUM_BITS) port map ( Clk => Clk, Rst => Rst, Load_in => zeros, Count_Enable => ceo_d1(i-1), Count_Load => '0', Count_Down => '0', Count_out => open, Carry_Out => co(i) ); -- register the carry out AND the count enable to create the count enable out ceo(i) <= co(i) and ceo_d1(i-1); FDR_0_I: FDR port map ( Q => ceo_d1(i), C => Clk, D => ceo(i), R => Rst ); end generate ALL_OTHERS; end generate COUNTER_GEN; -- Using the final carry out as a CE, clock a '1' to assert and hold the eval_timeout signal. FDRE_I: FDRE port map ( Q => eval_timeout, --[out] C => Clk, --[in] CE => ceo_d1(4), --[in] D => '1', --[in] R => Rst --[in] ); end imp;

mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/blk_mem_gen_v8_1/blk_mem_axi_read_wrapper.vhd

27

57813

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mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_1_1/blk_mem_gen_v8_1/blk_mem_axi_read_wrapper.vhd

27

57813

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block gqDFw5NFAM6CTSTQpb6ewV0dkTDze+wC3QoGAxwxbjcNW9/DsOht+2F009+7g6jE2OnhGLtqTq+c HspFg2GBAA== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block OROCzcjj1wgCYlIqlabkGZopoXwccuhDPoDiFwbBlsbzl7flKX8tC5m+07o0XejIs9tQT70vCTz8 eor9UB573WqZyEwu6nS7RfReZTn9rXIEfFTmb5LNQYR53WQufFJWXVGGzbi12Azu0TUMNBykYjra GCJvYkOLjulS+N02/QU= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/fifo_generator_v11_0/builtin/fifo_generator_v11_0_builtin.vhd

19

49663

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block MxpeY9fwU4EddFSpExWohS5o9i8UPinR6kQv/f7rVpVjW9v1XPHFNv5NQBBqnxbGk/3GroOhKYHi zeZXd9sb8Q== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block genV68U/jEyVif/FXdfTRcDdNLXMaB4JkzDnEPHISJLebDAxHBqab4xQb3vzSMzS4EZxJxM3czS7 l6/Pa+/lUNH4iHFgH3/d34ImoXy9UrVsNWI4O1k56f8CO5JZkX0ENM2JUr2+jZNnrmepHCpz3pyr N2xknPLUPWomWT5p45Y= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 4dyOi6X0ND7jxJKLfQYpMzBQUnXRUvqhIlWd2qdz2OgGY9VUivCAp2239OkMu2rIWSpkdV3gd8Tn 4E+XnpveIi4nHAn1AdqR2yW6qJRqYI/CpvcG8E7ZhuUiWSAPiQ/jcxRmeyzLFdVhgEV4hed5vk+9 Qi0C1DUHqDNPvc06f+xZUSTzBSqXkxyUqGIa+j3ZmCrjq04hmRDILUEkjqmR0K0TOLNdsLd81gAl LqIfeuzK3hLcVWnnJG54RzS/q6bahPN8UaYhtJREcAC9BD1S+QEdDXRxFczj2T1LQBL5rSryR8bI LV6YqNl+85SCCMZmZV8Io9S7fDVIrhzNm4Kcmw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block PIdLn+S6alHzFt/ir7zZvMPdMeYQTL6BrWSuIGxsOazGugSdn7m2jtyII74LXXAGUQ0h11spxnUf W/HpoHHxg6pfmAZclwmfvLsFiVi0w0hNMmIWoR8TGPdAC93Y5+aRfoAJNuDfUDfLzdBM4O7G2ZFx YGYpvBcNhzcFFuSCCK4= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block KkGw0OOEdMUjhZKEmICwPPGTbEeQxk+K4HH0ah7Z5cm5dbbyDDJyn1CdBy6WY7ZD/SXDbXp0Ibi6 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mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/proc_common_v4_0/hdl/src/vhdl/or_gate_f.vhd

15

9178

------------------------------------------------------------------------------- -- $Id: or_gate_f.vhd,v 1.1.4.2 2010/09/14 22:35:46 dougt Exp $ ------------------------------------------------------------------------------- -- or_gate_f.vhd - entity/architecture pair ------------------------------------------------------------------------------- -- -- ************************************************************************* -- ** ** -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This text/file contains proprietary, confidential ** -- ** information of Xilinx, Inc., is distributed under ** -- ** license from Xilinx, Inc., and may be used, copied ** -- ** and/or disclosed only pursuant to the terms of a valid ** -- ** license agreement with Xilinx, Inc. Xilinx hereby ** -- ** grants you a license to use this text/file solely for ** -- ** design, simulation, implementation and creation of ** -- ** design files limited to Xilinx devices or technologies. ** -- ** Use with non-Xilinx devices or technologies is expressly ** -- ** prohibited and immediately terminates your license unless ** -- ** covered by a separate agreement. ** -- ** ** -- ** Xilinx is providing this design, code, or information ** -- ** "as-is" solely for use in developing programs and ** -- ** solutions for Xilinx devices, with no obligation on the ** -- ** part of Xilinx to provide support. By providing this design, ** -- ** code, or information as one possible implementation of ** -- ** this feature, application or standard, Xilinx is making no ** -- ** representation that this implementation is free from any ** -- ** claims of infringement. You are responsible for obtaining ** -- ** any rights you may require for your implementation. ** -- ** Xilinx expressly disclaims any warranty whatsoever with ** -- ** respect to the adequacy of the implementation, including ** -- ** but not limited to any warranties or representations that this ** -- ** implementation is free from claims of infringement, implied ** -- ** warranties of merchantability or fitness for a particular ** -- ** purpose. ** -- ** ** -- ** Xilinx products are not intended for use in life support ** -- ** appliances, devices, or systems. Use in such applications is ** -- ** expressly prohibited. ** -- ** ** -- ** Any modifications that are made to the Source Code are ** -- ** done at the users sole risk and will be unsupported. ** -- ** The Xilinx Support Hotline does not have access to source ** -- ** code and therefore cannot answer specific questions related ** -- ** to source HDL. The Xilinx Hotline support of original source ** -- ** code IP shall only address issues and questions related ** -- ** to the standard Netlist version of the core (and thus ** -- ** indirectly, the original core source). ** -- ** ** -- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** This copyright and support notice must be retained as part ** -- ** of this text at all times. ** -- ** ** -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: or_gate_f.vhd -- -- Description: OR gates. The width of each OR gate (C_OR_WIDTH) -- and the number of or gates (C_BUS_WIDTH) are -- parameterizable. -- -- Y(j) <= A(j) OR A(C_BUS_WIDTH+j) -- OR A(2*C_BUS_WIDTH+j) -- ... -- OR A((C_OR_WIDTH-1)*C_BUS_WIDTH+j), -- -- for 0 <= j < C_BUS_WIDTH -- -- If C_FAMILY is set (or left defaulted) to "nofamily" -- then the implementation will be by synthesis inference. -- Otherwise, a structural implementation optimized to -- C_FAMILY may be generated, depending on whether -- C_FAMILY supports the needed primtives. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- or_gate_f.vhd -- ------------------------------------------------------------------------------- -- Author: FLO -- History: -- FLO 2006-12-11 -- ^^^^^^ -- First Version, derived from or_gate by BLT -- ~~~~~~ -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Changed proc_common library version to v4_0 -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library proc_common_v4_0; ------------------------------------------------------------------------------- -- Definition of Generics: -- C_OR_WIDTH -- Which Xilinx FPGA family to target when -- syntesizing, affect the RLOC string values -- C_BUS_WIDTH -- Which Y position the RLOC should start from -- -- Definition of Ports: -- A -- Input. Input buses are concatenated together to -- form input A. Example: to OR buses R, S, and T, -- assign A <= R & S & T; -- Y -- Output. Same width as input buses. -- ------------------------------------------------------------------------------- entity or_gate_f is generic ( C_OR_WIDTH : natural := 17; C_BUS_WIDTH : natural := 1; C_FAMILY : string := "nofamily" ); port ( A : in std_logic_vector(0 to C_OR_WIDTH*C_BUS_WIDTH-1); Y : out std_logic_vector(0 to C_BUS_WIDTH-1) ); end entity or_gate_f; architecture imp of or_gate_f is ------------------------------------------------------------------------------- -- Component Declarations ------------------------------------------------------------------------------- signal test : std_logic_vector(0 to C_BUS_WIDTH-1); ------------------------------------------------------------------------------- -- Begin architecture ------------------------------------------------------------------------------- begin BUS_WIDTH_FOR_GEN: for i in 0 to C_BUS_WIDTH-1 generate signal in_Bus : std_logic_vector(0 to C_OR_WIDTH-1); begin ORDER_INPUT_BUS_PROCESS: process( A ) is begin for k in 0 to C_OR_WIDTH-1 loop in_Bus(k) <= A(k*C_BUS_WIDTH+i); end loop; end process ORDER_INPUT_BUS_PROCESS; OR_BITS_I: entity proc_common_v4_0.or_muxcy_f generic map ( C_NUM_BITS => C_OR_WIDTH, C_FAMILY => C_FAMILY ) port map ( In_bus => in_Bus, --[in] Or_out => Y(i) --[out] ); end generate BUS_WIDTH_FOR_GEN; end architecture imp;

mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/ipif_mirror128.vhd

15

17011

--SINGLE_FILE_TAG ------------------------------------------------------------------------------- -- $Id: ipif_mirror128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $ ------------------------------------------------------------------------------- -- ipif_mirror128 - entity/architecture pair ------------------------------------------------------------------------------- -- -- ************************************************************************* -- ** ** -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This text/file contains proprietary, confidential ** -- ** information of Xilinx, Inc., is distributed under ** -- ** license from Xilinx, Inc., and may be used, copied ** -- ** and/or disclosed only pursuant to the terms of a valid ** -- ** license agreement with Xilinx, Inc. Xilinx hereby ** -- ** grants you a license to use this text/file solely for ** -- ** design, simulation, implementation and creation of ** -- ** design files limited to Xilinx devices or technologies. ** -- ** Use with non-Xilinx devices or technologies is expressly ** -- ** prohibited and immediately terminates your license unless ** -- ** covered by a separate agreement. ** -- ** ** -- ** Xilinx is providing this design, code, or information ** -- ** "as-is" solely for use in developing programs and ** -- ** solutions for Xilinx devices, with no obligation on the ** -- ** part of Xilinx to provide support. By providing this design, ** -- ** code, or information as one possible implementation of ** -- ** this feature, application or standard, Xilinx is making no ** -- ** representation that this implementation is free from any ** -- ** claims of infringement. You are responsible for obtaining ** -- ** any rights you may require for your implementation. ** -- ** Xilinx expressly disclaims any warranty whatsoever with ** -- ** respect to the adequacy of the implementation, including ** -- ** but not limited to any warranties or representations that this ** -- ** implementation is free from claims of infringement, implied ** -- ** warranties of merchantability or fitness for a particular ** -- ** purpose. ** -- ** ** -- ** Xilinx products are not intended for use in life support ** -- ** appliances, devices, or systems. Use in such applications is ** -- ** expressly prohibited. ** -- ** ** -- ** Any modifications that are made to the Source Code are ** -- ** done at the users sole risk and will be unsupported. ** -- ** The Xilinx Support Hotline does not have access to source ** -- ** code and therefore cannot answer specific questions related ** -- ** to source HDL. The Xilinx Hotline support of original source ** -- ** code IP shall only address issues and questions related ** -- ** to the standard Netlist version of the core (and thus ** -- ** indirectly, the original core source). ** -- ** ** -- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** This copyright and support notice must be retained as part ** -- ** of this text at all times. ** -- ** ** -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: ipif_steer128.vhd -- Version: v1.00b -- Description: Read and Write Steering logic for IPIF -- -- For writes, this logic mirrors data from the master with -- the smaller bus width to the correct byte lanes of the -- larger IPIF devices. The BE signals are also mirrored. -- -- For reads, the Decode_size signal determines how read -- data is steered onto the byte lanes. To simplify the -- logic, the read data is mirrored onto the entire data -- bus, insuring that the lanes corrsponding to the BE's -- have correct data. -- -- -- ------------------------------------------------------------------------------- -- Structure: -- -- ipif_steer128.vhd -- ------------------------------------------------------------------------------- -- Author: Gary Burch -- History: -- GAB 10-10-2008 -- First version -- ^^^^^^ -- First version of IPIF mirror logic. -- ~~~~~~ -- -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_cmb" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; ------------------------------------------------------------------------------- -- Port declarations -- generic definitions: -- C_DWIDTH : integer := width of IPIF Slave -- C_SMALLEST : integer := width of smallest Master (not access size) -- that will access the IPIF Slave -- C_AWIDTH : integer := width of the host address bus attached to -- the IPIF -- port definitions: -- Wr_Data_In : in Write Data In (from host data bus) -- Rd_Data_In : in Read Data In (from IPIC data bus) -- Addr : in Address bus from host address bus -- BE_In : in Byte Enables In from host side -- Decode_size : in Size of Master accessing slave -- Size indication (Decode_size) -- 00 - 32-Bit Master -- 01 - 64-Bit Master -- 10 - 128-Bit Master -- 11 - 256-Bit Master (Not Support) -- -- Wr_Data_Out : out Write Data Out (to IPIF data bus) -- Rd_Data_Out : out Read Data Out (to host data bus) -- BE_Out : out Byte Enables Out to IPIF side -- ------------------------------------------------------------------------------- entity ipif_mirror128 is generic ( C_DWIDTH : integer := 32; -- 64, 128 (Slave Dwidth) C_SMALLEST : integer := 32; -- 32, 64, 128 (Smallest Master) C_AWIDTH : integer := 32 ); port ( Wr_Addr : in std_logic_vector(0 to C_AWIDTH-1); Wr_Size : in std_logic_vector(0 to 1); Rd_Addr : in std_logic_vector(0 to C_AWIDTH-1); Rd_Size : in std_logic_vector(0 to 1); Wr_Data_In : in std_logic_vector(0 to C_DWIDTH-1); Rd_Data_In : in std_logic_vector(0 to C_DWIDTH-1); BE_In : in std_logic_vector(0 to C_DWIDTH/8-1); Wr_Data_Out : out std_logic_vector(0 to C_DWIDTH-1); Rd_Data_Out : out std_logic_vector(0 to C_DWIDTH-1); BE_Out : out std_logic_vector(0 to C_DWIDTH/8-1) ); end entity ipif_mirror128; ------------------------------------------------------------------------------- -- Architecture section ------------------------------------------------------------------------------- architecture IMP of ipif_mirror128 is ------------------------------------------------------------------------------- -- Begin architecture ------------------------------------------------------------------------------- begin -- architecture IMP GEN_SAME: if C_DWIDTH <= C_SMALLEST generate Wr_Data_Out <= Wr_Data_In; BE_Out <= BE_In; Rd_Data_Out <= Rd_Data_In; end generate GEN_SAME; ------------------------------------------------------------------------------- -- Write Data Mirroring ------------------------------------------------------------------------------- --------------------- -- 64 Bit Support -- --------------------- GEN_WR_64_32: if C_DWIDTH = 64 and C_SMALLEST = 32 generate signal addr_bits : std_logic; begin CONNECT_PROC: process (addr_bits,Wr_Addr,Wr_Data_In,BE_In,Wr_Size) begin Wr_Data_Out <= Wr_Data_In; BE_Out <= BE_In; addr_bits <= Wr_Addr(C_AWIDTH-3); --a29 case addr_bits is when '0' => case Wr_Size is when "00" => -- 32-Bit Master BE_Out(4 to 7) <= (others => '0'); when others => null; end case; when '1' => case Wr_Size is when "00" => -- 32-Bit Master Wr_Data_Out(32 to 63) <= Wr_Data_In(0 to 31); BE_Out(4 to 7) <= BE_In(0 to 3); BE_Out(0 to 3) <= (others => '0'); when others => null; end case; when others => null; end case; end process CONNECT_PROC; end generate GEN_WR_64_32; --------------------- -- 128 Bit Support -- --------------------- GEN_WR_128_32: if C_DWIDTH = 128 and C_SMALLEST = 32 generate signal addr_bits : std_logic_vector(0 to 1); begin CONNECT_PROC: process (addr_bits,Wr_Addr,Wr_Data_In,BE_In,Wr_Size) begin Wr_Data_Out <= Wr_Data_In; BE_Out <= BE_In; addr_bits <= Wr_Addr(C_AWIDTH-4 to C_AWIDTH-3); case addr_bits is when "00" => --0 case Wr_Size is when "00" => -- 32-Bit Master BE_Out(4 to 15) <= (others => '0'); when "01" => -- 64-Bit Master BE_Out(8 to 15) <= (others => '0'); when others => null; end case; when "01" => --4 case Wr_Size is when "00" => -- 32-Bit Master Wr_Data_Out(32 to 63) <= Wr_Data_In(0 to 31); BE_Out(4 to 7) <= BE_In(0 to 3); BE_Out(0 to 3) <= (others => '0'); BE_Out(8 to 15) <= (others => '0'); when others => null; end case; when "10" => --8 case Wr_Size is when "00" => -- 32-Bit Master Wr_Data_Out(64 to 95) <= Wr_Data_In(0 to 31); BE_Out(8 to 11) <= BE_In(0 to 3); BE_Out(0 to 7) <= (others => '0'); BE_Out(12 to 15) <= (others => '0'); when "01" => -- 64-Bit Master Wr_Data_Out(64 to 127) <= Wr_Data_In(0 to 63); BE_Out(8 to 15) <= BE_In(0 to 7); BE_Out(0 to 7) <= (others => '0'); when others => null; end case; when "11" => --C case Wr_Size is when "00" => --32-Bit Master Wr_Data_Out(96 to 127) <= Wr_Data_In(0 to 31); BE_Out(12 to 15) <= BE_In(0 to 3); BE_Out(0 to 11) <= (others => '0'); when "01" => --64-Bit Master Wr_Data_Out(64 to 127) <= Wr_Data_In(0 to 63); BE_Out(8 to 15) <= BE_In(0 to 7); BE_Out(0 to 7) <= (others => '0'); when others => null; end case; when others => null; end case; end process CONNECT_PROC; end generate GEN_WR_128_32; GEN_WR_128_64: if C_DWIDTH = 128 and C_SMALLEST = 64 generate signal addr_bits : std_logic; begin CONNECT_PROC: process (addr_bits,Wr_Addr,Wr_Data_In,BE_In,Wr_Size) begin Wr_Data_Out <= Wr_Data_In; BE_Out <= BE_In; addr_bits <= Wr_Addr(C_AWIDTH-4); case addr_bits is when '0' => case Wr_Size is when "01" => -- 64-Bit Master BE_Out(8 to 15) <= (others => '0'); when others => null; end case; when '1' => --8 case Wr_Size is when "01" => -- 64-Bit Master Wr_Data_Out(64 to 127) <= Wr_Data_In(0 to 63); BE_Out(8 to 15) <= BE_In(0 to 7); BE_Out(0 to 7) <= (others => '0'); when others => null; end case; when others => null; end case; end process CONNECT_PROC; end generate GEN_WR_128_64; ------------------------------------------------------------------------------- -- Read Data Steering ------------------------------------------------------------------------------- --------------------- -- 64 Bit Support -- --------------------- GEN_RD_64_32: if C_DWIDTH = 64 and C_SMALLEST = 32 generate signal addr_bits : std_logic; begin CONNECT_PROC: process (addr_bits,Rd_Addr,Rd_Data_In,Rd_Size) begin Rd_Data_Out <= Rd_Data_In; addr_bits <= Rd_Addr(C_AWIDTH-3); --a29 case addr_bits is when '1' => case Rd_Size is when "00" => -- 32-Bit Master Rd_Data_Out(0 to 31) <= Rd_Data_In(32 to 63); when others => null; end case; when others => null; end case; end process CONNECT_PROC; end generate GEN_RD_64_32; --------------------- -- 128 Bit Support -- --------------------- GEN_RD_128_32: if C_DWIDTH = 128 and C_SMALLEST = 32 generate signal addr_bits : std_logic_vector(0 to 1); begin CONNECT_PROC: process (addr_bits,Rd_Addr,Rd_Data_In,Rd_Size) begin Rd_Data_Out <= Rd_Data_In; addr_bits <= Rd_Addr(C_AWIDTH-4 to C_AWIDTH-3); case addr_bits is when "01" => --4 case Rd_Size is when "00" => -- 32-Bit Master Rd_Data_Out(0 to 31) <= Rd_Data_In(32 to 63); when others => null; end case; when "10" => --8 case Rd_Size is when "00" => -- 32-Bit Master Rd_Data_Out(0 to 31) <= Rd_Data_In(64 to 95); when "01" => -- 64-Bit Master Rd_Data_Out(0 to 63) <= Rd_Data_In(64 to 127); when others => null; end case; when "11" => --C case Rd_Size is when "00" => --32-Bit Master Rd_Data_Out(0 to 31) <= Rd_Data_In(96 to 127); when "01" => --64-Bit Master Rd_Data_Out(0 to 63) <= Rd_Data_In(64 to 127); when others => null; end case; when others => null; end case; end process CONNECT_PROC; end generate GEN_RD_128_32; GEN_RD_128_64: if C_DWIDTH = 128 and C_SMALLEST = 64 generate signal addr_bits : std_logic; begin CONNECT_PROC: process (addr_bits,Rd_Addr,Rd_Data_In,Rd_Size) begin Rd_Data_Out <= Rd_Data_In; addr_bits <= Rd_Addr(C_AWIDTH-4); case addr_bits is when '1' => --8 case Rd_Size is when "01" => -- 64-Bit Master Rd_Data_Out(0 to 63) <= Rd_Data_In(64 to 127); when others => null; end case; when others => null; end case; end process CONNECT_PROC; end generate GEN_RD_128_64; end architecture IMP;

mit

djmatt/VHDL-Lib

VHDL/Muxer/demuxer.vhd

1

4036

---------------------------------------------------------------------------------------------------- -- demuxer ---------------------------------------------------------------------------------------------------- -- Matthew Dallmeyer - [email protected] ---------------------------------------------------------------------------------------------------- -- PACKAGE ---------------------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library work; package demuxer_pkg is --demuxer componenet declaration component demuxer is generic( INIT_SEL : std_logic_vector(1 downto 0) := b"01"); port( clk : in std_logic; clk_2x : in std_logic; rst : in std_logic; sigs : in std_logic_vector; sig1 : out std_logic_vector; sig2 : out std_logic_vector); end component; end package; ---------------------------------------------------------------------------------------------------- -- ENTITY ---------------------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; --This entity takes 2 input signals and interlaces them into 1 output signal. During development --it was determined that the clock inputs must be phase aligned for best results entity demuxer is generic( INIT_SEL : std_logic_vector(1 downto 0) := b"01"); port( clk : in std_logic; clk_2x : in std_logic; rst : in std_logic; sigs : in std_logic_vector; sig1 : out std_logic_vector; sig2 : out std_logic_vector); end demuxer; ---------------------------------------------------------------------------------------------------- -- ARCHITECTURE ---------------------------------------------------------------------------------------------------- architecture behave of demuxer is signal sigs_reg : std_logic_vector(sig1'range) := (others => '0'); signal selector : std_logic_vector(INIT_SEL'range) := INIT_SEL; signal sel1 : std_logic_vector(sig1'range) := (others => '0'); signal sel2 : std_logic_vector(sig2'range) := (others => '0'); signal selx : std_logic_vector(sig1'range) := (others => '0'); signal sig1_reg : std_logic_vector(sig1'range) := (others => '0'); signal sig2_reg : std_logic_vector(sig2'range) := (others => '0'); begin --Register the input reg_in : process(clk_2x) begin if(rising_edge(clk_2x)) then if(rst = '1') then sigs_reg <= (others => '0'); else sigs_reg <= sigs; end if; end if; end process; --Selection update_selection : process(clk_2x) begin if(rising_edge(clk_2x)) then if(rst = '1') then selector <= INIT_SEL; else selector <= std_logic_vector(rotate_right(unsigned(selector), 1)); end if; end if; end process; --Register the selection reg_sel : process(clk_2x) begin if(rising_edge(clk_2x)) then if(rst = '1') then sel1 <= (others => '0'); sel2 <= (others => '0'); else case selector is when b"01" => sel1 <= sigs; when b"10" => sel2 <= sigs; when others => selx <= sigs; end case; end if; end if; end process; --Register the output reg_out : process(clk) begin if(rising_edge(clk)) then if(rst = '1') then sig1_reg <= (others => '0'); sig2_reg <= (others => '0'); else sig1_reg <= sel1; sig2_reg <= sel2; end if; end if; end process; sig1 <= sig1_reg; sig2 <= sig2_reg; end behave;

mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_0_0/fifo_generator_v11_0/builtin/logic_builtin.vhd

19

30579

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mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/proc_common_v4_0/hdl/src/vhdl/srl_fifo.vhd

15

11841

------------------------------------------------------------------------------- -- $Id: srl_fifo.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $ ------------------------------------------------------------------------------- -- SRL_FIFO entity and architecture ------------------------------------------------------------------------------- -- -- ************************************************************************* -- ** ** -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This text/file contains proprietary, confidential ** -- ** information of Xilinx, Inc., is distributed under ** -- ** license from Xilinx, Inc., and may be used, copied ** -- ** and/or disclosed only pursuant to the terms of a valid ** -- ** license agreement with Xilinx, Inc. Xilinx hereby ** -- ** grants you a license to use this text/file solely for ** -- ** design, simulation, implementation and creation of ** -- ** design files limited to Xilinx devices or technologies. ** -- ** Use with non-Xilinx devices or technologies is expressly ** -- ** prohibited and immediately terminates your license unless ** -- ** covered by a separate agreement. ** -- ** ** -- ** Xilinx is providing this design, code, or information ** -- ** "as-is" solely for use in developing programs and ** -- ** solutions for Xilinx devices, with no obligation on the ** -- ** part of Xilinx to provide support. By providing this design, ** -- ** code, or information as one possible implementation of ** -- ** this feature, application or standard, Xilinx is making no ** -- ** representation that this implementation is free from any ** -- ** claims of infringement. You are responsible for obtaining ** -- ** any rights you may require for your implementation. ** -- ** Xilinx expressly disclaims any warranty whatsoever with ** -- ** respect to the adequacy of the implementation, including ** -- ** but not limited to any warranties or representations that this ** -- ** implementation is free from claims of infringement, implied ** -- ** warranties of merchantability or fitness for a particular ** -- ** purpose. ** -- ** ** -- ** Xilinx products are not intended for use in life support ** -- ** appliances, devices, or systems. Use in such applications is ** -- ** expressly prohibited. ** -- ** ** -- ** Any modifications that are made to the Source Code are ** -- ** done at the users sole risk and will be unsupported. ** -- ** The Xilinx Support Hotline does not have access to source ** -- ** code and therefore cannot answer specific questions related ** -- ** to source HDL. The Xilinx Hotline support of original source ** -- ** code IP shall only address issues and questions related ** -- ** to the standard Netlist version of the core (and thus ** -- ** indirectly, the original core source). ** -- ** ** -- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** This copyright and support notice must be retained as part ** -- ** of this text at all times. ** -- ** ** -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: srl_fifo.vhd -- -- Description: -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- srl_fifo.vhd -- ------------------------------------------------------------------------------- -- Author: goran -- Revision: $Revision: 1.1.4.1 $ -- Date: $Date: 2010/09/14 22:35:47 $ -- -- History: -- goran 2001-05-11 First Version -- KC 2001-06-20 Added Addr as an output port, for use as an occupancy -- value -- -- DCW 2002-03-12 Structural implementation of synchronous reset for -- Data_Exists DFF (using FDR) -- jam 2002-04-12 added C_XON generic for mixed vhdl/verilog sims -- -- als 2002-04-18 added default for XON generic in SRL16E, FDRE, and FDR -- component declarations -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; library unisim; use unisim.all; entity SRL_FIFO is generic ( C_DATA_BITS : natural := 8; C_DEPTH : natural := 16; C_XON : boolean := false ); port ( Clk : in std_logic; Reset : in std_logic; FIFO_Write : in std_logic; Data_In : in std_logic_vector(0 to C_DATA_BITS-1); FIFO_Read : in std_logic; Data_Out : out std_logic_vector(0 to C_DATA_BITS-1); FIFO_Full : out std_logic; Data_Exists : out std_logic; Addr : out std_logic_vector(0 to 3) -- Added Addr as a port ); end entity SRL_FIFO; architecture IMP of SRL_FIFO is component SRL16E is -- pragma translate_off generic ( INIT : bit_vector := X"0000" ); -- pragma translate_on port ( CE : in std_logic; D : in std_logic; Clk : in std_logic; A0 : in std_logic; A1 : in std_logic; A2 : in std_logic; A3 : in std_logic; Q : out std_logic); end component SRL16E; component LUT4 generic( INIT : bit_vector := X"0000" ); port ( O : out std_logic; I0 : in std_logic; I1 : in std_logic; I2 : in std_logic; I3 : in std_logic); end component; component MULT_AND port ( I0 : in std_logic; I1 : in std_logic; LO : out std_logic); end component; component MUXCY_L port ( DI : in std_logic; CI : in std_logic; S : in std_logic; LO : out std_logic); end component; component XORCY port ( LI : in std_logic; CI : in std_logic; O : out std_logic); end component; component FDRE is port ( Q : out std_logic; C : in std_logic; CE : in std_logic; D : in std_logic; R : in std_logic); end component FDRE; component FDR is port ( Q : out std_logic; C : in std_logic; D : in std_logic; R : in std_logic); end component FDR; signal addr_i : std_logic_vector(0 to 3); signal buffer_Full : std_logic; signal buffer_Empty : std_logic; signal next_Data_Exists : std_logic; signal data_Exists_I : std_logic; signal valid_Write : std_logic; signal hsum_A : std_logic_vector(0 to 3); signal sum_A : std_logic_vector(0 to 3); signal addr_cy : std_logic_vector(0 to 4); begin -- architecture IMP buffer_Full <= '1' when (addr_i = "1111") else '0'; FIFO_Full <= buffer_Full; buffer_Empty <= '1' when (addr_i = "0000") else '0'; next_Data_Exists <= (data_Exists_I and not buffer_Empty) or (buffer_Empty and FIFO_Write) or (data_Exists_I and not FIFO_Read); Data_Exists_DFF : FDR port map ( Q => data_Exists_I, -- [out std_logic] C => Clk, -- [in std_logic] D => next_Data_Exists, -- [in std_logic] R => Reset); -- [in std_logic] Data_Exists <= data_Exists_I; valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full); addr_cy(0) <= valid_Write; Addr_Counters : for I in 0 to 3 generate hsum_A(I) <= (FIFO_Read xor addr_i(I)) and (FIFO_Write or not buffer_Empty); MUXCY_L_I : MUXCY_L port map ( DI => addr_i(I), -- [in std_logic] CI => addr_cy(I), -- [in std_logic] S => hsum_A(I), -- [in std_logic] LO => addr_cy(I+1)); -- [out std_logic] XORCY_I : XORCY port map ( LI => hsum_A(I), -- [in std_logic] CI => addr_cy(I), -- [in std_logic] O => sum_A(I)); -- [out std_logic] FDRE_I : FDRE port map ( Q => addr_i(I), -- [out std_logic] C => Clk, -- [in std_logic] CE => data_Exists_I, -- [in std_logic] D => sum_A(I), -- [in std_logic] R => Reset); -- [in std_logic] end generate Addr_Counters; FIFO_RAM : for I in 0 to C_DATA_BITS-1 generate SRL16E_I : SRL16E -- pragma translate_off generic map ( INIT => x"0000") -- pragma translate_on port map ( CE => valid_Write, -- [in std_logic] D => Data_In(I), -- [in std_logic] Clk => Clk, -- [in std_logic] A0 => addr_i(0), -- [in std_logic] A1 => addr_i(1), -- [in std_logic] A2 => addr_i(2), -- [in std_logic] A3 => addr_i(3), -- [in std_logic] Q => Data_Out(I)); -- [out std_logic] end generate FIFO_RAM; ------------------------------------------------------------------------------- -- INT_ADDR_PROCESS ------------------------------------------------------------------------------- -- This process assigns the internal address to the output port ------------------------------------------------------------------------------- INT_ADDR_PROCESS:process (addr_i) begin -- process Addr <= addr_i; end process; end architecture IMP;

mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_1_1/fifo_generator_v11_0/ramfifo/wr_dc_as.vhd

19

10866

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mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_0_0/fifo_generator_v11_0/common/wr_pf_as.vhd

19

27402

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block e5HXux03McEJscFg80ZeuZznrIJptNO1SFQrz1pWkRP7P3QoqpS2mJZRj5k487CXMg1LSvaDqmT2 OL7PFCCTiQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block hgCd2yd1Ey3kW4Xi8EYui71ziVJlfu+yPA/iSZYYtw01d1xCQQbb29qdxk14t+CL2ulbT/AG/Tph KVRTNfPiGK79TWiKACghNYtvZsEbOSiWp2tzfhZzsTJKt6Q/Tnk5KS0q9lShCg5S46ZxNmKbnoII YTwtWH6VQAWKrWw0gQI= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_auto_pc_3/fifo_generator_v11_0/common/wr_pf_as.vhd

19

27402

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block e5HXux03McEJscFg80ZeuZznrIJptNO1SFQrz1pWkRP7P3QoqpS2mJZRj5k487CXMg1LSvaDqmT2 OL7PFCCTiQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block hgCd2yd1Ey3kW4Xi8EYui71ziVJlfu+yPA/iSZYYtw01d1xCQQbb29qdxk14t+CL2ulbT/AG/Tph KVRTNfPiGK79TWiKACghNYtvZsEbOSiWp2tzfhZzsTJKt6Q/Tnk5KS0q9lShCg5S46ZxNmKbnoII YTwtWH6VQAWKrWw0gQI= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/fifo_generator_v11_0/common/wr_pf_as.vhd

19

27402

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block e5HXux03McEJscFg80ZeuZznrIJptNO1SFQrz1pWkRP7P3QoqpS2mJZRj5k487CXMg1LSvaDqmT2 OL7PFCCTiQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block hgCd2yd1Ey3kW4Xi8EYui71ziVJlfu+yPA/iSZYYtw01d1xCQQbb29qdxk14t+CL2ulbT/AG/Tph KVRTNfPiGK79TWiKACghNYtvZsEbOSiWp2tzfhZzsTJKt6Q/Tnk5KS0q9lShCg5S46ZxNmKbnoII YTwtWH6VQAWKrWw0gQI= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/fifo_generator_v11_0/builtin/clk_x_pntrs_builtin.vhd

19

43418

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block rMj+x3ocDbJ+0HvlMPtFLLYN4V3iOWmu0i3VYcvwPU8r9dUqilqv5BoOperD1z/j12cu4ait0bNC TvgieQY6qg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block LiFkBwHJvbvIRsrs7TuS9x+hbpgzWqPRKAN+86jD7W/DWOy2HiTI+Pr3kejl0F7PQ/wd2Tf3u0hB l5PFI7Uciy5uXiQA7fDmYLdPcNoMNQWm9hohp6Q8wB4H3kSwMFgjlrwYcv97jBF9K/DD+f6kjMEJ pjxxREwM6oJfyPhyhBI= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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mit

djmatt/VHDL-Lib

VHDL/FIR_Filter/tb_sparse_fir_filter.vhd

1

3105

-------------------------------------------------------------------------------------------------- -- FIR Filter Testbench -------------------------------------------------------------------------------------------------- -- Matthew Dallmeyer - [email protected] -------------------------------------------------------------------------------------------------- -- ENTITY -------------------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; use work.tb_clockgen_pkg.all; use work.tb_read_csv_pkg.all; use work.tb_write_csv_pkg.all; use work.dsp_pkg.all; use work.sparse_fir_filter_pkg.all; --This module is a test-bench for simulating the fir filter entity tb_sparse_fir_filter is end tb_sparse_fir_filter; -------------------------------------------------------------------------------------------------- -- ARCHITECTURE -------------------------------------------------------------------------------------------------- architecture sim of tb_sparse_fir_filter is constant INPUT_FILE : string := "X:\Education\Masters Thesis\matlab\sparse_fir_filter\chirp.csv"; -- constant TEST_FILTER : coefficient_array := LOW_PASS_21; -- constant OUTPUT_FILE : string -- := "X:\Education\Masters Thesis\matlab\sparse_fir_filter\chirp_lowpass21.csv"; -- constant TEST_FILTER : coefficient_array := HIGH_PASS_41; -- constant OUTPUT_FILE : string -- := "X:\Education\Masters Thesis\matlab\sparse_fir_filter\chirp_highpass41.csv"; constant TEST_FILTER : coefficient_array := LOW_PASS_101; constant OUTPUT_FILE : string := "X:\Education\Masters Thesis\matlab\sparse_fir_filter\chirp_lowpass101.csv"; signal rst : std_logic := '0'; signal clk : std_logic := '0'; signal sig : std_logic_vector(NUM_SIG_BITS-1 downto 0) := (others => '0'); signal filtered : fir_sig := (others => '0'); begin --Instantiate clock generator clk1 : tb_clockgen generic map(PERIOD => 10ns, DUTY_CYCLE => 0.50) port map( clk => clk); --Instantiate file reader reader : tb_read_csv generic map(FILENAME => INPUT_FILE) port map( clk => clk, data => sig); --Instantiate unit under test uut : entity work.sparse_fir_filter(behave) generic map(h => TEST_FILTER) port map( clk => clk, rst => rst, x => signed(sig), y => filtered); --Instantiate a file writer writer : tb_write_csv generic map(FILENAME => OUTPUT_FILE) port map( clk => clk, data => std_logic_vector(filtered(30 downto 15))); --Main Process --TODO: Add a check for end of file, once reached terminate simulation. main: process begin rst <= '1'; wait for 10ns; rst <= '0'; wait; end process; end sim;

mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_0_0/fifo_generator_v11_0/builtin/bin_cntr.vhd

19

8597

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block CJc8rmbxQK7PiD9FE9h/V8z28Q2yjtwOLUGOHj92X0D4bGhAiTKxH6Gs6WbTk3x8dF6WKWHXW0Xd imaqryWs/A== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block KUGgnJN/sGLwh1pfD6BBRkJkdz3qYXsMmFAG0D8TIT3kvn1DM/WYFdJfNjuI3TZJ+GjJhgQt/TQj vszszvccproNtKL+iK2kDAI+dODbmK/3dk8pZpjNIY8iqG+SZd4LOHkCbGnDn8J5L1SCb1FbgOpc lYLzGKyKMfpMp2H5zrU= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/blk_mem_gen_wrapper.vhd

12

33638

------------------------------------------------------------------------------- -- $Id: blk_mem_gen_wrapper.vhd,v 1.1.2.69 2010/12/17 19:23:25 dougt Exp $ ------------------------------------------------------------------------------- -- blk_mem_gen_wrapper.vhd - entity/architecture pair ------------------------------------------------------------------------------- -- -- **************************************************************************** -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This text/file contains proprietary, confidential ** -- ** information of Xilinx, Inc., is distributed under ** -- ** license from Xilinx, Inc., and may be used, copied ** -- ** and/or disclosed only pursuant to the terms of a valid ** -- ** license agreement with Xilinx, Inc. Xilinx hereby ** -- ** grants you a license to use this text/file solely for ** -- ** design, simulation, implementation and creation of ** -- ** design files limited to Xilinx devices or technologies. ** -- ** Use with non-Xilinx devices or technologies is expressly ** -- ** prohibited and immediately terminates your license unless ** -- ** covered by a separate agreement. ** -- ** ** -- ** Xilinx is providing this design, code, or information ** -- ** "as-is" solely for use in developing programs and ** -- ** solutions for Xilinx devices, with no obligation on the ** -- ** part of Xilinx to provide support. By providing this design, ** -- ** code, or information as one possible implementation of ** -- ** this feature, application or standard, Xilinx is making no ** -- ** representation that this implementation is free from any ** -- ** claims of infringement. You are responsible for obtaining ** -- ** any rights you may require for your implementation. ** -- ** Xilinx expressly disclaims any warranty whatsoever with ** -- ** respect to the adequacy of the implementation, including ** -- ** but not limited to any warranties or representations that this ** -- ** implementation is free from claims of infringement, implied ** -- ** warranties of merchantability or fitness for a particular ** -- ** purpose. ** -- ** ** -- ** Xilinx products are not intended for use in life support ** -- ** appliances, devices, or systems. Use in such applications is ** -- ** expressly prohibited. ** -- ** ** -- ** Any modifications that are made to the Source Code are ** -- ** done at the users sole risk and will be unsupported. ** -- ** The Xilinx Support Hotline does not have access to source ** -- ** code and therefore cannot answer specific questions related ** -- ** to source HDL. The Xilinx Hotline support of original source ** -- ** code IP shall only address issues and questions related ** -- ** to the standard Netlist version of the core (and thus ** -- ** indirectly, the original core source). ** -- ** ** -- ** Copyright (c) 2008, 2009. 2010 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** This copyright and support notice must be retained as part ** -- ** of this text at all times. ** -- **************************************************************************** -- ------------------------------------------------------------------------------- -- Filename: blk_mem_gen_wrapper.vhd -- Version: v1.00a -- Description: -- This wrapper file performs the direct call to Block Memory Generator -- during design implementation ------------------------------------------------------------------------------- -- ------------------------------------------------------------------------------- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- blk_mem_gen_wrapper.vhd -- | -- |-- blk_mem_gen_v2_7 -- | -- |-- blk_mem_gen_v6_2 -- ------------------------------------------------------------------------------- -- Revision History: -- -- -- Author: MW -- Revision: $Revision: 1.1.2.69 $ -- Date: $7/11/2008$ -- -- History: -- MW 7/11/2008 Initial Version -- MSH 2/26/2009 Add new blk_mem_gen version -- -- DET 4/8/2009 EDK 11.2 -- ~~~~~~ -- - Added blk_mem_gen_v3_2 instance callout -- ^^^^^^ -- -- DET 2/9/2010 for EDK 12.1 -- ~~~~~~ -- - Updated the the Blk Mem Gen version from blk_mem_gen_v3_2 -- to blk_mem_gen_v3_3 (for the S6/V6 IfGen case) -- ^^^^^^ -- -- DET 3/10/2010 For EDK 12.x -- ~~~~~~ -- -- Per CR553307 -- - Updated the the Blk Mem Gen version from blk_mem_gen_v3_3 -- to blk_mem_gen_v4_1 (for the S6/V6 IfGen case) -- ^^^^^^ -- -- DET 3/17/2010 Initial -- ~~~~~~ -- -- Per CR554253 -- - Incorporated changes to comment out FLOP_DELAY parameter from the -- blk_mem_gen_v4_1 instance. This parameter is on the XilinxCoreLib -- model for blk_mem_gen_v4_1 but is declared as a TIME type for the -- vhdl version and an integer for the verilog. -- ^^^^^^ -- -- DET 6/18/2010 EDK_MS2 -- ~~~~~~ -- -- Per IR565916 -- - Added constants FAM_IS_V6_OR_S6 and FAM_IS_NOT_V6_OR_S6. -- - Added derivative part type checks for S6 or V6. -- ^^^^^^ -- -- DET 8/27/2010 EDK 12.4 -- ~~~~~~ -- -- Per CR573867 -- - Added the the Blk Mem Gen version blk_mem_gen_v4_3 for the S6/V6 -- and later build case. -- - Updated method for derivative part support using new family -- aliasing function in family_support.vhd. -- - Incorporated an implementation to deal with unsupported FPGA -- parts passed in on the C_FAMILY parameter. -- ^^^^^^ -- -- DET 10/4/2010 EDK 13.1 -- ~~~~~~ -- - Updated to blk_mem_gen V5.2. -- ^^^^^^ -- -- DET 12/8/2010 EDK 13.1 -- ~~~~~~ -- -- Per CR586109 -- - Updated to blk_mem_gen V6.1 -- ^^^^^^ -- -- DET 12/17/2010 EDK 13.1 -- ~~~~~~ -- -- Per CR587494 -- - Regressed back to blk_mem_gen V5.2 -- ^^^^^^ -- -- DET 3/2/2011 EDk 13.2 -- ~~~~~~ -- -- Per CR595473 -- - Update to use blk_mem_gen_v6_2 for s6, v6, and later. -- ^^^^^^ -- -- DET 3/3/2011 EDK 13.2 -- ~~~~~~ -- - Removed C_ELABORATION_DIR parameter from the blk_mem_gen_v6_2 -- instance. -- ^^^^^^ -- ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synopsys translate_off --Library XilinxCoreLib; -- synopsys translate_on library blk_mem_gen_v8_1; library proc_common_v4_0; use blk_mem_gen_v8_1.all; --use proc_common_v4_0.coregen_comp_defs.all; use proc_common_v4_0.family_support.all; ------------------------------------------------------------------------------ -- Port Declaration ------------------------------------------------------------------------------ entity blk_mem_gen_wrapper is generic ( -- Device Family c_family : string := "virtex5"; -- "Virtex2" -- "Virtex4" -- "Virtex5" c_xdevicefamily : string := "virtex5"; -- Finest Resolution Device Family -- "Virtex2" -- "Virtex2-Pro" -- "Virtex4" -- "Virtex5" -- "Spartan-3A" -- "Spartan-3A DSP" c_elaboration_dir : string := ""; -- Memory Specific Configurations c_mem_type : integer := 2; -- This wrapper only supports the True Dual Port RAM -- 0: Single Port RAM -- 1: Simple Dual Port RAM -- 2: True Dual Port RAM -- 3: Single Port Rom -- 4: Dual Port RAM c_algorithm : integer := 1; -- 0: Selectable Primative -- 1: Minimum Area c_prim_type : integer := 1; -- 0: ( 1-bit wide) -- 1: ( 2-bit wide) -- 2: ( 4-bit wide) -- 3: ( 9-bit wide) -- 4: (18-bit wide) -- 5: (36-bit wide) -- 6: (72-bit wide, single port only) c_byte_size : integer := 9; -- 8 or 9 -- Simulation Behavior Options c_sim_collision_check : string := "NONE"; -- "None" -- "Generate_X" -- "All" -- "Warnings_only" c_common_clk : integer := 1; -- 0, 1 c_disable_warn_bhv_coll : integer := 0; -- 0, 1 c_disable_warn_bhv_range : integer := 0; -- 0, 1 -- Initialization Configuration Options c_load_init_file : integer := 0; c_init_file_name : string := "no_coe_file_loaded"; c_use_default_data : integer := 0; -- 0, 1 c_default_data : string := "0"; -- "..." -- Port A Specific Configurations c_has_mem_output_regs_a : integer := 0; -- 0, 1 c_has_mux_output_regs_a : integer := 0; -- 0, 1 c_write_width_a : integer := 32; -- 1 to 1152 c_read_width_a : integer := 32; -- 1 to 1152 c_write_depth_a : integer := 64; -- 2 to 9011200 c_read_depth_a : integer := 64; -- 2 to 9011200 c_addra_width : integer := 6; -- 1 to 24 c_write_mode_a : string := "WRITE_FIRST"; -- "Write_First" -- "Read_first" -- "No_Change" c_has_ena : integer := 1; -- 0, 1 c_has_regcea : integer := 0; -- 0, 1 c_has_ssra : integer := 0; -- 0, 1 c_sinita_val : string := "0"; --"..." c_use_byte_wea : integer := 0; -- 0, 1 c_wea_width : integer := 1; -- 1 to 128 -- Port B Specific Configurations c_has_mem_output_regs_b : integer := 0; -- 0, 1 c_has_mux_output_regs_b : integer := 0; -- 0, 1 c_write_width_b : integer := 32; -- 1 to 1152 c_read_width_b : integer := 32; -- 1 to 1152 c_write_depth_b : integer := 64; -- 2 to 9011200 c_read_depth_b : integer := 64; -- 2 to 9011200 c_addrb_width : integer := 6; -- 1 to 24 c_write_mode_b : string := "WRITE_FIRST"; -- "Write_First" -- "Read_first" -- "No_Change" c_has_enb : integer := 1; -- 0, 1 c_has_regceb : integer := 0; -- 0, 1 c_has_ssrb : integer := 0; -- 0, 1 c_sinitb_val : string := "0"; -- "..." c_use_byte_web : integer := 0; -- 0, 1 c_web_width : integer := 1; -- 1 to 128 -- Other Miscellaneous Configurations c_mux_pipeline_stages : integer := 0; -- 0, 1, 2, 3 -- The number of pipeline stages within the MUX -- for both Port A and Port B c_use_ecc : integer := 0; -- See DS512 for the limited core option selections for ECC support c_use_ramb16bwer_rst_bhv : integer := 0--; --0, 1 -- c_corename : string := "blk_mem_gen_v2_7" --Uncommenting the above parameter (C_CORENAME) will cause --the a failure in NGCBuild!!! ); port ( clka : in std_logic; ssra : in std_logic := '0'; dina : in std_logic_vector(c_write_width_a-1 downto 0) := (OTHERS => '0'); addra : in std_logic_vector(c_addra_width-1 downto 0); ena : in std_logic := '1'; regcea : in std_logic := '1'; wea : in std_logic_vector(c_wea_width-1 downto 0) := (OTHERS => '0'); douta : out std_logic_vector(c_read_width_a-1 downto 0); clkb : in std_logic := '0'; ssrb : in std_logic := '0'; dinb : in std_logic_vector(c_write_width_b-1 downto 0) := (OTHERS => '0'); addrb : in std_logic_vector(c_addrb_width-1 downto 0) := (OTHERS => '0'); enb : in std_logic := '1'; regceb : in std_logic := '1'; web : in std_logic_vector(c_web_width-1 downto 0) := (OTHERS => '0'); doutb : out std_logic_vector(c_read_width_b-1 downto 0); dbiterr : out std_logic; -- Double bit error that that cannot be auto corrected by ECC sbiterr : out std_logic -- Single Bit Error that has been auto corrected on the output bus ); end entity blk_mem_gen_wrapper; architecture implementation of blk_mem_gen_wrapper is Constant FAMILY_TO_USE : string := get_root_family(C_FAMILY); -- function from family_support.vhd Constant FAMILY_NOT_SUPPORTED : boolean := (equalIgnoringCase(FAMILY_TO_USE, "nofamily")); Constant FAMILY_IS_SUPPORTED : boolean := not(FAMILY_NOT_SUPPORTED); --Constant FAM_IS_S3_V4_V5 : boolean := (equalIgnoringCase(FAMILY_TO_USE, "spartan3" ) or -- equalIgnoringCase(FAMILY_TO_USE, "virtex4" ) or -- equalIgnoringCase(FAMILY_TO_USE, "virtex5")) and -- FAMILY_IS_SUPPORTED; -- --Constant FAM_IS_NOT_S3_V4_V5 : boolean := not(FAM_IS_S3_V4_V5) and -- FAMILY_IS_SUPPORTED; --Signals added to fix MTI and XSIM issues caused by fix for VCS issues not to use "LIBRARY_SCAN = TRUE" signal RDADDRECC : STD_LOGIC_VECTOR(c_addrb_width-1 DOWNTO 0); signal S_AXI_AWREADY : STD_LOGIC; signal S_AXI_WREADY : STD_LOGIC; signal S_AXI_BID : STD_LOGIC_VECTOR(3 DOWNTO 0); signal S_AXI_BRESP : STD_LOGIC_VECTOR(1 DOWNTO 0); signal S_AXI_BVALID : STD_LOGIC; signal S_AXI_ARREADY : STD_LOGIC; signal S_AXI_RID : STD_LOGIC_VECTOR(3 DOWNTO 0); signal S_AXI_RDATA : STD_LOGIC_VECTOR(c_write_width_b-1 DOWNTO 0); signal S_AXI_RRESP : STD_LOGIC_VECTOR(1 DOWNTO 0); signal S_AXI_RLAST : STD_LOGIC; signal S_AXI_RVALID : STD_LOGIC; signal S_AXI_SBITERR : STD_LOGIC; signal S_AXI_DBITERR : STD_LOGIC; signal S_AXI_RDADDRECC : STD_LOGIC_VECTOR(c_addrb_width-1 DOWNTO 0); signal S_AXI_WSTRB : STD_LOGIC_VECTOR(c_wea_width-1 downto 0); signal S_AXI_WDATA : STD_LOGIC_VECTOR(c_write_width_a-1 downto 0); begin S_AXI_WSTRB <= (others => '0'); S_AXI_WDATA <= (others => '0'); ------------------------------------------------------------ -- If Generate -- -- Label: GEN_NO_FAMILY -- -- If Generate Description: -- This IfGen is implemented if an unsupported FPGA family -- is passed in on the C_FAMILY parameter, -- ------------------------------------------------------------ GEN_NO_FAMILY : if (FAMILY_NOT_SUPPORTED) generate begin -- synthesis translate_off ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_ASSERTION -- -- Process Description: -- Generate a simulation error assertion for an unsupported -- FPGA family string passed in on the C_FAMILY parameter. -- ------------------------------------------------------------- DO_ASSERTION : process begin -- Wait until second rising clock edge to issue assertion Wait until clka = '1'; wait until clka = '0'; Wait until clka = '1'; -- Report an error in simulation environment assert FALSE report "********* UNSUPPORTED FPGA DEVICE! Check C_FAMILY parameter assignment!" severity ERROR; Wait; -- halt this process end process DO_ASSERTION; -- synthesis translate_on -- Tie outputs to logic low douta <= (others => '0'); -- : out std_logic_vector(c_read_width_a-1 downto 0); doutb <= (others => '0'); -- : out std_logic_vector(c_read_width_b-1 downto 0); dbiterr <= '0' ; -- : out std_logic; sbiterr <= '0' ; -- : out std_logic end generate GEN_NO_FAMILY; ------------------------------------------------------------ -- If Generate -- -- Label: V6_S6_AND_LATER -- -- If Generate Description: -- This IFGen Implements the Block Memeory using blk_mem_gen 5.2. -- This is for new cores designed and tested with FPGA -- Families of Virtex-6, Spartan-6 and later. -- ------------------------------------------------------------ FAMILY_SUPPORTED: if(FAMILY_IS_SUPPORTED) generate begin ------------------------------------------------------------------------------- -- Instantiate the generalized FIFO Generator instance -- -- NOTE: -- DO NOT CHANGE TO DIRECT ENTITY INSTANTIATION!!! -- This is a Coregen Block Memory Generator Call module -- for new IP BRAM implementations. -- ------------------------------------------------------------------------------- I_TRUE_DUAL_PORT_BLK_MEM_GEN : entity blk_mem_gen_v8_1.blk_mem_gen_v8_1 generic map ( --C_CORENAME => c_corename , -- Device Family C_FAMILY => FAMILY_TO_USE , C_XDEVICEFAMILY => c_xdevicefamily , C_ELABORATION_DIR => c_elaboration_dir , ------------------ C_INTERFACE_TYPE => 0 , C_USE_BRAM_BLOCK => 0 , C_AXI_TYPE => 0 , C_AXI_SLAVE_TYPE => 0 , C_HAS_AXI_ID => 0 , C_AXI_ID_WIDTH => 4 , ------------------ -- Memory Specific Configurations C_MEM_TYPE => c_mem_type , C_BYTE_SIZE => c_byte_size , C_ALGORITHM => c_algorithm , C_PRIM_TYPE => c_prim_type , C_LOAD_INIT_FILE => c_load_init_file , C_INIT_FILE_NAME => c_init_file_name , C_INIT_FILE => "" , C_USE_DEFAULT_DATA => c_use_default_data , C_DEFAULT_DATA => c_default_data , -- Port A Specific Configurations C_RST_TYPE => "SYNC" , C_HAS_RSTA => c_has_ssra , C_RST_PRIORITY_A => "CE" , C_RSTRAM_A => 0 , C_INITA_VAL => c_sinita_val , C_HAS_ENA => c_has_ena , C_HAS_REGCEA => c_has_regcea , C_USE_BYTE_WEA => c_use_byte_wea , C_WEA_WIDTH => c_wea_width , C_WRITE_MODE_A => c_write_mode_a , C_WRITE_WIDTH_A => c_write_width_a , C_READ_WIDTH_A => c_read_width_a , C_WRITE_DEPTH_A => c_write_depth_a , C_READ_DEPTH_A => c_read_depth_a , C_ADDRA_WIDTH => c_addra_width , -- Port B Specific Configurations C_HAS_RSTB => c_has_ssrb , C_RST_PRIORITY_B => "CE" , C_RSTRAM_B => 0 , C_INITB_VAL => c_sinitb_val , C_HAS_ENB => c_has_enb , C_HAS_REGCEB => c_has_regceb , C_USE_BYTE_WEB => c_use_byte_web , C_WEB_WIDTH => c_web_width , C_WRITE_MODE_B => c_write_mode_b , C_WRITE_WIDTH_B => c_write_width_b , C_READ_WIDTH_B => c_read_width_b , C_WRITE_DEPTH_B => c_write_depth_b , C_READ_DEPTH_B => c_read_depth_b , C_ADDRB_WIDTH => c_addrb_width , C_HAS_MEM_OUTPUT_REGS_A => c_has_mem_output_regs_a , C_HAS_MEM_OUTPUT_REGS_B => c_has_mem_output_regs_b , C_HAS_MUX_OUTPUT_REGS_A => c_has_mux_output_regs_a , C_HAS_MUX_OUTPUT_REGS_B => c_has_mux_output_regs_b , C_HAS_SOFTECC_INPUT_REGS_A => 0 , C_HAS_SOFTECC_OUTPUT_REGS_B => 0 , -- Other Miscellaneous Configurations C_MUX_PIPELINE_STAGES => c_mux_pipeline_stages , C_USE_SOFTECC => 0 , C_USE_ECC => c_use_ecc , -- Simulation Behavior Options C_HAS_INJECTERR => 0 , C_SIM_COLLISION_CHECK => c_sim_collision_check , C_COMMON_CLK => c_common_clk , C_DISABLE_WARN_BHV_COLL => c_disable_warn_bhv_coll , C_DISABLE_WARN_BHV_RANGE => c_disable_warn_bhv_range ) port map ( CLKA => clka , RSTA => ssra , ENA => ena , REGCEA => regcea , WEA => wea , ADDRA => addra , DINA => dina , DOUTA => douta , CLKB => clkb , RSTB => ssrb , ENB => enb , REGCEB => regceb , WEB => web , ADDRB => addrb , DINB => dinb , DOUTB => doutb , INJECTSBITERR => '0' , -- input INJECTDBITERR => '0' , -- input SBITERR => sbiterr , DBITERR => dbiterr , RDADDRECC => RDADDRECC , -- output -- AXI BMG Input and Output Port Declarations -- new for v6.2 -- new for v6.2 -- AXI Global Signals -- new for v6.2 S_AClk => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2 S_ARESETN => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2 -- new for v6.2 -- AXI Full/Lite Slave Write (write side) -- new for v6.2 S_AXI_AWID => "0000" , -- : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2 S_AXI_AWADDR => "00000000000000000000000000000000" , -- : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2 S_AXI_AWLEN => "00000000" , -- : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2 S_AXI_AWSIZE => "000" , -- : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2 S_AXI_AWBURST => "00" , -- : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2 S_AXI_AWVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2 S_AXI_AWREADY => S_AXI_AWREADY , -- : OUT STD_LOGIC; -- new for v6.2 S_AXI_WDATA => S_AXI_WDATA , -- : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2 S_AXI_WSTRB => S_AXI_WSTRB , -- : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2 S_AXI_WLAST => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2 S_AXI_WVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2 S_AXI_WREADY => S_AXI_WREADY , -- : OUT STD_LOGIC; -- new for v6.2 S_AXI_BID => S_AXI_BID , -- : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2 S_AXI_BRESP => S_AXI_BRESP , -- : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); -- new for v6.2 S_AXI_BVALID => S_AXI_BVALID , -- : OUT STD_LOGIC; -- new for v6.2 S_AXI_BREADY => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2 -- new for v6.2 -- AXI Full/Lite Slave Read (Write side) -- new for v6.2 S_AXI_ARID => "0000" , -- : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2 S_AXI_ARADDR => "00000000000000000000000000000000" , -- : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2 S_AXI_ARLEN => "00000000" , -- : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2 S_AXI_ARSIZE => "000" , -- : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2 S_AXI_ARBURST => "00" , -- : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2 S_AXI_ARVALID => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2 S_AXI_ARREADY => S_AXI_ARREADY , -- : OUT STD_LOGIC; -- new for v6.2 S_AXI_RID => S_AXI_RID , -- : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- new for v6.2 S_AXI_RDATA => S_AXI_RDATA , -- : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0); -- new for v6.2 S_AXI_RRESP => S_AXI_RRESP , -- : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0); -- new for v6.2 S_AXI_RLAST => S_AXI_RLAST , -- : OUT STD_LOGIC; -- new for v6.2 S_AXI_RVALID => S_AXI_RVALID , -- : OUT STD_LOGIC; -- new for v6.2 S_AXI_RREADY => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2 -- new for v6.2 -- AXI Full/Lite Sideband Signals -- new for v6.2 S_AXI_INJECTSBITERR => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2 S_AXI_INJECTDBITERR => '0' , -- : IN STD_LOGIC := '0'; -- new for v6.2 S_AXI_SBITERR => S_AXI_SBITERR , -- : OUT STD_LOGIC; -- new for v6.2 S_AXI_DBITERR => S_AXI_DBITERR , -- : OUT STD_LOGIC; -- new for v6.2 S_AXI_RDADDRECC => S_AXI_RDADDRECC -- : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) -- new for v6.2 ); end generate FAMILY_SUPPORTED; end implementation;

mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_auto_pc_3/fifo_generator_v11_0/ramfifo/rd_pe_sshft.vhd

19

17676

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block SOOYAbmSVdMSmEhVcX6OANZAlRBhIeIgp+j8aWie5qMiZZfkKWRKGFlDj4dOK2MxGgpLi60kolAl iwo8CvQQmg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block XO8hvx7ayNrMYNs+QowHbS9oiS1GjnY7XWvxUBWvS8S0pBwgguPJgxI5Jawjx75IEBra9z6gur8D +8bJ3wjB5uOzP0Op4TufbsYZTMy5/IRaR1m1haAiZDNWpnRaJY0iGIl1ZfXnFFB/FNm2d6rg/H7b +K1wV2KmxNsYmhxGeUs= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block qrXPktUjITPZaeyYovMGSvjyrwEeWSEPCoXArB49zu0J+taotc50izauZkw4BvtuT10+TUqV3pWu H2Y4+wBhbI0avNdhBTQ6WysNgxNkl4xSoIMSUDeWLPrThpvXqf5EM2xFWnYEsoSt1fOlTzsbNp4Z xTF0/8eRzGcTqQK8goNirFS4li1yNxnvMyocM7UB0Hgwd4r1WhVfwqexmsE2F2aKD0WceDfUKvzW BkaD/pggzoFKe9ZBj4krjm5QO6MJe6tmyETtklCe5Tp5KFVAoUG5SSUacYfOW5JRRQQN1B29KV6+ B/PXOjnEprmrDoW2/GvnZUOJ8iICUgvcDDx9Gw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block RfdpJMuL5lneUspdc3THLHWNRfMy7ZKvo7MAlgXNSeMyJ16shj6csIbQx7zWlYY0s5cmQ5qBeuky S0nRybRR8cWMHwN/9rEo4V+uesao4mJ5GbtqRFTH0pGXUIW0hSA/qLXBAZCtANiThLFmTTovXGQx QWChhP7QcQZsZBRuEUY= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block KfAPtRUOpYg8KaNj0Wxd1r4Bcs5Lt64mregrxrObBeYBNNIje2iGcuv2d5+PQzzomKwP4NoGlbzx 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mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/fifo_generator_v11_0/ramfifo/rd_pe_sshft.vhd

19

17676

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block SOOYAbmSVdMSmEhVcX6OANZAlRBhIeIgp+j8aWie5qMiZZfkKWRKGFlDj4dOK2MxGgpLi60kolAl iwo8CvQQmg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block XO8hvx7ayNrMYNs+QowHbS9oiS1GjnY7XWvxUBWvS8S0pBwgguPJgxI5Jawjx75IEBra9z6gur8D +8bJ3wjB5uOzP0Op4TufbsYZTMy5/IRaR1m1haAiZDNWpnRaJY0iGIl1ZfXnFFB/FNm2d6rg/H7b +K1wV2KmxNsYmhxGeUs= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block qrXPktUjITPZaeyYovMGSvjyrwEeWSEPCoXArB49zu0J+taotc50izauZkw4BvtuT10+TUqV3pWu H2Y4+wBhbI0avNdhBTQ6WysNgxNkl4xSoIMSUDeWLPrThpvXqf5EM2xFWnYEsoSt1fOlTzsbNp4Z xTF0/8eRzGcTqQK8goNirFS4li1yNxnvMyocM7UB0Hgwd4r1WhVfwqexmsE2F2aKD0WceDfUKvzW BkaD/pggzoFKe9ZBj4krjm5QO6MJe6tmyETtklCe5Tp5KFVAoUG5SSUacYfOW5JRRQQN1B29KV6+ B/PXOjnEprmrDoW2/GvnZUOJ8iICUgvcDDx9Gw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block RfdpJMuL5lneUspdc3THLHWNRfMy7ZKvo7MAlgXNSeMyJ16shj6csIbQx7zWlYY0s5cmQ5qBeuky S0nRybRR8cWMHwN/9rEo4V+uesao4mJ5GbtqRFTH0pGXUIW0hSA/qLXBAZCtANiThLFmTTovXGQx QWChhP7QcQZsZBRuEUY= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block KfAPtRUOpYg8KaNj0Wxd1r4Bcs5Lt64mregrxrObBeYBNNIje2iGcuv2d5+PQzzomKwP4NoGlbzx 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mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_auto_pc_3/blk_mem_gen_v8_1/blk_mem_gen_mux.vhd

27

91985

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block PFFltKdLY0A82yxFqahMaWdN+zxj5kThYAcsDyz3A2vhpKKQpGJvV8/AkpYYPyltKlIzJB6Md9uF AN2ca05J0g== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block obdm7XtHPDQGZMrK3kNZKnRt8ypfk4aZ9VtSDpnSwNdbgwrFg4uylDkc4YjBW8BFR32vEdXmCKFe 3L1bSMhXRkPXZ88hMJlBty0IcmSYNatn3RV9VG9yYtXM73zMkJ4NIx7KoDtvOCnGQpHNAJTknAv6 BNEUXajqHzh/vB/QNBQ= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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y3WZOw== `protect end_protected

mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/blk_mem_gen_v8_1/blk_mem_gen_mux.vhd

27

91985

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block PFFltKdLY0A82yxFqahMaWdN+zxj5kThYAcsDyz3A2vhpKKQpGJvV8/AkpYYPyltKlIzJB6Md9uF AN2ca05J0g== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block obdm7XtHPDQGZMrK3kNZKnRt8ypfk4aZ9VtSDpnSwNdbgwrFg4uylDkc4YjBW8BFR32vEdXmCKFe 3L1bSMhXRkPXZ88hMJlBty0IcmSYNatn3RV9VG9yYtXM73zMkJ4NIx7KoDtvOCnGQpHNAJTknAv6 BNEUXajqHzh/vB/QNBQ= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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y3WZOw== `protect end_protected

mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/fifo_generator_v11_0/builtin/builtin_extdepth_v6.vhd

19

50137

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block hezhI5arYh5Ll2LsYr9SKRVb8M09iAN2m4JSbciXeqmprOA6kAYKyNVYZrZl+7uJ9rCbSy2t8SS7 C18wuehlMQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block iG3qoWxeKUs22C9+IygRgNw/Ob9GNJdHtLxrQAtYdMzP86eceFi53EP4Epvud6QFqZ+YCcJAJz6X BiP6+zFZ6SCjFFuXw9pefFKNSIH8+q7UF5dPb1d06lbHzIZD+3mRDkhnSZjrqT/zLAUZb/IQ1Lbm Z5oVMb2d2CoW5etMngE= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_0_0/fifo_generator_v11_0/ramfifo/rd_status_flags_ss.vhd

19

18129

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block IVTcVKz+qqR6KelbIxn6hKss0fyLwIejVgwej+TN1ST/vU6syUW6hxZyGugx/VRu65UT+0QU+88C 5SDN434/fA== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block W0uuDuJZlgdtFvYMz+doOP0vwnGc2SXfLiGH2a5FulZQF1GjNx3fjKnarWbbCm92Rksm2FFSGof4 SgtGKAeCq4Yz/Vqm5xuP6QHmdBwou49vkKDs52HUud9c3EaEYtdNlkb4+DCcueqZu76yWN8rf2DJ ekmu+LGiL1dmyzv30tE= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/fifo_generator_v11_0/ramfifo/rd_status_flags_ss.vhd

19

18129

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block IVTcVKz+qqR6KelbIxn6hKss0fyLwIejVgwej+TN1ST/vU6syUW6hxZyGugx/VRu65UT+0QU+88C 5SDN434/fA== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block W0uuDuJZlgdtFvYMz+doOP0vwnGc2SXfLiGH2a5FulZQF1GjNx3fjKnarWbbCm92Rksm2FFSGof4 SgtGKAeCq4Yz/Vqm5xuP6QHmdBwou49vkKDs52HUud9c3EaEYtdNlkb4+DCcueqZu76yWN8rf2DJ ekmu+LGiL1dmyzv30tE= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Da9hmR0COgf/nsNRjZU5mrjIzRjN0/ufJQ7crbPh82WrNgInUm192216ks1D/Quh1gQ5TieAOChY 26CHNdLfPPmjLAo5/cOIRsIuy2JD7JAEIDFhFO2BcC4GrUAhSArSC4/9FyqXrVJUKuDybwv0tWSf qpHjmJw18CiVw84ne90mESBOJ0fW1ujayfbI70yaGaFjJM/DPm4Lq+TC+TFlaimxpTFNrAUzQNVF VSkf44Zb11D7if2jaL6ua4hPGgYpPcisaJtcEYpURXS8Lw+NjmMExnMpUW39NqnMiTEPom3YBwag JMKm6/EZOnBvVc8SljH7y69fXiGUXgw6Z6POkg== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 1/llP5a+sEX6Ky1I5ak8Fr3e35uMro1bXNqkrntPBRVTqUhQPFl7wfr/6Abnu74l73YggylsZJi1 1Erm6sC9oDhL9IE4pENErrDQRZHuFnl4+DlguLd11swTlNfBwauGoCBXbTtZ8+O70UI/sRzXqbZc NDH1RywyQLhMRmSOjCU= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block OI4vyCtRzSCtjYNsCqL7rYkcvPw30aumOHoxNPQx0NU0Kc5/zvGo5pjE7sDqPsv0b00mAjKXUE8e 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mit

jakubcabal/uart_for_fpga

examples/uart2wb/uart2wbm.vhd

2

9087

-------------------------------------------------------------------------------- -- PROJECT: SIMPLE UART FOR FPGA -------------------------------------------------------------------------------- -- AUTHORS: Jakub Cabal <[email protected]> -- LICENSE: The MIT License, please read LICENSE file -- WEBSITE: https://github.com/jakubcabal/uart-for-fpga -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity UART2WBM is Generic ( CLK_FREQ : integer := 50e6; -- system clock frequency in Hz BAUD_RATE : integer := 115200 -- baud rate value ); Port ( -- CLOCK AND RESET CLK : in std_logic; RST : in std_logic; -- UART INTERFACE UART_TXD : out std_logic; UART_RXD : in std_logic; -- WISHBONE MASTER INTERFACE WB_CYC : out std_logic; WB_STB : out std_logic; WB_WE : out std_logic; WB_ADDR : out std_logic_vector(15 downto 0); WB_DOUT : out std_logic_vector(31 downto 0); WB_STALL : in std_logic; WB_ACK : in std_logic; WB_DIN : in std_logic_vector(31 downto 0) ); end entity; architecture RTL of UART2WBM is type state is (cmd, addr_low, addr_high, dout0, dout1, dout2, dout3, request, wait4ack, response, din0, din1, din2, din3); signal fsm_pstate : state; signal fsm_nstate : state; signal cmd_reg : std_logic_vector(7 downto 0); signal cmd_next : std_logic_vector(7 downto 0); signal addr_reg : std_logic_vector(15 downto 0); signal addr_next : std_logic_vector(15 downto 0); signal dout_reg : std_logic_vector(31 downto 0); signal dout_next : std_logic_vector(31 downto 0); signal din_reg : std_logic_vector(31 downto 0); signal uart_dout : std_logic_vector(7 downto 0); signal uart_dout_vld : std_logic; signal uart_din : std_logic_vector(7 downto 0); signal uart_din_vld : std_logic; signal uart_din_rdy : std_logic; begin process (CLK) begin if (rising_edge(CLK)) then cmd_reg <= cmd_next; addr_reg <= addr_next; dout_reg <= dout_next; end if; end process; WB_WE <= cmd_reg(0); WB_ADDR <= addr_reg; WB_DOUT <= dout_reg; process (CLK) begin if (rising_edge(CLK)) then if (WB_ACK = '1') then din_reg <= WB_DIN; end if; end if; end process; -- ------------------------------------------------------------------------- -- FSM -- ------------------------------------------------------------------------- process (CLK) begin if (rising_edge(CLK)) then if (RST = '1') then fsm_pstate <= cmd; else fsm_pstate <= fsm_nstate; end if; end if; end process; process (fsm_pstate, uart_dout, uart_dout_vld, cmd_reg, addr_reg, dout_reg, WB_STALL, WB_ACK, uart_din_rdy, din_reg) begin fsm_nstate <= cmd; cmd_next <= cmd_reg; addr_next <= addr_reg; dout_next <= dout_reg; WB_STB <= '0'; WB_CYC <= '0'; uart_din <= cmd_reg; uart_din_vld <= '0'; case fsm_pstate is when cmd => -- idle and read request cmd from UART cmd_next <= uart_dout; if (uart_dout_vld = '1') then fsm_nstate <= addr_low; else fsm_nstate <= cmd; end if; when addr_low => -- read low bits of address from UART addr_next(7 downto 0) <= uart_dout; if (uart_dout_vld = '1') then fsm_nstate <= addr_high; else fsm_nstate <= addr_low; end if; when addr_high => -- read high bits of address from UART addr_next(15 downto 8) <= uart_dout; if (uart_dout_vld = '1') then if (cmd_reg(0) = '1') then fsm_nstate <= dout0; -- write cmd else fsm_nstate <= request; -- read cmd end if; else fsm_nstate <= addr_high; end if; when dout0 => -- read data byte 0 from UART (write cmd only) dout_next(7 downto 0) <= uart_dout; if (uart_dout_vld = '1') then fsm_nstate <= dout1; else fsm_nstate <= dout0; end if; when dout1 => -- read data byte 1 from UART (write cmd only) dout_next(15 downto 8) <= uart_dout; if (uart_dout_vld = '1') then fsm_nstate <= dout2; else fsm_nstate <= dout1; end if; when dout2 => -- read data byte 2 from UART (write cmd only) dout_next(23 downto 16) <= uart_dout; if (uart_dout_vld = '1') then fsm_nstate <= dout3; else fsm_nstate <= dout2; end if; when dout3 => -- read data byte 3 from UART (write cmd only) dout_next(31 downto 24) <= uart_dout; if (uart_dout_vld = '1') then fsm_nstate <= request; -- write request else fsm_nstate <= dout3; end if; when request => -- send WR or RD request to Wishbone bus WB_STB <= '1'; -- request is valid WB_CYC <= '1'; if (WB_STALL = '0') then fsm_nstate <= wait4ack; else fsm_nstate <= request; end if; when wait4ack => -- wait for ACK on Wishbone bus WB_CYC <= '1'; if (WB_ACK = '1') then fsm_nstate <= response; else fsm_nstate <= wait4ack; end if; when response => -- send response cmd to UART uart_din <= cmd_reg; uart_din_vld <= '1'; if (uart_din_rdy = '1') then if (cmd_reg(0) = '1') then fsm_nstate <= cmd; -- idle or new read request cmd (write cmd only) else fsm_nstate <= din0; -- send read data to UART (read cmd only) end if; else fsm_nstate <= response; end if; when din0 => -- send read data byte 0 to UART (read cmd only) uart_din <= din_reg(7 downto 0); uart_din_vld <= '1'; if (uart_din_rdy = '1') then fsm_nstate <= din1; else fsm_nstate <= din0; end if; when din1 => -- send read data byte 1 to UART (read cmd only) uart_din <= din_reg(15 downto 8); uart_din_vld <= '1'; if (uart_din_rdy = '1') then fsm_nstate <= din2; else fsm_nstate <= din1; end if; when din2 => -- send read data byte 2 to UART (read cmd only) uart_din <= din_reg(23 downto 16); uart_din_vld <= '1'; if (uart_din_rdy = '1') then fsm_nstate <= din3; else fsm_nstate <= din2; end if; when din3 => -- send read data byte 3 to UART (read cmd only) uart_din <= din_reg(31 downto 24); uart_din_vld <= '1'; if (uart_din_rdy = '1') then fsm_nstate <= cmd; else fsm_nstate <= din3; end if; end case; end process; -- ------------------------------------------------------------------------- -- UART module -- ------------------------------------------------------------------------- uart_i : entity work.UART generic map ( CLK_FREQ => CLK_FREQ, BAUD_RATE => BAUD_RATE, PARITY_BIT => "none", USE_DEBOUNCER => True ) port map ( CLK => CLK, RST => RST, -- UART INTERFACE UART_TXD => UART_TXD, UART_RXD => UART_RXD, -- USER DATA INPUT INTERFACE DIN => uart_din, DIN_VLD => uart_din_vld, DIN_RDY => uart_din_rdy, -- USER DATA OUTPUT INTERFACE DOUT => uart_dout, DOUT_VLD => uart_dout_vld, FRAME_ERROR => open, PARITY_ERROR => open ); end architecture;

mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_1_1/proc_common_v4_0/hdl/src/vhdl/pf_dpram_select.vhd

15

118961

------------------------------------------------------------------------------- -- $Id: pf_dpram_select.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $ ------------------------------------------------------------------------------- -- pf_dpram_select.vhd ------------------------------------------------------------------------------- -- -- ************************************************************************* -- ** ** -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This text/file contains proprietary, confidential ** -- ** information of Xilinx, Inc., is distributed under ** -- ** license from Xilinx, Inc., and may be used, copied ** -- ** and/or disclosed only pursuant to the terms of a valid ** -- ** license agreement with Xilinx, Inc. Xilinx hereby ** -- ** grants you a license to use this text/file solely for ** -- ** design, simulation, implementation and creation of ** -- ** design files limited to Xilinx devices or technologies. ** -- ** Use with non-Xilinx devices or technologies is expressly ** -- ** prohibited and immediately terminates your license unless ** -- ** covered by a separate agreement. ** -- ** ** -- ** Xilinx is providing this design, code, or information ** -- ** "as-is" solely for use in developing programs and ** -- ** solutions for Xilinx devices, with no obligation on the ** -- ** part of Xilinx to provide support. By providing this design, ** -- ** code, or information as one possible implementation of ** -- ** this feature, application or standard, Xilinx is making no ** -- ** representation that this implementation is free from any ** -- ** claims of infringement. You are responsible for obtaining ** -- ** any rights you may require for your implementation. ** -- ** Xilinx expressly disclaims any warranty whatsoever with ** -- ** respect to the adequacy of the implementation, including ** -- ** but not limited to any warranties or representations that this ** -- ** implementation is free from claims of infringement, implied ** -- ** warranties of merchantability or fitness for a particular ** -- ** purpose. ** -- ** ** -- ** Xilinx products are not intended for use in life support ** -- ** appliances, devices, or systems. Use in such applications is ** -- ** expressly prohibited. ** -- ** ** -- ** Any modifications that are made to the Source Code are ** -- ** done at the users sole risk and will be unsupported. ** -- ** The Xilinx Support Hotline does not have access to source ** -- ** code and therefore cannot answer specific questions related ** -- ** to source HDL. The Xilinx Hotline support of original source ** -- ** code IP shall only address issues and questions related ** -- ** to the standard Netlist version of the core (and thus ** -- ** indirectly, the original core source). ** -- ** ** -- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** This copyright and support notice must be retained as part ** -- ** of this text at all times. ** -- ** ** -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: pf_dpram_select.vhd -- -- Description: This vhdl design file uses three input parameters describing -- the desired storage depth, data width, and FPGA family type. -- From these, the design selects the optimum Block RAM -- primitive for the basic storage element and connects them -- in parallel to accomodate the desired data width. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- pf_dpram_select.vhd -- ------------------------------------------------------------------------------- -- Author: D. Thorpe -- Revision: $Revision: 1.1.4.1 $ -- Date: $Date: 2010/09/14 22:35:47 $ -- -- History: -- DET Oct. 7, 2001 First Version -- - Adopted design concepts from Goran Bilski's -- opb_bram.vhd design in the formulation of this -- design for the Mauna Loa packet FIFO dual port -- core function. -- -- DET Oct-31-2001 -- - Changed the generic input parameter C_FAMILY of type string -- back to the boolean type parameter C_VIRTEX_II. XST support -- change. -- -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library unisim; use unisim.all; -- uses BRAM primitives ------------------------------------------------------------------------------- entity pf_dpram_select is generic ( C_DP_DATA_WIDTH : Integer := 32; C_DP_ADDRESS_WIDTH : Integer := 9; C_VIRTEX_II : Boolean := true ); port ( -- Write Port signals Wr_rst : In std_logic; Wr_Clk : in std_logic; Wr_Enable : In std_logic; Wr_Req : In std_logic; Wr_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1); Wr_Data : In std_logic_vector(0 to C_DP_DATA_WIDTH-1); -- Read Port Signals Rd_rst : In std_logic; Rd_Clk : in std_logic; Rd_Enable : In std_logic; Rd_Address : in std_logic_vector(0 to C_DP_ADDRESS_WIDTH-1); Rd_Data : out std_logic_vector(0 to C_DP_DATA_WIDTH-1) ); end entity pf_dpram_select; architecture implementation of pf_dpram_select is Type family_type is ( any , x4k , x4ke , x4kl , x4kex , x4kxl , x4kxv , x4kxla , spartan , spartanxl, spartan2 , spartan2e, virtex , virtexe , virtex2 , virtex2p , unsupported ); Type bram_prim_type is ( use_srl , B4_S1_S1 , B4_S2_S2 , B4_S4_S4 , B4_S8_S8 , B4_S16_S16 , B16_S1_S1 , B16_S2_S2 , B16_S4_S4 , B16_S9_S9 , B16_S18_S18 , B16_S36_S36 , indeterminate ); ----------------------------------------------------------------------------- -- This function converts the input C_VIRTEX_II boolean type to an enumerated -- type. Only Virtex and Virtex II types are currently supported. This -- used to convert a string to a family type function but string support in -- the synthesis tools was found to be mutually exclusive between Synplicity -- and XST. ----------------------------------------------------------------------------- function get_prim_family (vertex2_select : boolean) return family_type is Variable prim_family : family_type; begin If (vertex2_select) Then prim_family := virtex2; else prim_family := virtex; End if; Return (prim_family); end function get_prim_family; ----------------------------------------------------------------------------- -- This function chooses the optimum BRAM primitive to utilize as -- specified by the inputs for data depth, data width, and FPGA part family. ----------------------------------------------------------------------------- function get_bram_primitive (target_depth: integer; target_width: integer; family : family_type ) return bram_prim_type is Variable primitive : bram_prim_type; begin Case family Is When virtex2p | virtex2 => Case target_depth Is When 1 | 2 => primitive := indeterminate; -- depth is too small for BRAM -- based fifo control logic When 4 | 8 | 16 => -- primitive := use_srl; -- activate when SRL FIFO incorporated Case target_width Is -- use BRAM for now When 1 => primitive := B16_S1_S1; When 2 => primitive := B16_S2_S2; When 3 | 4 => primitive := B16_S4_S4; When 5 | 6 | 7 | 8 | 9 => primitive := B16_S9_S9; When 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 => primitive := B16_S18_S18; When others => primitive := B16_S36_S36; End case; when 32 | 64 | 128 | 256 | 512 => Case target_width Is When 1 => primitive := B16_S1_S1; When 2 => primitive := B16_S2_S2; When 3 | 4 => primitive := B16_S4_S4; When 5 | 6 | 7 | 8 | 9 => primitive := B16_S9_S9; When 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 => primitive := B16_S18_S18; When others => primitive := B16_S36_S36; End case; When 1024 => Case target_width Is When 1 => primitive := B16_S1_S1; When 2 => primitive := B16_S2_S2; When 3 | 4 => primitive := B16_S4_S4; When 5 | 6 | 7 | 8 | 9 => primitive := B16_S9_S9; When others => primitive := B16_S18_S18; End case; When 2048 => Case target_width Is When 1 => primitive := B16_S1_S1; When 2 => primitive := B16_S2_S2; When 3 | 4 => primitive := B16_S4_S4; When others => primitive := B16_S9_S9; End case; When 4096 => Case target_width Is When 1 => primitive := B16_S1_S1; When 2 => primitive := B16_S2_S2; When others => primitive := B16_S4_S4; End case; When 8192 => Case target_width Is When 1 => primitive := B16_S1_S1; When others => primitive := B16_S2_S2; End case; When 16384 => primitive := B16_S1_S1; When others => primitive := indeterminate; End case; When spartan2 | spartan2e | virtex | virtexe => Case target_depth Is When 1 | 2 => primitive := indeterminate; -- depth is too small for BRAM -- based fifo control logic When 4 | 8 | 16 => -- primitive := use_srl; -- activate this when SRL FIFO is -- incorporated Case target_width Is -- use BRAM for now When 1 => primitive := B4_S1_S1; When 2 => primitive := B4_S2_S2; When 3 | 4 => primitive := B4_S4_S4; When 5 | 6 | 7 | 8 => primitive := B4_S8_S8; When others => primitive := B4_S16_S16; End case; when 32 | 64 | 128 | 256 => Case target_width Is When 1 => primitive := B4_S1_S1; When 2 => primitive := B4_S2_S2; When 3 | 4 => primitive := B4_S4_S4; When 5 | 6 | 7 | 8 => primitive := B4_S8_S8; When others => primitive := B4_S16_S16; End case; when 512 => Case target_width Is When 1 => primitive := B4_S1_S1; When 2 => primitive := B4_S2_S2; When 3 | 4 => primitive := B4_S4_S4; When others => primitive := B4_S8_S8; End case; When 1024 => Case target_width Is When 1 => primitive := B4_S1_S1; When 2 => primitive := B4_S2_S2; When others => primitive := B4_S4_S4; End case; When 2048 => Case target_width Is When 1 => primitive := B4_S1_S1; When others => primitive := B4_S2_S2; End case; When 4096 => primitive := B4_S1_S1; When others => primitive := indeterminate; End case; When others => primitive := indeterminate; End case; Return primitive; end function get_bram_primitive; ----------------------------------------------------------------------------- -- This function calculates the number of BRAM primitives required as -- specified by the inputs for data width and BRAM primitive type. ----------------------------------------------------------------------------- function get_num_prims (bram_prim : bram_prim_type; mem_width : integer) return integer is Variable bram_num : integer; begin Case bram_prim Is When B16_S1_S1 | B4_S1_S1 => bram_num := mem_width; When B16_S2_S2 | B4_S2_S2 => bram_num := (mem_width+1)/2; When B16_S4_S4 | B4_S4_S4 => bram_num := (mem_width+3)/4; When B4_S8_S8 => bram_num := (mem_width+7)/8; When B16_S9_S9 => bram_num := (mem_width+8)/9; When B4_S16_S16 => bram_num := (mem_width+15)/16; When B16_S18_S18 => bram_num := (mem_width+17)/18; When B16_S36_S36 => bram_num := (mem_width+35)/36; When others => bram_num := 1; End case; Return (bram_num); end function get_num_prims; -- Now set the global CONSTANTS needed for IF-Generates -- Determine the number of BRAM storage locations needed constant FIFO_DEPTH : Integer := 2**C_DP_ADDRESS_WIDTH; -- Convert the input C_VIRTEX_II generic boolean to enumerated type Constant BRAM_FAMILY : family_type := get_prim_family(C_VIRTEX_II); -- Select the optimum BRAM primitive to use constant BRAM_PRIMITIVE : bram_prim_type := get_bram_primitive(FIFO_DEPTH, C_DP_DATA_WIDTH, BRAM_FAMILY); -- Calculate how many of the selected primitives are needed -- to populate the desired data width constant BRAM_NUM : integer := get_num_prims(BRAM_PRIMITIVE, C_DP_DATA_WIDTH); begin -- architecture ---------------------------------------------------------------------------- -- Using VII 512 x 36 Dual Port Primitive ---------------------------------------------------------------------------- Using_RAMB16_S36_S36 : if (BRAM_PRIMITIVE = B16_S36_S36) generate component RAMB16_S36_S36 port (DIA : in STD_LOGIC_VECTOR (31 downto 0); DIB : in STD_LOGIC_VECTOR (31 downto 0); DIPA : in STD_LOGIC_VECTOR (3 downto 0); DIPB : in STD_LOGIC_VECTOR (3 downto 0); ENA : in std_logic; ENB : in std_logic; WEA : in std_logic; WEB : in std_logic; SSRA : in std_logic; SSRB : in std_logic; CLKA : in std_logic; CLKB : in std_logic; ADDRA : in STD_LOGIC_VECTOR (8 downto 0); ADDRB : in STD_LOGIC_VECTOR (8 downto 0); DOA : out STD_LOGIC_VECTOR (31 downto 0); DOB : out STD_LOGIC_VECTOR (31 downto 0); DOPA : out STD_LOGIC_VECTOR (3 downto 0); DOPB : out STD_LOGIC_VECTOR (3 downto 0)); end component; Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep Constant PRIM_PDBUS_WIDTH : integer := 4; -- 4 parity data bits Constant PRIM_DBUS_WIDTH : integer := 32; -- 4 parity data bits Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH + PRIM_PDBUS_WIDTH; -- (data + parity) Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH; type dbus_slice_array is array(BRAM_NUM downto 1) of std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); type pdbus_slice_array is array(BRAM_NUM downto 1) of std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_enable : std_logic; signal port_a_wr_enable : std_logic; signal port_a_ssr : std_logic; signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_enable : std_logic; signal port_b_wr_enable : std_logic; signal port_b_ssr : std_logic; begin -- generate port_a_enable <= Wr_Enable; port_a_wr_enable <= Wr_Req; port_a_ssr <= Wr_rst; port_b_data_in <= (others => '0'); -- no input data to port B port_b_enable <= Rd_Enable; port_b_wr_enable <= '0'; -- no writing to port B port_b_ssr <= Rd_rst; -- translate big-endian and little_endian indexes of the -- data buses TRANSLATE_DATA : process (Wr_Data, port_b_data_out) Begin port_a_data_in <= (others => '0'); for i in C_DP_DATA_WIDTH-1 downto 0 loop port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i); Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i); End loop; End process TRANSLATE_DATA; -- translate big-endian and little_endian indexes of the -- address buses (makes simulation easier) TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address) Begin port_a_addr <= (others => '0'); port_b_addr <= (others => '0'); for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i); port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i); End loop; End process TRANSLATE_ADDRESS; slice_a_abus <= port_a_addr; slice_b_abus <= port_b_addr; BRAM_LOOP : for i in BRAM_NUM downto 1 generate slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH); slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH); port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i); port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i); slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH); slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH); port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i); port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i); -- Port A is fixed as the input (write) port -- Port B is fixed as the output (read) port I_DPB16_512x32 : RAMB16_S36_S36 port map( DIA => slice_a_dbus_in(i), DIB => slice_b_dbus_in(i), DIPA => slice_a_pdbus_in(i), DIPB => slice_b_pdbus_in(i), ENA => port_a_enable, ENB => port_b_enable, WEA => port_a_wr_enable, WEB => port_b_wr_enable, SSRA => port_a_ssr, SSRB => port_b_ssr, CLKA => Wr_Clk, CLKB => Rd_Clk, ADDRA => slice_a_abus, ADDRB => slice_b_abus, DOA => slice_a_dbus_out(i), DOB => slice_b_dbus_out(i), DOPA => slice_a_pdbus_out(i), DOPB => slice_b_pdbus_out(i) ); End generate BRAM_LOOP; end generate Using_RAMB16_S36_S36; --========================================================================== ---------------------------------------------------------------------------- -- Using VII 1024 x 18 Dual Port Primitive ---------------------------------------------------------------------------- Using_RAMB16_S18_S18 : if (BRAM_PRIMITIVE = B16_S18_S18) generate component RAMB16_S18_S18 port (DIA : in STD_LOGIC_VECTOR (15 downto 0); DIB : in STD_LOGIC_VECTOR (15 downto 0); DIPA : in STD_LOGIC_VECTOR (1 downto 0); DIPB : in STD_LOGIC_VECTOR (1 downto 0); ENA : in std_logic; ENB : in std_logic; WEA : in std_logic; WEB : in std_logic; SSRA : in std_logic; SSRB : in std_logic; CLKA : in std_logic; CLKB : in std_logic; ADDRA : in STD_LOGIC_VECTOR (9 downto 0); ADDRB : in STD_LOGIC_VECTOR (9 downto 0); DOA : out STD_LOGIC_VECTOR (15 downto 0); DOB : out STD_LOGIC_VECTOR (15 downto 0); DOPA : out STD_LOGIC_VECTOR (1 downto 0); DOPB : out STD_LOGIC_VECTOR (1 downto 0) ); end component; Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep Constant PRIM_PDBUS_WIDTH : integer := 2; -- 2 parity data bits Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH + PRIM_PDBUS_WIDTH; -- (data + parity) Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH; type dbus_slice_array is array(BRAM_NUM downto 1) of std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); type pdbus_slice_array is array(BRAM_NUM downto 1) of std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_enable : std_logic; signal port_a_wr_enable : std_logic; signal port_a_ssr : std_logic; signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_enable : std_logic; signal port_b_wr_enable : std_logic; signal port_b_ssr : std_logic; begin -- generate port_a_enable <= Wr_Enable; port_a_wr_enable <= Wr_Req; port_a_ssr <= Wr_rst; port_b_data_in <= (others => '0'); -- no input data to port B port_b_enable <= Rd_Enable; port_b_wr_enable <= '0'; -- no writing to port B port_b_ssr <= Rd_rst; -- translate big-endian and little_endian indexes of the -- data buses TRANSLATE_DATA : process (Wr_Data, port_b_data_out) Begin port_a_data_in <= (others => '0'); for i in C_DP_DATA_WIDTH-1 downto 0 loop port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i); Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i); End loop; End process TRANSLATE_DATA; -- translate big-endian and little_endian indexes of the -- address buses (makes simulation easier) TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address) Begin port_a_addr <= (others => '0'); port_b_addr <= (others => '0'); for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i); port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i); End loop; End process TRANSLATE_ADDRESS; slice_a_abus <= port_a_addr; slice_b_abus <= port_b_addr; BRAM_LOOP : for i in BRAM_NUM downto 1 generate slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH); slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH); port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i); port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i); slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH); slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH); port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i); port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i); -- Port A is fixed as the input (write) port -- Port B is fixed as the output (read) port I_DPB16_1024x18 : RAMB16_S18_S18 port map( DIA => slice_a_dbus_in(i), DIB => slice_b_dbus_in(i), DIPA => slice_a_pdbus_in(i), DIPB => slice_b_pdbus_in(i), ENA => port_a_enable, ENB => port_b_enable, WEA => port_a_wr_enable, WEB => port_b_wr_enable, SSRA => port_a_ssr, SSRB => port_b_ssr, CLKA => Wr_Clk, CLKB => Rd_Clk, ADDRA => slice_a_abus, ADDRB => slice_b_abus, DOA => slice_a_dbus_out(i), DOB => slice_b_dbus_out(i), DOPA => slice_a_pdbus_out(i), DOPB => slice_b_pdbus_out(i) ); End generate BRAM_LOOP; end generate Using_RAMB16_S18_S18; --========================================================================== ---------------------------------------------------------------------------- -- Using VII 2048 x 9 Dual Port Primitive ---------------------------------------------------------------------------- Using_RAMB16_S9_S9 : if (BRAM_PRIMITIVE = B16_S9_S9) generate component RAMB16_S9_S9 port ( DIA : in std_logic_vector (7 downto 0); DIB : in std_logic_vector (7 downto 0); DIPA : in std_logic_vector (0 downto 0); DIPB : in std_logic_vector (0 downto 0); ENA : in std_logic; ENB : in std_logic; WEA : in std_logic; WEB : in std_logic; SSRA : in std_logic; SSRB : in std_logic; CLKA : in std_logic; CLKB : in std_logic; ADDRA : in std_logic_vector (10 downto 0); ADDRB : in std_logic_vector (10 downto 0); DOA : out std_logic_vector (7 downto 0); DOB : out std_logic_vector (7 downto 0); DOPA : out std_logic_vector (0 downto 0); DOPB : out std_logic_vector (0 downto 0) ); end component; Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep Constant PRIM_PDBUS_WIDTH : integer := 1; -- 1 parity data bit Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH + PRIM_PDBUS_WIDTH; -- (data + parity) Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH; type dbus_slice_array is array(BRAM_NUM downto 1) of std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); type pdbus_slice_array is array(BRAM_NUM downto 1) of std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_enable : std_logic; signal port_a_wr_enable : std_logic; signal port_a_ssr : std_logic; signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_enable : std_logic; signal port_b_wr_enable : std_logic; signal port_b_ssr : std_logic; begin -- generate port_a_enable <= Wr_Enable; port_a_wr_enable <= Wr_Req; port_a_ssr <= Wr_rst; port_b_data_in <= (others => '0'); -- no input data to port B port_b_enable <= Rd_Enable; port_b_wr_enable <= '0'; -- no writing to port B port_b_ssr <= Rd_rst; -- translate big-endian and little_endian indexes of the -- data buses TRANSLATE_DATA : process (Wr_Data, port_b_data_out) Begin port_a_data_in <= (others => '0'); for i in C_DP_DATA_WIDTH-1 downto 0 loop port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i); Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i); End loop; End process TRANSLATE_DATA; -- translate big-endian and little_endian indexes of the -- address buses (makes simulation easier) TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address) Begin port_a_addr <= (others => '0'); port_b_addr <= (others => '0'); for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i); port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i); End loop; End process TRANSLATE_ADDRESS; slice_a_abus <= port_a_addr; slice_b_abus <= port_b_addr; BRAM_LOOP : for i in BRAM_NUM downto 1 generate slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH); slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH); port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i); port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i); slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH); slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH); port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i); port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i); -- Port A is fixed as the input (write) port -- Port B is fixed as the output (read) port I_DPB16_2048x9 : RAMB16_S9_S9 port map( DIA => slice_a_dbus_in(i), DIB => slice_b_dbus_in(i), DIPA => slice_a_pdbus_in(i), DIPB => slice_b_pdbus_in(i), ENA => port_a_enable, ENB => port_b_enable, WEA => port_a_wr_enable, WEB => port_b_wr_enable, SSRA => port_a_ssr, SSRB => port_b_ssr, CLKA => Wr_Clk, CLKB => Rd_Clk, ADDRA => slice_a_abus, ADDRB => slice_b_abus, DOA => slice_a_dbus_out(i), DOB => slice_b_dbus_out(i), DOPA => slice_a_pdbus_out(i), DOPB => slice_b_pdbus_out(i) ); End generate BRAM_LOOP; end generate Using_RAMB16_S9_S9; --========================================================================== ---------------------------------------------------------------------------- -- Using VII 4096 x 4 Dual Port Primitive ---------------------------------------------------------------------------- Using_RAMB16_S4_S4 : if (BRAM_PRIMITIVE = B16_S4_S4) generate component RAMB16_S4_S4 port ( DIA : in std_logic_vector (3 downto 0); DIB : in std_logic_vector (3 downto 0); ENA : in std_logic; ENB : in std_logic; WEA : in std_logic; WEB : in std_logic; SSRA : in std_logic; SSRB : in std_logic; CLKA : in std_logic; CLKB : in std_logic; ADDRA : in std_logic_vector (11 downto 0); ADDRB : in std_logic_vector (11 downto 0); DOA : out std_logic_vector (3 downto 0); DOB : out std_logic_vector (3 downto 0) ); end component; Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH + PRIM_PDBUS_WIDTH; -- (data + parity) Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH; type dbus_slice_array is array(BRAM_NUM downto 1) of std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); --type pdbus_slice_array is array(BRAM_NUM downto 1) of -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); --Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); --Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); --Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); --Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_enable : std_logic; signal port_a_wr_enable : std_logic; signal port_a_ssr : std_logic; signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_enable : std_logic; signal port_b_wr_enable : std_logic; signal port_b_ssr : std_logic; begin -- generate port_a_enable <= Wr_Enable; port_a_wr_enable <= Wr_Req; port_a_ssr <= Wr_rst; port_b_data_in <= (others => '0'); -- no input data to port B port_b_enable <= Rd_Enable; port_b_wr_enable <= '0'; -- no writing to port B port_b_ssr <= Rd_rst; -- translate big-endian and little_endian indexes of the -- data buses TRANSLATE_DATA : process (Wr_Data, port_b_data_out) Begin port_a_data_in <= (others => '0'); for i in C_DP_DATA_WIDTH-1 downto 0 loop port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i); Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i); End loop; End process TRANSLATE_DATA; -- translate big-endian and little_endian indexes of the -- address buses (makes simulation easier) TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address) Begin port_a_addr <= (others => '0'); port_b_addr <= (others => '0'); for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i); port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i); End loop; End process TRANSLATE_ADDRESS; slice_a_abus <= port_a_addr; slice_b_abus <= port_b_addr; BRAM_LOOP : for i in BRAM_NUM downto 1 generate --slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto -- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH); slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH); --port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto -- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i); port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i); --slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto -- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH); slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH); --port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto -- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i); port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i); -- Port A is fixed as the input (write) port -- Port B is fixed as the output (read) port I_DPB16_4096x4 : RAMB16_S4_S4 port map( DIA => slice_a_dbus_in(i), DIB => slice_b_dbus_in(i), ENA => port_a_enable, ENB => port_b_enable, WEA => port_a_wr_enable, WEB => port_b_wr_enable, SSRA => port_a_ssr, SSRB => port_b_ssr, CLKA => Wr_Clk, CLKB => Rd_Clk, ADDRA => slice_a_abus, ADDRB => slice_b_abus, DOA => slice_a_dbus_out(i), DOB => slice_b_dbus_out(i) ); End generate BRAM_LOOP; end generate Using_RAMB16_S4_S4; --========================================================================== ---------------------------------------------------------------------------- -- Using VII 8192 x 2 Dual Port Primitive ---------------------------------------------------------------------------- Using_RAMB16_S2_S2 : if (BRAM_PRIMITIVE = B16_S2_S2) generate component RAMB16_S2_S2 port ( DIA : in std_logic_vector (1 downto 0); DIB : in std_logic_vector (1 downto 0); ENA : in std_logic; ENB : in std_logic; WEA : in std_logic; WEB : in std_logic; SSRA : in std_logic; SSRB : in std_logic; CLKA : in std_logic; CLKB : in std_logic; ADDRA : in std_logic_vector (12 downto 0); ADDRB : in std_logic_vector (12 downto 0); DOA : out std_logic_vector (1 downto 0); DOB : out std_logic_vector (1 downto 0) ); end component; Constant PRIM_ADDR_WIDTH : integer := 13; -- 8192 deep Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH + PRIM_PDBUS_WIDTH; -- (data + parity) Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH; type dbus_slice_array is array(BRAM_NUM downto 1) of std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); --type pdbus_slice_array is array(BRAM_NUM downto 1) of -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); --Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); --Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); --Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); --Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_enable : std_logic; signal port_a_wr_enable : std_logic; signal port_a_ssr : std_logic; signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_enable : std_logic; signal port_b_wr_enable : std_logic; signal port_b_ssr : std_logic; begin -- generate port_a_enable <= Wr_Enable; port_a_wr_enable <= Wr_Req; port_a_ssr <= Wr_rst; port_b_data_in <= (others => '0'); -- no input data to port B port_b_enable <= Rd_Enable; port_b_wr_enable <= '0'; -- no writing to port B port_b_ssr <= Rd_rst; -- translate big-endian and little_endian indexes of the -- data buses TRANSLATE_DATA : process (Wr_Data, port_b_data_out) Begin port_a_data_in <= (others => '0'); for i in C_DP_DATA_WIDTH-1 downto 0 loop port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i); Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i); End loop; End process TRANSLATE_DATA; -- translate big-endian and little_endian indexes of the -- address buses (makes simulation easier) TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address) Begin port_a_addr <= (others => '0'); port_b_addr <= (others => '0'); for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i); port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i); End loop; End process TRANSLATE_ADDRESS; slice_a_abus <= port_a_addr; slice_b_abus <= port_b_addr; BRAM_LOOP : for i in BRAM_NUM downto 1 generate --slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto -- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH); slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH); --port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto -- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i); port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i); --slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto -- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH); slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH); --port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto -- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i); port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i); -- Port A is fixed as the input (write) port -- Port B is fixed as the output (read) port I_DPB16_8192x2 : RAMB16_S2_S2 port map( DIA => slice_a_dbus_in(i), DIB => slice_b_dbus_in(i), ENA => port_a_enable, ENB => port_b_enable, WEA => port_a_wr_enable, WEB => port_b_wr_enable, SSRA => port_a_ssr, SSRB => port_b_ssr, CLKA => Wr_Clk, CLKB => Rd_Clk, ADDRA => slice_a_abus, ADDRB => slice_b_abus, DOA => slice_a_dbus_out(i), DOB => slice_b_dbus_out(i) ); End generate BRAM_LOOP; end generate Using_RAMB16_S2_S2; --========================================================================== ---------------------------------------------------------------------------- -- Using VII 16384 x 1 Dual Port Primitive ---------------------------------------------------------------------------- Using_RAMB16_S1_S1 : if (BRAM_PRIMITIVE = B16_S1_S1) generate component RAMB16_S1_S1 port ( DIA : in std_logic_vector (0 downto 0); DIB : in std_logic_vector (0 downto 0); ENA : in std_logic; ENB : in std_logic; WEA : in std_logic; WEB : in std_logic; SSRA : in std_logic; SSRB : in std_logic; CLKA : in std_logic; CLKB : in std_logic; ADDRA : in std_logic_vector (13 downto 0); ADDRB : in std_logic_vector (13 downto 0); DOA : out std_logic_vector (0 downto 0); DOB : out std_logic_vector (0 downto 0) ); end component; Constant PRIM_ADDR_WIDTH : integer := 14; -- 16384 deep Constant PRIM_PDBUS_WIDTH : integer := 0; -- 0 parity data bits Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bits Constant SLICE_DBUS_WIDTH : integer := PRIM_DBUS_WIDTH + PRIM_PDBUS_WIDTH; -- (data + parity) Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * SLICE_DBUS_WIDTH; type dbus_slice_array is array(BRAM_NUM downto 1) of std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); --type pdbus_slice_array is array(BRAM_NUM downto 1) of -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_a_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); --Signal slice_a_pdbus_in : pdbus_slice_array; -- std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_a_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); --Signal slice_a_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_b_dbus_in : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); --Signal slice_b_pdbus_in : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_b_dbus_out : dbus_slice_array; --std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); --Signal slice_b_pdbus_out : pdbus_slice_array; --std_logic_vector(PRIM_PDBUS_WIDTH-1 downto 0); Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_enable : std_logic; signal port_a_wr_enable : std_logic; signal port_a_ssr : std_logic; signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_enable : std_logic; signal port_b_wr_enable : std_logic; signal port_b_ssr : std_logic; begin -- generate port_a_enable <= Wr_Enable; port_a_wr_enable <= Wr_Req; port_a_ssr <= Wr_rst; port_b_data_in <= (others => '0'); -- no input data to port B port_b_enable <= Rd_Enable; port_b_wr_enable <= '0'; -- no writing to port B port_b_ssr <= Rd_rst; -- translate big-endian and little_endian indexes of the -- data buses TRANSLATE_DATA : process (Wr_Data, port_b_data_out) Begin port_a_data_in <= (others => '0'); for i in C_DP_DATA_WIDTH-1 downto 0 loop port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i); Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i); End loop; End process TRANSLATE_DATA; -- translate big-endian and little_endian indexes of the -- address buses (makes simulation easier) TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address) Begin port_a_addr <= (others => '0'); port_b_addr <= (others => '0'); for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i); port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i); End loop; End process TRANSLATE_ADDRESS; slice_a_abus <= port_a_addr; slice_b_abus <= port_b_addr; BRAM_LOOP : for i in BRAM_NUM downto 1 generate --slice_a_pdbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-1 downto -- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH); slice_a_dbus_in(i) <= port_a_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH); --port_a_data_out((i*SLICE_DBUS_WIDTH)-1 downto -- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_a_pdbus_out(i); port_a_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i); --slice_b_pdbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-1 downto -- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH); slice_b_dbus_in(i) <= port_b_data_in((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH); --port_b_data_out((i*SLICE_DBUS_WIDTH)-1 downto -- (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH) <= slice_b_pdbus_out(i); port_b_data_out((i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-1 downto (i*SLICE_DBUS_WIDTH)-PRIM_PDBUS_WIDTH-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i); -- Port A is fixed as the input (write) port -- Port B is fixed as the output (read) port I_DPB16_16384x1 : RAMB16_S1_S1 port map( DIA => slice_a_dbus_in(i), DIB => slice_b_dbus_in(i), ENA => port_a_enable, ENB => port_b_enable, WEA => port_a_wr_enable, WEB => port_b_wr_enable, SSRA => port_a_ssr, SSRB => port_b_ssr, CLKA => Wr_Clk, CLKB => Rd_Clk, ADDRA => slice_a_abus, ADDRB => slice_b_abus, DOA => slice_a_dbus_out(i), DOB => slice_b_dbus_out(i) ); End generate BRAM_LOOP; end generate Using_RAMB16_S1_S1; --========================================================================== -- End of Virtex-II and Virtex-II Pro support --/////////////////////////////////////////////////////////////////////////// --/////////////////////////////////////////////////////////////////////////// -- Start Spartan-II, Spartan-IIE, Virtex, and VirtexE support ---------------------------------------------------------------------------- -- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE -- 4096 x 1 Dual Port Primitive ---------------------------------------------------------------------------- Using_RAMB4_S1_S1 : if (BRAM_PRIMITIVE = B4_S1_S1) generate component RAMB4_S1_S1 port ( DIA : in std_logic_vector (0 downto 0); DIB : in std_logic_vector (0 downto 0); ENA : in std_logic; ENB : in std_logic; WEA : in std_logic; WEB : in std_logic; RSTA : in std_logic; RSTB : in std_logic; CLKA : in std_logic; CLKB : in std_logic; ADDRA : in std_logic_vector (11 downto 0); ADDRB : in std_logic_vector (11 downto 0); DOA : out std_logic_vector (0 downto 0); DOB : out std_logic_vector (0 downto 0)); end component; Constant PRIM_ADDR_WIDTH : integer := 12; -- 4096 deep Constant PRIM_DBUS_WIDTH : integer := 1; -- 1 data bit Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH; type dbus_slice_array is array(BRAM_NUM downto 1) of std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); Signal slice_a_dbus_in : dbus_slice_array; Signal slice_a_dbus_out : dbus_slice_array; Signal slice_b_dbus_in : dbus_slice_array; Signal slice_b_dbus_out : dbus_slice_array; Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_enable : std_logic; signal port_a_wr_enable : std_logic; signal port_a_ssr : std_logic; signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_enable : std_logic; signal port_b_wr_enable : std_logic; signal port_b_ssr : std_logic; begin -- generate port_a_enable <= Wr_Enable; port_a_wr_enable <= Wr_Req; port_a_ssr <= wr_rst; -- no output reset value port_b_data_in <= (others => '0'); -- no input data to port B port_b_enable <= Rd_Enable; port_b_wr_enable <= '0'; -- no writing to port B port_b_ssr <= rd_rst; -- no output reset value -- translate big-endian and little_endian indexes of the -- data buses TRANSLATE_DATA : process (Wr_Data, port_b_data_out) Begin port_a_data_in <= (others => '0'); for i in C_DP_DATA_WIDTH-1 downto 0 loop port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i); Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i); End loop; End process TRANSLATE_DATA; -- translate big-endian and little_endian indexes of the -- address buses (makes simulation easier) TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address) Begin port_a_addr <= (others => '0'); port_b_addr <= (others => '0'); for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i); port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i); End loop; End process TRANSLATE_ADDRESS; slice_a_abus <= port_a_addr; slice_b_abus <= port_b_addr; BRAM_LOOP : for i in BRAM_NUM downto 1 generate slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto (i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH); port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto (i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i); slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto (i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH); port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto (i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i); -- Port A is fixed as the input (write) port -- Port B is fixed as the output (read) port I_DPB4_4096x1 : RAMB4_S1_S1 port map( DIA => slice_a_dbus_in(i), DIB => slice_b_dbus_in(i), ENA => port_a_enable, ENB => port_b_enable, WEA => port_a_wr_enable, WEB => port_b_wr_enable, RSTA => port_a_ssr, RSTB => port_b_ssr, CLKA => Wr_Clk, CLKB => Rd_Clk, ADDRA => slice_a_abus, ADDRB => slice_b_abus, DOA => slice_a_dbus_out(i), DOB => slice_b_dbus_out(i) ); End generate BRAM_LOOP; end generate Using_RAMB4_S1_S1; --========================================================================== ---------------------------------------------------------------------------- -- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE -- 2048 x 2 Dual Port Primitive ---------------------------------------------------------------------------- Using_RAMB4_S2_S2 : if (BRAM_PRIMITIVE = B4_S2_S2) generate component RAMB4_S2_S2 port ( DIA : in std_logic_vector (1 downto 0); DIB : in std_logic_vector (1 downto 0); ENA : in std_logic; ENB : in std_logic; WEA : in std_logic; WEB : in std_logic; RSTA : in std_logic; RSTB : in std_logic; CLKA : in std_logic; CLKB : in std_logic; ADDRA : in std_logic_vector (10 downto 0); ADDRB : in std_logic_vector (10 downto 0); DOA : out std_logic_vector (1 downto 0); DOB : out std_logic_vector (1 downto 0)); end component; Constant PRIM_ADDR_WIDTH : integer := 11; -- 2048 deep Constant PRIM_DBUS_WIDTH : integer := 2; -- 2 data bits Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH; type dbus_slice_array is array(BRAM_NUM downto 1) of std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); Signal slice_a_dbus_in : dbus_slice_array; Signal slice_a_dbus_out : dbus_slice_array; Signal slice_b_dbus_in : dbus_slice_array; Signal slice_b_dbus_out : dbus_slice_array; Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_enable : std_logic; signal port_a_wr_enable : std_logic; signal port_a_ssr : std_logic; signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_enable : std_logic; signal port_b_wr_enable : std_logic; signal port_b_ssr : std_logic; begin -- generate port_a_enable <= Wr_Enable; port_a_wr_enable <= Wr_Req; port_a_ssr <= wr_rst; -- no output reset value port_b_data_in <= (others => '0'); -- no input data to port B port_b_enable <= Rd_Enable; port_b_wr_enable <= '0'; -- no writing to port B port_b_ssr <= rd_rst; -- no output reset value -- translate big-endian and little_endian indexes of the -- data buses TRANSLATE_DATA : process (Wr_Data, port_b_data_out) Begin port_a_data_in <= (others => '0'); for i in C_DP_DATA_WIDTH-1 downto 0 loop port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i); Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i); End loop; End process TRANSLATE_DATA; -- translate big-endian and little_endian indexes of the -- address buses (makes simulation easier) TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address) Begin port_a_addr <= (others => '0'); port_b_addr <= (others => '0'); for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i); port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i); End loop; End process TRANSLATE_ADDRESS; slice_a_abus <= port_a_addr; slice_b_abus <= port_b_addr; BRAM_LOOP : for i in BRAM_NUM downto 1 generate slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto (i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH); port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto (i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i); slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto (i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH); port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto (i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i); -- Port A is fixed as the input (write) port -- Port B is fixed as the output (read) port I_DPB4_2048x2 : RAMB4_S2_S2 port map( DIA => slice_a_dbus_in(i), DIB => slice_b_dbus_in(i), ENA => port_a_enable, ENB => port_b_enable, WEA => port_a_wr_enable, WEB => port_b_wr_enable, RSTA => port_a_ssr, RSTB => port_b_ssr, CLKA => Wr_Clk, CLKB => Rd_Clk, ADDRA => slice_a_abus, ADDRB => slice_b_abus, DOA => slice_a_dbus_out(i), DOB => slice_b_dbus_out(i) ); End generate BRAM_LOOP; end generate Using_RAMB4_S2_S2; --========================================================================== ---------------------------------------------------------------------------- -- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE -- 1024 x 4 Dual Port Primitive ---------------------------------------------------------------------------- Using_RAMB4_S4_S4 : if (BRAM_PRIMITIVE = B4_S4_S4) generate component RAMB4_S4_S4 port ( DIA : in std_logic_vector (3 downto 0); DIB : in std_logic_vector (3 downto 0); ENA : in std_logic; ENB : in std_logic; WEA : in std_logic; WEB : in std_logic; RSTA : in std_logic; RSTB : in std_logic; CLKA : in std_logic; CLKB : in std_logic; ADDRA : in std_logic_vector (9 downto 0); ADDRB : in std_logic_vector (9 downto 0); DOA : out std_logic_vector (3 downto 0); DOB : out std_logic_vector (3 downto 0)); end component; Constant PRIM_ADDR_WIDTH : integer := 10; -- 1024 deep Constant PRIM_DBUS_WIDTH : integer := 4; -- 4 data bits Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH; type dbus_slice_array is array(BRAM_NUM downto 1) of std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); Signal slice_a_dbus_in : dbus_slice_array; Signal slice_a_dbus_out : dbus_slice_array; Signal slice_b_dbus_in : dbus_slice_array; Signal slice_b_dbus_out : dbus_slice_array; Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_enable : std_logic; signal port_a_wr_enable : std_logic; signal port_a_ssr : std_logic; signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_enable : std_logic; signal port_b_wr_enable : std_logic; signal port_b_ssr : std_logic; begin -- generate port_a_enable <= Wr_Enable; port_a_wr_enable <= Wr_Req; port_a_ssr <= wr_rst; -- no output reset value port_b_data_in <= (others => '0'); -- no input data to port B port_b_enable <= Rd_Enable; port_b_wr_enable <= '0'; -- no writing to port B port_b_ssr <= rd_rst; -- no output reset value -- translate big-endian and little_endian indexes of the -- data buses TRANSLATE_DATA : process (Wr_Data, port_b_data_out) Begin port_a_data_in <= (others => '0'); for i in C_DP_DATA_WIDTH-1 downto 0 loop port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i); Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i); End loop; End process TRANSLATE_DATA; -- translate big-endian and little_endian indexes of the -- address buses (makes simulation easier) TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address) Begin port_a_addr <= (others => '0'); port_b_addr <= (others => '0'); for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i); port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i); End loop; End process TRANSLATE_ADDRESS; slice_a_abus <= port_a_addr; slice_b_abus <= port_b_addr; BRAM_LOOP : for i in BRAM_NUM downto 1 generate slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto (i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH); port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto (i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i); slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto (i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH); port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto (i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i); -- Port A is fixed as the input (write) port -- Port B is fixed as the output (read) port I_DPB4_1024x4 : RAMB4_S4_S4 port map( DIA => slice_a_dbus_in(i), DIB => slice_b_dbus_in(i), ENA => port_a_enable, ENB => port_b_enable, WEA => port_a_wr_enable, WEB => port_b_wr_enable, RSTA => port_a_ssr, RSTB => port_b_ssr, CLKA => Wr_Clk, CLKB => Rd_Clk, ADDRA => slice_a_abus, ADDRB => slice_b_abus, DOA => slice_a_dbus_out(i), DOB => slice_b_dbus_out(i) ); End generate BRAM_LOOP; end generate Using_RAMB4_S4_S4; --========================================================================== ---------------------------------------------------------------------------- -- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE -- 512 x 8 Dual Port Primitive ---------------------------------------------------------------------------- Using_RAMB4_S8_S8 : if (BRAM_PRIMITIVE = B4_S8_S8) generate component RAMB4_S8_S8 port ( DIA : in std_logic_vector (7 downto 0); DIB : in std_logic_vector (7 downto 0); ENA : in std_logic; ENB : in std_logic; WEA : in std_logic; WEB : in std_logic; RSTA : in std_logic; RSTB : in std_logic; CLKA : in std_logic; CLKB : in std_logic; ADDRA : in std_logic_vector (8 downto 0); ADDRB : in std_logic_vector (8 downto 0); DOA : out std_logic_vector (7 downto 0); DOB : out std_logic_vector (7 downto 0)); end component; Constant PRIM_ADDR_WIDTH : integer := 9; -- 512 deep Constant PRIM_DBUS_WIDTH : integer := 8; -- 8 data bits Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH; type dbus_slice_array is array(BRAM_NUM downto 1) of std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); Signal slice_a_dbus_in : dbus_slice_array; Signal slice_a_dbus_out : dbus_slice_array; Signal slice_b_dbus_in : dbus_slice_array; Signal slice_b_dbus_out : dbus_slice_array; Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_enable : std_logic; signal port_a_wr_enable : std_logic; signal port_a_ssr : std_logic; signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_enable : std_logic; signal port_b_wr_enable : std_logic; signal port_b_ssr : std_logic; begin -- generate port_a_enable <= Wr_Enable; port_a_wr_enable <= Wr_Req; port_a_ssr <= wr_rst; -- no output reset value port_b_data_in <= (others => '0'); -- no input data to port B port_b_enable <= Rd_Enable; port_b_wr_enable <= '0'; -- no writing to port B port_b_ssr <= rd_rst; -- no output reset value -- translate big-endian and little_endian indexes of the -- data buses TRANSLATE_DATA : process (Wr_Data, port_b_data_out) Begin port_a_data_in <= (others => '0'); for i in C_DP_DATA_WIDTH-1 downto 0 loop port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i); Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i); End loop; End process TRANSLATE_DATA; -- translate big-endian and little_endian indexes of the -- address buses (makes simulation easier) TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address) Begin port_a_addr <= (others => '0'); port_b_addr <= (others => '0'); for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i); port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i); End loop; End process TRANSLATE_ADDRESS; slice_a_abus <= port_a_addr; slice_b_abus <= port_b_addr; BRAM_LOOP : for i in BRAM_NUM downto 1 generate slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto (i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH); port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto (i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i); slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto (i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH); port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto (i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i); -- Port A is fixed as the input (write) port -- Port B is fixed as the output (read) port I_DPB4_512x8 : RAMB4_S8_S8 port map( DIA => slice_a_dbus_in(i), DIB => slice_b_dbus_in(i), ENA => port_a_enable, ENB => port_b_enable, WEA => port_a_wr_enable, WEB => port_b_wr_enable, RSTA => port_a_ssr, RSTB => port_b_ssr, CLKA => Wr_Clk, CLKB => Rd_Clk, ADDRA => slice_a_abus, ADDRB => slice_b_abus, DOA => slice_a_dbus_out(i), DOB => slice_b_dbus_out(i) ); End generate BRAM_LOOP; end generate Using_RAMB4_S8_S8; --========================================================================== ---------------------------------------------------------------------------- -- Using Spartan-II, Spartan-IIE, Virtex, and VirtexE -- 256 x 16 Dual Port Primitive ---------------------------------------------------------------------------- Using_RAMB4_S16_S16 : if (BRAM_PRIMITIVE = B4_S16_S16) generate component RAMB4_S16_S16 port (DIA : in STD_LOGIC_VECTOR (15 downto 0); DIB : in STD_LOGIC_VECTOR (15 downto 0); ENA : in std_logic; ENB : in std_logic; WEA : in std_logic; WEB : in std_logic; RSTA : in std_logic; RSTB : in std_logic; CLKA : in std_logic; CLKB : in std_logic; ADDRA : in STD_LOGIC_VECTOR (7 downto 0); ADDRB : in STD_LOGIC_VECTOR (7 downto 0); DOA : out STD_LOGIC_VECTOR (15 downto 0); DOB : out STD_LOGIC_VECTOR (15 downto 0)); end component; Constant PRIM_ADDR_WIDTH : integer := 8; -- 256 deep Constant PRIM_DBUS_WIDTH : integer := 16; -- 16 data bits Constant BRAM_DATA_WIDTH : integer := BRAM_NUM * PRIM_DBUS_WIDTH; type dbus_slice_array is array(BRAM_NUM downto 1) of std_logic_vector(PRIM_DBUS_WIDTH-1 downto 0); Signal slice_a_dbus_in : dbus_slice_array; Signal slice_a_dbus_out : dbus_slice_array; Signal slice_b_dbus_in : dbus_slice_array; Signal slice_b_dbus_out : dbus_slice_array; Signal slice_a_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); Signal slice_b_abus : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_a_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_a_enable : std_logic; signal port_a_wr_enable : std_logic; signal port_a_ssr : std_logic; signal port_b_addr : std_logic_vector(PRIM_ADDR_WIDTH-1 downto 0); signal port_b_data_in : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_data_out : std_logic_vector(BRAM_DATA_WIDTH-1 downto 0); signal port_b_enable : std_logic; signal port_b_wr_enable : std_logic; signal port_b_ssr : std_logic; begin -- generate port_a_enable <= Wr_Enable; port_a_wr_enable <= Wr_Req; port_a_ssr <= wr_rst; -- no output reset value port_b_data_in <= (others => '0'); -- no input data to port B port_b_enable <= Rd_Enable; port_b_wr_enable <= '0'; -- no writing to port B port_b_ssr <= rd_rst; -- no output reset value -- translate big-endian and little_endian indexes of the -- data buses TRANSLATE_DATA : process (Wr_Data, port_b_data_out) Begin port_a_data_in <= (others => '0'); for i in C_DP_DATA_WIDTH-1 downto 0 loop port_a_data_in(i) <= Wr_Data(C_DP_DATA_WIDTH-1-i); Rd_Data(C_DP_DATA_WIDTH-1-i) <= port_b_data_out(i); End loop; End process TRANSLATE_DATA; -- translate big-endian and little_endian indexes of the -- address buses (makes simulation easier) TRANSLATE_ADDRESS : process (Wr_Address, Rd_Address) Begin port_a_addr <= (others => '0'); port_b_addr <= (others => '0'); for i in C_DP_ADDRESS_WIDTH-1 downto 0 loop port_a_addr(i) <= Wr_Address(C_DP_ADDRESS_WIDTH-1-i); port_b_addr(i) <= Rd_Address(C_DP_ADDRESS_WIDTH-1-i); End loop; End process TRANSLATE_ADDRESS; slice_a_abus <= port_a_addr; slice_b_abus <= port_b_addr; BRAM_LOOP : for i in BRAM_NUM downto 1 generate slice_a_dbus_in(i) <= port_a_data_in((i*PRIM_DBUS_WIDTH)-1 downto (i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH); port_a_data_out((i*PRIM_DBUS_WIDTH)-1 downto (i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_a_dbus_out(i); slice_b_dbus_in(i) <= port_b_data_in((i*PRIM_DBUS_WIDTH)-1 downto (i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH); port_b_data_out((i*PRIM_DBUS_WIDTH)-1 downto (i*PRIM_DBUS_WIDTH)-PRIM_DBUS_WIDTH) <= slice_b_dbus_out(i); -- Port A is fixed as the input (write) port -- Port B is fixed as the output (read) port I_DPB4_256x16 : RAMB4_S16_S16 port map( DIA => slice_a_dbus_in(i), DIB => slice_b_dbus_in(i), ENA => port_a_enable, ENB => port_b_enable, WEA => port_a_wr_enable, WEB => port_b_wr_enable, RSTA => port_a_ssr, RSTB => port_b_ssr, CLKA => Wr_Clk, CLKB => Rd_Clk, ADDRA => slice_a_abus, ADDRB => slice_b_abus, DOA => slice_a_dbus_out(i), DOB => slice_b_dbus_out(i) ); End generate BRAM_LOOP; end generate Using_RAMB4_S16_S16; --========================================================================== UNSUPPORTED_FAMILY : if (BRAM_PRIMITIVE = indeterminate) generate begin -- assert (false) -- report "Unsupported Part Family Selected or FIFO Depth/Width is invalid!" -- severity failure; -- end generate UNSUPPORTED_FAMILY; end architecture implementation;

mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_1_1/fifo_generator_v11_0/ramfifo/clk_x_pntrs.vhd

19

35009

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mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_1_1/proc_common_v4_0/hdl/src/vhdl/inferred_lut4.vhd

15

7214

------------------------------------------------------------------------------- -- $Id: inferred_lut4.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $ ------------------------------------------------------------------------------- -- inferred_lut4.vhd ------------------------------------------------------------------------------- -- -- ************************************************************************* -- ** ** -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This text/file contains proprietary, confidential ** -- ** information of Xilinx, Inc., is distributed under ** -- ** license from Xilinx, Inc., and may be used, copied ** -- ** and/or disclosed only pursuant to the terms of a valid ** -- ** license agreement with Xilinx, Inc. Xilinx hereby ** -- ** grants you a license to use this text/file solely for ** -- ** design, simulation, implementation and creation of ** -- ** design files limited to Xilinx devices or technologies. ** -- ** Use with non-Xilinx devices or technologies is expressly ** -- ** prohibited and immediately terminates your license unless ** -- ** covered by a separate agreement. ** -- ** ** -- ** Xilinx is providing this design, code, or information ** -- ** "as-is" solely for use in developing programs and ** -- ** solutions for Xilinx devices, with no obligation on the ** -- ** part of Xilinx to provide support. By providing this design, ** -- ** code, or information as one possible implementation of ** -- ** this feature, application or standard, Xilinx is making no ** -- ** representation that this implementation is free from any ** -- ** claims of infringement. You are responsible for obtaining ** -- ** any rights you may require for your implementation. ** -- ** Xilinx expressly disclaims any warranty whatsoever with ** -- ** respect to the adequacy of the implementation, including ** -- ** but not limited to any warranties or representations that this ** -- ** implementation is free from claims of infringement, implied ** -- ** warranties of merchantability or fitness for a particular ** -- ** purpose. ** -- ** ** -- ** Xilinx products are not intended for use in life support ** -- ** appliances, devices, or systems. Use in such applications is ** -- ** expressly prohibited. ** -- ** ** -- ** Any modifications that are made to the Source Code are ** -- ** done at the users sole risk and will be unsupported. ** -- ** The Xilinx Support Hotline does not have access to source ** -- ** code and therefore cannot answer specific questions related ** -- ** to source HDL. The Xilinx Hotline support of original source ** -- ** code IP shall only address issues and questions related ** -- ** to the standard Netlist version of the core (and thus ** -- ** indirectly, the original core source). ** -- ** ** -- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** This copyright and support notice must be retained as part ** -- ** of this text at all times. ** -- ** ** -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: inferred_lut4.vhd -- -- Description: This module is used to infer a LUT4 instantiation in -- structural VHDL. It is compatable with Synplicity and xst -- synthesis tools. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- inferred_lut4.vhd -- ------------------------------------------------------------------------------- -- Author: D.Thorpe -- -- History: -- DET 2001-10-11 LUT4 implementation to work around xst lut4 problem with -- INIT generic. Adapted from XST France work-around -- solution sent to Bert Tise. -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "Bus_clk", "Bus_clk_div#", "Bus_clk_#x" -- Bus_rst signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library ieee; use ieee.std_logic_arith.all; library ieee; use ieee.std_logic_unsigned.all; ------------------------------------------------------------------------------- entity inferred_lut4 is generic (INIT : bit_vector(15 downto 0)); port ( O : out std_logic; I0 : in std_logic; I1 : in std_logic; I2 : in std_logic; I3 : in std_logic ); end entity inferred_lut4; ------------------------------------------------------------------------------- architecture implementation of inferred_lut4 is signal b : std_logic_vector(3 downto 0); signal tmp : integer range 0 to 15; begin b <= (I3, I2, I1, I0); tmp <= conv_integer(b); O <= To_StdUlogic(INIT(tmp)); end architecture implementation;

mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_1_1/blk_mem_gen_v8_1/blk_mem_axi_write_wrapper.vhd

27

66283

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mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/fifo_generator_v11_0/ramfifo/bram_fifo_rstlogic.vhd

19

21262

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block dKfOe1Fgzj6faSFeL/IK/IGbXRIzt9OQ8DZnq2KAQwbAq1xs/txiDbhMB5jT5GTGOpfv1lX7K9mJ mDVaIsrDmA== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block cmnaZ+nYMcuVxuKDdMnuchBB9inZOxPR3/E/irYVdWCPhl0UM4JuWPFoKMQnAcsoQ3vgnwO/qltn 0x8JvlvddPokOTwabXK7+R741NBmTaawP5Y3zobRhI33jusePpwNTanCHaHjalZxzALXRseOguzG AwGiKgpBkrzwT+frUqs= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_1_1/proc_common_v4_0/hdl/src/vhdl/pf_occ_counter.vhd

15

10945

------------------------------------------------------------------------------- -- $Id: pf_occ_counter.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $ ------------------------------------------------------------------------------- -- pf_occ_counter - entity/architecture pair ------------------------------------------------------------------------------- -- -- ************************************************************************* -- ** ** -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This text/file contains proprietary, confidential ** -- ** information of Xilinx, Inc., is distributed under ** -- ** license from Xilinx, Inc., and may be used, copied ** -- ** and/or disclosed only pursuant to the terms of a valid ** -- ** license agreement with Xilinx, Inc. Xilinx hereby ** -- ** grants you a license to use this text/file solely for ** -- ** design, simulation, implementation and creation of ** -- ** design files limited to Xilinx devices or technologies. ** -- ** Use with non-Xilinx devices or technologies is expressly ** -- ** prohibited and immediately terminates your license unless ** -- ** covered by a separate agreement. ** -- ** ** -- ** Xilinx is providing this design, code, or information ** -- ** "as-is" solely for use in developing programs and ** -- ** solutions for Xilinx devices, with no obligation on the ** -- ** part of Xilinx to provide support. By providing this design, ** -- ** code, or information as one possible implementation of ** -- ** this feature, application or standard, Xilinx is making no ** -- ** representation that this implementation is free from any ** -- ** claims of infringement. You are responsible for obtaining ** -- ** any rights you may require for your implementation. ** -- ** Xilinx expressly disclaims any warranty whatsoever with ** -- ** respect to the adequacy of the implementation, including ** -- ** but not limited to any warranties or representations that this ** -- ** implementation is free from claims of infringement, implied ** -- ** warranties of merchantability or fitness for a particular ** -- ** purpose. ** -- ** ** -- ** Xilinx products are not intended for use in life support ** -- ** appliances, devices, or systems. Use in such applications is ** -- ** expressly prohibited. ** -- ** ** -- ** Any modifications that are made to the Source Code are ** -- ** done at the users sole risk and will be unsupported. ** -- ** The Xilinx Support Hotline does not have access to source ** -- ** code and therefore cannot answer specific questions related ** -- ** to source HDL. The Xilinx Hotline support of original source ** -- ** code IP shall only address issues and questions related ** -- ** to the standard Netlist version of the core (and thus ** -- ** indirectly, the original core source). ** -- ** ** -- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** This copyright and support notice must be retained as part ** -- ** of this text at all times. ** -- ** ** -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: pf_occ_counter.vhd -- -- Description: Implements packet fifo occupancy counter. This special -- counter provides these functions: -- - up/down count control -- - pre-increment/pre-decrement of input load value -- - count by 2 -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- pf_occ_counter.vhd -- ------------------------------------------------------------------------------- -- Author: B.L. Tise -- Revision: $Revision: 1.1.4.1 $ -- Date: $Date: 2010/09/14 22:35:47 $ -- -- History: -- D. Thorpe 2001-09-07 First Version -- - adapted from B Tise MicroBlaze counters -- -- DET 2001-09-11 -- - Added the Rst signal connect to the pf_counter_bit module -- -- DET 2002-02-24 -- - Changed the use of MUXCY_L to MUXCY. -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Changed proc_common library version to v4_0 -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; library unisim; use unisim.vcomponents.all; library proc_common_v4_0; use proc_common_v4_0.pf_counter_bit; ----------------------------------------------------------------------------- -- Entity section ----------------------------------------------------------------------------- entity pf_occ_counter is generic ( C_COUNT_WIDTH : integer := 9 ); port ( Clk : in std_logic; Rst : in std_logic; Carry_Out : out std_logic; Load_In : in std_logic_vector(0 to C_COUNT_WIDTH-1); Count_Enable : in std_logic; Count_Load : in std_logic; Count_Down : in std_logic; Cnt_by_2 : In std_logic; Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1) ); end entity pf_occ_counter; ----------------------------------------------------------------------------- -- Architecture section ----------------------------------------------------------------------------- architecture implementation of pf_occ_counter is component MUXCY is port ( DI : in std_logic; CI : in std_logic; S : in std_logic; O : out std_logic); end component MUXCY; constant CY_START : integer := 1; signal alu_cy : std_logic_vector(0 to C_COUNT_WIDTH-1); signal iCount_Out : std_logic_vector(0 to C_COUNT_WIDTH-2); signal i_mux_Count_Out : std_logic_vector(0 to C_COUNT_WIDTH-2); signal count_clock_en : std_logic; signal carry_out_lsb : std_logic; signal carry_in_lsb : std_logic; signal count_out_lsb : std_logic; Signal mux_cnt_in_lsb : std_logic; Signal carry_out_select_di: std_logic; Signal carry_start : std_logic; Signal carry_start_select : std_logic; Signal by_2_carry_start : std_logic; begin -- VHDL_RTL ----------------------------------------------------------------------------- -- Generate the Counter bits ----------------------------------------------------------------------------- count_clock_en <= Count_Enable or Count_Load; MUX_THE_LSB_INPUT : process (count_out_lsb, Load_In, Count_Load) Begin If (Count_Load = '0') Then mux_cnt_in_lsb <= count_out_lsb; else mux_cnt_in_lsb <= Load_In(C_COUNT_WIDTH-1); End if; End process MUX_THE_LSB_INPUT; carry_start <= Count_Down xor Count_Enable; by_2_carry_start <= Cnt_by_2 and Count_Down; carry_start_select <= not(Cnt_by_2); I_MUXCY_LSB_IN : MUXCY port map ( DI => by_2_carry_start, CI => carry_start, S => carry_start_select, O => carry_in_lsb); I_COUNTER_BIT_LSB : entity proc_common_v4_0.pf_counter_bit port map ( Clk => Clk, Rst => Rst, Count_In => mux_cnt_in_lsb, Load_In => '0', Count_Load => '0', Count_Down => Count_Down, Carry_In => carry_in_lsb, Clock_Enable => count_clock_en, Result => count_out_lsb, Carry_Out => carry_out_lsb); carry_out_select_di <= Count_Down xor Cnt_by_2; I_MUXCY_LSB_OUT : MUXCY port map ( DI => carry_out_select_di, CI => carry_out_lsb, S => carry_start_select, O => alu_cy(C_COUNT_WIDTH-1)); I_ADDSUB_GEN : for i in 0 to C_COUNT_WIDTH-2 generate begin MUX_THE_INPUT : process (iCount_Out, Load_In, Count_Load) Begin If (Count_Load = '0') Then i_mux_Count_Out(i) <= iCount_Out(i); else i_mux_Count_Out(i) <= Load_In(i); End if; End process MUX_THE_INPUT; Counter_Bit_I : entity proc_common_v4_0.pf_counter_bit port map ( Clk => Clk, Rst => Rst, Count_In => i_mux_Count_Out(i), Load_In => '0', Count_Load => '0', Count_Down => Count_Down, Carry_In => alu_cy(i+1), Clock_Enable => count_clock_en, Result => iCount_Out(i), Carry_Out => alu_cy(i)); end generate I_ADDSUB_GEN; Count_Out <= iCount_Out & count_out_lsb; Carry_Out <= '0'; end architecture implementation;

mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_xbar_1/fifo_generator_v11_0/ramfifo/rd_handshaking_flags.vhd

19

13954

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1dz0YkI8nLiWEV896erUvAgCmSgD/KlgSypbqJULmNZPkMVnsc7bPncI `protect end_protected

mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/fifo_generator_v11_0/ramfifo/rd_handshaking_flags.vhd

19

13954

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block YeJs3h9nPnCnr3aRxIBZUXmhDS7WeTgKjgxxU15evXAwgLO5UoYuCJb2fGld8H5MyDQGWc8UFp3Q QS1bcwQeLw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block QMDnsLueMbfhPqb347LcBnHgrgkl6fbZ0QORe+igLd+Fn4pMYglXhNwzAsr45PWnZnHEuCtMe3Am 9p5sJ/ms8icpsPjNhMihj0/+LhkVUeJEYGJR6AGOi4DauCIoKWFsirWy53ZScEPa2MEe+a32HUq7 sCpglfzmrbsWEab4EEg= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block F3FpAl1oCeVkGEm2PKCJ71S6Z3CGasBF9SuzLFWQnXwmvUuKd7HyekhOce1QfyX+pLQcgfmP3XmZ qpZIDWOrbZbtPCk3pZcRYdM0rjk3gWPTq89GN09GyodyzYH5nERal74RXFzqDSlXYzgzDvsSzAku WQ8fc8R6wi9d8ZzaPtv7Mn3RMOg32FvlzTpy40zwgHFS17RZjspNh23gqb62COtY3bIw5wgzOnnc pwYSu+4rxmNM105eSJdh2TJiSEN9+pTEYMITQ2PUZ0OLL5Qstj3GHFD8/78u9ynXfzh4PnzFHX+c DtImYoh20HOPJeCFpBeWPHfekXHEPhbC52n0dQ== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Lq9ua7Pc8cPhzNKkRvioUx2DGTzaswIzLnIP4rJJ3cLZM5wsk5kiUTKl9rdBpb7G3yE/zCnmkGDT ZEvIhQ4CGdpOb9ZjoYg0BIc1GhYnGIexWpvkFarqP15NwctZCibdBpj579M1D8fvQ9Xw1j6ILLQ5 gUYJd4OzxaJCHTNx0vw= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block qzr81pSyvLThhRepJmzjPLJdFa8x8hA7KFKfUSPL+CaCFf8sC6XyXYts+1DRzPvdthUp8ISKrFAv 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1dz0YkI8nLiWEV896erUvAgCmSgD/KlgSypbqJULmNZPkMVnsc7bPncI `protect end_protected

mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/fifo_generator_v11_0/fifo_generator_v11_0_synth.vhd

19

237901

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block bvOwtDo+u1XQuHmmirIW0G1Eep8h4q1lu6sagQVNOpqoo1dUL25zlZCKWpryXBrbavlsSVZj+/Kj u5U6Rqq3pA== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block R8VeuF45EN20zhkGmJksRGl35KTSV0YbXBmOJfN53AFOKNxf64co0R3kMl1KH48vuem/BXWPzNwW 17k9On+EP4ryAUZ6V1YvtlO9Er2xv4nZefuEO+pELxS67R6s3b0HhdPIKa2fxDF3e7AwjfjDxMiG HOQbqK01rVOmqe+2yps= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block qqYTedtVydnDu0uy4wgVS9xnI5W4e3CBu2tom9I4ji9x6Du0u8YzLw4sHBXlBjTr0CIBWi+453uv 6i+HBaHUw6WLmgP+uD0PvRoMp9iMm4rcTjCZCtUo+5bxaKDQQyKy3VozWJN9cYsOEXUyn41sbHk0 MfnFQ231FTzHKrD8+sW8iXzJhrvAxVZSOCQNc8FKSuvFHDKgrQOZi/Dde7fskgmy7Y+pQzZQUv6h 7xsxzMyVpdCwJjhjdow/xj17Fc+yTtNKSxkHMIxVK6RXkbOidb7jBkIw+8aEzlqsG5f5vpboGqLH 6uQ8IqqBeKv3BDowwIwUDotWgCgTdyFmv35LwA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block xgoCG0tChkhv+ljdCxpV0I73D5nOgliZqF/G39R6pkQNEQixpt7jSEz4sP4s78dR6d8BiB9A3KNg s8gNghB9SqKmhRG0Jvm/hSIBQCWAqWOwg26IvTnT3j3MalMVsj1r5WE9uyiqdJ+QCTo/Y58NBx8l pM5ABblrTJM59LnIcqI= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block VTcA7V7opij8+vJ+tjjgJGiOJ+o6V1u444VHa/k01STvZB7T6/Ztq4KXHSVmD+driESiC+2EQRes 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mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/proc_common_v4_0/hdl/src/vhdl/cntr_incr_decr_addn_f.vhd

15

11429

------------------------------------------------------------------------------- -- $Id: cntr_incr_decr_addn_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $ ------------------------------------------------------------------------------- -- cntr_incr_decr_addn_f - entity / architecture pair ------------------------------------------------------------------------------- -- -- ************************************************************************* -- ** ** -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This text/file contains proprietary, confidential ** -- ** information of Xilinx, Inc., is distributed under ** -- ** license from Xilinx, Inc., and may be used, copied ** -- ** and/or disclosed only pursuant to the terms of a valid ** -- ** license agreement with Xilinx, Inc. Xilinx hereby ** -- ** grants you a license to use this text/file solely for ** -- ** design, simulation, implementation and creation of ** -- ** design files limited to Xilinx devices or technologies. ** -- ** Use with non-Xilinx devices or technologies is expressly ** -- ** prohibited and immediately terminates your license unless ** -- ** covered by a separate agreement. ** -- ** ** -- ** Xilinx is providing this design, code, or information ** -- ** "as-is" solely for use in developing programs and ** -- ** solutions for Xilinx devices, with no obligation on the ** -- ** part of Xilinx to provide support. By providing this design, ** -- ** code, or information as one possible implementation of ** -- ** this feature, application or standard, Xilinx is making no ** -- ** representation that this implementation is free from any ** -- ** claims of infringement. You are responsible for obtaining ** -- ** any rights you may require for your implementation. ** -- ** Xilinx expressly disclaims any warranty whatsoever with ** -- ** respect to the adequacy of the implementation, including ** -- ** but not limited to any warranties or representations that this ** -- ** implementation is free from claims of infringement, implied ** -- ** warranties of merchantability or fitness for a particular ** -- ** purpose. ** -- ** ** -- ** Xilinx products are not intended for use in life support ** -- ** appliances, devices, or systems. Use in such applications is ** -- ** expressly prohibited. ** -- ** ** -- ** Any modifications that are made to the Source Code are ** -- ** done at the users sole risk and will be unsupported. ** -- ** The Xilinx Support Hotline does not have access to source ** -- ** code and therefore cannot answer specific questions related ** -- ** to source HDL. The Xilinx Hotline support of original source ** -- ** code IP shall only address issues and questions related ** -- ** to the standard Netlist version of the core (and thus ** -- ** indirectly, the original core source). ** -- ** ** -- ** Copyright (c) 2005 - 2010 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** This copyright and support notice must be retained as part ** -- ** of this text at all times. ** -- ** ** -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: cntr_incr_decr_addn_f.vhd -- -- Description: This counter can increment, decrement or skip ahead -- by an arbitrary amount. -- -- If Reset is active, the value Cnt synchronously resets -- to all ones. (This reset value, different than the -- customary reset value of zero, caters to the original -- application of cntr_incr_decr_addn_f as the address -- counter for srl_fifo_rbu_f.) -- -- Otherwise, on each Clk, one is added to Cnt if Incr is -- asserted and one is subtracted if Decr is asserted. (If -- both are asserted, then there is no change to Cnt.) -- -- If Decr is not asserted, then the input value, -- Nm_to_add, is added. (Simultaneous assertion of Incr -- would add one more.) If Decr is asserted, then -- N_to_add, is ignored, i.e., it is possible to decrement -- by one or add N, but not both, and Decr overrides. -- -- The value that Cnt will take on at the next clock -- is available as Cnt_p1. -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- cntr_incr_decr_addn_f.vhd -- ------------------------------------------------------------------------------- -- -- History: -- FLO 12/30/05 First Version. -- -- ~~~~~~ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- predecessor value by # clks: "*_p#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; -- entity cntr_incr_decr_addn_f is generic ( C_SIZE : natural; C_FAMILY : string := "nofamily" ); port ( Clk : in std_logic; Reset : in std_logic; -- Note: the counter resets to all ones! Incr : in std_logic; Decr : in std_logic; N_to_add : in std_logic_vector(C_SIZE-1 downto 0); Cnt : out std_logic_vector(C_SIZE-1 downto 0); Cnt_p1 : out std_logic_vector(C_SIZE-1 downto 0) ); end entity cntr_incr_decr_addn_f; ---( library proc_common_v4_0; library ieee; use ieee.numeric_std.UNSIGNED; use ieee.numeric_std."+"; library unisim; use unisim.all; -- Make unisim entities available for default binding. -- architecture imp of cntr_incr_decr_addn_f is use proc_common_v4_0.family_support; use family_support.all; -- primitives_type, primitive_array_type, supported constant COUNTER_PRIMS_AVAIL : boolean := supported(C_FAMILY, (u_MUXCY_L, u_XORCY, u_FDS)); signal cnt_i : std_logic_vector(Cnt'range); signal cnt_i_p1 : std_logic_vector(Cnt'range); ---------------------------------------------------------------------------- -- Unisim components declared locally for maximum avoidance of default -- binding and vcomponents version issues. ---------------------------------------------------------------------------- component MUXCY_L port ( LO : out std_ulogic; CI : in std_ulogic; DI : in std_ulogic; S : in std_ulogic ); end component; component XORCY port ( O : out std_ulogic; CI : in std_ulogic; LI : in std_ulogic ); end component; component FDS generic ( INIT : bit := '1' ); port ( Q : out std_ulogic; C : in std_ulogic; D : in std_ulogic; S : in std_ulogic ); end component; begin -- architecture imp ---( STRUCTURAL_A_GEN : if COUNTER_PRIMS_AVAIL = true generate signal hsum_A : std_logic_vector(Cnt'range); signal cry : std_logic_vector(Cnt'length downto 0); begin ---( cry(0) <= Incr; Addr_Counters : for I in cnt_i'range generate hsum_A(I) <= ((Decr or N_to_add(i)) xor cnt_i(I)); MUXCY_L_I : component MUXCY_L port map ( DI => cnt_i(I), CI => cry(I), S => hsum_A(I), LO => cry(I+1)); XORCY_I : component XORCY port map ( LI => hsum_A(I), CI => cry(I), O => cnt_i_p1(I)); FDS_I : component FDS port map ( Q => cnt_i(I), C => Clk, D => cnt_i_p1(I), S => Reset); end generate Addr_Counters; ---) end generate STRUCTURAL_A_GEN; ---) ---( INFERRED_GEN : if COUNTER_PRIMS_AVAIL = false generate -- CNT_I_P1_PROC : process( cnt_i, N_to_add, Decr, Incr ) is -- function qual_n_to_add(N_to_add : std_logic_vector; Decr : std_logic ) return UNSIGNED is variable r: UNSIGNED(N_to_add'range); begin for i in r'range loop r(i) := N_to_add(i) or Decr; end loop; return r; end; -- function to_singleton_unsigned(s : std_logic) return unsigned is variable r : unsigned(0 to 0) := (others => s); begin return r; end; -- begin cnt_i_p1 <= std_logic_vector( UNSIGNED(cnt_i) + qual_n_to_add(N_to_add, Decr) + to_singleton_unsigned(Incr) ); end process; -- CNT_I_PROC : process(Clk) is begin if Clk'event and Clk = '1' then if Reset = '1' then cnt_i <= (others => '1'); else cnt_i <= cnt_i_p1; end if; end if; end process; -- end generate INFERRED_GEN; ---) Cnt <= cnt_i; Cnt_p1 <= cnt_i_p1; end architecture imp; ---)

mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_auto_pc_3/fifo_generator_v11_0/fifo_generator_v11_0_pkg.vhd

19

129958

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mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_1_1/proc_common_v4_0/hdl/src/vhdl/soft_reset.vhd

15

13928

------------------------------------------------------------------------------- -- $Id: soft_reset.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $ ------------------------------------------------------------------------------- --soft_reset.vhd v1.01a ------------------------------------------------------------------------------- -- -- ************************************************************************* -- ** ** -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This text/file contains proprietary, confidential ** -- ** information of Xilinx, Inc., is distributed under ** -- ** license from Xilinx, Inc., and may be used, copied ** -- ** and/or disclosed only pursuant to the terms of a valid ** -- ** license agreement with Xilinx, Inc. Xilinx hereby ** -- ** grants you a license to use this text/file solely for ** -- ** design, simulation, implementation and creation of ** -- ** design files limited to Xilinx devices or technologies. ** -- ** Use with non-Xilinx devices or technologies is expressly ** -- ** prohibited and immediately terminates your license unless ** -- ** covered by a separate agreement. ** -- ** ** -- ** Xilinx is providing this design, code, or information ** -- ** "as-is" solely for use in developing programs and ** -- ** solutions for Xilinx devices, with no obligation on the ** -- ** part of Xilinx to provide support. By providing this design, ** -- ** code, or information as one possible implementation of ** -- ** this feature, application or standard, Xilinx is making no ** -- ** representation that this implementation is free from any ** -- ** claims of infringement. You are responsible for obtaining ** -- ** any rights you may require for your implementation. ** -- ** Xilinx expressly disclaims any warranty whatsoever with ** -- ** respect to the adequacy of the implementation, including ** -- ** but not limited to any warranties or representations that this ** -- ** implementation is free from claims of infringement, implied ** -- ** warranties of merchantability or fitness for a particular ** -- ** purpose. ** -- ** ** -- ** Xilinx products are not intended for use in life support ** -- ** appliances, devices, or systems. Use in such applications is ** -- ** expressly prohibited. ** -- ** ** -- ** Any modifications that are made to the Source Code are ** -- ** done at the users sole risk and will be unsupported. ** -- ** The Xilinx Support Hotline does not have access to source ** -- ** code and therefore cannot answer specific questions related ** -- ** to source HDL. The Xilinx Hotline support of original source ** -- ** code IP shall only address issues and questions related ** -- ** to the standard Netlist version of the core (and thus ** -- ** indirectly, the original core source). ** -- ** ** -- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** This copyright and support notice must be retained as part ** -- ** of this text at all times. ** -- ** ** -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: soft_reset.vhd -- Version: v1_00_a -- Description: This VHDL design file is the Soft Reset Service -- ------------------------------------------------------------------------------- -- Structure: -- -- soft_reset.vhd -- -- ------------------------------------------------------------------------------- -- Author: Gary Burch -- -- History: -- GAB Aug 2, 2006 v1.00a (initial release) -- -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- -- Library definitions library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; ------------------------------------------------------------------------------- entity soft_reset is generic ( C_SIPIF_DWIDTH : integer := 32; -- Width of the write data bus C_RESET_WIDTH : integer := 4 -- Width of triggered reset in Bus Clocks ); port ( -- Inputs From the IPIF Bus Bus2IP_Reset : in std_logic; Bus2IP_Clk : in std_logic; Bus2IP_WrCE : in std_logic; Bus2IP_Data : in std_logic_vector(0 to C_SIPIF_DWIDTH-1); Bus2IP_BE : in std_logic_vector(0 to (C_SIPIF_DWIDTH/8)-1); -- Final Device Reset Output Reset2IP_Reset : out std_logic; -- Status Reply Outputs to the Bus Reset2Bus_WrAck : out std_logic; Reset2Bus_Error : out std_logic; Reset2Bus_ToutSup : out std_logic ); end soft_reset ; ------------------------------------------------------------------------------- architecture implementation of soft_reset is ------------------------------------------------------------------------------- -- Function Declarations ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Type Declarations ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- -- Module Software Reset screen value for write data -- This requires a Hex 'A' to be written to ativate the S/W reset port constant RESET_MATCH : std_logic_vector(0 to 3) := "1010"; -- Required BE index to be active during Reset activation constant BE_MATCH : integer := 3; ------------------------------------------------------------------------------- -- Signal Declarations ------------------------------------------------------------------------------- signal sm_reset : std_logic; signal error_reply : std_logic; signal reset_wrack : std_logic; signal reset_error : std_logic; signal reset_trig : std_logic; signal wrack : std_logic; signal wrack_ff_chain : std_logic; signal flop_q_chain : std_logic_vector(0 to C_RESET_WIDTH); --signal bus2ip_wrce_d1 : std_logic; signal data_is_non_reset_match : std_logic; signal sw_rst_cond : std_logic; signal sw_rst_cond_d1 : std_logic; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- begin -- Misc assignments Reset2Bus_WrAck <= reset_wrack; Reset2Bus_Error <= reset_error; Reset2Bus_ToutSup <= sm_reset; -- Suppress a data phase timeout when -- a commanded reset is active. reset_wrack <= (reset_error or wrack);-- and Bus2IP_WrCE; reset_error <= data_is_non_reset_match and Bus2IP_WrCE; Reset2IP_Reset <= Bus2IP_Reset or sm_reset; --------------------------------------------------------------------------------- ---- Register WRCE for use in creating a strobe pulse --------------------------------------------------------------------------------- --REG_WRCE : process(Bus2IP_Clk) -- begin -- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then -- if(Bus2IP_Reset = '1')then -- bus2ip_wrce_d1 <= '0'; -- else -- bus2ip_wrce_d1 <= Bus2IP_WrCE; -- end if; -- end if; -- end process REG_WRCE; -- ------------------------------------------------------------------------------- -- Start the S/W reset state machine as a result of an IPIF Bus write to -- the Reset port and the data on the DBus inputs matching the Reset -- match value. If the value on the data bus input does not match the -- designated reset key, an error acknowledge is generated. ------------------------------------------------------------------------------- --DETECT_SW_RESET : process (Bus2IP_Clk) -- begin -- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then -- if (Bus2IP_Reset = '1') then -- error_reply <= '0'; -- reset_trig <= '0'; -- elsif (Bus2IP_WrCE = '1' -- and Bus2IP_BE(BE_MATCH) = '1' -- and Bus2IP_Data(28 to 31) = RESET_MATCH) then -- error_reply <= '0'; -- reset_trig <= Bus2IP_WrCE and not bus2ip_wrce_d1; -- elsif (Bus2IP_WrCE = '1') then -- error_reply <= '1'; -- reset_trig <= '0'; -- else -- error_reply <= '0'; -- reset_trig <= '0'; -- end if; -- end if; -- end process DETECT_SW_RESET; data_is_non_reset_match <= '0' when (Bus2IP_Data(C_SIPIF_DWIDTH-4 to C_SIPIF_DWIDTH-1) = RESET_MATCH and Bus2IP_BE(BE_MATCH) = '1') else '1'; -------------------------------------------------------------------------------- -- SW Reset -------------------------------------------------------------------------------- ---------------------------------------------------------------------------- sw_rst_cond <= Bus2IP_WrCE and not data_is_non_reset_match; -- RST_PULSE_PROC : process (Bus2IP_Clk) Begin if (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then if (Bus2IP_Reset = '1') Then sw_rst_cond_d1 <= '0'; reset_trig <= '0'; else sw_rst_cond_d1 <= sw_rst_cond; reset_trig <= sw_rst_cond and not sw_rst_cond_d1; end if; end if; End process; ------------------------------------------------------------------------------- -- RESET_FLOPS: -- This FORGEN implements the register chain used to create -- the parameterizable reset pulse width. ------------------------------------------------------------------------------- RESET_FLOPS : for index in 0 to C_RESET_WIDTH-1 generate flop_q_chain(0) <= '0'; RST_FLOPS : FDRSE port map( Q => flop_q_chain(index+1), -- : out std_logic; C => Bus2IP_Clk, -- : in std_logic; CE => '1', -- : in std_logic; D => flop_q_chain(index), -- : in std_logic; R => Bus2IP_Reset, -- : in std_logic; S => reset_trig -- : in std_logic ); end generate RESET_FLOPS; -- Use the last flop output for the commanded reset pulse sm_reset <= flop_q_chain(C_RESET_WIDTH); wrack_ff_chain <= flop_q_chain(C_RESET_WIDTH) and not(flop_q_chain(C_RESET_WIDTH-1)); -- Register the Write Acknowledge for the Reset write -- This is generated at the end of the reset pulse. This -- keeps the Slave busy until the commanded reset completes. FF_WRACK : FDRSE port map( Q => wrack, -- : out std_logic; C => Bus2IP_Clk, -- : in std_logic; CE => '1', -- : in std_logic; D => wrack_ff_chain, -- : in std_logic; R => Bus2IP_Reset, -- : in std_logic; S => '0' -- : in std_logic ); end implementation;

mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/proc_common_v4_0/hdl/src/vhdl/proc_common_pkg.vhd

15

18735

------------------------------------------------------------------------------- -- $Id: proc_common_pkg.vhd,v 1.1.4.46 2010/10/28 01:14:32 ostlerf Exp $ ------------------------------------------------------------------------------- -- Processor Common Library Package ------------------------------------------------------------------------------- -- -- ************************************************************************* -- ** ** -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This text/file contains proprietary, confidential ** -- ** information of Xilinx, Inc., is distributed under ** -- ** license from Xilinx, Inc., and may be used, copied ** -- ** and/or disclosed only pursuant to the terms of a valid ** -- ** license agreement with Xilinx, Inc. Xilinx hereby ** -- ** grants you a license to use this text/file solely for ** -- ** design, simulation, implementation and creation of ** -- ** design files limited to Xilinx devices or technologies. ** -- ** Use with non-Xilinx devices or technologies is expressly ** -- ** prohibited and immediately terminates your license unless ** -- ** covered by a separate agreement. ** -- ** ** -- ** Xilinx is providing this design, code, or information ** -- ** "as-is" solely for use in developing programs and ** -- ** solutions for Xilinx devices, with no obligation on the ** -- ** part of Xilinx to provide support. By providing this design, ** -- ** code, or information as one possible implementation of ** -- ** this feature, application or standard, Xilinx is making no ** -- ** representation that this implementation is free from any ** -- ** claims of infringement. You are responsible for obtaining ** -- ** any rights you may require for your implementation. ** -- ** Xilinx expressly disclaims any warranty whatsoever with ** -- ** respect to the adequacy of the implementation, including ** -- ** but not limited to any warranties or representations that this ** -- ** implementation is free from claims of infringement, implied ** -- ** warranties of merchantability or fitness for a particular ** -- ** purpose. ** -- ** ** -- ** Xilinx products are not intended for use in life support ** -- ** appliances, devices, or systems. Use in such applications is ** -- ** expressly prohibited. ** -- ** ** -- ** Any modifications that are made to the Source Code are ** -- ** done at the users sole risk and will be unsupported. ** -- ** The Xilinx Support Hotline does not have access to source ** -- ** code and therefore cannot answer specific questions related ** -- ** to source HDL. The Xilinx Hotline support of original source ** -- ** code IP shall only address issues and questions related ** -- ** to the standard Netlist version of the core (and thus ** -- ** indirectly, the original core source). ** -- ** ** -- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** This copyright and support notice must be retained as part ** -- ** of this text at all times. ** -- ** ** -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: proc_common_pkg.vhd -- Version: v1.21b -- Description: This file contains the constants and functions used in the -- processor common library components. -- ------------------------------------------------------------------------------- -- Structure: -- ------------------------------------------------------------------------------- -- Author: ALS -- History: -- ALS 09/12/01 -- Created from opb_arb_pkg.vhd -- -- ALS 09/21/01 -- ^^^^^^ -- Added pwr function. Replaced log2 function with one that works for XST. -- ~~~~~~ -- -- ALS 12/07/01 -- ^^^^^^ -- Added Addr_bits function. -- ~~~~~~ -- ALS 01/31/02 -- ^^^^^^ -- Added max2 function. -- ~~~~~~ -- FLO 02/22/02 -- ^^^^^^ -- Extended input argument range of log2 function to 2^30. Also, added -- a check that the argument does not exceed this value; a failure -- assertion violation is generated if it does not. -- ~~~~~~ -- FLO 08/31/06 -- ^^^^^^ -- Removed type TARGET_FAMILY_TYPE and functions Get_Reg_File_Area and -- Get_RLOC_Name. These objects are not used. Further, the functions -- produced misleading warnings (CR419886, CR419898). -- ~~~~~~ -- FLO 05/25/07 -- ^^^^^^ -- -Reimplemented function pad_power2 to correct error when the input -- argument is 1. (fixes CR 303469) -- -Added function clog2(x), which returns the integer ceiling of the -- base 2 logarithm of x. This function can be used in place of log2 -- when wishing to avoid the XST warning, "VHDL Assertion Statement -- with non constant condition is ignored". -- ~~~~~~ -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Incorporated new disclaimer header -- ^^^^^^ -- -- DET 5/8/2009 v4_0 for EDK L.SP2 -- ~~~~~~ -- - Per CR520627 -- - Added synthesis translate_off/on constructs to the log2 function -- around the assertion statement. This removes a repetative XST Warning -- in SRP files about a non-constant assertion check. -- ^^^^^^ -- FL0 20/27/2010 -- ^^^^^^ -- Removed 42 TBD comment, again. (CR 568493) -- ~~~~~~ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; -- need conversion function to convert reals/integers to std logic vectors use ieee.std_logic_arith.conv_std_logic_vector; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; package proc_common_pkg is ------------------------------------------------------------------------------- -- Type Declarations ------------------------------------------------------------------------------- type CHAR_TO_INT_TYPE is array (character) of integer; -- type INTEGER_ARRAY_TYPE is array (natural range <>) of integer; -- Type SLV64_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 63); ------------------------------------------------------------------------------- -- Function and Procedure Declarations ------------------------------------------------------------------------------- function max2 (num1, num2 : integer) return integer; function min2 (num1, num2 : integer) return integer; function Addr_Bits(x,y : std_logic_vector) return integer; function clog2(x : positive) return natural; function pad_power2 ( in_num : integer ) return integer; function pad_4 ( in_num : integer ) return integer; function log2(x : natural) return integer; function pwr(x: integer; y: integer) return integer; function String_To_Int(S : string) return integer; function itoa (int : integer) return string; ------------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- -- the RESET_ACTIVE constant should denote the logic level of an active reset constant RESET_ACTIVE : std_logic := '1'; -- table containing strings representing hex characters for conversion to -- integers constant STRHEX_TO_INT_TABLE : CHAR_TO_INT_TYPE := ('0' => 0, '1' => 1, '2' => 2, '3' => 3, '4' => 4, '5' => 5, '6' => 6, '7' => 7, '8' => 8, '9' => 9, 'A'|'a' => 10, 'B'|'b' => 11, 'C'|'c' => 12, 'D'|'d' => 13, 'E'|'e' => 14, 'F'|'f' => 15, others => -1); end proc_common_pkg; package body proc_common_pkg is ------------------------------------------------------------------------------- -- Function Definitions ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Function max2 -- -- This function returns the greater of two numbers. ------------------------------------------------------------------------------- function max2 (num1, num2 : integer) return integer is begin if num1 >= num2 then return num1; else return num2; end if; end function max2; ------------------------------------------------------------------------------- -- Function min2 -- -- This function returns the lesser of two numbers. ------------------------------------------------------------------------------- function min2 (num1, num2 : integer) return integer is begin if num1 <= num2 then return num1; else return num2; end if; end function min2; ------------------------------------------------------------------------------- -- Function Addr_bits -- -- function to convert an address range (base address and an upper address) -- into the number of upper address bits needed for decoding a device -- select signal. will handle slices and big or little endian ------------------------------------------------------------------------------- function Addr_Bits(x,y : std_logic_vector) return integer is variable addr_xor : std_logic_vector(x'range); variable count : integer := 0; begin assert x'length = y'length and (x'ascending xnor y'ascending) report "Addr_Bits: arguments are not the same type" severity ERROR; addr_xor := x xor y; for i in x'range loop if addr_xor(i) = '1' then return count; end if; count := count + 1; end loop; return x'length; end Addr_Bits; -------------------------------------------------------------------------------- -- Function clog2 - returns the integer ceiling of the base 2 logarithm of x, -- i.e., the least integer greater than or equal to log2(x). -------------------------------------------------------------------------------- function clog2(x : positive) return natural is variable r : natural := 0; variable rp : natural := 1; -- rp tracks the value 2**r begin while rp < x loop -- Termination condition T: x <= 2**r -- Loop invariant L: 2**(r-1) < x r := r + 1; if rp > integer'high - rp then exit; end if; -- If doubling rp overflows -- the integer range, the doubled value would exceed x, so safe to exit. rp := rp + rp; end loop; -- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r return r; -- end clog2; ------------------------------------------------------------------------------- -- Function pad_power2 -- -- This function returns the next power of 2 from the input number. If the -- input number is a power of 2, this function returns the input number. -- -- This function is used to round up the number of masters to the next power -- of 2 if the number of masters is not already a power of 2. -- -- Input argument 0, which is not a power of two, is accepted and returns 0. -- Input arguments less than 0 are not allowed. ------------------------------------------------------------------------------- -- function pad_power2 (in_num : integer ) return integer is begin if in_num = 0 then return 0; else return 2**(clog2(in_num)); end if; end pad_power2; ------------------------------------------------------------------------------- -- Function pad_4 -- -- This function returns the next multiple of 4 from the input number. If the -- input number is a multiple of 4, this function returns the input number. -- ------------------------------------------------------------------------------- -- function pad_4 (in_num : integer ) return integer is variable out_num : integer; begin out_num := (((in_num-1)/4) + 1)*4; return out_num; end pad_4; ------------------------------------------------------------------------------- -- Function log2 -- returns number of bits needed to encode x choices -- x = 0 returns 0 -- x = 1 returns 0 -- x = 2 returns 1 -- x = 4 returns 2, etc. ------------------------------------------------------------------------------- -- function log2(x : natural) return integer is variable i : integer := 0; variable val: integer := 1; begin if x = 0 then return 0; else for j in 0 to 29 loop -- for loop for XST if val >= x then null; else i := i+1; val := val*2; end if; end loop; -- Fix per CR520627 XST was ignoring this anyway and printing a -- Warning in SRP file. This will get rid of the warning and not -- impact simulation. -- synthesis translate_off assert val >= x report "Function log2 received argument larger" & " than its capability of 2^30. " severity failure; -- synthesis translate_on return i; end if; end function log2; ------------------------------------------------------------------------------- -- Function pwr -- x**y -- negative numbers not allowed for y ------------------------------------------------------------------------------- function pwr(x: integer; y: integer) return integer is variable z : integer := 1; begin if y = 0 then return 1; else for i in 1 to y loop z := z * x; end loop; return z; end if; end function pwr; ------------------------------------------------------------------------------- -- Function itoa -- -- The itoa function converts an integer to a text string. -- This function is required since `image doesn't work in Synplicity -- Valid input range is -9999 to 9999 ------------------------------------------------------------------------------- -- function itoa (int : integer) return string is type table is array (0 to 9) of string (1 to 1); constant LUT : table := ("0", "1", "2", "3", "4", "5", "6", "7", "8", "9"); variable str1 : string(1 to 1); variable str2 : string(1 to 2); variable str3 : string(1 to 3); variable str4 : string(1 to 4); variable str5 : string(1 to 5); variable abs_int : natural; variable thousands_place : natural; variable hundreds_place : natural; variable tens_place : natural; variable ones_place : natural; variable sign : integer; begin abs_int := abs(int); if abs_int > int then sign := -1; else sign := 1; end if; thousands_place := abs_int/1000; hundreds_place := (abs_int-thousands_place*1000)/100; tens_place := (abs_int-thousands_place*1000-hundreds_place*100)/10; ones_place := (abs_int-thousands_place*1000-hundreds_place*100-tens_place*10); if sign>0 then if thousands_place>0 then str4 := LUT(thousands_place) & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place); return str4; elsif hundreds_place>0 then str3 := LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place); return str3; elsif tens_place>0 then str2 := LUT(tens_place) & LUT(ones_place); return str2; else str1 := LUT(ones_place); return str1; end if; else if thousands_place>0 then str5 := "-" & LUT(thousands_place) & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place); return str5; elsif hundreds_place>0 then str4 := "-" & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place); return str4; elsif tens_place>0 then str3 := "-" & LUT(tens_place) & LUT(ones_place); return str3; else str2 := "-" & LUT(ones_place); return str2; end if; end if; end itoa; ----------------------------------------------------------------------------- -- Function String_To_Int -- -- Converts a string of hex character to an integer -- accept negative numbers ----------------------------------------------------------------------------- function String_To_Int(S : String) return Integer is variable Result : integer := 0; variable Temp : integer := S'Left; variable Negative : integer := 1; begin for I in S'Left to S'Right loop if (S(I) = '-') then Temp := 0; Negative := -1; else Temp := STRHEX_TO_INT_TABLE(S(I)); if (Temp = -1) then assert false report "Wrong value in String_To_Int conversion " & S(I) severity error; end if; end if; Result := Result * 16 + Temp; end loop; return (Negative * Result); end String_To_Int; end package body proc_common_pkg;

mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_0_0/blk_mem_gen_v8_1/blk_mem_output_block.vhd

27

17222

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mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_1_1/proc_common_v4_0/hdl/src/vhdl/ld_arith_reg.vhd

15

15091

------------------------------------------------------------------------------- -- $Id: ld_arith_reg.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $ ------------------------------------------------------------------------------- -- Loadable arithmetic register. ------------------------------------------------------------------------------- -- -- ************************************************************************* -- ** ** -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This text/file contains proprietary, confidential ** -- ** information of Xilinx, Inc., is distributed under ** -- ** license from Xilinx, Inc., and may be used, copied ** -- ** and/or disclosed only pursuant to the terms of a valid ** -- ** license agreement with Xilinx, Inc. Xilinx hereby ** -- ** grants you a license to use this text/file solely for ** -- ** design, simulation, implementation and creation of ** -- ** design files limited to Xilinx devices or technologies. ** -- ** Use with non-Xilinx devices or technologies is expressly ** -- ** prohibited and immediately terminates your license unless ** -- ** covered by a separate agreement. ** -- ** ** -- ** Xilinx is providing this design, code, or information ** -- ** "as-is" solely for use in developing programs and ** -- ** solutions for Xilinx devices, with no obligation on the ** -- ** part of Xilinx to provide support. By providing this design, ** -- ** code, or information as one possible implementation of ** -- ** this feature, application or standard, Xilinx is making no ** -- ** representation that this implementation is free from any ** -- ** claims of infringement. You are responsible for obtaining ** -- ** any rights you may require for your implementation. ** -- ** Xilinx expressly disclaims any warranty whatsoever with ** -- ** respect to the adequacy of the implementation, including ** -- ** but not limited to any warranties or representations that this ** -- ** implementation is free from claims of infringement, implied ** -- ** warranties of merchantability or fitness for a particular ** -- ** purpose. ** -- ** ** -- ** Xilinx products are not intended for use in life support ** -- ** appliances, devices, or systems. Use in such applications is ** -- ** expressly prohibited. ** -- ** ** -- ** Any modifications that are made to the Source Code are ** -- ** done at the users sole risk and will be unsupported. ** -- ** The Xilinx Support Hotline does not have access to source ** -- ** code and therefore cannot answer specific questions related ** -- ** to source HDL. The Xilinx Hotline support of original source ** -- ** code IP shall only address issues and questions related ** -- ** to the standard Netlist version of the core (and thus ** -- ** indirectly, the original core source). ** -- ** ** -- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** This copyright and support notice must be retained as part ** -- ** of this text at all times. ** -- ** ** -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: ld_arith_reg.vhd -- Version: -------------------------------------------------------------------------------- -- Description: A register that can be loaded and added to or subtracted from -- (but not both). The width of the register is specified -- with a generic. The load value and the arith -- value, i.e. the value to be added (subtracted), may be of -- lesser width than the register and may be -- offset from the LSB position. (Uncovered positions -- load or add (subtract) zero.) The register can be -- reset, via the RST signal, to a freely selectable value. -- The register is defined in terms of big-endian bit ordering. -- ------------------------------------------------------------------------------- -- Structure: -- -- ld_arith_reg.vhd ------------------------------------------------------------------------------- -- Author: FO -- -- History: -- -- FO 08/01 -- First version -- -- FO 11/14/01 -- Cosmetic improvements -- -- FO 02/22/02 -- Switched from MUXCY_L primitive to MUXCY. -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; entity ld_arith_reg is generic ( ------------------------------------------------------------------------ -- True if the arithmetic operation is add, false if subtract. C_ADD_SUB_NOT : boolean := false; ------------------------------------------------------------------------ -- Width of the register. C_REG_WIDTH : natural := 8; ------------------------------------------------------------------------ -- Reset value. (No default, must be specified in the instantiation.) C_RESET_VALUE : std_logic_vector; ------------------------------------------------------------------------ -- Width of the load data. C_LD_WIDTH : natural := 8; ------------------------------------------------------------------------ -- Offset from the LSB (toward more significant) of the load data. C_LD_OFFSET : natural := 0; ------------------------------------------------------------------------ -- Width of the arithmetic data. C_AD_WIDTH : natural := 8; ------------------------------------------------------------------------ -- Offset from the LSB of the arithmetic data. C_AD_OFFSET : natural := 0 ------------------------------------------------------------------------ -- Dependencies: (1) C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH -- (2) C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH ------------------------------------------------------------------------ ); port ( CK : in std_logic; RST : in std_logic; -- Reset to C_RESET_VALUE. (Overrides OP,LOAD) Q : out std_logic_vector(0 to C_REG_WIDTH-1); LD : in std_logic_vector(0 to C_LD_WIDTH-1); -- Load data. AD : in std_logic_vector(0 to C_AD_WIDTH-1); -- Arith data. LOAD : in std_logic; -- Enable for the load op, Q <= LD. OP : in std_logic -- Enable for the arith op, Q <= Q + AD. -- (Q <= Q - AD if C_ADD_SUB_NOT = false.) -- (Overrrides LOAD.) ); end ld_arith_reg; library unisim; use unisim.all; library ieee; use ieee.numeric_std.all; architecture imp of ld_arith_reg is component MULT_AND port( LO : out std_ulogic; I1 : in std_ulogic; I0 : in std_ulogic); end component; component MUXCY is port ( DI : in std_logic; CI : in std_logic; S : in std_logic; O : out std_logic); end component MUXCY; component XORCY is port ( LI : in std_logic; CI : in std_logic; O : out std_logic); end component XORCY; component FDRE is port ( Q : out std_logic; C : in std_logic; CE : in std_logic; D : in std_logic; R : in std_logic ); end component FDRE; component FDSE is port ( Q : out std_logic; C : in std_logic; CE : in std_logic; D : in std_logic; S : in std_logic ); end component FDSE; signal q_i, q_i_ns, xorcy_out, gen_cry_kill_n : std_logic_vector(0 to C_REG_WIDTH-1); signal cry : std_logic_vector(0 to C_REG_WIDTH); begin -- synthesis translate_off assert C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH report "ld_arith_reg, constraint does not hold: " & "C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH" severity error; assert C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH report "ld_arith_reg, constraint does not hold: " & "C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH" severity error; -- synthesis translate_on Q <= q_i; cry(C_REG_WIDTH) <= '0' when C_ADD_SUB_NOT else OP; PERBIT_GEN: for j in C_REG_WIDTH-1 downto 0 generate signal load_bit, arith_bit, CE : std_logic; begin ------------------------------------------------------------------------ -- Assign to load_bit either zero or the bit from input port LD. ------------------------------------------------------------------------ D_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_LD_OFFSET or j < C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET generate load_bit <= '0'; end generate; D_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_LD_OFFSET and j >= C_REG_WIDTH - C_LD_OFFSET - C_LD_WIDTH generate load_bit <= LD(j - (C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET)); end generate; ------------------------------------------------------------------------ -- Assign to arith_bit either zero or the bit from input port AD. ------------------------------------------------------------------------ AD_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_AD_OFFSET or j < C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET generate arith_bit <= '0'; end generate; AD_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_AD_OFFSET and j >= C_REG_WIDTH - C_AD_OFFSET - C_AD_WIDTH generate arith_bit <= AD(j - (C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET)); end generate; ------------------------------------------------------------------------ -- LUT output generation. -- Adder case ------------------------------------------------------------------------ Q_I_GEN_ADD: if C_ADD_SUB_NOT generate q_i_ns(j) <= q_i(j) xor arith_bit when OP = '1' else load_bit; end generate; ------------------------------------------------------------------------ -- Subtractor case ------------------------------------------------------------------------ Q_I_GEN_SUB: if not C_ADD_SUB_NOT generate q_i_ns(j) <= q_i(j) xnor arith_bit when OP = '1' else load_bit; end generate; ------------------------------------------------------------------------ -- Kill carries (borrows) for loads but -- generate or kill carries (borrows) for add (sub). ------------------------------------------------------------------------ MULT_AND_i1: MULT_AND port map ( LO => gen_cry_kill_n(j), I1 => OP, I0 => Q_i(j) ); ------------------------------------------------------------------------ -- Propagate the carry (borrow) out. ------------------------------------------------------------------------ MUXCY_i1: MUXCY port map ( DI => gen_cry_kill_n(j), CI => cry(j+1), S => q_i_ns(j), O => cry(j) ); ------------------------------------------------------------------------ -- Apply the effect of carry (borrow) in. ------------------------------------------------------------------------ XORCY_i1: XORCY port map ( LI => q_i_ns(j), CI => cry(j+1), O => xorcy_out(j) ); CE <= LOAD or OP; ------------------------------------------------------------------------ -- Generate either a resettable or setable FF for bit j, depending -- on C_RESET_VALUE at bit j. ------------------------------------------------------------------------ FF_RST0_GEN: if C_RESET_VALUE(j) = '0' generate FDRE_i1: FDRE port map ( Q => q_i(j), C => CK, CE => CE, D => xorcy_out(j), R => RST ); end generate; FF_RST1_GEN: if C_RESET_VALUE(j) = '1' generate FDSE_i1: FDSE port map ( Q => q_i(j), C => CK, CE => CE, D => xorcy_out(j), S => RST ); end generate; end generate; end imp;

mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_f.vhd

15

12529

------------------------------------------------------------------------------- -- $Id: pselect_f.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $ ------------------------------------------------------------------------------- -- pselect_f.vhd - entity/architecture pair ------------------------------------------------------------------------------- -- -- ************************************************************************* -- ** ** -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This text/file contains proprietary, confidential ** -- ** information of Xilinx, Inc., is distributed under ** -- ** license from Xilinx, Inc., and may be used, copied ** -- ** and/or disclosed only pursuant to the terms of a valid ** -- ** license agreement with Xilinx, Inc. Xilinx hereby ** -- ** grants you a license to use this text/file solely for ** -- ** design, simulation, implementation and creation of ** -- ** design files limited to Xilinx devices or technologies. ** -- ** Use with non-Xilinx devices or technologies is expressly ** -- ** prohibited and immediately terminates your license unless ** -- ** covered by a separate agreement. ** -- ** ** -- ** Xilinx is providing this design, code, or information ** -- ** "as-is" solely for use in developing programs and ** -- ** solutions for Xilinx devices, with no obligation on the ** -- ** part of Xilinx to provide support. By providing this design, ** -- ** code, or information as one possible implementation of ** -- ** this feature, application or standard, Xilinx is making no ** -- ** representation that this implementation is free from any ** -- ** claims of infringement. You are responsible for obtaining ** -- ** any rights you may require for your implementation. ** -- ** Xilinx expressly disclaims any warranty whatsoever with ** -- ** respect to the adequacy of the implementation, including ** -- ** but not limited to any warranties or representations that this ** -- ** implementation is free from claims of infringement, implied ** -- ** warranties of merchantability or fitness for a particular ** -- ** purpose. ** -- ** ** -- ** Xilinx products are not intended for use in life support ** -- ** appliances, devices, or systems. Use in such applications is ** -- ** expressly prohibited. ** -- ** ** -- ** Any modifications that are made to the Source Code are ** -- ** done at the users sole risk and will be unsupported. ** -- ** The Xilinx Support Hotline does not have access to source ** -- ** code and therefore cannot answer specific questions related ** -- ** to source HDL. The Xilinx Hotline support of original source ** -- ** code IP shall only address issues and questions related ** -- ** to the standard Netlist version of the core (and thus ** -- ** indirectly, the original core source). ** -- ** ** -- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** This copyright and support notice must be retained as part ** -- ** of this text at all times. ** -- ** ** -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: pselect_f.vhd -- -- Description: -- (Note: At least as early as I.31, XST implements a carry- -- chain structure for most decoders when these are coded in -- inferrable VHLD. An example of such code can be seen -- below in the "INFERRED_GEN" Generate Statement. -- -- -> New code should not need to instantiate pselect-type -- components. -- -- -> Existing code can be ported to Virtex5 and later by -- replacing pselect instances by pselect_f instances. -- As long as the C_FAMILY parameter is not included -- in the Generic Map, an inferred implementation -- will result. -- -- -> If the designer wishes to force an explicit carry- -- chain implementation, pselect_f can be used with -- the C_FAMILY parameter set to the target -- Xilinx FPGA family. -- ) -- -- Parameterizeable peripheral select (address decode). -- AValid qualifier comes in on Carry In at bottom -- of carry chain. -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: pselect_f.vhd -- family_support.vhd -- ------------------------------------------------------------------------------- -- History: -- Vaibhav & FLO 05/26/06 First Version -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Changed proc_common library version to v4_0 -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; library unisim; use unisim.all; library proc_common_v4_0; use proc_common_v4_0.family_support.all; ----------------------------------------------------------------------------- -- Entity section ----------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Definition of Generics: -- C_AB -- number of address bits to decode -- C_AW -- width of address bus -- C_BAR -- base address of peripheral (peripheral select -- is asserted when the C_AB most significant -- address bits match the C_AB most significant -- C_BAR bits -- Definition of Ports: -- A -- address input -- AValid -- address qualifier -- CS -- peripheral select ------------------------------------------------------------------------------- entity pselect_f is generic ( C_AB : integer := 9; C_AW : integer := 32; C_BAR : std_logic_vector; C_FAMILY : string := "nofamily" ); port ( A : in std_logic_vector(0 to C_AW-1); AValid : in std_logic; CS : out std_logic ); end entity pselect_f; ----------------------------------------------------------------------------- -- Architecture section ----------------------------------------------------------------------------- architecture imp of pselect_f is component MUXCY is port ( O : out std_logic; CI : in std_logic; DI : in std_logic; S : in std_logic ); end component MUXCY; constant NLS : natural := native_lut_size(C_FAMILY); constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY) or NLS=0 -- LUT not supported. or C_AB <= NLS; -- Just one LUT -- needed. ----------------------------------------------------------------------------- -- C_BAR may not be indexed from 0 and may not be ascending; -- BAR recasts C_BAR to have these properties. ----------------------------------------------------------------------------- constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR; type bo2sl_type is array (boolean) of std_logic; constant bo2sl : bo2sl_type := (false => '0', true => '1'); function min(i, j: integer) return integer is begin if i<j then return i; else return j; end if; end; begin ------------------------------------------------------------------------------ -- Check that the generics are valid. ------------------------------------------------------------------------------ -- synthesis translate_off assert (C_AB <= C_BAR'length) and (C_AB <= C_AW) report "pselect_f generic error: " & "(C_AB <= C_BAR'length) and (C_AB <= C_AW)" & " does not hold." severity failure; -- synthesis translate_on ------------------------------------------------------------------------------ -- Build a behavioral decoder ------------------------------------------------------------------------------ INFERRED_GEN : if (USE_INFERRED = TRUE ) generate begin XST_WA:if C_AB > 0 generate CS <= AValid when A(0 to C_AB-1) = BAR (0 to C_AB-1) else '0' ; end generate XST_WA; PASS_ON_GEN:if C_AB = 0 generate CS <= AValid ; end generate PASS_ON_GEN; end generate INFERRED_GEN; ------------------------------------------------------------------------------ -- Build a structural decoder using the fast carry chain ------------------------------------------------------------------------------ GEN_STRUCTURAL_A : if (USE_INFERRED = FALSE ) generate constant NUM_LUTS : integer := (C_AB+(NLS-1))/NLS; signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround signal carry_chain : std_logic_vector(0 to NUM_LUTS); begin carry_chain(NUM_LUTS) <= AValid; -- Initialize start of carry chain. CS <= carry_chain(0); -- Assign end of carry chain to output. XST_WA: if NUM_LUTS > 0 generate -- workaround for XST begin GEN_DECODE: for i in 0 to NUM_LUTS-1 generate constant NI : natural := i; constant BTL : positive := min(NLS, C_AB-NI*NLS);-- num Bits This LUT begin lut_out(i) <= bo2sl(A(NI*NLS to NI*NLS+BTL-1) = -- LUT BAR(NI*NLS to NI*NLS+BTL-1)); MUXCY_I: component MUXCY -- MUXCY port map ( O => carry_chain(i), CI => carry_chain(i+1), DI => '0', S => lut_out(i) ); end generate GEN_DECODE; end generate XST_WA; end generate GEN_STRUCTURAL_A; end imp;

mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/fifo_generator_v11_0/ramfifo/rd_logic.vhd

19

48192

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mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/proc_common_v4_0/hdl/src/vhdl/down_counter.vhd

15

8398

------------------------------------------------------------------------------- -- $Id: down_counter.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $ ------------------------------------------------------------------------------ -- PLB Arbiter ------------------------------------------------------------------------------- -- -- ************************************************************************* -- ** ** -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This text/file contains proprietary, confidential ** -- ** information of Xilinx, Inc., is distributed under ** -- ** license from Xilinx, Inc., and may be used, copied ** -- ** and/or disclosed only pursuant to the terms of a valid ** -- ** license agreement with Xilinx, Inc. Xilinx hereby ** -- ** grants you a license to use this text/file solely for ** -- ** design, simulation, implementation and creation of ** -- ** design files limited to Xilinx devices or technologies. ** -- ** Use with non-Xilinx devices or technologies is expressly ** -- ** prohibited and immediately terminates your license unless ** -- ** covered by a separate agreement. ** -- ** ** -- ** Xilinx is providing this design, code, or information ** -- ** "as-is" solely for use in developing programs and ** -- ** solutions for Xilinx devices, with no obligation on the ** -- ** part of Xilinx to provide support. By providing this design, ** -- ** code, or information as one possible implementation of ** -- ** this feature, application or standard, Xilinx is making no ** -- ** representation that this implementation is free from any ** -- ** claims of infringement. You are responsible for obtaining ** -- ** any rights you may require for your implementation. ** -- ** Xilinx expressly disclaims any warranty whatsoever with ** -- ** respect to the adequacy of the implementation, including ** -- ** but not limited to any warranties or representations that this ** -- ** implementation is free from claims of infringement, implied ** -- ** warranties of merchantability or fitness for a particular ** -- ** purpose. ** -- ** ** -- ** Xilinx products are not intended for use in life support ** -- ** appliances, devices, or systems. Use in such applications is ** -- ** expressly prohibited. ** -- ** ** -- ** Any modifications that are made to the Source Code are ** -- ** done at the users sole risk and will be unsupported. ** -- ** The Xilinx Support Hotline does not have access to source ** -- ** code and therefore cannot answer specific questions related ** -- ** to source HDL. The Xilinx Hotline support of original source ** -- ** code IP shall only address issues and questions related ** -- ** to the standard Netlist version of the core (and thus ** -- ** indirectly, the original core source). ** -- ** ** -- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** This copyright and support notice must be retained as part ** -- ** of this text at all times. ** -- ** ** -- ************************************************************************* -- ------------------------------------------------------------------------------ -- Filename: down_counter.vhd -- -- Description: Parameterizable down counter with synchronous load and -- reset. -- ------------------------------------------------------------------------------- -- Structure: -- Multi-use module ------------------------------------------------------------------------------- -- Author: ALS -- History: -- ALS 04/10/01 -- First version -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Changed proc_common library version to v4_0 -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_cmb" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.STD_LOGIC_1164.all; use ieee.STD_LOGIC_ARITH.all; -- PROC_COMMON_PKG contains the RESET_ACTIVE constant library proc_common_v4_0; use proc_common_v4_0.proc_common_pkg.all; ------------------------------------------------------------------------------- -- Port Declaration ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Definition of Generics: -- C_CNT_WIDTH -- counter width -- -- Definition of Ports: -- input Din -- data to be loaded into counter -- input Load -- load control signal -- input Cnt_en -- count enable signal -- input Clk -- input Rst -- -- output Cnt_out -- counter output ------------------------------------------------------------------------------- entity down_counter is generic ( -- Select width of counter C_CNT_WIDTH : INTEGER := 4 ); port ( Din : in std_logic_vector(0 to C_CNT_WIDTH-1); Load : in std_logic; Cnt_en : in std_logic; Cnt_out : out std_logic_vector(0 to C_CNT_WIDTH - 1 ); Clk : in std_logic; Rst : in std_logic ); end down_counter; architecture simulation of down_counter is ------------------------------------------------------------------------------- -- Signal Declarations ------------------------------------------------------------------------------- -- internal count signal cnt : unsigned(0 to C_CNT_WIDTH - 1 ); begin ------------------------------------------------------------------------------- -- COUNTER_PROCESS process ------------------------------------------------------------------------------- COUNTER_PROCESS:process (Clk) begin if Clk'event and Clk = '1' then if Rst = RESET_ACTIVE then cnt <= (others => '0'); elsif Load = '1' then cnt <= unsigned(Din); elsif Cnt_en = '1' then cnt <= cnt - 1; else cnt <= cnt; end if; end if; end process COUNTER_PROCESS; CNTOUT_PROCESS:process (cnt) begin Cnt_out <= conv_std_logic_vector(cnt, C_CNT_WIDTH); end process CNTOUT_PROCESS; end simulation;

mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/fifo_generator_v11_0/ramfifo/fifo_generator_ramfifo.vhd

19

78408

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mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_xbar_1/fifo_generator_v11_0/builtin/fifo_generator_v11_0_comps_builtin.vhd

19

32006

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block bdlZLEAewQqpv1o7OoBr4R377V8Hk5Fd8+q/Az6G9nxroFaOnD3V9+lWQZaiTQ+UR8tYlBixiDT3 2rrbvlUYqg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block PNj5XhRRPylbuLUnq16m36512+Iu+tuxUNOB5vui/U9Vyxliy5LDYUjGyTrkosJ5RLmSfgYfmdaq x3GXyG6MVOiZo15XiDmGz5Xa3WMM3TuUhfpzNItvR+cjVJcfSX1Vpo9/m4Gf2HbgWDY8/uge9Yz+ pdDWTg9IqOS1f9m0bhc= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/fifo_generator_v11_0/builtin/builtin_extdepth_low_latency.vhd

19

43742

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block L9EbKuxxzV/09pnAb0OGW9DxPQ+o+m/MvX4x5f3JCiR63+KWt2eYB17k+9mGgVY+K1VLxoYz0z6V YvlDefublw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block gJD53XIM6IXGcoGao7b+pChhlJwhGxOuVwSTI1iU+aaEVIG37JelabzUSiGlwgboK2Zv8N9/EzBK Y9pDSGcMvhlTABOa75VEGmta9QvVzRVMjXtd0b/jrdUkZar600zvkPbB8+QESNshxT7B96klkdIo XvMdlDR/SEQxmh4Mkpk= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/proc_common_v4_0/hdl/src/vhdl/or_gate.vhd

15

9199

------------------------------------------------------------------------------- -- $Id: or_gate.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $ ------------------------------------------------------------------------------- -- or_gate.vhd - entity/architecture pair ------------------------------------------------------------------------------- -- -- ************************************************************************* -- ** ** -- ** DISCLAIMER OF LIABILITY ** -- ** ** -- ** This text/file contains proprietary, confidential ** -- ** information of Xilinx, Inc., is distributed under ** -- ** license from Xilinx, Inc., and may be used, copied ** -- ** and/or disclosed only pursuant to the terms of a valid ** -- ** license agreement with Xilinx, Inc. Xilinx hereby ** -- ** grants you a license to use this text/file solely for ** -- ** design, simulation, implementation and creation of ** -- ** design files limited to Xilinx devices or technologies. ** -- ** Use with non-Xilinx devices or technologies is expressly ** -- ** prohibited and immediately terminates your license unless ** -- ** covered by a separate agreement. ** -- ** ** -- ** Xilinx is providing this design, code, or information ** -- ** "as-is" solely for use in developing programs and ** -- ** solutions for Xilinx devices, with no obligation on the ** -- ** part of Xilinx to provide support. By providing this design, ** -- ** code, or information as one possible implementation of ** -- ** this feature, application or standard, Xilinx is making no ** -- ** representation that this implementation is free from any ** -- ** claims of infringement. You are responsible for obtaining ** -- ** any rights you may require for your implementation. ** -- ** Xilinx expressly disclaims any warranty whatsoever with ** -- ** respect to the adequacy of the implementation, including ** -- ** but not limited to any warranties or representations that this ** -- ** implementation is free from claims of infringement, implied ** -- ** warranties of merchantability or fitness for a particular ** -- ** purpose. ** -- ** ** -- ** Xilinx products are not intended for use in life support ** -- ** appliances, devices, or systems. Use in such applications is ** -- ** expressly prohibited. ** -- ** ** -- ** Any modifications that are made to the Source Code are ** -- ** done at the users sole risk and will be unsupported. ** -- ** The Xilinx Support Hotline does not have access to source ** -- ** code and therefore cannot answer specific questions related ** -- ** to source HDL. The Xilinx Hotline support of original source ** -- ** code IP shall only address issues and questions related ** -- ** to the standard Netlist version of the core (and thus ** -- ** indirectly, the original core source). ** -- ** ** -- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** This copyright and support notice must be retained as part ** -- ** of this text at all times. ** -- ** ** -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: or_gate.vhd -- Version: v1.00a -- Description: OR gate implementation -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- or_gate.vhd -- ------------------------------------------------------------------------------- -- Author: B.L. Tise -- History: -- BLT 2001-05-23 First Version -- ^^^^^^ -- First version of OPB Bus. -- ~~~~~~ -- -- DET 1/17/2008 v4_0 -- ~~~~~~ -- - Changed proc_common library version to v4_0 -- - Incorporated new disclaimer header -- ^^^^^^ -- ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library proc_common_v4_0; use proc_common_v4_0.all; ------------------------------------------------------------------------------- -- Definition of Generics: -- C_OR_WIDTH -- Which Xilinx FPGA family to target when -- syntesizing, affect the RLOC string values -- C_BUS_WIDTH -- Which Y position the RLOC should start from -- -- Definition of Ports: -- A -- Input. Input buses are concatenated together to -- form input A. Example: to OR buses R, S, and T, -- assign A <= R & S & T; -- Y -- Output. Same width as input buses. -- ------------------------------------------------------------------------------- entity or_gate is generic ( C_OR_WIDTH : natural range 1 to 32 := 17; C_BUS_WIDTH : natural range 1 to 64 := 1; C_USE_LUT_OR : boolean := TRUE ); port ( A : in std_logic_vector(0 to C_OR_WIDTH*C_BUS_WIDTH-1); Y : out std_logic_vector(0 to C_BUS_WIDTH-1) ); end entity or_gate; architecture imp of or_gate is ------------------------------------------------------------------------------- -- Component Declarations ------------------------------------------------------------------------------- component or_muxcy generic ( C_NUM_BITS : integer := 8 ); port ( In_bus : in std_logic_vector(0 to C_NUM_BITS-1); Or_out : out std_logic ); end component or_muxcy; signal test : std_logic_vector(0 to C_BUS_WIDTH-1); ------------------------------------------------------------------------------- -- Begin architecture ------------------------------------------------------------------------------- begin USE_LUT_OR_GEN: if C_USE_LUT_OR generate OR_PROCESS: process( A ) is variable yi : std_logic_vector(0 to (C_OR_WIDTH)); begin for j in 0 to C_BUS_WIDTH-1 loop yi(0) := '0'; for i in 0 to C_OR_WIDTH-1 loop yi(i+1) := yi(i) or A(i*C_BUS_WIDTH+j); end loop; Y(j) <= yi(C_OR_WIDTH); end loop; end process OR_PROCESS; end generate USE_LUT_OR_GEN; USE_MUXCY_OR_GEN: if not C_USE_LUT_OR generate BUS_WIDTH_FOR_GEN: for i in 0 to C_BUS_WIDTH-1 generate signal in_Bus : std_logic_vector(0 to C_OR_WIDTH-1); begin ORDER_INPUT_BUS_PROCESS: process( A ) is begin for k in 0 to C_OR_WIDTH-1 loop in_Bus(k) <= A(k*C_BUS_WIDTH+i); end loop; end process ORDER_INPUT_BUS_PROCESS; OR_BITS_I: or_muxcy generic map ( C_NUM_BITS => C_OR_WIDTH ) port map ( In_bus => in_Bus, --[in] Or_out => Y(i) --[out] ); end generate BUS_WIDTH_FOR_GEN; end generate USE_MUXCY_OR_GEN; end architecture imp;

mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_xbar_1/fifo_generator_v11_0/fifo_generator_v11_0_defaults.vhd

19

30145

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mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_0_0/fifo_generator_v11_0/ramfifo/wr_logic_pkt_fifo.vhd

19

31831

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block Pb7E+qNVEP4sE5d3TkwQJMYKTR/FjAPrexB6qdDJcLdscPV5w27UvNCqw/kg86JgS2hNrfoEvTNF uJ9eNTpy4Q== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Egq1eCtVuCp02bpffloqFi7UMw6fphk3UOZCcejhe9NQNeC0Z0b1+S1NY8yEfAVY74l4oz8pZ1vA hbrAzplanZae/BDY57rCQ6UjD8G9keaOwYv6mG13f+m77D7Y1nVpXOE4Uujw3cZ1QgwXR1H4YfYp ysjb+lxmo0pqYRikRIQ= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block KJqrZ5TKkbTlecBRrKRCsxKhAd1omWJvIin7DNafgTE5a5N2or7GsTSawdWWjYWHESLBvStvRGQE jVUeK8m63dYVJN98fa8T9iAHTDt9yiBRki/VqfvAejvDOEI+l8row+LhhHMvCd29xmkCeQKiq4Qt hsdsz+jNufnCYY4Y1CVO/4preMZeG5Ow85vRd/341CoWEOBji8o4pk0XyIttBBgjBzWO8JyhLpza R+Z8LgFoZ5OTfgpyTJ4SjYRWp9IHP2HL9TShNo3PmM36nFNBvQSLoEjLgk4+rUr657++ugJH31/C Y/QScvwJcbqMK15awb6twj42y2gxJSFzAPzSGg== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block KxmYEF19quU2lnDIx1hLVbiBV1iU7MlwBSbpQKNAVv6HLtZNpIjv2UPtz6sPs9Xac0T26s1Kjo2c fAw+uaSeKdgWE1BMMV8ya3nIO40+wJlyaPYGp3qW9dt6kM+FZZl/3MCpgIMx24FXg4CPHrHNKu54 /3DZJ7o9x/QjyM8WSeM= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block n4InNydlMoO1IH7Kq1VdB5tuRxM6d++erhleefbfKU7rQGdfSjRtqcQ+h67LKfA/jQJYdDdZMjd3 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mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_auto_pc_3/fifo_generator_v11_0/ramfifo/wr_logic_pkt_fifo.vhd

19

31831

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block Pb7E+qNVEP4sE5d3TkwQJMYKTR/FjAPrexB6qdDJcLdscPV5w27UvNCqw/kg86JgS2hNrfoEvTNF uJ9eNTpy4Q== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Egq1eCtVuCp02bpffloqFi7UMw6fphk3UOZCcejhe9NQNeC0Z0b1+S1NY8yEfAVY74l4oz8pZ1vA hbrAzplanZae/BDY57rCQ6UjD8G9keaOwYv6mG13f+m77D7Y1nVpXOE4Uujw3cZ1QgwXR1H4YfYp ysjb+lxmo0pqYRikRIQ= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block KJqrZ5TKkbTlecBRrKRCsxKhAd1omWJvIin7DNafgTE5a5N2or7GsTSawdWWjYWHESLBvStvRGQE jVUeK8m63dYVJN98fa8T9iAHTDt9yiBRki/VqfvAejvDOEI+l8row+LhhHMvCd29xmkCeQKiq4Qt hsdsz+jNufnCYY4Y1CVO/4preMZeG5Ow85vRd/341CoWEOBji8o4pk0XyIttBBgjBzWO8JyhLpza R+Z8LgFoZ5OTfgpyTJ4SjYRWp9IHP2HL9TShNo3PmM36nFNBvQSLoEjLgk4+rUr657++ugJH31/C Y/QScvwJcbqMK15awb6twj42y2gxJSFzAPzSGg== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block KxmYEF19quU2lnDIx1hLVbiBV1iU7MlwBSbpQKNAVv6HLtZNpIjv2UPtz6sPs9Xac0T26s1Kjo2c fAw+uaSeKdgWE1BMMV8ya3nIO40+wJlyaPYGp3qW9dt6kM+FZZl/3MCpgIMx24FXg4CPHrHNKu54 /3DZJ7o9x/QjyM8WSeM= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block n4InNydlMoO1IH7Kq1VdB5tuRxM6d++erhleefbfKU7rQGdfSjRtqcQ+h67LKfA/jQJYdDdZMjd3 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mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_0_0/fifo_generator_v11_0/ramfifo/bram_sync_reg.vhd

19

7904

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block ISK+8BrzqbDVc2hIh4k9UuGvqsq6yFic71tfszsK7KRf52jFUoK33AosGVUYsGH1pmrUc2NUQcDQ LseNrcojiQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block CxxZHetyKRTjg1ePIJzq+w/Yg+inN7g9nkhYUjpPSXav+SKIAQvdh174FZUi0SnoR2INo+rdZ3gz yq46XymO3b/3npnRNCCU259giTvnOJxmkrtnjRyUpOg8jB2jnHg/f/BlL3OJUGGiFonBs+6rnNvW 4aiU6ycFpLQsNzqRlAw= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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GPxAxnrSDPM= `protect end_protected

mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_axi_gpio_1_1/fifo_generator_v11_0/ramfifo/bram_sync_reg.vhd

19

7904

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block ISK+8BrzqbDVc2hIh4k9UuGvqsq6yFic71tfszsK7KRf52jFUoK33AosGVUYsGH1pmrUc2NUQcDQ LseNrcojiQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block CxxZHetyKRTjg1ePIJzq+w/Yg+inN7g9nkhYUjpPSXav+SKIAQvdh174FZUi0SnoR2INo+rdZ3gz yq46XymO3b/3npnRNCCU259giTvnOJxmkrtnjRyUpOg8jB2jnHg/f/BlL3OJUGGiFonBs+6rnNvW 4aiU6ycFpLQsNzqRlAw= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block HZ1Kttz7DNn3t428AVZ/hrbCqljpJfsdfcEo7T7pfqxl88ELioDFFp9rVcvvZiZMU++45qS8CpOD SfwcEjOj8ndwnIsrDamIUHs+Qm4vUDDq8EtyiGhux+pwMtpg8rH6kCwLDCkdk848fWRbBOGctdAr AiQz4Fie2ectzKGEhjERjquMNqkQkhNIuEu/CSTnyD7KnG+FK+llVBavN8lxjWeDvk+quMyk8Dbo gA/SdzYI7TCZkNEFS/PvF3Z8fPBK4pBWz7TyfdHacMjMkaPd5zGsPBmQy77xwc4m/sfhM7ZX+YW6 VBTILiYtg7u194UVgu4fHE7f45jr0jTur9wbVw== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block 2VX2NPBJC/FYSjnVp8ueqtxuxLgenRIKbrff8tdhuTb77js7o9S4OVH2n84fEyvr3hl3lrO9ekVq VvQQOlQBg7Zv5/tFAeI5YFisgygYrqeX9dQcI485CaCpeN9nanYXhtHWROH+ZOYckBZHUhhjC82p LnYwoausKSjsi+rXE64= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block HdQIwrCqCFDZv9OQZsva3DMtF+8TwiePvWLQndNAXK/1V46C6C4sVLdH6SK4FvPis45PZ52T91rx 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GPxAxnrSDPM= `protect end_protected

mit

bpervan/zedboard

LRI-Lab5.srcs/sources_1/bd/ZynqDesign/ip/ZynqDesign_rst_processing_system7_0_100M_0/fifo_generator_v11_0/ramfifo/dc_ss_fwft.vhd

19

9156

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block eRz+leRSRPpou0Iyb6bnhB8hg9kPbBirrzFUAdKqw/be3+N8ZrhDizYaLfXqnwxlgZsSWJCzRfM7 HvMw/rTLhw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Rl74r1iJC/bnSjzA+Rx4NZe56NnmjoVRFzUux12uAkwgT++rVuZ0cWQxVSY31Gff9TGn02lNxavo U1xWF81U2u/Zi0XY7ZHmbpbdUEdpSv9huiEIrpuLuTgWjBSUwsGYqRxHLx1vq4vioRXFlAhPk9JA iYodwxjKI7YbbZElfVA= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block lO1ylq105LQ/xiJNZcB3fPTy1RngsQ3yQ/KJ6FM1qs+SoXmUQjQaEb6hJLPAypYN8r4VdJAzSC/U 5nFe27DWNjEKmiIleROkH20okne+9N7+PhPIZQnib521U3SV/ecBImKKPYRpHhAeqE7OE/DzQFWx 10ISqR1I6WBii4R8gkz5k4dkFHhiTU6fgkIHLUXXclJrpQ6fHHlk7MPcpQDjK7bXjIiQ81qfpVmp P5Kh8wiY7VppUj33GlIcYsNio8GAIV3e0kBKLoX73uDqdvJ/2zBzKOZoDd0As7C4AHF8YSixL0MC djalIDRCSOBX8Rd9h057rIe8ZIXNMu/BHoKk/g== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block aJoUzTg4Ju9hNY+ZPcuNUmGg+rCD8aivgSTst8VRB5/g9QHuzghA24ad2z08gxWDFeIOT/HFgT6H g4nDsyLlbHK2gxUijkJ6ORkRfGOxb8UwHTzLEIRJ5zmkHtJXYM250JOsiukrgEDT40HqdtSgre6O kXXliGFm9MU0LwRby+I= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block ca/+TaSll/KHF7mIE37XMZRKDQpSdluwuJA9x/CRPHNmOrubSxRKoPtbXlxVM6ehE2hXp6yB6qBf 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mit

dries007/Basys3

FPGA-Z/FPGA-Z.srcs/sim_1/new/test2.vhd

1

902

---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 04/16/2016 09:56:37 PM -- Design Name: -- Module Name: test2 - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity test2 is -- Port ( ); end test2; architecture Behavioral of test2 is begin end Behavioral;

mit

dries007/Basys3

VGA_text/VGA_text.srcs/sources_1/ip/FrameBuffer/FrameBuffer_sim_netlist.vhdl

1

105072

-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015 -- Date : Fri Jun 3 00:16:36 2016 -- Host : Dries007-Arch running 64-bit unknown -- Command : write_vhdl -force -mode funcsim -- /home/dries/Projects/Basys3/VGA_text/VGA_text.srcs/sources_1/ip/FrameBuffer/FrameBuffer_sim_netlist.vhdl -- Design : FrameBuffer -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7a35tcpg236-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity FrameBuffer_blk_mem_gen_mux is port ( douta : out STD_LOGIC_VECTOR ( 7 downto 0 ); DOADO : in STD_LOGIC_VECTOR ( 7 downto 0 ); \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); addra : in STD_LOGIC_VECTOR ( 2 downto 0 ); ena : in STD_LOGIC; clka : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_mux : entity is "blk_mem_gen_mux"; end FrameBuffer_blk_mem_gen_mux; architecture STRUCTURE of FrameBuffer_blk_mem_gen_mux is signal \no_softecc_sel_reg.ce_pri.sel_pipe[0]_i_1_n_0\ : STD_LOGIC; signal \no_softecc_sel_reg.ce_pri.sel_pipe[1]_i_1_n_0\ : STD_LOGIC; signal \no_softecc_sel_reg.ce_pri.sel_pipe[2]_i_1_n_0\ : STD_LOGIC; signal sel_pipe : STD_LOGIC_VECTOR ( 2 downto 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \no_softecc_sel_reg.ce_pri.sel_pipe[1]_i_1\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \no_softecc_sel_reg.ce_pri.sel_pipe[2]_i_1\ : label is "soft_lutpair0"; begin \douta[0]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOADO(0), I1 => sel_pipe(0), I2 => sel_pipe(1), I3 => sel_pipe(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(0), I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(0), O => douta(0) ); \douta[1]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOADO(1), I1 => sel_pipe(0), I2 => sel_pipe(1), I3 => sel_pipe(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(1), I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(1), O => douta(1) ); \douta[2]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOADO(2), I1 => sel_pipe(0), I2 => sel_pipe(1), I3 => sel_pipe(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(2), I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(2), O => douta(2) ); \douta[3]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOADO(3), I1 => sel_pipe(0), I2 => sel_pipe(1), I3 => sel_pipe(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3), I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(3), O => douta(3) ); \douta[4]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOADO(4), I1 => sel_pipe(0), I2 => sel_pipe(1), I3 => sel_pipe(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(4), I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(4), O => douta(4) ); \douta[5]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOADO(5), I1 => sel_pipe(0), I2 => sel_pipe(1), I3 => sel_pipe(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(5), I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(5), O => douta(5) ); \douta[6]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOADO(6), I1 => sel_pipe(0), I2 => sel_pipe(1), I3 => sel_pipe(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(6), I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(6), O => douta(6) ); \douta[7]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOADO(7), I1 => sel_pipe(0), I2 => sel_pipe(1), I3 => sel_pipe(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(7), I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7), O => douta(7) ); \no_softecc_sel_reg.ce_pri.sel_pipe[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => addra(0), I1 => ena, I2 => sel_pipe(0), O => \no_softecc_sel_reg.ce_pri.sel_pipe[0]_i_1_n_0\ ); \no_softecc_sel_reg.ce_pri.sel_pipe[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => addra(1), I1 => ena, I2 => sel_pipe(1), O => \no_softecc_sel_reg.ce_pri.sel_pipe[1]_i_1_n_0\ ); \no_softecc_sel_reg.ce_pri.sel_pipe[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => addra(2), I1 => ena, I2 => sel_pipe(2), O => \no_softecc_sel_reg.ce_pri.sel_pipe[2]_i_1_n_0\ ); \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clka, CE => '1', D => \no_softecc_sel_reg.ce_pri.sel_pipe[0]_i_1_n_0\, Q => sel_pipe(0), R => '0' ); \no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clka, CE => '1', D => \no_softecc_sel_reg.ce_pri.sel_pipe[1]_i_1_n_0\, Q => sel_pipe(1), R => '0' ); \no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clka, CE => '1', D => \no_softecc_sel_reg.ce_pri.sel_pipe[2]_i_1_n_0\, Q => sel_pipe(2), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \FrameBuffer_blk_mem_gen_mux__parameterized0\ is port ( doutb : out STD_LOGIC_VECTOR ( 7 downto 0 ); DOBDO : in STD_LOGIC_VECTOR ( 7 downto 0 ); \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 2 downto 0 ); clkb : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \FrameBuffer_blk_mem_gen_mux__parameterized0\ : entity is "blk_mem_gen_mux"; end \FrameBuffer_blk_mem_gen_mux__parameterized0\; architecture STRUCTURE of \FrameBuffer_blk_mem_gen_mux__parameterized0\ is signal \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0]\ : STD_LOGIC; signal \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[1]\ : STD_LOGIC; signal \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[2]\ : STD_LOGIC; signal sel_pipe_d1 : STD_LOGIC_VECTOR ( 2 downto 0 ); begin \doutb[0]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOBDO(0), I1 => sel_pipe_d1(0), I2 => sel_pipe_d1(1), I3 => sel_pipe_d1(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(0), I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(0), O => doutb(0) ); \doutb[1]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOBDO(1), I1 => sel_pipe_d1(0), I2 => sel_pipe_d1(1), I3 => sel_pipe_d1(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(1), I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(1), O => doutb(1) ); \doutb[2]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOBDO(2), I1 => sel_pipe_d1(0), I2 => sel_pipe_d1(1), I3 => sel_pipe_d1(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(2), I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(2), O => doutb(2) ); \doutb[3]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOBDO(3), I1 => sel_pipe_d1(0), I2 => sel_pipe_d1(1), I3 => sel_pipe_d1(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3), I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(3), O => doutb(3) ); \doutb[4]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOBDO(4), I1 => sel_pipe_d1(0), I2 => sel_pipe_d1(1), I3 => sel_pipe_d1(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(4), I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(4), O => doutb(4) ); \doutb[5]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOBDO(5), I1 => sel_pipe_d1(0), I2 => sel_pipe_d1(1), I3 => sel_pipe_d1(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(5), I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(5), O => doutb(5) ); \doutb[6]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOBDO(6), I1 => sel_pipe_d1(0), I2 => sel_pipe_d1(1), I3 => sel_pipe_d1(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(6), I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(6), O => doutb(6) ); \doutb[7]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOBDO(7), I1 => sel_pipe_d1(0), I2 => sel_pipe_d1(1), I3 => sel_pipe_d1(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(7), I5 => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7), O => doutb(7) ); \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clkb, CE => '1', D => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0]\, Q => sel_pipe_d1(0), R => '0' ); \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clkb, CE => '1', D => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[1]\, Q => sel_pipe_d1(1), R => '0' ); \no_softecc_norm_sel2.has_mem_regs.WITHOUT_ECC_PIPE.ce_pri.sel_pipe_d1_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clkb, CE => '1', D => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[2]\, Q => sel_pipe_d1(2), R => '0' ); \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clkb, CE => '1', D => addrb(0), Q => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[0]\, R => '0' ); \no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clkb, CE => '1', D => addrb(1), Q => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[1]\, R => '0' ); \no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clkb, CE => '1', D => addrb(2), Q => \no_softecc_sel_reg.ce_pri.sel_pipe_reg_n_0_[2]\, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity FrameBuffer_blk_mem_gen_prim_wrapper_init is port ( \douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); \doutb[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); clka : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 7 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ); web : in STD_LOGIC_VECTOR ( 0 to 0 ); ena : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init"; end FrameBuffer_blk_mem_gen_prim_wrapper_init; architecture STRUCTURE of FrameBuffer_blk_mem_gen_prim_wrapper_init is signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1_n_0\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2_n_0\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_n_92\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute CLOCK_DOMAINS : string; attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT"; attribute box_type : string; attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE"; begin \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1 generic map( DOA_REG => 0, DOB_REG => 1, EN_ECC_READ => false, EN_ECC_WRITE => false, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"2020202020202020202020202020202020202020202020202020202020202B80", INIT_01 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_02 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_03 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_04 => X"802B202020202020202020202020202020202020202020202020202020202020", INIT_05 => X"4646464646464646464646464646464646464620202020202020202020202B2B", INIT_06 => X"4720202020202020202020205050505050505050505050505050505050464646", INIT_07 => X"2020414141202020202020202020202020202020474747474747474747474747", INIT_08 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_09 => X"2B2B202020202020202020202047474747474747474747474747202020202020", INIT_0A => X"3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A4620202020202020202020202020", INIT_0B => X"3A47474720202020202020503A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A50463A3A", INIT_0C => X"20413A3A3A412020202020202020202020202020473A3A3A3A3A3A3A3A3A3A3A", INIT_0D => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_0E => X"20202020202020202020202020473A3A3A3A3A3A3A3A3A3A3A3A474747202020", INIT_0F => X"3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A4620202020202020202020202020", INIT_10 => X"3A3A3A3A474720202020503A3A3A3A3A5050505050503A3A3A3A3A3A50463A3A", INIT_11 => X"413A3A3A3A3A4120202020202020202020202020473A3A3A3A3A3A3A3A3A3A3A", INIT_12 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_13 => X"20202020202020202020202020473A3A3A3A3A3A3A3A3A3A3A3A3A3A3A474720", INIT_14 => X"3A3A4646464646464646463A3A3A3A3A3A464620202020202020202020202020", INIT_15 => X"473A3A3A3A3A472020503A3A3A3A3A502020202020503A3A3A3A3A5050463A3A", INIT_16 => X"3A3A3A3A3A3A3A41202020202020202020202020473A3A3A3A47474747474747", INIT_17 => X"2020202020202020202020202020202020202020202020202020202020202041", INIT_18 => X"20202020202020202020202020473A3A3A3A47474747474747473A3A3A3A3A47", INIT_19 => X"46464620202020202020463A3A3A3A3A46202020202020202020202020202020", INIT_1A => X"20473A3A3A3A3A4720503A3A3A3A3A502020202020503A3A3A3A502020464646", INIT_1B => X"3A3A3A3A3A3A3A3A412020202020202020202020474747474747202020202020", INIT_1C => X"472020202020202020202020202020202020202020202020202020202020413A", INIT_1D => X"2020202020202020202020202047474747474720202020202020473A3A3A3A3A", INIT_1E => X"20202020202020202020463A3A3A3A3A46202020202020202020202020202020", INIT_1F => X"2020473A3A3A3A3A47503A3A3A3A3A502020202020503A3A3A3A502020202020", INIT_20 => X"3A3A3A413A3A3A3A3A4120202020202020202020202020202020202020202020", INIT_21 => X"3A47202020202020202020202020202020202020202020202020202020413A3A", INIT_22 => X"202020202020202020202020202020202020202020202020202020473A3A3A3A", INIT_23 => X"464646464646464646463A3A3A3A3A3A46202020202020202020202020202020", INIT_24 => X"2020473A3A3A3A3A4720503A3A3A3A3A5050505050503A3A3A3A502020202020", INIT_25 => X"3A3A4120413A3A3A3A3A41202020202020202020202020202020202020202020", INIT_26 => X"3A472020202020202020202020202020202020202020202020202020413A3A3A", INIT_27 => X"202020202020202020202020202020202020202020202020202020473A3A3A3A", INIT_28 => X"463A3A3A3A3A3A3A3A3A3A3A3A3A3A3A46202020202020202020202020202020", INIT_29 => X"2020473A3A3A3A3A47202050503A3A3A3A3A3A3A3A3A3A3A3A3A502020202020", INIT_2A => X"3A41202020413A3A3A3A3A412020202020202020474747474747474747472020", INIT_2B => X"3A47202D2D2D2D2D2D2D2D2D2D2D2D2D2D2D202020202020202020413A3A3A3A", INIT_2C => X"202020202020202020202020204747474747474747474720202020473A3A3A3A", INIT_2D => X"463A3A3A3A3A3A3A3A3A3A3A3A3A3A3A46202020202020202020202020202020", INIT_2E => X"2020473A3A3A3A3A47202020205050505050505050503A3A3A3A502020202020", INIT_2F => X"412020202020413A3A3A3A3A4120202020202020473A3A3A3A3A3A3A3A472020", INIT_30 => X"3A47202D3A3A3A3A3A3A3A3A3A3A3A3A3A2D2020202020202020413A3A3A3A3A", INIT_31 => X"20202020202020202020202020473A3A3A3A3A3A3A3A4720202020473A3A3A3A", INIT_32 => X"464646464646464646463A3A3A3A3A3A46202020202020202020202020202020", INIT_33 => X"2020473A3A3A3A3A47202020202020202020202020503A3A3A3A502020202020", INIT_34 => X"41414141414141413A3A3A3A3A41202020202020473A3A3A3A47474747472020", INIT_35 => X"3A47202D2D2D2D2D2D2D2D2D2D2D2D2D2D2D20202020202020413A3A3A3A3A41", INIT_36 => X"20202020202020202020202020473A3A3A3A474747474720202020473A3A3A3A", INIT_37 => X"20202020202020202020463A3A3A3A3A46202020202020202020202020202020", INIT_38 => X"2020473A3A3A3A3A47202020202020202020202020503A3A3A3A502020202020", INIT_39 => X"3A3A3A3A3A3A3A3A3A3A3A3A3A3A412020202020473A3A3A3A47202020202020", INIT_3A => X"3A4720202020202020202020202020202020202020202020413A3A3A3A3A3A3A", INIT_3B => X"20202020202020202020202020473A3A3A3A472020202020202020473A3A3A3A", INIT_3C => X"20202020202020202020463A3A3A3A3A46202020202020202020202020202020", INIT_3D => X"20473A3A3A3A3A4720202020202020202020202020503A3A3A3A502020202020", INIT_3E => X"414141414141414141413A3A3A3A3A4120202020473A3A3A3A47202020202020", INIT_3F => X"4720202020202020202020202020202020202020202020413A3A3A3A3A414141", INIT_40 => X"20202020202020202020202020473A3A3A3A4720202020202020473A3A3A3A3A", INIT_41 => X"202020202020202046463A3A3A3A3A3A3A464620202020202020202020202020", INIT_42 => X"473A3A3A3A3A4720202020202020202020202050503A3A3A3A3A3A5050202020", INIT_43 => X"20202020202020202020413A3A3A3A3A41202020473A3A3A3A47474747474747", INIT_44 => X"20202020202020202020202020202020202020202020413A3A3A3A3A41202020", INIT_45 => X"20202020202020202020202020473A3A3A3A47474747474747473A3A3A3A3A47", INIT_46 => X"202020202020202046463A3A3A3A3A3A3A3A4620202020202020202020202020", INIT_47 => X"3A3A3A3A474720202020202020202020202020503A3A3A3A3A3A3A3A50202020", INIT_48 => X"2020202020202020202020413A3A3A3A3A412020473A3A3A3A3A3A3A3A3A3A3A", INIT_49 => X"202020202020202020202020202020202020202020413A3A3A3A3A4120202020", INIT_4A => X"20202020202020202020202020473A3A3A3A3A3A3A3A3A3A3A3A3A3A3A474720", INIT_4B => X"202020202020202046463A3A3A3A3A3A3A3A4620202020202020202020202020", INIT_4C => X"3A474747202020202020202020202020202020503A3A3A3A3A3A3A3A50202020", INIT_4D => X"202020202020202020202020413A3A3A3A3A4120473A3A3A4747473A3A3A3A3A", INIT_4E => X"2020202020202020202020202020202020202020413A3A3A3A3A412020202020", INIT_4F => X"20202020202020202020202020473A3A3A4747473A3A3A3A3A3A474747202020", INIT_50 => X"2020202020202020464646464646464646464620202020202020202020202020", INIT_51 => X"4720202020202020202020202020202020202050505050505050505050202020", INIT_52 => X"2020202020202020202020202041414141414141474747472020204747474747", INIT_53 => X"2020202020202020202020202020202020202041414141414141202020202020", INIT_54 => X"2020202020202020202020202047474747202020474747474747202020202020", INIT_55 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_56 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_57 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_58 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_59 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_5A => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_5B => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_5C => X"6F6E6973616320696E696D206465736162204C444856202F2041475046206E41", INIT_5D => X"202020202020202020202020202020202020202020202020202020202020202E", INIT_5E => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_5F => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_60 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_61 => X"20217475706E69207478657420726F662064616F6279656B2061206573552020", INIT_62 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_63 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_64 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_65 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_66 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_67 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_68 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_69 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_6A => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_6B => X"202020203A656B696C206427756F7920656D61672061206B6369502020202020", INIT_6C => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_6D => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_6E => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_6F => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_70 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_71 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_72 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_73 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_74 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_75 => X"2020202020202020202020657474656C756F5220202020202020202020202020", INIT_76 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_77 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_78 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_79 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_7A => X"2020202020202020207265776F6C207265686769482020202020202020202020", INIT_7B => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_7C => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_7D => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_7E => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_7F => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_A => X"000000000", INIT_B => X"000000000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", READ_WIDTH_A => 9, READ_WIDTH_B => 9, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", WRITE_WIDTH_A => 9, WRITE_WIDTH_B => 9 ) port map ( ADDRARDADDR(15) => '1', ADDRARDADDR(14 downto 3) => addra(11 downto 0), ADDRARDADDR(2 downto 0) => B"111", ADDRBWRADDR(15) => '1', ADDRBWRADDR(14 downto 3) => addrb(11 downto 0), ADDRBWRADDR(2 downto 0) => B"111", CASCADEINA => '0', CASCADEINB => '0', CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\, CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\, CLKARDCLK => clka, CLKBWRCLK => clkb, DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\, DIADI(31 downto 8) => B"000000000000000000000000", DIADI(7 downto 0) => dina(7 downto 0), DIBDI(31 downto 8) => B"000000000000000000000000", DIBDI(7 downto 0) => dinb(7 downto 0), DIPADIP(3 downto 0) => B"0000", DIPBDIP(3 downto 0) => B"0000", DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8), DOADO(7 downto 0) => \douta[7]\(7 downto 0), DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8), DOBDO(7 downto 0) => \doutb[7]\(7 downto 0), DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1), DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_n_88\, DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1), DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_n_92\, ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0), ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1_n_0\, ENBWREN => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2_n_0\, INJECTDBITERR => '0', INJECTSBITERR => '0', RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0), REGCEAREGCE => '0', REGCEB => '1', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\, WEA(3) => wea(0), WEA(2) => wea(0), WEA(1) => wea(0), WEA(0) => wea(0), WEBWE(7 downto 4) => B"0000", WEBWE(3) => web(0), WEBWE(2) => web(0), WEBWE(1) => web(0), WEBWE(0) => web(0) ); \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => ena, I1 => addra(12), I2 => addra(13), O => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1_n_0\ ); \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => addrb(12), I1 => addrb(13), O => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized0\ is port ( \douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); \doutb[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); clka : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 7 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ); web : in STD_LOGIC_VECTOR ( 0 to 0 ); ena : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init"; end \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized0\; architecture STRUCTURE of \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized0\ is signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1__0_n_0\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2__0_n_0\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_n_92\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute CLOCK_DOMAINS : string; attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT"; attribute box_type : string; attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE"; begin \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1 generic map( DOA_REG => 0, DOB_REG => 1, EN_ECC_READ => false, EN_ECC_WRITE => false, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_01 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_02 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_03 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_04 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_05 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_06 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_07 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_08 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_09 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_0A => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_0B => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_0C => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_0D => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_0E => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_0F => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_10 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_11 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_12 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_13 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_14 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_15 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_16 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_17 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_18 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_19 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_1A => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_1B => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_1C => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_1D => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_1E => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_1F => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_20 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_21 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_22 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_23 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_24 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_25 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_26 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_27 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_28 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_29 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_2A => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_2B => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_2C => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_2D => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_2E => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_2F => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_30 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_31 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_32 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_33 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_34 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_35 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_36 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_37 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_38 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_39 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_3A => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_3B => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_3C => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_3D => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_3E => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_3F => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_40 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_41 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_42 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_43 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_44 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_45 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_46 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_47 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_48 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_49 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_4A => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_4B => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_4C => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_4D => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_4E => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_4F => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_50 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_51 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_52 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_53 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_54 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_55 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_56 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_57 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_58 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_59 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_5A => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_5B => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_5C => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_5D => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_5E => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_5F => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_60 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_61 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_62 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_63 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_64 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_65 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_66 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_67 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_68 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_69 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_6A => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_6B => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_6C => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_6D => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_6E => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_6F => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_70 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_71 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_72 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_73 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_74 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_75 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_76 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_77 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_78 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_79 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_7A => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_7B => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_7C => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_7D => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_7E => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_7F => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_A => X"000000000", INIT_B => X"000000000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", READ_WIDTH_A => 9, READ_WIDTH_B => 9, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", WRITE_WIDTH_A => 9, WRITE_WIDTH_B => 9 ) port map ( ADDRARDADDR(15) => '1', ADDRARDADDR(14 downto 3) => addra(11 downto 0), ADDRARDADDR(2 downto 0) => B"111", ADDRBWRADDR(15) => '1', ADDRBWRADDR(14 downto 3) => addrb(11 downto 0), ADDRBWRADDR(2 downto 0) => B"111", CASCADEINA => '0', CASCADEINB => '0', CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\, CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\, CLKARDCLK => clka, CLKBWRCLK => clkb, DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\, DIADI(31 downto 8) => B"000000000000000000000000", DIADI(7 downto 0) => dina(7 downto 0), DIBDI(31 downto 8) => B"000000000000000000000000", DIBDI(7 downto 0) => dinb(7 downto 0), DIPADIP(3 downto 0) => B"0000", DIPBDIP(3 downto 0) => B"0000", DOADO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 8), DOADO(7 downto 0) => \douta[7]\(7 downto 0), DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8), DOBDO(7 downto 0) => \doutb[7]\(7 downto 0), DOPADOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 1), DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_n_88\, DOPBDOP(3 downto 1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 1), DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_n_92\, ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0), ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1__0_n_0\, ENBWREN => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2__0_n_0\, INJECTDBITERR => '0', INJECTSBITERR => '0', RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0), REGCEAREGCE => '0', REGCEB => '1', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\, WEA(3) => wea(0), WEA(2) => wea(0), WEA(1) => wea(0), WEA(0) => wea(0), WEBWE(7 downto 4) => B"0000", WEBWE(3) => web(0), WEBWE(2) => web(0), WEBWE(1) => web(0), WEBWE(0) => web(0) ); \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"08" ) port map ( I0 => addra(12), I1 => ena, I2 => addra(13), O => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_1__0_n_0\ ); \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2__0\: unisim.vcomponents.LUT2 generic map( INIT => X"4" ) port map ( I0 => addrb(13), I1 => addrb(12), O => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_i_2__0_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized1\ is port ( DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 ); DOBDO : out STD_LOGIC_VECTOR ( 7 downto 0 ); clka : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 7 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ); web : in STD_LOGIC_VECTOR ( 0 to 0 ); ena : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized1\ : entity is "blk_mem_gen_prim_wrapper_init"; end \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized1\; architecture STRUCTURE of \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized1\ is signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_n_33\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_n_35\ : STD_LOGIC; signal ram_ena : STD_LOGIC; signal ram_enb : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 8 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 8 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 to 1 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 to 1 ); attribute CLOCK_DOMAINS : string; attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\ : label is "INDEPENDENT"; attribute box_type : string; attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE"; begin \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1 generic map( DOA_REG => 0, DOB_REG => 1, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_01 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_02 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_03 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_04 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_05 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_06 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_07 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_08 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_09 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_0A => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_0B => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_0C => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_0D => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_0E => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_0F => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_10 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_11 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_12 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_13 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_14 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_15 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_16 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_17 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_18 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_19 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_1A => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_1B => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_1C => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_1D => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_1E => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_1F => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_20 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_21 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_22 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_23 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_24 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_25 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_26 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_27 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_28 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_29 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_2A => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_2B => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_2C => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_2D => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_2E => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_2F => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_30 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_31 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_32 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_33 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_34 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_35 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_36 => X"2020202020202020202020202020202020202020202020202020202020202B2B", INIT_37 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_38 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_39 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_3A => X"2B2B202020202020202020202020202020202020202020202020202020202020", INIT_3B => X"2020202020202020202020202020202020202020202020202020202020202B80", INIT_3C => X"6867697279706F43202020202020202020202020202020202020202020202020", INIT_3D => X"656972642F2F3A707474683C2037303073656972442036313032202943282074", INIT_3E => X"20202020202020202020202020202020202020202020203E74656E2E37303073", INIT_3F => X"802B202020202020202020202020202020202020202020202020202020202020", INIT_A => X"00000", INIT_B => X"00000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", READ_WIDTH_A => 9, READ_WIDTH_B => 9, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"00000", SRVAL_B => X"00000", WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", WRITE_WIDTH_A => 9, WRITE_WIDTH_B => 9 ) port map ( ADDRARDADDR(13 downto 3) => addra(10 downto 0), ADDRARDADDR(2 downto 0) => B"000", ADDRBWRADDR(13 downto 3) => addrb(10 downto 0), ADDRBWRADDR(2 downto 0) => B"000", CLKARDCLK => clka, CLKBWRCLK => clkb, DIADI(15 downto 8) => B"00000000", DIADI(7 downto 0) => dina(7 downto 0), DIBDI(15 downto 8) => B"00000000", DIBDI(7 downto 0) => dinb(7 downto 0), DIPADIP(1 downto 0) => B"00", DIPBDIP(1 downto 0) => B"00", DOADO(15 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 8), DOADO(7 downto 0) => DOADO(7 downto 0), DOBDO(15 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 8), DOBDO(7 downto 0) => DOBDO(7 downto 0), DOPADOP(1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1), DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_n_33\, DOPBDOP(1) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1), DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_n_35\, ENARDEN => ram_ena, ENBWREN => ram_enb, REGCEAREGCE => '0', REGCEB => '1', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', WEA(1) => wea(0), WEA(0) => wea(0), WEBWE(3 downto 2) => B"00", WEBWE(1) => web(0), WEBWE(0) => web(0) ); \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"1000" ) port map ( I0 => addra(12), I1 => addra(11), I2 => addra(13), I3 => ena, O => ram_ena ); \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM18.ram_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"04" ) port map ( I0 => addrb(11), I1 => addrb(13), I2 => addrb(12), O => ram_enb ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity FrameBuffer_blk_mem_gen_prim_width is port ( \douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); \doutb[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); clka : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 7 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ); web : in STD_LOGIC_VECTOR ( 0 to 0 ); ena : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width"; end FrameBuffer_blk_mem_gen_prim_width; architecture STRUCTURE of FrameBuffer_blk_mem_gen_prim_width is begin \prim_init.ram\: entity work.FrameBuffer_blk_mem_gen_prim_wrapper_init port map ( addra(13 downto 0) => addra(13 downto 0), addrb(13 downto 0) => addrb(13 downto 0), clka => clka, clkb => clkb, dina(7 downto 0) => dina(7 downto 0), dinb(7 downto 0) => dinb(7 downto 0), \douta[7]\(7 downto 0) => \douta[7]\(7 downto 0), \doutb[7]\(7 downto 0) => \doutb[7]\(7 downto 0), ena => ena, wea(0) => wea(0), web(0) => web(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \FrameBuffer_blk_mem_gen_prim_width__parameterized0\ is port ( \douta[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); \doutb[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); clka : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 7 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ); web : in STD_LOGIC_VECTOR ( 0 to 0 ); ena : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \FrameBuffer_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width"; end \FrameBuffer_blk_mem_gen_prim_width__parameterized0\; architecture STRUCTURE of \FrameBuffer_blk_mem_gen_prim_width__parameterized0\ is begin \prim_init.ram\: entity work.\FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized0\ port map ( addra(13 downto 0) => addra(13 downto 0), addrb(13 downto 0) => addrb(13 downto 0), clka => clka, clkb => clkb, dina(7 downto 0) => dina(7 downto 0), dinb(7 downto 0) => dinb(7 downto 0), \douta[7]\(7 downto 0) => \douta[7]\(7 downto 0), \doutb[7]\(7 downto 0) => \doutb[7]\(7 downto 0), ena => ena, wea(0) => wea(0), web(0) => web(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \FrameBuffer_blk_mem_gen_prim_width__parameterized1\ is port ( DOADO : out STD_LOGIC_VECTOR ( 7 downto 0 ); DOBDO : out STD_LOGIC_VECTOR ( 7 downto 0 ); clka : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 7 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ); web : in STD_LOGIC_VECTOR ( 0 to 0 ); ena : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \FrameBuffer_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width"; end \FrameBuffer_blk_mem_gen_prim_width__parameterized1\; architecture STRUCTURE of \FrameBuffer_blk_mem_gen_prim_width__parameterized1\ is begin \prim_init.ram\: entity work.\FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized1\ port map ( DOADO(7 downto 0) => DOADO(7 downto 0), DOBDO(7 downto 0) => DOBDO(7 downto 0), addra(13 downto 0) => addra(13 downto 0), addrb(13 downto 0) => addrb(13 downto 0), clka => clka, clkb => clkb, dina(7 downto 0) => dina(7 downto 0), dinb(7 downto 0) => dinb(7 downto 0), ena => ena, wea(0) => wea(0), web(0) => web(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity FrameBuffer_blk_mem_gen_generic_cstr is port ( doutb : out STD_LOGIC_VECTOR ( 7 downto 0 ); douta : out STD_LOGIC_VECTOR ( 7 downto 0 ); clka : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 7 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ); web : in STD_LOGIC_VECTOR ( 0 to 0 ); ena : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr"; end FrameBuffer_blk_mem_gen_generic_cstr; architecture STRUCTURE of FrameBuffer_blk_mem_gen_generic_cstr is signal ram_douta : STD_LOGIC_VECTOR ( 7 downto 0 ); signal ram_doutb : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \ramloop[1].ram.r_n_0\ : STD_LOGIC; signal \ramloop[1].ram.r_n_1\ : STD_LOGIC; signal \ramloop[1].ram.r_n_10\ : STD_LOGIC; signal \ramloop[1].ram.r_n_11\ : STD_LOGIC; signal \ramloop[1].ram.r_n_12\ : STD_LOGIC; signal \ramloop[1].ram.r_n_13\ : STD_LOGIC; signal \ramloop[1].ram.r_n_14\ : STD_LOGIC; signal \ramloop[1].ram.r_n_15\ : STD_LOGIC; signal \ramloop[1].ram.r_n_2\ : STD_LOGIC; signal \ramloop[1].ram.r_n_3\ : STD_LOGIC; signal \ramloop[1].ram.r_n_4\ : STD_LOGIC; signal \ramloop[1].ram.r_n_5\ : STD_LOGIC; signal \ramloop[1].ram.r_n_6\ : STD_LOGIC; signal \ramloop[1].ram.r_n_7\ : STD_LOGIC; signal \ramloop[1].ram.r_n_8\ : STD_LOGIC; signal \ramloop[1].ram.r_n_9\ : STD_LOGIC; signal \ramloop[2].ram.r_n_0\ : STD_LOGIC; signal \ramloop[2].ram.r_n_1\ : STD_LOGIC; signal \ramloop[2].ram.r_n_10\ : STD_LOGIC; signal \ramloop[2].ram.r_n_11\ : STD_LOGIC; signal \ramloop[2].ram.r_n_12\ : STD_LOGIC; signal \ramloop[2].ram.r_n_13\ : STD_LOGIC; signal \ramloop[2].ram.r_n_14\ : STD_LOGIC; signal \ramloop[2].ram.r_n_15\ : STD_LOGIC; signal \ramloop[2].ram.r_n_2\ : STD_LOGIC; signal \ramloop[2].ram.r_n_3\ : STD_LOGIC; signal \ramloop[2].ram.r_n_4\ : STD_LOGIC; signal \ramloop[2].ram.r_n_5\ : STD_LOGIC; signal \ramloop[2].ram.r_n_6\ : STD_LOGIC; signal \ramloop[2].ram.r_n_7\ : STD_LOGIC; signal \ramloop[2].ram.r_n_8\ : STD_LOGIC; signal \ramloop[2].ram.r_n_9\ : STD_LOGIC; begin \has_mux_a.A\: entity work.FrameBuffer_blk_mem_gen_mux port map ( \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(7) => \ramloop[1].ram.r_n_0\, \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(6) => \ramloop[1].ram.r_n_1\, \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(5) => \ramloop[1].ram.r_n_2\, \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(4) => \ramloop[1].ram.r_n_3\, \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3) => \ramloop[1].ram.r_n_4\, \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(2) => \ramloop[1].ram.r_n_5\, \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(1) => \ramloop[1].ram.r_n_6\, \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(0) => \ramloop[1].ram.r_n_7\, \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7 downto 0) => ram_douta(7 downto 0), DOADO(7) => \ramloop[2].ram.r_n_0\, DOADO(6) => \ramloop[2].ram.r_n_1\, DOADO(5) => \ramloop[2].ram.r_n_2\, DOADO(4) => \ramloop[2].ram.r_n_3\, DOADO(3) => \ramloop[2].ram.r_n_4\, DOADO(2) => \ramloop[2].ram.r_n_5\, DOADO(1) => \ramloop[2].ram.r_n_6\, DOADO(0) => \ramloop[2].ram.r_n_7\, addra(2 downto 0) => addra(13 downto 11), clka => clka, douta(7 downto 0) => douta(7 downto 0), ena => ena ); \has_mux_b.B\: entity work.\FrameBuffer_blk_mem_gen_mux__parameterized0\ port map ( \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(7) => \ramloop[1].ram.r_n_8\, \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(6) => \ramloop[1].ram.r_n_9\, \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(5) => \ramloop[1].ram.r_n_10\, \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(4) => \ramloop[1].ram.r_n_11\, \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(3) => \ramloop[1].ram.r_n_12\, \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(2) => \ramloop[1].ram.r_n_13\, \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(1) => \ramloop[1].ram.r_n_14\, \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram\(0) => \ramloop[1].ram.r_n_15\, \DEVICE_7SERIES.NO_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.ram_0\(7 downto 0) => ram_doutb(7 downto 0), DOBDO(7) => \ramloop[2].ram.r_n_8\, DOBDO(6) => \ramloop[2].ram.r_n_9\, DOBDO(5) => \ramloop[2].ram.r_n_10\, DOBDO(4) => \ramloop[2].ram.r_n_11\, DOBDO(3) => \ramloop[2].ram.r_n_12\, DOBDO(2) => \ramloop[2].ram.r_n_13\, DOBDO(1) => \ramloop[2].ram.r_n_14\, DOBDO(0) => \ramloop[2].ram.r_n_15\, addrb(2 downto 0) => addrb(13 downto 11), clkb => clkb, doutb(7 downto 0) => doutb(7 downto 0) ); \ramloop[0].ram.r\: entity work.FrameBuffer_blk_mem_gen_prim_width port map ( addra(13 downto 0) => addra(13 downto 0), addrb(13 downto 0) => addrb(13 downto 0), clka => clka, clkb => clkb, dina(7 downto 0) => dina(7 downto 0), dinb(7 downto 0) => dinb(7 downto 0), \douta[7]\(7 downto 0) => ram_douta(7 downto 0), \doutb[7]\(7 downto 0) => ram_doutb(7 downto 0), ena => ena, wea(0) => wea(0), web(0) => web(0) ); \ramloop[1].ram.r\: entity work.\FrameBuffer_blk_mem_gen_prim_width__parameterized0\ port map ( addra(13 downto 0) => addra(13 downto 0), addrb(13 downto 0) => addrb(13 downto 0), clka => clka, clkb => clkb, dina(7 downto 0) => dina(7 downto 0), dinb(7 downto 0) => dinb(7 downto 0), \douta[7]\(7) => \ramloop[1].ram.r_n_0\, \douta[7]\(6) => \ramloop[1].ram.r_n_1\, \douta[7]\(5) => \ramloop[1].ram.r_n_2\, \douta[7]\(4) => \ramloop[1].ram.r_n_3\, \douta[7]\(3) => \ramloop[1].ram.r_n_4\, \douta[7]\(2) => \ramloop[1].ram.r_n_5\, \douta[7]\(1) => \ramloop[1].ram.r_n_6\, \douta[7]\(0) => \ramloop[1].ram.r_n_7\, \doutb[7]\(7) => \ramloop[1].ram.r_n_8\, \doutb[7]\(6) => \ramloop[1].ram.r_n_9\, \doutb[7]\(5) => \ramloop[1].ram.r_n_10\, \doutb[7]\(4) => \ramloop[1].ram.r_n_11\, \doutb[7]\(3) => \ramloop[1].ram.r_n_12\, \doutb[7]\(2) => \ramloop[1].ram.r_n_13\, \doutb[7]\(1) => \ramloop[1].ram.r_n_14\, \doutb[7]\(0) => \ramloop[1].ram.r_n_15\, ena => ena, wea(0) => wea(0), web(0) => web(0) ); \ramloop[2].ram.r\: entity work.\FrameBuffer_blk_mem_gen_prim_width__parameterized1\ port map ( DOADO(7) => \ramloop[2].ram.r_n_0\, DOADO(6) => \ramloop[2].ram.r_n_1\, DOADO(5) => \ramloop[2].ram.r_n_2\, DOADO(4) => \ramloop[2].ram.r_n_3\, DOADO(3) => \ramloop[2].ram.r_n_4\, DOADO(2) => \ramloop[2].ram.r_n_5\, DOADO(1) => \ramloop[2].ram.r_n_6\, DOADO(0) => \ramloop[2].ram.r_n_7\, DOBDO(7) => \ramloop[2].ram.r_n_8\, DOBDO(6) => \ramloop[2].ram.r_n_9\, DOBDO(5) => \ramloop[2].ram.r_n_10\, DOBDO(4) => \ramloop[2].ram.r_n_11\, DOBDO(3) => \ramloop[2].ram.r_n_12\, DOBDO(2) => \ramloop[2].ram.r_n_13\, DOBDO(1) => \ramloop[2].ram.r_n_14\, DOBDO(0) => \ramloop[2].ram.r_n_15\, addra(13 downto 0) => addra(13 downto 0), addrb(13 downto 0) => addrb(13 downto 0), clka => clka, clkb => clkb, dina(7 downto 0) => dina(7 downto 0), dinb(7 downto 0) => dinb(7 downto 0), ena => ena, wea(0) => wea(0), web(0) => web(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity FrameBuffer_blk_mem_gen_top is port ( doutb : out STD_LOGIC_VECTOR ( 7 downto 0 ); douta : out STD_LOGIC_VECTOR ( 7 downto 0 ); clka : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 7 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ); web : in STD_LOGIC_VECTOR ( 0 to 0 ); ena : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_top : entity is "blk_mem_gen_top"; end FrameBuffer_blk_mem_gen_top; architecture STRUCTURE of FrameBuffer_blk_mem_gen_top is begin \valid.cstr\: entity work.FrameBuffer_blk_mem_gen_generic_cstr port map ( addra(13 downto 0) => addra(13 downto 0), addrb(13 downto 0) => addrb(13 downto 0), clka => clka, clkb => clkb, dina(7 downto 0) => dina(7 downto 0), dinb(7 downto 0) => dinb(7 downto 0), douta(7 downto 0) => douta(7 downto 0), doutb(7 downto 0) => doutb(7 downto 0), ena => ena, wea(0) => wea(0), web(0) => web(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity FrameBuffer_blk_mem_gen_v8_3_1_synth is port ( doutb : out STD_LOGIC_VECTOR ( 7 downto 0 ); douta : out STD_LOGIC_VECTOR ( 7 downto 0 ); clka : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 7 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ); web : in STD_LOGIC_VECTOR ( 0 to 0 ); ena : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_v8_3_1_synth : entity is "blk_mem_gen_v8_3_1_synth"; end FrameBuffer_blk_mem_gen_v8_3_1_synth; architecture STRUCTURE of FrameBuffer_blk_mem_gen_v8_3_1_synth is begin \gnativebmg.native_blk_mem_gen\: entity work.FrameBuffer_blk_mem_gen_top port map ( addra(13 downto 0) => addra(13 downto 0), addrb(13 downto 0) => addrb(13 downto 0), clka => clka, clkb => clkb, dina(7 downto 0) => dina(7 downto 0), dinb(7 downto 0) => dinb(7 downto 0), douta(7 downto 0) => douta(7 downto 0), doutb(7 downto 0) => doutb(7 downto 0), ena => ena, wea(0) => wea(0), web(0) => web(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity FrameBuffer_blk_mem_gen_v8_3_1 is port ( clka : in STD_LOGIC; rsta : in STD_LOGIC; ena : in STD_LOGIC; regcea : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); douta : out STD_LOGIC_VECTOR ( 7 downto 0 ); clkb : in STD_LOGIC; rstb : in STD_LOGIC; enb : in STD_LOGIC; regceb : in STD_LOGIC; web : in STD_LOGIC_VECTOR ( 0 to 0 ); addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 7 downto 0 ); doutb : out STD_LOGIC_VECTOR ( 7 downto 0 ); injectsbiterr : in STD_LOGIC; injectdbiterr : in STD_LOGIC; eccpipece : in STD_LOGIC; sbiterr : out STD_LOGIC; dbiterr : out STD_LOGIC; rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 ); sleep : in STD_LOGIC; deepsleep : in STD_LOGIC; shutdown : in STD_LOGIC; rsta_busy : out STD_LOGIC; rstb_busy : out STD_LOGIC; s_aclk : in STD_LOGIC; s_aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; s_axi_injectsbiterr : in STD_LOGIC; s_axi_injectdbiterr : in STD_LOGIC; s_axi_sbiterr : out STD_LOGIC; s_axi_dbiterr : out STD_LOGIC; s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 ) ); attribute C_ADDRA_WIDTH : integer; attribute C_ADDRA_WIDTH of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 14; attribute C_ADDRB_WIDTH : integer; attribute C_ADDRB_WIDTH of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 14; attribute C_ALGORITHM : integer; attribute C_ALGORITHM of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 4; attribute C_AXI_SLAVE_TYPE : integer; attribute C_AXI_SLAVE_TYPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_AXI_TYPE : integer; attribute C_AXI_TYPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1; attribute C_BYTE_SIZE : integer; attribute C_BYTE_SIZE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 8; attribute C_COMMON_CLK : integer; attribute C_COMMON_CLK of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_COUNT_18K_BRAM : string; attribute C_COUNT_18K_BRAM of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "1"; attribute C_COUNT_36K_BRAM : string; attribute C_COUNT_36K_BRAM of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "2"; attribute C_CTRL_ECC_ALGO : string; attribute C_CTRL_ECC_ALGO of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "NONE"; attribute C_DEFAULT_DATA : string; attribute C_DEFAULT_DATA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "0"; attribute C_DISABLE_WARN_BHV_COLL : integer; attribute C_DISABLE_WARN_BHV_COLL of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_DISABLE_WARN_BHV_RANGE : integer; attribute C_DISABLE_WARN_BHV_RANGE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_ELABORATION_DIR : string; attribute C_ELABORATION_DIR of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "./"; attribute C_ENABLE_32BIT_ADDRESS : integer; attribute C_ENABLE_32BIT_ADDRESS of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_EN_DEEPSLEEP_PIN : integer; attribute C_EN_DEEPSLEEP_PIN of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_EN_ECC_PIPE : integer; attribute C_EN_ECC_PIPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_EN_RDADDRA_CHG : integer; attribute C_EN_RDADDRA_CHG of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_EN_RDADDRB_CHG : integer; attribute C_EN_RDADDRB_CHG of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_EN_SAFETY_CKT : integer; attribute C_EN_SAFETY_CKT of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_EN_SHUTDOWN_PIN : integer; attribute C_EN_SHUTDOWN_PIN of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_EN_SLEEP_PIN : integer; attribute C_EN_SLEEP_PIN of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_EST_POWER_SUMMARY : string; attribute C_EST_POWER_SUMMARY of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "Estimated Power for IP : 4.61856 mW"; attribute C_FAMILY : string; attribute C_FAMILY of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "artix7"; attribute C_HAS_AXI_ID : integer; attribute C_HAS_AXI_ID of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_ENA : integer; attribute C_HAS_ENA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1; attribute C_HAS_ENB : integer; attribute C_HAS_ENB of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_INJECTERR : integer; attribute C_HAS_INJECTERR of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_MEM_OUTPUT_REGS_A : integer; attribute C_HAS_MEM_OUTPUT_REGS_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_MEM_OUTPUT_REGS_B : integer; attribute C_HAS_MEM_OUTPUT_REGS_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1; attribute C_HAS_MUX_OUTPUT_REGS_A : integer; attribute C_HAS_MUX_OUTPUT_REGS_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_MUX_OUTPUT_REGS_B : integer; attribute C_HAS_MUX_OUTPUT_REGS_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_REGCEA : integer; attribute C_HAS_REGCEA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_REGCEB : integer; attribute C_HAS_REGCEB of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_RSTA : integer; attribute C_HAS_RSTA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_RSTB : integer; attribute C_HAS_RSTB of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; attribute C_HAS_SOFTECC_INPUT_REGS_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; attribute C_HAS_SOFTECC_OUTPUT_REGS_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_INITA_VAL : string; attribute C_INITA_VAL of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "0"; attribute C_INITB_VAL : string; attribute C_INITB_VAL of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "0"; attribute C_INIT_FILE : string; attribute C_INIT_FILE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "FrameBuffer.mem"; attribute C_INIT_FILE_NAME : string; attribute C_INIT_FILE_NAME of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "FrameBuffer.mif"; attribute C_INTERFACE_TYPE : integer; attribute C_INTERFACE_TYPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_LOAD_INIT_FILE : integer; attribute C_LOAD_INIT_FILE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1; attribute C_MEM_TYPE : integer; attribute C_MEM_TYPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 2; attribute C_MUX_PIPELINE_STAGES : integer; attribute C_MUX_PIPELINE_STAGES of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_PRIM_TYPE : integer; attribute C_PRIM_TYPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1; attribute C_READ_DEPTH_A : integer; attribute C_READ_DEPTH_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 10240; attribute C_READ_DEPTH_B : integer; attribute C_READ_DEPTH_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 10240; attribute C_READ_WIDTH_A : integer; attribute C_READ_WIDTH_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 8; attribute C_READ_WIDTH_B : integer; attribute C_READ_WIDTH_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 8; attribute C_RSTRAM_A : integer; attribute C_RSTRAM_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_RSTRAM_B : integer; attribute C_RSTRAM_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_RST_PRIORITY_A : string; attribute C_RST_PRIORITY_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "CE"; attribute C_RST_PRIORITY_B : string; attribute C_RST_PRIORITY_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "CE"; attribute C_SIM_COLLISION_CHECK : string; attribute C_SIM_COLLISION_CHECK of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "ALL"; attribute C_USE_BRAM_BLOCK : integer; attribute C_USE_BRAM_BLOCK of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_USE_BYTE_WEA : integer; attribute C_USE_BYTE_WEA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1; attribute C_USE_BYTE_WEB : integer; attribute C_USE_BYTE_WEB of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1; attribute C_USE_DEFAULT_DATA : integer; attribute C_USE_DEFAULT_DATA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_USE_ECC : integer; attribute C_USE_ECC of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_USE_SOFTECC : integer; attribute C_USE_SOFTECC of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_USE_URAM : integer; attribute C_USE_URAM of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_WEA_WIDTH : integer; attribute C_WEA_WIDTH of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1; attribute C_WEB_WIDTH : integer; attribute C_WEB_WIDTH of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1; attribute C_WRITE_DEPTH_A : integer; attribute C_WRITE_DEPTH_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 10240; attribute C_WRITE_DEPTH_B : integer; attribute C_WRITE_DEPTH_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 10240; attribute C_WRITE_MODE_A : string; attribute C_WRITE_MODE_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "WRITE_FIRST"; attribute C_WRITE_MODE_B : string; attribute C_WRITE_MODE_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "WRITE_FIRST"; attribute C_WRITE_WIDTH_A : integer; attribute C_WRITE_WIDTH_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 8; attribute C_WRITE_WIDTH_B : integer; attribute C_WRITE_WIDTH_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 8; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "artix7"; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "blk_mem_gen_v8_3_1"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "yes"; end FrameBuffer_blk_mem_gen_v8_3_1; architecture STRUCTURE of FrameBuffer_blk_mem_gen_v8_3_1 is signal \<const0>\ : STD_LOGIC; begin dbiterr <= \<const0>\; rdaddrecc(13) <= \<const0>\; rdaddrecc(12) <= \<const0>\; rdaddrecc(11) <= \<const0>\; rdaddrecc(10) <= \<const0>\; rdaddrecc(9) <= \<const0>\; rdaddrecc(8) <= \<const0>\; rdaddrecc(7) <= \<const0>\; rdaddrecc(6) <= \<const0>\; rdaddrecc(5) <= \<const0>\; rdaddrecc(4) <= \<const0>\; rdaddrecc(3) <= \<const0>\; rdaddrecc(2) <= \<const0>\; rdaddrecc(1) <= \<const0>\; rdaddrecc(0) <= \<const0>\; rsta_busy <= \<const0>\; rstb_busy <= \<const0>\; s_axi_arready <= \<const0>\; s_axi_awready <= \<const0>\; s_axi_bid(3) <= \<const0>\; s_axi_bid(2) <= \<const0>\; s_axi_bid(1) <= \<const0>\; s_axi_bid(0) <= \<const0>\; s_axi_bresp(1) <= \<const0>\; s_axi_bresp(0) <= \<const0>\; s_axi_bvalid <= \<const0>\; s_axi_dbiterr <= \<const0>\; s_axi_rdaddrecc(13) <= \<const0>\; s_axi_rdaddrecc(12) <= \<const0>\; s_axi_rdaddrecc(11) <= \<const0>\; s_axi_rdaddrecc(10) <= \<const0>\; s_axi_rdaddrecc(9) <= \<const0>\; s_axi_rdaddrecc(8) <= \<const0>\; s_axi_rdaddrecc(7) <= \<const0>\; s_axi_rdaddrecc(6) <= \<const0>\; s_axi_rdaddrecc(5) <= \<const0>\; s_axi_rdaddrecc(4) <= \<const0>\; s_axi_rdaddrecc(3) <= \<const0>\; s_axi_rdaddrecc(2) <= \<const0>\; s_axi_rdaddrecc(1) <= \<const0>\; s_axi_rdaddrecc(0) <= \<const0>\; s_axi_rdata(7) <= \<const0>\; s_axi_rdata(6) <= \<const0>\; s_axi_rdata(5) <= \<const0>\; s_axi_rdata(4) <= \<const0>\; s_axi_rdata(3) <= \<const0>\; s_axi_rdata(2) <= \<const0>\; s_axi_rdata(1) <= \<const0>\; s_axi_rdata(0) <= \<const0>\; s_axi_rid(3) <= \<const0>\; s_axi_rid(2) <= \<const0>\; s_axi_rid(1) <= \<const0>\; s_axi_rid(0) <= \<const0>\; s_axi_rlast <= \<const0>\; s_axi_rresp(1) <= \<const0>\; s_axi_rresp(0) <= \<const0>\; s_axi_rvalid <= \<const0>\; s_axi_sbiterr <= \<const0>\; s_axi_wready <= \<const0>\; sbiterr <= \<const0>\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); inst_blk_mem_gen: entity work.FrameBuffer_blk_mem_gen_v8_3_1_synth port map ( addra(13 downto 0) => addra(13 downto 0), addrb(13 downto 0) => addrb(13 downto 0), clka => clka, clkb => clkb, dina(7 downto 0) => dina(7 downto 0), dinb(7 downto 0) => dinb(7 downto 0), douta(7 downto 0) => douta(7 downto 0), doutb(7 downto 0) => doutb(7 downto 0), ena => ena, wea(0) => wea(0), web(0) => web(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity FrameBuffer is port ( clka : in STD_LOGIC; ena : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); douta : out STD_LOGIC_VECTOR ( 7 downto 0 ); clkb : in STD_LOGIC; web : in STD_LOGIC_VECTOR ( 0 to 0 ); addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 7 downto 0 ); doutb : out STD_LOGIC_VECTOR ( 7 downto 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of FrameBuffer : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of FrameBuffer : entity is "FrameBuffer,blk_mem_gen_v8_3_1,{}"; attribute core_generation_info : string; attribute core_generation_info of FrameBuffer : entity is "FrameBuffer,blk_mem_gen_v8_3_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=2,C_BYTE_SIZE=8,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=FrameBuffer.mif,C_INIT_FILE=FrameBuffer.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=1,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=10240,C_READ_DEPTH_A=10240,C_ADDRA_WIDTH=14,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=1,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=10240,C_READ_DEPTH_B=10240,C_ADDRB_WIDTH=14,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=1,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=2,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 4.61856 mW}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of FrameBuffer : entity is "yes"; attribute x_core_info : string; attribute x_core_info of FrameBuffer : entity is "blk_mem_gen_v8_3_1,Vivado 2015.4"; end FrameBuffer; architecture STRUCTURE of FrameBuffer is signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC; signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC; signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 ); signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 ); signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute C_ADDRA_WIDTH : integer; attribute C_ADDRA_WIDTH of U0 : label is 14; attribute C_ADDRB_WIDTH : integer; attribute C_ADDRB_WIDTH of U0 : label is 14; attribute C_ALGORITHM : integer; attribute C_ALGORITHM of U0 : label is 1; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of U0 : label is 4; attribute C_AXI_SLAVE_TYPE : integer; attribute C_AXI_SLAVE_TYPE of U0 : label is 0; attribute C_AXI_TYPE : integer; attribute C_AXI_TYPE of U0 : label is 1; attribute C_BYTE_SIZE : integer; attribute C_BYTE_SIZE of U0 : label is 8; attribute C_COMMON_CLK : integer; attribute C_COMMON_CLK of U0 : label is 0; attribute C_COUNT_18K_BRAM : string; attribute C_COUNT_18K_BRAM of U0 : label is "1"; attribute C_COUNT_36K_BRAM : string; attribute C_COUNT_36K_BRAM of U0 : label is "2"; attribute C_CTRL_ECC_ALGO : string; attribute C_CTRL_ECC_ALGO of U0 : label is "NONE"; attribute C_DEFAULT_DATA : string; attribute C_DEFAULT_DATA of U0 : label is "0"; attribute C_DISABLE_WARN_BHV_COLL : integer; attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0; attribute C_DISABLE_WARN_BHV_RANGE : integer; attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0; attribute C_ELABORATION_DIR : string; attribute C_ELABORATION_DIR of U0 : label is "./"; attribute C_ENABLE_32BIT_ADDRESS : integer; attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0; attribute C_EN_DEEPSLEEP_PIN : integer; attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0; attribute C_EN_ECC_PIPE : integer; attribute C_EN_ECC_PIPE of U0 : label is 0; attribute C_EN_RDADDRA_CHG : integer; attribute C_EN_RDADDRA_CHG of U0 : label is 0; attribute C_EN_RDADDRB_CHG : integer; attribute C_EN_RDADDRB_CHG of U0 : label is 0; attribute C_EN_SAFETY_CKT : integer; attribute C_EN_SAFETY_CKT of U0 : label is 0; attribute C_EN_SHUTDOWN_PIN : integer; attribute C_EN_SHUTDOWN_PIN of U0 : label is 0; attribute C_EN_SLEEP_PIN : integer; attribute C_EN_SLEEP_PIN of U0 : label is 0; attribute C_EST_POWER_SUMMARY : string; attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 4.61856 mW"; attribute C_FAMILY : string; attribute C_FAMILY of U0 : label is "artix7"; attribute C_HAS_AXI_ID : integer; attribute C_HAS_AXI_ID of U0 : label is 0; attribute C_HAS_ENA : integer; attribute C_HAS_ENA of U0 : label is 1; attribute C_HAS_ENB : integer; attribute C_HAS_ENB of U0 : label is 0; attribute C_HAS_INJECTERR : integer; attribute C_HAS_INJECTERR of U0 : label is 0; attribute C_HAS_MEM_OUTPUT_REGS_A : integer; attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0; attribute C_HAS_MEM_OUTPUT_REGS_B : integer; attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 1; attribute C_HAS_MUX_OUTPUT_REGS_A : integer; attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0; attribute C_HAS_MUX_OUTPUT_REGS_B : integer; attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0; attribute C_HAS_REGCEA : integer; attribute C_HAS_REGCEA of U0 : label is 0; attribute C_HAS_REGCEB : integer; attribute C_HAS_REGCEB of U0 : label is 0; attribute C_HAS_RSTA : integer; attribute C_HAS_RSTA of U0 : label is 0; attribute C_HAS_RSTB : integer; attribute C_HAS_RSTB of U0 : label is 0; attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0; attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0; attribute C_INITA_VAL : string; attribute C_INITA_VAL of U0 : label is "0"; attribute C_INITB_VAL : string; attribute C_INITB_VAL of U0 : label is "0"; attribute C_INIT_FILE : string; attribute C_INIT_FILE of U0 : label is "FrameBuffer.mem"; attribute C_INIT_FILE_NAME : string; attribute C_INIT_FILE_NAME of U0 : label is "FrameBuffer.mif"; attribute C_INTERFACE_TYPE : integer; attribute C_INTERFACE_TYPE of U0 : label is 0; attribute C_LOAD_INIT_FILE : integer; attribute C_LOAD_INIT_FILE of U0 : label is 1; attribute C_MEM_TYPE : integer; attribute C_MEM_TYPE of U0 : label is 2; attribute C_MUX_PIPELINE_STAGES : integer; attribute C_MUX_PIPELINE_STAGES of U0 : label is 0; attribute C_PRIM_TYPE : integer; attribute C_PRIM_TYPE of U0 : label is 1; attribute C_READ_DEPTH_A : integer; attribute C_READ_DEPTH_A of U0 : label is 10240; attribute C_READ_DEPTH_B : integer; attribute C_READ_DEPTH_B of U0 : label is 10240; attribute C_READ_WIDTH_A : integer; attribute C_READ_WIDTH_A of U0 : label is 8; attribute C_READ_WIDTH_B : integer; attribute C_READ_WIDTH_B of U0 : label is 8; attribute C_RSTRAM_A : integer; attribute C_RSTRAM_A of U0 : label is 0; attribute C_RSTRAM_B : integer; attribute C_RSTRAM_B of U0 : label is 0; attribute C_RST_PRIORITY_A : string; attribute C_RST_PRIORITY_A of U0 : label is "CE"; attribute C_RST_PRIORITY_B : string; attribute C_RST_PRIORITY_B of U0 : label is "CE"; attribute C_SIM_COLLISION_CHECK : string; attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL"; attribute C_USE_BRAM_BLOCK : integer; attribute C_USE_BRAM_BLOCK of U0 : label is 0; attribute C_USE_BYTE_WEA : integer; attribute C_USE_BYTE_WEA of U0 : label is 1; attribute C_USE_BYTE_WEB : integer; attribute C_USE_BYTE_WEB of U0 : label is 1; attribute C_USE_DEFAULT_DATA : integer; attribute C_USE_DEFAULT_DATA of U0 : label is 0; attribute C_USE_ECC : integer; attribute C_USE_ECC of U0 : label is 0; attribute C_USE_SOFTECC : integer; attribute C_USE_SOFTECC of U0 : label is 0; attribute C_USE_URAM : integer; attribute C_USE_URAM of U0 : label is 0; attribute C_WEA_WIDTH : integer; attribute C_WEA_WIDTH of U0 : label is 1; attribute C_WEB_WIDTH : integer; attribute C_WEB_WIDTH of U0 : label is 1; attribute C_WRITE_DEPTH_A : integer; attribute C_WRITE_DEPTH_A of U0 : label is 10240; attribute C_WRITE_DEPTH_B : integer; attribute C_WRITE_DEPTH_B of U0 : label is 10240; attribute C_WRITE_MODE_A : string; attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST"; attribute C_WRITE_MODE_B : string; attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST"; attribute C_WRITE_WIDTH_A : integer; attribute C_WRITE_WIDTH_A of U0 : label is 8; attribute C_WRITE_WIDTH_B : integer; attribute C_WRITE_WIDTH_B of U0 : label is 8; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of U0 : label is "artix7"; attribute DONT_TOUCH : boolean; attribute DONT_TOUCH of U0 : label is std.standard.true; attribute downgradeipidentifiedwarnings of U0 : label is "yes"; begin U0: entity work.FrameBuffer_blk_mem_gen_v8_3_1 port map ( addra(13 downto 0) => addra(13 downto 0), addrb(13 downto 0) => addrb(13 downto 0), clka => clka, clkb => clkb, dbiterr => NLW_U0_dbiterr_UNCONNECTED, deepsleep => '0', dina(7 downto 0) => dina(7 downto 0), dinb(7 downto 0) => dinb(7 downto 0), douta(7 downto 0) => douta(7 downto 0), doutb(7 downto 0) => doutb(7 downto 0), eccpipece => '0', ena => ena, enb => '0', injectdbiterr => '0', injectsbiterr => '0', rdaddrecc(13 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(13 downto 0), regcea => '0', regceb => '0', rsta => '0', rsta_busy => NLW_U0_rsta_busy_UNCONNECTED, rstb => '0', rstb_busy => NLW_U0_rstb_busy_UNCONNECTED, s_aclk => '0', s_aresetn => '0', s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000", s_axi_arburst(1 downto 0) => B"00", s_axi_arid(3 downto 0) => B"0000", s_axi_arlen(7 downto 0) => B"00000000", s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED, s_axi_arsize(2 downto 0) => B"000", s_axi_arvalid => '0', s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000", s_axi_awburst(1 downto 0) => B"00", s_axi_awid(3 downto 0) => B"0000", s_axi_awlen(7 downto 0) => B"00000000", s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED, s_axi_awsize(2 downto 0) => B"000", s_axi_awvalid => '0', s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0), s_axi_bready => '0', s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0), s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED, s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED, s_axi_injectdbiterr => '0', s_axi_injectsbiterr => '0', s_axi_rdaddrecc(13 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(13 downto 0), s_axi_rdata(7 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(7 downto 0), s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0), s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED, s_axi_rready => '0', s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0), s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED, s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED, s_axi_wdata(7 downto 0) => B"00000000", s_axi_wlast => '0', s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED, s_axi_wstrb(0) => '0', s_axi_wvalid => '0', sbiterr => NLW_U0_sbiterr_UNCONNECTED, shutdown => '0', sleep => '0', wea(0) => wea(0), web(0) => web(0) ); end STRUCTURE;

mit

huahu/zenturio-editor

public/vendor/ace-builds/kitchen-sink/docs/vhdl.vhd

472

830

library IEEE user IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity COUNT16 is port ( cOut :out std_logic_vector(15 downto 0); -- counter output clkEn :in std_logic; -- count enable clk :in std_logic; -- clock input rst :in std_logic -- reset input ); end entity; architecture count_rtl of COUNT16 is signal count :std_logic_vector (15 downto 0); begin process (clk, rst) begin if(rst = '1') then count <= (others=>'0'); elsif(rising_edge(clk)) then if(clkEn = '1') then count <= count + 1; end if; end if; end process; cOut <= count; end architecture;

mit

whitef0x0/EECE353-Lab5

drawline.vhd

1

4263

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity drawline is port(CLK : in std_logic; RST : in std_logic; DRAW : in std_logic x_start : in std_logic_vector(7 downto 0); y_start : in std_logic_vector(7 downto 0); x_end : in std_logic_vector(7 downto 0); y_end : in std_logic_vector(7 downto 0); line_color : in std_logic_vector(2 downto 0); VGA_R, VGA_G, VGA_B : out std_logic_vector(9 downto 0); -- The outs go to VGA controller VGA_HS : out std_logic; VGA_VS : out std_logic; VGA_BLANK : out std_logic; VGA_SYNC : out std_logic; VGA_CLK : out std_logic); end drawline; architecture rtl of drawline is -- Component from the Verilog file: vga_adapter.v component vga_adapter generic(RESOLUTION : string); port ( resetn : in std_logic; clock : in std_logic; colour : in std_logic_vector(2 downto 0); x : in std_logic_vector(7 downto 0); y : in std_logic_vector(6 downto 0); plot : in std_logic; VGA_R, VGA_G, VGA_B : out std_logic_vector(9 downto 0); VGA_HS, VGA_VS, VGA_BLANK, VGA_SYNC, VGA_CLK : out std_logic); end component; component fsm_line is PORT ( clock : IN STD_LOGIC; resetb : IN STD_LOGIC; xdone, ydone, ldone : IN STD_LOGIC; sw : IN STD_LOGIC_VECTOR(17 downto 0); draw : IN STD_LOGIC; resetx, resety, incr_y, incr_x, plot, initl, drawl : OUT STD_LOGIC; colour : OUT STD_LOGIC_VECTOR(2 downto 0); x : OUT STD_LOGIC_VECTOR(7 downto 0); y : OUT STD_LOGIC_VECTOR(6 downto 0); ledg : OUT STD_LOGIC_VECTOR(7 downto 0) ); end component; component datapath_line is PORT ( clock : IN STD_LOGIC; resetb : IN STD_LOGIC; resetx, resety, incr_y, incr_x, initl, drawl : IN STD_LOGIC; x : OUT STD_LOGIC_VECTOR(7 downto 0); y : OUT STD_LOGIC_VECTOR(6 downto 0); x0in : IN STD_LOGIC_VECTOR(7 downto 0); -- x1 y0in : IN STD_LOGIC_VECTOR(6 downto 0); -- y1 x1in : IN STD_LOGIC_VECTOR(7 downto 0); -- x0 y1in : IN STD_LOGIC_VECTOR(6 downto 0); -- y0 xdone, ydone, ldone : OUT STD_LOGIC ); end component; signal s_x : std_logic_vector(7 downto 0) := "00000000"; signal s_y : std_logic_vector(6 downto 0) := "0000000"; signal colour : std_logic_vector(2 downto 0); signal plot : std_logic; signal resety, resetx, initl : std_logic; signal xdone, ydone, ldone : std_logic; signal incr_y, incr_x, drawl : std_logic; signal x_int : std_logic_vector(7 downto 0); signal y_int : std_logic_vector(6 downto 0); begin vga_u0 : vga_adapter generic map(RESOLUTION => "160x120") port map(resetn => RST, clock => CLK, colour => colour, x => s_x, y => s_y, plot => plot, VGA_R => VGA_R, VGA_G => VGA_G, VGA_B => VGA_B, VGA_HS => VGA_HS, VGA_VS => VGA_VS, VGA_BLANK => VGA_BLANK, VGA_SYNC => VGA_SYNC, VGA_CLK => VGA_CLK ); fsm_line0 : fsm_line PORT MAP( clock => CLK, resetb => RST, xdone => xdone, ydone => ydone, ldone => ldone, --sw => SW, draw => DRAW, resetx => resetx, resety => resety, incr_y => incr_y, incr_x => incr_x, plot => plot, initl => initl, drawl => drawl, colour_in => line_color, colour_out => colour, x => x_int, y => y_int, ); datapath_line0 : datapath_line PORT MAP( clock => CLK, resetb => RST, resetx => resetx, resety => resety, initl => initl, drawl => drawl, x => s_x, y => s_y, xin => x_int, yin => y_int, xdone => xdone, ydone => ydone, ldone => ldone, incr_y => incr_y, incr_x => incr_x ); end rtl;

mit

oetr/FPGA-I2C-Slave

txt_util.vhd

4

14508

library ieee; use ieee.std_logic_1164.all; use std.textio.all; package txt_util is -- prints a message to the screen procedure print(text: string); -- prints the message when active -- useful for debug switches procedure print(active: boolean; text: string); -- converts std_logic into a character function chr(sl: std_logic) return character; -- converts std_logic into a string (1 to 1) function str(sl: std_logic) return string; -- converts std_logic_vector into a string (binary base) function str(slv: std_logic_vector) return string; -- converts boolean into a string function str(b: boolean) return string; -- converts an integer into a single character -- (can also be used for hex conversion and other bases) function chr(int: integer) return character; -- converts integer into string using specified base function str(int: integer; base: integer) return string; -- converts integer to string, using base 10 function str(int: integer) return string; -- convert std_logic_vector into a string in hex format function hstr(slv: std_logic_vector) return string; -- functions to manipulate strings ----------------------------------- -- convert a character to upper case function to_upper(c: character) return character; -- convert a character to lower case function to_lower(c: character) return character; -- convert a string to upper case function to_upper(s: string) return string; -- convert a string to lower case function to_lower(s: string) return string; -- functions to convert strings into other formats -------------------------------------------------- -- converts a character into std_logic function to_std_logic(c: character) return std_logic; -- converts a string into std_logic_vector function to_std_logic_vector(s: string) return std_logic_vector; -- file I/O ----------- -- read variable length string from input file procedure str_read(file in_file: TEXT; res_string: out string); -- print string to a file and start new line procedure print(file out_file: TEXT; new_string: in string); -- print character to a file and start new line procedure print(file out_file: TEXT; char: in character); end txt_util; package body txt_util is -- prints text to the screen procedure print(text: string) is variable msg_line: line; begin write(msg_line, text); writeline(output, msg_line); end print; -- prints text to the screen when active procedure print(active: boolean; text: string) is begin if active then print(text); end if; end print; -- converts std_logic into a character function chr(sl: std_logic) return character is variable c: character; begin case sl is when 'U' => c:= 'U'; when 'X' => c:= 'X'; when '0' => c:= '0'; when '1' => c:= '1'; when 'Z' => c:= 'Z'; when 'W' => c:= 'W'; when 'L' => c:= 'L'; when 'H' => c:= 'H'; when '-' => c:= '-'; end case; return c; end chr; -- converts std_logic into a string (1 to 1) function str(sl: std_logic) return string is variable s: string(1 to 1); begin s(1) := chr(sl); return s; end str; -- converts std_logic_vector into a string (binary base) -- (this also takes care of the fact that the range of -- a string is natural while a std_logic_vector may -- have an integer range) function str(slv: std_logic_vector) return string is variable result : string (1 to slv'length); variable r : integer; begin r := 1; for i in slv'range loop result(r) := chr(slv(i)); r := r + 1; end loop; return result; end str; function str(b: boolean) return string is begin if b then return "true"; else return "false"; end if; end str; -- converts an integer into a character -- for 0 to 9 the obvious mapping is used, higher -- values are mapped to the characters A-Z -- (this is usefull for systems with base > 10) -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) function chr(int: integer) return character is variable c: character; begin case int is when 0 => c := '0'; when 1 => c := '1'; when 2 => c := '2'; when 3 => c := '3'; when 4 => c := '4'; when 5 => c := '5'; when 6 => c := '6'; when 7 => c := '7'; when 8 => c := '8'; when 9 => c := '9'; when 10 => c := 'A'; when 11 => c := 'B'; when 12 => c := 'C'; when 13 => c := 'D'; when 14 => c := 'E'; when 15 => c := 'F'; when 16 => c := 'G'; when 17 => c := 'H'; when 18 => c := 'I'; when 19 => c := 'J'; when 20 => c := 'K'; when 21 => c := 'L'; when 22 => c := 'M'; when 23 => c := 'N'; when 24 => c := 'O'; when 25 => c := 'P'; when 26 => c := 'Q'; when 27 => c := 'R'; when 28 => c := 'S'; when 29 => c := 'T'; when 30 => c := 'U'; when 31 => c := 'V'; when 32 => c := 'W'; when 33 => c := 'X'; when 34 => c := 'Y'; when 35 => c := 'Z'; when others => c := '?'; end case; return c; end chr; -- convert integer to string using specified base -- (adapted from Steve Vogwell's posting in comp.lang.vhdl) function str(int: integer; base: integer) return string is variable temp: string(1 to 10); variable num: integer; variable abs_int: integer; variable len: integer := 1; variable power: integer := 1; begin -- bug fix for negative numbers abs_int := abs(int); num := abs_int; while num >= base loop -- Determine how many len := len + 1; -- characters required num := num / base; -- to represent the end loop ; -- number. for i in len downto 1 loop -- Convert the number to temp(i) := chr(abs_int/power mod base); -- a string starting power := power * base; -- with the right hand end loop ; -- side. -- return result and add sign if required if int < 0 then return '-'& temp(1 to len); else return temp(1 to len); end if; end str; -- convert integer to string, using base 10 function str(int: integer) return string is begin return str(int, 10) ; end str; -- converts a std_logic_vector into a hex string. function hstr(slv: std_logic_vector) return string is variable hexlen: integer; variable longslv : std_logic_vector(67 downto 0) := (others => '0'); variable hex : string(1 to 16); variable fourbit : std_logic_vector(3 downto 0); begin hexlen := (slv'left+1)/4; if (slv'left+1) mod 4 /= 0 then hexlen := hexlen + 1; end if; longslv(slv'left downto 0) := slv; for i in (hexlen -1) downto 0 loop fourbit := longslv(((i*4)+3) downto (i*4)); case fourbit is when "0000" => hex(hexlen -I) := '0'; when "0001" => hex(hexlen -I) := '1'; when "0010" => hex(hexlen -I) := '2'; when "0011" => hex(hexlen -I) := '3'; when "0100" => hex(hexlen -I) := '4'; when "0101" => hex(hexlen -I) := '5'; when "0110" => hex(hexlen -I) := '6'; when "0111" => hex(hexlen -I) := '7'; when "1000" => hex(hexlen -I) := '8'; when "1001" => hex(hexlen -I) := '9'; when "1010" => hex(hexlen -I) := 'A'; when "1011" => hex(hexlen -I) := 'B'; when "1100" => hex(hexlen -I) := 'C'; when "1101" => hex(hexlen -I) := 'D'; when "1110" => hex(hexlen -I) := 'E'; when "1111" => hex(hexlen -I) := 'F'; when "ZZZZ" => hex(hexlen -I) := 'z'; when "UUUU" => hex(hexlen -I) := 'u'; when "XXXX" => hex(hexlen -I) := 'x'; when others => hex(hexlen -I) := '?'; end case; end loop; return hex(1 to hexlen); end hstr; -- functions to manipulate strings ----------------------------------- -- convert a character to upper case function to_upper(c: character) return character is variable u: character; begin case c is when 'a' => u := 'A'; when 'b' => u := 'B'; when 'c' => u := 'C'; when 'd' => u := 'D'; when 'e' => u := 'E'; when 'f' => u := 'F'; when 'g' => u := 'G'; when 'h' => u := 'H'; when 'i' => u := 'I'; when 'j' => u := 'J'; when 'k' => u := 'K'; when 'l' => u := 'L'; when 'm' => u := 'M'; when 'n' => u := 'N'; when 'o' => u := 'O'; when 'p' => u := 'P'; when 'q' => u := 'Q'; when 'r' => u := 'R'; when 's' => u := 'S'; when 't' => u := 'T'; when 'u' => u := 'U'; when 'v' => u := 'V'; when 'w' => u := 'W'; when 'x' => u := 'X'; when 'y' => u := 'Y'; when 'z' => u := 'Z'; when others => u := c; end case; return u; end to_upper; -- convert a character to lower case function to_lower(c: character) return character is variable l: character; begin case c is when 'A' => l := 'a'; when 'B' => l := 'b'; when 'C' => l := 'c'; when 'D' => l := 'd'; when 'E' => l := 'e'; when 'F' => l := 'f'; when 'G' => l := 'g'; when 'H' => l := 'h'; when 'I' => l := 'i'; when 'J' => l := 'j'; when 'K' => l := 'k'; when 'L' => l := 'l'; when 'M' => l := 'm'; when 'N' => l := 'n'; when 'O' => l := 'o'; when 'P' => l := 'p'; when 'Q' => l := 'q'; when 'R' => l := 'r'; when 'S' => l := 's'; when 'T' => l := 't'; when 'U' => l := 'u'; when 'V' => l := 'v'; when 'W' => l := 'w'; when 'X' => l := 'x'; when 'Y' => l := 'y'; when 'Z' => l := 'z'; when others => l := c; end case; return l; end to_lower; -- convert a string to upper case function to_upper(s: string) return string is variable uppercase: string (s'range); begin for i in s'range loop uppercase(i):= to_upper(s(i)); end loop; return uppercase; end to_upper; -- convert a string to lower case function to_lower(s: string) return string is variable lowercase: string (s'range); begin for i in s'range loop lowercase(i):= to_lower(s(i)); end loop; return lowercase; end to_lower; -- functions to convert strings into other types -- converts a character into a std_logic function to_std_logic(c: character) return std_logic is variable sl: std_logic; begin case c is when 'U' => sl := 'U'; when 'X' => sl := 'X'; when '0' => sl := '0'; when '1' => sl := '1'; when 'Z' => sl := 'Z'; when 'W' => sl := 'W'; when 'L' => sl := 'L'; when 'H' => sl := 'H'; when '-' => sl := '-'; when others => sl := 'X'; end case; return sl; end to_std_logic; -- converts a string into std_logic_vector function to_std_logic_vector(s: string) return std_logic_vector is variable slv: std_logic_vector(s'high-s'low downto 0); variable k: integer; begin k := s'high-s'low; for i in s'range loop slv(k) := to_std_logic(s(i)); k := k - 1; end loop; return slv; end to_std_logic_vector; ---------------- -- file I/O -- ---------------- -- read variable length string from input file procedure str_read(file in_file: TEXT; res_string: out string) is variable l: line; variable c: character; variable is_string: boolean; begin readline(in_file, l); -- clear the contents of the result string for i in res_string'range loop res_string(i) := ' '; end loop; -- read all characters of the line, up to the length -- of the results string for i in res_string'range loop read(l, c, is_string); res_string(i) := c; if not is_string then -- found end of line exit; end if; end loop; end str_read; -- print string to a file procedure print(file out_file: TEXT; new_string: in string) is variable l: line; begin write(l, new_string); writeline(out_file, l); end print; -- print character to a file and start new line procedure print(file out_file: TEXT; char: in character) is variable l: line; begin write(l, char); writeline(out_file, l); end print; -- appends contents of a string to a file until line feed occurs -- (LF is considered to be the end of the string) procedure str_write(file out_file: TEXT; new_string: in string) is begin for i in new_string'range loop print(out_file, new_string(i)); if new_string(i) = LF then -- end of string exit; end if; end loop; end str_write; end txt_util;

mit

dries007/Basys3

VGA/VGA.srcs/sources_1/ip/dist_mem_gen_0/dist_mem_gen_v8_0_9/hdl/dist_mem_gen_v8_0_vhsyn_rfs.vhd

3

173089

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mit

whitef0x0/EECE353-Lab5

lab5.vhd

1

630

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity lab5 is port(CLOCK_50 : in std_logic; KEY : in std_logic_vector(3 downto 0); SW : in std_logic_vector(17 downto 0); VGA_R, VGA_G, VGA_B : out std_logic_vector(9 downto 0); -- The outs go to VGA controller VGA_HS : out std_logic; VGA_VS : out std_logic; VGA_BLANK : out std_logic; VGA_SYNC : out std_logic; VGA_CLK : out std_logic); end lab5; architecture RTL of lab5 is begin end RTL;

mit

oetr/FPGA-I2C-Slave

debounce.vhd

1

2024

------------------------------------------------------------ -- File : debounce.vhd ------------------------------------------------------------ -- Author : Peter Samarin <[email protected]> ------------------------------------------------------------ -- Copyright (c) 2019 Peter Samarin ------------------------------------------------------------ -- Description: debouncing circuit that forwards only -- signals that have been stable for the whole duration of -- the counter ------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; ------------------------------------------------------------ entity debounce is generic ( WAIT_CYCLES : integer := 5); port ( signal_in : in std_logic; signal_out : out std_logic; clk : in std_logic); end entity debounce; ------------------------------------------------------------ architecture arch of debounce is type state_t is (idle, check_input_stable); signal state_reg : state_t := idle; signal out_reg : std_logic := signal_in; signal signal_in_reg : std_logic; signal counter : integer range 0 to WAIT_CYCLES-1 := 0; begin process (clk) is begin if rising_edge(clk) then case state_reg is when idle => if out_reg /= signal_in then signal_in_reg <= signal_in; state_reg <= check_input_stable; counter <= WAIT_CYCLES-1; end if; when check_input_stable => if counter = 0 then if signal_in = signal_in_reg then out_reg <= signal_in; end if; state_reg <= idle; else if signal_in /= signal_in_reg then state_reg <= idle; end if; counter <= counter - 1; end if; end case; end if; end process; -- output signal_out <= out_reg; end architecture arch;

mit

dries007/Basys3

FPGA-Z/FPGA-Z.srcs/sim_2/new/test2.vhd

1

874

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use work.Font.all; use ieee.std_logic_textio.all; use std.textio.all; entity test2 is end test2; architecture Behavioral of test2 is begin process variable output : boolean; variable y : integer; variable x : integer; file outfile : text is out "out.txt"; --declare output file variable outline : line; --line number declaration begin for yl in 0 to 15 loop for xl in 0 to 7 loop x := xl; y := yl; output := draw_char(xl, yl, 33); if output then write(outline, string'("1")); else write(outline, string'("0")); end if; wait for 1ps; end loop; writeline(outfile, outline); end loop; writeline(outfile, outline); end process; end Behavioral;

mit

dries007/Basys3

VGA_text/VGA_text.srcs/sources_1/new/Vga.vhd

1

3873

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; use ieee.math_real.all; use work.Font.all; -- Information from http://tinyvga.com/vga-timing/1280x1024@60Hz entity Vga is Generic ( H_PIX : integer := 1280; -- Horizontal frame size H_FP : integer := 48; -- Horizontal Front Porch H_SY : integer := 112; -- Horizontal Sync H_BP : integer := 248; -- Horizontal Back Porch H_POL : std_logic := '1'; -- Horizontal Sync Polarity V_PIX : integer := 1024; -- Vertical frame size V_FP : integer := 1; -- Vertical Front Porch V_SY : integer := 3; -- Vertical Sync V_BP : integer := 36; -- Vertical Back Porch V_POL : std_logic := '1' -- Vertical Sync Polarity ); Port ( clk : in std_logic; hSync : out std_logic; vSync : out std_logic; vgaRed : out std_logic_vector (3 downto 0); vgaGreen : out std_logic_vector (3 downto 0); vgaBlue : out std_logic_vector (3 downto 0); fbOutAddr : out std_logic_vector(13 downto 0); fbOutDat : in std_logic_vector(7 downto 0) ); end Vga; architecture Behavioral of Vga is constant H_MAX : integer := H_PIX + H_FP + H_SY + H_BP; -- 1688 for 1280x1024@60Hz constant V_MAX : integer := V_PIX + V_FP + V_SY + V_BP; -- 1066 for 1280x1024@60Hz -------------------------------------------------------- begin -- BEGIN -------------------------------------------------------- process(clk) variable h_count : integer range 0 to H_MAX - 1 := 0; --horizontal counter (counts the columns) variable v_count : integer range 0 to V_MAX - 1 := 0; --vertical counter (counts the rows) variable char : std_logic_vector(7 downto 0); --variable nextChar : std_logic_vector(7 downto 0); variable charX : integer range 0 to 8; variable charY : integer range 0 to 16; begin if (rising_edge(clk)) then --counters if (h_count < H_MAX - 1) then h_count := h_count + 1; else h_count := 0; if (v_count < V_MAX - 1) then v_count := v_count + 1; else v_count := 0; end if; end if; --horizontal sync signal if (h_count < H_PIX + H_FP or h_count > H_PIX + H_FP + H_SY) then hSync <= not H_POL; else hSync <= H_POL; end if; --vertical sync signal if (v_count < V_PIX + V_FP or v_count > V_PIX + V_FP + V_SY) then vSync <= not V_POL; else vSync <= V_POL; end if; --text display if (h_count < H_PIX AND v_count < V_PIX) then charX := h_count mod 8; charY := v_count mod 16; if (charX = 0) then -- Set up next character char := fbOutDat; elsif (charX = 1) then fbOutAddr <= std_logic_vector(to_unsigned(1 + (h_count / 8) + ((v_count / 16) * 160), fbOutAddr'LENGTH)); end if; -- char[7] = invert bit if (char(7) = '1' xor draw_char(charX, charY, to_integer(unsigned(char and "01111111")))) then vgaRed <= "1111"; vgaGreen <= "1111"; vgaBlue <= "1111"; else vgaRed <= "0000"; vgaGreen <= "0000"; vgaBlue <= "0000"; end if; else fbOutAddr <= std_logic_vector(to_unsigned(((v_count / 16) * 160), fbOutAddr'LENGTH)); vgaRed <= "0000"; vgaGreen <= "0000"; vgaBlue <= "0000"; end if; end if; end process; -------------------------------------------------------- end Behavioral; -- END --------------------------------------------------------

mit

dries007/Basys3

FPGA-Z/FPGA-Z.sim/sim_1/impl/func/test1_func_impl.vhd

1

420761

-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015 -- Date : Fri Apr 15 21:41:42 2016 -- Host : Dries007-Arch running 64-bit unknown -- Command : write_vhdl -mode funcsim -nolib -force -file -- /home/dries/Projects/Basys3/FPGA-Z/FPGA-Z.sim/sim_1/impl/func/test1_func_impl.vhd -- Design : top -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7a35tcpg236-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity ClockDivider_ClockDivider_clk_wiz is port ( clkIn : in STD_LOGIC; clk108M : out STD_LOGIC; clk10M : out STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of ClockDivider_ClockDivider_clk_wiz : entity is "ClockDivider_clk_wiz"; end ClockDivider_ClockDivider_clk_wiz; architecture STRUCTURE of ClockDivider_ClockDivider_clk_wiz is signal clk108M_ClockDivider : STD_LOGIC; signal clk10M_ClockDivider : STD_LOGIC; signal clkfbout_ClockDivider : STD_LOGIC; signal clkfbout_buf_ClockDivider : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_LOCKED_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC; signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 ); attribute BOX_TYPE : string; attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE"; attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE"; attribute BOX_TYPE of clkout2_buf : label is "PRIMITIVE"; attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE"; begin clkf_buf: unisim.vcomponents.BUFG port map ( I => clkfbout_ClockDivider, O => clkfbout_buf_ClockDivider ); clkout1_buf: unisim.vcomponents.BUFG port map ( I => clk108M_ClockDivider, O => clk108M ); clkout2_buf: unisim.vcomponents.BUFG port map ( I => clk10M_ClockDivider, O => clk10M ); mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV generic map( BANDWIDTH => "OPTIMIZED", CLKFBOUT_MULT_F => 54.000000, CLKFBOUT_PHASE => 0.000000, CLKFBOUT_USE_FINE_PS => false, CLKIN1_PERIOD => 10.000000, CLKIN2_PERIOD => 0.000000, CLKOUT0_DIVIDE_F => 10.000000, CLKOUT0_DUTY_CYCLE => 0.500000, CLKOUT0_PHASE => 0.000000, CLKOUT0_USE_FINE_PS => false, CLKOUT1_DIVIDE => 108, CLKOUT1_DUTY_CYCLE => 0.500000, CLKOUT1_PHASE => 0.000000, CLKOUT1_USE_FINE_PS => false, CLKOUT2_DIVIDE => 1, CLKOUT2_DUTY_CYCLE => 0.500000, CLKOUT2_PHASE => 0.000000, CLKOUT2_USE_FINE_PS => false, CLKOUT3_DIVIDE => 1, CLKOUT3_DUTY_CYCLE => 0.500000, CLKOUT3_PHASE => 0.000000, CLKOUT3_USE_FINE_PS => false, CLKOUT4_CASCADE => false, CLKOUT4_DIVIDE => 1, CLKOUT4_DUTY_CYCLE => 0.500000, CLKOUT4_PHASE => 0.000000, CLKOUT4_USE_FINE_PS => false, CLKOUT5_DIVIDE => 1, CLKOUT5_DUTY_CYCLE => 0.500000, CLKOUT5_PHASE => 0.000000, CLKOUT5_USE_FINE_PS => false, CLKOUT6_DIVIDE => 1, CLKOUT6_DUTY_CYCLE => 0.500000, CLKOUT6_PHASE => 0.000000, CLKOUT6_USE_FINE_PS => false, COMPENSATION => "BUF_IN", DIVCLK_DIVIDE => 5, IS_CLKINSEL_INVERTED => '0', IS_PSEN_INVERTED => '0', IS_PSINCDEC_INVERTED => '0', IS_PWRDWN_INVERTED => '0', IS_RST_INVERTED => '0', REF_JITTER1 => 0.010000, REF_JITTER2 => 0.010000, SS_EN => "FALSE", SS_MODE => "CENTER_HIGH", SS_MOD_PERIOD => 10000, STARTUP_WAIT => false ) port map ( CLKFBIN => clkfbout_buf_ClockDivider, CLKFBOUT => clkfbout_ClockDivider, CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED, CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED, CLKIN1 => clkIn, CLKIN2 => '0', CLKINSEL => '1', CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED, CLKOUT0 => clk108M_ClockDivider, CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED, CLKOUT1 => clk10M_ClockDivider, CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED, CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED, CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED, CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED, CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED, CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED, CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED, CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED, DADDR(6 downto 0) => B"0000000", DCLK => '0', DEN => '0', DI(15 downto 0) => B"0000000000000000", DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0), DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED, DWE => '0', LOCKED => NLW_mmcm_adv_inst_LOCKED_UNCONNECTED, PSCLK => '0', PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED, PSEN => '0', PSINCDEC => '0', PWRDWN => '0', RST => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \FrameBuffer_blk_mem_gen_mux__parameterized0\ is port ( doutb : out STD_LOGIC_VECTOR ( 7 downto 0 ); DOBDO : in STD_LOGIC_VECTOR ( 7 downto 0 ); \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\ : in STD_LOGIC_VECTOR ( 7 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 2 downto 0 ); clkb : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \FrameBuffer_blk_mem_gen_mux__parameterized0\ : entity is "blk_mem_gen_mux"; end \FrameBuffer_blk_mem_gen_mux__parameterized0\; architecture STRUCTURE of \FrameBuffer_blk_mem_gen_mux__parameterized0\ is signal sel_pipe : STD_LOGIC_VECTOR ( 2 downto 0 ); begin \doutb[0]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOBDO(0), I1 => sel_pipe(0), I2 => sel_pipe(1), I3 => sel_pipe(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(0), I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(0), O => doutb(0) ); \doutb[1]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOBDO(1), I1 => sel_pipe(0), I2 => sel_pipe(1), I3 => sel_pipe(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(1), I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(1), O => doutb(1) ); \doutb[2]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOBDO(2), I1 => sel_pipe(0), I2 => sel_pipe(1), I3 => sel_pipe(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(2), I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(2), O => doutb(2) ); \doutb[3]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOBDO(3), I1 => sel_pipe(0), I2 => sel_pipe(1), I3 => sel_pipe(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(3), I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(3), O => doutb(3) ); \doutb[4]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOBDO(4), I1 => sel_pipe(0), I2 => sel_pipe(1), I3 => sel_pipe(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(4), I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(4), O => doutb(4) ); \doutb[5]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOBDO(5), I1 => sel_pipe(0), I2 => sel_pipe(1), I3 => sel_pipe(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(5), I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(5), O => doutb(5) ); \doutb[6]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOBDO(6), I1 => sel_pipe(0), I2 => sel_pipe(1), I3 => sel_pipe(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(6), I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(6), O => doutb(6) ); \doutb[7]_INST_0\: unisim.vcomponents.LUT6 generic map( INIT => X"02FF020F02F00200" ) port map ( I0 => DOBDO(7), I1 => sel_pipe(0), I2 => sel_pipe(1), I3 => sel_pipe(2), I4 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(7), I5 => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(7), O => doutb(7) ); \no_softecc_sel_reg.ce_pri.sel_pipe_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clkb, CE => '1', D => addrb(0), Q => sel_pipe(0), R => '0' ); \no_softecc_sel_reg.ce_pri.sel_pipe_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clkb, CE => '1', D => addrb(1), Q => sel_pipe(1), R => '0' ); \no_softecc_sel_reg.ce_pri.sel_pipe_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clkb, CE => '1', D => addrb(2), Q => sel_pipe(2), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity FrameBuffer_blk_mem_gen_prim_wrapper_init is port ( \doutb[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); clka : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init"; end FrameBuffer_blk_mem_gen_prim_wrapper_init; architecture STRUCTURE of FrameBuffer_blk_mem_gen_prim_wrapper_init is signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1_n_0\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2_n_0\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute BOX_TYPE : string; attribute BOX_TYPE of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE"; attribute CLOCK_DOMAINS : string; attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT"; attribute PWROPT_WRITE_MODE_CHANGE_A : string; attribute PWROPT_WRITE_MODE_CHANGE_A of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "READ_FIRST:NO_CHANGE_2"; begin \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1 generic map( DOA_REG => 0, DOB_REG => 0, EN_ECC_READ => false, EN_ECC_WRITE => false, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_01 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_02 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_03 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_04 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_05 => X"4646464646464646464646464646464646462020202020202020202020202020", INIT_06 => X"2020202020202020202020505050505050505050505050505050505046464646", INIT_07 => X"2041414120202020202020202020202020202047474747474747474747474747", INIT_08 => X"5A20202020202020202020202020202020202020202020202020202020202020", INIT_09 => X"20202020202020202020202020205A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A", INIT_0A => X"3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A462020202020202020202020202020", INIT_0B => X"47474720202020202020503A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A50463A3A3A", INIT_0C => X"413A3A3A412020202020202020202020202020473A3A3A3A3A3A3A3A3A3A3A3A", INIT_0D => X"5A20202020202020202020202020202020202020202020202020202020202020", INIT_0E => X"20202020202020202020202020205A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A3A", INIT_0F => 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\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\, WEA(3) => wea(0), WEA(2) => wea(0), WEA(1) => wea(0), WEA(0) => wea(0), WEBWE(7 downto 0) => B"00000000" ); \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => wea(0), I1 => addra(12), I2 => addra(13), O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1_n_0\ ); \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => addrb(12), I1 => addrb(13), O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized0\ is port ( \doutb[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); clka : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init"; end \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized0\; architecture STRUCTURE of \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized0\ is signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__0_n_0\ : STD_LOGIC; signal \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__0_n_0\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 8 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 ); attribute BOX_TYPE : string; attribute BOX_TYPE of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE"; attribute CLOCK_DOMAINS : string; attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\ : label is "INDEPENDENT"; attribute PWROPT_WRITE_MODE_CHANGE_A : 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X"2020202020202020202020202020202020202020202020202020202020202020", INIT_35 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_36 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_37 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_38 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_39 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_3A => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_3B => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_3C => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_3D => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_3E => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_3F => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_40 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_41 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_42 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_43 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_44 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_45 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_46 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_47 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_48 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_49 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_4A => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_4B => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_4C => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_4D => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_4E => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_4F => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_50 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_51 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_52 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_53 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_54 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_55 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_56 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_57 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_58 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_59 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_5A => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_5B => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_5C => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_5D => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_5E => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_5F => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_60 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_61 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_62 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_63 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_64 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_65 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_66 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_67 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_68 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_69 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_6A => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_6B => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_6C => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_6D => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_6E => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_6F => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_70 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_71 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_72 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_73 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_74 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_75 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_76 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_77 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_78 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_79 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_7A => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_7B => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_7C => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_7D => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_7E => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_7F => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_A => X"000000000", INIT_B => X"000000000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", READ_WIDTH_A => 9, READ_WIDTH_B => 9, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"000000000", SRVAL_B => X"000000000", WRITE_MODE_A => "NO_CHANGE", WRITE_MODE_B => "READ_FIRST", WRITE_WIDTH_A => 9, WRITE_WIDTH_B => 9 ) port map ( ADDRARDADDR(15) => '1', ADDRARDADDR(14 downto 3) => addra(11 downto 0), ADDRARDADDR(2 downto 0) => B"111", ADDRBWRADDR(15) => '1', ADDRBWRADDR(14 downto 3) => addrb(11 downto 0), ADDRBWRADDR(2 downto 0) => B"111", CASCADEINA => '0', CASCADEINB => '0', CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\, CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\, CLKARDCLK => clka, CLKBWRCLK => clkb, DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\, DIADI(31 downto 8) => B"000000000000000000000000", DIADI(7 downto 0) => dina(7 downto 0), DIBDI(31 downto 0) => B"00000000000000000000000000000000", DIPADIP(3 downto 0) => B"0000", DIPBDIP(3 downto 0) => B"0000", DOADO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 0), DOBDO(31 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 8), DOBDO(7 downto 0) => \doutb[7]\(7 downto 0), DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 0), DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0), ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0), ENARDEN => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__0_n_0\, ENBWREN => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__0_n_0\, INJECTDBITERR => '0', INJECTSBITERR => '0', RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0), REGCEAREGCE => '0', REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\, WEA(3) => wea(0), WEA(2) => wea(0), WEA(1) => wea(0), WEA(0) => wea(0), WEBWE(7 downto 0) => B"00000000" ); \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"08" ) port map ( I0 => addra(12), I1 => wea(0), I2 => addra(13), O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1__0_n_0\ ); \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__0\: unisim.vcomponents.LUT2 generic map( INIT => X"4" ) port map ( I0 => addrb(13), I1 => addrb(12), O => \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2__0_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized1\ is port ( DOBDO : out STD_LOGIC_VECTOR ( 7 downto 0 ); clka : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized1\ : entity is "blk_mem_gen_prim_wrapper_init"; end \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized1\; architecture STRUCTURE of \FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized1\ is signal ram_ena : STD_LOGIC; signal ram_enb : STD_LOGIC; signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 8 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 ); attribute BOX_TYPE : string; attribute BOX_TYPE of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE"; attribute CLOCK_DOMAINS : string; attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "INDEPENDENT"; attribute PWROPT_WRITE_MODE_CHANGE_A : string; attribute PWROPT_WRITE_MODE_CHANGE_A of \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\ : label is "READ_FIRST:NO_CHANGE_2"; begin \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1 generic map( DOA_REG => 0, DOB_REG => 0, INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_01 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_02 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_03 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_04 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_05 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_06 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_07 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_08 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_09 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_0A => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_0B => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_0C => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_0D => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_0E => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_0F => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_10 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_11 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_12 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_13 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_14 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_15 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_16 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_17 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_18 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_19 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_1A => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_1B => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_1C => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_1D => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_1E => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_1F => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_20 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_21 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_22 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_23 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_24 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_25 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_26 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_27 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_28 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_29 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_2A => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_2B => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_2C => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_2D => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_2E => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_2F => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_30 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_31 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_32 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_33 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_34 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_35 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_36 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_37 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_38 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_39 => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_3A => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_3B => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_3C => X"6867697279706F43202020202020202020202020202020202020202020202020", INIT_3D => X"656972642F2F3A707474683C2037303073656972442036313032202943282074", INIT_3E => X"20202020202020202020202020202020202020202020203E74656E2E37303073", INIT_3F => X"2020202020202020202020202020202020202020202020202020202020202020", INIT_A => X"00000", INIT_B => X"00000", INIT_FILE => "NONE", IS_CLKARDCLK_INVERTED => '0', IS_CLKBWRCLK_INVERTED => '0', IS_ENARDEN_INVERTED => '0', IS_ENBWREN_INVERTED => '0', IS_RSTRAMARSTRAM_INVERTED => '0', IS_RSTRAMB_INVERTED => '0', IS_RSTREGARSTREG_INVERTED => '0', IS_RSTREGB_INVERTED => '0', RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", READ_WIDTH_A => 9, READ_WIDTH_B => 9, RSTREG_PRIORITY_A => "REGCE", RSTREG_PRIORITY_B => "REGCE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "7SERIES", SRVAL_A => X"00000", SRVAL_B => X"00000", WRITE_MODE_A => "NO_CHANGE", WRITE_MODE_B => "READ_FIRST", WRITE_WIDTH_A => 9, WRITE_WIDTH_B => 9 ) port map ( ADDRARDADDR(13 downto 3) => addra(10 downto 0), ADDRARDADDR(2 downto 0) => B"000", ADDRBWRADDR(13 downto 3) => addrb(10 downto 0), ADDRBWRADDR(2 downto 0) => B"000", CLKARDCLK => clka, CLKBWRCLK => clkb, DIADI(15 downto 8) => B"00000000", DIADI(7 downto 0) => dina(7 downto 0), DIBDI(15 downto 0) => B"0000000000000000", DIPADIP(1 downto 0) => B"00", DIPBDIP(1 downto 0) => B"00", DOADO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOADO_UNCONNECTED\(15 downto 0), DOBDO(15 downto 8) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 8), DOBDO(7 downto 0) => DOBDO(7 downto 0), DOPADOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPADOP_UNCONNECTED\(1 downto 0), DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0), ENARDEN => ram_ena, ENBWREN => ram_enb, REGCEAREGCE => '0', REGCEB => '0', RSTRAMARSTRAM => '0', RSTRAMB => '0', RSTREGARSTREG => '0', RSTREGB => '0', WEA(1) => wea(0), WEA(0) => wea(0), WEBWE(3 downto 0) => B"0000" ); \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"1000" ) port map ( I0 => addra(12), I1 => addra(11), I2 => addra(13), I3 => wea(0), O => ram_ena ); \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM18.ram_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"04" ) port map ( I0 => addrb(11), I1 => addrb(13), I2 => addrb(12), O => ram_enb ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity Vga is port ( addrb : out STD_LOGIC_VECTOR ( 13 downto 0 ); Hsync_OBUF : out STD_LOGIC; Vsync_OBUF : out STD_LOGIC; vgaBlue_OBUF : out STD_LOGIC_VECTOR ( 0 to 0 ); clk108M : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 7 downto 0 ) ); end Vga; architecture STRUCTURE of Vga is signal X : STD_LOGIC_VECTOR ( 2 downto 0 ); signal Y : STD_LOGIC_VECTOR ( 3 downto 0 ); signal char : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \char[0]_i_1_n_0\ : STD_LOGIC; signal \char[1]_i_1_n_0\ : STD_LOGIC; signal \char[2]_i_1_n_0\ : STD_LOGIC; signal \char[3]_i_1_n_0\ : STD_LOGIC; signal \char[4]_i_1_n_0\ : STD_LOGIC; signal \char[5]_i_1_n_0\ : STD_LOGIC; signal \char[6]_i_1_n_0\ : STD_LOGIC; signal \char[7]_i_1_n_0\ : STD_LOGIC; signal enable : STD_LOGIC; signal enable_i_1_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_10_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_11_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_12_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_13_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_14_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_15_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_16_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_17_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_18_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_19_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_1_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_20_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_21_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_22_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_23_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_24_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_25_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_26_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_27_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_28_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_2_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_3_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_4_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_5_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_6_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_7_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_8_n_0 : STD_LOGIC; signal fbOutAddr_reg_i_9_n_0 : STD_LOGIC; signal g0_b0_n_0 : STD_LOGIC; signal g0_b1_n_0 : STD_LOGIC; signal g0_b2_i_1_n_0 : STD_LOGIC; signal g0_b2_i_2_n_0 : STD_LOGIC; signal g0_b2_n_0 : STD_LOGIC; signal g0_b3_n_0 : STD_LOGIC; signal g0_b4_n_0 : STD_LOGIC; signal g0_b5_n_0 : STD_LOGIC; signal g0_b6_n_0 : STD_LOGIC; signal g0_b7_n_0 : STD_LOGIC; signal g10_b0_n_0 : STD_LOGIC; signal g10_b1_n_0 : STD_LOGIC; signal g10_b2_n_0 : STD_LOGIC; signal g10_b3_n_0 : STD_LOGIC; signal g10_b4_n_0 : STD_LOGIC; signal g10_b5_n_0 : STD_LOGIC; signal g11_b0_n_0 : STD_LOGIC; signal g11_b1_n_0 : STD_LOGIC; signal g11_b2_n_0 : STD_LOGIC; signal g11_b3_n_0 : STD_LOGIC; signal g11_b4_n_0 : STD_LOGIC; signal g11_b5_n_0 : STD_LOGIC; signal g11_b6_n_0 : STD_LOGIC; signal g12_b0_n_0 : STD_LOGIC; signal g12_b1_n_0 : STD_LOGIC; signal g12_b2_n_0 : STD_LOGIC; signal g12_b3_n_0 : STD_LOGIC; signal g12_b4_n_0 : STD_LOGIC; signal g12_b5_n_0 : STD_LOGIC; signal g12_b6_n_0 : STD_LOGIC; signal g13_b0_n_0 : STD_LOGIC; signal g13_b1_n_0 : STD_LOGIC; signal g13_b2_n_0 : STD_LOGIC; signal g13_b3_n_0 : STD_LOGIC; signal g13_b4_n_0 : STD_LOGIC; signal g13_b5_n_0 : STD_LOGIC; signal g13_b6_n_0 : STD_LOGIC; signal g14_b0_n_0 : STD_LOGIC; signal g14_b1_n_0 : STD_LOGIC; signal g14_b2_n_0 : STD_LOGIC; signal g14_b3_n_0 : STD_LOGIC; signal g14_b4_n_0 : STD_LOGIC; signal g14_b5_n_0 : STD_LOGIC; signal g14_b6_n_0 : STD_LOGIC; signal g15_b0_n_0 : STD_LOGIC; signal g15_b1_n_0 : STD_LOGIC; signal g15_b2_n_0 : STD_LOGIC; signal g15_b3_n_0 : STD_LOGIC; signal g15_b4_n_0 : STD_LOGIC; signal g15_b5_n_0 : STD_LOGIC; signal g15_b6_n_0 : STD_LOGIC; signal g16_b0_n_0 : STD_LOGIC; signal g16_b1_n_0 : STD_LOGIC; signal g16_b2_n_0 : STD_LOGIC; signal g16_b3_n_0 : STD_LOGIC; signal g16_b4_n_0 : STD_LOGIC; signal g16_b5_n_0 : STD_LOGIC; signal g16_b6_n_0 : STD_LOGIC; signal g17_b0_n_0 : STD_LOGIC; signal g17_b1_n_0 : STD_LOGIC; signal g17_b2_n_0 : STD_LOGIC; signal g17_b3_n_0 : STD_LOGIC; signal g17_b4_n_0 : STD_LOGIC; signal g17_b5_n_0 : STD_LOGIC; signal g17_b6_n_0 : STD_LOGIC; signal g18_b0_n_0 : STD_LOGIC; signal g18_b1_n_0 : STD_LOGIC; signal g18_b2_n_0 : STD_LOGIC; signal g18_b3_n_0 : STD_LOGIC; signal g18_b4_n_0 : STD_LOGIC; signal g18_b5_n_0 : STD_LOGIC; signal g18_b6_n_0 : STD_LOGIC; signal g19_b0_n_0 : STD_LOGIC; signal g19_b1_n_0 : STD_LOGIC; signal g19_b2_n_0 : STD_LOGIC; signal g19_b3_n_0 : STD_LOGIC; signal g19_b4_n_0 : STD_LOGIC; signal g19_b5_n_0 : STD_LOGIC; signal g19_b6_n_0 : STD_LOGIC; signal g19_b7_n_0 : STD_LOGIC; signal g1_b0_n_0 : STD_LOGIC; signal g1_b1_n_0 : STD_LOGIC; signal g1_b2_n_0 : STD_LOGIC; signal g1_b3_n_0 : STD_LOGIC; signal g1_b4_n_0 : STD_LOGIC; signal g1_b5_n_0 : STD_LOGIC; signal g1_b6_n_0 : STD_LOGIC; signal g1_b7_n_0 : STD_LOGIC; signal g20_b0_n_0 : STD_LOGIC; signal g20_b1_n_0 : STD_LOGIC; signal g20_b2_n_0 : STD_LOGIC; signal g20_b3_n_0 : STD_LOGIC; signal g20_b4_n_0 : STD_LOGIC; signal g20_b5_n_0 : STD_LOGIC; signal g20_b6_n_0 : STD_LOGIC; signal g21_b0_n_0 : STD_LOGIC; signal g21_b1_n_0 : STD_LOGIC; signal g21_b2_n_0 : STD_LOGIC; signal g21_b3_n_0 : STD_LOGIC; signal g21_b5_n_0 : STD_LOGIC; signal g21_b6_n_0 : STD_LOGIC; signal g21_b7_n_0 : STD_LOGIC; signal g22_b0_n_0 : STD_LOGIC; signal g22_b1_n_0 : STD_LOGIC; signal g22_b2_n_0 : STD_LOGIC; signal g22_b3_n_0 : STD_LOGIC; signal g22_b4_n_0 : STD_LOGIC; signal g22_b5_n_0 : STD_LOGIC; signal g22_b6_n_0 : STD_LOGIC; signal g22_b7_n_0 : STD_LOGIC; signal g23_b0_n_0 : STD_LOGIC; signal g23_b1_n_0 : STD_LOGIC; signal g23_b2_n_0 : STD_LOGIC; signal g23_b3_n_0 : STD_LOGIC; signal g23_b4_n_0 : STD_LOGIC; signal g23_b5_n_0 : STD_LOGIC; signal g23_b6_n_0 : STD_LOGIC; signal g23_b7_n_0 : STD_LOGIC; signal g24_b0_n_0 : STD_LOGIC; signal g24_b1_n_0 : STD_LOGIC; signal g24_b2_n_0 : STD_LOGIC; signal g24_b3_n_0 : STD_LOGIC; signal g24_b4_n_0 : STD_LOGIC; signal g24_b5_n_0 : STD_LOGIC; signal g24_b6_n_0 : STD_LOGIC; signal g25_b0_n_0 : STD_LOGIC; signal g25_b1_n_0 : STD_LOGIC; signal g25_b2_n_0 : STD_LOGIC; signal g25_b3_n_0 : STD_LOGIC; signal g25_b4_n_0 : STD_LOGIC; signal g25_b5_n_0 : STD_LOGIC; signal g25_b6_n_0 : STD_LOGIC; signal g26_b0_n_0 : STD_LOGIC; signal g26_b1_n_0 : STD_LOGIC; signal g26_b2_n_0 : STD_LOGIC; signal g26_b3_n_0 : STD_LOGIC; signal g26_b4_n_0 : STD_LOGIC; signal g26_b5_n_0 : STD_LOGIC; signal g26_b6_n_0 : STD_LOGIC; signal g27_b0_n_0 : STD_LOGIC; signal g27_b1_n_0 : STD_LOGIC; signal g27_b2_n_0 : STD_LOGIC; signal g27_b3_n_0 : STD_LOGIC; signal g27_b5_n_0 : STD_LOGIC; signal g27_b6_n_0 : STD_LOGIC; signal g27_b7_n_0 : STD_LOGIC; signal g28_b0_n_0 : STD_LOGIC; signal g28_b1_n_0 : STD_LOGIC; signal g28_b2_n_0 : STD_LOGIC; signal g28_b3_n_0 : STD_LOGIC; signal g28_b4_n_0 : STD_LOGIC; signal g28_b5_n_0 : STD_LOGIC; signal g28_b6_n_0 : STD_LOGIC; signal g29_b0_n_0 : STD_LOGIC; signal g29_b1_n_0 : STD_LOGIC; signal g29_b2_n_0 : STD_LOGIC; signal g29_b3_n_0 : STD_LOGIC; signal g29_b4_n_0 : STD_LOGIC; signal g29_b5_n_0 : STD_LOGIC; signal g29_b6_n_0 : STD_LOGIC; signal g29_b7_n_0 : STD_LOGIC; signal g2_b0_n_0 : STD_LOGIC; signal g2_b1_n_0 : STD_LOGIC; signal g2_b2_n_0 : STD_LOGIC; signal g2_b3_n_0 : STD_LOGIC; signal g2_b4_n_0 : STD_LOGIC; signal g2_b5_n_0 : STD_LOGIC; signal g2_b6_n_0 : STD_LOGIC; signal g2_b7_n_0 : STD_LOGIC; signal g30_b0_n_0 : STD_LOGIC; signal g30_b1_n_0 : STD_LOGIC; signal g30_b2_n_0 : STD_LOGIC; signal g30_b3_n_0 : STD_LOGIC; signal g30_b4_n_0 : STD_LOGIC; signal g30_b5_n_0 : STD_LOGIC; signal g30_b6_n_0 : STD_LOGIC; signal g30_b7_n_0 : STD_LOGIC; signal g31_b0_n_0 : STD_LOGIC; signal g31_b1_n_0 : STD_LOGIC; signal g31_b2_n_0 : STD_LOGIC; signal g31_b3_n_0 : STD_LOGIC; signal g31_b4_n_0 : STD_LOGIC; signal g31_b5_n_0 : STD_LOGIC; signal g31_b6_n_0 : STD_LOGIC; signal g3_b0_n_0 : STD_LOGIC; signal g3_b1_n_0 : STD_LOGIC; signal g3_b2_n_0 : STD_LOGIC; signal g3_b3_n_0 : STD_LOGIC; signal g3_b4_n_0 : STD_LOGIC; signal g3_b5_n_0 : STD_LOGIC; signal g3_b6_n_0 : STD_LOGIC; signal g3_b7_n_0 : STD_LOGIC; signal g4_b0_n_0 : STD_LOGIC; signal g4_b1_n_0 : STD_LOGIC; signal g4_b2_n_0 : STD_LOGIC; signal g4_b3_n_0 : STD_LOGIC; signal g4_b4_n_0 : STD_LOGIC; signal g4_b5_n_0 : STD_LOGIC; signal g4_b6_n_0 : STD_LOGIC; signal g5_b0_n_0 : STD_LOGIC; signal g5_b1_n_0 : STD_LOGIC; signal g5_b2_n_0 : STD_LOGIC; signal g5_b3_n_0 : STD_LOGIC; signal g5_b4_n_0 : STD_LOGIC; signal g5_b5_n_0 : STD_LOGIC; signal g5_b6_n_0 : STD_LOGIC; signal g5_b7_n_0 : STD_LOGIC; signal g6_b0_n_0 : STD_LOGIC; signal g6_b1_n_0 : STD_LOGIC; signal g6_b2_n_0 : STD_LOGIC; signal g6_b3_n_0 : STD_LOGIC; signal g6_b4_n_0 : STD_LOGIC; signal g6_b5_n_0 : STD_LOGIC; signal g6_b6_n_0 : STD_LOGIC; signal g7_b0_n_0 : STD_LOGIC; signal g7_b1_n_0 : STD_LOGIC; signal g7_b2_n_0 : STD_LOGIC; signal g7_b3_n_0 : STD_LOGIC; signal g7_b4_n_0 : STD_LOGIC; signal g7_b5_n_0 : STD_LOGIC; signal g7_b6_n_0 : STD_LOGIC; signal g7_b7_n_0 : STD_LOGIC; signal g8_b0_n_0 : STD_LOGIC; signal g8_b1_n_0 : STD_LOGIC; signal g8_b2_n_0 : STD_LOGIC; signal g8_b3_n_0 : STD_LOGIC; signal g8_b4_n_0 : STD_LOGIC; signal g8_b6_n_0 : STD_LOGIC; signal g9_b0_n_0 : STD_LOGIC; signal g9_b1_n_0 : STD_LOGIC; signal g9_b2_n_0 : STD_LOGIC; signal g9_b3_n_0 : STD_LOGIC; signal g9_b4_n_0 : STD_LOGIC; signal g9_b5_n_0 : STD_LOGIC; signal g9_b6_n_0 : STD_LOGIC; signal hSync_i_1_n_0 : STD_LOGIC; signal hSync_i_2_n_0 : STD_LOGIC; signal hSync_i_3_n_0 : STD_LOGIC; signal \h_count[2]_i_1_n_0\ : STD_LOGIC; signal \h_count_reg__0\ : STD_LOGIC_VECTOR ( 10 downto 3 ); signal nextChar : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \nextChar[7]_i_1_n_0\ : STD_LOGIC; signal p_0_in : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal vSync_i_1_n_0 : STD_LOGIC; signal vSync_i_2_n_0 : STD_LOGIC; signal \v_count[0]_rep_i_1_n_0\ : STD_LOGIC; signal \v_count[1]_rep_i_1_n_0\ : STD_LOGIC; signal \v_count[2]_rep_i_1_n_0\ : STD_LOGIC; signal \v_count[3]_rep__0_i_1_n_0\ : STD_LOGIC; signal \v_count[3]_rep_i_1_n_0\ : STD_LOGIC; signal \v_count_reg[0]_rep_n_0\ : STD_LOGIC; signal \v_count_reg[1]_rep_n_0\ : STD_LOGIC; signal \v_count_reg[2]_rep_n_0\ : STD_LOGIC; signal \v_count_reg[3]_rep__0_n_0\ : STD_LOGIC; signal \v_count_reg[3]_rep_n_0\ : STD_LOGIC; signal \v_count_reg__0\ : STD_LOGIC_VECTOR ( 10 downto 4 ); signal \vgaRed[0]_i_10_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_11_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_13_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_14_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_15_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_16_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_17_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_18_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_19_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_1_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_20_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_21_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_22_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_23_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_29_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_33_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_34_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_40_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_41_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_42_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_48_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_4_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_56_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_5_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_64_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_68_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_69_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_6_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_7_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_80_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_8_n_0\ : STD_LOGIC; signal \vgaRed[0]_i_9_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_100_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_101_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_102_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_103_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_104_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_105_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_106_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_107_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_108_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_109_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_110_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_111_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_112_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_113_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_114_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_115_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_116_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_117_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_118_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_119_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_120_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_121_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_122_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_123_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_124_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_125_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_126_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_127_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_128_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_129_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_12_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_130_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_131_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_132_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_133_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_134_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_135_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_136_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_137_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_138_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_139_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_140_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_141_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_142_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_143_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_144_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_145_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_146_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_147_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_148_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_149_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_150_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_151_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_152_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_153_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_154_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_155_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_156_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_157_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_158_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_159_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_160_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_161_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_162_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_163_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_164_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_165_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_166_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_167_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_168_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_169_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_170_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_171_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_172_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_173_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_174_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_175_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_176_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_177_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_178_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_179_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_180_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_24_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_25_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_26_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_27_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_28_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_2_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_30_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_31_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_32_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_35_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_36_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_37_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_38_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_39_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_3_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_43_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_44_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_45_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_46_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_47_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_49_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_50_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_51_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_52_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_53_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_54_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_55_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_57_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_58_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_59_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_60_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_61_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_62_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_63_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_65_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_66_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_67_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_70_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_71_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_72_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_73_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_74_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_75_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_76_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_77_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_78_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_79_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_81_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_82_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_83_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_84_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_85_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_86_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_87_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_88_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_89_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_90_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_91_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_92_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_93_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_94_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_95_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_96_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_97_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_98_n_0\ : STD_LOGIC; signal \vgaRed_reg[0]_i_99_n_0\ : STD_LOGIC; signal NLW_fbOutAddr_reg_CARRYCASCOUT_UNCONNECTED : STD_LOGIC; signal NLW_fbOutAddr_reg_MULTSIGNOUT_UNCONNECTED : STD_LOGIC; signal NLW_fbOutAddr_reg_OVERFLOW_UNCONNECTED : STD_LOGIC; signal NLW_fbOutAddr_reg_PATTERNBDETECT_UNCONNECTED : STD_LOGIC; signal NLW_fbOutAddr_reg_PATTERNDETECT_UNCONNECTED : STD_LOGIC; signal NLW_fbOutAddr_reg_UNDERFLOW_UNCONNECTED : STD_LOGIC; signal NLW_fbOutAddr_reg_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 ); signal NLW_fbOutAddr_reg_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 ); signal NLW_fbOutAddr_reg_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_fbOutAddr_reg_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 14 ); signal NLW_fbOutAddr_reg_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \v_count[0]_i_1\ : label is "soft_lutpair19"; attribute SOFT_HLUTNM of \v_count[0]_rep_i_1\ : label is "soft_lutpair19"; attribute SOFT_HLUTNM of \v_count[1]_i_1\ : label is "soft_lutpair18"; attribute SOFT_HLUTNM of \v_count[1]_rep_i_1\ : label is "soft_lutpair18"; attribute SOFT_HLUTNM of \v_count[2]_i_1\ : label is "soft_lutpair14"; attribute SOFT_HLUTNM of \v_count[3]_i_1\ : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \v_count[3]_rep__0_i_1\ : label is "soft_lutpair13"; attribute SOFT_HLUTNM of \v_count[3]_rep_i_1\ : label is "soft_lutpair14"; attribute ORIG_CELL_NAME : string; attribute ORIG_CELL_NAME of \v_count_reg[0]\ : label is "v_count_reg[0]"; attribute ORIG_CELL_NAME of \v_count_reg[0]_rep\ : label is "v_count_reg[0]"; attribute ORIG_CELL_NAME of \v_count_reg[1]\ : label is "v_count_reg[1]"; attribute ORIG_CELL_NAME of \v_count_reg[1]_rep\ : label is "v_count_reg[1]"; attribute ORIG_CELL_NAME of \v_count_reg[2]\ : label is "v_count_reg[2]"; attribute ORIG_CELL_NAME of \v_count_reg[2]_rep\ : label is "v_count_reg[2]"; attribute ORIG_CELL_NAME of \v_count_reg[3]\ : label is "v_count_reg[3]"; attribute ORIG_CELL_NAME of \v_count_reg[3]_rep\ : label is "v_count_reg[3]"; attribute ORIG_CELL_NAME of \v_count_reg[3]_rep__0\ : label is "v_count_reg[3]"; begin \char[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0002" ) port map ( I0 => nextChar(0), I1 => X(1), I2 => X(0), I3 => X(2), I4 => char(0), O => \char[0]_i_1_n_0\ ); \char[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0002" ) port map ( I0 => nextChar(1), I1 => X(1), I2 => X(0), I3 => X(2), I4 => char(1), O => \char[1]_i_1_n_0\ ); \char[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0002" ) port map ( I0 => nextChar(2), I1 => X(1), I2 => X(0), I3 => X(2), I4 => char(2), O => \char[2]_i_1_n_0\ ); \char[3]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0002" ) port map ( I0 => nextChar(3), I1 => X(1), I2 => X(0), I3 => X(2), I4 => char(3), O => \char[3]_i_1_n_0\ ); \char[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0002" ) port map ( I0 => nextChar(4), I1 => X(1), I2 => X(0), I3 => X(2), I4 => char(4), O => \char[4]_i_1_n_0\ ); \char[5]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0002" ) port map ( I0 => nextChar(5), I1 => X(1), I2 => X(0), I3 => X(2), I4 => char(5), O => \char[5]_i_1_n_0\ ); \char[6]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0002" ) port map ( I0 => nextChar(6), I1 => X(1), I2 => X(0), I3 => X(2), I4 => char(6), O => \char[6]_i_1_n_0\ ); \char[7]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0002" ) port map ( I0 => nextChar(7), I1 => X(1), I2 => X(0), I3 => X(2), I4 => char(7), O => \char[7]_i_1_n_0\ ); \char_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => enable, D => \char[0]_i_1_n_0\, Q => char(0), R => '0' ); \char_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => enable, D => \char[1]_i_1_n_0\, Q => char(1), R => '0' ); \char_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => enable, D => \char[2]_i_1_n_0\, Q => char(2), R => '0' ); \char_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => enable, D => \char[3]_i_1_n_0\, Q => char(3), R => '0' ); \char_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => enable, D => \char[4]_i_1_n_0\, Q => char(4), R => '0' ); \char_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => enable, D => \char[5]_i_1_n_0\, Q => char(5), R => '0' ); \char_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => enable, D => \char[6]_i_1_n_0\, Q => char(6), R => '0' ); \char_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => enable, D => \char[7]_i_1_n_0\, Q => char(7), R => '0' ); enable_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"0057" ) port map ( I0 => \h_count_reg__0\(10), I1 => \h_count_reg__0\(8), I2 => \h_count_reg__0\(9), I3 => \v_count_reg__0\(10), O => enable_i_1_n_0 ); enable_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => '1', D => enable_i_1_n_0, Q => enable, R => '0' ); fbOutAddr_reg: unisim.vcomponents.DSP48E1 generic map( ACASCREG => 1, ADREG => 1, ALUMODEREG => 0, AREG => 1, AUTORESET_PATDET => "NO_RESET", A_INPUT => "DIRECT", BCASCREG => 0, BREG => 0, B_INPUT => "DIRECT", CARRYINREG => 0, CARRYINSELREG => 0, CREG => 1, DREG => 1, INMODEREG => 0, MASK => X"3FFFFFFFFFFF", MREG => 0, OPMODEREG => 0, PATTERN => X"000000000000", PREG => 1, SEL_MASK => "MASK", SEL_PATTERN => "PATTERN", USE_DPORT => false, USE_MULT => "MULTIPLY", USE_PATTERN_DETECT => "NO_PATDET", USE_SIMD => "ONE48" ) port map ( A(29 downto 7) => B"00000000000000000000000", A(6) => fbOutAddr_reg_i_5_n_0, A(5) => fbOutAddr_reg_i_6_n_0, A(4) => fbOutAddr_reg_i_7_n_0, A(3) => fbOutAddr_reg_i_8_n_0, A(2) => fbOutAddr_reg_i_9_n_0, A(1) => fbOutAddr_reg_i_10_n_0, A(0) => fbOutAddr_reg_i_11_n_0, ACIN(29 downto 0) => B"000000000000000000000000000000", ACOUT(29 downto 0) => NLW_fbOutAddr_reg_ACOUT_UNCONNECTED(29 downto 0), ALUMODE(3 downto 0) => B"0000", B(17 downto 0) => B"000000000010100000", BCIN(17 downto 0) => B"000000000000000000", BCOUT(17 downto 0) => NLW_fbOutAddr_reg_BCOUT_UNCONNECTED(17 downto 0), C(47 downto 8) => B"0000000000000000000000000000000000000000", C(7) => fbOutAddr_reg_i_12_n_0, C(6) => fbOutAddr_reg_i_13_n_0, C(5) => fbOutAddr_reg_i_14_n_0, C(4) => fbOutAddr_reg_i_15_n_0, C(3) => fbOutAddr_reg_i_16_n_0, C(2) => fbOutAddr_reg_i_17_n_0, C(1) => fbOutAddr_reg_i_18_n_0, C(0) => fbOutAddr_reg_i_19_n_0, CARRYCASCIN => '0', CARRYCASCOUT => NLW_fbOutAddr_reg_CARRYCASCOUT_UNCONNECTED, CARRYIN => '0', CARRYINSEL(2 downto 0) => B"000", CARRYOUT(3 downto 0) => NLW_fbOutAddr_reg_CARRYOUT_UNCONNECTED(3 downto 0), CEA1 => '0', CEA2 => fbOutAddr_reg_i_1_n_0, CEAD => '0', CEALUMODE => '0', CEB1 => '0', CEB2 => '0', CEC => '1', CECARRYIN => '0', CECTRL => '0', CED => '0', CEINMODE => '0', CEM => '0', CEP => fbOutAddr_reg_i_2_n_0, CLK => clk108M, D(24 downto 0) => B"0000000000000000000000000", INMODE(4 downto 0) => B"00000", MULTSIGNIN => '0', MULTSIGNOUT => NLW_fbOutAddr_reg_MULTSIGNOUT_UNCONNECTED, OPMODE(6) => '0', OPMODE(5) => enable, OPMODE(4) => enable, OPMODE(3 downto 0) => B"0101", OVERFLOW => NLW_fbOutAddr_reg_OVERFLOW_UNCONNECTED, P(47 downto 14) => NLW_fbOutAddr_reg_P_UNCONNECTED(47 downto 14), P(13 downto 0) => addrb(13 downto 0), PATTERNBDETECT => NLW_fbOutAddr_reg_PATTERNBDETECT_UNCONNECTED, PATTERNDETECT => NLW_fbOutAddr_reg_PATTERNDETECT_UNCONNECTED, PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000", PCOUT(47 downto 0) => NLW_fbOutAddr_reg_PCOUT_UNCONNECTED(47 downto 0), RSTA => fbOutAddr_reg_i_3_n_0, RSTALLCARRYIN => '0', RSTALUMODE => '0', RSTB => '0', RSTC => fbOutAddr_reg_i_1_n_0, RSTCTRL => '0', RSTD => '0', RSTINMODE => '0', RSTM => '0', RSTP => fbOutAddr_reg_i_4_n_0, UNDERFLOW => NLW_fbOutAddr_reg_UNDERFLOW_UNCONNECTED ); fbOutAddr_reg_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"88808888" ) port map ( I0 => \h_count_reg__0\(9), I1 => \h_count_reg__0\(10), I2 => \h_count_reg__0\(8), I3 => fbOutAddr_reg_i_20_n_0, I4 => fbOutAddr_reg_i_21_n_0, O => fbOutAddr_reg_i_1_n_0 ); fbOutAddr_reg_i_10: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => Y(3), I1 => Y(1), I2 => Y(0), I3 => Y(2), I4 => \v_count_reg__0\(4), I5 => \v_count_reg__0\(5), O => fbOutAddr_reg_i_10_n_0 ); fbOutAddr_reg_i_11: unisim.vcomponents.LUT5 generic map( INIT => X"6AAAAAAA" ) port map ( I0 => \v_count_reg__0\(4), I1 => Y(2), I2 => Y(0), I3 => Y(1), I4 => Y(3), O => fbOutAddr_reg_i_11_n_0 ); fbOutAddr_reg_i_12: unisim.vcomponents.LUT5 generic map( INIT => X"6AAAAAAA" ) port map ( I0 => \h_count_reg__0\(10), I1 => \h_count_reg__0\(8), I2 => fbOutAddr_reg_i_27_n_0, I3 => \h_count_reg__0\(7), I4 => \h_count_reg__0\(9), O => fbOutAddr_reg_i_12_n_0 ); fbOutAddr_reg_i_13: unisim.vcomponents.LUT4 generic map( INIT => X"6AAA" ) port map ( I0 => \h_count_reg__0\(9), I1 => \h_count_reg__0\(7), I2 => fbOutAddr_reg_i_27_n_0, I3 => \h_count_reg__0\(8), O => fbOutAddr_reg_i_13_n_0 ); fbOutAddr_reg_i_14: unisim.vcomponents.LUT6 generic map( INIT => X"AAAA6AAAAAAAAAAA" ) port map ( I0 => \h_count_reg__0\(8), I1 => \h_count_reg__0\(6), I2 => \h_count_reg__0\(5), I3 => \h_count_reg__0\(4), I4 => fbOutAddr_reg_i_28_n_0, I5 => \h_count_reg__0\(7), O => fbOutAddr_reg_i_14_n_0 ); fbOutAddr_reg_i_15: unisim.vcomponents.LUT5 generic map( INIT => X"9AAAAAAA" ) port map ( I0 => \h_count_reg__0\(7), I1 => fbOutAddr_reg_i_28_n_0, I2 => \h_count_reg__0\(4), I3 => \h_count_reg__0\(5), I4 => \h_count_reg__0\(6), O => fbOutAddr_reg_i_15_n_0 ); fbOutAddr_reg_i_16: unisim.vcomponents.LUT4 generic map( INIT => X"BF40" ) port map ( I0 => fbOutAddr_reg_i_28_n_0, I1 => \h_count_reg__0\(4), I2 => \h_count_reg__0\(5), I3 => \h_count_reg__0\(6), O => fbOutAddr_reg_i_16_n_0 ); fbOutAddr_reg_i_17: unisim.vcomponents.LUT6 generic map( INIT => X"6AAAAAAAAAAAAAAA" ) port map ( I0 => \h_count_reg__0\(5), I1 => X(2), I2 => X(0), I3 => X(1), I4 => \h_count_reg__0\(3), I5 => \h_count_reg__0\(4), O => fbOutAddr_reg_i_17_n_0 ); fbOutAddr_reg_i_18: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => X(2), I1 => X(0), I2 => X(1), I3 => \h_count_reg__0\(3), I4 => \h_count_reg__0\(4), O => fbOutAddr_reg_i_18_n_0 ); fbOutAddr_reg_i_19: unisim.vcomponents.LUT4 generic map( INIT => X"6AAA" ) port map ( I0 => \h_count_reg__0\(3), I1 => X(2), I2 => X(0), I3 => X(1), O => fbOutAddr_reg_i_19_n_0 ); fbOutAddr_reg_i_2: unisim.vcomponents.LUT5 generic map( INIT => X"AAAABAAA" ) port map ( I0 => fbOutAddr_reg_i_22_n_0, I1 => X(2), I2 => enable, I3 => X(1), I4 => X(0), O => fbOutAddr_reg_i_2_n_0 ); fbOutAddr_reg_i_20: unisim.vcomponents.LUT3 generic map( INIT => X"A8" ) port map ( I0 => \h_count_reg__0\(7), I1 => \h_count_reg__0\(6), I2 => \h_count_reg__0\(5), O => fbOutAddr_reg_i_20_n_0 ); fbOutAddr_reg_i_21: unisim.vcomponents.LUT6 generic map( INIT => X"1555FFFFFFFFFFFF" ) port map ( I0 => \h_count_reg__0\(3), I1 => X(1), I2 => X(0), I3 => X(2), I4 => \h_count_reg__0\(7), I5 => \h_count_reg__0\(4), O => fbOutAddr_reg_i_21_n_0 ); fbOutAddr_reg_i_22: unisim.vcomponents.LUT4 generic map( INIT => X"4440" ) port map ( I0 => enable, I1 => \h_count_reg__0\(10), I2 => \h_count_reg__0\(8), I3 => \h_count_reg__0\(9), O => fbOutAddr_reg_i_22_n_0 ); fbOutAddr_reg_i_23: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => \v_count_reg__0\(6), I1 => \v_count_reg__0\(7), I2 => \v_count_reg__0\(9), I3 => \v_count_reg__0\(8), O => fbOutAddr_reg_i_23_n_0 ); fbOutAddr_reg_i_24: unisim.vcomponents.LUT3 generic map( INIT => X"7F" ) port map ( I0 => Y(1), I1 => Y(0), I2 => Y(2), O => fbOutAddr_reg_i_24_n_0 ); fbOutAddr_reg_i_25: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => Y(3), I1 => \v_count_reg__0\(4), O => fbOutAddr_reg_i_25_n_0 ); fbOutAddr_reg_i_26: unisim.vcomponents.LUT6 generic map( INIT => X"8000000000000000" ) port map ( I0 => \v_count_reg__0\(5), I1 => \v_count_reg__0\(4), I2 => Y(2), I3 => Y(0), I4 => Y(1), I5 => Y(3), O => fbOutAddr_reg_i_26_n_0 ); fbOutAddr_reg_i_27: unisim.vcomponents.LUT4 generic map( INIT => X"0080" ) port map ( I0 => \h_count_reg__0\(6), I1 => \h_count_reg__0\(5), I2 => \h_count_reg__0\(4), I3 => fbOutAddr_reg_i_28_n_0, O => fbOutAddr_reg_i_27_n_0 ); fbOutAddr_reg_i_28: unisim.vcomponents.LUT4 generic map( INIT => X"7FFF" ) port map ( I0 => X(2), I1 => X(0), I2 => X(1), I3 => \h_count_reg__0\(3), O => fbOutAddr_reg_i_28_n_0 ); fbOutAddr_reg_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"AA8A888800000000" ) port map ( I0 => fbOutAddr_reg_i_1_n_0, I1 => fbOutAddr_reg_i_23_n_0, I2 => fbOutAddr_reg_i_24_n_0, I3 => fbOutAddr_reg_i_25_n_0, I4 => \v_count_reg__0\(5), I5 => \v_count_reg__0\(10), O => fbOutAddr_reg_i_3_n_0 ); fbOutAddr_reg_i_4: unisim.vcomponents.LUT5 generic map( INIT => X"0000A800" ) port map ( I0 => \v_count_reg__0\(10), I1 => \h_count_reg__0\(9), I2 => \h_count_reg__0\(8), I3 => \h_count_reg__0\(10), I4 => enable, O => fbOutAddr_reg_i_4_n_0 ); fbOutAddr_reg_i_5: unisim.vcomponents.LUT6 generic map( INIT => X"6AAAAAAAAAAAAAAA" ) port map ( I0 => \v_count_reg__0\(10), I1 => \v_count_reg__0\(8), I2 => \v_count_reg__0\(6), I3 => fbOutAddr_reg_i_26_n_0, I4 => \v_count_reg__0\(7), I5 => \v_count_reg__0\(9), O => fbOutAddr_reg_i_5_n_0 ); fbOutAddr_reg_i_6: unisim.vcomponents.LUT5 generic map( INIT => X"6AAAAAAA" ) port map ( I0 => \v_count_reg__0\(9), I1 => \v_count_reg__0\(7), I2 => fbOutAddr_reg_i_26_n_0, I3 => \v_count_reg__0\(6), I4 => \v_count_reg__0\(8), O => fbOutAddr_reg_i_6_n_0 ); fbOutAddr_reg_i_7: unisim.vcomponents.LUT4 generic map( INIT => X"6AAA" ) port map ( I0 => \v_count_reg__0\(8), I1 => \v_count_reg__0\(6), I2 => fbOutAddr_reg_i_26_n_0, I3 => \v_count_reg__0\(7), O => fbOutAddr_reg_i_7_n_0 ); fbOutAddr_reg_i_8: unisim.vcomponents.LUT6 generic map( INIT => X"AA6AAAAAAAAAAAAA" ) port map ( I0 => \v_count_reg__0\(7), I1 => \v_count_reg__0\(5), I2 => \v_count_reg__0\(4), I3 => fbOutAddr_reg_i_24_n_0, I4 => Y(3), I5 => \v_count_reg__0\(6), O => fbOutAddr_reg_i_8_n_0 ); fbOutAddr_reg_i_9: unisim.vcomponents.LUT5 generic map( INIT => X"A6AAAAAA" ) port map ( I0 => \v_count_reg__0\(6), I1 => Y(3), I2 => fbOutAddr_reg_i_24_n_0, I3 => \v_count_reg__0\(4), I4 => \v_count_reg__0\(5), O => fbOutAddr_reg_i_9_n_0 ); g0_b0: unisim.vcomponents.LUT6 generic map( INIT => X"000007F807F80000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g0_b0_n_0 ); g0_b1: unisim.vcomponents.LUT6 generic map( INIT => X"01E00FFC08040000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g0_b1_n_0 ); g0_b2: unisim.vcomponents.LUT6 generic map( INIT => X"03F00F6C08940000" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g0_b2_n_0 ); g0_b2_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0002" ) port map ( I0 => nextChar(0), I1 => X(1), I2 => X(0), I3 => X(2), I4 => char(0), O => g0_b2_i_1_n_0 ); g0_b2_i_2: unisim.vcomponents.LUT5 generic map( INIT => X"FFFE0002" ) port map ( I0 => nextChar(1), I1 => X(1), I2 => X(0), I3 => X(2), I4 => char(1), O => g0_b2_i_2_n_0 ); g0_b3: unisim.vcomponents.LUT6 generic map( INIT => X"07F00E7C09840000" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g0_b3_n_0 ); g0_b4: unisim.vcomponents.LUT6 generic map( INIT => X"0FE00E7C09840000" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g0_b4_n_0 ); g0_b5: unisim.vcomponents.LUT6 generic map( INIT => X"07F00F6C08940000" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g0_b5_n_0 ); g0_b6: unisim.vcomponents.LUT6 generic map( INIT => X"03F00FFC08040000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g0_b6_n_0 ); g0_b7: unisim.vcomponents.LUT6 generic map( INIT => X"01E007F807F80000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g0_b7_n_0 ); g10_b0: unisim.vcomponents.LUT6 generic map( INIT => X"0000008000000000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g10_b0_n_0 ); g10_b1: unisim.vcomponents.LUT6 generic map( INIT => X"008002A000000000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g10_b1_n_0 ); g10_b2: unisim.vcomponents.LUT6 generic map( INIT => X"008003E0080403F0" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g10_b2_n_0 ); g10_b3: unisim.vcomponents.LUT6 generic map( INIT => X"03E001C00C0C07F8" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g10_b3_n_0 ); g10_b4: unisim.vcomponents.LUT6 generic map( INIT => X"03E001C007F80C0C" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g10_b4_n_0 ); g10_b5: unisim.vcomponents.LUT6 generic map( INIT => X"008003E003F00804" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g10_b5_n_0 ); g11_b0: unisim.vcomponents.LUT5 generic map( INIT => X"20000000" ) port map ( I0 => Y(1), I1 => \v_count_reg[2]_rep_n_0\, I2 => \v_count_reg[3]_rep_n_0\, I3 => \char[0]_i_1_n_0\, I4 => \char[1]_i_1_n_0\, O => g11_b0_n_0 ); g11_b1: unisim.vcomponents.LUT6 generic map( INIT => X"0600000000800000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g11_b1_n_0 ); g11_b2: unisim.vcomponents.LUT6 generic map( INIT => X"0300000000801000" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g11_b2_n_0 ); g11_b3: unisim.vcomponents.LUT6 generic map( INIT => X"01800C0000801E00" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g11_b3_n_0 ); g11_b4: unisim.vcomponents.LUT6 generic map( INIT => X"00C00C0000800E00" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g11_b4_n_0 ); g11_b5: unisim.vcomponents.LUT6 generic map( INIT => X"0060000000800000" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g11_b5_n_0 ); g11_b6: unisim.vcomponents.LUT6 generic map( INIT => X"0030000000800000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g11_b6_n_0 ); g12_b0: unisim.vcomponents.LUT6 generic map( INIT => X"04080E08000007F8" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g12_b0_n_0 ); g12_b1: unisim.vcomponents.LUT6 generic map( INIT => X"0C0C0F0C08100FFC" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g12_b1_n_0 ); g12_b2: unisim.vcomponents.LUT6 generic map( INIT => X"0844098408180984" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g12_b2_n_0 ); g12_b3: unisim.vcomponents.LUT6 generic map( INIT => X"084408C40FFC08C4" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g12_b3_n_0 ); g12_b4: unisim.vcomponents.LUT6 generic map( INIT => X"084408640FFC0864" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g12_b4_n_0 ); g12_b5: unisim.vcomponents.LUT6 generic map( INIT => X"0FFC0C3C08000FFC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g12_b5_n_0 ); g12_b6: unisim.vcomponents.LUT6 generic map( INIT => X"07B80C18080007F8" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g12_b6_n_0 ); g13_b0: unisim.vcomponents.LUT6 generic map( INIT => X"000C07F0047C00C0" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g13_b0_n_0 ); g13_b1: unisim.vcomponents.LUT6 generic map( INIT => X"000C0FF80C7C00E0" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g13_b1_n_0 ); g13_b2: unisim.vcomponents.LUT6 generic map( INIT => X"0F04084C084400B0" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g13_b2_n_0 ); g13_b3: unisim.vcomponents.LUT6 generic map( INIT => X"0F84084408440898" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g13_b3_n_0 ); g13_b4: unisim.vcomponents.LUT6 generic map( INIT => X"00C4084408440FFC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g13_b4_n_0 ); g13_b5: unisim.vcomponents.LUT6 generic map( INIT => X"007C0FC00FC40FFC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g13_b5_n_0 ); g13_b6: unisim.vcomponents.LUT6 generic map( INIT => X"003C078007840880" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g13_b6_n_0 ); g14_b0: unisim.vcomponents.LUT6 generic map( INIT => X"00000000003807B8" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g14_b0_n_0 ); g14_b1: unisim.vcomponents.LUT6 generic map( INIT => X"00000000087C0FFC" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g14_b1_n_0 ); g14_b2: unisim.vcomponents.LUT6 generic map( INIT => X"0800000008440844" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g14_b2_n_0 ); g14_b3: unisim.vcomponents.LUT6 generic map( INIT => X"0E30063008440844" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g14_b3_n_0 ); g14_b4: unisim.vcomponents.LUT6 generic map( INIT => X"063006300C440844" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g14_b4_n_0 ); g14_b5: unisim.vcomponents.LUT6 generic map( INIT => X"0000000007FC0FFC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g14_b5_n_0 ); g14_b6: unisim.vcomponents.LUT6 generic map( INIT => X"0000000003F807B8" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g14_b6_n_0 ); g15_b0: unisim.vcomponents.LUT6 generic map( INIT => X"0018000000000000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g15_b0_n_0 ); g15_b1: unisim.vcomponents.LUT6 generic map( INIT => X"001C080801200080" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g15_b1_n_0 ); g15_b2: unisim.vcomponents.LUT6 generic map( INIT => X"00040C18012001C0" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g15_b2_n_0 ); g15_b3: unisim.vcomponents.LUT6 generic map( INIT => X"0DC4063001200360" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g15_b3_n_0 ); g15_b4: unisim.vcomponents.LUT6 generic map( INIT => X"0DE4036001200630" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g15_b4_n_0 ); g15_b5: unisim.vcomponents.LUT6 generic map( INIT => X"003C01C001200C18" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g15_b5_n_0 ); g15_b6: unisim.vcomponents.LUT6 generic map( INIT => X"0018008001200808" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g15_b6_n_0 ); g16_b0: unisim.vcomponents.LUT6 generic map( INIT => X"03F008040FE007F8" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g16_b0_n_0 ); g16_b1: unisim.vcomponents.LUT6 generic map( INIT => X"07F80FFC0FF00FFC" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g16_b1_n_0 ); g16_b2: unisim.vcomponents.LUT6 generic map( INIT => X"0C0C0FFC00980804" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g16_b2_n_0 ); g16_b3: unisim.vcomponents.LUT6 generic map( INIT => X"08040844008C0BC4" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g16_b3_n_0 ); g16_b4: unisim.vcomponents.LUT6 generic map( INIT => X"0804084400980BC4" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g16_b4_n_0 ); g16_b5: unisim.vcomponents.LUT6 generic map( INIT => X"0C0C0FFC0FF00BFC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g16_b5_n_0 ); g16_b6: unisim.vcomponents.LUT6 generic map( INIT => X"061807B80FE001F8" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g16_b6_n_0 ); g17_b0: unisim.vcomponents.LUT6 generic map( INIT => X"03F0080408040804" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g17_b0_n_0 ); g17_b1: unisim.vcomponents.LUT6 generic map( INIT => X"07F80FFC0FFC0FFC" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g17_b1_n_0 ); g17_b2: unisim.vcomponents.LUT5 generic map( INIT => X"223E3E3E" ) port map ( I0 => \v_count_reg[1]_rep_n_0\, I1 => Y(2), I2 => \v_count_reg[3]_rep__0_n_0\, I3 => g0_b2_i_1_n_0, I4 => g0_b2_i_2_n_0, O => g17_b2_n_0 ); g17_b3: unisim.vcomponents.LUT6 generic map( INIT => X"0884084408440804" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g17_b3_n_0 ); g17_b4: unisim.vcomponents.LUT6 generic map( INIT => X"088400E408E40C0C" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g17_b4_n_0 ); g17_b5: unisim.vcomponents.LUT6 generic map( INIT => X"078C000C0C0C07F8" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g17_b5_n_0 ); g17_b6: unisim.vcomponents.LUT6 generic map( INIT => X"0F98001C0E1C03F0" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g17_b6_n_0 ); g18_b0: unisim.vcomponents.LUT6 generic map( INIT => X"0804070000000FFC" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g18_b0_n_0 ); g18_b1: unisim.vcomponents.LUT5 generic map( INIT => X"3E30003E" ) port map ( I0 => Y(1), I1 => \v_count_reg[2]_rep_n_0\, I2 => \v_count_reg[3]_rep_n_0\, I3 => \char[0]_i_1_n_0\, I4 => \char[1]_i_1_n_0\, O => g18_b1_n_0 ); g18_b2: unisim.vcomponents.LUT6 generic map( INIT => X"0FFC080008040040" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g18_b2_n_0 ); g18_b3: unisim.vcomponents.LUT6 generic map( INIT => X"00C008040FFC0040" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g18_b3_n_0 ); g18_b4: unisim.vcomponents.LUT6 generic map( INIT => X"01E00FFC0FFC0040" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g18_b4_n_0 ); g18_b5: unisim.vcomponents.LUT6 generic map( INIT => X"0F3C07FC08040FFC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g18_b5_n_0 ); g18_b6: unisim.vcomponents.LUT6 generic map( INIT => X"0E1C000400000FFC" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g18_b6_n_0 ); g19_b0: unisim.vcomponents.LUT6 generic map( INIT => X"07F80FFC0FFC0804" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g19_b0_n_0 ); g19_b1: unisim.vcomponents.LUT3 generic map( INIT => X"3E" ) port map ( I0 => Y(1), I1 => \v_count_reg[2]_rep_n_0\, I2 => \v_count_reg[3]_rep_n_0\, O => g19_b1_n_0 ); g19_b2: unisim.vcomponents.LUT6 generic map( INIT => X"0804003800380FFC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g19_b2_n_0 ); g19_b3: unisim.vcomponents.LUT6 generic map( INIT => X"0804007000700804" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g19_b3_n_0 ); g19_b4: unisim.vcomponents.LUT6 generic map( INIT => X"080400E000700800" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g19_b4_n_0 ); g19_b5: unisim.vcomponents.LUT6 generic map( INIT => X"0FFC0FFC00380C00" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g19_b5_n_0 ); g19_b6: unisim.vcomponents.LUT6 generic map( INIT => X"07F80FFC0FFC0E00" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g19_b6_n_0 ); g19_b7: unisim.vcomponents.LUT5 generic map( INIT => X"00003E00" ) port map ( I0 => Y(1), I1 => \v_count_reg[2]_rep_n_0\, I2 => \v_count_reg[3]_rep_n_0\, I3 => \char[0]_i_1_n_0\, I4 => \char[1]_i_1_n_0\, O => g19_b7_n_0 ); g1_b0: unisim.vcomponents.LUT6 generic map( INIT => X"000000C001C00080" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g1_b0_n_0 ); g1_b1: unisim.vcomponents.LUT6 generic map( INIT => X"000001E001C001C0" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g1_b1_n_0 ); g1_b2: unisim.vcomponents.LUT6 generic map( INIT => X"018009F009F003E0" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g1_b2_n_0 ); g1_b3: unisim.vcomponents.LUT6 generic map( INIT => X"03C00FF80E3807F0" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g1_b3_n_0 ); g1_b4: unisim.vcomponents.LUT6 generic map( INIT => X"03C00FF80E3803E0" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g1_b4_n_0 ); g1_b5: unisim.vcomponents.LUT6 generic map( INIT => X"018009F009F001C0" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g1_b5_n_0 ); g1_b6: unisim.vcomponents.LUT6 generic map( INIT => X"000001E001C00080" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g1_b6_n_0 ); g1_b7: unisim.vcomponents.LUT6 generic map( INIT => X"000000C001C00000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g1_b7_n_0 ); g20_b0: unisim.vcomponents.LUT6 generic map( INIT => X"0618080407F80804" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g20_b0_n_0 ); g20_b1: unisim.vcomponents.LUT6 generic map( INIT => X"0E3C0FFC0FFC0FFC" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g20_b1_n_0 ); g20_b2: unisim.vcomponents.LUT6 generic map( INIT => X"08640FFC08040FFC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g20_b2_n_0 ); g20_b3: unisim.vcomponents.LUT6 generic map( INIT => X"084400440E040844" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g20_b3_n_0 ); g20_b4: unisim.vcomponents.LUT6 generic map( INIT => X"08C400C43C040044" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g20_b4_n_0 ); g20_b5: unisim.vcomponents.LUT6 generic map( INIT => X"0F9C0FFC3FFC007C" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g20_b5_n_0 ); g20_b6: unisim.vcomponents.LUT6 generic map( INIT => X"07180F3827F80038" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g20_b6_n_0 ); g21_b0: unisim.vcomponents.LUT6 generic map( INIT => X"03FC01FC07FC001C" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g21_b0_n_0 ); g21_b1: unisim.vcomponents.LUT5 generic map( INIT => X"3E1E3E02" ) port map ( I0 => Y(1), I1 => \v_count_reg[2]_rep_n_0\, I2 => \v_count_reg[3]_rep_n_0\, I3 => \char[0]_i_1_n_0\, I4 => \char[1]_i_1_n_0\, O => g21_b1_n_0 ); g21_b2: unisim.vcomponents.LUT6 generic map( INIT => X"0E00060008000804" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g21_b2_n_0 ); g21_b3: unisim.vcomponents.LUT6 generic map( INIT => X"03800C0008000FFC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g21_b3_n_0 ); g21_b5: unisim.vcomponents.LUT6 generic map( INIT => X"0E0006000FFC0804" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g21_b5_n_0 ); g21_b6: unisim.vcomponents.LUT6 generic map( INIT => X"0FFC03FC07FC000C" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g21_b6_n_0 ); g21_b7: unisim.vcomponents.LUT6 generic map( INIT => X"03FC01FC0000001C" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g21_b7_n_0 ); g22_b0: unisim.vcomponents.LUT6 generic map( INIT => X"00000E1C001C0C0C" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g22_b0_n_0 ); g22_b1: unisim.vcomponents.LUT6 generic map( INIT => X"00000F0C003C0E1C" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g22_b1_n_0 ); g22_b2: unisim.vcomponents.LUT6 generic map( INIT => X"0FFC098408600330" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g22_b2_n_0 ); g22_b3: unisim.vcomponents.LUT6 generic map( INIT => X"0FFC08C40FC001E0" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g22_b3_n_0 ); g22_b4: unisim.vcomponents.LUT6 generic map( INIT => X"080408640FC001E0" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g22_b4_n_0 ); g22_b5: unisim.vcomponents.LUT6 generic map( INIT => X"0804083408600330" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g22_b5_n_0 ); g22_b6: unisim.vcomponents.LUT6 generic map( INIT => X"00000C1C003C0E1C" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g22_b6_n_0 ); g22_b7: unisim.vcomponents.LUT6 generic map( INIT => X"00000E0C001C0C0C" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g22_b7_n_0 ); g23_b0: unisim.vcomponents.LUT6 generic map( INIT => X"2000000800000038" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g23_b0_n_0 ); g23_b1: unisim.vcomponents.LUT6 generic map( INIT => X"2000000C00000070" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g23_b1_n_0 ); g23_b2: unisim.vcomponents.LUT6 generic map( INIT => X"20000006080400E0" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g23_b2_n_0 ); g23_b3: unisim.vcomponents.LUT6 generic map( INIT => X"20000003080401C0" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g23_b3_n_0 ); g23_b4: unisim.vcomponents.LUT6 generic map( INIT => X"200000060FFC0380" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g23_b4_n_0 ); g23_b5: unisim.vcomponents.LUT6 generic map( INIT => X"2000000C0FFC0700" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g23_b5_n_0 ); g23_b6: unisim.vcomponents.LUT6 generic map( INIT => X"2000000800000E00" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g23_b6_n_0 ); g23_b7: unisim.vcomponents.LUT6 generic map( INIT => X"2000000000000000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g23_b7_n_0 ); g24_b0: unisim.vcomponents.LUT6 generic map( INIT => X"07C0000407000000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g24_b0_n_0 ); g24_b1: unisim.vcomponents.LUT6 generic map( INIT => X"0FE00FFC0FA00000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g24_b1_n_0 ); g24_b2: unisim.vcomponents.LUT6 generic map( INIT => X"08200FFC08A00003" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g24_b2_n_0 ); g24_b3: unisim.vcomponents.LUT6 generic map( INIT => X"0820082008A00007" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g24_b3_n_0 ); g24_b4: unisim.vcomponents.LUT6 generic map( INIT => X"0820086007E00004" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g24_b4_n_0 ); g24_b5: unisim.vcomponents.LUT6 generic map( INIT => X"0C600FC00FC00000" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g24_b5_n_0 ); g24_b6: unisim.vcomponents.LUT6 generic map( INIT => X"0440078008000000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g24_b6_n_0 ); g25_b0: unisim.vcomponents.LUT6 generic map( INIT => X"27C0084007C00780" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g25_b0_n_0 ); g25_b1: unisim.vcomponents.LUT6 generic map( INIT => X"6FE00FF80FE00FC0" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g25_b1_n_0 ); g25_b2: unisim.vcomponents.LUT6 generic map( INIT => X"48200FFC08A00860" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g25_b2_n_0 ); g25_b3: unisim.vcomponents.LUT6 generic map( INIT => X"4820084408A00824" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g25_b3_n_0 ); g25_b4: unisim.vcomponents.LUT6 generic map( INIT => X"7FC0000C08A007FC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g25_b4_n_0 ); g25_b5: unisim.vcomponents.LUT6 generic map( INIT => X"3FE000180CE00FFC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g25_b5_n_0 ); g25_b6: unisim.vcomponents.LUT6 generic map( INIT => X"0020000004C00800" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g25_b6_n_0 ); g26_b0: unisim.vcomponents.LUT6 generic map( INIT => X"0804000000000804" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g26_b0_n_0 ); g26_b1: unisim.vcomponents.LUT5 generic map( INIT => X"3E40003E" ) port map ( I0 => Y(1), I1 => \v_count_reg[2]_rep_n_0\, I2 => \v_count_reg[3]_rep_n_0\, I3 => \char[0]_i_1_n_0\, I4 => \char[1]_i_1_n_0\, O => g26_b1_n_0 ); g26_b2: unisim.vcomponents.LUT6 generic map( INIT => X"0FFC700008200FFC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g26_b2_n_0 ); g26_b3: unisim.vcomponents.LUT6 generic map( INIT => X"018040000FEC0040" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g26_b3_n_0 ); g26_b4: unisim.vcomponents.LUT6 generic map( INIT => X"03C040200FEC0020" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g26_b4_n_0 ); g26_b5: unisim.vcomponents.LUT6 generic map( INIT => X"0E607FEC08000FE0" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g26_b5_n_0 ); g26_b6: unisim.vcomponents.LUT6 generic map( INIT => X"0C203FEC00000FC0" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g26_b6_n_0 ); g27_b0: unisim.vcomponents.LUT6 generic map( INIT => X"07C000200FE00000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g27_b0_n_0 ); g27_b1: unisim.vcomponents.LUT6 generic map( INIT => X"0FE00FE00FE00000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g27_b1_n_0 ); g27_b2: unisim.vcomponents.LUT6 generic map( INIT => X"08200FC000600804" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g27_b2_n_0 ); g27_b3: unisim.vcomponents.LUT6 generic map( INIT => X"082000200FC00FFC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g27_b3_n_0 ); g27_b5: unisim.vcomponents.LUT6 generic map( INIT => X"0FE00FE000600800" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g27_b5_n_0 ); g27_b6: unisim.vcomponents.LUT6 generic map( INIT => X"07C00FC00FE00000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g27_b6_n_0 ); g27_b7: unisim.vcomponents.LUT5 generic map( INIT => X"00003800" ) port map ( I0 => Y(1), I1 => \v_count_reg[2]_rep_n_0\, I2 => \v_count_reg[3]_rep_n_0\, I3 => \char[0]_i_1_n_0\, I4 => \char[1]_i_1_n_0\, O => g27_b7_n_0 ); g28_b0: unisim.vcomponents.LUT6 generic map( INIT => X"0440082007C04020" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g28_b0_n_0 ); g28_b1: unisim.vcomponents.LUT6 generic map( INIT => X"0CE00FE00FE07FE0" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g28_b1_n_0 ); g28_b2: unisim.vcomponents.LUT6 generic map( INIT => X"09A00FC008207FC0" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g28_b2_n_0 ); g28_b3: unisim.vcomponents.LUT6 generic map( INIT => X"0920086048204820" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g28_b3_n_0 ); g28_b4: unisim.vcomponents.LUT6 generic map( INIT => X"0B2000207FC00820" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g28_b4_n_0 ); g28_b5: unisim.vcomponents.LUT6 generic map( INIT => X"0E6000E07FE00FE0" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g28_b5_n_0 ); g28_b6: unisim.vcomponents.LUT6 generic map( INIT => X"044000C0402007C0" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g28_b6_n_0 ); g29_b0: unisim.vcomponents.LUT6 generic map( INIT => X"07E001E007E00020" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g29_b0_n_0 ); g29_b1: unisim.vcomponents.LUT6 generic map( INIT => X"0FE003E00FE00020" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g29_b1_n_0 ); g29_b2: unisim.vcomponents.LUT6 generic map( INIT => X"0C000600080007F8" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g29_b2_n_0 ); g29_b3: unisim.vcomponents.LUT6 generic map( INIT => X"07000C0008000FFC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g29_b3_n_0 ); g29_b4: unisim.vcomponents.LUT6 generic map( INIT => X"07000C0007E00820" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g29_b4_n_0 ); g29_b5: unisim.vcomponents.LUT6 generic map( INIT => X"0C0006000FE00C20" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g29_b5_n_0 ); g29_b6: unisim.vcomponents.LUT6 generic map( INIT => X"0FE003E008000400" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g29_b6_n_0 ); g29_b7: unisim.vcomponents.LUT6 generic map( INIT => X"07E001E000000000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g29_b7_n_0 ); g2_b0: unisim.vcomponents.LUT6 generic map( INIT => X"0780FFFF0000FFFF" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g2_b0_n_0 ); g2_b1: unisim.vcomponents.LUT5 generic map( INIT => X"38E718FF" ) port map ( I0 => Y(1), I1 => \v_count_reg[2]_rep_n_0\, I2 => \v_count_reg[3]_rep_n_0\, I3 => \char[0]_i_1_n_0\, I4 => \char[1]_i_1_n_0\, O => g2_b1_n_0 ); g2_b2: unisim.vcomponents.LUT6 generic map( INIT => X"0860F99F0660FE7F" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g2_b2_n_0 ); g2_b3: unisim.vcomponents.LUT6 generic map( INIT => X"0874FBDF0420FC3F" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g2_b3_n_0 ); g2_b4: unisim.vcomponents.LUT6 generic map( INIT => X"0FDCFBDF0420FC3F" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g2_b4_n_0 ); g2_b5: unisim.vcomponents.LUT6 generic map( INIT => X"078CF99F0660FE7F" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g2_b5_n_0 ); g2_b6: unisim.vcomponents.LUT5 generic map( INIT => X"06E718FF" ) port map ( I0 => Y(1), I1 => \v_count_reg[2]_rep_n_0\, I2 => \v_count_reg[3]_rep_n_0\, I3 => \char[0]_i_1_n_0\, I4 => \char[1]_i_1_n_0\, O => g2_b6_n_0 ); g2_b7: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \char[0]_i_1_n_0\, O => g2_b7_n_0 ); g30_b0: unisim.vcomponents.LUT6 generic map( INIT => X"00000C6047E00820" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g30_b0_n_0 ); g30_b1: unisim.vcomponents.LUT6 generic map( INIT => X"00400E604FE00C60" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g30_b1_n_0 ); g30_b2: unisim.vcomponents.LUT6 generic map( INIT => X"00400B20480006C0" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g30_b2_n_0 ); g30_b3: unisim.vcomponents.LUT6 generic map( INIT => X"07F809A048000380" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g30_b3_n_0 ); g30_b4: unisim.vcomponents.LUT6 generic map( INIT => X"0FBC08E068000380" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g30_b4_n_0 ); g30_b5: unisim.vcomponents.LUT6 generic map( INIT => X"08040C603FE006C0" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g30_b5_n_0 ); g30_b6: unisim.vcomponents.LUT6 generic map( INIT => X"08040C201FE00C60" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g30_b6_n_0 ); g30_b7: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000820" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g30_b7_n_0 ); g31_b0: unisim.vcomponents.LUT6 generic map( INIT => X"0780000800000000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g31_b0_n_0 ); g31_b1: unisim.vcomponents.LUT6 generic map( INIT => X"07C0000C08040000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g31_b1_n_0 ); g31_b2: unisim.vcomponents.LUT6 generic map( INIT => X"0460000408040000" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g31_b2_n_0 ); g31_b3: unisim.vcomponents.LUT6 generic map( INIT => X"0430000C0FBC0FBC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g31_b3_n_0 ); g31_b4: unisim.vcomponents.LUT6 generic map( INIT => X"0460000807F80FBC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g31_b4_n_0 ); g31_b5: unisim.vcomponents.LUT6 generic map( INIT => X"07C0000C00400000" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g31_b5_n_0 ); g31_b6: unisim.vcomponents.LUT6 generic map( INIT => X"0780000400400000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g31_b6_n_0 ); g3_b0: unisim.vcomponents.LUT6 generic map( INIT => X"02A01C000C000000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g3_b0_n_0 ); g3_b1: unisim.vcomponents.LUT6 generic map( INIT => X"02A01FFC0E000278" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g3_b1_n_0 ); g3_b2: unisim.vcomponents.LUT6 generic map( INIT => X"01C00FFC0FFC02FC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g3_b2_n_0 ); g3_b3: unisim.vcomponents.LUT6 generic map( INIT => X"0F78001407FC0F84" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g3_b3_n_0 ); g3_b4: unisim.vcomponents.LUT6 generic map( INIT => X"0F78001400140F84" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g3_b4_n_0 ); g3_b5: unisim.vcomponents.LUT6 generic map( INIT => X"01C00E14001402FC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g3_b5_n_0 ); g3_b6: unisim.vcomponents.LUT6 generic map( INIT => X"02A00FFC001C0278" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g3_b6_n_0 ); g3_b7: unisim.vcomponents.LUT6 generic map( INIT => X"02A007FC001C0000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g3_b7_n_0 ); g4_b0: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000400FFE" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g4_b0_n_0 ); g4_b1: unisim.vcomponents.LUT6 generic map( INIT => X"0DFC0110004007FC" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g4_b1_n_0 ); g4_b2: unisim.vcomponents.LUT6 generic map( INIT => X"0DFC031800E003F8" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g4_b2_n_0 ); g4_b3: unisim.vcomponents.LUT6 generic map( INIT => X"000007FC01F001F0" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g4_b3_n_0 ); g4_b4: unisim.vcomponents.LUT6 generic map( INIT => X"000007FC03F800E0" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g4_b4_n_0 ); g4_b5: unisim.vcomponents.LUT6 generic map( INIT => X"0DFC031807FC0040" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g4_b5_n_0 ); g4_b6: unisim.vcomponents.LUT6 generic map( INIT => X"0DFC01100FFE0040" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g4_b6_n_0 ); g5_b0: unisim.vcomponents.LUT6 generic map( INIT => X"00000F0008C40038" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g5_b0_n_0 ); g5_b1: unisim.vcomponents.LUT6 generic map( INIT => X"09100F0019EE007C" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g5_b1_n_0 ); g5_b2: unisim.vcomponents.LUT6 generic map( INIT => X"1B180F00133A0044" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g5_b2_n_0 ); g5_b3: unisim.vcomponents.LUT6 generic map( INIT => X"1FFC0F0012120FFC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g5_b3_n_0 ); g5_b4: unisim.vcomponents.LUT6 generic map( INIT => X"0FFC0F0017320FFC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g5_b4_n_0 ); g5_b5: unisim.vcomponents.LUT6 generic map( INIT => X"0B180F001DE60004" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g5_b5_n_0 ); g5_b6: unisim.vcomponents.LUT6 generic map( INIT => X"09100F0008C40FFC" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g5_b6_n_0 ); g5_b7: unisim.vcomponents.LUT5 generic map( INIT => X"0000003E" ) port map ( I0 => Y(1), I1 => \v_count_reg[2]_rep_n_0\, I2 => \v_count_reg[3]_rep_n_0\, I3 => \char[0]_i_1_n_0\, I4 => \char[1]_i_1_n_0\, O => g5_b7_n_0 ); g6_b0: unisim.vcomponents.LUT5 generic map( INIT => X"00800000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[1]_i_1_n_0\, O => g6_b0_n_0 ); g6_b1: unisim.vcomponents.LUT6 generic map( INIT => X"01C0008002000010" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g6_b1_n_0 ); g6_b2: unisim.vcomponents.LUT6 generic map( INIT => X"03E0008006000018" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g6_b2_n_0 ); g6_b3: unisim.vcomponents.LUT5 generic map( INIT => X"02A00FFC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_2_n_0, O => g6_b3_n_0 ); g6_b4: unisim.vcomponents.LUT6 generic map( INIT => X"008003E00FFC0FFC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g6_b4_n_0 ); g6_b5: unisim.vcomponents.LUT6 generic map( INIT => X"008001C006000018" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g6_b5_n_0 ); g6_b6: unisim.vcomponents.LUT6 generic map( INIT => X"0080008002000010" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g6_b6_n_0 ); g7_b0: unisim.vcomponents.LUT6 generic map( INIT => X"00300600008003C0" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g7_b0_n_0 ); g7_b1: unisim.vcomponents.LUT6 generic map( INIT => X"00F0078001C003C0" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g7_b1_n_0 ); g7_b2: unisim.vcomponents.LUT6 generic map( INIT => X"03F007E003E00200" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g7_b2_n_0 ); g7_b3: unisim.vcomponents.LUT6 generic map( INIT => X"07F007F000800200" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g7_b3_n_0 ); g7_b4: unisim.vcomponents.LUT6 generic map( INIT => X"03F007E000800200" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g7_b4_n_0 ); g7_b5: unisim.vcomponents.LUT6 generic map( INIT => X"00F0078003E00200" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g7_b5_n_0 ); g7_b6: unisim.vcomponents.LUT6 generic map( INIT => X"0030060001C00200" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g7_b6_n_0 ); g7_b7: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000800000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g7_b7_n_0 ); g8_b0: unisim.vcomponents.LUT6 generic map( INIT => X"0220000000000000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g8_b0_n_0 ); g8_b1: unisim.vcomponents.LUT6 generic map( INIT => X"0FF8000E00000000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g8_b1_n_0 ); g8_b2: unisim.vcomponents.LUT6 generic map( INIT => X"0FF8001E00380000" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g8_b2_n_0 ); g8_b3: unisim.vcomponents.LUT6 generic map( INIT => X"022000000DFC0000" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g8_b3_n_0 ); g8_b4: unisim.vcomponents.LUT6 generic map( INIT => X"0FF800000DFC0000" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g8_b4_n_0 ); g8_b6: unisim.vcomponents.LUT6 generic map( INIT => X"0220000E00000000" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g8_b6_n_0 ); g9_b0: unisim.vcomponents.LUT6 generic map( INIT => X"000007800C300638" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g9_b0_n_0 ); g9_b1: unisim.vcomponents.LUT6 generic map( INIT => X"00100FD806300C7C" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g9_b1_n_0 ); g9_b2: unisim.vcomponents.LUT6 generic map( INIT => X"001E087C03000844" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g9_b2_n_0 ); g9_b3: unisim.vcomponents.LUT6 generic map( INIT => X"000E08E401803847" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g9_b3_n_0 ); g9_b4: unisim.vcomponents.LUT6 generic map( INIT => X"000007BC00C03847" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g9_b4_n_0 ); g9_b5: unisim.vcomponents.LUT6 generic map( INIT => X"00000FD80C600FCC" ) port map ( I0 => Y(0), I1 => \v_count_reg[1]_rep_n_0\, I2 => Y(2), I3 => \v_count_reg[3]_rep__0_n_0\, I4 => g0_b2_i_1_n_0, I5 => g0_b2_i_2_n_0, O => g9_b5_n_0 ); g9_b6: unisim.vcomponents.LUT6 generic map( INIT => X"000008400C300798" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => \v_count_reg[3]_rep_n_0\, I4 => \char[0]_i_1_n_0\, I5 => \char[1]_i_1_n_0\, O => g9_b6_n_0 ); hSync_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"00000000AAFFAFC0" ) port map ( I0 => hSync_i_2_n_0, I1 => \h_count_reg__0\(4), I2 => \h_count_reg__0\(5), I3 => \h_count_reg__0\(7), I4 => \h_count_reg__0\(6), I5 => hSync_i_3_n_0, O => hSync_i_1_n_0 ); hSync_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000001" ) port map ( I0 => X(2), I1 => X(0), I2 => X(1), I3 => \h_count_reg__0\(3), I4 => \h_count_reg__0\(4), I5 => \h_count_reg__0\(6), O => hSync_i_2_n_0 ); hSync_i_3: unisim.vcomponents.LUT3 generic map( INIT => X"BF" ) port map ( I0 => \h_count_reg__0\(9), I1 => \h_count_reg__0\(8), I2 => \h_count_reg__0\(10), O => hSync_i_3_n_0 ); hSync_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => '1', D => hSync_i_1_n_0, Q => Hsync_OBUF, R => '0' ); \h_count[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => X(0), O => p_0_in(0) ); \h_count[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => X(0), I1 => X(1), O => p_0_in(1) ); \h_count[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => X(2), I1 => X(1), I2 => X(0), O => \h_count[2]_i_1_n_0\ ); \h_count_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => '1', D => p_0_in(0), Q => X(0), R => fbOutAddr_reg_i_1_n_0 ); \h_count_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => '1', D => fbOutAddr_reg_i_12_n_0, Q => \h_count_reg__0\(10), R => fbOutAddr_reg_i_1_n_0 ); \h_count_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => '1', D => p_0_in(1), Q => X(1), R => fbOutAddr_reg_i_1_n_0 ); \h_count_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => '1', D => \h_count[2]_i_1_n_0\, Q => X(2), R => fbOutAddr_reg_i_1_n_0 ); \h_count_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => '1', D => fbOutAddr_reg_i_19_n_0, Q => \h_count_reg__0\(3), R => fbOutAddr_reg_i_1_n_0 ); \h_count_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => '1', D => fbOutAddr_reg_i_18_n_0, Q => \h_count_reg__0\(4), R => fbOutAddr_reg_i_1_n_0 ); \h_count_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => '1', D => fbOutAddr_reg_i_17_n_0, Q => \h_count_reg__0\(5), R => fbOutAddr_reg_i_1_n_0 ); \h_count_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => '1', D => fbOutAddr_reg_i_16_n_0, Q => \h_count_reg__0\(6), R => fbOutAddr_reg_i_1_n_0 ); \h_count_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => '1', D => fbOutAddr_reg_i_15_n_0, Q => \h_count_reg__0\(7), R => fbOutAddr_reg_i_1_n_0 ); \h_count_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => '1', D => fbOutAddr_reg_i_14_n_0, Q => \h_count_reg__0\(8), R => fbOutAddr_reg_i_1_n_0 ); \h_count_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => '1', D => fbOutAddr_reg_i_13_n_0, Q => \h_count_reg__0\(9), R => fbOutAddr_reg_i_1_n_0 ); \nextChar[7]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"1000" ) port map ( I0 => X(1), I1 => X(0), I2 => enable, I3 => X(2), O => \nextChar[7]_i_1_n_0\ ); \nextChar_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => \nextChar[7]_i_1_n_0\, D => D(0), Q => nextChar(0), R => '0' ); \nextChar_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => \nextChar[7]_i_1_n_0\, D => D(1), Q => nextChar(1), R => '0' ); \nextChar_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => \nextChar[7]_i_1_n_0\, D => D(2), Q => nextChar(2), R => '0' ); \nextChar_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => \nextChar[7]_i_1_n_0\, D => D(3), Q => nextChar(3), R => '0' ); \nextChar_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => \nextChar[7]_i_1_n_0\, D => D(4), Q => nextChar(4), R => '0' ); \nextChar_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => \nextChar[7]_i_1_n_0\, D => D(5), Q => nextChar(5), R => '0' ); \nextChar_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => \nextChar[7]_i_1_n_0\, D => D(6), Q => nextChar(6), R => '0' ); \nextChar_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => \nextChar[7]_i_1_n_0\, D => D(7), Q => nextChar(7), R => '0' ); vSync_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"0000001E" ) port map ( I0 => \v_count_reg[0]_rep_n_0\, I1 => Y(1), I2 => \v_count_reg[2]_rep_n_0\, I3 => vSync_i_2_n_0, I4 => fbOutAddr_reg_i_23_n_0, O => vSync_i_1_n_0 ); vSync_i_2: unisim.vcomponents.LUT4 generic map( INIT => X"FFEF" ) port map ( I0 => \v_count_reg__0\(4), I1 => Y(3), I2 => \v_count_reg__0\(10), I3 => \v_count_reg__0\(5), O => vSync_i_2_n_0 ); vSync_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => '1', D => vSync_i_1_n_0, Q => Vsync_OBUF, R => '0' ); \v_count[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => Y(0), O => \p_0_in__0\(0) ); \v_count[0]_rep_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => Y(0), O => \v_count[0]_rep_i_1_n_0\ ); \v_count[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => Y(0), I1 => Y(1), O => \p_0_in__0\(1) ); \v_count[1]_rep_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => Y(0), I1 => Y(1), O => \v_count[1]_rep_i_1_n_0\ ); \v_count[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => Y(2), I1 => Y(0), I2 => Y(1), O => \p_0_in__0\(2) ); \v_count[2]_rep_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"6A" ) port map ( I0 => Y(2), I1 => Y(0), I2 => Y(1), O => \v_count[2]_rep_i_1_n_0\ ); \v_count[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"6AAA" ) port map ( I0 => Y(3), I1 => Y(1), I2 => Y(0), I3 => Y(2), O => \p_0_in__0\(3) ); \v_count[3]_rep__0_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"6AAA" ) port map ( I0 => Y(3), I1 => Y(1), I2 => Y(0), I3 => Y(2), O => \v_count[3]_rep__0_i_1_n_0\ ); \v_count[3]_rep_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"6AAA" ) port map ( I0 => Y(3), I1 => Y(1), I2 => Y(0), I3 => Y(2), O => \v_count[3]_rep_i_1_n_0\ ); \v_count_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => fbOutAddr_reg_i_1_n_0, D => \p_0_in__0\(0), Q => Y(0), R => fbOutAddr_reg_i_3_n_0 ); \v_count_reg[0]_rep\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => fbOutAddr_reg_i_1_n_0, D => \v_count[0]_rep_i_1_n_0\, Q => \v_count_reg[0]_rep_n_0\, R => fbOutAddr_reg_i_3_n_0 ); \v_count_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => fbOutAddr_reg_i_1_n_0, D => fbOutAddr_reg_i_5_n_0, Q => \v_count_reg__0\(10), R => fbOutAddr_reg_i_3_n_0 ); \v_count_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => fbOutAddr_reg_i_1_n_0, D => \p_0_in__0\(1), Q => Y(1), R => fbOutAddr_reg_i_3_n_0 ); \v_count_reg[1]_rep\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => fbOutAddr_reg_i_1_n_0, D => \v_count[1]_rep_i_1_n_0\, Q => \v_count_reg[1]_rep_n_0\, R => fbOutAddr_reg_i_3_n_0 ); \v_count_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => fbOutAddr_reg_i_1_n_0, D => \p_0_in__0\(2), Q => Y(2), R => fbOutAddr_reg_i_3_n_0 ); \v_count_reg[2]_rep\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => fbOutAddr_reg_i_1_n_0, D => \v_count[2]_rep_i_1_n_0\, Q => \v_count_reg[2]_rep_n_0\, R => fbOutAddr_reg_i_3_n_0 ); \v_count_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => fbOutAddr_reg_i_1_n_0, D => \p_0_in__0\(3), Q => Y(3), R => fbOutAddr_reg_i_3_n_0 ); \v_count_reg[3]_rep\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => fbOutAddr_reg_i_1_n_0, D => \v_count[3]_rep_i_1_n_0\, Q => \v_count_reg[3]_rep_n_0\, R => fbOutAddr_reg_i_3_n_0 ); \v_count_reg[3]_rep__0\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => fbOutAddr_reg_i_1_n_0, D => \v_count[3]_rep__0_i_1_n_0\, Q => \v_count_reg[3]_rep__0_n_0\, R => fbOutAddr_reg_i_3_n_0 ); \v_count_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => fbOutAddr_reg_i_1_n_0, D => fbOutAddr_reg_i_11_n_0, Q => \v_count_reg__0\(4), R => fbOutAddr_reg_i_3_n_0 ); \v_count_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => fbOutAddr_reg_i_1_n_0, D => fbOutAddr_reg_i_10_n_0, Q => \v_count_reg__0\(5), R => fbOutAddr_reg_i_3_n_0 ); \v_count_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => fbOutAddr_reg_i_1_n_0, D => fbOutAddr_reg_i_9_n_0, Q => \v_count_reg__0\(6), R => fbOutAddr_reg_i_3_n_0 ); \v_count_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => fbOutAddr_reg_i_1_n_0, D => fbOutAddr_reg_i_8_n_0, Q => \v_count_reg__0\(7), R => fbOutAddr_reg_i_3_n_0 ); \v_count_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => fbOutAddr_reg_i_1_n_0, D => fbOutAddr_reg_i_7_n_0, Q => \v_count_reg__0\(8), R => fbOutAddr_reg_i_3_n_0 ); \v_count_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => fbOutAddr_reg_i_1_n_0, D => fbOutAddr_reg_i_6_n_0, Q => \v_count_reg__0\(9), R => fbOutAddr_reg_i_3_n_0 ); \vgaRed[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"28222888" ) port map ( I0 => enable, I1 => \char[7]_i_1_n_0\, I2 => \vgaRed_reg[0]_i_2_n_0\, I3 => X(2), I4 => \vgaRed_reg[0]_i_3_n_0\, O => \vgaRed[0]_i_1_n_0\ ); \vgaRed[0]_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \vgaRed_reg[0]_i_32_n_0\, I1 => \vgaRed[0]_i_33_n_0\, I2 => \char[5]_i_1_n_0\, I3 => \vgaRed[0]_i_34_n_0\, I4 => \char[4]_i_1_n_0\, I5 => \vgaRed_reg[0]_i_35_n_0\, O => \vgaRed[0]_i_10_n_0\ ); \vgaRed[0]_i_11\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \vgaRed_reg[0]_i_36_n_0\, I1 => \vgaRed_reg[0]_i_37_n_0\, I2 => \char[5]_i_1_n_0\, I3 => \vgaRed_reg[0]_i_38_n_0\, I4 => \char[4]_i_1_n_0\, I5 => \vgaRed_reg[0]_i_39_n_0\, O => \vgaRed[0]_i_11_n_0\ ); \vgaRed[0]_i_13\: unisim.vcomponents.LUT6 generic map( INIT => X"0020FFFF00200000" ) port map ( I0 => g10_b0_n_0, I1 => \char[2]_i_1_n_0\, I2 => \char[3]_i_1_n_0\, I3 => \char[4]_i_1_n_0\, I4 => \char[5]_i_1_n_0\, I5 => \vgaRed[0]_i_42_n_0\, O => \vgaRed[0]_i_13_n_0\ ); \vgaRed[0]_i_14\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \vgaRed_reg[0]_i_43_n_0\, I1 => \vgaRed_reg[0]_i_44_n_0\, I2 => \char[5]_i_1_n_0\, I3 => \vgaRed_reg[0]_i_45_n_0\, I4 => \char[4]_i_1_n_0\, I5 => \vgaRed_reg[0]_i_46_n_0\, O => \vgaRed[0]_i_14_n_0\ ); \vgaRed[0]_i_15\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \vgaRed_reg[0]_i_47_n_0\, I1 => \vgaRed[0]_i_48_n_0\, I2 => \char[5]_i_1_n_0\, I3 => \vgaRed_reg[0]_i_49_n_0\, I4 => \char[4]_i_1_n_0\, I5 => \vgaRed_reg[0]_i_50_n_0\, O => \vgaRed[0]_i_15_n_0\ ); \vgaRed[0]_i_16\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \vgaRed_reg[0]_i_51_n_0\, I1 => \vgaRed_reg[0]_i_52_n_0\, I2 => \char[5]_i_1_n_0\, I3 => \vgaRed_reg[0]_i_53_n_0\, I4 => \char[4]_i_1_n_0\, I5 => \vgaRed_reg[0]_i_54_n_0\, O => \vgaRed[0]_i_16_n_0\ ); \vgaRed[0]_i_17\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \vgaRed_reg[0]_i_55_n_0\, I1 => \vgaRed[0]_i_56_n_0\, I2 => \char[5]_i_1_n_0\, I3 => \vgaRed_reg[0]_i_57_n_0\, I4 => \char[4]_i_1_n_0\, I5 => \vgaRed_reg[0]_i_58_n_0\, O => \vgaRed[0]_i_17_n_0\ ); \vgaRed[0]_i_18\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \vgaRed_reg[0]_i_59_n_0\, I1 => \vgaRed_reg[0]_i_60_n_0\, I2 => \char[5]_i_1_n_0\, I3 => \vgaRed_reg[0]_i_61_n_0\, I4 => \char[4]_i_1_n_0\, I5 => \vgaRed_reg[0]_i_62_n_0\, O => \vgaRed[0]_i_18_n_0\ ); \vgaRed[0]_i_19\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \vgaRed_reg[0]_i_63_n_0\, I1 => \vgaRed[0]_i_64_n_0\, I2 => \char[5]_i_1_n_0\, I3 => \vgaRed_reg[0]_i_65_n_0\, I4 => \char[4]_i_1_n_0\, I5 => \vgaRed_reg[0]_i_66_n_0\, O => \vgaRed[0]_i_19_n_0\ ); \vgaRed[0]_i_20\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \vgaRed_reg[0]_i_67_n_0\, I1 => \vgaRed[0]_i_68_n_0\, I2 => \char[5]_i_1_n_0\, I3 => \vgaRed[0]_i_69_n_0\, I4 => \char[4]_i_1_n_0\, I5 => \vgaRed_reg[0]_i_70_n_0\, O => \vgaRed[0]_i_20_n_0\ ); \vgaRed[0]_i_21\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \vgaRed_reg[0]_i_71_n_0\, I1 => \vgaRed_reg[0]_i_72_n_0\, I2 => \char[5]_i_1_n_0\, I3 => \vgaRed_reg[0]_i_73_n_0\, I4 => \char[4]_i_1_n_0\, I5 => \vgaRed_reg[0]_i_74_n_0\, O => \vgaRed[0]_i_21_n_0\ ); \vgaRed[0]_i_22\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \vgaRed_reg[0]_i_75_n_0\, I1 => \vgaRed_reg[0]_i_76_n_0\, I2 => \char[5]_i_1_n_0\, I3 => \vgaRed_reg[0]_i_77_n_0\, I4 => \char[4]_i_1_n_0\, I5 => \vgaRed_reg[0]_i_78_n_0\, O => \vgaRed[0]_i_22_n_0\ ); \vgaRed[0]_i_23\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \vgaRed_reg[0]_i_79_n_0\, I1 => \vgaRed[0]_i_80_n_0\, I2 => \char[5]_i_1_n_0\, I3 => \vgaRed_reg[0]_i_81_n_0\, I4 => \char[4]_i_1_n_0\, I5 => \vgaRed_reg[0]_i_82_n_0\, O => \vgaRed[0]_i_23_n_0\ ); \vgaRed[0]_i_29\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => g11_b5_n_0, I1 => g10_b5_n_0, I2 => \char[3]_i_1_n_0\, I3 => g9_b5_n_0, I4 => \char[2]_i_1_n_0\, I5 => g8_b2_n_0, O => \vgaRed[0]_i_29_n_0\ ); \vgaRed[0]_i_33\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => g27_b3_n_0, I1 => g26_b4_n_0, I2 => \char[3]_i_1_n_0\, I3 => g25_b4_n_0, I4 => \char[2]_i_1_n_0\, I5 => g24_b4_n_0, O => \vgaRed[0]_i_33_n_0\ ); \vgaRed[0]_i_34\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => g23_b4_n_0, I1 => g22_b4_n_0, I2 => \char[3]_i_1_n_0\, I3 => g21_b3_n_0, I4 => \char[2]_i_1_n_0\, I5 => g20_b4_n_0, O => \vgaRed[0]_i_34_n_0\ ); \vgaRed[0]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \vgaRed[0]_i_8_n_0\, I1 => \vgaRed[0]_i_9_n_0\, I2 => X(0), I3 => \vgaRed[0]_i_10_n_0\, I4 => \char[6]_i_1_n_0\, I5 => \vgaRed[0]_i_11_n_0\, O => \vgaRed[0]_i_4_n_0\ ); \vgaRed[0]_i_40\: unisim.vcomponents.LUT6 generic map( INIT => X"AFC0A0C0A000A000" ) port map ( I0 => \vgaRed_reg[0]_i_109_n_0\, I1 => g21_b7_n_0, I2 => \char[4]_i_1_n_0\, I3 => \char[3]_i_1_n_0\, I4 => g19_b7_n_0, I5 => \char[2]_i_1_n_0\, O => \vgaRed[0]_i_40_n_0\ ); \vgaRed[0]_i_41\: unisim.vcomponents.LUT6 generic map( INIT => X"0FC000C0A000A000" ) port map ( I0 => g30_b7_n_0, I1 => g29_b7_n_0, I2 => \char[4]_i_1_n_0\, I3 => \char[3]_i_1_n_0\, I4 => g27_b7_n_0, I5 => \char[2]_i_1_n_0\, O => \vgaRed[0]_i_41_n_0\ ); \vgaRed[0]_i_42\: unisim.vcomponents.LUT6 generic map( INIT => X"B080FFFFB0800000" ) port map ( I0 => g7_b7_n_0, I1 => \char[3]_i_1_n_0\, I2 => \char[2]_i_1_n_0\, I3 => g5_b7_n_0, I4 => \char[4]_i_1_n_0\, I5 => \vgaRed_reg[0]_i_110_n_0\, O => \vgaRed[0]_i_42_n_0\ ); \vgaRed[0]_i_48\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => g11_b6_n_0, I1 => g10_b1_n_0, I2 => \char[3]_i_1_n_0\, I3 => g9_b6_n_0, I4 => \char[2]_i_1_n_0\, I5 => g8_b6_n_0, O => \vgaRed[0]_i_48_n_0\ ); \vgaRed[0]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \vgaRed_reg[0]_i_12_n_0\, I1 => \vgaRed[0]_i_13_n_0\, I2 => X(0), I3 => \vgaRed[0]_i_14_n_0\, I4 => \char[6]_i_1_n_0\, I5 => \vgaRed[0]_i_15_n_0\, O => \vgaRed[0]_i_5_n_0\ ); \vgaRed[0]_i_56\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => g11_b1_n_0, I1 => g10_b1_n_0, I2 => \char[3]_i_1_n_0\, I3 => g9_b1_n_0, I4 => \char[2]_i_1_n_0\, I5 => g8_b1_n_0, O => \vgaRed[0]_i_56_n_0\ ); \vgaRed[0]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \vgaRed[0]_i_16_n_0\, I1 => \vgaRed[0]_i_17_n_0\, I2 => X(0), I3 => \vgaRed[0]_i_18_n_0\, I4 => \char[6]_i_1_n_0\, I5 => \vgaRed[0]_i_19_n_0\, O => \vgaRed[0]_i_6_n_0\ ); \vgaRed[0]_i_64\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => g11_b0_n_0, I1 => g10_b0_n_0, I2 => \char[3]_i_1_n_0\, I3 => g9_b0_n_0, I4 => \char[2]_i_1_n_0\, I5 => g8_b0_n_0, O => \vgaRed[0]_i_64_n_0\ ); \vgaRed[0]_i_68\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => g27_b3_n_0, I1 => g26_b3_n_0, I2 => \char[3]_i_1_n_0\, I3 => g25_b3_n_0, I4 => \char[2]_i_1_n_0\, I5 => g24_b3_n_0, O => \vgaRed[0]_i_68_n_0\ ); \vgaRed[0]_i_69\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => g23_b3_n_0, I1 => g22_b3_n_0, I2 => \char[3]_i_1_n_0\, I3 => g21_b3_n_0, I4 => \char[2]_i_1_n_0\, I5 => g20_b3_n_0, O => \vgaRed[0]_i_69_n_0\ ); \vgaRed[0]_i_7\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \vgaRed[0]_i_20_n_0\, I1 => \vgaRed[0]_i_21_n_0\, I2 => X(0), I3 => \vgaRed[0]_i_22_n_0\, I4 => \char[6]_i_1_n_0\, I5 => \vgaRed[0]_i_23_n_0\, O => \vgaRed[0]_i_7_n_0\ ); \vgaRed[0]_i_8\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \vgaRed_reg[0]_i_24_n_0\, I1 => \vgaRed_reg[0]_i_25_n_0\, I2 => \char[5]_i_1_n_0\, I3 => \vgaRed_reg[0]_i_26_n_0\, I4 => \char[4]_i_1_n_0\, I5 => \vgaRed_reg[0]_i_27_n_0\, O => \vgaRed[0]_i_8_n_0\ ); \vgaRed[0]_i_80\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => g11_b2_n_0, I1 => g10_b2_n_0, I2 => \char[3]_i_1_n_0\, I3 => g9_b2_n_0, I4 => \char[2]_i_1_n_0\, I5 => g8_b2_n_0, O => \vgaRed[0]_i_80_n_0\ ); \vgaRed[0]_i_9\: unisim.vcomponents.LUT6 generic map( INIT => X"AFA0CFCFAFA0C0C0" ) port map ( I0 => \vgaRed_reg[0]_i_28_n_0\, I1 => \vgaRed[0]_i_29_n_0\, I2 => \char[5]_i_1_n_0\, I3 => \vgaRed_reg[0]_i_30_n_0\, I4 => \char[4]_i_1_n_0\, I5 => \vgaRed_reg[0]_i_31_n_0\, O => \vgaRed[0]_i_9_n_0\ ); \vgaRed_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk108M, CE => '1', D => \vgaRed[0]_i_1_n_0\, Q => vgaBlue_OBUF(0), R => '0' ); \vgaRed_reg[0]_i_100\: unisim.vcomponents.MUXF7 port map ( I0 => g18_b4_n_0, I1 => g19_b4_n_0, O => \vgaRed_reg[0]_i_100_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_101\: unisim.vcomponents.MUXF7 port map ( I0 => g12_b4_n_0, I1 => g13_b4_n_0, O => \vgaRed_reg[0]_i_101_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_102\: unisim.vcomponents.MUXF7 port map ( I0 => g14_b4_n_0, I1 => g15_b4_n_0, O => \vgaRed_reg[0]_i_102_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_103\: unisim.vcomponents.MUXF7 port map ( I0 => g8_b4_n_0, I1 => g9_b4_n_0, O => \vgaRed_reg[0]_i_103_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_104\: unisim.vcomponents.MUXF7 port map ( I0 => g10_b4_n_0, I1 => g11_b4_n_0, O => \vgaRed_reg[0]_i_104_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_105\: unisim.vcomponents.MUXF7 port map ( I0 => g4_b4_n_0, I1 => g5_b4_n_0, O => \vgaRed_reg[0]_i_105_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_106\: unisim.vcomponents.MUXF7 port map ( I0 => g6_b4_n_0, I1 => g7_b4_n_0, O => \vgaRed_reg[0]_i_106_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_107\: unisim.vcomponents.MUXF7 port map ( I0 => g0_b4_n_0, I1 => g1_b4_n_0, O => \vgaRed_reg[0]_i_107_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_108\: unisim.vcomponents.MUXF7 port map ( I0 => g2_b4_n_0, I1 => g3_b4_n_0, O => \vgaRed_reg[0]_i_108_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_109\: unisim.vcomponents.MUXF7 port map ( I0 => g22_b7_n_0, I1 => g23_b7_n_0, O => \vgaRed_reg[0]_i_109_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_110\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_179_n_0\, I1 => \vgaRed_reg[0]_i_180_n_0\, O => \vgaRed_reg[0]_i_110_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_111\: unisim.vcomponents.MUXF7 port map ( I0 => g28_b6_n_0, I1 => g29_b6_n_0, O => \vgaRed_reg[0]_i_111_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_112\: unisim.vcomponents.MUXF7 port map ( I0 => g30_b6_n_0, I1 => g31_b6_n_0, O => \vgaRed_reg[0]_i_112_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_113\: unisim.vcomponents.MUXF7 port map ( I0 => g24_b6_n_0, I1 => g25_b6_n_0, O => \vgaRed_reg[0]_i_113_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_114\: unisim.vcomponents.MUXF7 port map ( I0 => g26_b6_n_0, I1 => g27_b6_n_0, O => \vgaRed_reg[0]_i_114_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_115\: unisim.vcomponents.MUXF7 port map ( I0 => g20_b6_n_0, I1 => g21_b6_n_0, O => \vgaRed_reg[0]_i_115_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_116\: unisim.vcomponents.MUXF7 port map ( I0 => g22_b6_n_0, I1 => g23_b6_n_0, O => \vgaRed_reg[0]_i_116_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_117\: unisim.vcomponents.MUXF7 port map ( I0 => g16_b6_n_0, I1 => g17_b6_n_0, O => \vgaRed_reg[0]_i_117_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_118\: unisim.vcomponents.MUXF7 port map ( I0 => g18_b6_n_0, I1 => g19_b6_n_0, O => \vgaRed_reg[0]_i_118_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_119\: unisim.vcomponents.MUXF7 port map ( I0 => g12_b6_n_0, I1 => g13_b6_n_0, O => \vgaRed_reg[0]_i_119_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_12\: unisim.vcomponents.MUXF7 port map ( I0 => \vgaRed[0]_i_40_n_0\, I1 => \vgaRed[0]_i_41_n_0\, O => \vgaRed_reg[0]_i_12_n_0\, S => \char[5]_i_1_n_0\ ); \vgaRed_reg[0]_i_120\: unisim.vcomponents.MUXF7 port map ( I0 => g14_b6_n_0, I1 => g15_b6_n_0, O => \vgaRed_reg[0]_i_120_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_121\: unisim.vcomponents.MUXF7 port map ( I0 => g4_b6_n_0, I1 => g5_b6_n_0, O => \vgaRed_reg[0]_i_121_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_122\: unisim.vcomponents.MUXF7 port map ( I0 => g6_b6_n_0, I1 => g7_b6_n_0, O => \vgaRed_reg[0]_i_122_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_123\: unisim.vcomponents.MUXF7 port map ( I0 => g0_b6_n_0, I1 => g1_b6_n_0, O => \vgaRed_reg[0]_i_123_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_124\: unisim.vcomponents.MUXF7 port map ( I0 => g2_b6_n_0, I1 => g3_b6_n_0, O => \vgaRed_reg[0]_i_124_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_125\: unisim.vcomponents.MUXF7 port map ( I0 => g28_b1_n_0, I1 => g29_b1_n_0, O => \vgaRed_reg[0]_i_125_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_126\: unisim.vcomponents.MUXF7 port map ( I0 => g30_b1_n_0, I1 => g31_b1_n_0, O => \vgaRed_reg[0]_i_126_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_127\: unisim.vcomponents.MUXF7 port map ( I0 => g24_b1_n_0, I1 => g25_b1_n_0, O => \vgaRed_reg[0]_i_127_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_128\: unisim.vcomponents.MUXF7 port map ( I0 => g26_b1_n_0, I1 => g27_b1_n_0, O => \vgaRed_reg[0]_i_128_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_129\: unisim.vcomponents.MUXF7 port map ( I0 => g20_b1_n_0, I1 => g21_b1_n_0, O => \vgaRed_reg[0]_i_129_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_130\: unisim.vcomponents.MUXF7 port map ( I0 => g22_b1_n_0, I1 => g23_b1_n_0, O => \vgaRed_reg[0]_i_130_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_131\: unisim.vcomponents.MUXF7 port map ( I0 => g16_b1_n_0, I1 => g17_b1_n_0, O => \vgaRed_reg[0]_i_131_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_132\: unisim.vcomponents.MUXF7 port map ( I0 => g18_b1_n_0, I1 => g19_b1_n_0, O => \vgaRed_reg[0]_i_132_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_133\: unisim.vcomponents.MUXF7 port map ( I0 => g12_b1_n_0, I1 => g13_b1_n_0, O => \vgaRed_reg[0]_i_133_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_134\: unisim.vcomponents.MUXF7 port map ( I0 => g14_b1_n_0, I1 => g15_b1_n_0, O => \vgaRed_reg[0]_i_134_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_135\: unisim.vcomponents.MUXF7 port map ( I0 => g4_b1_n_0, I1 => g5_b1_n_0, O => \vgaRed_reg[0]_i_135_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_136\: unisim.vcomponents.MUXF7 port map ( I0 => g6_b1_n_0, I1 => g7_b1_n_0, O => \vgaRed_reg[0]_i_136_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_137\: unisim.vcomponents.MUXF7 port map ( I0 => g0_b1_n_0, I1 => g1_b1_n_0, O => \vgaRed_reg[0]_i_137_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_138\: unisim.vcomponents.MUXF7 port map ( I0 => g2_b1_n_0, I1 => g3_b1_n_0, O => \vgaRed_reg[0]_i_138_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_139\: unisim.vcomponents.MUXF7 port map ( I0 => g28_b0_n_0, I1 => g29_b0_n_0, O => \vgaRed_reg[0]_i_139_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_140\: unisim.vcomponents.MUXF7 port map ( I0 => g30_b0_n_0, I1 => g31_b0_n_0, O => \vgaRed_reg[0]_i_140_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_141\: unisim.vcomponents.MUXF7 port map ( I0 => g24_b0_n_0, I1 => g25_b0_n_0, O => \vgaRed_reg[0]_i_141_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_142\: unisim.vcomponents.MUXF7 port map ( I0 => g26_b0_n_0, I1 => g27_b0_n_0, O => \vgaRed_reg[0]_i_142_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_143\: unisim.vcomponents.MUXF7 port map ( I0 => g20_b0_n_0, I1 => g21_b0_n_0, O => \vgaRed_reg[0]_i_143_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_144\: unisim.vcomponents.MUXF7 port map ( I0 => g22_b0_n_0, I1 => g23_b0_n_0, O => \vgaRed_reg[0]_i_144_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_145\: unisim.vcomponents.MUXF7 port map ( I0 => g16_b0_n_0, I1 => g17_b0_n_0, O => \vgaRed_reg[0]_i_145_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_146\: unisim.vcomponents.MUXF7 port map ( I0 => g18_b0_n_0, I1 => g19_b0_n_0, O => \vgaRed_reg[0]_i_146_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_147\: unisim.vcomponents.MUXF7 port map ( I0 => g12_b0_n_0, I1 => g13_b0_n_0, O => \vgaRed_reg[0]_i_147_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_148\: unisim.vcomponents.MUXF7 port map ( I0 => g14_b0_n_0, I1 => g15_b0_n_0, O => \vgaRed_reg[0]_i_148_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_149\: unisim.vcomponents.MUXF7 port map ( I0 => g4_b0_n_0, I1 => g5_b0_n_0, O => \vgaRed_reg[0]_i_149_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_150\: unisim.vcomponents.MUXF7 port map ( I0 => g6_b0_n_0, I1 => g7_b0_n_0, O => \vgaRed_reg[0]_i_150_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_151\: unisim.vcomponents.MUXF7 port map ( I0 => g0_b0_n_0, I1 => g1_b0_n_0, O => \vgaRed_reg[0]_i_151_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_152\: unisim.vcomponents.MUXF7 port map ( I0 => g2_b0_n_0, I1 => g3_b0_n_0, O => \vgaRed_reg[0]_i_152_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_153\: unisim.vcomponents.MUXF7 port map ( I0 => g28_b3_n_0, I1 => g29_b3_n_0, O => \vgaRed_reg[0]_i_153_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_154\: unisim.vcomponents.MUXF7 port map ( I0 => g30_b3_n_0, I1 => g31_b3_n_0, O => \vgaRed_reg[0]_i_154_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_155\: unisim.vcomponents.MUXF7 port map ( I0 => g16_b3_n_0, I1 => g17_b3_n_0, O => \vgaRed_reg[0]_i_155_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_156\: unisim.vcomponents.MUXF7 port map ( I0 => g18_b3_n_0, I1 => g19_b3_n_0, O => \vgaRed_reg[0]_i_156_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_157\: unisim.vcomponents.MUXF7 port map ( I0 => g12_b3_n_0, I1 => g13_b3_n_0, O => \vgaRed_reg[0]_i_157_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_158\: unisim.vcomponents.MUXF7 port map ( I0 => g14_b3_n_0, I1 => g15_b3_n_0, O => \vgaRed_reg[0]_i_158_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_159\: unisim.vcomponents.MUXF7 port map ( I0 => g8_b3_n_0, I1 => g9_b3_n_0, O => \vgaRed_reg[0]_i_159_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_160\: unisim.vcomponents.MUXF7 port map ( I0 => g10_b3_n_0, I1 => g11_b3_n_0, O => \vgaRed_reg[0]_i_160_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_161\: unisim.vcomponents.MUXF7 port map ( I0 => g4_b3_n_0, I1 => g5_b3_n_0, O => \vgaRed_reg[0]_i_161_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_162\: unisim.vcomponents.MUXF7 port map ( I0 => g6_b3_n_0, I1 => g7_b3_n_0, O => \vgaRed_reg[0]_i_162_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_163\: unisim.vcomponents.MUXF7 port map ( I0 => g0_b3_n_0, I1 => g1_b3_n_0, O => \vgaRed_reg[0]_i_163_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_164\: unisim.vcomponents.MUXF7 port map ( I0 => g2_b3_n_0, I1 => g3_b3_n_0, O => \vgaRed_reg[0]_i_164_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_165\: unisim.vcomponents.MUXF7 port map ( I0 => g28_b2_n_0, I1 => g29_b2_n_0, O => \vgaRed_reg[0]_i_165_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_166\: unisim.vcomponents.MUXF7 port map ( I0 => g30_b2_n_0, I1 => g31_b2_n_0, O => \vgaRed_reg[0]_i_166_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_167\: unisim.vcomponents.MUXF7 port map ( I0 => g24_b2_n_0, I1 => g25_b2_n_0, O => \vgaRed_reg[0]_i_167_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_168\: unisim.vcomponents.MUXF7 port map ( I0 => g26_b2_n_0, I1 => g27_b2_n_0, O => \vgaRed_reg[0]_i_168_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_169\: unisim.vcomponents.MUXF7 port map ( I0 => g20_b2_n_0, I1 => g21_b2_n_0, O => \vgaRed_reg[0]_i_169_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_170\: unisim.vcomponents.MUXF7 port map ( I0 => g22_b2_n_0, I1 => g23_b2_n_0, O => \vgaRed_reg[0]_i_170_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_171\: unisim.vcomponents.MUXF7 port map ( I0 => g16_b2_n_0, I1 => g17_b2_n_0, O => \vgaRed_reg[0]_i_171_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_172\: unisim.vcomponents.MUXF7 port map ( I0 => g18_b2_n_0, I1 => g19_b2_n_0, O => \vgaRed_reg[0]_i_172_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_173\: unisim.vcomponents.MUXF7 port map ( I0 => g12_b2_n_0, I1 => g13_b2_n_0, O => \vgaRed_reg[0]_i_173_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_174\: unisim.vcomponents.MUXF7 port map ( I0 => g14_b2_n_0, I1 => g15_b2_n_0, O => \vgaRed_reg[0]_i_174_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_175\: unisim.vcomponents.MUXF7 port map ( I0 => g4_b2_n_0, I1 => g5_b2_n_0, O => \vgaRed_reg[0]_i_175_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_176\: unisim.vcomponents.MUXF7 port map ( I0 => g6_b2_n_0, I1 => g7_b2_n_0, O => \vgaRed_reg[0]_i_176_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_177\: unisim.vcomponents.MUXF7 port map ( I0 => g0_b2_n_0, I1 => g1_b2_n_0, O => \vgaRed_reg[0]_i_177_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_178\: unisim.vcomponents.MUXF7 port map ( I0 => g2_b2_n_0, I1 => g3_b2_n_0, O => \vgaRed_reg[0]_i_178_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_179\: unisim.vcomponents.MUXF7 port map ( I0 => g0_b7_n_0, I1 => g1_b7_n_0, O => \vgaRed_reg[0]_i_179_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_180\: unisim.vcomponents.MUXF7 port map ( I0 => g2_b7_n_0, I1 => g3_b7_n_0, O => \vgaRed_reg[0]_i_180_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_2\: unisim.vcomponents.MUXF7 port map ( I0 => \vgaRed[0]_i_4_n_0\, I1 => \vgaRed[0]_i_5_n_0\, O => \vgaRed_reg[0]_i_2_n_0\, S => X(1) ); \vgaRed_reg[0]_i_24\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_83_n_0\, I1 => \vgaRed_reg[0]_i_84_n_0\, O => \vgaRed_reg[0]_i_24_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_25\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_85_n_0\, I1 => \vgaRed_reg[0]_i_86_n_0\, O => \vgaRed_reg[0]_i_25_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_26\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_87_n_0\, I1 => \vgaRed_reg[0]_i_88_n_0\, O => \vgaRed_reg[0]_i_26_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_27\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_89_n_0\, I1 => \vgaRed_reg[0]_i_90_n_0\, O => \vgaRed_reg[0]_i_27_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_28\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_91_n_0\, I1 => \vgaRed_reg[0]_i_92_n_0\, O => \vgaRed_reg[0]_i_28_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_3\: unisim.vcomponents.MUXF7 port map ( I0 => \vgaRed[0]_i_6_n_0\, I1 => \vgaRed[0]_i_7_n_0\, O => \vgaRed_reg[0]_i_3_n_0\, S => X(1) ); \vgaRed_reg[0]_i_30\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_93_n_0\, I1 => \vgaRed_reg[0]_i_94_n_0\, O => \vgaRed_reg[0]_i_30_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_31\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_95_n_0\, I1 => \vgaRed_reg[0]_i_96_n_0\, O => \vgaRed_reg[0]_i_31_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_32\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_97_n_0\, I1 => \vgaRed_reg[0]_i_98_n_0\, O => \vgaRed_reg[0]_i_32_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_35\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_99_n_0\, I1 => \vgaRed_reg[0]_i_100_n_0\, O => \vgaRed_reg[0]_i_35_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_36\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_101_n_0\, I1 => \vgaRed_reg[0]_i_102_n_0\, O => \vgaRed_reg[0]_i_36_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_37\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_103_n_0\, I1 => \vgaRed_reg[0]_i_104_n_0\, O => \vgaRed_reg[0]_i_37_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_38\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_105_n_0\, I1 => \vgaRed_reg[0]_i_106_n_0\, O => \vgaRed_reg[0]_i_38_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_39\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_107_n_0\, I1 => \vgaRed_reg[0]_i_108_n_0\, O => \vgaRed_reg[0]_i_39_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_43\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_111_n_0\, I1 => \vgaRed_reg[0]_i_112_n_0\, O => \vgaRed_reg[0]_i_43_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_44\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_113_n_0\, I1 => \vgaRed_reg[0]_i_114_n_0\, O => \vgaRed_reg[0]_i_44_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_45\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_115_n_0\, I1 => \vgaRed_reg[0]_i_116_n_0\, O => \vgaRed_reg[0]_i_45_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_46\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_117_n_0\, I1 => \vgaRed_reg[0]_i_118_n_0\, O => \vgaRed_reg[0]_i_46_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_47\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_119_n_0\, I1 => \vgaRed_reg[0]_i_120_n_0\, O => \vgaRed_reg[0]_i_47_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_49\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_121_n_0\, I1 => \vgaRed_reg[0]_i_122_n_0\, O => \vgaRed_reg[0]_i_49_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_50\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_123_n_0\, I1 => \vgaRed_reg[0]_i_124_n_0\, O => \vgaRed_reg[0]_i_50_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_51\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_125_n_0\, I1 => \vgaRed_reg[0]_i_126_n_0\, O => \vgaRed_reg[0]_i_51_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_52\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_127_n_0\, I1 => \vgaRed_reg[0]_i_128_n_0\, O => \vgaRed_reg[0]_i_52_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_53\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_129_n_0\, I1 => \vgaRed_reg[0]_i_130_n_0\, O => \vgaRed_reg[0]_i_53_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_54\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_131_n_0\, I1 => \vgaRed_reg[0]_i_132_n_0\, O => \vgaRed_reg[0]_i_54_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_55\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_133_n_0\, I1 => \vgaRed_reg[0]_i_134_n_0\, O => \vgaRed_reg[0]_i_55_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_57\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_135_n_0\, I1 => \vgaRed_reg[0]_i_136_n_0\, O => \vgaRed_reg[0]_i_57_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_58\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_137_n_0\, I1 => \vgaRed_reg[0]_i_138_n_0\, O => \vgaRed_reg[0]_i_58_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_59\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_139_n_0\, I1 => \vgaRed_reg[0]_i_140_n_0\, O => \vgaRed_reg[0]_i_59_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_60\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_141_n_0\, I1 => \vgaRed_reg[0]_i_142_n_0\, O => \vgaRed_reg[0]_i_60_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_61\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_143_n_0\, I1 => \vgaRed_reg[0]_i_144_n_0\, O => \vgaRed_reg[0]_i_61_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_62\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_145_n_0\, I1 => \vgaRed_reg[0]_i_146_n_0\, O => \vgaRed_reg[0]_i_62_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_63\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_147_n_0\, I1 => \vgaRed_reg[0]_i_148_n_0\, O => \vgaRed_reg[0]_i_63_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_65\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_149_n_0\, I1 => \vgaRed_reg[0]_i_150_n_0\, O => \vgaRed_reg[0]_i_65_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_66\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_151_n_0\, I1 => \vgaRed_reg[0]_i_152_n_0\, O => \vgaRed_reg[0]_i_66_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_67\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_153_n_0\, I1 => \vgaRed_reg[0]_i_154_n_0\, O => \vgaRed_reg[0]_i_67_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_70\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_155_n_0\, I1 => \vgaRed_reg[0]_i_156_n_0\, O => \vgaRed_reg[0]_i_70_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_71\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_157_n_0\, I1 => \vgaRed_reg[0]_i_158_n_0\, O => \vgaRed_reg[0]_i_71_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_72\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_159_n_0\, I1 => \vgaRed_reg[0]_i_160_n_0\, O => \vgaRed_reg[0]_i_72_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_73\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_161_n_0\, I1 => \vgaRed_reg[0]_i_162_n_0\, O => \vgaRed_reg[0]_i_73_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_74\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_163_n_0\, I1 => \vgaRed_reg[0]_i_164_n_0\, O => \vgaRed_reg[0]_i_74_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_75\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_165_n_0\, I1 => \vgaRed_reg[0]_i_166_n_0\, O => \vgaRed_reg[0]_i_75_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_76\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_167_n_0\, I1 => \vgaRed_reg[0]_i_168_n_0\, O => \vgaRed_reg[0]_i_76_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_77\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_169_n_0\, I1 => \vgaRed_reg[0]_i_170_n_0\, O => \vgaRed_reg[0]_i_77_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_78\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_171_n_0\, I1 => \vgaRed_reg[0]_i_172_n_0\, O => \vgaRed_reg[0]_i_78_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_79\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_173_n_0\, I1 => \vgaRed_reg[0]_i_174_n_0\, O => \vgaRed_reg[0]_i_79_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_81\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_175_n_0\, I1 => \vgaRed_reg[0]_i_176_n_0\, O => \vgaRed_reg[0]_i_81_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_82\: unisim.vcomponents.MUXF8 port map ( I0 => \vgaRed_reg[0]_i_177_n_0\, I1 => \vgaRed_reg[0]_i_178_n_0\, O => \vgaRed_reg[0]_i_82_n_0\, S => \char[3]_i_1_n_0\ ); \vgaRed_reg[0]_i_83\: unisim.vcomponents.MUXF7 port map ( I0 => g28_b5_n_0, I1 => g29_b5_n_0, O => \vgaRed_reg[0]_i_83_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_84\: unisim.vcomponents.MUXF7 port map ( I0 => g30_b5_n_0, I1 => g31_b5_n_0, O => \vgaRed_reg[0]_i_84_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_85\: unisim.vcomponents.MUXF7 port map ( I0 => g24_b5_n_0, I1 => g25_b5_n_0, O => \vgaRed_reg[0]_i_85_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_86\: unisim.vcomponents.MUXF7 port map ( I0 => g26_b5_n_0, I1 => g27_b5_n_0, O => \vgaRed_reg[0]_i_86_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_87\: unisim.vcomponents.MUXF7 port map ( I0 => g20_b5_n_0, I1 => g21_b5_n_0, O => \vgaRed_reg[0]_i_87_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_88\: unisim.vcomponents.MUXF7 port map ( I0 => g22_b5_n_0, I1 => g23_b5_n_0, O => \vgaRed_reg[0]_i_88_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_89\: unisim.vcomponents.MUXF7 port map ( I0 => g16_b5_n_0, I1 => g17_b5_n_0, O => \vgaRed_reg[0]_i_89_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_90\: unisim.vcomponents.MUXF7 port map ( I0 => g18_b5_n_0, I1 => g19_b5_n_0, O => \vgaRed_reg[0]_i_90_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_91\: unisim.vcomponents.MUXF7 port map ( I0 => g12_b5_n_0, I1 => g13_b5_n_0, O => \vgaRed_reg[0]_i_91_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_92\: unisim.vcomponents.MUXF7 port map ( I0 => g14_b5_n_0, I1 => g15_b5_n_0, O => \vgaRed_reg[0]_i_92_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_93\: unisim.vcomponents.MUXF7 port map ( I0 => g4_b5_n_0, I1 => g5_b5_n_0, O => \vgaRed_reg[0]_i_93_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_94\: unisim.vcomponents.MUXF7 port map ( I0 => g6_b5_n_0, I1 => g7_b5_n_0, O => \vgaRed_reg[0]_i_94_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_95\: unisim.vcomponents.MUXF7 port map ( I0 => g0_b5_n_0, I1 => g1_b5_n_0, O => \vgaRed_reg[0]_i_95_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_96\: unisim.vcomponents.MUXF7 port map ( I0 => g2_b5_n_0, I1 => g3_b5_n_0, O => \vgaRed_reg[0]_i_96_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_97\: unisim.vcomponents.MUXF7 port map ( I0 => g28_b4_n_0, I1 => g29_b4_n_0, O => \vgaRed_reg[0]_i_97_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_98\: unisim.vcomponents.MUXF7 port map ( I0 => g30_b4_n_0, I1 => g31_b4_n_0, O => \vgaRed_reg[0]_i_98_n_0\, S => \char[2]_i_1_n_0\ ); \vgaRed_reg[0]_i_99\: unisim.vcomponents.MUXF7 port map ( I0 => g16_b4_n_0, I1 => g17_b4_n_0, O => \vgaRed_reg[0]_i_99_n_0\, S => \char[2]_i_1_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity ps2_keyboard is port ( ps2_code_new : out STD_LOGIC; break_reg : out STD_LOGIC; shift_l_reg : out STD_LOGIC; shift_r_reg : out STD_LOGIC; e0_code_reg : out STD_LOGIC; control_r_reg : out STD_LOGIC; control_l_reg : out STD_LOGIC; caps_lock_reg : out STD_LOGIC; \ascii_reg[7]\ : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 1 downto 0 ); \ascii_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 ); E : out STD_LOGIC_VECTOR ( 0 to 0 ); PS2Clk_IBUF : in STD_LOGIC; clk_BUFG : in STD_LOGIC; PS2Data_IBUF : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); break : in STD_LOGIC; shift_l : in STD_LOGIC; shift_r : in STD_LOGIC; e0_code : in STD_LOGIC; control_r_reg_0 : in STD_LOGIC; control_l_reg_0 : in STD_LOGIC; caps_lock_reg_0 : in STD_LOGIC; \ascii_reg[7]_0\ : in STD_LOGIC; prev_ps2_code_new : in STD_LOGIC ); end ps2_keyboard; architecture STRUCTURE of ps2_keyboard is signal \ascii[0]_i_10_n_0\ : STD_LOGIC; signal \ascii[0]_i_11_n_0\ : STD_LOGIC; signal \ascii[0]_i_2_n_0\ : STD_LOGIC; signal \ascii[0]_i_3_n_0\ : STD_LOGIC; signal \ascii[0]_i_4_n_0\ : STD_LOGIC; signal \ascii[0]_i_5_n_0\ : STD_LOGIC; signal \ascii[0]_i_6_n_0\ : STD_LOGIC; signal \ascii[0]_i_8_n_0\ : STD_LOGIC; signal \ascii[0]_i_9_n_0\ : STD_LOGIC; signal \ascii[1]_i_2_n_0\ : STD_LOGIC; signal \ascii[1]_i_3_n_0\ : STD_LOGIC; signal \ascii[1]_i_4_n_0\ : STD_LOGIC; signal \ascii[1]_i_5_n_0\ : STD_LOGIC; signal \ascii[1]_i_6_n_0\ : STD_LOGIC; signal \ascii[1]_i_7_n_0\ : STD_LOGIC; signal \ascii[1]_i_8_n_0\ : STD_LOGIC; signal \ascii[1]_i_9_n_0\ : STD_LOGIC; signal \ascii[2]_i_10_n_0\ : STD_LOGIC; signal \ascii[2]_i_11_n_0\ : STD_LOGIC; signal \ascii[2]_i_12_n_0\ : STD_LOGIC; signal \ascii[2]_i_3_n_0\ : STD_LOGIC; signal \ascii[2]_i_4_n_0\ : STD_LOGIC; signal \ascii[2]_i_5_n_0\ : STD_LOGIC; signal \ascii[2]_i_6_n_0\ : STD_LOGIC; signal \ascii[2]_i_7_n_0\ : STD_LOGIC; signal \ascii[2]_i_9_n_0\ : STD_LOGIC; signal \ascii[3]_i_10_n_0\ : STD_LOGIC; signal \ascii[3]_i_3_n_0\ : STD_LOGIC; signal \ascii[3]_i_4_n_0\ : STD_LOGIC; signal \ascii[3]_i_5_n_0\ : STD_LOGIC; signal \ascii[3]_i_6_n_0\ : STD_LOGIC; signal \ascii[3]_i_7_n_0\ : STD_LOGIC; signal \ascii[3]_i_8_n_0\ : STD_LOGIC; signal \ascii[3]_i_9_n_0\ : STD_LOGIC; signal \ascii[4]_i_10_n_0\ : STD_LOGIC; signal \ascii[4]_i_2_n_0\ : STD_LOGIC; signal \ascii[4]_i_3_n_0\ : STD_LOGIC; signal \ascii[4]_i_4_n_0\ : STD_LOGIC; signal \ascii[4]_i_5_n_0\ : STD_LOGIC; signal \ascii[4]_i_7_n_0\ : STD_LOGIC; signal \ascii[4]_i_8_n_0\ : STD_LOGIC; signal \ascii[4]_i_9_n_0\ : STD_LOGIC; signal \ascii[5]_i_10_n_0\ : STD_LOGIC; signal \ascii[5]_i_11_n_0\ : STD_LOGIC; signal \ascii[5]_i_12_n_0\ : STD_LOGIC; signal \ascii[5]_i_13_n_0\ : STD_LOGIC; signal \ascii[5]_i_14_n_0\ : STD_LOGIC; signal \ascii[5]_i_15_n_0\ : STD_LOGIC; signal \ascii[5]_i_16_n_0\ : STD_LOGIC; signal \ascii[5]_i_17_n_0\ : STD_LOGIC; signal \ascii[5]_i_2_n_0\ : STD_LOGIC; signal \ascii[5]_i_3_n_0\ : STD_LOGIC; signal \ascii[5]_i_4_n_0\ : STD_LOGIC; signal \ascii[6]_i_10_n_0\ : STD_LOGIC; signal \ascii[6]_i_11_n_0\ : STD_LOGIC; signal \ascii[6]_i_12_n_0\ : STD_LOGIC; signal \ascii[6]_i_13_n_0\ : STD_LOGIC; signal \ascii[6]_i_14_n_0\ : STD_LOGIC; signal \ascii[6]_i_15_n_0\ : STD_LOGIC; signal \ascii[6]_i_16_n_0\ : STD_LOGIC; signal \ascii[6]_i_17_n_0\ : STD_LOGIC; signal \ascii[6]_i_3_n_0\ : STD_LOGIC; signal \ascii[6]_i_4_n_0\ : STD_LOGIC; signal \ascii[6]_i_5_n_0\ : STD_LOGIC; signal \ascii[6]_i_6_n_0\ : STD_LOGIC; signal \ascii[6]_i_7_n_0\ : STD_LOGIC; signal \ascii[6]_i_8_n_0\ : STD_LOGIC; signal \ascii[6]_i_9_n_0\ : STD_LOGIC; signal \ascii_reg[0]_i_7_n_0\ : STD_LOGIC; signal \ascii_reg[2]_i_2_n_0\ : STD_LOGIC; signal \ascii_reg[2]_i_8_n_0\ : STD_LOGIC; signal \ascii_reg[3]_i_2_n_0\ : STD_LOGIC; signal \ascii_reg[4]_i_6_n_0\ : STD_LOGIC; signal \ascii_reg[5]_i_5_n_0\ : STD_LOGIC; signal \ascii_reg[5]_i_6_n_0\ : STD_LOGIC; signal \ascii_reg[5]_i_7_n_0\ : STD_LOGIC; signal \ascii_reg[5]_i_8_n_0\ : STD_LOGIC; signal \ascii_reg[5]_i_9_n_0\ : STD_LOGIC; signal break_i_2_n_0 : STD_LOGIC; signal caps_lock_i_2_n_0 : STD_LOGIC; signal clear : STD_LOGIC; signal control_l_i_2_n_0 : STD_LOGIC; signal control_r_i_2_n_0 : STD_LOGIC; signal control_r_i_3_n_0 : STD_LOGIC; signal \count_idle[0]_i_2_n_0\ : STD_LOGIC; signal \count_idle[0]_i_4_n_0\ : STD_LOGIC; signal \count_idle[0]_i_8_n_0\ : STD_LOGIC; signal \count_idle[0]_i_9_n_0\ : STD_LOGIC; signal count_idle_reg : STD_LOGIC_VECTOR ( 12 downto 0 ); signal \count_idle_reg[0]_i_3_n_0\ : STD_LOGIC; signal \count_idle_reg[0]_i_3_n_4\ : STD_LOGIC; signal \count_idle_reg[0]_i_3_n_5\ : STD_LOGIC; signal \count_idle_reg[0]_i_3_n_6\ : STD_LOGIC; signal \count_idle_reg[0]_i_3_n_7\ : STD_LOGIC; signal \count_idle_reg[12]_i_1_n_7\ : STD_LOGIC; signal \count_idle_reg[4]_i_1_n_0\ : STD_LOGIC; signal \count_idle_reg[4]_i_1_n_4\ : STD_LOGIC; signal \count_idle_reg[4]_i_1_n_5\ : STD_LOGIC; signal \count_idle_reg[4]_i_1_n_6\ : STD_LOGIC; signal \count_idle_reg[4]_i_1_n_7\ : STD_LOGIC; signal \count_idle_reg[8]_i_1_n_0\ : STD_LOGIC; signal \count_idle_reg[8]_i_1_n_4\ : STD_LOGIC; signal \count_idle_reg[8]_i_1_n_5\ : STD_LOGIC; signal \count_idle_reg[8]_i_1_n_6\ : STD_LOGIC; signal \count_idle_reg[8]_i_1_n_7\ : STD_LOGIC; signal e0_code_i_2_n_0 : STD_LOGIC; signal ps2_clk_int : STD_LOGIC; signal ps2_code : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \^ps2_code_new\ : STD_LOGIC; signal ps2_code_new0 : STD_LOGIC; signal ps2_code_new_i_2_n_0 : STD_LOGIC; signal ps2_code_new_i_3_n_0 : STD_LOGIC; signal ps2_code_new_i_4_n_0 : STD_LOGIC; signal ps2_code_new_i_5_n_0 : STD_LOGIC; signal ps2_code_new_i_6_n_0 : STD_LOGIC; signal ps2_code_new_i_7_n_0 : STD_LOGIC; signal ps2_data_int : STD_LOGIC; signal ps2_word : STD_LOGIC_VECTOR ( 10 downto 0 ); signal shift_l_i_2_n_0 : STD_LOGIC; signal shift_r_i_2_n_0 : STD_LOGIC; signal shift_r_i_3_n_0 : STD_LOGIC; signal \state[1]_i_2_n_0\ : STD_LOGIC; signal \NLW_count_idle_reg[0]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_count_idle_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_count_idle_reg[12]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_count_idle_reg[4]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_count_idle_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \ascii[5]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \ascii[6]_i_2\ : label is "soft_lutpair1"; begin ps2_code_new <= \^ps2_code_new\; \ascii[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CDC8" ) port map ( I0 => control_r_reg_0, I1 => \ascii[0]_i_2_n_0\, I2 => control_l_reg_0, I3 => \ascii[0]_i_3_n_0\, O => \ascii_reg[6]\(0) ); \ascii[0]_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"DCFDFFDF01000888" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(3), I3 => ps2_code(0), I4 => ps2_code(5), I5 => ps2_code(4), O => \ascii[0]_i_10_n_0\ ); \ascii[0]_i_11\: unisim.vcomponents.LUT6 generic map( INIT => X"FDBDFDFFEEBD030C" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(0), I3 => ps2_code(5), I4 => ps2_code(3), I5 => ps2_code(4), O => \ascii[0]_i_11_n_0\ ); \ascii[0]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"C0CFC0C0CACACFCF" ) port map ( I0 => ps2_code(2), I1 => \ascii[0]_i_4_n_0\, I2 => ps2_code(1), I3 => ps2_code(6), I4 => ps2_code(4), I5 => ps2_code(3), O => \ascii[0]_i_2_n_0\ ); \ascii[0]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"CDC8CDCDCDC8C8C8" ) port map ( I0 => shift_l, I1 => \ascii[0]_i_5_n_0\, I2 => shift_r, I3 => \ascii[0]_i_6_n_0\, I4 => ps2_code(7), I5 => \ascii_reg[0]_i_7_n_0\, O => \ascii[0]_i_3_n_0\ ); \ascii[0]_i_4\: unisim.vcomponents.LUT4 generic map( INIT => X"6515" ) port map ( I0 => ps2_code(5), I1 => ps2_code(0), I2 => ps2_code(3), I3 => ps2_code(4), O => \ascii[0]_i_4_n_0\ ); \ascii[0]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"EFE0CFCFEFE0C0C0" ) port map ( I0 => ps2_code(3), I1 => ps2_code(4), I2 => ps2_code(7), I3 => \ascii[0]_i_8_n_0\, I4 => ps2_code(2), I5 => \ascii[0]_i_9_n_0\, O => \ascii[0]_i_5_n_0\ ); \ascii[0]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"F8" ) port map ( I0 => ps2_code(3), I1 => ps2_code(2), I2 => ps2_code(4), O => \ascii[0]_i_6_n_0\ ); \ascii[0]_i_8\: unisim.vcomponents.LUT6 generic map( INIT => X"EDBDFDFFEEB90344" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(0), I3 => ps2_code(5), I4 => ps2_code(3), I5 => ps2_code(4), O => \ascii[0]_i_8_n_0\ ); \ascii[0]_i_9\: unisim.vcomponents.LUT6 generic map( INIT => X"DCFDFFD701000888" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(3), I3 => ps2_code(0), I4 => ps2_code(5), I5 => ps2_code(4), O => \ascii[0]_i_9_n_0\ ); \ascii[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CDC8" ) port map ( I0 => control_r_reg_0, I1 => \ascii[1]_i_2_n_0\, I2 => control_l_reg_0, I3 => \ascii[1]_i_3_n_0\, O => \ascii_reg[6]\(1) ); \ascii[1]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"6632FFFF66320000" ) port map ( I0 => ps2_code(6), I1 => ps2_code(0), I2 => ps2_code(4), I3 => ps2_code(3), I4 => ps2_code(2), I5 => \ascii[1]_i_4_n_0\, O => \ascii[1]_i_2_n_0\ ); \ascii[1]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"CDC8" ) port map ( I0 => shift_l, I1 => \ascii[1]_i_5_n_0\, I2 => shift_r, I3 => \ascii[1]_i_6_n_0\, O => \ascii[1]_i_3_n_0\ ); \ascii[1]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"55559DCDFFFFFFFF" ) port map ( I0 => ps2_code(0), I1 => ps2_code(3), I2 => ps2_code(5), I3 => ps2_code(4), I4 => ps2_code(6), I5 => ps2_code(1), O => \ascii[1]_i_4_n_0\ ); \ascii[1]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"2F202F2F2F202020" ) port map ( I0 => ps2_code(4), I1 => ps2_code(3), I2 => ps2_code(7), I3 => \ascii[1]_i_7_n_0\, I4 => ps2_code(2), I5 => \ascii[1]_i_8_n_0\, O => \ascii[1]_i_5_n_0\ ); \ascii[1]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"2F202F2F2F202020" ) port map ( I0 => ps2_code(4), I1 => ps2_code(3), I2 => ps2_code(7), I3 => \ascii[1]_i_9_n_0\, I4 => ps2_code(2), I5 => \ascii[1]_i_8_n_0\, O => \ascii[1]_i_6_n_0\ ); \ascii[1]_i_7\: unisim.vcomponents.LUT6 generic map( INIT => X"1120100EEEFD0024" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(5), I3 => ps2_code(0), I4 => ps2_code(4), I5 => ps2_code(3), O => \ascii[1]_i_7_n_0\ ); \ascii[1]_i_8\: unisim.vcomponents.LUT6 generic map( INIT => X"20222248DFFF1008" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(0), I3 => ps2_code(5), I4 => ps2_code(4), I5 => ps2_code(3), O => \ascii[1]_i_8_n_0\ ); \ascii[1]_i_9\: unisim.vcomponents.LUT6 generic map( INIT => X"11021004EAFD0024" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(5), I3 => ps2_code(0), I4 => ps2_code(4), I5 => ps2_code(3), O => \ascii[1]_i_9_n_0\ ); \ascii[2]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CDC8" ) port map ( I0 => control_r_reg_0, I1 => \ascii_reg[2]_i_2_n_0\, I2 => control_l_reg_0, I3 => \ascii[2]_i_3_n_0\, O => \ascii_reg[6]\(2) ); \ascii[2]_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"8AAA8E8ADEDDF777" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(4), I3 => ps2_code(0), I4 => ps2_code(5), I5 => ps2_code(3), O => \ascii[2]_i_10_n_0\ ); \ascii[2]_i_11\: unisim.vcomponents.LUT6 generic map( INIT => X"8AAA8E8ADEDDF7F7" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(4), I3 => ps2_code(0), I4 => ps2_code(5), I5 => ps2_code(3), O => \ascii[2]_i_11_n_0\ ); \ascii[2]_i_12\: unisim.vcomponents.LUT6 generic map( INIT => X"1504001010303814" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(5), I3 => ps2_code(3), I4 => ps2_code(4), I5 => ps2_code(0), O => \ascii[2]_i_12_n_0\ ); \ascii[2]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"CDC8CDCDCDC8C8C8" ) port map ( I0 => shift_l, I1 => \ascii[2]_i_6_n_0\, I2 => shift_r, I3 => \ascii[2]_i_7_n_0\, I4 => ps2_code(7), I5 => \ascii_reg[2]_i_8_n_0\, O => \ascii[2]_i_3_n_0\ ); \ascii[2]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"0FAFF0C0EF00CFC0" ) port map ( I0 => ps2_code(6), I1 => ps2_code(3), I2 => ps2_code(1), I3 => ps2_code(5), I4 => ps2_code(4), I5 => ps2_code(0), O => \ascii[2]_i_4_n_0\ ); \ascii[2]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"5FF0AAFA4EF0FFFF" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(5), I3 => ps2_code(0), I4 => ps2_code(4), I5 => ps2_code(3), O => \ascii[2]_i_5_n_0\ ); \ascii[2]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"0F00DFDF0F00D0D0" ) port map ( I0 => ps2_code(3), I1 => ps2_code(1), I2 => ps2_code(7), I3 => \ascii[2]_i_9_n_0\, I4 => ps2_code(2), I5 => \ascii[2]_i_10_n_0\, O => \ascii[2]_i_6_n_0\ ); \ascii[2]_i_7\: unisim.vcomponents.LUT3 generic map( INIT => X"0D" ) port map ( I0 => ps2_code(3), I1 => ps2_code(1), I2 => ps2_code(2), O => \ascii[2]_i_7_n_0\ ); \ascii[2]_i_9\: unisim.vcomponents.LUT6 generic map( INIT => X"1500001010303A14" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(5), I3 => ps2_code(3), I4 => ps2_code(4), I5 => ps2_code(0), O => \ascii[2]_i_9_n_0\ ); \ascii[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CDC8" ) port map ( I0 => control_r_reg_0, I1 => \ascii_reg[3]_i_2_n_0\, I2 => control_l_reg_0, I3 => \ascii[3]_i_3_n_0\, O => \ascii_reg[6]\(3) ); \ascii[3]_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"EEECFECDEBCDEBCF" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(5), I3 => ps2_code(0), I4 => ps2_code(3), I5 => ps2_code(4), O => \ascii[3]_i_10_n_0\ ); \ascii[3]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"CDC8" ) port map ( I0 => shift_l, I1 => \ascii[3]_i_6_n_0\, I2 => shift_r, I3 => \ascii[3]_i_7_n_0\, O => \ascii[3]_i_3_n_0\ ); \ascii[3]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"EFE2333F" ) port map ( I0 => ps2_code(6), I1 => ps2_code(5), I2 => ps2_code(0), I3 => ps2_code(3), I4 => ps2_code(4), O => \ascii[3]_i_4_n_0\ ); \ascii[3]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"FF444444F4F444F4" ) port map ( I0 => ps2_code(3), I1 => ps2_code(1), I2 => ps2_code(6), I3 => ps2_code(0), I4 => ps2_code(4), I5 => ps2_code(5), O => \ascii[3]_i_5_n_0\ ); \ascii[3]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"FFF0DFDFFFF0D0D0" ) port map ( I0 => ps2_code(0), I1 => ps2_code(6), I2 => ps2_code(7), I3 => \ascii[3]_i_8_n_0\, I4 => ps2_code(2), I5 => \ascii[3]_i_9_n_0\, O => \ascii[3]_i_6_n_0\ ); \ascii[3]_i_7\: unisim.vcomponents.LUT6 generic map( INIT => X"FFF0DFDFFFF0D0D0" ) port map ( I0 => ps2_code(0), I1 => ps2_code(6), I2 => ps2_code(7), I3 => \ascii[3]_i_10_n_0\, I4 => ps2_code(2), I5 => \ascii[3]_i_9_n_0\, O => \ascii[3]_i_7_n_0\ ); \ascii[3]_i_8\: unisim.vcomponents.LUT6 generic map( INIT => X"EEECFEEDEBCFEFCF" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(5), I3 => ps2_code(0), I4 => ps2_code(3), I5 => ps2_code(4), O => \ascii[3]_i_8_n_0\ ); \ascii[3]_i_9\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFDFFB313D333" ) port map ( I0 => ps2_code(1), I1 => ps2_code(0), I2 => ps2_code(5), I3 => ps2_code(4), I4 => ps2_code(3), I5 => ps2_code(6), O => \ascii[3]_i_9_n_0\ ); \ascii[4]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CDC8" ) port map ( I0 => control_r_reg_0, I1 => \ascii[4]_i_2_n_0\, I2 => control_l_reg_0, I3 => \ascii[4]_i_3_n_0\, O => \ascii_reg[6]\(4) ); \ascii[4]_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"15321434FFEF1428" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(5), I3 => ps2_code(0), I4 => ps2_code(4), I5 => ps2_code(3), O => \ascii[4]_i_10_n_0\ ); \ascii[4]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"CFCCC3FFCCCC8CB8" ) port map ( I0 => ps2_code(1), I1 => ps2_code(2), I2 => ps2_code(5), I3 => ps2_code(4), I4 => ps2_code(0), I5 => ps2_code(3), O => \ascii[4]_i_2_n_0\ ); \ascii[4]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"CDC8CDCDCDC8C8C8" ) port map ( I0 => shift_l, I1 => \ascii[4]_i_4_n_0\, I2 => shift_r, I3 => \ascii[4]_i_5_n_0\, I4 => ps2_code(7), I5 => \ascii_reg[4]_i_6_n_0\, O => \ascii[4]_i_3_n_0\ ); \ascii[4]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"2F202F2F2F202020" ) port map ( I0 => ps2_code(4), I1 => ps2_code(3), I2 => ps2_code(7), I3 => \ascii[4]_i_7_n_0\, I4 => ps2_code(2), I5 => \ascii[4]_i_8_n_0\, O => \ascii[4]_i_4_n_0\ ); \ascii[4]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => ps2_code(4), I1 => ps2_code(3), O => \ascii[4]_i_5_n_0\ ); \ascii[4]_i_7\: unisim.vcomponents.LUT6 generic map( INIT => X"0510141EFBED0000" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(5), I3 => ps2_code(0), I4 => ps2_code(4), I5 => ps2_code(3), O => \ascii[4]_i_7_n_0\ ); \ascii[4]_i_8\: unisim.vcomponents.LUT6 generic map( INIT => X"00A20248CDF70240" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(0), I3 => ps2_code(5), I4 => ps2_code(4), I5 => ps2_code(3), O => \ascii[4]_i_8_n_0\ ); \ascii[4]_i_9\: unisim.vcomponents.LUT6 generic map( INIT => X"00A20200CDF70200" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(0), I3 => ps2_code(5), I4 => ps2_code(4), I5 => ps2_code(3), O => \ascii[4]_i_9_n_0\ ); \ascii[5]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"CDC8" ) port map ( I0 => control_r_reg_0, I1 => \ascii[6]_i_4_n_0\, I2 => control_l_reg_0, I3 => \ascii[5]_i_2_n_0\, O => \ascii_reg[6]\(5) ); \ascii[5]_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF8F4C8080" ) port map ( I0 => ps2_code(3), I1 => ps2_code(1), I2 => ps2_code(4), I3 => ps2_code(0), I4 => ps2_code(6), I5 => ps2_code(5), O => \ascii[5]_i_10_n_0\ ); \ascii[5]_i_11\: unisim.vcomponents.LUT6 generic map( INIT => X"111131335544166C" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(3), I3 => ps2_code(4), I4 => ps2_code(0), I5 => ps2_code(5), O => \ascii[5]_i_11_n_0\ ); \ascii[5]_i_12\: unisim.vcomponents.LUT6 generic map( INIT => X"F5F5F0F590201080" ) port map ( I0 => ps2_code(1), I1 => ps2_code(4), I2 => ps2_code(6), I3 => ps2_code(0), I4 => ps2_code(3), I5 => ps2_code(5), O => \ascii[5]_i_12_n_0\ ); \ascii[5]_i_13\: unisim.vcomponents.LUT6 generic map( INIT => X"1202001240064648" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(0), I3 => ps2_code(4), I4 => ps2_code(3), I5 => ps2_code(5), O => \ascii[5]_i_13_n_0\ ); \ascii[5]_i_14\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF0F4C8080" ) port map ( I0 => ps2_code(3), I1 => ps2_code(1), I2 => ps2_code(4), I3 => ps2_code(0), I4 => ps2_code(6), I5 => ps2_code(5), O => \ascii[5]_i_14_n_0\ ); \ascii[5]_i_15\: unisim.vcomponents.LUT6 generic map( INIT => X"11113333154432EC" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(3), I3 => ps2_code(4), I4 => ps2_code(0), I5 => ps2_code(5), O => \ascii[5]_i_15_n_0\ ); \ascii[5]_i_16\: unisim.vcomponents.LUT6 generic map( INIT => X"F5F5F0F510201080" ) port map ( I0 => ps2_code(1), I1 => ps2_code(4), I2 => ps2_code(6), I3 => ps2_code(0), I4 => ps2_code(3), I5 => ps2_code(5), O => \ascii[5]_i_16_n_0\ ); \ascii[5]_i_17\: unisim.vcomponents.LUT6 generic map( INIT => X"12020212020E4248" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(0), I3 => ps2_code(4), I4 => ps2_code(3), I5 => ps2_code(5), O => \ascii[5]_i_17_n_0\ ); \ascii[5]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"CDC8CDCDCDC8C8C8" ) port map ( I0 => shift_l, I1 => \ascii[5]_i_3_n_0\, I2 => shift_r, I3 => \ascii[5]_i_4_n_0\, I4 => ps2_code(7), I5 => \ascii_reg[5]_i_5_n_0\, O => \ascii[5]_i_2_n_0\ ); \ascii[5]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"2F202F2F2F202020" ) port map ( I0 => ps2_code(5), I1 => ps2_code(2), I2 => ps2_code(7), I3 => \ascii_reg[5]_i_6_n_0\, I4 => caps_lock_reg_0, I5 => \ascii_reg[5]_i_7_n_0\, O => \ascii[5]_i_3_n_0\ ); \ascii[5]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => ps2_code(5), I1 => ps2_code(2), O => \ascii[5]_i_4_n_0\ ); \ascii[6]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \ascii[6]_i_3_n_0\, I1 => Q(0), O => E(0) ); \ascii[6]_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"00B030300000C0C0" ) port map ( I0 => e0_code, I1 => ps2_code(6), I2 => ps2_code(0), I3 => ps2_code(3), I4 => ps2_code(4), I5 => ps2_code(5), O => \ascii[6]_i_10_n_0\ ); \ascii[6]_i_11\: unisim.vcomponents.LUT5 generic map( INIT => X"3333F4CC" ) port map ( I0 => ps2_code(0), I1 => ps2_code(6), I2 => ps2_code(3), I3 => ps2_code(4), I4 => ps2_code(5), O => \ascii[6]_i_11_n_0\ ); \ascii[6]_i_12\: unisim.vcomponents.LUT6 generic map( INIT => X"11113B3B555436EC" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(3), I3 => ps2_code(4), I4 => ps2_code(0), I5 => ps2_code(5), O => \ascii[6]_i_12_n_0\ ); \ascii[6]_i_13\: unisim.vcomponents.LUT6 generic map( INIT => X"0C040404C8C8F0C0" ) port map ( I0 => ps2_code(4), I1 => ps2_code(1), I2 => ps2_code(5), I3 => ps2_code(0), I4 => ps2_code(3), I5 => ps2_code(6), O => \ascii[6]_i_13_n_0\ ); \ascii[6]_i_14\: unisim.vcomponents.LUT6 generic map( INIT => X"0513141811340014" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(5), I3 => ps2_code(0), I4 => ps2_code(4), I5 => ps2_code(3), O => \ascii[6]_i_14_n_0\ ); \ascii[6]_i_15\: unisim.vcomponents.LUT6 generic map( INIT => X"0513141A11340014" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(5), I3 => ps2_code(0), I4 => ps2_code(4), I5 => ps2_code(3), O => \ascii[6]_i_15_n_0\ ); \ascii[6]_i_16\: unisim.vcomponents.LUT6 generic map( INIT => X"FCFFFCFCC8400840" ) port map ( I0 => ps2_code(4), I1 => ps2_code(1), I2 => ps2_code(6), I3 => ps2_code(3), I4 => ps2_code(0), I5 => ps2_code(5), O => \ascii[6]_i_16_n_0\ ); \ascii[6]_i_17\: unisim.vcomponents.LUT6 generic map( INIT => X"0511141211140014" ) port map ( I0 => ps2_code(1), I1 => ps2_code(6), I2 => ps2_code(5), I3 => ps2_code(0), I4 => ps2_code(4), I5 => ps2_code(3), O => \ascii[6]_i_17_n_0\ ); \ascii[6]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"CDC8" ) port map ( I0 => control_r_reg_0, I1 => \ascii[6]_i_4_n_0\, I2 => control_l_reg_0, I3 => \ascii[6]_i_5_n_0\, O => \ascii_reg[6]\(6) ); \ascii[6]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"F0E20000" ) port map ( I0 => \ascii[6]_i_6_n_0\, I1 => control_l_reg_0, I2 => \ascii[6]_i_7_n_0\, I3 => control_r_reg_0, I4 => Q(1), O => \ascii[6]_i_3_n_0\ ); \ascii[6]_i_4\: unisim.vcomponents.LUT4 generic map( INIT => X"0008" ) port map ( I0 => ps2_code(6), I1 => ps2_code(3), I2 => ps2_code(0), I3 => ps2_code(2), O => \ascii[6]_i_4_n_0\ ); \ascii[6]_i_5\: unisim.vcomponents.LUT4 generic map( INIT => X"CDC8" ) port map ( I0 => shift_l, I1 => \ascii[6]_i_8_n_0\, I2 => shift_r, I3 => \ascii[6]_i_9_n_0\, O => \ascii[6]_i_5_n_0\ ); \ascii[6]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"00000000FFE200E2" ) port map ( I0 => \ascii[6]_i_10_n_0\, I1 => ps2_code(1), I2 => \ascii[6]_i_11_n_0\, I3 => ps2_code(2), I4 => \ascii[6]_i_12_n_0\, I5 => ps2_code(7), O => \ascii[6]_i_6_n_0\ ); \ascii[6]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"00E2" ) port map ( I0 => \ascii[6]_i_13_n_0\, I1 => ps2_code(2), I2 => \ascii[6]_i_14_n_0\, I3 => ps2_code(7), O => \ascii[6]_i_7_n_0\ ); \ascii[6]_i_8\: unisim.vcomponents.LUT6 generic map( INIT => X"0F008F8F0F008080" ) port map ( I0 => ps2_code(6), I1 => ps2_code(5), I2 => ps2_code(7), I3 => \ascii[6]_i_15_n_0\, I4 => ps2_code(2), I5 => \ascii[6]_i_16_n_0\, O => \ascii[6]_i_8_n_0\ ); \ascii[6]_i_9\: unisim.vcomponents.LUT6 generic map( INIT => X"0F008F8F0F008080" ) port map ( I0 => ps2_code(6), I1 => ps2_code(5), I2 => ps2_code(7), I3 => \ascii[6]_i_17_n_0\, I4 => ps2_code(2), I5 => \ascii[6]_i_16_n_0\, O => \ascii[6]_i_9_n_0\ ); \ascii[7]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FF0FFFFF0D0F0D00" ) port map ( I0 => ps2_code(7), I1 => \state[1]_i_2_n_0\, I2 => Q(1), I3 => Q(0), I4 => \ascii[6]_i_3_n_0\, I5 => \ascii_reg[7]_0\, O => \ascii_reg[7]\ ); \ascii_reg[0]_i_7\: unisim.vcomponents.MUXF7 port map ( I0 => \ascii[0]_i_10_n_0\, I1 => \ascii[0]_i_11_n_0\, O => \ascii_reg[0]_i_7_n_0\, S => ps2_code(2) ); \ascii_reg[2]_i_2\: unisim.vcomponents.MUXF7 port map ( I0 => \ascii[2]_i_4_n_0\, I1 => \ascii[2]_i_5_n_0\, O => \ascii_reg[2]_i_2_n_0\, S => ps2_code(2) ); \ascii_reg[2]_i_8\: unisim.vcomponents.MUXF7 port map ( I0 => \ascii[2]_i_11_n_0\, I1 => \ascii[2]_i_12_n_0\, O => \ascii_reg[2]_i_8_n_0\, S => ps2_code(2) ); \ascii_reg[3]_i_2\: unisim.vcomponents.MUXF7 port map ( I0 => \ascii[3]_i_4_n_0\, I1 => \ascii[3]_i_5_n_0\, O => \ascii_reg[3]_i_2_n_0\, S => ps2_code(2) ); \ascii_reg[4]_i_6\: unisim.vcomponents.MUXF7 port map ( I0 => \ascii[4]_i_9_n_0\, I1 => \ascii[4]_i_10_n_0\, O => \ascii_reg[4]_i_6_n_0\, S => ps2_code(2) ); \ascii_reg[5]_i_5\: unisim.vcomponents.MUXF8 port map ( I0 => \ascii_reg[5]_i_8_n_0\, I1 => \ascii_reg[5]_i_9_n_0\, O => \ascii_reg[5]_i_5_n_0\, S => caps_lock_reg_0 ); \ascii_reg[5]_i_6\: unisim.vcomponents.MUXF7 port map ( I0 => \ascii[5]_i_10_n_0\, I1 => \ascii[5]_i_11_n_0\, O => \ascii_reg[5]_i_6_n_0\, S => ps2_code(2) ); \ascii_reg[5]_i_7\: unisim.vcomponents.MUXF7 port map ( I0 => \ascii[5]_i_12_n_0\, I1 => \ascii[5]_i_13_n_0\, O => \ascii_reg[5]_i_7_n_0\, S => ps2_code(2) ); \ascii_reg[5]_i_8\: unisim.vcomponents.MUXF7 port map ( I0 => \ascii[5]_i_14_n_0\, I1 => \ascii[5]_i_15_n_0\, O => \ascii_reg[5]_i_8_n_0\, S => ps2_code(2) ); \ascii_reg[5]_i_9\: unisim.vcomponents.MUXF7 port map ( I0 => \ascii[5]_i_16_n_0\, I1 => \ascii[5]_i_17_n_0\, O => \ascii_reg[5]_i_9_n_0\, S => ps2_code(2) ); break_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FF00FFFF00000800" ) port map ( I0 => ps2_code(7), I1 => break_i_2_n_0, I2 => ps2_code(2), I3 => Q(0), I4 => Q(1), I5 => break, O => break_reg ); break_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000200000" ) port map ( I0 => ps2_code(6), I1 => ps2_code(0), I2 => ps2_code(4), I3 => ps2_code(3), I4 => ps2_code(5), I5 => ps2_code(1), O => break_i_2_n_0 ); caps_lock_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFEFFFFF00100000" ) port map ( I0 => Q(0), I1 => break, I2 => caps_lock_i_2_n_0, I3 => ps2_code(7), I4 => Q(1), I5 => caps_lock_reg_0, O => caps_lock_reg ); caps_lock_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000010000" ) port map ( I0 => ps2_code(1), I1 => ps2_code(5), I2 => shift_r_i_3_n_0, I3 => ps2_code(0), I4 => ps2_code(6), I5 => ps2_code(2), O => caps_lock_i_2_n_0 ); control_l_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFF7F00000040" ) port map ( I0 => break, I1 => Q(1), I2 => control_l_i_2_n_0, I3 => ps2_code(7), I4 => Q(0), I5 => control_l_reg_0, O => control_l_reg ); control_l_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000001000000000" ) port map ( I0 => ps2_code(1), I1 => e0_code, I2 => control_r_i_3_n_0, I3 => ps2_code(5), I4 => ps2_code(6), I5 => ps2_code(2), O => control_l_i_2_n_0 ); control_r_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFF7F00000040" ) port map ( I0 => break, I1 => Q(1), I2 => control_r_i_2_n_0, I3 => ps2_code(7), I4 => Q(0), I5 => control_r_reg_0, O => control_r_reg ); control_r_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000004000000000" ) port map ( I0 => ps2_code(1), I1 => e0_code, I2 => control_r_i_3_n_0, I3 => ps2_code(5), I4 => ps2_code(6), I5 => ps2_code(2), O => control_r_i_2_n_0 ); control_r_i_3: unisim.vcomponents.LUT3 generic map( INIT => X"04" ) port map ( I0 => ps2_code(3), I1 => ps2_code(4), I2 => ps2_code(0), O => control_r_i_3_n_0 ); \count_idle[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => ps2_clk_int, O => clear ); \count_idle[0]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"DF" ) port map ( I0 => count_idle_reg(10), I1 => \count_idle[0]_i_4_n_0\, I2 => count_idle_reg(12), O => \count_idle[0]_i_2_n_0\ ); \count_idle[0]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF7FFFFFFFFFF" ) port map ( I0 => count_idle_reg(7), I1 => count_idle_reg(5), I2 => \count_idle[0]_i_9_n_0\, I3 => count_idle_reg(4), I4 => count_idle_reg(9), I5 => count_idle_reg(8), O => \count_idle[0]_i_4_n_0\ ); \count_idle[0]_i_8\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => count_idle_reg(0), O => \count_idle[0]_i_8_n_0\ ); \count_idle[0]_i_9\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFDFFFFFFFF" ) port map ( I0 => count_idle_reg(0), I1 => count_idle_reg(2), I2 => count_idle_reg(6), I3 => count_idle_reg(11), I4 => count_idle_reg(3), I5 => count_idle_reg(1), O => \count_idle[0]_i_9_n_0\ ); \count_idle_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \count_idle[0]_i_2_n_0\, D => \count_idle_reg[0]_i_3_n_7\, Q => count_idle_reg(0), R => clear ); \count_idle_reg[0]_i_3\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \count_idle_reg[0]_i_3_n_0\, CO(2 downto 0) => \NLW_count_idle_reg[0]_i_3_CO_UNCONNECTED\(2 downto 0), CYINIT => '0', DI(3 downto 0) => B"0001", O(3) => \count_idle_reg[0]_i_3_n_4\, O(2) => \count_idle_reg[0]_i_3_n_5\, O(1) => \count_idle_reg[0]_i_3_n_6\, O(0) => \count_idle_reg[0]_i_3_n_7\, S(3 downto 1) => count_idle_reg(3 downto 1), S(0) => \count_idle[0]_i_8_n_0\ ); \count_idle_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \count_idle[0]_i_2_n_0\, D => \count_idle_reg[8]_i_1_n_5\, Q => count_idle_reg(10), R => clear ); \count_idle_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \count_idle[0]_i_2_n_0\, D => \count_idle_reg[8]_i_1_n_4\, Q => count_idle_reg(11), R => clear ); \count_idle_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \count_idle[0]_i_2_n_0\, D => \count_idle_reg[12]_i_1_n_7\, Q => count_idle_reg(12), R => clear ); \count_idle_reg[12]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \count_idle_reg[8]_i_1_n_0\, CO(3 downto 0) => \NLW_count_idle_reg[12]_i_1_CO_UNCONNECTED\(3 downto 0), CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 1) => \NLW_count_idle_reg[12]_i_1_O_UNCONNECTED\(3 downto 1), O(0) => \count_idle_reg[12]_i_1_n_7\, S(3 downto 1) => B"000", S(0) => count_idle_reg(12) ); \count_idle_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \count_idle[0]_i_2_n_0\, D => \count_idle_reg[0]_i_3_n_6\, Q => count_idle_reg(1), R => clear ); \count_idle_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \count_idle[0]_i_2_n_0\, D => \count_idle_reg[0]_i_3_n_5\, Q => count_idle_reg(2), R => clear ); \count_idle_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \count_idle[0]_i_2_n_0\, D => \count_idle_reg[0]_i_3_n_4\, Q => count_idle_reg(3), R => clear ); \count_idle_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \count_idle[0]_i_2_n_0\, D => \count_idle_reg[4]_i_1_n_7\, Q => count_idle_reg(4), R => clear ); \count_idle_reg[4]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \count_idle_reg[0]_i_3_n_0\, CO(3) => \count_idle_reg[4]_i_1_n_0\, CO(2 downto 0) => \NLW_count_idle_reg[4]_i_1_CO_UNCONNECTED\(2 downto 0), CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \count_idle_reg[4]_i_1_n_4\, O(2) => \count_idle_reg[4]_i_1_n_5\, O(1) => \count_idle_reg[4]_i_1_n_6\, O(0) => \count_idle_reg[4]_i_1_n_7\, S(3 downto 0) => count_idle_reg(7 downto 4) ); \count_idle_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \count_idle[0]_i_2_n_0\, D => \count_idle_reg[4]_i_1_n_6\, Q => count_idle_reg(5), R => clear ); \count_idle_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \count_idle[0]_i_2_n_0\, D => \count_idle_reg[4]_i_1_n_5\, Q => count_idle_reg(6), R => clear ); \count_idle_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \count_idle[0]_i_2_n_0\, D => \count_idle_reg[4]_i_1_n_4\, Q => count_idle_reg(7), R => clear ); \count_idle_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \count_idle[0]_i_2_n_0\, D => \count_idle_reg[8]_i_1_n_7\, Q => count_idle_reg(8), R => clear ); \count_idle_reg[8]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \count_idle_reg[4]_i_1_n_0\, CO(3) => \count_idle_reg[8]_i_1_n_0\, CO(2 downto 0) => \NLW_count_idle_reg[8]_i_1_CO_UNCONNECTED\(2 downto 0), CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \count_idle_reg[8]_i_1_n_4\, O(2) => \count_idle_reg[8]_i_1_n_5\, O(1) => \count_idle_reg[8]_i_1_n_6\, O(0) => \count_idle_reg[8]_i_1_n_7\, S(3 downto 0) => count_idle_reg(11 downto 8) ); \count_idle_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \count_idle[0]_i_2_n_0\, D => \count_idle_reg[8]_i_1_n_6\, Q => count_idle_reg(9), R => clear ); e0_code_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FF00FFFF00000800" ) port map ( I0 => ps2_code(7), I1 => e0_code_i_2_n_0, I2 => ps2_code(2), I3 => Q(0), I4 => Q(1), I5 => e0_code, O => e0_code_reg ); e0_code_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000020000" ) port map ( I0 => ps2_code(6), I1 => ps2_code(0), I2 => ps2_code(4), I3 => ps2_code(3), I4 => ps2_code(5), I5 => ps2_code(1), O => e0_code_i_2_n_0 ); ps2_clk_int_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => '1', D => PS2Clk_IBUF, Q => ps2_clk_int, R => '0' ); ps2_code_new_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"8000" ) port map ( I0 => count_idle_reg(10), I1 => ps2_code_new_i_2_n_0, I2 => count_idle_reg(8), I3 => count_idle_reg(12), O => ps2_code_new0 ); ps2_code_new_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"4000000000000000" ) port map ( I0 => count_idle_reg(9), I1 => count_idle_reg(4), I2 => ps2_code_new_i_3_n_0, I3 => count_idle_reg(1), I4 => count_idle_reg(5), I5 => count_idle_reg(7), O => ps2_code_new_i_2_n_0 ); ps2_code_new_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"0000001000000000" ) port map ( I0 => count_idle_reg(3), I1 => count_idle_reg(11), I2 => ps2_code_new_i_4_n_0, I3 => count_idle_reg(6), I4 => count_idle_reg(2), I5 => count_idle_reg(0), O => ps2_code_new_i_3_n_0 ); ps2_code_new_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"FF96FF6969009600" ) port map ( I0 => ps2_word(9), I1 => ps2_word(7), I2 => ps2_word(8), I3 => ps2_code_new_i_5_n_0, I4 => ps2_word(5), I5 => ps2_code_new_i_6_n_0, O => ps2_code_new_i_4_n_0 ); ps2_code_new_i_5: unisim.vcomponents.LUT6 generic map( INIT => X"6996000096690000" ) port map ( I0 => ps2_word(6), I1 => ps2_word(3), I2 => ps2_word(4), I3 => ps2_word(1), I4 => ps2_code_new_i_7_n_0, I5 => ps2_word(2), O => ps2_code_new_i_5_n_0 ); ps2_code_new_i_6: unisim.vcomponents.LUT6 generic map( INIT => X"9669000069960000" ) port map ( I0 => ps2_word(6), I1 => ps2_word(3), I2 => ps2_word(4), I3 => ps2_word(1), I4 => ps2_code_new_i_7_n_0, I5 => ps2_word(2), O => ps2_code_new_i_6_n_0 ); ps2_code_new_i_7: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => ps2_word(10), I1 => ps2_word(0), O => ps2_code_new_i_7_n_0 ); ps2_code_new_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => '1', D => ps2_code_new0, Q => \^ps2_code_new\, R => '0' ); \ps2_code_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => ps2_code_new0, D => ps2_word(1), Q => ps2_code(0), R => '0' ); \ps2_code_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => ps2_code_new0, D => ps2_word(2), Q => ps2_code(1), R => '0' ); \ps2_code_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => ps2_code_new0, D => ps2_word(3), Q => ps2_code(2), R => '0' ); \ps2_code_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => ps2_code_new0, D => ps2_word(4), Q => ps2_code(3), R => '0' ); \ps2_code_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => ps2_code_new0, D => ps2_word(5), Q => ps2_code(4), R => '0' ); \ps2_code_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => ps2_code_new0, D => ps2_word(6), Q => ps2_code(5), R => '0' ); \ps2_code_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => ps2_code_new0, D => ps2_word(7), Q => ps2_code(6), R => '0' ); \ps2_code_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => ps2_code_new0, D => ps2_word(8), Q => ps2_code(7), R => '0' ); ps2_data_int_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => '1', D => PS2Data_IBUF, Q => ps2_data_int, R => '0' ); \ps2_word_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '1' ) port map ( C => ps2_clk_int, CE => '1', D => ps2_word(1), Q => ps2_word(0), R => '0' ); \ps2_word_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '1' ) port map ( C => ps2_clk_int, CE => '1', D => ps2_data_int, Q => ps2_word(10), R => '0' ); \ps2_word_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '1' ) port map ( C => ps2_clk_int, CE => '1', D => ps2_word(2), Q => ps2_word(1), R => '0' ); \ps2_word_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '1' ) port map ( C => ps2_clk_int, CE => '1', D => ps2_word(3), Q => ps2_word(2), R => '0' ); \ps2_word_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '1' ) port map ( C => ps2_clk_int, CE => '1', D => ps2_word(4), Q => ps2_word(3), R => '0' ); \ps2_word_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '1' ) port map ( C => ps2_clk_int, CE => '1', D => ps2_word(5), Q => ps2_word(4), R => '0' ); \ps2_word_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '1' ) port map ( C => ps2_clk_int, CE => '1', D => ps2_word(6), Q => ps2_word(5), R => '0' ); \ps2_word_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '1' ) port map ( C => ps2_clk_int, CE => '1', D => ps2_word(7), Q => ps2_word(6), R => '0' ); \ps2_word_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '1' ) port map ( C => ps2_clk_int, CE => '1', D => ps2_word(8), Q => ps2_word(7), R => '0' ); \ps2_word_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '1' ) port map ( C => ps2_clk_int, CE => '1', D => ps2_word(9), Q => ps2_word(8), R => '0' ); \ps2_word_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '1' ) port map ( C => ps2_clk_int, CE => '1', D => ps2_word(10), Q => ps2_word(9), R => '0' ); shift_l_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFF7F00000040" ) port map ( I0 => break, I1 => Q(1), I2 => shift_l_i_2_n_0, I3 => ps2_code(7), I4 => Q(0), I5 => shift_l, O => shift_l_reg ); shift_l_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000020" ) port map ( I0 => ps2_code(1), I1 => ps2_code(5), I2 => \ascii[4]_i_5_n_0\, I3 => ps2_code(0), I4 => ps2_code(6), I5 => ps2_code(2), O => shift_l_i_2_n_0 ); shift_r_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFF7F00000040" ) port map ( I0 => break, I1 => Q(1), I2 => shift_r_i_2_n_0, I3 => ps2_code(7), I4 => Q(0), I5 => shift_r, O => shift_r_reg ); shift_r_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000000001000000" ) port map ( I0 => ps2_code(1), I1 => ps2_code(5), I2 => shift_r_i_3_n_0, I3 => ps2_code(0), I4 => ps2_code(6), I5 => ps2_code(2), O => shift_r_i_2_n_0 ); shift_r_i_3: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => ps2_code(3), I1 => ps2_code(4), O => shift_r_i_3_n_0 ); \state[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"000004F4" ) port map ( I0 => prev_ps2_code_new, I1 => \^ps2_code_new\, I2 => Q(1), I3 => break, I4 => Q(0), O => D(0) ); \state[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"00D00FD0" ) port map ( I0 => ps2_code(7), I1 => \state[1]_i_2_n_0\, I2 => Q(0), I3 => Q(1), I4 => break, O => D(1) ); \state[1]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFBFFFF" ) port map ( I0 => ps2_code(1), I1 => ps2_code(5), I2 => ps2_code(3), I3 => ps2_code(0), I4 => ps2_code(6), I5 => ps2_code(2), O => \state[1]_i_2_n_0\ ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity ClockDivider is port ( clkIn : in STD_LOGIC; clk108M : out STD_LOGIC; clk10M : out STD_LOGIC ); attribute CORE_GENERATION_INFO : string; attribute CORE_GENERATION_INFO of ClockDivider : entity is "ClockDivider,clk_wiz_v5_2_1,{component_name=ClockDivider,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}"; end ClockDivider; architecture STRUCTURE of ClockDivider is begin inst: entity work.ClockDivider_ClockDivider_clk_wiz port map ( clk108M => clk108M, clk10M => clk10M, clkIn => clkIn ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity FrameBuffer_blk_mem_gen_prim_width is port ( \doutb[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); clka : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width"; end FrameBuffer_blk_mem_gen_prim_width; architecture STRUCTURE of FrameBuffer_blk_mem_gen_prim_width is begin \prim_init.ram\: entity work.FrameBuffer_blk_mem_gen_prim_wrapper_init port map ( addra(13 downto 0) => addra(13 downto 0), addrb(13 downto 0) => addrb(13 downto 0), clka => clka, clkb => clkb, dina(7 downto 0) => dina(7 downto 0), \doutb[7]\(7 downto 0) => \doutb[7]\(7 downto 0), wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \FrameBuffer_blk_mem_gen_prim_width__parameterized0\ is port ( \doutb[7]\ : out STD_LOGIC_VECTOR ( 7 downto 0 ); clka : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \FrameBuffer_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width"; end \FrameBuffer_blk_mem_gen_prim_width__parameterized0\; architecture STRUCTURE of \FrameBuffer_blk_mem_gen_prim_width__parameterized0\ is begin \prim_init.ram\: entity work.\FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized0\ port map ( addra(13 downto 0) => addra(13 downto 0), addrb(13 downto 0) => addrb(13 downto 0), clka => clka, clkb => clkb, dina(7 downto 0) => dina(7 downto 0), \doutb[7]\(7 downto 0) => \doutb[7]\(7 downto 0), wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity \FrameBuffer_blk_mem_gen_prim_width__parameterized1\ is port ( DOBDO : out STD_LOGIC_VECTOR ( 7 downto 0 ); clka : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of \FrameBuffer_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width"; end \FrameBuffer_blk_mem_gen_prim_width__parameterized1\; architecture STRUCTURE of \FrameBuffer_blk_mem_gen_prim_width__parameterized1\ is begin \prim_init.ram\: entity work.\FrameBuffer_blk_mem_gen_prim_wrapper_init__parameterized1\ port map ( DOBDO(7 downto 0) => DOBDO(7 downto 0), addra(13 downto 0) => addra(13 downto 0), addrb(13 downto 0) => addrb(13 downto 0), clka => clka, clkb => clkb, dina(7 downto 0) => dina(7 downto 0), wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity ps2_keyboard_to_ascii is port ( \next_s_reg[1]\ : out STD_LOGIC; \next_s_reg[0]\ : out STD_LOGIC; \counter_reg[0]\ : out STD_LOGIC; \fb_in_dat_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 ); \counter_reg[12]\ : out STD_LOGIC; PS2Clk_IBUF : in STD_LOGIC; clk_BUFG : in STD_LOGIC; PS2Data_IBUF : in STD_LOGIC; D : in STD_LOGIC_VECTOR ( 1 downto 0 ); \current_s_reg[0]\ : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 1 downto 0 ); \counter_reg[0]_0\ : in STD_LOGIC; \counter_reg[0]_1\ : in STD_LOGIC; \counter_reg[0]_2\ : in STD_LOGIC; \counter_reg[0]_3\ : in STD_LOGIC; \counter_reg[0]_4\ : in STD_LOGIC; \counter_reg[0]_5\ : in STD_LOGIC; \counter_reg[0]_6\ : in STD_LOGIC; \counter_reg[4]\ : in STD_LOGIC; \counter_reg[4]_0\ : in STD_LOGIC ); end ps2_keyboard_to_ascii; architecture STRUCTURE of ps2_keyboard_to_ascii is signal ascii_code : STD_LOGIC_VECTOR ( 6 downto 0 ); signal ascii_new : STD_LOGIC; signal ascii_new_i_1_n_0 : STD_LOGIC; signal ascii_new_i_2_n_0 : STD_LOGIC; signal ascii_new_i_3_n_0 : STD_LOGIC; signal ascii_new_i_4_n_0 : STD_LOGIC; signal ascii_new_i_5_n_0 : STD_LOGIC; signal ascii_new_i_6_n_0 : STD_LOGIC; signal ascii_new_i_7_n_0 : STD_LOGIC; signal ascii_new_i_8_n_0 : STD_LOGIC; signal ascii_new_i_9_n_0 : STD_LOGIC; signal \ascii_reg_n_0_[0]\ : STD_LOGIC; signal \ascii_reg_n_0_[1]\ : STD_LOGIC; signal \ascii_reg_n_0_[2]\ : STD_LOGIC; signal \ascii_reg_n_0_[3]\ : STD_LOGIC; signal \ascii_reg_n_0_[4]\ : STD_LOGIC; signal \ascii_reg_n_0_[5]\ : STD_LOGIC; signal \ascii_reg_n_0_[6]\ : STD_LOGIC; signal \ascii_reg_n_0_[7]\ : STD_LOGIC; signal break : STD_LOGIC; signal caps_lock_reg_n_0 : STD_LOGIC; signal control_l_reg_n_0 : STD_LOGIC; signal control_r_reg_n_0 : STD_LOGIC; signal e0_code : STD_LOGIC; signal prev_ps2_code_new : STD_LOGIC; signal ps2_code_new : STD_LOGIC; signal ps2_keyboard_0_n_1 : STD_LOGIC; signal ps2_keyboard_0_n_10 : STD_LOGIC; signal ps2_keyboard_0_n_11 : STD_LOGIC; signal ps2_keyboard_0_n_12 : STD_LOGIC; signal ps2_keyboard_0_n_13 : STD_LOGIC; signal ps2_keyboard_0_n_14 : STD_LOGIC; signal ps2_keyboard_0_n_15 : STD_LOGIC; signal ps2_keyboard_0_n_16 : STD_LOGIC; signal ps2_keyboard_0_n_17 : STD_LOGIC; signal ps2_keyboard_0_n_18 : STD_LOGIC; signal ps2_keyboard_0_n_2 : STD_LOGIC; signal ps2_keyboard_0_n_3 : STD_LOGIC; signal ps2_keyboard_0_n_4 : STD_LOGIC; signal ps2_keyboard_0_n_5 : STD_LOGIC; signal ps2_keyboard_0_n_6 : STD_LOGIC; signal ps2_keyboard_0_n_7 : STD_LOGIC; signal ps2_keyboard_0_n_8 : STD_LOGIC; signal ps2_keyboard_0_n_9 : STD_LOGIC; signal \repeat_counter[0]_i_10_n_0\ : STD_LOGIC; signal \repeat_counter[0]_i_11_n_0\ : STD_LOGIC; signal \repeat_counter[0]_i_12_n_0\ : STD_LOGIC; signal \repeat_counter[0]_i_1_n_0\ : STD_LOGIC; signal \repeat_counter[0]_i_3_n_0\ : STD_LOGIC; signal \repeat_counter[0]_i_4_n_0\ : STD_LOGIC; signal \repeat_counter[0]_i_5_n_0\ : STD_LOGIC; signal \repeat_counter[0]_i_6_n_0\ : STD_LOGIC; signal \repeat_counter[0]_i_7_n_0\ : STD_LOGIC; signal \repeat_counter[0]_i_8_n_0\ : STD_LOGIC; signal \repeat_counter[0]_i_9_n_0\ : STD_LOGIC; signal \repeat_counter[12]_i_2_n_0\ : STD_LOGIC; signal \repeat_counter[12]_i_3_n_0\ : STD_LOGIC; signal \repeat_counter[12]_i_4_n_0\ : STD_LOGIC; signal \repeat_counter[12]_i_5_n_0\ : STD_LOGIC; signal \repeat_counter[16]_i_2_n_0\ : STD_LOGIC; signal \repeat_counter[16]_i_3_n_0\ : STD_LOGIC; signal \repeat_counter[16]_i_4_n_0\ : STD_LOGIC; signal \repeat_counter[16]_i_5_n_0\ : STD_LOGIC; signal \repeat_counter[20]_i_2_n_0\ : STD_LOGIC; signal \repeat_counter[4]_i_2_n_0\ : STD_LOGIC; signal \repeat_counter[4]_i_3_n_0\ : STD_LOGIC; signal \repeat_counter[4]_i_4_n_0\ : STD_LOGIC; signal \repeat_counter[4]_i_5_n_0\ : STD_LOGIC; signal \repeat_counter[8]_i_2_n_0\ : STD_LOGIC; signal \repeat_counter[8]_i_3_n_0\ : STD_LOGIC; signal \repeat_counter[8]_i_4_n_0\ : STD_LOGIC; signal \repeat_counter[8]_i_5_n_0\ : STD_LOGIC; signal repeat_counter_reg : STD_LOGIC_VECTOR ( 20 downto 0 ); signal \repeat_counter_reg[0]_i_2_n_0\ : STD_LOGIC; signal \repeat_counter_reg[0]_i_2_n_4\ : STD_LOGIC; signal \repeat_counter_reg[0]_i_2_n_5\ : STD_LOGIC; signal \repeat_counter_reg[0]_i_2_n_6\ : STD_LOGIC; signal \repeat_counter_reg[0]_i_2_n_7\ : STD_LOGIC; signal \repeat_counter_reg[12]_i_1_n_0\ : STD_LOGIC; signal \repeat_counter_reg[12]_i_1_n_4\ : STD_LOGIC; signal \repeat_counter_reg[12]_i_1_n_5\ : STD_LOGIC; signal \repeat_counter_reg[12]_i_1_n_6\ : STD_LOGIC; signal \repeat_counter_reg[12]_i_1_n_7\ : STD_LOGIC; signal \repeat_counter_reg[16]_i_1_n_0\ : STD_LOGIC; signal \repeat_counter_reg[16]_i_1_n_4\ : STD_LOGIC; signal \repeat_counter_reg[16]_i_1_n_5\ : STD_LOGIC; signal \repeat_counter_reg[16]_i_1_n_6\ : STD_LOGIC; signal \repeat_counter_reg[16]_i_1_n_7\ : STD_LOGIC; signal \repeat_counter_reg[20]_i_1_n_7\ : STD_LOGIC; signal \repeat_counter_reg[4]_i_1_n_0\ : STD_LOGIC; signal \repeat_counter_reg[4]_i_1_n_4\ : STD_LOGIC; signal \repeat_counter_reg[4]_i_1_n_5\ : STD_LOGIC; signal \repeat_counter_reg[4]_i_1_n_6\ : STD_LOGIC; signal \repeat_counter_reg[4]_i_1_n_7\ : STD_LOGIC; signal \repeat_counter_reg[8]_i_1_n_0\ : STD_LOGIC; signal \repeat_counter_reg[8]_i_1_n_4\ : STD_LOGIC; signal \repeat_counter_reg[8]_i_1_n_5\ : STD_LOGIC; signal \repeat_counter_reg[8]_i_1_n_6\ : STD_LOGIC; signal \repeat_counter_reg[8]_i_1_n_7\ : STD_LOGIC; signal shift_l : STD_LOGIC; signal shift_r : STD_LOGIC; signal state : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \NLW_repeat_counter_reg[0]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_repeat_counter_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_repeat_counter_reg[16]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_repeat_counter_reg[20]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_repeat_counter_reg[20]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_repeat_counter_reg[4]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_repeat_counter_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); begin \ascii_code_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => ascii_new_i_1_n_0, D => \ascii_reg_n_0_[0]\, Q => ascii_code(0), R => '0' ); \ascii_code_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => ascii_new_i_1_n_0, D => \ascii_reg_n_0_[1]\, Q => ascii_code(1), R => '0' ); \ascii_code_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => ascii_new_i_1_n_0, D => \ascii_reg_n_0_[2]\, Q => ascii_code(2), R => '0' ); \ascii_code_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => ascii_new_i_1_n_0, D => \ascii_reg_n_0_[3]\, Q => ascii_code(3), R => '0' ); \ascii_code_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => ascii_new_i_1_n_0, D => \ascii_reg_n_0_[4]\, Q => ascii_code(4), R => '0' ); \ascii_code_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => ascii_new_i_1_n_0, D => \ascii_reg_n_0_[5]\, Q => ascii_code(5), R => '0' ); \ascii_code_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => ascii_new_i_1_n_0, D => \ascii_reg_n_0_[6]\, Q => ascii_code(6), R => '0' ); ascii_new_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"0000A80800000000" ) port map ( I0 => state(1), I1 => ascii_new_i_2_n_0, I2 => repeat_counter_reg(16), I3 => ascii_new_i_3_n_0, I4 => \ascii_reg_n_0_[7]\, I5 => state(0), O => ascii_new_i_1_n_0 ); ascii_new_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"FF00FF01FF00FE00" ) port map ( I0 => repeat_counter_reg(19), I1 => repeat_counter_reg(12), I2 => repeat_counter_reg(11), I3 => ascii_new_i_3_n_0, I4 => repeat_counter_reg(10), I5 => ascii_new_i_4_n_0, O => ascii_new_i_2_n_0 ); ascii_new_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFFE" ) port map ( I0 => \ascii_reg_n_0_[3]\, I1 => \ascii_reg_n_0_[5]\, I2 => ascii_new_i_5_n_0, I3 => \ascii_reg_n_0_[0]\, I4 => \ascii_reg_n_0_[4]\, I5 => \ascii_reg_n_0_[6]\, O => ascii_new_i_3_n_0 ); ascii_new_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"EFFFFFFF40000000" ) port map ( I0 => repeat_counter_reg(7), I1 => ascii_new_i_6_n_0, I2 => repeat_counter_reg(2), I3 => repeat_counter_reg(0), I4 => repeat_counter_reg(18), I5 => ascii_new_i_3_n_0, O => ascii_new_i_4_n_0 ); ascii_new_i_5: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => \ascii_reg_n_0_[2]\, I1 => \ascii_reg_n_0_[1]\, O => ascii_new_i_5_n_0 ); ascii_new_i_6: unisim.vcomponents.LUT6 generic map( INIT => X"EFFFFFFF40000000" ) port map ( I0 => repeat_counter_reg(5), I1 => ascii_new_i_7_n_0, I2 => repeat_counter_reg(6), I3 => repeat_counter_reg(17), I4 => repeat_counter_reg(1), I5 => ascii_new_i_3_n_0, O => ascii_new_i_6_n_0 ); ascii_new_i_7: unisim.vcomponents.LUT6 generic map( INIT => X"BFFFFFFF80000000" ) port map ( I0 => ascii_new_i_8_n_0, I1 => repeat_counter_reg(9), I2 => repeat_counter_reg(4), I3 => repeat_counter_reg(14), I4 => repeat_counter_reg(15), I5 => ascii_new_i_3_n_0, O => ascii_new_i_7_n_0 ); ascii_new_i_8: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFF8000" ) port map ( I0 => repeat_counter_reg(13), I1 => repeat_counter_reg(20), I2 => repeat_counter_reg(3), I3 => repeat_counter_reg(8), I4 => ascii_new_i_9_n_0, I5 => \ascii_reg_n_0_[6]\, O => ascii_new_i_8_n_0 ); ascii_new_i_9: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFFE" ) port map ( I0 => \ascii_reg_n_0_[4]\, I1 => \ascii_reg_n_0_[0]\, I2 => \ascii_reg_n_0_[2]\, I3 => \ascii_reg_n_0_[1]\, I4 => \ascii_reg_n_0_[5]\, I5 => \ascii_reg_n_0_[3]\, O => ascii_new_i_9_n_0 ); ascii_new_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => '1', D => ascii_new_i_1_n_0, Q => ascii_new, R => '0' ); \ascii_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_BUFG, CE => ps2_keyboard_0_n_18, D => ps2_keyboard_0_n_17, Q => \ascii_reg_n_0_[0]\, R => '0' ); \ascii_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_BUFG, CE => ps2_keyboard_0_n_18, D => ps2_keyboard_0_n_16, Q => \ascii_reg_n_0_[1]\, R => '0' ); \ascii_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_BUFG, CE => ps2_keyboard_0_n_18, D => ps2_keyboard_0_n_15, Q => \ascii_reg_n_0_[2]\, R => '0' ); \ascii_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_BUFG, CE => ps2_keyboard_0_n_18, D => ps2_keyboard_0_n_14, Q => \ascii_reg_n_0_[3]\, R => '0' ); \ascii_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_BUFG, CE => ps2_keyboard_0_n_18, D => ps2_keyboard_0_n_13, Q => \ascii_reg_n_0_[4]\, R => '0' ); \ascii_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_BUFG, CE => ps2_keyboard_0_n_18, D => ps2_keyboard_0_n_12, Q => \ascii_reg_n_0_[5]\, R => '0' ); \ascii_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_BUFG, CE => ps2_keyboard_0_n_18, D => ps2_keyboard_0_n_11, Q => \ascii_reg_n_0_[6]\, R => '0' ); \ascii_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_BUFG, CE => '1', D => ps2_keyboard_0_n_8, Q => \ascii_reg_n_0_[7]\, R => '0' ); break_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => '1', D => ps2_keyboard_0_n_1, Q => break, R => '0' ); caps_lock_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => '1', D => ps2_keyboard_0_n_7, Q => caps_lock_reg_n_0, R => '0' ); control_l_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => '1', D => ps2_keyboard_0_n_6, Q => control_l_reg_n_0, R => '0' ); control_r_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => '1', D => ps2_keyboard_0_n_5, Q => control_r_reg_n_0, R => '0' ); \counter[12]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"0003A0F3" ) port map ( I0 => ascii_new, I1 => \counter_reg[4]\, I2 => Q(1), I3 => Q(0), I4 => \counter_reg[4]_0\, O => \counter_reg[12]\ ); \counter[13]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"8F" ) port map ( I0 => Q(1), I1 => ascii_new, I2 => Q(0), O => \counter_reg[0]\ ); e0_code_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => '1', D => ps2_keyboard_0_n_4, Q => e0_code, R => '0' ); \fb_in_dat[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"8380" ) port map ( I0 => ascii_code(0), I1 => Q(0), I2 => Q(1), I3 => \counter_reg[0]_0\, O => \fb_in_dat_reg[6]\(0) ); \fb_in_dat[1]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"8380" ) port map ( I0 => ascii_code(1), I1 => Q(0), I2 => Q(1), I3 => \counter_reg[0]_1\, O => \fb_in_dat_reg[6]\(1) ); \fb_in_dat[2]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"8380" ) port map ( I0 => ascii_code(2), I1 => Q(0), I2 => Q(1), I3 => \counter_reg[0]_2\, O => \fb_in_dat_reg[6]\(2) ); \fb_in_dat[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"8380" ) port map ( I0 => ascii_code(3), I1 => Q(0), I2 => Q(1), I3 => \counter_reg[0]_3\, O => \fb_in_dat_reg[6]\(3) ); \fb_in_dat[4]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"8380" ) port map ( I0 => ascii_code(4), I1 => Q(0), I2 => Q(1), I3 => \counter_reg[0]_4\, O => \fb_in_dat_reg[6]\(4) ); \fb_in_dat[5]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"8380" ) port map ( I0 => ascii_code(5), I1 => Q(0), I2 => Q(1), I3 => \counter_reg[0]_5\, O => \fb_in_dat_reg[6]\(5) ); \fb_in_dat[6]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"8380" ) port map ( I0 => ascii_code(6), I1 => Q(0), I2 => Q(1), I3 => \counter_reg[0]_6\, O => \fb_in_dat_reg[6]\(6) ); \next_s[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"EEE0EEEE" ) port map ( I0 => D(0), I1 => \current_s_reg[0]\, I2 => Q(0), I3 => Q(1), I4 => ascii_new, O => \next_s_reg[0]\ ); \next_s[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"EEEEEEFE" ) port map ( I0 => D(1), I1 => \current_s_reg[0]\, I2 => ascii_new, I3 => Q(1), I4 => Q(0), O => \next_s_reg[1]\ ); prev_ps2_code_new_reg: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => clk_BUFG, CE => '1', D => ps2_code_new, Q => prev_ps2_code_new, R => '0' ); ps2_keyboard_0: entity work.ps2_keyboard port map ( D(1) => ps2_keyboard_0_n_9, D(0) => ps2_keyboard_0_n_10, E(0) => ps2_keyboard_0_n_18, PS2Clk_IBUF => PS2Clk_IBUF, PS2Data_IBUF => PS2Data_IBUF, Q(1 downto 0) => state(1 downto 0), \ascii_reg[6]\(6) => ps2_keyboard_0_n_11, \ascii_reg[6]\(5) => ps2_keyboard_0_n_12, \ascii_reg[6]\(4) => ps2_keyboard_0_n_13, \ascii_reg[6]\(3) => ps2_keyboard_0_n_14, \ascii_reg[6]\(2) => ps2_keyboard_0_n_15, \ascii_reg[6]\(1) => ps2_keyboard_0_n_16, \ascii_reg[6]\(0) => ps2_keyboard_0_n_17, \ascii_reg[7]\ => ps2_keyboard_0_n_8, \ascii_reg[7]_0\ => \ascii_reg_n_0_[7]\, break => break, break_reg => ps2_keyboard_0_n_1, caps_lock_reg => ps2_keyboard_0_n_7, caps_lock_reg_0 => caps_lock_reg_n_0, clk_BUFG => clk_BUFG, control_l_reg => ps2_keyboard_0_n_6, control_l_reg_0 => control_l_reg_n_0, control_r_reg => ps2_keyboard_0_n_5, control_r_reg_0 => control_r_reg_n_0, e0_code => e0_code, e0_code_reg => ps2_keyboard_0_n_4, prev_ps2_code_new => prev_ps2_code_new, ps2_code_new => ps2_code_new, shift_l => shift_l, shift_l_reg => ps2_keyboard_0_n_2, shift_r => shift_r, shift_r_reg => ps2_keyboard_0_n_3 ); \repeat_counter[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"00A80000" ) port map ( I0 => state(1), I1 => repeat_counter_reg(16), I2 => \repeat_counter[0]_i_3_n_0\, I3 => \ascii_reg_n_0_[7]\, I4 => state(0), O => \repeat_counter[0]_i_1_n_0\ ); \repeat_counter[0]_i_10\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000001" ) port map ( I0 => \ascii_reg_n_0_[3]\, I1 => \ascii_reg_n_0_[5]\, I2 => ascii_new_i_5_n_0, I3 => \ascii_reg_n_0_[0]\, I4 => \ascii_reg_n_0_[4]\, I5 => \ascii_reg_n_0_[6]\, O => \repeat_counter[0]_i_10_n_0\ ); \repeat_counter[0]_i_11\: unisim.vcomponents.LUT6 generic map( INIT => X"F7FFFFFFFFFFFFFF" ) port map ( I0 => repeat_counter_reg(6), I1 => repeat_counter_reg(14), I2 => \repeat_counter[0]_i_12_n_0\, I3 => repeat_counter_reg(4), I4 => repeat_counter_reg(15), I5 => repeat_counter_reg(17), O => \repeat_counter[0]_i_11_n_0\ ); \repeat_counter[0]_i_12\: unisim.vcomponents.LUT6 generic map( INIT => X"F7FFFFFFFFFFFFFF" ) port map ( I0 => repeat_counter_reg(8), I1 => repeat_counter_reg(20), I2 => ascii_new_i_3_n_0, I3 => repeat_counter_reg(13), I4 => repeat_counter_reg(3), I5 => repeat_counter_reg(9), O => \repeat_counter[0]_i_12_n_0\ ); \repeat_counter[0]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFFFFFE" ) port map ( I0 => repeat_counter_reg(12), I1 => repeat_counter_reg(10), I2 => \repeat_counter[0]_i_9_n_0\, I3 => repeat_counter_reg(7), I4 => repeat_counter_reg(11), I5 => repeat_counter_reg(19), O => \repeat_counter[0]_i_3_n_0\ ); \repeat_counter[0]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \repeat_counter[0]_i_10_n_0\, I1 => repeat_counter_reg(0), O => \repeat_counter[0]_i_4_n_0\ ); \repeat_counter[0]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \repeat_counter[0]_i_10_n_0\, I1 => repeat_counter_reg(3), O => \repeat_counter[0]_i_5_n_0\ ); \repeat_counter[0]_i_6\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \repeat_counter[0]_i_10_n_0\, I1 => repeat_counter_reg(2), O => \repeat_counter[0]_i_6_n_0\ ); \repeat_counter[0]_i_7\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \repeat_counter[0]_i_10_n_0\, I1 => repeat_counter_reg(1), O => \repeat_counter[0]_i_7_n_0\ ); \repeat_counter[0]_i_8\: unisim.vcomponents.LUT2 generic map( INIT => X"4" ) port map ( I0 => repeat_counter_reg(0), I1 => \repeat_counter[0]_i_10_n_0\, O => \repeat_counter[0]_i_8_n_0\ ); \repeat_counter[0]_i_9\: unisim.vcomponents.LUT6 generic map( INIT => X"FFF7FFFFFFFFFFFF" ) port map ( I0 => repeat_counter_reg(0), I1 => repeat_counter_reg(1), I2 => \repeat_counter[0]_i_11_n_0\, I3 => repeat_counter_reg(5), I4 => repeat_counter_reg(2), I5 => repeat_counter_reg(18), O => \repeat_counter[0]_i_9_n_0\ ); \repeat_counter[12]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \repeat_counter[0]_i_10_n_0\, I1 => repeat_counter_reg(15), O => \repeat_counter[12]_i_2_n_0\ ); \repeat_counter[12]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \repeat_counter[0]_i_10_n_0\, I1 => repeat_counter_reg(14), O => \repeat_counter[12]_i_3_n_0\ ); \repeat_counter[12]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \repeat_counter[0]_i_10_n_0\, I1 => repeat_counter_reg(13), O => \repeat_counter[12]_i_4_n_0\ ); \repeat_counter[12]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \repeat_counter[0]_i_10_n_0\, I1 => repeat_counter_reg(12), O => \repeat_counter[12]_i_5_n_0\ ); \repeat_counter[16]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \repeat_counter[0]_i_10_n_0\, I1 => repeat_counter_reg(19), O => \repeat_counter[16]_i_2_n_0\ ); \repeat_counter[16]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \repeat_counter[0]_i_10_n_0\, I1 => repeat_counter_reg(18), O => \repeat_counter[16]_i_3_n_0\ ); \repeat_counter[16]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \repeat_counter[0]_i_10_n_0\, I1 => repeat_counter_reg(17), O => \repeat_counter[16]_i_4_n_0\ ); \repeat_counter[16]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \repeat_counter[0]_i_10_n_0\, I1 => repeat_counter_reg(16), O => \repeat_counter[16]_i_5_n_0\ ); \repeat_counter[20]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \repeat_counter[0]_i_10_n_0\, I1 => repeat_counter_reg(20), O => \repeat_counter[20]_i_2_n_0\ ); \repeat_counter[4]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \repeat_counter[0]_i_10_n_0\, I1 => repeat_counter_reg(7), O => \repeat_counter[4]_i_2_n_0\ ); \repeat_counter[4]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \repeat_counter[0]_i_10_n_0\, I1 => repeat_counter_reg(6), O => \repeat_counter[4]_i_3_n_0\ ); \repeat_counter[4]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \repeat_counter[0]_i_10_n_0\, I1 => repeat_counter_reg(5), O => \repeat_counter[4]_i_4_n_0\ ); \repeat_counter[4]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \repeat_counter[0]_i_10_n_0\, I1 => repeat_counter_reg(4), O => \repeat_counter[4]_i_5_n_0\ ); \repeat_counter[8]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \repeat_counter[0]_i_10_n_0\, I1 => repeat_counter_reg(11), O => \repeat_counter[8]_i_2_n_0\ ); \repeat_counter[8]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \repeat_counter[0]_i_10_n_0\, I1 => repeat_counter_reg(10), O => \repeat_counter[8]_i_3_n_0\ ); \repeat_counter[8]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \repeat_counter[0]_i_10_n_0\, I1 => repeat_counter_reg(9), O => \repeat_counter[8]_i_4_n_0\ ); \repeat_counter[8]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \repeat_counter[0]_i_10_n_0\, I1 => repeat_counter_reg(8), O => \repeat_counter[8]_i_5_n_0\ ); \repeat_counter_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \repeat_counter[0]_i_1_n_0\, D => \repeat_counter_reg[0]_i_2_n_7\, Q => repeat_counter_reg(0), R => '0' ); \repeat_counter_reg[0]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \repeat_counter_reg[0]_i_2_n_0\, CO(2 downto 0) => \NLW_repeat_counter_reg[0]_i_2_CO_UNCONNECTED\(2 downto 0), CYINIT => '0', DI(3 downto 1) => B"000", DI(0) => \repeat_counter[0]_i_4_n_0\, O(3) => \repeat_counter_reg[0]_i_2_n_4\, O(2) => \repeat_counter_reg[0]_i_2_n_5\, O(1) => \repeat_counter_reg[0]_i_2_n_6\, O(0) => \repeat_counter_reg[0]_i_2_n_7\, S(3) => \repeat_counter[0]_i_5_n_0\, S(2) => \repeat_counter[0]_i_6_n_0\, S(1) => \repeat_counter[0]_i_7_n_0\, S(0) => \repeat_counter[0]_i_8_n_0\ ); \repeat_counter_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \repeat_counter[0]_i_1_n_0\, D => \repeat_counter_reg[8]_i_1_n_5\, Q => repeat_counter_reg(10), R => '0' ); \repeat_counter_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \repeat_counter[0]_i_1_n_0\, D => \repeat_counter_reg[8]_i_1_n_4\, Q => repeat_counter_reg(11), R => '0' ); \repeat_counter_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \repeat_counter[0]_i_1_n_0\, D => \repeat_counter_reg[12]_i_1_n_7\, Q => repeat_counter_reg(12), R => '0' ); \repeat_counter_reg[12]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \repeat_counter_reg[8]_i_1_n_0\, CO(3) => \repeat_counter_reg[12]_i_1_n_0\, CO(2 downto 0) => \NLW_repeat_counter_reg[12]_i_1_CO_UNCONNECTED\(2 downto 0), CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \repeat_counter_reg[12]_i_1_n_4\, O(2) => \repeat_counter_reg[12]_i_1_n_5\, O(1) => \repeat_counter_reg[12]_i_1_n_6\, O(0) => \repeat_counter_reg[12]_i_1_n_7\, S(3) => \repeat_counter[12]_i_2_n_0\, S(2) => \repeat_counter[12]_i_3_n_0\, S(1) => \repeat_counter[12]_i_4_n_0\, S(0) => \repeat_counter[12]_i_5_n_0\ ); \repeat_counter_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \repeat_counter[0]_i_1_n_0\, D => \repeat_counter_reg[12]_i_1_n_6\, Q => repeat_counter_reg(13), R => '0' ); \repeat_counter_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \repeat_counter[0]_i_1_n_0\, D => \repeat_counter_reg[12]_i_1_n_5\, Q => repeat_counter_reg(14), R => '0' ); \repeat_counter_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \repeat_counter[0]_i_1_n_0\, D => \repeat_counter_reg[12]_i_1_n_4\, Q => repeat_counter_reg(15), R => '0' ); \repeat_counter_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \repeat_counter[0]_i_1_n_0\, D => \repeat_counter_reg[16]_i_1_n_7\, Q => repeat_counter_reg(16), R => '0' ); \repeat_counter_reg[16]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \repeat_counter_reg[12]_i_1_n_0\, CO(3) => \repeat_counter_reg[16]_i_1_n_0\, CO(2 downto 0) => \NLW_repeat_counter_reg[16]_i_1_CO_UNCONNECTED\(2 downto 0), CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \repeat_counter_reg[16]_i_1_n_4\, O(2) => \repeat_counter_reg[16]_i_1_n_5\, O(1) => \repeat_counter_reg[16]_i_1_n_6\, O(0) => \repeat_counter_reg[16]_i_1_n_7\, S(3) => \repeat_counter[16]_i_2_n_0\, S(2) => \repeat_counter[16]_i_3_n_0\, S(1) => \repeat_counter[16]_i_4_n_0\, S(0) => \repeat_counter[16]_i_5_n_0\ ); \repeat_counter_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \repeat_counter[0]_i_1_n_0\, D => \repeat_counter_reg[16]_i_1_n_6\, Q => repeat_counter_reg(17), R => '0' ); \repeat_counter_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \repeat_counter[0]_i_1_n_0\, D => \repeat_counter_reg[16]_i_1_n_5\, Q => repeat_counter_reg(18), R => '0' ); \repeat_counter_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \repeat_counter[0]_i_1_n_0\, D => \repeat_counter_reg[16]_i_1_n_4\, Q => repeat_counter_reg(19), R => '0' ); \repeat_counter_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \repeat_counter[0]_i_1_n_0\, D => \repeat_counter_reg[0]_i_2_n_6\, Q => repeat_counter_reg(1), R => '0' ); \repeat_counter_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \repeat_counter[0]_i_1_n_0\, D => \repeat_counter_reg[20]_i_1_n_7\, Q => repeat_counter_reg(20), R => '0' ); \repeat_counter_reg[20]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \repeat_counter_reg[16]_i_1_n_0\, CO(3 downto 0) => \NLW_repeat_counter_reg[20]_i_1_CO_UNCONNECTED\(3 downto 0), CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 1) => \NLW_repeat_counter_reg[20]_i_1_O_UNCONNECTED\(3 downto 1), O(0) => \repeat_counter_reg[20]_i_1_n_7\, S(3 downto 1) => B"000", S(0) => \repeat_counter[20]_i_2_n_0\ ); \repeat_counter_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \repeat_counter[0]_i_1_n_0\, D => \repeat_counter_reg[0]_i_2_n_5\, Q => repeat_counter_reg(2), R => '0' ); \repeat_counter_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \repeat_counter[0]_i_1_n_0\, D => \repeat_counter_reg[0]_i_2_n_4\, Q => repeat_counter_reg(3), R => '0' ); \repeat_counter_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \repeat_counter[0]_i_1_n_0\, D => \repeat_counter_reg[4]_i_1_n_7\, Q => repeat_counter_reg(4), R => '0' ); \repeat_counter_reg[4]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \repeat_counter_reg[0]_i_2_n_0\, CO(3) => \repeat_counter_reg[4]_i_1_n_0\, CO(2 downto 0) => \NLW_repeat_counter_reg[4]_i_1_CO_UNCONNECTED\(2 downto 0), CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \repeat_counter_reg[4]_i_1_n_4\, O(2) => \repeat_counter_reg[4]_i_1_n_5\, O(1) => \repeat_counter_reg[4]_i_1_n_6\, O(0) => \repeat_counter_reg[4]_i_1_n_7\, S(3) => \repeat_counter[4]_i_2_n_0\, S(2) => \repeat_counter[4]_i_3_n_0\, S(1) => \repeat_counter[4]_i_4_n_0\, S(0) => \repeat_counter[4]_i_5_n_0\ ); \repeat_counter_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \repeat_counter[0]_i_1_n_0\, D => \repeat_counter_reg[4]_i_1_n_6\, Q => repeat_counter_reg(5), R => '0' ); \repeat_counter_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \repeat_counter[0]_i_1_n_0\, D => \repeat_counter_reg[4]_i_1_n_5\, Q => repeat_counter_reg(6), R => '0' ); \repeat_counter_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \repeat_counter[0]_i_1_n_0\, D => \repeat_counter_reg[4]_i_1_n_4\, Q => repeat_counter_reg(7), R => '0' ); \repeat_counter_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \repeat_counter[0]_i_1_n_0\, D => \repeat_counter_reg[8]_i_1_n_7\, Q => repeat_counter_reg(8), R => '0' ); \repeat_counter_reg[8]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \repeat_counter_reg[4]_i_1_n_0\, CO(3) => \repeat_counter_reg[8]_i_1_n_0\, CO(2 downto 0) => \NLW_repeat_counter_reg[8]_i_1_CO_UNCONNECTED\(2 downto 0), CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \repeat_counter_reg[8]_i_1_n_4\, O(2) => \repeat_counter_reg[8]_i_1_n_5\, O(1) => \repeat_counter_reg[8]_i_1_n_6\, O(0) => \repeat_counter_reg[8]_i_1_n_7\, S(3) => \repeat_counter[8]_i_2_n_0\, S(2) => \repeat_counter[8]_i_3_n_0\, S(1) => \repeat_counter[8]_i_4_n_0\, S(0) => \repeat_counter[8]_i_5_n_0\ ); \repeat_counter_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => \repeat_counter[0]_i_1_n_0\, D => \repeat_counter_reg[8]_i_1_n_6\, Q => repeat_counter_reg(9), R => '0' ); shift_l_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => '1', D => ps2_keyboard_0_n_2, Q => shift_l, R => '0' ); shift_r_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => '1', D => ps2_keyboard_0_n_3, Q => shift_r, R => '0' ); \state_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => '1', D => ps2_keyboard_0_n_10, Q => state(0), R => '0' ); \state_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => '1', D => ps2_keyboard_0_n_9, Q => state(1), R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity FrameBuffer_blk_mem_gen_generic_cstr is port ( doutb : out STD_LOGIC_VECTOR ( 7 downto 0 ); clka : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr"; end FrameBuffer_blk_mem_gen_generic_cstr; architecture STRUCTURE of FrameBuffer_blk_mem_gen_generic_cstr is signal ram_doutb : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \ramloop[1].ram.r_n_0\ : STD_LOGIC; signal \ramloop[1].ram.r_n_1\ : STD_LOGIC; signal \ramloop[1].ram.r_n_2\ : STD_LOGIC; signal \ramloop[1].ram.r_n_3\ : STD_LOGIC; signal \ramloop[1].ram.r_n_4\ : STD_LOGIC; signal \ramloop[1].ram.r_n_5\ : STD_LOGIC; signal \ramloop[1].ram.r_n_6\ : STD_LOGIC; signal \ramloop[1].ram.r_n_7\ : STD_LOGIC; signal \ramloop[2].ram.r_n_0\ : STD_LOGIC; signal \ramloop[2].ram.r_n_1\ : STD_LOGIC; signal \ramloop[2].ram.r_n_2\ : STD_LOGIC; signal \ramloop[2].ram.r_n_3\ : STD_LOGIC; signal \ramloop[2].ram.r_n_4\ : STD_LOGIC; signal \ramloop[2].ram.r_n_5\ : STD_LOGIC; signal \ramloop[2].ram.r_n_6\ : STD_LOGIC; signal \ramloop[2].ram.r_n_7\ : STD_LOGIC; begin \has_mux_b.B\: entity work.\FrameBuffer_blk_mem_gen_mux__parameterized0\ port map ( \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(7) => \ramloop[1].ram.r_n_0\, \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(6) => \ramloop[1].ram.r_n_1\, \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(5) => \ramloop[1].ram.r_n_2\, \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(4) => \ramloop[1].ram.r_n_3\, \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(3) => \ramloop[1].ram.r_n_4\, \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(2) => \ramloop[1].ram.r_n_5\, \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(1) => \ramloop[1].ram.r_n_6\, \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram\(0) => \ramloop[1].ram.r_n_7\, \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_0\(7 downto 0) => ram_doutb(7 downto 0), DOBDO(7) => \ramloop[2].ram.r_n_0\, DOBDO(6) => \ramloop[2].ram.r_n_1\, DOBDO(5) => \ramloop[2].ram.r_n_2\, DOBDO(4) => \ramloop[2].ram.r_n_3\, DOBDO(3) => \ramloop[2].ram.r_n_4\, DOBDO(2) => \ramloop[2].ram.r_n_5\, DOBDO(1) => \ramloop[2].ram.r_n_6\, DOBDO(0) => \ramloop[2].ram.r_n_7\, addrb(2 downto 0) => addrb(13 downto 11), clkb => clkb, doutb(7 downto 0) => doutb(7 downto 0) ); \ramloop[0].ram.r\: entity work.FrameBuffer_blk_mem_gen_prim_width port map ( addra(13 downto 0) => addra(13 downto 0), addrb(13 downto 0) => addrb(13 downto 0), clka => clka, clkb => clkb, dina(7 downto 0) => dina(7 downto 0), \doutb[7]\(7 downto 0) => ram_doutb(7 downto 0), wea(0) => wea(0) ); \ramloop[1].ram.r\: entity work.\FrameBuffer_blk_mem_gen_prim_width__parameterized0\ port map ( addra(13 downto 0) => addra(13 downto 0), addrb(13 downto 0) => addrb(13 downto 0), clka => clka, clkb => clkb, dina(7 downto 0) => dina(7 downto 0), \doutb[7]\(7) => \ramloop[1].ram.r_n_0\, \doutb[7]\(6) => \ramloop[1].ram.r_n_1\, \doutb[7]\(5) => \ramloop[1].ram.r_n_2\, \doutb[7]\(4) => \ramloop[1].ram.r_n_3\, \doutb[7]\(3) => \ramloop[1].ram.r_n_4\, \doutb[7]\(2) => \ramloop[1].ram.r_n_5\, \doutb[7]\(1) => \ramloop[1].ram.r_n_6\, \doutb[7]\(0) => \ramloop[1].ram.r_n_7\, wea(0) => wea(0) ); \ramloop[2].ram.r\: entity work.\FrameBuffer_blk_mem_gen_prim_width__parameterized1\ port map ( DOBDO(7) => \ramloop[2].ram.r_n_0\, DOBDO(6) => \ramloop[2].ram.r_n_1\, DOBDO(5) => \ramloop[2].ram.r_n_2\, DOBDO(4) => \ramloop[2].ram.r_n_3\, DOBDO(3) => \ramloop[2].ram.r_n_4\, DOBDO(2) => \ramloop[2].ram.r_n_5\, DOBDO(1) => \ramloop[2].ram.r_n_6\, DOBDO(0) => \ramloop[2].ram.r_n_7\, addra(13 downto 0) => addra(13 downto 0), addrb(13 downto 0) => addrb(13 downto 0), clka => clka, clkb => clkb, dina(7 downto 0) => dina(7 downto 0), wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity FrameBuffer_blk_mem_gen_top is port ( doutb : out STD_LOGIC_VECTOR ( 7 downto 0 ); clka : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_top : entity is "blk_mem_gen_top"; end FrameBuffer_blk_mem_gen_top; architecture STRUCTURE of FrameBuffer_blk_mem_gen_top is begin \valid.cstr\: entity work.FrameBuffer_blk_mem_gen_generic_cstr port map ( addra(13 downto 0) => addra(13 downto 0), addrb(13 downto 0) => addrb(13 downto 0), clka => clka, clkb => clkb, dina(7 downto 0) => dina(7 downto 0), doutb(7 downto 0) => doutb(7 downto 0), wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity FrameBuffer_blk_mem_gen_v8_3_1_synth is port ( doutb : out STD_LOGIC_VECTOR ( 7 downto 0 ); clka : in STD_LOGIC; clkb : in STD_LOGIC; addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); wea : in STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_v8_3_1_synth : entity is "blk_mem_gen_v8_3_1_synth"; end FrameBuffer_blk_mem_gen_v8_3_1_synth; architecture STRUCTURE of FrameBuffer_blk_mem_gen_v8_3_1_synth is begin \gnativebmg.native_blk_mem_gen\: entity work.FrameBuffer_blk_mem_gen_top port map ( addra(13 downto 0) => addra(13 downto 0), addrb(13 downto 0) => addrb(13 downto 0), clka => clka, clkb => clkb, dina(7 downto 0) => dina(7 downto 0), doutb(7 downto 0) => doutb(7 downto 0), wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity FrameBuffer_blk_mem_gen_v8_3_1 is port ( clka : in STD_LOGIC; rsta : in STD_LOGIC; ena : in STD_LOGIC; regcea : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); douta : out STD_LOGIC_VECTOR ( 7 downto 0 ); clkb : in STD_LOGIC; rstb : in STD_LOGIC; enb : in STD_LOGIC; regceb : in STD_LOGIC; web : in STD_LOGIC_VECTOR ( 0 to 0 ); addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); dinb : in STD_LOGIC_VECTOR ( 7 downto 0 ); doutb : out STD_LOGIC_VECTOR ( 7 downto 0 ); injectsbiterr : in STD_LOGIC; injectdbiterr : in STD_LOGIC; eccpipece : in STD_LOGIC; sbiterr : out STD_LOGIC; dbiterr : out STD_LOGIC; rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 ); sleep : in STD_LOGIC; deepsleep : in STD_LOGIC; shutdown : in STD_LOGIC; rsta_busy : out STD_LOGIC; rstb_busy : out STD_LOGIC; s_aclk : in STD_LOGIC; s_aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; s_axi_injectsbiterr : in STD_LOGIC; s_axi_injectdbiterr : in STD_LOGIC; s_axi_sbiterr : out STD_LOGIC; s_axi_dbiterr : out STD_LOGIC; s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 13 downto 0 ) ); attribute C_ADDRA_WIDTH : integer; attribute C_ADDRA_WIDTH of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 14; attribute C_ADDRB_WIDTH : integer; attribute C_ADDRB_WIDTH of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 14; attribute C_ALGORITHM : integer; attribute C_ALGORITHM of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 4; attribute C_AXI_SLAVE_TYPE : integer; attribute C_AXI_SLAVE_TYPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_AXI_TYPE : integer; attribute C_AXI_TYPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1; attribute C_BYTE_SIZE : integer; attribute C_BYTE_SIZE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 8; attribute C_COMMON_CLK : integer; attribute C_COMMON_CLK of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_COUNT_18K_BRAM : string; attribute C_COUNT_18K_BRAM of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "1"; attribute C_COUNT_36K_BRAM : string; attribute C_COUNT_36K_BRAM of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "2"; attribute C_CTRL_ECC_ALGO : string; attribute C_CTRL_ECC_ALGO of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "NONE"; attribute C_DEFAULT_DATA : string; attribute C_DEFAULT_DATA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "20"; attribute C_DISABLE_WARN_BHV_COLL : integer; attribute C_DISABLE_WARN_BHV_COLL of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_DISABLE_WARN_BHV_RANGE : integer; attribute C_DISABLE_WARN_BHV_RANGE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_ELABORATION_DIR : string; attribute C_ELABORATION_DIR of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "./"; attribute C_ENABLE_32BIT_ADDRESS : integer; attribute C_ENABLE_32BIT_ADDRESS of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_EN_DEEPSLEEP_PIN : integer; attribute C_EN_DEEPSLEEP_PIN of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_EN_ECC_PIPE : integer; attribute C_EN_ECC_PIPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_EN_RDADDRA_CHG : integer; attribute C_EN_RDADDRA_CHG of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_EN_RDADDRB_CHG : integer; attribute C_EN_RDADDRB_CHG of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_EN_SAFETY_CKT : integer; attribute C_EN_SAFETY_CKT of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_EN_SHUTDOWN_PIN : integer; attribute C_EN_SHUTDOWN_PIN of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_EN_SLEEP_PIN : integer; attribute C_EN_SLEEP_PIN of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_EST_POWER_SUMMARY : string; attribute C_EST_POWER_SUMMARY of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "Estimated Power for IP : 4.58651 mW"; attribute C_FAMILY : string; attribute C_FAMILY of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "artix7"; attribute C_HAS_AXI_ID : integer; attribute C_HAS_AXI_ID of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_ENA : integer; attribute C_HAS_ENA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_ENB : integer; attribute C_HAS_ENB of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_INJECTERR : integer; attribute C_HAS_INJECTERR of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_MEM_OUTPUT_REGS_A : integer; attribute C_HAS_MEM_OUTPUT_REGS_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_MEM_OUTPUT_REGS_B : integer; attribute C_HAS_MEM_OUTPUT_REGS_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_MUX_OUTPUT_REGS_A : integer; attribute C_HAS_MUX_OUTPUT_REGS_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_MUX_OUTPUT_REGS_B : integer; attribute C_HAS_MUX_OUTPUT_REGS_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_REGCEA : integer; attribute C_HAS_REGCEA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_REGCEB : integer; attribute C_HAS_REGCEB of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_RSTA : integer; attribute C_HAS_RSTA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_RSTB : integer; attribute C_HAS_RSTB of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; attribute C_HAS_SOFTECC_INPUT_REGS_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; attribute C_HAS_SOFTECC_OUTPUT_REGS_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_INITA_VAL : string; attribute C_INITA_VAL of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "0"; attribute C_INITB_VAL : string; attribute C_INITB_VAL of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "0"; attribute C_INIT_FILE : string; attribute C_INIT_FILE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "FrameBuffer.mem"; attribute C_INIT_FILE_NAME : string; attribute C_INIT_FILE_NAME of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "FrameBuffer.mif"; attribute C_INTERFACE_TYPE : integer; attribute C_INTERFACE_TYPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_LOAD_INIT_FILE : integer; attribute C_LOAD_INIT_FILE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1; attribute C_MEM_TYPE : integer; attribute C_MEM_TYPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1; attribute C_MUX_PIPELINE_STAGES : integer; attribute C_MUX_PIPELINE_STAGES of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_PRIM_TYPE : integer; attribute C_PRIM_TYPE of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1; attribute C_READ_DEPTH_A : integer; attribute C_READ_DEPTH_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 10240; attribute C_READ_DEPTH_B : integer; attribute C_READ_DEPTH_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 10240; attribute C_READ_WIDTH_A : integer; attribute C_READ_WIDTH_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 8; attribute C_READ_WIDTH_B : integer; attribute C_READ_WIDTH_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 8; attribute C_RSTRAM_A : integer; attribute C_RSTRAM_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_RSTRAM_B : integer; attribute C_RSTRAM_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_RST_PRIORITY_A : string; attribute C_RST_PRIORITY_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "CE"; attribute C_RST_PRIORITY_B : string; attribute C_RST_PRIORITY_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "CE"; attribute C_SIM_COLLISION_CHECK : string; attribute C_SIM_COLLISION_CHECK of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "ALL"; attribute C_USE_BRAM_BLOCK : integer; attribute C_USE_BRAM_BLOCK of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_USE_BYTE_WEA : integer; attribute C_USE_BYTE_WEA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1; attribute C_USE_BYTE_WEB : integer; attribute C_USE_BYTE_WEB of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1; attribute C_USE_DEFAULT_DATA : integer; attribute C_USE_DEFAULT_DATA of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1; attribute C_USE_ECC : integer; attribute C_USE_ECC of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_USE_SOFTECC : integer; attribute C_USE_SOFTECC of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_USE_URAM : integer; attribute C_USE_URAM of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 0; attribute C_WEA_WIDTH : integer; attribute C_WEA_WIDTH of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1; attribute C_WEB_WIDTH : integer; attribute C_WEB_WIDTH of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 1; attribute C_WRITE_DEPTH_A : integer; attribute C_WRITE_DEPTH_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 10240; attribute C_WRITE_DEPTH_B : integer; attribute C_WRITE_DEPTH_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 10240; attribute C_WRITE_MODE_A : string; attribute C_WRITE_MODE_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "READ_FIRST"; attribute C_WRITE_MODE_B : string; attribute C_WRITE_MODE_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "WRITE_FIRST"; attribute C_WRITE_WIDTH_A : integer; attribute C_WRITE_WIDTH_A of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 8; attribute C_WRITE_WIDTH_B : integer; attribute C_WRITE_WIDTH_B of FrameBuffer_blk_mem_gen_v8_3_1 : entity is 8; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "artix7"; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "blk_mem_gen_v8_3_1"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of FrameBuffer_blk_mem_gen_v8_3_1 : entity is "yes"; end FrameBuffer_blk_mem_gen_v8_3_1; architecture STRUCTURE of FrameBuffer_blk_mem_gen_v8_3_1 is begin dbiterr <= 'Z'; rsta_busy <= 'Z'; rstb_busy <= 'Z'; s_axi_arready <= 'Z'; s_axi_awready <= 'Z'; s_axi_bvalid <= 'Z'; s_axi_dbiterr <= 'Z'; s_axi_rlast <= 'Z'; s_axi_rvalid <= 'Z'; s_axi_sbiterr <= 'Z'; s_axi_wready <= 'Z'; sbiterr <= 'Z'; douta(0) <= 'Z'; douta(1) <= 'Z'; douta(2) <= 'Z'; douta(3) <= 'Z'; douta(4) <= 'Z'; douta(5) <= 'Z'; douta(6) <= 'Z'; douta(7) <= 'Z'; rdaddrecc(0) <= 'Z'; rdaddrecc(1) <= 'Z'; rdaddrecc(2) <= 'Z'; rdaddrecc(3) <= 'Z'; rdaddrecc(4) <= 'Z'; rdaddrecc(5) <= 'Z'; rdaddrecc(6) <= 'Z'; rdaddrecc(7) <= 'Z'; rdaddrecc(8) <= 'Z'; rdaddrecc(9) <= 'Z'; rdaddrecc(10) <= 'Z'; rdaddrecc(11) <= 'Z'; rdaddrecc(12) <= 'Z'; rdaddrecc(13) <= 'Z'; s_axi_bid(0) <= 'Z'; s_axi_bid(1) <= 'Z'; s_axi_bid(2) <= 'Z'; s_axi_bid(3) <= 'Z'; s_axi_bresp(0) <= 'Z'; s_axi_bresp(1) <= 'Z'; s_axi_rdaddrecc(0) <= 'Z'; s_axi_rdaddrecc(1) <= 'Z'; s_axi_rdaddrecc(2) <= 'Z'; s_axi_rdaddrecc(3) <= 'Z'; s_axi_rdaddrecc(4) <= 'Z'; s_axi_rdaddrecc(5) <= 'Z'; s_axi_rdaddrecc(6) <= 'Z'; s_axi_rdaddrecc(7) <= 'Z'; s_axi_rdaddrecc(8) <= 'Z'; s_axi_rdaddrecc(9) <= 'Z'; s_axi_rdaddrecc(10) <= 'Z'; s_axi_rdaddrecc(11) <= 'Z'; s_axi_rdaddrecc(12) <= 'Z'; s_axi_rdaddrecc(13) <= 'Z'; s_axi_rdata(0) <= 'Z'; s_axi_rdata(1) <= 'Z'; s_axi_rdata(2) <= 'Z'; s_axi_rdata(3) <= 'Z'; s_axi_rdata(4) <= 'Z'; s_axi_rdata(5) <= 'Z'; s_axi_rdata(6) <= 'Z'; s_axi_rdata(7) <= 'Z'; s_axi_rid(0) <= 'Z'; s_axi_rid(1) <= 'Z'; s_axi_rid(2) <= 'Z'; s_axi_rid(3) <= 'Z'; s_axi_rresp(0) <= 'Z'; s_axi_rresp(1) <= 'Z'; inst_blk_mem_gen: entity work.FrameBuffer_blk_mem_gen_v8_3_1_synth port map ( addra(13 downto 0) => addra(13 downto 0), addrb(13 downto 0) => addrb(13 downto 0), clka => clka, clkb => clkb, dina(7 downto 0) => dina(7 downto 0), doutb(7 downto 0) => doutb(7 downto 0), wea(0) => wea(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity FrameBuffer is port ( clka : in STD_LOGIC; wea : in STD_LOGIC_VECTOR ( 0 to 0 ); addra : in STD_LOGIC_VECTOR ( 13 downto 0 ); dina : in STD_LOGIC_VECTOR ( 7 downto 0 ); clkb : in STD_LOGIC; addrb : in STD_LOGIC_VECTOR ( 13 downto 0 ); doutb : out STD_LOGIC_VECTOR ( 7 downto 0 ) ); attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of FrameBuffer : entity is "FrameBuffer,blk_mem_gen_v8_3_1,{}"; attribute CORE_GENERATION_INFO : string; attribute CORE_GENERATION_INFO of FrameBuffer : entity is "FrameBuffer,blk_mem_gen_v8_3_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=8,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=FrameBuffer.mif,C_INIT_FILE=FrameBuffer.mem,C_USE_DEFAULT_DATA=1,C_DEFAULT_DATA=20,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=1,C_WEA_WIDTH=1,C_WRITE_MODE_A=READ_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=10240,C_READ_DEPTH_A=10240,C_ADDRA_WIDTH=14,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=1,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=10240,C_READ_DEPTH_B=10240,C_ADDRB_WIDTH=14,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=2,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 4.58651 mW}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of FrameBuffer : entity is "yes"; attribute x_core_info : string; attribute x_core_info of FrameBuffer : entity is "blk_mem_gen_v8_3_1,Vivado 2015.4"; end FrameBuffer; architecture STRUCTURE of FrameBuffer is signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_deepsleep_UNCONNECTED : STD_LOGIC; signal NLW_U0_eccpipece_UNCONNECTED : STD_LOGIC; signal NLW_U0_ena_UNCONNECTED : STD_LOGIC; signal NLW_U0_enb_UNCONNECTED : STD_LOGIC; signal NLW_U0_injectdbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_injectsbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_regcea_UNCONNECTED : STD_LOGIC; signal NLW_U0_regceb_UNCONNECTED : STD_LOGIC; signal NLW_U0_rsta_UNCONNECTED : STD_LOGIC; signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC; signal NLW_U0_rstb_UNCONNECTED : STD_LOGIC; signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_aclk_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_aresetn_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_arvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_awvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_bready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_injectdbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_injectsbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_rready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_wlast_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_wvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC; signal NLW_U0_shutdown_UNCONNECTED : STD_LOGIC; signal NLW_U0_sleep_UNCONNECTED : STD_LOGIC; signal NLW_U0_dinb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 ); signal NLW_U0_s_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_U0_s_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_U0_s_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_s_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_U0_s_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_U0_s_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_U0_s_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_U0_s_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_s_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_U0_s_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 ); signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_U0_s_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); signal NLW_U0_s_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_web_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); attribute C_ADDRA_WIDTH : integer; attribute C_ADDRA_WIDTH of U0 : label is 14; attribute C_ADDRB_WIDTH : integer; attribute C_ADDRB_WIDTH of U0 : label is 14; attribute C_ALGORITHM : integer; attribute C_ALGORITHM of U0 : label is 1; attribute C_AXI_ID_WIDTH : integer; attribute C_AXI_ID_WIDTH of U0 : label is 4; attribute C_AXI_SLAVE_TYPE : integer; attribute C_AXI_SLAVE_TYPE of U0 : label is 0; attribute C_AXI_TYPE : integer; attribute C_AXI_TYPE of U0 : label is 1; attribute C_BYTE_SIZE : integer; attribute C_BYTE_SIZE of U0 : label is 8; attribute C_COMMON_CLK : integer; attribute C_COMMON_CLK of U0 : label is 0; attribute C_COUNT_18K_BRAM : string; attribute C_COUNT_18K_BRAM of U0 : label is "1"; attribute C_COUNT_36K_BRAM : string; attribute C_COUNT_36K_BRAM of U0 : label is "2"; attribute C_CTRL_ECC_ALGO : string; attribute C_CTRL_ECC_ALGO of U0 : label is "NONE"; attribute C_DEFAULT_DATA : string; attribute C_DEFAULT_DATA of U0 : label is "20"; attribute C_DISABLE_WARN_BHV_COLL : integer; attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0; attribute C_DISABLE_WARN_BHV_RANGE : integer; attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0; attribute C_ELABORATION_DIR : string; attribute C_ELABORATION_DIR of U0 : label is "./"; attribute C_ENABLE_32BIT_ADDRESS : integer; attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0; attribute C_EN_DEEPSLEEP_PIN : integer; attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0; attribute C_EN_ECC_PIPE : integer; attribute C_EN_ECC_PIPE of U0 : label is 0; attribute C_EN_RDADDRA_CHG : integer; attribute C_EN_RDADDRA_CHG of U0 : label is 0; attribute C_EN_RDADDRB_CHG : integer; attribute C_EN_RDADDRB_CHG of U0 : label is 0; attribute C_EN_SAFETY_CKT : integer; attribute C_EN_SAFETY_CKT of U0 : label is 0; attribute C_EN_SHUTDOWN_PIN : integer; attribute C_EN_SHUTDOWN_PIN of U0 : label is 0; attribute C_EN_SLEEP_PIN : integer; attribute C_EN_SLEEP_PIN of U0 : label is 0; attribute C_EST_POWER_SUMMARY : string; attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 4.58651 mW"; attribute C_FAMILY : string; attribute C_FAMILY of U0 : label is "artix7"; attribute C_HAS_AXI_ID : integer; attribute C_HAS_AXI_ID of U0 : label is 0; attribute C_HAS_ENA : integer; attribute C_HAS_ENA of U0 : label is 0; attribute C_HAS_ENB : integer; attribute C_HAS_ENB of U0 : label is 0; attribute C_HAS_INJECTERR : integer; attribute C_HAS_INJECTERR of U0 : label is 0; attribute C_HAS_MEM_OUTPUT_REGS_A : integer; attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0; attribute C_HAS_MEM_OUTPUT_REGS_B : integer; attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0; attribute C_HAS_MUX_OUTPUT_REGS_A : integer; attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0; attribute C_HAS_MUX_OUTPUT_REGS_B : integer; attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0; attribute C_HAS_REGCEA : integer; attribute C_HAS_REGCEA of U0 : label is 0; attribute C_HAS_REGCEB : integer; attribute C_HAS_REGCEB of U0 : label is 0; attribute C_HAS_RSTA : integer; attribute C_HAS_RSTA of U0 : label is 0; attribute C_HAS_RSTB : integer; attribute C_HAS_RSTB of U0 : label is 0; attribute C_HAS_SOFTECC_INPUT_REGS_A : integer; attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0; attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer; attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0; attribute C_INITA_VAL : string; attribute C_INITA_VAL of U0 : label is "0"; attribute C_INITB_VAL : string; attribute C_INITB_VAL of U0 : label is "0"; attribute C_INIT_FILE : string; attribute C_INIT_FILE of U0 : label is "FrameBuffer.mem"; attribute C_INIT_FILE_NAME : string; attribute C_INIT_FILE_NAME of U0 : label is "FrameBuffer.mif"; attribute C_INTERFACE_TYPE : integer; attribute C_INTERFACE_TYPE of U0 : label is 0; attribute C_LOAD_INIT_FILE : integer; attribute C_LOAD_INIT_FILE of U0 : label is 1; attribute C_MEM_TYPE : integer; attribute C_MEM_TYPE of U0 : label is 1; attribute C_MUX_PIPELINE_STAGES : integer; attribute C_MUX_PIPELINE_STAGES of U0 : label is 0; attribute C_PRIM_TYPE : integer; attribute C_PRIM_TYPE of U0 : label is 1; attribute C_READ_DEPTH_A : integer; attribute C_READ_DEPTH_A of U0 : label is 10240; attribute C_READ_DEPTH_B : integer; attribute C_READ_DEPTH_B of U0 : label is 10240; attribute C_READ_WIDTH_A : integer; attribute C_READ_WIDTH_A of U0 : label is 8; attribute C_READ_WIDTH_B : integer; attribute C_READ_WIDTH_B of U0 : label is 8; attribute C_RSTRAM_A : integer; attribute C_RSTRAM_A of U0 : label is 0; attribute C_RSTRAM_B : integer; attribute C_RSTRAM_B of U0 : label is 0; attribute C_RST_PRIORITY_A : string; attribute C_RST_PRIORITY_A of U0 : label is "CE"; attribute C_RST_PRIORITY_B : string; attribute C_RST_PRIORITY_B of U0 : label is "CE"; attribute C_SIM_COLLISION_CHECK : string; attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL"; attribute C_USE_BRAM_BLOCK : integer; attribute C_USE_BRAM_BLOCK of U0 : label is 0; attribute C_USE_BYTE_WEA : integer; attribute C_USE_BYTE_WEA of U0 : label is 1; attribute C_USE_BYTE_WEB : integer; attribute C_USE_BYTE_WEB of U0 : label is 1; attribute C_USE_DEFAULT_DATA : integer; attribute C_USE_DEFAULT_DATA of U0 : label is 1; attribute C_USE_ECC : integer; attribute C_USE_ECC of U0 : label is 0; attribute C_USE_SOFTECC : integer; attribute C_USE_SOFTECC of U0 : label is 0; attribute C_USE_URAM : integer; attribute C_USE_URAM of U0 : label is 0; attribute C_WEA_WIDTH : integer; attribute C_WEA_WIDTH of U0 : label is 1; attribute C_WEB_WIDTH : integer; attribute C_WEB_WIDTH of U0 : label is 1; attribute C_WRITE_DEPTH_A : integer; attribute C_WRITE_DEPTH_A of U0 : label is 10240; attribute C_WRITE_DEPTH_B : integer; attribute C_WRITE_DEPTH_B of U0 : label is 10240; attribute C_WRITE_MODE_A : string; attribute C_WRITE_MODE_A of U0 : label is "READ_FIRST"; attribute C_WRITE_MODE_B : string; attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST"; attribute C_WRITE_WIDTH_A : integer; attribute C_WRITE_WIDTH_A of U0 : label is 8; attribute C_WRITE_WIDTH_B : integer; attribute C_WRITE_WIDTH_B of U0 : label is 8; attribute C_XDEVICEFAMILY : string; attribute C_XDEVICEFAMILY of U0 : label is "artix7"; attribute DONT_TOUCH : boolean; attribute DONT_TOUCH of U0 : label is std.standard.true; attribute downgradeipidentifiedwarnings of U0 : label is "yes"; begin U0: entity work.FrameBuffer_blk_mem_gen_v8_3_1 port map ( addra(13 downto 0) => addra(13 downto 0), addrb(13 downto 0) => addrb(13 downto 0), clka => clka, clkb => clkb, dbiterr => NLW_U0_dbiterr_UNCONNECTED, deepsleep => NLW_U0_deepsleep_UNCONNECTED, dina(7 downto 0) => dina(7 downto 0), dinb(7 downto 0) => NLW_U0_dinb_UNCONNECTED(7 downto 0), douta(7 downto 0) => NLW_U0_douta_UNCONNECTED(7 downto 0), doutb(7 downto 0) => doutb(7 downto 0), eccpipece => NLW_U0_eccpipece_UNCONNECTED, ena => NLW_U0_ena_UNCONNECTED, enb => NLW_U0_enb_UNCONNECTED, injectdbiterr => NLW_U0_injectdbiterr_UNCONNECTED, injectsbiterr => NLW_U0_injectsbiterr_UNCONNECTED, rdaddrecc(13 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(13 downto 0), regcea => NLW_U0_regcea_UNCONNECTED, regceb => NLW_U0_regceb_UNCONNECTED, rsta => NLW_U0_rsta_UNCONNECTED, rsta_busy => NLW_U0_rsta_busy_UNCONNECTED, rstb => NLW_U0_rstb_UNCONNECTED, rstb_busy => NLW_U0_rstb_busy_UNCONNECTED, s_aclk => NLW_U0_s_aclk_UNCONNECTED, s_aresetn => NLW_U0_s_aresetn_UNCONNECTED, s_axi_araddr(31 downto 0) => NLW_U0_s_axi_araddr_UNCONNECTED(31 downto 0), s_axi_arburst(1 downto 0) => NLW_U0_s_axi_arburst_UNCONNECTED(1 downto 0), s_axi_arid(3 downto 0) => NLW_U0_s_axi_arid_UNCONNECTED(3 downto 0), s_axi_arlen(7 downto 0) => NLW_U0_s_axi_arlen_UNCONNECTED(7 downto 0), s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED, s_axi_arsize(2 downto 0) => NLW_U0_s_axi_arsize_UNCONNECTED(2 downto 0), s_axi_arvalid => NLW_U0_s_axi_arvalid_UNCONNECTED, s_axi_awaddr(31 downto 0) => NLW_U0_s_axi_awaddr_UNCONNECTED(31 downto 0), s_axi_awburst(1 downto 0) => NLW_U0_s_axi_awburst_UNCONNECTED(1 downto 0), s_axi_awid(3 downto 0) => NLW_U0_s_axi_awid_UNCONNECTED(3 downto 0), s_axi_awlen(7 downto 0) => NLW_U0_s_axi_awlen_UNCONNECTED(7 downto 0), s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED, s_axi_awsize(2 downto 0) => NLW_U0_s_axi_awsize_UNCONNECTED(2 downto 0), s_axi_awvalid => NLW_U0_s_axi_awvalid_UNCONNECTED, s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0), s_axi_bready => NLW_U0_s_axi_bready_UNCONNECTED, s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0), s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED, s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED, s_axi_injectdbiterr => NLW_U0_s_axi_injectdbiterr_UNCONNECTED, s_axi_injectsbiterr => NLW_U0_s_axi_injectsbiterr_UNCONNECTED, s_axi_rdaddrecc(13 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(13 downto 0), s_axi_rdata(7 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(7 downto 0), s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0), s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED, s_axi_rready => NLW_U0_s_axi_rready_UNCONNECTED, s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0), s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED, s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED, s_axi_wdata(7 downto 0) => NLW_U0_s_axi_wdata_UNCONNECTED(7 downto 0), s_axi_wlast => NLW_U0_s_axi_wlast_UNCONNECTED, s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED, s_axi_wstrb(0) => NLW_U0_s_axi_wstrb_UNCONNECTED(0), s_axi_wvalid => NLW_U0_s_axi_wvalid_UNCONNECTED, sbiterr => NLW_U0_sbiterr_UNCONNECTED, shutdown => NLW_U0_shutdown_UNCONNECTED, sleep => NLW_U0_sleep_UNCONNECTED, wea(0) => wea(0), web(0) => NLW_U0_web_UNCONNECTED(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity top is port ( vgaRed : out STD_LOGIC_VECTOR ( 3 downto 0 ); vgaGreen : out STD_LOGIC_VECTOR ( 3 downto 0 ); vgaBlue : out STD_LOGIC_VECTOR ( 3 downto 0 ); Hsync : out STD_LOGIC; Vsync : out STD_LOGIC; led : out STD_LOGIC_VECTOR ( 15 downto 0 ); sw : in STD_LOGIC_VECTOR ( 15 downto 0 ); clk : in STD_LOGIC; btnC : in STD_LOGIC; btnU : in STD_LOGIC; btnL : in STD_LOGIC; btnR : in STD_LOGIC; btnD : in STD_LOGIC; PS2Clk : in STD_LOGIC; PS2Data : in STD_LOGIC; RsRx : inout STD_LOGIC; RsTx : inout STD_LOGIC ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of top : entity is true; attribute ECO_CHECKSUM : string; attribute ECO_CHECKSUM of top : entity is "d678d57b"; attribute POWER_OPT_BRAM_CDC : integer; attribute POWER_OPT_BRAM_CDC of top : entity is 0; attribute POWER_OPT_BRAM_SR_ADDR : integer; attribute POWER_OPT_BRAM_SR_ADDR of top : entity is 0; attribute POWER_OPT_LOOPED_NET_PERCENTAGE : integer; attribute POWER_OPT_LOOPED_NET_PERCENTAGE of top : entity is 0; end top; architecture STRUCTURE of top is signal Hsync_OBUF : STD_LOGIC; signal PS2Clk_IBUF : STD_LOGIC; signal PS2Data_IBUF : STD_LOGIC; signal Vsync_OBUF : STD_LOGIC; signal addra : STD_LOGIC_VECTOR ( 13 downto 0 ); signal btnC_IBUF : STD_LOGIC; signal btnD_IBUF : STD_LOGIC; signal btnL_IBUF : STD_LOGIC; signal btnR_IBUF : STD_LOGIC; signal btnU_IBUF : STD_LOGIC; signal clk108M : STD_LOGIC; signal clk10M : STD_LOGIC; signal clk_1_i_1_n_0 : STD_LOGIC; signal clk_1_i_2_n_0 : STD_LOGIC; signal clk_1_i_3_n_0 : STD_LOGIC; signal clk_1_i_4_n_0 : STD_LOGIC; signal clk_1_i_5_n_0 : STD_LOGIC; signal clk_1_reg_n_0 : STD_LOGIC; signal clk_BUFG : STD_LOGIC; signal clk_IBUF : STD_LOGIC; signal \counter[0]__0_i_1_n_0\ : STD_LOGIC; signal \counter[0]_i_1_n_0\ : STD_LOGIC; signal \counter[10]_i_1_n_0\ : STD_LOGIC; signal \counter[13]_i_2_n_0\ : STD_LOGIC; signal \counter[13]_i_3_n_0\ : STD_LOGIC; signal \counter[13]_i_4_n_0\ : STD_LOGIC; signal \counter[13]_i_6_n_0\ : STD_LOGIC; signal \counter[13]_i_7_n_0\ : STD_LOGIC; signal \counter[1]_i_1_n_0\ : STD_LOGIC; signal \counter[22]_i_10_n_0\ : STD_LOGIC; signal \counter[22]_i_11_n_0\ : STD_LOGIC; signal \counter[22]_i_12_n_0\ : STD_LOGIC; signal \counter[22]_i_13_n_0\ : STD_LOGIC; signal \counter[22]_i_14_n_0\ : STD_LOGIC; signal \counter[22]_i_15_n_0\ : STD_LOGIC; signal \counter[22]_i_16_n_0\ : STD_LOGIC; signal \counter[22]_i_17_n_0\ : STD_LOGIC; signal \counter[22]_i_18_n_0\ : STD_LOGIC; signal \counter[22]_i_19_n_0\ : STD_LOGIC; signal \counter[22]_i_1_n_0\ : STD_LOGIC; signal \counter[22]_i_20_n_0\ : STD_LOGIC; signal \counter[22]_i_21_n_0\ : STD_LOGIC; signal \counter[22]_i_22_n_0\ : STD_LOGIC; signal \counter[22]_i_7_n_0\ : STD_LOGIC; signal \counter[2]_i_1_n_0\ : STD_LOGIC; signal \counter[4]_i_1_n_0\ : STD_LOGIC; signal \counter[5]_i_1_n_0\ : STD_LOGIC; signal \counter[6]_i_1_n_0\ : STD_LOGIC; signal \counter[7]_i_1_n_0\ : STD_LOGIC; signal \counter[8]_i_1_n_0\ : STD_LOGIC; signal \counter[9]_i_1_n_0\ : STD_LOGIC; signal \counter_reg[0]__0_n_0\ : STD_LOGIC; signal \counter_reg[10]__0_n_0\ : STD_LOGIC; signal \counter_reg[11]__0_n_0\ : STD_LOGIC; signal \counter_reg[12]__0_i_1_n_0\ : STD_LOGIC; signal \counter_reg[12]__0_i_1_n_4\ : STD_LOGIC; signal \counter_reg[12]__0_i_1_n_5\ : STD_LOGIC; signal \counter_reg[12]__0_i_1_n_6\ : STD_LOGIC; signal \counter_reg[12]__0_i_1_n_7\ : STD_LOGIC; signal \counter_reg[12]__0_n_0\ : STD_LOGIC; signal \counter_reg[12]_i_2_n_0\ : STD_LOGIC; signal \counter_reg[12]_i_2_n_4\ : STD_LOGIC; signal \counter_reg[12]_i_2_n_5\ : STD_LOGIC; signal \counter_reg[12]_i_2_n_6\ : STD_LOGIC; signal \counter_reg[12]_i_2_n_7\ : STD_LOGIC; signal \counter_reg[13]__0_n_0\ : STD_LOGIC; signal \counter_reg[13]_i_5_n_7\ : STD_LOGIC; signal \counter_reg[16]_i_1_n_0\ : STD_LOGIC; signal \counter_reg[16]_i_1_n_4\ : STD_LOGIC; signal \counter_reg[16]_i_1_n_5\ : STD_LOGIC; signal \counter_reg[16]_i_1_n_6\ : STD_LOGIC; signal \counter_reg[16]_i_1_n_7\ : STD_LOGIC; signal \counter_reg[1]__0_n_0\ : STD_LOGIC; signal \counter_reg[20]_i_1_n_0\ : STD_LOGIC; signal \counter_reg[20]_i_1_n_4\ : STD_LOGIC; signal \counter_reg[20]_i_1_n_5\ : STD_LOGIC; signal \counter_reg[20]_i_1_n_6\ : STD_LOGIC; signal \counter_reg[20]_i_1_n_7\ : STD_LOGIC; signal \counter_reg[22]_i_2_n_6\ : STD_LOGIC; signal \counter_reg[22]_i_2_n_7\ : STD_LOGIC; signal \counter_reg[22]_i_3_n_3\ : STD_LOGIC; signal \counter_reg[22]_i_6_n_0\ : STD_LOGIC; signal \counter_reg[22]_i_9_n_0\ : STD_LOGIC; signal \counter_reg[2]__0_n_0\ : STD_LOGIC; signal \counter_reg[3]__0_n_0\ : STD_LOGIC; signal \counter_reg[3]_i_1_n_0\ : STD_LOGIC; signal \counter_reg[3]_i_1_n_4\ : STD_LOGIC; signal \counter_reg[3]_i_1_n_5\ : STD_LOGIC; signal \counter_reg[3]_i_1_n_6\ : STD_LOGIC; signal \counter_reg[3]_i_1_n_7\ : STD_LOGIC; signal \counter_reg[4]__0_i_1_n_0\ : STD_LOGIC; signal \counter_reg[4]__0_i_1_n_4\ : STD_LOGIC; signal \counter_reg[4]__0_i_1_n_5\ : STD_LOGIC; signal \counter_reg[4]__0_i_1_n_6\ : STD_LOGIC; signal \counter_reg[4]__0_i_1_n_7\ : STD_LOGIC; signal \counter_reg[4]__0_n_0\ : STD_LOGIC; signal \counter_reg[5]__0_n_0\ : STD_LOGIC; signal \counter_reg[6]__0_n_0\ : STD_LOGIC; signal \counter_reg[7]__0_n_0\ : STD_LOGIC; signal \counter_reg[8]__0_i_1_n_0\ : STD_LOGIC; signal \counter_reg[8]__0_i_1_n_4\ : STD_LOGIC; signal \counter_reg[8]__0_i_1_n_5\ : STD_LOGIC; signal \counter_reg[8]__0_i_1_n_6\ : STD_LOGIC; signal \counter_reg[8]__0_i_1_n_7\ : STD_LOGIC; signal \counter_reg[8]__0_n_0\ : STD_LOGIC; signal \counter_reg[8]_i_2_n_0\ : STD_LOGIC; signal \counter_reg[8]_i_2_n_4\ : STD_LOGIC; signal \counter_reg[8]_i_2_n_5\ : STD_LOGIC; signal \counter_reg[8]_i_2_n_6\ : STD_LOGIC; signal \counter_reg[8]_i_2_n_7\ : STD_LOGIC; signal \counter_reg[9]__0_n_0\ : STD_LOGIC; signal \counter_reg_n_0_[0]\ : STD_LOGIC; signal \counter_reg_n_0_[10]\ : STD_LOGIC; signal \counter_reg_n_0_[11]\ : STD_LOGIC; signal \counter_reg_n_0_[12]\ : STD_LOGIC; signal \counter_reg_n_0_[13]\ : STD_LOGIC; signal \counter_reg_n_0_[14]\ : STD_LOGIC; signal \counter_reg_n_0_[15]\ : STD_LOGIC; signal \counter_reg_n_0_[16]\ : STD_LOGIC; signal \counter_reg_n_0_[17]\ : STD_LOGIC; signal \counter_reg_n_0_[18]\ : STD_LOGIC; signal \counter_reg_n_0_[19]\ : STD_LOGIC; signal \counter_reg_n_0_[1]\ : STD_LOGIC; signal \counter_reg_n_0_[20]\ : STD_LOGIC; signal \counter_reg_n_0_[21]\ : STD_LOGIC; signal \counter_reg_n_0_[22]\ : STD_LOGIC; signal \counter_reg_n_0_[2]\ : STD_LOGIC; signal \counter_reg_n_0_[3]\ : STD_LOGIC; signal \counter_reg_n_0_[4]\ : STD_LOGIC; signal \counter_reg_n_0_[5]\ : STD_LOGIC; signal \counter_reg_n_0_[6]\ : STD_LOGIC; signal \counter_reg_n_0_[7]\ : STD_LOGIC; signal \counter_reg_n_0_[8]\ : STD_LOGIC; signal \counter_reg_n_0_[9]\ : STD_LOGIC; signal current_s : STD_LOGIC_VECTOR ( 1 downto 0 ); signal dina : STD_LOGIC_VECTOR ( 7 downto 0 ); signal doutb : STD_LOGIC_VECTOR ( 7 downto 0 ); signal fbOutAddr : STD_LOGIC_VECTOR ( 13 downto 0 ); signal fb_in_addr0 : STD_LOGIC_VECTOR ( 13 downto 0 ); signal \fb_in_addr[0]_i_1_n_0\ : STD_LOGIC; signal \fb_in_addr[10]_i_1_n_0\ : STD_LOGIC; signal \fb_in_addr[11]_i_1_n_0\ : STD_LOGIC; signal \fb_in_addr[11]_i_3_n_0\ : STD_LOGIC; signal \fb_in_addr[11]_i_4_n_0\ : STD_LOGIC; signal \fb_in_addr[11]_i_5_n_0\ : STD_LOGIC; signal \fb_in_addr[11]_i_6_n_0\ : STD_LOGIC; signal \fb_in_addr[11]_i_7_n_0\ : STD_LOGIC; signal \fb_in_addr[11]_i_8_n_0\ : STD_LOGIC; signal \fb_in_addr[11]_i_9_n_0\ : STD_LOGIC; signal \fb_in_addr[12]_i_1_n_0\ : STD_LOGIC; signal \fb_in_addr[13]_i_1_n_0\ : STD_LOGIC; signal \fb_in_addr[13]_i_3_n_0\ : STD_LOGIC; signal \fb_in_addr[13]_i_4_n_0\ : STD_LOGIC; signal \fb_in_addr[1]_i_1_n_0\ : STD_LOGIC; signal \fb_in_addr[2]_i_1_n_0\ : STD_LOGIC; signal \fb_in_addr[3]_i_1_n_0\ : STD_LOGIC; signal \fb_in_addr[3]_i_3_n_0\ : STD_LOGIC; signal \fb_in_addr[3]_i_4_n_0\ : STD_LOGIC; signal \fb_in_addr[3]_i_5_n_0\ : STD_LOGIC; signal \fb_in_addr[3]_i_6_n_0\ : STD_LOGIC; signal \fb_in_addr[3]_i_7_n_0\ : STD_LOGIC; signal \fb_in_addr[4]_i_1_n_0\ : STD_LOGIC; signal \fb_in_addr[5]_i_1_n_0\ : STD_LOGIC; signal \fb_in_addr[6]_i_1_n_0\ : STD_LOGIC; signal \fb_in_addr[7]_i_1_n_0\ : STD_LOGIC; signal \fb_in_addr[7]_i_3_n_0\ : STD_LOGIC; signal \fb_in_addr[7]_i_4_n_0\ : STD_LOGIC; signal \fb_in_addr[7]_i_5_n_0\ : STD_LOGIC; signal \fb_in_addr[7]_i_6_n_0\ : STD_LOGIC; signal \fb_in_addr[7]_i_7_n_0\ : STD_LOGIC; signal \fb_in_addr[7]_i_8_n_0\ : STD_LOGIC; signal \fb_in_addr[8]_i_1_n_0\ : STD_LOGIC; signal \fb_in_addr[9]_i_1_n_0\ : STD_LOGIC; signal \fb_in_addr_reg[11]_i_2_n_0\ : STD_LOGIC; signal \fb_in_addr_reg[3]_i_2_n_0\ : STD_LOGIC; signal \fb_in_addr_reg[7]_i_2_n_0\ : STD_LOGIC; signal fb_in_dat : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \g0_b0__0_n_0\ : STD_LOGIC; signal \g0_b1__0_n_0\ : STD_LOGIC; signal \g0_b2__0_n_0\ : STD_LOGIC; signal \g0_b3__0_n_0\ : STD_LOGIC; signal \g0_b4__0_n_0\ : STD_LOGIC; signal \g0_b5__0_n_0\ : STD_LOGIC; signal \g0_b6__0_i_1_n_0\ : STD_LOGIC; signal \g0_b6__0_i_2_n_0\ : STD_LOGIC; signal \g0_b6__0_i_3_n_0\ : STD_LOGIC; signal \g0_b6__0_i_4_n_0\ : STD_LOGIC; signal \g0_b6__0_i_5_n_0\ : STD_LOGIC; signal \g0_b6__0_i_6_n_0\ : STD_LOGIC; signal \g0_b6__0_i_7_n_0\ : STD_LOGIC; signal \g0_b6__0_n_0\ : STD_LOGIC; signal keyboard0_n_0 : STD_LOGIC; signal keyboard0_n_1 : STD_LOGIC; signal keyboard0_n_10 : STD_LOGIC; signal keyboard0_n_2 : STD_LOGIC; signal next_s : STD_LOGIC_VECTOR ( 1 downto 0 ); signal \next_s[1]_i_2_n_0\ : STD_LOGIC; signal \sw[0]\ : STD_LOGIC; signal \sw[0]_IBUF\ : STD_LOGIC; signal \sw[10]\ : STD_LOGIC; signal \sw[10]_IBUF\ : STD_LOGIC; signal \sw[11]\ : STD_LOGIC; signal \sw[11]_IBUF\ : STD_LOGIC; signal \sw[12]\ : STD_LOGIC; signal \sw[12]_IBUF\ : STD_LOGIC; signal \sw[13]\ : STD_LOGIC; signal \sw[13]_IBUF\ : STD_LOGIC; signal \sw[14]\ : STD_LOGIC; signal \sw[14]_IBUF\ : STD_LOGIC; signal \sw[15]\ : STD_LOGIC; signal \sw[15]_IBUF\ : STD_LOGIC; signal \sw[1]\ : STD_LOGIC; signal \sw[1]_IBUF\ : STD_LOGIC; signal \sw[2]\ : STD_LOGIC; signal \sw[2]_IBUF\ : STD_LOGIC; signal \sw[3]\ : STD_LOGIC; signal \sw[3]_IBUF\ : STD_LOGIC; signal \sw[4]\ : STD_LOGIC; signal \sw[4]_IBUF\ : STD_LOGIC; signal \sw[5]\ : STD_LOGIC; signal \sw[5]_IBUF\ : STD_LOGIC; signal \sw[6]\ : STD_LOGIC; signal \sw[6]_IBUF\ : STD_LOGIC; signal \sw[7]\ : STD_LOGIC; signal \sw[7]_IBUF\ : STD_LOGIC; signal \sw[8]\ : STD_LOGIC; signal \sw[8]_IBUF\ : STD_LOGIC; signal \sw[9]\ : STD_LOGIC; signal \sw[9]_IBUF\ : STD_LOGIC; signal vgaBlue_OBUF : STD_LOGIC_VECTOR ( 0 to 0 ); signal \PS2Clk^Mid\ : STD_LOGIC; signal \PS2Data^Mid\ : STD_LOGIC; signal \NLW_counter_reg[12]__0_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_counter_reg[12]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_counter_reg[13]_i_5_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_counter_reg[13]_i_5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_counter_reg[16]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_counter_reg[20]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_counter_reg[22]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_counter_reg[22]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_counter_reg[22]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 ); signal \NLW_counter_reg[22]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_counter_reg[22]_i_6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_counter_reg[22]_i_6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_counter_reg[22]_i_9_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_counter_reg[22]_i_9_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_counter_reg[3]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_counter_reg[4]__0_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_counter_reg[8]__0_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_counter_reg[8]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_fb_in_addr_reg[11]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_fb_in_addr_reg[13]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \NLW_fb_in_addr_reg[13]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 ); signal \NLW_fb_in_addr_reg[3]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \NLW_fb_in_addr_reg[7]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 ); attribute OPT_INSERTED : boolean; attribute OPT_INSERTED of btnC_IBUF_inst : label is std.standard.true; attribute OPT_INSERTED of btnD_IBUF_inst : label is std.standard.true; attribute OPT_INSERTED of btnL_IBUF_inst : label is std.standard.true; attribute OPT_INSERTED of btnR_IBUF_inst : label is std.standard.true; attribute OPT_INSERTED of btnU_IBUF_inst : label is std.standard.true; attribute OPT_INSERTED of clk_IBUF_inst : label is std.standard.true; attribute syn_black_box : string; attribute syn_black_box of clock0 : label is "TRUE"; attribute syn_black_box of frameBuffer0 : label is "TRUE"; attribute x_core_info : string; attribute x_core_info of frameBuffer0 : label is "blk_mem_gen_v8_3_1,Vivado 2015.4"; attribute OPT_INSERTED of \sw[0]_IBUF_inst\ : label is std.standard.true; attribute OPT_INSERTED of \sw[10]_IBUF_inst\ : label is std.standard.true; attribute OPT_INSERTED of \sw[11]_IBUF_inst\ : label is std.standard.true; attribute OPT_INSERTED of \sw[12]_IBUF_inst\ : label is std.standard.true; attribute OPT_INSERTED of \sw[13]_IBUF_inst\ : label is std.standard.true; attribute OPT_INSERTED of \sw[14]_IBUF_inst\ : label is std.standard.true; attribute OPT_INSERTED of \sw[15]_IBUF_inst\ : label is std.standard.true; attribute OPT_INSERTED of \sw[1]_IBUF_inst\ : label is std.standard.true; attribute OPT_INSERTED of \sw[2]_IBUF_inst\ : label is std.standard.true; attribute OPT_INSERTED of \sw[3]_IBUF_inst\ : label is std.standard.true; attribute OPT_INSERTED of \sw[4]_IBUF_inst\ : label is std.standard.true; attribute OPT_INSERTED of \sw[5]_IBUF_inst\ : label is std.standard.true; attribute OPT_INSERTED of \sw[6]_IBUF_inst\ : label is std.standard.true; attribute OPT_INSERTED of \sw[7]_IBUF_inst\ : label is std.standard.true; attribute OPT_INSERTED of \sw[8]_IBUF_inst\ : label is std.standard.true; attribute OPT_INSERTED of \sw[9]_IBUF_inst\ : label is std.standard.true; begin \PS2Clk^Mid\ <= PS2Clk; \PS2Data^Mid\ <= PS2Data; \sw[0]\ <= sw(0); \sw[10]\ <= sw(10); \sw[11]\ <= sw(11); \sw[12]\ <= sw(12); \sw[13]\ <= sw(13); \sw[14]\ <= sw(14); \sw[15]\ <= sw(15); \sw[1]\ <= sw(1); \sw[2]\ <= sw(2); \sw[3]\ <= sw(3); \sw[4]\ <= sw(4); \sw[5]\ <= sw(5); \sw[6]\ <= sw(6); \sw[7]\ <= sw(7); \sw[8]\ <= sw(8); \sw[9]\ <= sw(9); \pullup_PS2Clk^Midinst\: unisim.vcomponents.PULLUP port map ( O => \PS2Clk^Mid\ ); \pullup_PS2Data^Midinst\: unisim.vcomponents.PULLUP port map ( O => \PS2Data^Mid\ ); led(0) <= 'Z'; led(1) <= 'Z'; led(2) <= 'Z'; led(3) <= 'Z'; led(4) <= 'Z'; led(5) <= 'Z'; led(6) <= 'Z'; led(7) <= 'Z'; led(8) <= 'Z'; led(9) <= 'Z'; led(10) <= 'Z'; led(11) <= 'Z'; led(12) <= 'Z'; led(13) <= 'Z'; led(14) <= 'Z'; led(15) <= 'Z'; Hsync_OBUF_inst: unisim.vcomponents.OBUF port map ( I => Hsync_OBUF, O => Hsync ); PS2Clk_IBUF_inst: unisim.vcomponents.IBUF port map ( I => \PS2Clk^Mid\, O => PS2Clk_IBUF ); PS2Data_IBUF_inst: unisim.vcomponents.IBUF port map ( I => \PS2Data^Mid\, O => PS2Data_IBUF ); Vsync_OBUF_inst: unisim.vcomponents.OBUF port map ( I => Vsync_OBUF, O => Vsync ); btnC_IBUF_inst: unisim.vcomponents.IBUF port map ( I => btnC, O => btnC_IBUF ); btnD_IBUF_inst: unisim.vcomponents.IBUF port map ( I => btnD, O => btnD_IBUF ); btnL_IBUF_inst: unisim.vcomponents.IBUF port map ( I => btnL, O => btnL_IBUF ); btnR_IBUF_inst: unisim.vcomponents.IBUF port map ( I => btnR, O => btnR_IBUF ); btnU_IBUF_inst: unisim.vcomponents.IBUF port map ( I => btnU, O => btnU_IBUF ); clk_1_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"2AAAAAAAD5555555" ) port map ( I0 => \counter_reg[22]_i_3_n_3\, I1 => clk_1_i_2_n_0, I2 => clk_1_i_3_n_0, I3 => clk_1_i_4_n_0, I4 => clk_1_i_5_n_0, I5 => clk_1_reg_n_0, O => clk_1_i_1_n_0 ); clk_1_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000001" ) port map ( I0 => \counter_reg[16]_i_1_n_6\, I1 => \counter_reg[16]_i_1_n_5\, I2 => \counter_reg[12]__0_i_1_n_4\, I3 => \counter_reg[16]_i_1_n_7\, I4 => \counter_reg[20]_i_1_n_7\, I5 => \counter_reg[16]_i_1_n_4\, O => clk_1_i_2_n_0 ); clk_1_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"0000000100000000" ) port map ( I0 => \counter_reg[20]_i_1_n_4\, I1 => \counter_reg[22]_i_2_n_7\, I2 => \counter_reg[20]_i_1_n_6\, I3 => \counter_reg[20]_i_1_n_5\, I4 => \counter_reg[22]_i_2_n_6\, I5 => \counter_reg[0]__0_n_0\, O => clk_1_i_3_n_0 ); clk_1_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000001" ) port map ( I0 => \counter_reg[8]__0_i_1_n_4\, I1 => \counter_reg[12]__0_i_1_n_7\, I2 => \counter_reg[8]__0_i_1_n_6\, I3 => \counter_reg[8]__0_i_1_n_5\, I4 => \counter_reg[12]__0_i_1_n_5\, I5 => \counter_reg[12]__0_i_1_n_6\, O => clk_1_i_4_n_0 ); clk_1_i_5: unisim.vcomponents.LUT5 generic map( INIT => X"00000001" ) port map ( I0 => \counter_reg[4]__0_i_1_n_7\, I1 => \counter_reg[4]__0_i_1_n_6\, I2 => \counter_reg[4]__0_i_1_n_5\, I3 => \counter_reg[8]__0_i_1_n_7\, I4 => \counter_reg[4]__0_i_1_n_4\, O => clk_1_i_5_n_0 ); clk_1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => clk_1_i_1_n_0, Q => clk_1_reg_n_0, R => '0' ); clk_BUFG_inst: unisim.vcomponents.BUFG port map ( I => clk_IBUF, O => clk_BUFG ); clk_IBUF_inst: unisim.vcomponents.IBUF port map ( I => clk, O => clk_IBUF ); clock0: entity work.ClockDivider port map ( clk108M => clk108M, clk10M => clk10M, clkIn => clk_BUFG ); \counter[0]__0_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \counter_reg[0]__0_n_0\, O => \counter[0]__0_i_1_n_0\ ); \counter[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \counter_reg_n_0_[0]\, O => \counter[0]_i_1_n_0\ ); \counter[10]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFF01FF0FFF01" ) port map ( I0 => \counter[13]_i_3_n_0\, I1 => current_s(1), I2 => \counter[13]_i_4_n_0\, I3 => \next_s[1]_i_2_n_0\, I4 => \counter_reg[12]_i_2_n_6\, I5 => \counter[13]_i_6_n_0\, O => \counter[10]_i_1_n_0\ ); \counter[13]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFF01FF0FFF01" ) port map ( I0 => \counter[13]_i_3_n_0\, I1 => current_s(1), I2 => \counter[13]_i_4_n_0\, I3 => \next_s[1]_i_2_n_0\, I4 => \counter_reg[13]_i_5_n_7\, I5 => \counter[13]_i_6_n_0\, O => \counter[13]_i_2_n_0\ ); \counter[13]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFFFFFE" ) port map ( I0 => \counter_reg_n_0_[4]\, I1 => \counter_reg_n_0_[2]\, I2 => \counter_reg_n_0_[1]\, I3 => \counter[13]_i_7_n_0\, I4 => \g0_b6__0_i_6_n_0\, O => \counter[13]_i_3_n_0\ ); \counter[13]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"4F" ) port map ( I0 => \counter[13]_i_3_n_0\, I1 => current_s(1), I2 => current_s(0), O => \counter[13]_i_4_n_0\ ); \counter[13]_i_6\: unisim.vcomponents.LUT3 generic map( INIT => X"32" ) port map ( I0 => \g0_b6__0_i_1_n_0\, I1 => current_s(0), I2 => current_s(1), O => \counter[13]_i_6_n_0\ ); \counter[13]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"FFDF" ) port map ( I0 => \counter_reg_n_0_[13]\, I1 => \counter_reg_n_0_[0]\, I2 => \counter_reg_n_0_[11]\, I3 => \counter_reg_n_0_[3]\, O => \counter[13]_i_7_n_0\ ); \counter[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFF01FF0FFF01" ) port map ( I0 => \counter[13]_i_3_n_0\, I1 => current_s(1), I2 => \counter[13]_i_4_n_0\, I3 => \next_s[1]_i_2_n_0\, I4 => \counter_reg[3]_i_1_n_7\, I5 => \counter[13]_i_6_n_0\, O => \counter[1]_i_1_n_0\ ); \counter[22]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \counter_reg[22]_i_3_n_3\, O => \counter[22]_i_1_n_0\ ); \counter[22]_i_10\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => \counter_reg_n_0_[18]\, I1 => \counter_reg_n_0_[19]\, O => \counter[22]_i_10_n_0\ ); \counter[22]_i_11\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \counter_reg_n_0_[14]\, I1 => \counter_reg_n_0_[15]\, O => \counter[22]_i_11_n_0\ ); \counter[22]_i_12\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \counter_reg_n_0_[20]\, I1 => \counter_reg_n_0_[21]\, O => \counter[22]_i_12_n_0\ ); \counter[22]_i_13\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \counter_reg_n_0_[18]\, I1 => \counter_reg_n_0_[19]\, O => \counter[22]_i_13_n_0\ ); \counter[22]_i_14\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \counter_reg_n_0_[16]\, I1 => \counter_reg_n_0_[17]\, O => \counter[22]_i_14_n_0\ ); \counter[22]_i_15\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \counter_reg_n_0_[14]\, I1 => \counter_reg_n_0_[15]\, O => \counter[22]_i_15_n_0\ ); \counter[22]_i_16\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \counter_reg[11]__0_n_0\, O => \counter[22]_i_16_n_0\ ); \counter[22]_i_17\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => \counter_reg[8]__0_n_0\, I1 => \counter_reg[9]__0_n_0\, O => \counter[22]_i_17_n_0\ ); \counter[22]_i_18\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \counter_reg[6]__0_n_0\, I1 => \counter_reg[7]__0_n_0\, O => \counter[22]_i_18_n_0\ ); \counter[22]_i_19\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \counter_reg[12]__0_n_0\, I1 => \counter_reg[13]__0_n_0\, O => \counter[22]_i_19_n_0\ ); \counter[22]_i_20\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \counter_reg[11]__0_n_0\, I1 => \counter_reg[10]__0_n_0\, O => \counter[22]_i_20_n_0\ ); \counter[22]_i_21\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \counter_reg[8]__0_n_0\, I1 => \counter_reg[9]__0_n_0\, O => \counter[22]_i_21_n_0\ ); \counter[22]_i_22\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \counter_reg[6]__0_n_0\, I1 => \counter_reg[7]__0_n_0\, O => \counter[22]_i_22_n_0\ ); \counter[22]_i_7\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \counter_reg_n_0_[22]\, O => \counter[22]_i_7_n_0\ ); \counter[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFF01FF0FFF01" ) port map ( I0 => \counter[13]_i_3_n_0\, I1 => current_s(1), I2 => \counter[13]_i_4_n_0\, I3 => \next_s[1]_i_2_n_0\, I4 => \counter_reg[3]_i_1_n_6\, I5 => \counter[13]_i_6_n_0\, O => \counter[2]_i_1_n_0\ ); \counter[4]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFF01FF0FFF01" ) port map ( I0 => \counter[13]_i_3_n_0\, I1 => current_s(1), I2 => \counter[13]_i_4_n_0\, I3 => \next_s[1]_i_2_n_0\, I4 => \counter_reg[3]_i_1_n_4\, I5 => \counter[13]_i_6_n_0\, O => \counter[4]_i_1_n_0\ ); \counter[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFF01FF0FFF01" ) port map ( I0 => \counter[13]_i_3_n_0\, I1 => current_s(1), I2 => \counter[13]_i_4_n_0\, I3 => \next_s[1]_i_2_n_0\, I4 => \counter_reg[8]_i_2_n_7\, I5 => \counter[13]_i_6_n_0\, O => \counter[5]_i_1_n_0\ ); \counter[6]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFF01FF0FFF01" ) port map ( I0 => \counter[13]_i_3_n_0\, I1 => current_s(1), I2 => \counter[13]_i_4_n_0\, I3 => \next_s[1]_i_2_n_0\, I4 => \counter_reg[8]_i_2_n_6\, I5 => \counter[13]_i_6_n_0\, O => \counter[6]_i_1_n_0\ ); \counter[7]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFF01FF0FFF01" ) port map ( I0 => \counter[13]_i_3_n_0\, I1 => current_s(1), I2 => \counter[13]_i_4_n_0\, I3 => \next_s[1]_i_2_n_0\, I4 => \counter_reg[8]_i_2_n_5\, I5 => \counter[13]_i_6_n_0\, O => \counter[7]_i_1_n_0\ ); \counter[8]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFF01FF0FFF01" ) port map ( I0 => \counter[13]_i_3_n_0\, I1 => current_s(1), I2 => \counter[13]_i_4_n_0\, I3 => \next_s[1]_i_2_n_0\, I4 => \counter_reg[8]_i_2_n_4\, I5 => \counter[13]_i_6_n_0\, O => \counter[8]_i_1_n_0\ ); \counter[9]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFF01FF0FFF01" ) port map ( I0 => \counter[13]_i_3_n_0\, I1 => current_s(1), I2 => \counter[13]_i_4_n_0\, I3 => \next_s[1]_i_2_n_0\, I4 => \counter_reg[12]_i_2_n_7\, I5 => \counter[13]_i_6_n_0\, O => \counter[9]_i_1_n_0\ ); \counter_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \counter[0]_i_1_n_0\, Q => \counter_reg_n_0_[0]\, R => keyboard0_n_10 ); \counter_reg[0]__0\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter[0]__0_i_1_n_0\, Q => \counter_reg[0]__0_n_0\, R => \counter[22]_i_1_n_0\ ); \counter_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \counter[10]_i_1_n_0\, Q => \counter_reg_n_0_[10]\, R => '0' ); \counter_reg[10]__0\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[12]__0_i_1_n_6\, Q => \counter_reg[10]__0_n_0\, R => \counter[22]_i_1_n_0\ ); \counter_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \counter_reg[12]_i_2_n_5\, Q => \counter_reg_n_0_[11]\, R => keyboard0_n_10 ); \counter_reg[11]__0\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[12]__0_i_1_n_5\, Q => \counter_reg[11]__0_n_0\, R => \counter[22]_i_1_n_0\ ); \counter_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \counter_reg[12]_i_2_n_4\, Q => \counter_reg_n_0_[12]\, R => keyboard0_n_10 ); \counter_reg[12]__0\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[12]__0_i_1_n_4\, Q => \counter_reg[12]__0_n_0\, R => \counter[22]_i_1_n_0\ ); \counter_reg[12]__0_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \counter_reg[8]__0_i_1_n_0\, CO(3) => \counter_reg[12]__0_i_1_n_0\, CO(2 downto 0) => \NLW_counter_reg[12]__0_i_1_CO_UNCONNECTED\(2 downto 0), CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \counter_reg[12]__0_i_1_n_4\, O(2) => \counter_reg[12]__0_i_1_n_5\, O(1) => \counter_reg[12]__0_i_1_n_6\, O(0) => \counter_reg[12]__0_i_1_n_7\, S(3) => \counter_reg[12]__0_n_0\, S(2) => \counter_reg[11]__0_n_0\, S(1) => \counter_reg[10]__0_n_0\, S(0) => \counter_reg[9]__0_n_0\ ); \counter_reg[12]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => \counter_reg[8]_i_2_n_0\, CO(3) => \counter_reg[12]_i_2_n_0\, CO(2 downto 0) => \NLW_counter_reg[12]_i_2_CO_UNCONNECTED\(2 downto 0), CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \counter_reg[12]_i_2_n_4\, O(2) => \counter_reg[12]_i_2_n_5\, O(1) => \counter_reg[12]_i_2_n_6\, O(0) => \counter_reg[12]_i_2_n_7\, S(3) => \counter_reg_n_0_[12]\, S(2) => \counter_reg_n_0_[11]\, S(1) => \counter_reg_n_0_[10]\, S(0) => \counter_reg_n_0_[9]\ ); \counter_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \counter[13]_i_2_n_0\, Q => \counter_reg_n_0_[13]\, R => '0' ); \counter_reg[13]__0\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[16]_i_1_n_7\, Q => \counter_reg[13]__0_n_0\, R => \counter[22]_i_1_n_0\ ); \counter_reg[13]_i_5\: unisim.vcomponents.CARRY4 port map ( CI => \counter_reg[12]_i_2_n_0\, CO(3 downto 0) => \NLW_counter_reg[13]_i_5_CO_UNCONNECTED\(3 downto 0), CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 1) => \NLW_counter_reg[13]_i_5_O_UNCONNECTED\(3 downto 1), O(0) => \counter_reg[13]_i_5_n_7\, S(3 downto 1) => B"000", S(0) => \counter_reg_n_0_[13]\ ); \counter_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[16]_i_1_n_6\, Q => \counter_reg_n_0_[14]\, R => \counter[22]_i_1_n_0\ ); \counter_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[16]_i_1_n_5\, Q => \counter_reg_n_0_[15]\, R => \counter[22]_i_1_n_0\ ); \counter_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[16]_i_1_n_4\, Q => \counter_reg_n_0_[16]\, R => \counter[22]_i_1_n_0\ ); \counter_reg[16]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \counter_reg[12]__0_i_1_n_0\, CO(3) => \counter_reg[16]_i_1_n_0\, CO(2 downto 0) => \NLW_counter_reg[16]_i_1_CO_UNCONNECTED\(2 downto 0), CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \counter_reg[16]_i_1_n_4\, O(2) => \counter_reg[16]_i_1_n_5\, O(1) => \counter_reg[16]_i_1_n_6\, O(0) => \counter_reg[16]_i_1_n_7\, S(3) => \counter_reg_n_0_[16]\, S(2) => \counter_reg_n_0_[15]\, S(1) => \counter_reg_n_0_[14]\, S(0) => \counter_reg[13]__0_n_0\ ); \counter_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[20]_i_1_n_7\, Q => \counter_reg_n_0_[17]\, R => \counter[22]_i_1_n_0\ ); \counter_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[20]_i_1_n_6\, Q => \counter_reg_n_0_[18]\, R => \counter[22]_i_1_n_0\ ); \counter_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[20]_i_1_n_5\, Q => \counter_reg_n_0_[19]\, R => \counter[22]_i_1_n_0\ ); \counter_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \counter[1]_i_1_n_0\, Q => \counter_reg_n_0_[1]\, R => '0' ); \counter_reg[1]__0\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[4]__0_i_1_n_7\, Q => \counter_reg[1]__0_n_0\, R => \counter[22]_i_1_n_0\ ); \counter_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[20]_i_1_n_4\, Q => \counter_reg_n_0_[20]\, R => \counter[22]_i_1_n_0\ ); \counter_reg[20]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \counter_reg[16]_i_1_n_0\, CO(3) => \counter_reg[20]_i_1_n_0\, CO(2 downto 0) => \NLW_counter_reg[20]_i_1_CO_UNCONNECTED\(2 downto 0), CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \counter_reg[20]_i_1_n_4\, O(2) => \counter_reg[20]_i_1_n_5\, O(1) => \counter_reg[20]_i_1_n_6\, O(0) => \counter_reg[20]_i_1_n_7\, S(3) => \counter_reg_n_0_[20]\, S(2) => \counter_reg_n_0_[19]\, S(1) => \counter_reg_n_0_[18]\, S(0) => \counter_reg_n_0_[17]\ ); \counter_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[22]_i_2_n_7\, Q => \counter_reg_n_0_[21]\, R => \counter[22]_i_1_n_0\ ); \counter_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[22]_i_2_n_6\, Q => \counter_reg_n_0_[22]\, R => \counter[22]_i_1_n_0\ ); \counter_reg[22]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => \counter_reg[20]_i_1_n_0\, CO(3 downto 0) => \NLW_counter_reg[22]_i_2_CO_UNCONNECTED\(3 downto 0), CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 2) => \NLW_counter_reg[22]_i_2_O_UNCONNECTED\(3 downto 2), O(1) => \counter_reg[22]_i_2_n_6\, O(0) => \counter_reg[22]_i_2_n_7\, S(3 downto 2) => B"00", S(1) => \counter_reg_n_0_[22]\, S(0) => \counter_reg_n_0_[21]\ ); \counter_reg[22]_i_3\: unisim.vcomponents.CARRY4 port map ( CI => \counter_reg[22]_i_6_n_0\, CO(3 downto 1) => \NLW_counter_reg[22]_i_3_CO_UNCONNECTED\(3 downto 1), CO(0) => \counter_reg[22]_i_3_n_3\, CYINIT => '0', DI(3 downto 1) => B"000", DI(0) => \counter[22]_i_7_n_0\, O(3 downto 0) => \NLW_counter_reg[22]_i_3_O_UNCONNECTED\(3 downto 0), S(3 downto 1) => B"000", S(0) => \counter_reg_n_0_[22]\ ); \counter_reg[22]_i_6\: unisim.vcomponents.CARRY4 port map ( CI => \counter_reg[22]_i_9_n_0\, CO(3) => \counter_reg[22]_i_6_n_0\, CO(2 downto 0) => \NLW_counter_reg[22]_i_6_CO_UNCONNECTED\(2 downto 0), CYINIT => '0', DI(3) => '0', DI(2) => \counter[22]_i_10_n_0\, DI(1) => '0', DI(0) => \counter[22]_i_11_n_0\, O(3 downto 0) => \NLW_counter_reg[22]_i_6_O_UNCONNECTED\(3 downto 0), S(3) => \counter[22]_i_12_n_0\, S(2) => \counter[22]_i_13_n_0\, S(1) => \counter[22]_i_14_n_0\, S(0) => \counter[22]_i_15_n_0\ ); \counter_reg[22]_i_9\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \counter_reg[22]_i_9_n_0\, CO(2 downto 0) => \NLW_counter_reg[22]_i_9_CO_UNCONNECTED\(2 downto 0), CYINIT => '0', DI(3) => '0', DI(2) => \counter[22]_i_16_n_0\, DI(1) => \counter[22]_i_17_n_0\, DI(0) => \counter[22]_i_18_n_0\, O(3 downto 0) => \NLW_counter_reg[22]_i_9_O_UNCONNECTED\(3 downto 0), S(3) => \counter[22]_i_19_n_0\, S(2) => \counter[22]_i_20_n_0\, S(1) => \counter[22]_i_21_n_0\, S(0) => \counter[22]_i_22_n_0\ ); \counter_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \counter[2]_i_1_n_0\, Q => \counter_reg_n_0_[2]\, R => '0' ); \counter_reg[2]__0\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[4]__0_i_1_n_6\, Q => \counter_reg[2]__0_n_0\, R => \counter[22]_i_1_n_0\ ); \counter_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \counter_reg[3]_i_1_n_5\, Q => \counter_reg_n_0_[3]\, R => keyboard0_n_10 ); \counter_reg[3]__0\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[4]__0_i_1_n_5\, Q => \counter_reg[3]__0_n_0\, R => \counter[22]_i_1_n_0\ ); \counter_reg[3]_i_1\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \counter_reg[3]_i_1_n_0\, CO(2 downto 0) => \NLW_counter_reg[3]_i_1_CO_UNCONNECTED\(2 downto 0), CYINIT => \counter_reg_n_0_[0]\, DI(3 downto 0) => B"0000", O(3) => \counter_reg[3]_i_1_n_4\, O(2) => \counter_reg[3]_i_1_n_5\, O(1) => \counter_reg[3]_i_1_n_6\, O(0) => \counter_reg[3]_i_1_n_7\, S(3) => \counter_reg_n_0_[4]\, S(2) => \counter_reg_n_0_[3]\, S(1) => \counter_reg_n_0_[2]\, S(0) => \counter_reg_n_0_[1]\ ); \counter_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \counter[4]_i_1_n_0\, Q => \counter_reg_n_0_[4]\, R => '0' ); \counter_reg[4]__0\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[4]__0_i_1_n_4\, Q => \counter_reg[4]__0_n_0\, R => \counter[22]_i_1_n_0\ ); \counter_reg[4]__0_i_1\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \counter_reg[4]__0_i_1_n_0\, CO(2 downto 0) => \NLW_counter_reg[4]__0_i_1_CO_UNCONNECTED\(2 downto 0), CYINIT => \counter_reg[0]__0_n_0\, DI(3 downto 0) => B"0000", O(3) => \counter_reg[4]__0_i_1_n_4\, O(2) => \counter_reg[4]__0_i_1_n_5\, O(1) => \counter_reg[4]__0_i_1_n_6\, O(0) => \counter_reg[4]__0_i_1_n_7\, S(3) => \counter_reg[4]__0_n_0\, S(2) => \counter_reg[3]__0_n_0\, S(1) => \counter_reg[2]__0_n_0\, S(0) => \counter_reg[1]__0_n_0\ ); \counter_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \counter[5]_i_1_n_0\, Q => \counter_reg_n_0_[5]\, R => '0' ); \counter_reg[5]__0\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[8]__0_i_1_n_7\, Q => \counter_reg[5]__0_n_0\, R => \counter[22]_i_1_n_0\ ); \counter_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \counter[6]_i_1_n_0\, Q => \counter_reg_n_0_[6]\, R => '0' ); \counter_reg[6]__0\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[8]__0_i_1_n_6\, Q => \counter_reg[6]__0_n_0\, R => \counter[22]_i_1_n_0\ ); \counter_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \counter[7]_i_1_n_0\, Q => \counter_reg_n_0_[7]\, R => '0' ); \counter_reg[7]__0\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[8]__0_i_1_n_5\, Q => \counter_reg[7]__0_n_0\, R => \counter[22]_i_1_n_0\ ); \counter_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \counter[8]_i_1_n_0\, Q => \counter_reg_n_0_[8]\, R => '0' ); \counter_reg[8]__0\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[8]__0_i_1_n_4\, Q => \counter_reg[8]__0_n_0\, R => \counter[22]_i_1_n_0\ ); \counter_reg[8]__0_i_1\: unisim.vcomponents.CARRY4 port map ( CI => \counter_reg[4]__0_i_1_n_0\, CO(3) => \counter_reg[8]__0_i_1_n_0\, CO(2 downto 0) => \NLW_counter_reg[8]__0_i_1_CO_UNCONNECTED\(2 downto 0), CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \counter_reg[8]__0_i_1_n_4\, O(2) => \counter_reg[8]__0_i_1_n_5\, O(1) => \counter_reg[8]__0_i_1_n_6\, O(0) => \counter_reg[8]__0_i_1_n_7\, S(3) => \counter_reg[8]__0_n_0\, S(2) => \counter_reg[7]__0_n_0\, S(1) => \counter_reg[6]__0_n_0\, S(0) => \counter_reg[5]__0_n_0\ ); \counter_reg[8]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => \counter_reg[3]_i_1_n_0\, CO(3) => \counter_reg[8]_i_2_n_0\, CO(2 downto 0) => \NLW_counter_reg[8]_i_2_CO_UNCONNECTED\(2 downto 0), CYINIT => '0', DI(3 downto 0) => B"0000", O(3) => \counter_reg[8]_i_2_n_4\, O(2) => \counter_reg[8]_i_2_n_5\, O(1) => \counter_reg[8]_i_2_n_6\, O(0) => \counter_reg[8]_i_2_n_7\, S(3) => \counter_reg_n_0_[8]\, S(2) => \counter_reg_n_0_[7]\, S(1) => \counter_reg_n_0_[6]\, S(0) => \counter_reg_n_0_[5]\ ); \counter_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \counter[9]_i_1_n_0\, Q => \counter_reg_n_0_[9]\, R => '0' ); \counter_reg[9]__0\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk10M, CE => '1', D => \counter_reg[12]__0_i_1_n_7\, Q => \counter_reg[9]__0_n_0\, R => \counter[22]_i_1_n_0\ ); \current_s_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => '1', D => next_s(0), Q => current_s(0), R => '0' ); \current_s_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => '1', D => next_s(1), Q => current_s(1), R => '0' ); \fb_in_addr[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"11F100E0" ) port map ( I0 => current_s(1), I1 => current_s(0), I2 => \counter[13]_i_3_n_0\, I3 => \counter_reg_n_0_[0]\, I4 => fb_in_addr0(0), O => \fb_in_addr[0]_i_1_n_0\ ); \fb_in_addr[10]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"CCCA0FFA" ) port map ( I0 => fb_in_addr0(10), I1 => \counter_reg[12]_i_2_n_6\, I2 => current_s(0), I3 => current_s(1), I4 => \counter[13]_i_3_n_0\, O => \fb_in_addr[10]_i_1_n_0\ ); \fb_in_addr[11]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"F111E000" ) port map ( I0 => current_s(1), I1 => current_s(0), I2 => \counter[13]_i_3_n_0\, I3 => \counter_reg[12]_i_2_n_5\, I4 => fb_in_addr0(11), O => \fb_in_addr[11]_i_1_n_0\ ); \fb_in_addr[11]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \counter_reg[12]_i_2_n_5\, I1 => \g0_b6__0_i_1_n_0\, O => \fb_in_addr[11]_i_3_n_0\ ); \fb_in_addr[11]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \counter_reg[12]_i_2_n_6\, I1 => \g0_b6__0_i_1_n_0\, O => \fb_in_addr[11]_i_4_n_0\ ); \fb_in_addr[11]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \counter_reg[8]_i_2_n_4\, I1 => \g0_b6__0_i_1_n_0\, O => \fb_in_addr[11]_i_5_n_0\ ); \fb_in_addr[11]_i_6\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => \g0_b6__0_i_1_n_0\, I1 => \counter_reg[12]_i_2_n_5\, O => \fb_in_addr[11]_i_6_n_0\ ); \fb_in_addr[11]_i_7\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => \g0_b6__0_i_1_n_0\, I1 => \counter_reg[12]_i_2_n_6\, O => \fb_in_addr[11]_i_7_n_0\ ); \fb_in_addr[11]_i_8\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \counter_reg[12]_i_2_n_7\, I1 => \g0_b6__0_i_1_n_0\, O => \fb_in_addr[11]_i_8_n_0\ ); \fb_in_addr[11]_i_9\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => \g0_b6__0_i_1_n_0\, I1 => \counter_reg[8]_i_2_n_4\, O => \fb_in_addr[11]_i_9_n_0\ ); \fb_in_addr[12]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"F111E000" ) port map ( I0 => current_s(1), I1 => current_s(0), I2 => \counter[13]_i_3_n_0\, I3 => \counter_reg[12]_i_2_n_4\, I4 => fb_in_addr0(12), O => \fb_in_addr[12]_i_1_n_0\ ); \fb_in_addr[13]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"CCCA0FFA" ) port map ( I0 => fb_in_addr0(13), I1 => \counter_reg[13]_i_5_n_7\, I2 => current_s(0), I3 => current_s(1), I4 => \counter[13]_i_3_n_0\, O => \fb_in_addr[13]_i_1_n_0\ ); \fb_in_addr[13]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \counter_reg[13]_i_5_n_7\, I1 => \g0_b6__0_i_1_n_0\, O => \fb_in_addr[13]_i_3_n_0\ ); \fb_in_addr[13]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \counter_reg[12]_i_2_n_4\, I1 => \g0_b6__0_i_1_n_0\, O => \fb_in_addr[13]_i_4_n_0\ ); \fb_in_addr[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"CCCA0FFA" ) port map ( I0 => fb_in_addr0(1), I1 => \counter_reg[3]_i_1_n_7\, I2 => current_s(0), I3 => current_s(1), I4 => \counter[13]_i_3_n_0\, O => \fb_in_addr[1]_i_1_n_0\ ); \fb_in_addr[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"CCCA0FFA" ) port map ( I0 => fb_in_addr0(2), I1 => \counter_reg[3]_i_1_n_6\, I2 => current_s(0), I3 => current_s(1), I4 => \counter[13]_i_3_n_0\, O => \fb_in_addr[2]_i_1_n_0\ ); \fb_in_addr[3]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"F111E000" ) port map ( I0 => current_s(1), I1 => current_s(0), I2 => \counter[13]_i_3_n_0\, I3 => \counter_reg[3]_i_1_n_5\, I4 => fb_in_addr0(3), O => \fb_in_addr[3]_i_1_n_0\ ); \fb_in_addr[3]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \counter_reg[3]_i_1_n_7\, I1 => \g0_b6__0_i_1_n_0\, O => \fb_in_addr[3]_i_3_n_0\ ); \fb_in_addr[3]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \g0_b6__0_i_1_n_0\, I1 => \counter_reg[3]_i_1_n_5\, O => \fb_in_addr[3]_i_4_n_0\ ); \fb_in_addr[3]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \g0_b6__0_i_1_n_0\, I1 => \counter_reg[3]_i_1_n_6\, O => \fb_in_addr[3]_i_5_n_0\ ); \fb_in_addr[3]_i_6\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => \g0_b6__0_i_1_n_0\, I1 => \counter_reg[3]_i_1_n_7\, O => \fb_in_addr[3]_i_6_n_0\ ); \fb_in_addr[3]_i_7\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \g0_b6__0_i_1_n_0\, I1 => \counter_reg_n_0_[0]\, O => \fb_in_addr[3]_i_7_n_0\ ); \fb_in_addr[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"CCCA0FFA" ) port map ( I0 => fb_in_addr0(4), I1 => \counter_reg[3]_i_1_n_4\, I2 => current_s(0), I3 => current_s(1), I4 => \counter[13]_i_3_n_0\, O => \fb_in_addr[4]_i_1_n_0\ ); \fb_in_addr[5]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"CCCA0FFA" ) port map ( I0 => fb_in_addr0(5), I1 => \counter_reg[8]_i_2_n_7\, I2 => current_s(0), I3 => current_s(1), I4 => \counter[13]_i_3_n_0\, O => \fb_in_addr[5]_i_1_n_0\ ); \fb_in_addr[6]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"CCCA0FFA" ) port map ( I0 => fb_in_addr0(6), I1 => \counter_reg[8]_i_2_n_6\, I2 => current_s(0), I3 => current_s(1), I4 => \counter[13]_i_3_n_0\, O => \fb_in_addr[6]_i_1_n_0\ ); \fb_in_addr[7]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"CCCA0FFA" ) port map ( I0 => fb_in_addr0(7), I1 => \counter_reg[8]_i_2_n_5\, I2 => current_s(0), I3 => current_s(1), I4 => \counter[13]_i_3_n_0\, O => \fb_in_addr[7]_i_1_n_0\ ); \fb_in_addr[7]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \counter_reg[8]_i_2_n_6\, I1 => \g0_b6__0_i_1_n_0\, O => \fb_in_addr[7]_i_3_n_0\ ); \fb_in_addr[7]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \counter_reg[8]_i_2_n_7\, I1 => \g0_b6__0_i_1_n_0\, O => \fb_in_addr[7]_i_4_n_0\ ); \fb_in_addr[7]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \counter_reg[8]_i_2_n_5\, I1 => \g0_b6__0_i_1_n_0\, O => \fb_in_addr[7]_i_5_n_0\ ); \fb_in_addr[7]_i_6\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => \g0_b6__0_i_1_n_0\, I1 => \counter_reg[8]_i_2_n_6\, O => \fb_in_addr[7]_i_6_n_0\ ); \fb_in_addr[7]_i_7\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => \g0_b6__0_i_1_n_0\, I1 => \counter_reg[8]_i_2_n_7\, O => \fb_in_addr[7]_i_7_n_0\ ); \fb_in_addr[7]_i_8\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \counter_reg[3]_i_1_n_4\, I1 => \g0_b6__0_i_1_n_0\, O => \fb_in_addr[7]_i_8_n_0\ ); \fb_in_addr[8]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"CCCA0FFA" ) port map ( I0 => fb_in_addr0(8), I1 => \counter_reg[8]_i_2_n_4\, I2 => current_s(0), I3 => current_s(1), I4 => \counter[13]_i_3_n_0\, O => \fb_in_addr[8]_i_1_n_0\ ); \fb_in_addr[9]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"CCCA0FFA" ) port map ( I0 => fb_in_addr0(9), I1 => \counter_reg[12]_i_2_n_7\, I2 => current_s(0), I3 => current_s(1), I4 => \counter[13]_i_3_n_0\, O => \fb_in_addr[9]_i_1_n_0\ ); \fb_in_addr_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \fb_in_addr[0]_i_1_n_0\, Q => addra(0), R => '0' ); \fb_in_addr_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \fb_in_addr[10]_i_1_n_0\, Q => addra(10), R => '0' ); \fb_in_addr_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \fb_in_addr[11]_i_1_n_0\, Q => addra(11), R => '0' ); \fb_in_addr_reg[11]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => \fb_in_addr_reg[7]_i_2_n_0\, CO(3) => \fb_in_addr_reg[11]_i_2_n_0\, CO(2 downto 0) => \NLW_fb_in_addr_reg[11]_i_2_CO_UNCONNECTED\(2 downto 0), CYINIT => '0', DI(3) => \fb_in_addr[11]_i_3_n_0\, DI(2) => \fb_in_addr[11]_i_4_n_0\, DI(1) => '0', DI(0) => \fb_in_addr[11]_i_5_n_0\, O(3 downto 0) => fb_in_addr0(11 downto 8), S(3) => \fb_in_addr[11]_i_6_n_0\, S(2) => \fb_in_addr[11]_i_7_n_0\, S(1) => \fb_in_addr[11]_i_8_n_0\, S(0) => \fb_in_addr[11]_i_9_n_0\ ); \fb_in_addr_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \fb_in_addr[12]_i_1_n_0\, Q => addra(12), R => '0' ); \fb_in_addr_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \fb_in_addr[13]_i_1_n_0\, Q => addra(13), R => '0' ); \fb_in_addr_reg[13]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => \fb_in_addr_reg[11]_i_2_n_0\, CO(3 downto 0) => \NLW_fb_in_addr_reg[13]_i_2_CO_UNCONNECTED\(3 downto 0), CYINIT => '0', DI(3 downto 0) => B"0000", O(3 downto 2) => \NLW_fb_in_addr_reg[13]_i_2_O_UNCONNECTED\(3 downto 2), O(1 downto 0) => fb_in_addr0(13 downto 12), S(3 downto 2) => B"00", S(1) => \fb_in_addr[13]_i_3_n_0\, S(0) => \fb_in_addr[13]_i_4_n_0\ ); \fb_in_addr_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \fb_in_addr[1]_i_1_n_0\, Q => addra(1), R => '0' ); \fb_in_addr_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \fb_in_addr[2]_i_1_n_0\, Q => addra(2), R => '0' ); \fb_in_addr_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \fb_in_addr[3]_i_1_n_0\, Q => addra(3), R => '0' ); \fb_in_addr_reg[3]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \fb_in_addr_reg[3]_i_2_n_0\, CO(2 downto 0) => \NLW_fb_in_addr_reg[3]_i_2_CO_UNCONNECTED\(2 downto 0), CYINIT => '0', DI(3 downto 2) => B"00", DI(1) => \fb_in_addr[3]_i_3_n_0\, DI(0) => '0', O(3 downto 0) => fb_in_addr0(3 downto 0), S(3) => \fb_in_addr[3]_i_4_n_0\, S(2) => \fb_in_addr[3]_i_5_n_0\, S(1) => \fb_in_addr[3]_i_6_n_0\, S(0) => \fb_in_addr[3]_i_7_n_0\ ); \fb_in_addr_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \fb_in_addr[4]_i_1_n_0\, Q => addra(4), R => '0' ); \fb_in_addr_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \fb_in_addr[5]_i_1_n_0\, Q => addra(5), R => '0' ); \fb_in_addr_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \fb_in_addr[6]_i_1_n_0\, Q => addra(6), R => '0' ); \fb_in_addr_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \fb_in_addr[7]_i_1_n_0\, Q => addra(7), R => '0' ); \fb_in_addr_reg[7]_i_2\: unisim.vcomponents.CARRY4 port map ( CI => \fb_in_addr_reg[3]_i_2_n_0\, CO(3) => \fb_in_addr_reg[7]_i_2_n_0\, CO(2 downto 0) => \NLW_fb_in_addr_reg[7]_i_2_CO_UNCONNECTED\(2 downto 0), CYINIT => '0', DI(3) => '0', DI(2) => \fb_in_addr[7]_i_3_n_0\, DI(1) => \fb_in_addr[7]_i_4_n_0\, DI(0) => '0', O(3 downto 0) => fb_in_addr0(7 downto 4), S(3) => \fb_in_addr[7]_i_5_n_0\, S(2) => \fb_in_addr[7]_i_6_n_0\, S(1) => \fb_in_addr[7]_i_7_n_0\, S(0) => \fb_in_addr[7]_i_8_n_0\ ); \fb_in_addr_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \fb_in_addr[8]_i_1_n_0\, Q => addra(8), R => '0' ); \fb_in_addr_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => \fb_in_addr[9]_i_1_n_0\, Q => addra(9), R => '0' ); \fb_in_dat[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"02" ) port map ( I0 => clk_1_reg_n_0, I1 => current_s(1), I2 => current_s(0), O => fb_in_dat(7) ); \fb_in_dat_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => fb_in_dat(0), Q => dina(0), R => '0' ); \fb_in_dat_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => fb_in_dat(1), Q => dina(1), R => '0' ); \fb_in_dat_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => fb_in_dat(2), Q => dina(2), R => '0' ); \fb_in_dat_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => fb_in_dat(3), Q => dina(3), R => '0' ); \fb_in_dat_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => fb_in_dat(4), Q => dina(4), R => '0' ); \fb_in_dat_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => fb_in_dat(5), Q => dina(5), R => '0' ); \fb_in_dat_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => fb_in_dat(6), Q => dina(6), R => '0' ); \fb_in_dat_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => keyboard0_n_2, D => fb_in_dat(7), Q => dina(7), R => '0' ); frameBuffer0: entity work.FrameBuffer port map ( addra(13 downto 0) => addra(13 downto 0), addrb(13 downto 0) => fbOutAddr(13 downto 0), clka => clk_BUFG, clkb => clk108M, dina(7 downto 0) => dina(7 downto 0), doutb(7 downto 0) => doutb(7 downto 0), wea(0) => '1' ); \g0_b0__0\: unisim.vcomponents.LUT6 generic map( INIT => X"000F40F40FBBBFB0" ) port map ( I0 => \counter_reg_n_0_[0]\, I1 => \g0_b6__0_i_1_n_0\, I2 => \g0_b6__0_i_2_n_0\, I3 => \g0_b6__0_i_3_n_0\, I4 => \g0_b6__0_i_4_n_0\, I5 => \g0_b6__0_i_5_n_0\, O => \g0_b0__0_n_0\ ); \g0_b1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"04F0B4F400B40F40" ) port map ( I0 => \counter_reg_n_0_[0]\, I1 => \g0_b6__0_i_1_n_0\, I2 => \g0_b6__0_i_2_n_0\, I3 => \g0_b6__0_i_3_n_0\, I4 => \g0_b6__0_i_4_n_0\, I5 => \g0_b6__0_i_5_n_0\, O => \g0_b1__0_n_0\ ); \g0_b2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"04FFBFB4B40400B0" ) port map ( I0 => \counter_reg_n_0_[0]\, I1 => \g0_b6__0_i_1_n_0\, I2 => \g0_b6__0_i_2_n_0\, I3 => \g0_b6__0_i_3_n_0\, I4 => \g0_b6__0_i_4_n_0\, I5 => \g0_b6__0_i_5_n_0\, O => \g0_b2__0_n_0\ ); \g0_b3__0\: unisim.vcomponents.LUT6 generic map( INIT => X"04F0F4B40BBF0000" ) port map ( I0 => \counter_reg_n_0_[0]\, I1 => \g0_b6__0_i_1_n_0\, I2 => \g0_b6__0_i_2_n_0\, I3 => \g0_b6__0_i_3_n_0\, I4 => \g0_b6__0_i_4_n_0\, I5 => \g0_b6__0_i_5_n_0\, O => \g0_b3__0_n_0\ ); \g0_b4__0\: unisim.vcomponents.LUT6 generic map( INIT => X"00040B00BB0B0F4B" ) port map ( I0 => \counter_reg_n_0_[0]\, I1 => \g0_b6__0_i_1_n_0\, I2 => \g0_b6__0_i_2_n_0\, I3 => \g0_b6__0_i_3_n_0\, I4 => \g0_b6__0_i_4_n_0\, I5 => \g0_b6__0_i_5_n_0\, O => \g0_b4__0_n_0\ ); \g0_b5__0\: unisim.vcomponents.LUT6 generic map( INIT => X"04FFFFFFFFFFFFF0" ) port map ( I0 => \counter_reg_n_0_[0]\, I1 => \g0_b6__0_i_1_n_0\, I2 => \g0_b6__0_i_2_n_0\, I3 => \g0_b6__0_i_3_n_0\, I4 => \g0_b6__0_i_4_n_0\, I5 => \g0_b6__0_i_5_n_0\, O => \g0_b5__0_n_0\ ); \g0_b6__0\: unisim.vcomponents.LUT6 generic map( INIT => X"000FFFF4BFBFBFFB" ) port map ( I0 => \counter_reg_n_0_[0]\, I1 => \g0_b6__0_i_1_n_0\, I2 => \g0_b6__0_i_2_n_0\, I3 => \g0_b6__0_i_3_n_0\, I4 => \g0_b6__0_i_4_n_0\, I5 => \g0_b6__0_i_5_n_0\, O => \g0_b6__0_n_0\ ); \g0_b6__0_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"000000000000007F" ) port map ( I0 => \counter_reg_n_0_[4]\, I1 => \counter_reg_n_0_[2]\, I2 => \counter_reg_n_0_[3]\, I3 => \counter_reg_n_0_[11]\, I4 => \counter_reg_n_0_[13]\, I5 => \g0_b6__0_i_6_n_0\, O => \g0_b6__0_i_1_n_0\ ); \g0_b6__0_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"84" ) port map ( I0 => \counter_reg_n_0_[0]\, I1 => \g0_b6__0_i_1_n_0\, I2 => \counter_reg[3]_i_1_n_7\, O => \g0_b6__0_i_2_n_0\ ); \g0_b6__0_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"D020" ) port map ( I0 => \counter_reg[3]_i_1_n_7\, I1 => \counter_reg_n_0_[0]\, I2 => \g0_b6__0_i_1_n_0\, I3 => \counter_reg[3]_i_1_n_6\, O => \g0_b6__0_i_3_n_0\ ); \g0_b6__0_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"A060A0A0" ) port map ( I0 => \counter_reg[3]_i_1_n_5\, I1 => \counter_reg[3]_i_1_n_6\, I2 => \g0_b6__0_i_1_n_0\, I3 => \counter_reg_n_0_[0]\, I4 => \counter_reg[3]_i_1_n_7\, O => \g0_b6__0_i_4_n_0\ ); \g0_b6__0_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"D0F0F0F020000000" ) port map ( I0 => \counter_reg[3]_i_1_n_7\, I1 => \counter_reg_n_0_[0]\, I2 => \g0_b6__0_i_1_n_0\, I3 => \counter_reg[3]_i_1_n_6\, I4 => \counter_reg[3]_i_1_n_5\, I5 => \counter_reg[3]_i_1_n_4\, O => \g0_b6__0_i_5_n_0\ ); \g0_b6__0_i_6\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => \g0_b6__0_i_7_n_0\, I1 => \counter_reg_n_0_[7]\, I2 => \counter_reg_n_0_[9]\, I3 => \counter_reg_n_0_[8]\, O => \g0_b6__0_i_6_n_0\ ); \g0_b6__0_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => \counter_reg_n_0_[6]\, I1 => \counter_reg_n_0_[5]\, I2 => \counter_reg_n_0_[10]\, I3 => \counter_reg_n_0_[12]\, O => \g0_b6__0_i_7_n_0\ ); keyboard0: entity work.ps2_keyboard_to_ascii port map ( D(1 downto 0) => next_s(1 downto 0), PS2Clk_IBUF => PS2Clk_IBUF, PS2Data_IBUF => PS2Data_IBUF, Q(1 downto 0) => current_s(1 downto 0), clk_BUFG => clk_BUFG, \counter_reg[0]\ => keyboard0_n_2, \counter_reg[0]_0\ => \g0_b0__0_n_0\, \counter_reg[0]_1\ => \g0_b1__0_n_0\, \counter_reg[0]_2\ => \g0_b2__0_n_0\, \counter_reg[0]_3\ => \g0_b3__0_n_0\, \counter_reg[0]_4\ => \g0_b4__0_n_0\, \counter_reg[0]_5\ => \g0_b5__0_n_0\, \counter_reg[0]_6\ => \g0_b6__0_n_0\, \counter_reg[12]\ => keyboard0_n_10, \counter_reg[4]\ => \g0_b6__0_i_1_n_0\, \counter_reg[4]_0\ => \counter[13]_i_3_n_0\, \current_s_reg[0]\ => \next_s[1]_i_2_n_0\, \fb_in_dat_reg[6]\(6 downto 0) => fb_in_dat(6 downto 0), \next_s_reg[0]\ => keyboard0_n_1, \next_s_reg[1]\ => keyboard0_n_0 ); \next_s[1]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"04" ) port map ( I0 => current_s(0), I1 => current_s(1), I2 => \counter[13]_i_3_n_0\, O => \next_s[1]_i_2_n_0\ ); \next_s_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => '1', D => keyboard0_n_1, Q => next_s(0), R => '0' ); \next_s_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => clk_BUFG, CE => '1', D => keyboard0_n_0, Q => next_s(1), R => '0' ); \sw[0]_IBUF_inst\: unisim.vcomponents.IBUF port map ( I => \sw[0]\, O => \sw[0]_IBUF\ ); \sw[10]_IBUF_inst\: unisim.vcomponents.IBUF port map ( I => \sw[10]\, O => \sw[10]_IBUF\ ); \sw[11]_IBUF_inst\: unisim.vcomponents.IBUF port map ( I => \sw[11]\, O => \sw[11]_IBUF\ ); \sw[12]_IBUF_inst\: unisim.vcomponents.IBUF port map ( I => \sw[12]\, O => \sw[12]_IBUF\ ); \sw[13]_IBUF_inst\: unisim.vcomponents.IBUF port map ( I => \sw[13]\, O => \sw[13]_IBUF\ ); \sw[14]_IBUF_inst\: unisim.vcomponents.IBUF port map ( I => \sw[14]\, O => \sw[14]_IBUF\ ); \sw[15]_IBUF_inst\: unisim.vcomponents.IBUF port map ( I => \sw[15]\, O => \sw[15]_IBUF\ ); \sw[1]_IBUF_inst\: unisim.vcomponents.IBUF port map ( I => \sw[1]\, O => \sw[1]_IBUF\ ); \sw[2]_IBUF_inst\: unisim.vcomponents.IBUF port map ( I => \sw[2]\, O => \sw[2]_IBUF\ ); \sw[3]_IBUF_inst\: unisim.vcomponents.IBUF port map ( I => \sw[3]\, O => \sw[3]_IBUF\ ); \sw[4]_IBUF_inst\: unisim.vcomponents.IBUF port map ( I => \sw[4]\, O => \sw[4]_IBUF\ ); \sw[5]_IBUF_inst\: unisim.vcomponents.IBUF port map ( I => \sw[5]\, O => \sw[5]_IBUF\ ); \sw[6]_IBUF_inst\: unisim.vcomponents.IBUF port map ( I => \sw[6]\, O => \sw[6]_IBUF\ ); \sw[7]_IBUF_inst\: unisim.vcomponents.IBUF port map ( I => \sw[7]\, O => \sw[7]_IBUF\ ); \sw[8]_IBUF_inst\: unisim.vcomponents.IBUF port map ( I => \sw[8]\, O => \sw[8]_IBUF\ ); \sw[9]_IBUF_inst\: unisim.vcomponents.IBUF port map ( I => \sw[9]\, O => \sw[9]_IBUF\ ); vga0: entity work.Vga port map ( D(7 downto 0) => doutb(7 downto 0), Hsync_OBUF => Hsync_OBUF, Vsync_OBUF => Vsync_OBUF, addrb(13 downto 0) => fbOutAddr(13 downto 0), clk108M => clk108M, vgaBlue_OBUF(0) => vgaBlue_OBUF(0) ); \vgaBlue_OBUF[0]_inst\: unisim.vcomponents.OBUF port map ( I => vgaBlue_OBUF(0), O => vgaBlue(0) ); \vgaBlue_OBUF[1]_inst\: unisim.vcomponents.OBUF port map ( I => vgaBlue_OBUF(0), O => vgaBlue(1) ); \vgaBlue_OBUF[2]_inst\: unisim.vcomponents.OBUF port map ( I => vgaBlue_OBUF(0), O => vgaBlue(2) ); \vgaBlue_OBUF[3]_inst\: unisim.vcomponents.OBUF port map ( I => vgaBlue_OBUF(0), O => vgaBlue(3) ); \vgaGreen_OBUF[0]_inst\: unisim.vcomponents.OBUF port map ( I => vgaBlue_OBUF(0), O => vgaGreen(0) ); \vgaGreen_OBUF[1]_inst\: unisim.vcomponents.OBUF port map ( I => vgaBlue_OBUF(0), O => vgaGreen(1) ); \vgaGreen_OBUF[2]_inst\: unisim.vcomponents.OBUF port map ( I => vgaBlue_OBUF(0), O => vgaGreen(2) ); \vgaGreen_OBUF[3]_inst\: unisim.vcomponents.OBUF port map ( I => vgaBlue_OBUF(0), O => vgaGreen(3) ); \vgaRed_OBUF[0]_inst\: unisim.vcomponents.OBUF port map ( I => vgaBlue_OBUF(0), O => vgaRed(0) ); \vgaRed_OBUF[1]_inst\: unisim.vcomponents.OBUF port map ( I => vgaBlue_OBUF(0), O => vgaRed(1) ); \vgaRed_OBUF[2]_inst\: unisim.vcomponents.OBUF port map ( I => vgaBlue_OBUF(0), O => vgaRed(2) ); \vgaRed_OBUF[3]_inst\: unisim.vcomponents.OBUF port map ( I => vgaBlue_OBUF(0), O => vgaRed(3) ); end STRUCTURE;

mit

MarkBlanco/FPGA_Sandbox

RecComp/Lab3/led_controller/led_controller.cache/ip/2017.3/38a92fb39758d0fa/led_controller_design_rst_ps7_0_100M_0_sim_netlist.vhdl

1

35714

-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017 -- Date : Tue Oct 17 15:19:41 2017 -- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS -- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ led_controller_design_rst_ps7_0_100M_0_sim_netlist.vhdl -- Design : led_controller_design_rst_ps7_0_100M_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is port ( lpf_asr_reg : out STD_LOGIC; scndry_out : out STD_LOGIC; lpf_asr : in STD_LOGIC; asr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 ); p_1_in : in STD_LOGIC; p_2_in : in STD_LOGIC; aux_reset_in : in STD_LOGIC; slowest_sync_clk : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is signal asr_d1 : STD_LOGIC; signal s_level_out_d1_cdc_to : STD_LOGIC; signal s_level_out_d2 : STD_LOGIC; signal s_level_out_d3 : STD_LOGIC; signal \^scndry_out\ : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; attribute box_type : string; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; begin scndry_out <= \^scndry_out\; \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => asr_d1, Q => s_level_out_d1_cdc_to, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => aux_reset_in, O => asr_d1 ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d1_cdc_to, Q => s_level_out_d2, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d3, Q => \^scndry_out\, R => '0' ); lpf_asr_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"EAAAAAA8" ) port map ( I0 => lpf_asr, I1 => asr_lpf(0), I2 => \^scndry_out\, I3 => p_1_in, I4 => p_2_in, O => lpf_asr_reg ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 is port ( lpf_exr_reg : out STD_LOGIC; scndry_out : out STD_LOGIC; lpf_exr : in STD_LOGIC; p_3_out : in STD_LOGIC_VECTOR ( 2 downto 0 ); mb_debug_sys_rst : in STD_LOGIC; ext_reset_in : in STD_LOGIC; slowest_sync_clk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 : entity is "cdc_sync"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 is signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\ : STD_LOGIC; signal s_level_out_d1_cdc_to : STD_LOGIC; signal s_level_out_d2 : STD_LOGIC; signal s_level_out_d3 : STD_LOGIC; signal \^scndry_out\ : STD_LOGIC; attribute ASYNC_REG : boolean; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR"; attribute box_type : string; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE"; attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true; attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR"; attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE"; begin scndry_out <= \^scndry_out\; \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\, Q => s_level_out_d1_cdc_to, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0\: unisim.vcomponents.LUT2 generic map( INIT => X"B" ) port map ( I0 => mb_debug_sys_rst, I1 => ext_reset_in, O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\ ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d1_cdc_to, Q => s_level_out_d2, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d2, Q => s_level_out_d3, R => '0' ); \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => s_level_out_d3, Q => \^scndry_out\, R => '0' ); lpf_exr_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"EAAAAAA8" ) port map ( I0 => lpf_exr, I1 => p_3_out(0), I2 => \^scndry_out\, I3 => p_3_out(1), I4 => p_3_out(2), O => lpf_exr_reg ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n is port ( Q : out STD_LOGIC_VECTOR ( 5 downto 0 ); seq_clr : in STD_LOGIC; seq_cnt_en : in STD_LOGIC; slowest_sync_clk : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n is signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 ); signal clear : STD_LOGIC; signal q_int0 : STD_LOGIC_VECTOR ( 5 downto 0 ); attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \q_int[4]_i_1\ : label is "soft_lutpair0"; begin Q(5 downto 0) <= \^q\(5 downto 0); \q_int[0]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^q\(0), O => q_int0(0) ); \q_int[1]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"6" ) port map ( I0 => \^q\(0), I1 => \^q\(1), O => q_int0(1) ); \q_int[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"78" ) port map ( I0 => \^q\(0), I1 => \^q\(1), I2 => \^q\(2), O => q_int0(2) ); \q_int[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"7F80" ) port map ( I0 => \^q\(1), I1 => \^q\(0), I2 => \^q\(2), I3 => \^q\(3), O => q_int0(3) ); \q_int[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"7FFF8000" ) port map ( I0 => \^q\(2), I1 => \^q\(0), I2 => \^q\(1), I3 => \^q\(3), I4 => \^q\(4), O => q_int0(4) ); \q_int[5]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => seq_clr, O => clear ); \q_int[5]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFF80000000" ) port map ( I0 => \^q\(3), I1 => \^q\(1), I2 => \^q\(0), I3 => \^q\(2), I4 => \^q\(4), I5 => \^q\(5), O => q_int0(5) ); \q_int_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(0), Q => \^q\(0), R => clear ); \q_int_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(1), Q => \^q\(1), R => clear ); \q_int_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(2), Q => \^q\(2), R => clear ); \q_int_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(3), Q => \^q\(3), R => clear ); \q_int_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(4), Q => \^q\(4), R => clear ); \q_int_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => seq_cnt_en, D => q_int0(5), Q => \^q\(5), R => clear ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf is port ( lpf_int : out STD_LOGIC; slowest_sync_clk : in STD_LOGIC; dcm_locked : in STD_LOGIC; aux_reset_in : in STD_LOGIC; mb_debug_sys_rst : in STD_LOGIC; ext_reset_in : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf is signal \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\ : STD_LOGIC; signal \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\ : STD_LOGIC; signal Q : STD_LOGIC; signal asr_lpf : STD_LOGIC_VECTOR ( 0 to 0 ); signal lpf_asr : STD_LOGIC; signal lpf_exr : STD_LOGIC; signal \lpf_int0__0\ : STD_LOGIC; signal p_1_in : STD_LOGIC; signal p_2_in : STD_LOGIC; signal p_3_in1_in : STD_LOGIC; signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 ); attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of POR_SRL_I : label is "SRL16"; attribute box_type : string; attribute box_type of POR_SRL_I : label is "PRIMITIVE"; attribute srl_name : string; attribute srl_name of POR_SRL_I : label is "U0/\EXT_LPF/POR_SRL_I "; begin \ACTIVE_LOW_AUX.ACT_LO_AUX\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync port map ( asr_lpf(0) => asr_lpf(0), aux_reset_in => aux_reset_in, lpf_asr => lpf_asr, lpf_asr_reg => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\, p_1_in => p_1_in, p_2_in => p_2_in, scndry_out => p_3_in1_in, slowest_sync_clk => slowest_sync_clk ); \ACTIVE_LOW_EXT.ACT_LO_EXT\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 port map ( ext_reset_in => ext_reset_in, lpf_exr => lpf_exr, lpf_exr_reg => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\, mb_debug_sys_rst => mb_debug_sys_rst, p_3_out(2 downto 0) => p_3_out(2 downto 0), scndry_out => p_3_out(3), slowest_sync_clk => slowest_sync_clk ); \AUX_LPF[1].asr_lpf_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_in1_in, Q => p_2_in, R => '0' ); \AUX_LPF[2].asr_lpf_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_2_in, Q => p_1_in, R => '0' ); \AUX_LPF[3].asr_lpf_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_1_in, Q => asr_lpf(0), R => '0' ); \EXT_LPF[1].exr_lpf_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(3), Q => p_3_out(2), R => '0' ); \EXT_LPF[2].exr_lpf_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(2), Q => p_3_out(1), R => '0' ); \EXT_LPF[3].exr_lpf_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(1), Q => p_3_out(0), R => '0' ); POR_SRL_I: unisim.vcomponents.SRL16E generic map( INIT => X"FFFF" ) port map ( A0 => '1', A1 => '1', A2 => '1', A3 => '1', CE => '1', CLK => slowest_sync_clk, D => '0', Q => Q ); lpf_asr_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\, Q => lpf_asr, R => '0' ); lpf_exr_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\, Q => lpf_exr, R => '0' ); lpf_int0: unisim.vcomponents.LUT4 generic map( INIT => X"FFEF" ) port map ( I0 => Q, I1 => lpf_asr, I2 => dcm_locked, I3 => lpf_exr, O => \lpf_int0__0\ ); lpf_int_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \lpf_int0__0\, Q => lpf_int, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr is port ( MB_out : out STD_LOGIC; Bsr_out : out STD_LOGIC; Pr_out : out STD_LOGIC; \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : out STD_LOGIC; \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : out STD_LOGIC; lpf_int : in STD_LOGIC; slowest_sync_clk : in STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr is signal \^bsr_out\ : STD_LOGIC; signal Core_i_1_n_0 : STD_LOGIC; signal \^mb_out\ : STD_LOGIC; signal \^pr_out\ : STD_LOGIC; signal \bsr_dec_reg_n_0_[0]\ : STD_LOGIC; signal \bsr_dec_reg_n_0_[2]\ : STD_LOGIC; signal bsr_i_1_n_0 : STD_LOGIC; signal \core_dec[0]_i_1_n_0\ : STD_LOGIC; signal \core_dec[2]_i_1_n_0\ : STD_LOGIC; signal \core_dec_reg_n_0_[0]\ : STD_LOGIC; signal \core_dec_reg_n_0_[1]\ : STD_LOGIC; signal from_sys_i_1_n_0 : STD_LOGIC; signal p_0_in : STD_LOGIC; signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 ); signal p_5_out : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \pr_dec0__0\ : STD_LOGIC; signal \pr_dec_reg_n_0_[0]\ : STD_LOGIC; signal \pr_dec_reg_n_0_[2]\ : STD_LOGIC; signal pr_i_1_n_0 : STD_LOGIC; signal seq_clr : STD_LOGIC; signal seq_cnt : STD_LOGIC_VECTOR ( 5 downto 0 ); signal seq_cnt_en : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of Core_i_1 : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \bsr_dec[2]_i_1\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of bsr_i_1 : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \core_dec[0]_i_1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \core_dec[2]_i_1\ : label is "soft_lutpair6"; attribute SOFT_HLUTNM of from_sys_i_1 : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \pr_dec[0]_i_1\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of pr_i_1 : label is "soft_lutpair4"; begin Bsr_out <= \^bsr_out\; MB_out <= \^mb_out\; Pr_out <= \^pr_out\; \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^bsr_out\, O => \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ ); \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^pr_out\, O => \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ ); Core_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^mb_out\, I1 => p_0_in, O => Core_i_1_n_0 ); Core_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => '1', D => Core_i_1_n_0, Q => \^mb_out\, S => lpf_int ); SEQ_COUNTER: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n port map ( Q(5 downto 0) => seq_cnt(5 downto 0), seq_clr => seq_clr, seq_cnt_en => seq_cnt_en, slowest_sync_clk => slowest_sync_clk ); \bsr_dec[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0804" ) port map ( I0 => seq_cnt_en, I1 => seq_cnt(3), I2 => seq_cnt(5), I3 => seq_cnt(4), O => p_5_out(0) ); \bsr_dec[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \core_dec_reg_n_0_[1]\, I1 => \bsr_dec_reg_n_0_[0]\, O => p_5_out(2) ); \bsr_dec_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_5_out(0), Q => \bsr_dec_reg_n_0_[0]\, R => '0' ); \bsr_dec_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_5_out(2), Q => \bsr_dec_reg_n_0_[2]\, R => '0' ); bsr_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^bsr_out\, I1 => \bsr_dec_reg_n_0_[2]\, O => bsr_i_1_n_0 ); bsr_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => '1', D => bsr_i_1_n_0, Q => \^bsr_out\, S => lpf_int ); \core_dec[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"8040" ) port map ( I0 => seq_cnt(4), I1 => seq_cnt(3), I2 => seq_cnt(5), I3 => seq_cnt_en, O => \core_dec[0]_i_1_n_0\ ); \core_dec[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \core_dec_reg_n_0_[1]\, I1 => \core_dec_reg_n_0_[0]\, O => \core_dec[2]_i_1_n_0\ ); \core_dec_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \core_dec[0]_i_1_n_0\, Q => \core_dec_reg_n_0_[0]\, R => '0' ); \core_dec_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \pr_dec0__0\, Q => \core_dec_reg_n_0_[1]\, R => '0' ); \core_dec_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => \core_dec[2]_i_1_n_0\, Q => p_0_in, R => '0' ); from_sys_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^mb_out\, I1 => seq_cnt_en, O => from_sys_i_1_n_0 ); from_sys_reg: unisim.vcomponents.FDSE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => from_sys_i_1_n_0, Q => seq_cnt_en, S => lpf_int ); pr_dec0: unisim.vcomponents.LUT4 generic map( INIT => X"0210" ) port map ( I0 => seq_cnt(0), I1 => seq_cnt(1), I2 => seq_cnt(2), I3 => seq_cnt_en, O => \pr_dec0__0\ ); \pr_dec[0]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"1080" ) port map ( I0 => seq_cnt_en, I1 => seq_cnt(5), I2 => seq_cnt(3), I3 => seq_cnt(4), O => p_3_out(0) ); \pr_dec[2]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \core_dec_reg_n_0_[1]\, I1 => \pr_dec_reg_n_0_[0]\, O => p_3_out(2) ); \pr_dec_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(0), Q => \pr_dec_reg_n_0_[0]\, R => '0' ); \pr_dec_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => p_3_out(2), Q => \pr_dec_reg_n_0_[2]\, R => '0' ); pr_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => \^pr_out\, I1 => \pr_dec_reg_n_0_[2]\, O => pr_i_1_n_0 ); pr_reg: unisim.vcomponents.FDSE generic map( INIT => '1' ) port map ( C => slowest_sync_clk, CE => '1', D => pr_i_1_n_0, Q => \^pr_out\, S => lpf_int ); seq_clr_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => '1', Q => seq_clr, R => lpf_int ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset is port ( slowest_sync_clk : in STD_LOGIC; ext_reset_in : in STD_LOGIC; aux_reset_in : in STD_LOGIC; mb_debug_sys_rst : in STD_LOGIC; dcm_locked : in STD_LOGIC; mb_reset : out STD_LOGIC; bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute C_AUX_RESET_HIGH : string; attribute C_AUX_RESET_HIGH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "1'b0"; attribute C_AUX_RST_WIDTH : integer; attribute C_AUX_RST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 4; attribute C_EXT_RESET_HIGH : string; attribute C_EXT_RESET_HIGH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "1'b0"; attribute C_EXT_RST_WIDTH : integer; attribute C_EXT_RST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 4; attribute C_FAMILY : string; attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "zynq"; attribute C_NUM_BUS_RST : integer; attribute C_NUM_BUS_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1; attribute C_NUM_INTERCONNECT_ARESETN : integer; attribute C_NUM_INTERCONNECT_ARESETN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1; attribute C_NUM_PERP_ARESETN : integer; attribute C_NUM_PERP_ARESETN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1; attribute C_NUM_PERP_RST : integer; attribute C_NUM_PERP_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset is signal Bsr_out : STD_LOGIC; signal MB_out : STD_LOGIC; signal Pr_out : STD_LOGIC; signal SEQ_n_3 : STD_LOGIC; signal SEQ_n_4 : STD_LOGIC; signal lpf_int : STD_LOGIC; attribute box_type : string; attribute box_type of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : label is "PRIMITIVE"; attribute box_type of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : label is "PRIMITIVE"; attribute box_type of \BSR_OUT_DFF[0].FDRE_BSR\ : label is "PRIMITIVE"; attribute box_type of FDRE_inst : label is "PRIMITIVE"; attribute box_type of \PR_OUT_DFF[0].FDRE_PER\ : label is "PRIMITIVE"; attribute equivalent_register_removal : string; attribute equivalent_register_removal of bus_struct_reset : signal is "no"; attribute equivalent_register_removal of interconnect_aresetn : signal is "no"; attribute equivalent_register_removal of peripheral_aresetn : signal is "no"; attribute equivalent_register_removal of peripheral_reset : signal is "no"; begin \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => SEQ_n_3, Q => interconnect_aresetn(0), R => '0' ); \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => SEQ_n_4, Q => peripheral_aresetn(0), R => '0' ); \BSR_OUT_DFF[0].FDRE_BSR\: unisim.vcomponents.FDRE generic map( INIT => '1', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => Bsr_out, Q => bus_struct_reset(0), R => '0' ); EXT_LPF: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf port map ( aux_reset_in => aux_reset_in, dcm_locked => dcm_locked, ext_reset_in => ext_reset_in, lpf_int => lpf_int, mb_debug_sys_rst => mb_debug_sys_rst, slowest_sync_clk => slowest_sync_clk ); FDRE_inst: unisim.vcomponents.FDRE generic map( INIT => '1', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => MB_out, Q => mb_reset, R => '0' ); \PR_OUT_DFF[0].FDRE_PER\: unisim.vcomponents.FDRE generic map( INIT => '1', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => slowest_sync_clk, CE => '1', D => Pr_out, Q => peripheral_reset(0), R => '0' ); SEQ: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr port map ( \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ => SEQ_n_3, \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ => SEQ_n_4, Bsr_out => Bsr_out, MB_out => MB_out, Pr_out => Pr_out, lpf_int => lpf_int, slowest_sync_clk => slowest_sync_clk ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is port ( slowest_sync_clk : in STD_LOGIC; ext_reset_in : in STD_LOGIC; aux_reset_in : in STD_LOGIC; mb_debug_sys_rst : in STD_LOGIC; dcm_locked : in STD_LOGIC; mb_reset : out STD_LOGIC; bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 ); interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ); peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "led_controller_design_rst_ps7_0_100M_0,proc_sys_reset,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; attribute x_core_info : string; attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "proc_sys_reset,Vivado 2017.3"; end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is attribute C_AUX_RESET_HIGH : string; attribute C_AUX_RESET_HIGH of U0 : label is "1'b0"; attribute C_AUX_RST_WIDTH : integer; attribute C_AUX_RST_WIDTH of U0 : label is 4; attribute C_EXT_RESET_HIGH : string; attribute C_EXT_RESET_HIGH of U0 : label is "1'b0"; attribute C_EXT_RST_WIDTH : integer; attribute C_EXT_RST_WIDTH of U0 : label is 4; attribute C_FAMILY : string; attribute C_FAMILY of U0 : label is "zynq"; attribute C_NUM_BUS_RST : integer; attribute C_NUM_BUS_RST of U0 : label is 1; attribute C_NUM_INTERCONNECT_ARESETN : integer; attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1; attribute C_NUM_PERP_ARESETN : integer; attribute C_NUM_PERP_ARESETN of U0 : label is 1; attribute C_NUM_PERP_RST : integer; attribute C_NUM_PERP_RST of U0 : label is 1; attribute x_interface_info : string; attribute x_interface_info of aux_reset_in : signal is "xilinx.com:signal:reset:1.0 aux_reset RST"; attribute x_interface_parameter : string; attribute x_interface_parameter of aux_reset_in : signal is "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW"; attribute x_interface_info of ext_reset_in : signal is "xilinx.com:signal:reset:1.0 ext_reset RST"; attribute x_interface_parameter of ext_reset_in : signal is "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW"; attribute x_interface_info of mb_debug_sys_rst : signal is "xilinx.com:signal:reset:1.0 dbg_reset RST"; attribute x_interface_parameter of mb_debug_sys_rst : signal is "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH"; attribute x_interface_info of mb_reset : signal is "xilinx.com:signal:reset:1.0 mb_rst RST"; attribute x_interface_parameter of mb_reset : signal is "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR"; attribute x_interface_info of slowest_sync_clk : signal is "xilinx.com:signal:clock:1.0 clock CLK"; attribute x_interface_parameter of slowest_sync_clk : signal is "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN led_controller_design_processing_system7_0_0_FCLK_CLK0"; attribute x_interface_info of bus_struct_reset : signal is "xilinx.com:signal:reset:1.0 bus_struct_reset RST"; attribute x_interface_parameter of bus_struct_reset : signal is "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT"; attribute x_interface_info of interconnect_aresetn : signal is "xilinx.com:signal:reset:1.0 interconnect_low_rst RST"; attribute x_interface_parameter of interconnect_aresetn : signal is "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT"; attribute x_interface_info of peripheral_aresetn : signal is "xilinx.com:signal:reset:1.0 peripheral_low_rst RST"; attribute x_interface_parameter of peripheral_aresetn : signal is "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL"; attribute x_interface_info of peripheral_reset : signal is "xilinx.com:signal:reset:1.0 peripheral_high_rst RST"; attribute x_interface_parameter of peripheral_reset : signal is "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL"; begin U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset port map ( aux_reset_in => aux_reset_in, bus_struct_reset(0) => bus_struct_reset(0), dcm_locked => dcm_locked, ext_reset_in => ext_reset_in, interconnect_aresetn(0) => interconnect_aresetn(0), mb_debug_sys_rst => mb_debug_sys_rst, mb_reset => mb_reset, peripheral_aresetn(0) => peripheral_aresetn(0), peripheral_reset(0) => peripheral_reset(0), slowest_sync_clk => slowest_sync_clk ); end STRUCTURE;

mit

MarkBlanco/FPGA_Sandbox

RecComp/Lab3/ip_repo/zed_audio_ctrl/zed_audio_ctrl.srcs/sources_1/imports/i2s_audio/axi_lite_ipif.vhd

3

13994

------------------------------------------------------------------- -- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. -- -- -- -- This file contains confidential and proprietary information -- -- of Xilinx, Inc. and is protected under U.S. and -- -- international copyright and other intellectual property -- -- laws. -- -- -- -- DISCLAIMER -- -- This disclaimer is not a license and does not grant any -- -- rights to the materials distributed herewith. Except as -- -- otherwise provided in a valid license issued to you by -- -- Xilinx, and to the maximum extent permitted by applicable -- -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- -- (2) Xilinx shall not be liable (whether in contract or tort, -- -- including negligence, or under any other theory of -- -- liability) for any loss or damage of any kind or nature -- -- related to, arising under or in connection with these -- -- materials, including for any direct, or any indirect, -- -- special, incidental, or consequential loss or damage -- -- (including loss of data, profits, goodwill, or any type of -- -- loss or damage suffered as a result of any action brought -- -- by a third party) even if such damage or loss was -- -- reasonably foreseeable or Xilinx had been advised of the -- -- possibility of the same. -- -- -- -- CRITICAL APPLICATIONS -- -- Xilinx products are not designed or intended to be fail- -- -- safe, or for use in any application requiring fail-safe -- -- performance, such as life-support or safety devices or -- -- systems, Class III medical devices, nuclear facilities, -- -- applications related to the deployment of airbags, or any -- -- other applications that could lead to death, personal -- -- injury, or severe property or environmental damage -- -- (individually and collectively, "Critical -- -- Applications"). Customer assumes the sole risk and -- -- liability of any use of Xilinx products in Critical -- -- Applications, subject only to applicable laws and -- -- regulations governing limitations on product liability. -- -- -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- -- PART OF THIS FILE AT ALL TIMES. -- ------------------------------------------------------------------- -- ************************************************************************ -- ------------------------------------------------------------------------------- -- Filename: axi_lite_ipif.vhd -- Version: v1.01.a -- Description: This is the top level design file for the axi_lite_ipif -- function. It provides a standardized slave interface -- between the IP and the AXI. This version supports -- single read/write transfers only. It does not provide -- address pipelining or simultaneous read and write -- operations. ------------------------------------------------------------------------------- -- Structure: This section shows the hierarchical structure of axi_lite_ipif. -- -- --axi_lite_ipif.vhd -- --slave_attachment.vhd -- --address_decoder.vhd ------------------------------------------------------------------------------- -- Author: BSB -- -- History: -- -- BSB 05/20/10 -- First version -- ~~~~~~ -- - Created the first version v1.00.a -- ^^^^^^ -- ~~~~~~ -- SK 06/09/10 -- v1.01.a -- 1. updated to reduce the utilization -- Closed CR #574507 -- 2. Optimized the state machine code -- 3. Optimized the address decoder logic to generate the CE's with common logic -- 4. Address GAP decoding logic is removed and timeout counter is made active -- for all transactions. -- ^^^^^^ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_cmb" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; use work.common_types.all; ------------------------------------------------------------------------------- -- Definition of Generics ------------------------------------------------------------------------------- -- C_S_AXI_DATA_WIDTH -- AXI data bus width -- C_S_AXI_ADDR_WIDTH -- AXI address bus width -- C_S_AXI_MIN_SIZE -- Minimum address range of the IP -- C_USE_WSTRB -- Use write strobs or not -- C_DPHASE_TIMEOUT -- Data phase time out counter -- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range -- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range -- C_FAMILY -- Target FPGA family ------------------------------------------------------------------------------- -- Definition of Ports ------------------------------------------------------------------------------- -- S_AXI_ACLK -- AXI Clock -- S_AXI_ARESETN -- AXI Reset -- S_AXI_AWADDR -- AXI Write address -- S_AXI_AWVALID -- Write address valid -- S_AXI_AWREADY -- Write address ready -- S_AXI_WDATA -- Write data -- S_AXI_WSTRB -- Write strobes -- S_AXI_WVALID -- Write valid -- S_AXI_WREADY -- Write ready -- S_AXI_BRESP -- Write response -- S_AXI_BVALID -- Write response valid -- S_AXI_BREADY -- Response ready -- S_AXI_ARADDR -- Read address -- S_AXI_ARVALID -- Read address valid -- S_AXI_ARREADY -- Read address ready -- S_AXI_RDATA -- Read data -- S_AXI_RRESP -- Read response -- S_AXI_RVALID -- Read valid -- S_AXI_RREADY -- Read ready -- Bus2IP_Clk -- Synchronization clock provided to User IP -- Bus2IP_Reset -- Active high reset for use by the User IP -- Bus2IP_Addr -- Desired address of read or write operation -- Bus2IP_RNW -- Read or write indicator for the transaction -- Bus2IP_BE -- Byte enables for the data bus -- Bus2IP_CS -- Chip select for the transcations -- Bus2IP_RdCE -- Chip enables for the read -- Bus2IP_WrCE -- Chip enables for the write -- Bus2IP_Data -- Write data bus to the User IP -- IP2Bus_Data -- Input Read Data bus from the User IP -- IP2Bus_WrAck -- Active high Write Data qualifier from the IP -- IP2Bus_RdAck -- Active high Read Data qualifier from the IP -- IP2Bus_Error -- Error signal from the IP ------------------------------------------------------------------------------- entity axi_lite_ipif is generic ( C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32; C_S_AXI_ADDR_WIDTH : integer := 32; C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF"; C_USE_WSTRB : integer := 0; C_DPHASE_TIMEOUT : integer range 0 to 512 := 8; C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := -- not used ( X"0000_0000_7000_0000", -- IP user0 base address X"0000_0000_7000_00FF", -- IP user0 high address X"0000_0000_7000_0100", -- IP user1 base address X"0000_0000_7000_01FF" -- IP user1 high address ); C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := -- not used ( 4, -- User0 CE Number 12 -- User1 CE Number ); C_FAMILY : string := "virtex6" ); port ( --System signals S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; S_AXI_AWADDR : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_AWREADY : out std_logic; S_AXI_WDATA : in std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_WSTRB : in std_logic_vector ((C_S_AXI_DATA_WIDTH/8)-1 downto 0); S_AXI_WVALID : in std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector (C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_RREADY : in std_logic; -- Controls to the IP/IPIF modules Bus2IP_Clk : out std_logic; Bus2IP_Resetn : out std_logic; Bus2IP_Addr : out std_logic_vector ((C_S_AXI_ADDR_WIDTH-1) downto 0); Bus2IP_RNW : out std_logic; Bus2IP_BE : out std_logic_vector (((C_S_AXI_DATA_WIDTH/8)-1) downto 0); Bus2IP_CS : out std_logic_vector (((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1) downto 0); Bus2IP_RdCE : out std_logic_vector ((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0); Bus2IP_WrCE : out std_logic_vector ((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0); Bus2IP_Data : out std_logic_vector ((C_S_AXI_DATA_WIDTH-1) downto 0); IP2Bus_Data : in std_logic_vector ((C_S_AXI_DATA_WIDTH-1) downto 0); IP2Bus_WrAck : in std_logic; IP2Bus_RdAck : in std_logic; IP2Bus_Error : in std_logic ); end axi_lite_ipif; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture imp of axi_lite_ipif is ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin ------------------------------------------------------------------------------- -- Slave Attachment ------------------------------------------------------------------------------- I_SLAVE_ATTACHMENT: entity work.slave_attachment generic map( C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY, C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY, C_IPIF_ABUS_WIDTH => C_S_AXI_ADDR_WIDTH, C_IPIF_DBUS_WIDTH => C_S_AXI_DATA_WIDTH, C_USE_WSTRB => C_USE_WSTRB, C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT, C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE, C_FAMILY => C_FAMILY ) port map( -- AXI signals S_AXI_ACLK => S_AXI_ACLK, S_AXI_ARESETN => S_AXI_ARESETN, S_AXI_AWADDR => S_AXI_AWADDR, S_AXI_AWVALID => S_AXI_AWVALID, S_AXI_AWREADY => S_AXI_AWREADY, S_AXI_WDATA => S_AXI_WDATA, S_AXI_WSTRB => S_AXI_WSTRB, S_AXI_WVALID => S_AXI_WVALID, S_AXI_WREADY => S_AXI_WREADY, S_AXI_BRESP => S_AXI_BRESP, S_AXI_BVALID => S_AXI_BVALID, S_AXI_BREADY => S_AXI_BREADY, S_AXI_ARADDR => S_AXI_ARADDR, S_AXI_ARVALID => S_AXI_ARVALID, S_AXI_ARREADY => S_AXI_ARREADY, S_AXI_RDATA => S_AXI_RDATA, S_AXI_RRESP => S_AXI_RRESP, S_AXI_RVALID => S_AXI_RVALID, S_AXI_RREADY => S_AXI_RREADY, -- IPIC signals Bus2IP_Clk => Bus2IP_Clk, Bus2IP_Resetn => Bus2IP_Resetn, Bus2IP_Addr => Bus2IP_Addr, Bus2IP_RNW => Bus2IP_RNW, Bus2IP_BE => Bus2IP_BE, Bus2IP_CS => Bus2IP_CS, Bus2IP_RdCE => Bus2IP_RdCE, Bus2IP_WrCE => Bus2IP_WrCE, Bus2IP_Data => Bus2IP_Data, IP2Bus_Data => IP2Bus_Data, IP2Bus_WrAck => IP2Bus_WrAck, IP2Bus_RdAck => IP2Bus_RdAck, IP2Bus_Error => IP2Bus_Error ); end imp;

mit

MarkBlanco/FPGA_Sandbox

RecComp/Lab3/lab3_project.xpr/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_bram_ctrl_0_2/synth/design_1_axi_bram_ctrl_0_2.vhd

1

17300

-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:axi_bram_ctrl:4.0 -- IP Revision: 12 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY axi_bram_ctrl_v4_0_12; USE axi_bram_ctrl_v4_0_12.axi_bram_ctrl; ENTITY design_1_axi_bram_ctrl_0_2 IS PORT ( s_axi_aclk : IN STD_LOGIC; s_axi_aresetn : IN STD_LOGIC; s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awlock : IN STD_LOGIC; s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arlock : IN STD_LOGIC; s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; bram_rst_a : OUT STD_LOGIC; bram_clk_a : OUT STD_LOGIC; bram_en_a : OUT STD_LOGIC; bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); bram_addr_a : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0) ); END design_1_axi_bram_ctrl_0_2; ARCHITECTURE design_1_axi_bram_ctrl_0_2_arch OF design_1_axi_bram_ctrl_0_2 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_bram_ctrl_0_2_arch: ARCHITECTURE IS "yes"; COMPONENT axi_bram_ctrl IS GENERIC ( C_BRAM_INST_MODE : STRING; C_MEMORY_DEPTH : INTEGER; C_BRAM_ADDR_WIDTH : INTEGER; C_S_AXI_ADDR_WIDTH : INTEGER; C_S_AXI_DATA_WIDTH : INTEGER; C_S_AXI_ID_WIDTH : INTEGER; C_S_AXI_PROTOCOL : STRING; C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER; C_SINGLE_PORT_BRAM : INTEGER; C_FAMILY : STRING; C_SELECT_XPM : INTEGER; C_S_AXI_CTRL_ADDR_WIDTH : INTEGER; C_S_AXI_CTRL_DATA_WIDTH : INTEGER; C_ECC : INTEGER; C_ECC_TYPE : INTEGER; C_FAULT_INJECT : INTEGER; C_ECC_ONOFF_RESET_VALUE : INTEGER ); PORT ( s_axi_aclk : IN STD_LOGIC; s_axi_aresetn : IN STD_LOGIC; ecc_interrupt : OUT STD_LOGIC; ecc_ue : OUT STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awlock : IN STD_LOGIC; s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(12 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arlock : IN STD_LOGIC; s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; s_axi_ctrl_awvalid : IN STD_LOGIC; s_axi_ctrl_awready : OUT STD_LOGIC; s_axi_ctrl_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_ctrl_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_ctrl_wvalid : IN STD_LOGIC; s_axi_ctrl_wready : OUT STD_LOGIC; s_axi_ctrl_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_ctrl_bvalid : OUT STD_LOGIC; s_axi_ctrl_bready : IN STD_LOGIC; s_axi_ctrl_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_ctrl_arvalid : IN STD_LOGIC; s_axi_ctrl_arready : OUT STD_LOGIC; s_axi_ctrl_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_ctrl_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_ctrl_rvalid : OUT STD_LOGIC; s_axi_ctrl_rready : IN STD_LOGIC; bram_rst_a : OUT STD_LOGIC; bram_clk_a : OUT STD_LOGIC; bram_en_a : OUT STD_LOGIC; bram_we_a : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); bram_addr_a : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); bram_wrdata_a : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); bram_rddata_a : IN STD_LOGIC_VECTOR(31 DOWNTO 0); bram_rst_b : OUT STD_LOGIC; bram_clk_b : OUT STD_LOGIC; bram_en_b : OUT STD_LOGIC; bram_we_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); bram_addr_b : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); bram_wrdata_b : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); bram_rddata_b : IN STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT axi_bram_ctrl; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF design_1_axi_bram_ctrl_0_2_arch: ARCHITECTURE IS "axi_bram_ctrl,Vivado 2017.3"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_bram_ctrl_0_2_arch : ARCHITECTURE IS "design_1_axi_bram_ctrl_0_2,axi_bram_ctrl,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_bram_ctrl_0_2_arch: ARCHITECTURE IS "design_1_axi_bram_ctrl_0_2,axi_bram_ctrl,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_bram_ctrl,x_ipVersion=4.0,x_ipCoreRevision=12,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_BRAM_INST_MODE=EXTERNAL,C_MEMORY_DEPTH=2048,C_BRAM_ADDR_WIDTH=11,C_S_AXI_ADDR_WIDTH=13,C_S_AXI_DATA_WIDTH=32,C_S_AXI_ID_WIDTH=1,C_S_AXI_PROTOCOL=AXI4,C_S_AXI_SUPPORTS_NARROW_BURST=0,C_SINGLE_PORT_BRAM=1,C_FAMILY=zynq,C_SELECT_XPM=0,C_S_AXI_CTRL_ADDR_WIDTH=32,C_S_AXI_CTRL_DATA_WIDTH=32,C_ECC" & "=0,C_ECC_TYPE=0,C_FAULT_INJECT=0,C_ECC_ONOFF_RESET_VALUE=0}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_PARAMETER : STRING; ATTRIBUTE X_INTERFACE_INFO OF bram_rddata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT"; ATTRIBUTE X_INTERFACE_INFO OF bram_wrdata_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN"; ATTRIBUTE X_INTERFACE_INFO OF bram_addr_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR"; ATTRIBUTE X_INTERFACE_INFO OF bram_we_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE"; ATTRIBUTE X_INTERFACE_INFO OF bram_en_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN"; ATTRIBUTE X_INTERFACE_INFO OF bram_clk_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK"; ATTRIBUTE X_INTERFACE_PARAMETER OF bram_rst_a: SIGNAL IS "XIL_INTERFACENAME BRAM_PORTA, MASTER_TYPE BRAM_CTRL, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, READ_WRITE_MODE READ_WRITE"; ATTRIBUTE X_INTERFACE_INFO OF bram_rst_a: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RLAST"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARPROT"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARBURST"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARLEN"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WLAST"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWPROT"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlock: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWBURST"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWLEN"; ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_awaddr: SIGNAL IS "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 13, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR"; ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aresetn: SIGNAL IS "XIL_INTERFACENAME RSTIF, POLARITY ACTIVE_LOW"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 RSTIF RST"; ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_aclk: SIGNAL IS "XIL_INTERFACENAME CLKIF, ASSOCIATED_BUSIF S_AXI:S_AXI_CTRL, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLKIF CLK"; BEGIN U0 : axi_bram_ctrl GENERIC MAP ( C_BRAM_INST_MODE => "EXTERNAL", C_MEMORY_DEPTH => 2048, C_BRAM_ADDR_WIDTH => 11, C_S_AXI_ADDR_WIDTH => 13, C_S_AXI_DATA_WIDTH => 32, C_S_AXI_ID_WIDTH => 1, C_S_AXI_PROTOCOL => "AXI4", C_S_AXI_SUPPORTS_NARROW_BURST => 0, C_SINGLE_PORT_BRAM => 1, C_FAMILY => "zynq", C_SELECT_XPM => 0, C_S_AXI_CTRL_ADDR_WIDTH => 32, C_S_AXI_CTRL_DATA_WIDTH => 32, C_ECC => 0, C_ECC_TYPE => 0, C_FAULT_INJECT => 0, C_ECC_ONOFF_RESET_VALUE => 0 ) PORT MAP ( s_axi_aclk => s_axi_aclk, s_axi_aresetn => s_axi_aresetn, s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_awaddr => s_axi_awaddr, s_axi_awlen => s_axi_awlen, s_axi_awsize => s_axi_awsize, s_axi_awburst => s_axi_awburst, s_axi_awlock => s_axi_awlock, s_axi_awcache => s_axi_awcache, s_axi_awprot => s_axi_awprot, s_axi_awvalid => s_axi_awvalid, s_axi_awready => s_axi_awready, s_axi_wdata => s_axi_wdata, s_axi_wstrb => s_axi_wstrb, s_axi_wlast => s_axi_wlast, s_axi_wvalid => s_axi_wvalid, s_axi_wready => s_axi_wready, s_axi_bresp => s_axi_bresp, s_axi_bvalid => s_axi_bvalid, s_axi_bready => s_axi_bready, s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axi_araddr => s_axi_araddr, s_axi_arlen => s_axi_arlen, s_axi_arsize => s_axi_arsize, s_axi_arburst => s_axi_arburst, s_axi_arlock => s_axi_arlock, s_axi_arcache => s_axi_arcache, s_axi_arprot => s_axi_arprot, s_axi_arvalid => s_axi_arvalid, s_axi_arready => s_axi_arready, s_axi_rdata => s_axi_rdata, s_axi_rresp => s_axi_rresp, s_axi_rlast => s_axi_rlast, s_axi_rvalid => s_axi_rvalid, s_axi_rready => s_axi_rready, s_axi_ctrl_awvalid => '0', s_axi_ctrl_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_ctrl_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_ctrl_wvalid => '0', s_axi_ctrl_bready => '0', s_axi_ctrl_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_ctrl_arvalid => '0', s_axi_ctrl_rready => '0', bram_rst_a => bram_rst_a, bram_clk_a => bram_clk_a, bram_en_a => bram_en_a, bram_we_a => bram_we_a, bram_addr_a => bram_addr_a, bram_wrdata_a => bram_wrdata_a, bram_rddata_a => bram_rddata_a, bram_rddata_b => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)) ); END design_1_axi_bram_ctrl_0_2_arch;

mit

MarkBlanco/FPGA_Sandbox

RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_processing_system7_0_0/ip_design_processing_system7_0_0_stub.vhdl

1

5959

-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017 -- Date : Wed Oct 18 15:15:21 2017 -- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS -- Command : write_vhdl -force -mode synth_stub -- /home/mark/Documents/Repos/FPGA_Sandbox/RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_processing_system7_0_0/ip_design_processing_system7_0_0_stub.vhdl -- Design : ip_design_processing_system7_0_0 -- Purpose : Stub declaration of top-level module interface -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity ip_design_processing_system7_0_0 is Port ( I2C0_SDA_I : in STD_LOGIC; I2C0_SDA_O : out STD_LOGIC; I2C0_SDA_T : out STD_LOGIC; I2C0_SCL_I : in STD_LOGIC; I2C0_SCL_O : out STD_LOGIC; I2C0_SCL_T : out STD_LOGIC; TTC0_WAVE0_OUT : out STD_LOGIC; TTC0_WAVE1_OUT : out STD_LOGIC; TTC0_WAVE2_OUT : out STD_LOGIC; USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); USB0_VBUS_PWRSELECT : out STD_LOGIC; USB0_VBUS_PWRFAULT : in STD_LOGIC; M_AXI_GP0_ARVALID : out STD_LOGIC; M_AXI_GP0_AWVALID : out STD_LOGIC; M_AXI_GP0_BREADY : out STD_LOGIC; M_AXI_GP0_RREADY : out STD_LOGIC; M_AXI_GP0_WLAST : out STD_LOGIC; M_AXI_GP0_WVALID : out STD_LOGIC; M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ACLK : in STD_LOGIC; M_AXI_GP0_ARREADY : in STD_LOGIC; M_AXI_GP0_AWREADY : in STD_LOGIC; M_AXI_GP0_BVALID : in STD_LOGIC; M_AXI_GP0_RLAST : in STD_LOGIC; M_AXI_GP0_RVALID : in STD_LOGIC; M_AXI_GP0_WREADY : in STD_LOGIC; M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); FCLK_CLK0 : out STD_LOGIC; FCLK_CLK1 : out STD_LOGIC; FCLK_RESET0_N : out STD_LOGIC; MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 ); DDR_CAS_n : inout STD_LOGIC; DDR_CKE : inout STD_LOGIC; DDR_Clk_n : inout STD_LOGIC; DDR_Clk : inout STD_LOGIC; DDR_CS_n : inout STD_LOGIC; DDR_DRSTB : inout STD_LOGIC; DDR_ODT : inout STD_LOGIC; DDR_RAS_n : inout STD_LOGIC; DDR_WEB : inout STD_LOGIC; DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_VRN : inout STD_LOGIC; DDR_VRP : inout STD_LOGIC; DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 ); PS_SRSTB : inout STD_LOGIC; PS_CLK : inout STD_LOGIC; PS_PORB : inout STD_LOGIC ); end ip_design_processing_system7_0_0; architecture stub of ip_design_processing_system7_0_0 is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; attribute black_box_pad_pin of stub : architecture is "I2C0_SDA_I,I2C0_SDA_O,I2C0_SDA_T,I2C0_SCL_I,I2C0_SCL_O,I2C0_SCL_T,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_CLK1,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "processing_system7_v5_5_processing_system7,Vivado 2017.3"; begin end;

mit

khaledhassan/vhdl-examples

adder_tree/adder.vhd

1

2067

-- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net> -- This software is distributed under the terms of the MIT License shown below. -- -- Permission is hereby granted, free of charge, to any person obtaining a copy -- of this software and associated documentation files (the "Software"), to -- deal in the Software without restriction, including without limitation the -- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or -- sell copies of the Software, and to permit persons to whom the Software is -- furnished to do so, subject to the following conditions: -- -- The above copyright notice and this permission notice shall be included in -- all copies or substantial portions of the Software. -- -- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -- IN THE SOFTWARE. -- Implements an adder of variable width with carry signals. library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity adder is generic ( WIDTH : positive := 8 ); port ( input1 : in std_logic_vector(WIDTH-1 downto 0); input2 : in std_logic_vector(WIDTH-1 downto 0); c_in : in std_logic; output : out std_logic_vector(WIDTH-1 downto 0); c_out : out std_logic ); end; architecture BHV of adder is signal full_sum : std_logic_vector(WIDTH downto 0); signal c_in_vec : std_logic_vector(0 downto 0); begin c_in_vec(0) <= c_in; full_sum <= std_logic_vector( resize(unsigned(input1), WIDTH+1) + resize(unsigned(input2), WIDTH+1) + resize(unsigned(c_in_vec), WIDTH+1) ); output <= full_sum(WIDTH-1 downto 0); c_out <= full_sum(WIDTH); end BHV;

mit

MarkBlanco/FPGA_Sandbox

RecComp/Lab1/my_lab_1/my_lab_1.ip_user_files/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_gpio_1_0/sim/zqynq_lab_1_design_axi_gpio_1_0.vhd

1

9004

-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:axi_gpio:2.0 -- IP Revision: 15 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY axi_gpio_v2_0_15; USE axi_gpio_v2_0_15.axi_gpio; ENTITY zqynq_lab_1_design_axi_gpio_1_0 IS PORT ( s_axi_aclk : IN STD_LOGIC; s_axi_aresetn : IN STD_LOGIC; s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; ip2intc_irpt : OUT STD_LOGIC; gpio_io_i : IN STD_LOGIC_VECTOR(4 DOWNTO 0) ); END zqynq_lab_1_design_axi_gpio_1_0; ARCHITECTURE zqynq_lab_1_design_axi_gpio_1_0_arch OF zqynq_lab_1_design_axi_gpio_1_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF zqynq_lab_1_design_axi_gpio_1_0_arch: ARCHITECTURE IS "yes"; COMPONENT axi_gpio IS GENERIC ( C_FAMILY : STRING; C_S_AXI_ADDR_WIDTH : INTEGER; C_S_AXI_DATA_WIDTH : INTEGER; C_GPIO_WIDTH : INTEGER; C_GPIO2_WIDTH : INTEGER; C_ALL_INPUTS : INTEGER; C_ALL_INPUTS_2 : INTEGER; C_ALL_OUTPUTS : INTEGER; C_ALL_OUTPUTS_2 : INTEGER; C_INTERRUPT_PRESENT : INTEGER; C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0); C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0); C_IS_DUAL : INTEGER; C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) ); PORT ( s_axi_aclk : IN STD_LOGIC; s_axi_aresetn : IN STD_LOGIC; s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; ip2intc_irpt : OUT STD_LOGIC; gpio_io_i : IN STD_LOGIC_VECTOR(4 DOWNTO 0); gpio_io_o : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); gpio_io_t : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0); gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT axi_gpio; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY"; ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT"; ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I"; BEGIN U0 : axi_gpio GENERIC MAP ( C_FAMILY => "zynq", C_S_AXI_ADDR_WIDTH => 9, C_S_AXI_DATA_WIDTH => 32, C_GPIO_WIDTH => 5, C_GPIO2_WIDTH => 32, C_ALL_INPUTS => 1, C_ALL_INPUTS_2 => 0, C_ALL_OUTPUTS => 0, C_ALL_OUTPUTS_2 => 0, C_INTERRUPT_PRESENT => 1, C_DOUT_DEFAULT => X"00000000", C_TRI_DEFAULT => X"FFFFFFFF", C_IS_DUAL => 0, C_DOUT_DEFAULT_2 => X"00000000", C_TRI_DEFAULT_2 => X"FFFFFFFF" ) PORT MAP ( s_axi_aclk => s_axi_aclk, s_axi_aresetn => s_axi_aresetn, s_axi_awaddr => s_axi_awaddr, s_axi_awvalid => s_axi_awvalid, s_axi_awready => s_axi_awready, s_axi_wdata => s_axi_wdata, s_axi_wstrb => s_axi_wstrb, s_axi_wvalid => s_axi_wvalid, s_axi_wready => s_axi_wready, s_axi_bresp => s_axi_bresp, s_axi_bvalid => s_axi_bvalid, s_axi_bready => s_axi_bready, s_axi_araddr => s_axi_araddr, s_axi_arvalid => s_axi_arvalid, s_axi_arready => s_axi_arready, s_axi_rdata => s_axi_rdata, s_axi_rresp => s_axi_rresp, s_axi_rvalid => s_axi_rvalid, s_axi_rready => s_axi_rready, ip2intc_irpt => ip2intc_irpt, gpio_io_i => gpio_io_i, gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)) ); END zqynq_lab_1_design_axi_gpio_1_0_arch;

mit

dawsonjon/FPGA-TX

synthesis/cmod_a7_15/tx/serial_in.vhd

3

3303

-------------------------------------------------------------------------------- --- --- SERIAL INPUT --- --- :Author: Jonathan P Dawson --- :Date: 17/10/2013 --- :email: [email protected] --- :license: MIT --- :Copyright: Copyright (C) Jonathan P Dawson 2013 --- --- A Serial Input Component --- -------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; entity serial_input is generic( clock_frequency : integer; baud_rate : integer ); port( clk : in std_logic; rst : in std_logic; rx : in std_logic; out1 : out std_logic_vector(7 downto 0); out1_stb : out std_logic; out1_ack : in std_logic ); end entity serial_input; architecture rtl of serial_input is component fifo is generic( width : integer; depth : integer ); port( clk : in std_logic; rst : in std_logic; input : in std_logic_vector(width-1 downto 0); input_stb : in std_logic; input_ack : out std_logic; output : out std_logic_vector(width-1 downto 0); output_stb : out std_logic; output_ack : in std_logic ); end component fifo; constant bit_clocks : integer := integer(round(real(clock_frequency)/real(baud_rate)))-1; constant bit_clocks_1_5 : integer := integer(round(real(clock_frequency)/real(baud_rate) * 1.5))-1; signal bit_count : integer range 0 to 8; signal bit_spacing : integer range 0 to bit_clocks_1_5; type serial_in_state_type is (idle, get_byte, output_data, wait_done); signal state : serial_in_state_type; signal rx_d, rx_d2 : std_logic; signal data : std_logic_vector(8 downto 0); signal int_out1 : std_logic_vector(7 downto 0); signal int_out1_stb : std_logic; signal int_out1_ack : std_logic; begin fifo_1 : fifo generic map( width => 8, depth => 16384 ) port map( clk => clk, rst => rst, input => int_out1, input_stb => int_out1_stb, input_ack => int_out1_ack, output => out1, output_stb => out1_stb, output_ack => out1_ack ); process begin wait until rising_edge(clk); rx_d <= rx; rx_d2 <= rx_d; case state is when idle => if rx_d2 = '0' then state <= get_byte; bit_spacing <= bit_clocks_1_5; bit_count <= 8; end if; when get_byte => if bit_spacing = 0 then data <= rx_d2 & data(8 downto 1); if bit_count = 0 then int_out1_stb <= '1'; state <= output_data; else bit_spacing <= bit_clocks; bit_count <= bit_count - 1; end if; else bit_spacing <= bit_spacing - 1; end if; when output_data => if int_out1_ack = '1' then int_out1_stb <= '0'; state <= wait_done; end if; when wait_done => if rx_d2 = '1' then state <= idle; end if; when others => state <= idle; end case; if rst = '1' then state <= idle; int_out1_stb <= '0'; end if; end process; int_out1 <= data(7 downto 0); end architecture rtl;

mit

MarkBlanco/FPGA_Sandbox

RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ipshared/b19f/hdl/vhdl/lms_pcore.vhd

2

10165

-- ------------------------------------------------------------- -- -- File Name: hdl_prj\hdlsrc\lms\lms_pcore.vhd -- Created: 2015-06-19 16:39:46 -- -- Generated by MATLAB 8.5 and HDL Coder 3.6 -- -- -- ------------------------------------------------------------- -- Rate and Clocking Details -- ------------------------------------------------------------- -- Model base rate: -1 -- Target subsystem base rate: -1 -- -- ------------------------------------------------------------- -- ------------------------------------------------------------- -- -- Module: lms_pcore -- Source Path: lms_pcore -- Hierarchy Level: 0 -- -- ------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.numeric_std.ALL; ENTITY lms_pcore IS PORT( IPCORE_CLK : IN std_logic; -- ufix1 IPCORE_RESETN : IN std_logic; -- ufix1 AXI4_Lite_ACLK : IN std_logic; -- ufix1 AXI4_Lite_ARESETN : IN std_logic; -- ufix1 AXI4_Lite_AWADDR : IN std_logic_vector(15 DOWNTO 0); -- ufix16 AXI4_Lite_AWVALID : IN std_logic; -- ufix1 AXI4_Lite_WDATA : IN std_logic_vector(31 DOWNTO 0); -- ufix32 AXI4_Lite_WSTRB : IN std_logic_vector(3 DOWNTO 0); -- ufix4 AXI4_Lite_WVALID : IN std_logic; -- ufix1 AXI4_Lite_BREADY : IN std_logic; -- ufix1 AXI4_Lite_ARADDR : IN std_logic_vector(15 DOWNTO 0); -- ufix16 AXI4_Lite_ARVALID : IN std_logic; -- ufix1 AXI4_Lite_RREADY : IN std_logic; -- ufix1 AXI4_Lite_AWREADY : OUT std_logic; -- ufix1 AXI4_Lite_WREADY : OUT std_logic; -- ufix1 AXI4_Lite_BRESP : OUT std_logic_vector(1 DOWNTO 0); -- ufix2 AXI4_Lite_BVALID : OUT std_logic; -- ufix1 AXI4_Lite_ARREADY : OUT std_logic; -- ufix1 AXI4_Lite_RDATA : OUT std_logic_vector(31 DOWNTO 0); -- ufix32 AXI4_Lite_RRESP : OUT std_logic_vector(1 DOWNTO 0); -- ufix2 AXI4_Lite_RVALID : OUT std_logic -- ufix1 ); END lms_pcore; ARCHITECTURE rtl OF lms_pcore IS -- Component Declarations COMPONENT lms_pcore_dut PORT( clk : IN std_logic; -- ufix1 reset : IN std_logic; dut_enable : IN std_logic; -- ufix1 x_k : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14 d_k : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14 ce_out : OUT std_logic; -- ufix1 e_k : OUT std_logic_vector(15 DOWNTO 0) -- sfix16_En14 ); END COMPONENT; COMPONENT lms_pcore_cop PORT( clk : IN std_logic; -- ufix1 reset : IN std_logic; in_strobe : IN std_logic; -- ufix1 cop_enable : IN std_logic; -- ufix1 out_ready : OUT std_logic; -- ufix1 dut_enable : OUT std_logic; -- ufix1 reg_strobe : OUT std_logic -- ufix1 ); END COMPONENT; COMPONENT lms_pcore_axi_lite PORT( reset : IN std_logic; AXI4_Lite_ACLK : IN std_logic; -- ufix1 AXI4_Lite_ARESETN : IN std_logic; -- ufix1 AXI4_Lite_AWADDR : IN std_logic_vector(15 DOWNTO 0); -- ufix16 AXI4_Lite_AWVALID : IN std_logic; -- ufix1 AXI4_Lite_WDATA : IN std_logic_vector(31 DOWNTO 0); -- ufix32 AXI4_Lite_WSTRB : IN std_logic_vector(3 DOWNTO 0); -- ufix4 AXI4_Lite_WVALID : IN std_logic; -- ufix1 AXI4_Lite_BREADY : IN std_logic; -- ufix1 AXI4_Lite_ARADDR : IN std_logic_vector(15 DOWNTO 0); -- ufix16 AXI4_Lite_ARVALID : IN std_logic; -- ufix1 AXI4_Lite_RREADY : IN std_logic; -- ufix1 read_cop_out_ready : IN std_logic; -- ufix1 cop_reg_strobe : IN std_logic; -- ufix1 read_e_k : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14 AXI4_Lite_AWREADY : OUT std_logic; -- ufix1 AXI4_Lite_WREADY : OUT std_logic; -- ufix1 AXI4_Lite_BRESP : OUT std_logic_vector(1 DOWNTO 0); -- ufix2 AXI4_Lite_BVALID : OUT std_logic; -- ufix1 AXI4_Lite_ARREADY : OUT std_logic; -- ufix1 AXI4_Lite_RDATA : OUT std_logic_vector(31 DOWNTO 0); -- ufix32 AXI4_Lite_RRESP : OUT std_logic_vector(1 DOWNTO 0); -- ufix2 AXI4_Lite_RVALID : OUT std_logic; -- ufix1 write_axi_enable : OUT std_logic; -- ufix1 strobe_cop_in_strobe : OUT std_logic; -- ufix1 write_x_k : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14 write_d_k : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14 reset_internal : OUT std_logic -- ufix1 ); END COMPONENT; -- Component Configuration Statements FOR ALL : lms_pcore_dut USE ENTITY work.lms_pcore_dut(rtl); FOR ALL : lms_pcore_cop USE ENTITY work.lms_pcore_cop(rtl); FOR ALL : lms_pcore_axi_lite USE ENTITY work.lms_pcore_axi_lite(rtl); -- Signals SIGNAL reset : std_logic; SIGNAL reset_cm : std_logic; -- ufix1 SIGNAL cop_dut_enable : std_logic; -- ufix1 SIGNAL write_x_k : std_logic_vector(15 DOWNTO 0); -- ufix16 SIGNAL write_d_k : std_logic_vector(15 DOWNTO 0); -- ufix16 SIGNAL ce_out_sig : std_logic; -- ufix1 SIGNAL e_k_sig : std_logic_vector(15 DOWNTO 0); -- ufix16 SIGNAL reset_internal : std_logic; -- ufix1 SIGNAL strobe_cop_in_strobe : std_logic; -- ufix1 SIGNAL write_axi_enable : std_logic; -- ufix1 SIGNAL cop_out_ready : std_logic; -- ufix1 SIGNAL cop_reg_strobe : std_logic; -- ufix1 SIGNAL AXI4_Lite_BRESP_tmp : std_logic_vector(1 DOWNTO 0); -- ufix2 SIGNAL AXI4_Lite_RDATA_tmp : std_logic_vector(31 DOWNTO 0); -- ufix32 SIGNAL AXI4_Lite_RRESP_tmp : std_logic_vector(1 DOWNTO 0); -- ufix2 BEGIN u_lms_pcore_dut_inst : lms_pcore_dut PORT MAP( clk => IPCORE_CLK, -- ufix1 reset => reset, dut_enable => cop_dut_enable, -- ufix1 x_k => write_x_k, -- sfix16_En14 d_k => write_d_k, -- sfix16_En14 ce_out => ce_out_sig, -- ufix1 e_k => e_k_sig -- sfix16_En14 ); u_lms_pcore_cop_inst : lms_pcore_cop PORT MAP( clk => IPCORE_CLK, -- ufix1 reset => reset, in_strobe => strobe_cop_in_strobe, -- ufix1 cop_enable => write_axi_enable, -- ufix1 out_ready => cop_out_ready, -- ufix1 dut_enable => cop_dut_enable, -- ufix1 reg_strobe => cop_reg_strobe -- ufix1 ); u_lms_pcore_axi_lite_inst : lms_pcore_axi_lite PORT MAP( reset => reset, AXI4_Lite_ACLK => AXI4_Lite_ACLK, -- ufix1 AXI4_Lite_ARESETN => AXI4_Lite_ARESETN, -- ufix1 AXI4_Lite_AWADDR => AXI4_Lite_AWADDR, -- ufix16 AXI4_Lite_AWVALID => AXI4_Lite_AWVALID, -- ufix1 AXI4_Lite_WDATA => AXI4_Lite_WDATA, -- ufix32 AXI4_Lite_WSTRB => AXI4_Lite_WSTRB, -- ufix4 AXI4_Lite_WVALID => AXI4_Lite_WVALID, -- ufix1 AXI4_Lite_BREADY => AXI4_Lite_BREADY, -- ufix1 AXI4_Lite_ARADDR => AXI4_Lite_ARADDR, -- ufix16 AXI4_Lite_ARVALID => AXI4_Lite_ARVALID, -- ufix1 AXI4_Lite_RREADY => AXI4_Lite_RREADY, -- ufix1 read_cop_out_ready => cop_out_ready, -- ufix1 cop_reg_strobe => strobe_cop_in_strobe, -- ufix1 read_e_k => e_k_sig, -- sfix16_En14 AXI4_Lite_AWREADY => AXI4_Lite_AWREADY, -- ufix1 AXI4_Lite_WREADY => AXI4_Lite_WREADY, -- ufix1 AXI4_Lite_BRESP => AXI4_Lite_BRESP_tmp, -- ufix2 AXI4_Lite_BVALID => AXI4_Lite_BVALID, -- ufix1 AXI4_Lite_ARREADY => AXI4_Lite_ARREADY, -- ufix1 AXI4_Lite_RDATA => AXI4_Lite_RDATA_tmp, -- ufix32 AXI4_Lite_RRESP => AXI4_Lite_RRESP_tmp, -- ufix2 AXI4_Lite_RVALID => AXI4_Lite_RVALID, -- ufix1 write_axi_enable => write_axi_enable, -- ufix1 strobe_cop_in_strobe => strobe_cop_in_strobe, -- ufix1 write_x_k => write_x_k, -- sfix16_En14 write_d_k => write_d_k, -- sfix16_En14 reset_internal => reset_internal -- ufix1 ); reset_cm <= NOT IPCORE_RESETN; reset <= reset_cm OR reset_internal; AXI4_Lite_BRESP <= AXI4_Lite_BRESP_tmp; AXI4_Lite_RDATA <= AXI4_Lite_RDATA_tmp; AXI4_Lite_RRESP <= AXI4_Lite_RRESP_tmp; END rtl;

mit

MarkBlanco/FPGA_Sandbox

RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_bram_ctrl_0_0/zqynq_lab_1_design_axi_bram_ctrl_0_0_sim_netlist.vhdl

1

291825

-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017 -- Date : Sat Sep 23 13:25:27 2017 -- Host : DarkCube running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode funcsim -- c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_bram_ctrl_0_0/zqynq_lab_1_design_axi_bram_ctrl_0_0_sim_netlist.vhdl -- Design : zqynq_lab_1_design_axi_bram_ctrl_0_0 -- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or -- synthesized. This netlist cannot be used for SDF annotated simulation. -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zqynq_lab_1_design_axi_bram_ctrl_0_0_SRL_FIFO is port ( bvalid_cnt_inc : out STD_LOGIC; bid_gets_fifo_load_d1_reg : out STD_LOGIC; bid_gets_fifo_load : out STD_LOGIC; axi_wdata_full_cmb114_out : out STD_LOGIC; \axi_bid_int_reg[0]\ : out STD_LOGIC; s_axi_aresetn : in STD_LOGIC; s_axi_aclk : in STD_LOGIC; \bvalid_cnt_reg[2]\ : in STD_LOGIC; wr_addr_sm_cs : in STD_LOGIC; \bvalid_cnt_reg[2]_0\ : in STD_LOGIC; \GEN_AWREADY.axi_aresetn_d2_reg\ : in STD_LOGIC; axi_awaddr_full : in STD_LOGIC; bram_addr_ld_en : in STD_LOGIC; bid_gets_fifo_load_d1 : in STD_LOGIC; s_axi_bready : in STD_LOGIC; axi_bvalid_int_reg : in STD_LOGIC; bvalid_cnt : in STD_LOGIC_VECTOR ( 2 downto 0 ); \bvalid_cnt_reg[1]\ : in STD_LOGIC; aw_active : in STD_LOGIC; s_axi_awready : in STD_LOGIC; s_axi_awvalid : in STD_LOGIC; curr_awlen_reg_1_or_2 : in STD_LOGIC; axi_awlen_pipe_1_or_2 : in STD_LOGIC; \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ : in STD_LOGIC; last_data_ack_mod : in STD_LOGIC; axi_awid_pipe : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 ); \out\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); axi_wr_burst : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wlast : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_bram_ctrl_0_0_SRL_FIFO : entity is "SRL_FIFO"; end zqynq_lab_1_design_axi_bram_ctrl_0_0_SRL_FIFO; architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0_SRL_FIFO is signal \Addr_Counters[0].FDRE_I_n_0\ : STD_LOGIC; signal \Addr_Counters[1].FDRE_I_n_0\ : STD_LOGIC; signal \Addr_Counters[2].FDRE_I_n_0\ : STD_LOGIC; signal \Addr_Counters[3].FDRE_I_n_0\ : STD_LOGIC; signal \Addr_Counters[3].XORCY_I_i_1_n_0\ : STD_LOGIC; signal CI : STD_LOGIC; signal D : STD_LOGIC; signal Data_Exists_DFF_i_2_n_0 : STD_LOGIC; signal Data_Exists_DFF_i_3_n_0 : STD_LOGIC; signal S : STD_LOGIC; signal S0_out : STD_LOGIC; signal S1_out : STD_LOGIC; signal addr_cy_1 : STD_LOGIC; signal addr_cy_2 : STD_LOGIC; signal addr_cy_3 : STD_LOGIC; signal \axi_bid_int[0]_i_2_n_0\ : STD_LOGIC; signal axi_bvalid_int_i_4_n_0 : STD_LOGIC; signal axi_bvalid_int_i_5_n_0 : STD_LOGIC; signal axi_bvalid_int_i_6_n_0 : STD_LOGIC; signal \^axi_wdata_full_cmb114_out\ : STD_LOGIC; signal bid_fifo_ld : STD_LOGIC; signal bid_fifo_not_empty : STD_LOGIC; signal bid_fifo_rd : STD_LOGIC; signal \^bid_gets_fifo_load\ : STD_LOGIC; signal bid_gets_fifo_load_d1_i_3_n_0 : STD_LOGIC; signal \^bid_gets_fifo_load_d1_reg\ : STD_LOGIC; signal \^bvalid_cnt_inc\ : STD_LOGIC; signal sum_A_0 : STD_LOGIC; signal sum_A_1 : STD_LOGIC; signal sum_A_2 : STD_LOGIC; signal sum_A_3 : STD_LOGIC; signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 ); attribute BOX_TYPE : string; attribute BOX_TYPE of \Addr_Counters[0].FDRE_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM : string; attribute XILINX_LEGACY_PRIM of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "(MUXCY,XORCY)"; attribute XILINX_TRANSFORM_PINMAP : string; attribute XILINX_TRANSFORM_PINMAP of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "LO:O"; attribute BOX_TYPE of \Addr_Counters[1].FDRE_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \Addr_Counters[2].FDRE_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of \Addr_Counters[3].FDRE_I\ : label is "PRIMITIVE"; attribute BOX_TYPE of Data_Exists_DFF : label is "PRIMITIVE"; attribute XILINX_LEGACY_PRIM of Data_Exists_DFF : label is "FDR"; attribute BOX_TYPE of \FIFO_RAM[0].SRL16E_I\ : label is "PRIMITIVE"; attribute srl_bus_name : string; attribute srl_bus_name of \FIFO_RAM[0].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM "; attribute srl_name : string; attribute srl_name of \FIFO_RAM[0].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[0].SRL16E_I "; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of axi_bvalid_int_i_3 : label is "soft_lutpair44"; attribute SOFT_HLUTNM of bid_gets_fifo_load_d1_i_3 : label is "soft_lutpair44"; begin axi_wdata_full_cmb114_out <= \^axi_wdata_full_cmb114_out\; bid_gets_fifo_load <= \^bid_gets_fifo_load\; bid_gets_fifo_load_d1_reg <= \^bid_gets_fifo_load_d1_reg\; bvalid_cnt_inc <= \^bvalid_cnt_inc\; \Addr_Counters[0].FDRE_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => bid_fifo_not_empty, D => sum_A_3, Q => \Addr_Counters[0].FDRE_I_n_0\, R => s_axi_aresetn ); \Addr_Counters[0].MUXCY_L_I_CARRY4\: unisim.vcomponents.CARRY4 port map ( CI => '0', CO(3) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED\(3), CO(2) => addr_cy_1, CO(1) => addr_cy_2, CO(0) => addr_cy_3, CYINIT => CI, DI(3) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED\(3), DI(2) => \Addr_Counters[2].FDRE_I_n_0\, DI(1) => \Addr_Counters[1].FDRE_I_n_0\, DI(0) => \Addr_Counters[0].FDRE_I_n_0\, O(3) => sum_A_0, O(2) => sum_A_1, O(1) => sum_A_2, O(0) => sum_A_3, S(3) => \Addr_Counters[3].XORCY_I_i_1_n_0\, S(2) => S0_out, S(1) => S1_out, S(0) => S ); \Addr_Counters[0].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000FFFFFFFE0000" ) port map ( I0 => \Addr_Counters[1].FDRE_I_n_0\, I1 => \Addr_Counters[3].FDRE_I_n_0\, I2 => \Addr_Counters[2].FDRE_I_n_0\, I3 => bram_addr_ld_en, I4 => \axi_bid_int[0]_i_2_n_0\, I5 => \Addr_Counters[0].FDRE_I_n_0\, O => S ); \Addr_Counters[0].MUXCY_L_I_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"8AAAAAAAAAAAAAAA" ) port map ( I0 => bram_addr_ld_en, I1 => \axi_bid_int[0]_i_2_n_0\, I2 => \Addr_Counters[0].FDRE_I_n_0\, I3 => \Addr_Counters[1].FDRE_I_n_0\, I4 => \Addr_Counters[3].FDRE_I_n_0\, I5 => \Addr_Counters[2].FDRE_I_n_0\, O => CI ); \Addr_Counters[1].FDRE_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => bid_fifo_not_empty, D => sum_A_2, Q => \Addr_Counters[1].FDRE_I_n_0\, R => s_axi_aresetn ); \Addr_Counters[1].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000FFFFFFFE0000" ) port map ( I0 => \Addr_Counters[0].FDRE_I_n_0\, I1 => \Addr_Counters[3].FDRE_I_n_0\, I2 => \Addr_Counters[2].FDRE_I_n_0\, I3 => bram_addr_ld_en, I4 => \axi_bid_int[0]_i_2_n_0\, I5 => \Addr_Counters[1].FDRE_I_n_0\, O => S1_out ); \Addr_Counters[2].FDRE_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => bid_fifo_not_empty, D => sum_A_1, Q => \Addr_Counters[2].FDRE_I_n_0\, R => s_axi_aresetn ); \Addr_Counters[2].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000FFFFFFFE0000" ) port map ( I0 => \Addr_Counters[0].FDRE_I_n_0\, I1 => \Addr_Counters[1].FDRE_I_n_0\, I2 => \Addr_Counters[3].FDRE_I_n_0\, I3 => bram_addr_ld_en, I4 => \axi_bid_int[0]_i_2_n_0\, I5 => \Addr_Counters[2].FDRE_I_n_0\, O => S0_out ); \Addr_Counters[3].FDRE_I\: unisim.vcomponents.FDRE generic map( INIT => '0', IS_C_INVERTED => '0', IS_D_INVERTED => '0', IS_R_INVERTED => '0' ) port map ( C => s_axi_aclk, CE => bid_fifo_not_empty, D => sum_A_0, Q => \Addr_Counters[3].FDRE_I_n_0\, R => s_axi_aresetn ); \Addr_Counters[3].XORCY_I_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000FFFFFFFE0000" ) port map ( I0 => \Addr_Counters[0].FDRE_I_n_0\, I1 => \Addr_Counters[1].FDRE_I_n_0\, I2 => \Addr_Counters[2].FDRE_I_n_0\, I3 => bram_addr_ld_en, I4 => \axi_bid_int[0]_i_2_n_0\, I5 => \Addr_Counters[3].FDRE_I_n_0\, O => \Addr_Counters[3].XORCY_I_i_1_n_0\ ); Data_Exists_DFF: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => D, Q => bid_fifo_not_empty, R => s_axi_aresetn ); Data_Exists_DFF_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"FE0A" ) port map ( I0 => bram_addr_ld_en, I1 => Data_Exists_DFF_i_2_n_0, I2 => Data_Exists_DFF_i_3_n_0, I3 => bid_fifo_not_empty, O => D ); Data_Exists_DFF_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"000000000000FFFD" ) port map ( I0 => \^bvalid_cnt_inc\, I1 => bvalid_cnt(2), I2 => bvalid_cnt(0), I3 => bvalid_cnt(1), I4 => \^bid_gets_fifo_load_d1_reg\, I5 => bid_gets_fifo_load_d1, O => Data_Exists_DFF_i_2_n_0 ); Data_Exists_DFF_i_3: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => \Addr_Counters[0].FDRE_I_n_0\, I1 => \Addr_Counters[1].FDRE_I_n_0\, I2 => \Addr_Counters[3].FDRE_I_n_0\, I3 => \Addr_Counters[2].FDRE_I_n_0\, O => Data_Exists_DFF_i_3_n_0 ); \FIFO_RAM[0].SRL16E_I\: unisim.vcomponents.SRL16E generic map( INIT => X"0000", IS_CLK_INVERTED => '0' ) port map ( A0 => \Addr_Counters[0].FDRE_I_n_0\, A1 => \Addr_Counters[1].FDRE_I_n_0\, A2 => \Addr_Counters[2].FDRE_I_n_0\, A3 => \Addr_Counters[3].FDRE_I_n_0\, CE => CI, CLK => s_axi_aclk, D => bid_fifo_ld, Q => bid_fifo_rd ); \FIFO_RAM[0].SRL16E_I_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axi_awid_pipe, I1 => axi_awaddr_full, I2 => s_axi_awid(0), O => bid_fifo_ld ); \axi_bid_int[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"ACAFACA0" ) port map ( I0 => bid_fifo_ld, I1 => bid_fifo_rd, I2 => \^bid_gets_fifo_load\, I3 => \axi_bid_int[0]_i_2_n_0\, I4 => s_axi_bid(0), O => \axi_bid_int_reg[0]\ ); \axi_bid_int[0]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"A888AAAAA8888888" ) port map ( I0 => bid_fifo_not_empty, I1 => bid_gets_fifo_load_d1, I2 => s_axi_bready, I3 => axi_bvalid_int_reg, I4 => bid_gets_fifo_load_d1_i_3_n_0, I5 => \^bvalid_cnt_inc\, O => \axi_bid_int[0]_i_2_n_0\ ); axi_bvalid_int_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"000055FD00000000" ) port map ( I0 => \out\(2), I1 => \^axi_wdata_full_cmb114_out\, I2 => axi_bvalid_int_i_4_n_0, I3 => axi_wr_burst, I4 => \out\(1), I5 => axi_bvalid_int_i_5_n_0, O => \^bvalid_cnt_inc\ ); axi_bvalid_int_i_3: unisim.vcomponents.LUT5 generic map( INIT => X"FE000000" ) port map ( I0 => bvalid_cnt(1), I1 => bvalid_cnt(0), I2 => bvalid_cnt(2), I3 => axi_bvalid_int_reg, I4 => s_axi_bready, O => \^bid_gets_fifo_load_d1_reg\ ); axi_bvalid_int_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"1F11000000000000" ) port map ( I0 => axi_bvalid_int_i_6_n_0, I1 => \bvalid_cnt_reg[2]\, I2 => wr_addr_sm_cs, I3 => \bvalid_cnt_reg[2]_0\, I4 => \GEN_AWREADY.axi_aresetn_d2_reg\, I5 => axi_awaddr_full, O => axi_bvalid_int_i_4_n_0 ); axi_bvalid_int_i_5: unisim.vcomponents.LUT5 generic map( INIT => X"74446444" ) port map ( I0 => \out\(0), I1 => \out\(2), I2 => s_axi_wvalid, I3 => s_axi_wlast, I4 => \^axi_wdata_full_cmb114_out\, O => axi_bvalid_int_i_5_n_0 ); axi_bvalid_int_i_6: unisim.vcomponents.LUT5 generic map( INIT => X"FEFFFFFF" ) port map ( I0 => curr_awlen_reg_1_or_2, I1 => axi_awlen_pipe_1_or_2, I2 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\, I3 => axi_awaddr_full, I4 => last_data_ack_mod, O => axi_bvalid_int_i_6_n_0 ); axi_wready_int_mod_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"7F7F7F007F007F00" ) port map ( I0 => bvalid_cnt(1), I1 => bvalid_cnt(0), I2 => bvalid_cnt(2), I3 => aw_active, I4 => s_axi_awready, I5 => s_axi_awvalid, O => \^axi_wdata_full_cmb114_out\ ); bid_gets_fifo_load_d1_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"00000800AA00AA00" ) port map ( I0 => bram_addr_ld_en, I1 => \^bid_gets_fifo_load_d1_reg\, I2 => bid_fifo_not_empty, I3 => \^bvalid_cnt_inc\, I4 => \bvalid_cnt_reg[1]\, I5 => bid_gets_fifo_load_d1_i_3_n_0, O => \^bid_gets_fifo_load\ ); bid_gets_fifo_load_d1_i_3: unisim.vcomponents.LUT3 generic map( INIT => X"FE" ) port map ( I0 => bvalid_cnt(2), I1 => bvalid_cnt(0), I2 => bvalid_cnt(1), O => bid_gets_fifo_load_d1_i_3_n_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst is port ( SR : out STD_LOGIC_VECTOR ( 0 to 0 ); bram_addr_ld_en_mod : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 0 to 0 ); D : out STD_LOGIC_VECTOR ( 13 downto 0 ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ : out STD_LOGIC; bram_addr_ld_en : out STD_LOGIC; \save_init_bram_addr_ld_reg[15]_0\ : out STD_LOGIC; \save_init_bram_addr_ld_reg[15]_1\ : out STD_LOGIC; \save_init_bram_addr_ld_reg[15]_2\ : out STD_LOGIC; \wrap_burst_total_reg[0]_0\ : out STD_LOGIC; \wrap_burst_total_reg[2]_0\ : out STD_LOGIC; curr_fixed_burst_reg_reg : out STD_LOGIC; curr_wrap_burst_reg_reg : out STD_LOGIC; curr_fixed_burst_reg : in STD_LOGIC; bram_addr_inc : in STD_LOGIC; bram_addr_rst_cmb : in STD_LOGIC; s_axi_aresetn : in STD_LOGIC; \out\ : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_wvalid : in STD_LOGIC; bram_addr_a : in STD_LOGIC_VECTOR ( 9 downto 0 ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0\ : in STD_LOGIC; \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ : in STD_LOGIC; \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\ : in STD_LOGIC; axi_awaddr_full : in STD_LOGIC; s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 ); \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\ : in STD_LOGIC; \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\ : in STD_LOGIC; \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\ : in STD_LOGIC; \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\ : in STD_LOGIC; \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\ : in STD_LOGIC; \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\ : in STD_LOGIC; \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\ : in STD_LOGIC; \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\ : in STD_LOGIC; \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\ : in STD_LOGIC; \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\ : in STD_LOGIC; \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\ : in STD_LOGIC; \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\ : in STD_LOGIC; \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\ : in STD_LOGIC; \GEN_AWREADY.axi_aresetn_d2_reg\ : in STD_LOGIC; wr_addr_sm_cs : in STD_LOGIC; last_data_ack_mod : in STD_LOGIC; bvalid_cnt : in STD_LOGIC_VECTOR ( 2 downto 0 ); aw_active : in STD_LOGIC; s_axi_awvalid : in STD_LOGIC; \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ : in STD_LOGIC; axi_awlen_pipe_1_or_2 : in STD_LOGIC; curr_awlen_reg_1_or_2 : in STD_LOGIC; curr_wrap_burst_reg : in STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); axi_awsize_pipe : in STD_LOGIC_VECTOR ( 0 to 0 ); curr_fixed_burst : in STD_LOGIC; curr_wrap_burst : in STD_LOGIC; s_axi_aresetn_0 : in STD_LOGIC; s_axi_aclk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst : entity is "wrap_brst"; end zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst; architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst is signal \^d\ : STD_LOGIC_VECTOR ( 13 downto 0 ); signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\ : STD_LOGIC; signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\ : STD_LOGIC; signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0\ : STD_LOGIC; signal \^gen_dual_addr_cnt.bram_addr_int_reg[8]\ : STD_LOGIC; signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal bram_addr_ld : STD_LOGIC_VECTOR ( 9 downto 1 ); signal \^bram_addr_ld_en\ : STD_LOGIC; signal \^bram_addr_ld_en_mod\ : STD_LOGIC; signal save_init_bram_addr_ld : STD_LOGIC_VECTOR ( 15 downto 3 ); signal \save_init_bram_addr_ld[3]_i_2__0_n_0\ : STD_LOGIC; signal \save_init_bram_addr_ld[4]_i_2__0_n_0\ : STD_LOGIC; signal \save_init_bram_addr_ld[5]_i_2__0_n_0\ : STD_LOGIC; signal \^save_init_bram_addr_ld_reg[15]_0\ : STD_LOGIC; signal \^save_init_bram_addr_ld_reg[15]_1\ : STD_LOGIC; signal \^save_init_bram_addr_ld_reg[15]_2\ : STD_LOGIC; signal wrap_burst_total : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \wrap_burst_total[0]_i_1__0_n_0\ : STD_LOGIC; signal \wrap_burst_total[0]_i_2__0_n_0\ : STD_LOGIC; signal \wrap_burst_total[0]_i_4__0_n_0\ : STD_LOGIC; signal \wrap_burst_total[0]_i_5_n_0\ : STD_LOGIC; signal \wrap_burst_total[1]_i_1__0_n_0\ : STD_LOGIC; signal \wrap_burst_total[2]_i_1__0_n_0\ : STD_LOGIC; signal \wrap_burst_total[2]_i_2__0_n_0\ : STD_LOGIC; signal \^wrap_burst_total_reg[0]_0\ : STD_LOGIC; signal \^wrap_burst_total_reg[2]_0\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7\ : label is "soft_lutpair48"; attribute SOFT_HLUTNM of \curr_fixed_burst_reg_i_1__0\ : label is "soft_lutpair48"; attribute SOFT_HLUTNM of \save_init_bram_addr_ld[3]_i_2__0\ : label is "soft_lutpair49"; attribute SOFT_HLUTNM of \save_init_bram_addr_ld[4]_i_2__0\ : label is "soft_lutpair49"; attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_3__0\ : label is "soft_lutpair46"; attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_4__0\ : label is "soft_lutpair45"; attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_5\ : label is "soft_lutpair47"; attribute SOFT_HLUTNM of \wrap_burst_total[1]_i_1__0\ : label is "soft_lutpair45"; attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_2__0\ : label is "soft_lutpair46"; attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_3__0\ : label is "soft_lutpair47"; begin D(13 downto 0) <= \^d\(13 downto 0); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[8]\; SR(0) <= \^sr\(0); bram_addr_ld_en <= \^bram_addr_ld_en\; bram_addr_ld_en_mod <= \^bram_addr_ld_en_mod\; \save_init_bram_addr_ld_reg[15]_0\ <= \^save_init_bram_addr_ld_reg[15]_0\; \save_init_bram_addr_ld_reg[15]_1\ <= \^save_init_bram_addr_ld_reg[15]_1\; \save_init_bram_addr_ld_reg[15]_2\ <= \^save_init_bram_addr_ld_reg[15]_2\; \wrap_burst_total_reg[0]_0\ <= \^wrap_burst_total_reg[0]_0\; \wrap_burst_total_reg[2]_0\ <= \^wrap_burst_total_reg[2]_0\; \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"BB8BBBBB88B88888" ) port map ( I0 => bram_addr_ld(8), I1 => \^bram_addr_ld_en_mod\, I2 => bram_addr_a(6), I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\, I4 => bram_addr_a(7), I5 => bram_addr_a(8), O => \^d\(8) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAABAAAAAAAAAAAA" ) port map ( I0 => \^bram_addr_ld_en_mod\, I1 => curr_fixed_burst_reg, I2 => \out\(1), I3 => \out\(2), I4 => \out\(0), I5 => s_axi_wvalid, O => E(0) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"B88BB8B8" ) port map ( I0 => bram_addr_ld(9), I1 => \^bram_addr_ld_en_mod\, I2 => bram_addr_a(9), I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0\, I4 => bram_addr_a(8), O => \^d\(9) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => save_init_bram_addr_ld(12), I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\, I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\, I3 => axi_awaddr_full, I4 => s_axi_awaddr(10), O => \^d\(10) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[13]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => save_init_bram_addr_ld(13), I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\, I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\, I3 => axi_awaddr_full, I4 => s_axi_awaddr(11), O => \^d\(11) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[14]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => save_init_bram_addr_ld(14), I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\, I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\, I3 => axi_awaddr_full, I4 => s_axi_awaddr(12), O => \^d\(12) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"4500FFFF" ) port map ( I0 => \^bram_addr_ld_en_mod\, I1 => curr_fixed_burst_reg, I2 => bram_addr_inc, I3 => bram_addr_rst_cmb, I4 => s_axi_aresetn, O => \^sr\(0) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"AAABAAAAAAAAAAAA" ) port map ( I0 => \^bram_addr_ld_en\, I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\, I2 => \out\(1), I3 => \out\(2), I4 => \out\(0), I5 => s_axi_wvalid, O => \^bram_addr_ld_en_mod\ ); \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => save_init_bram_addr_ld(15), I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\, I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\, I3 => axi_awaddr_full, I4 => s_axi_awaddr(13), O => \^d\(13) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"55555555FFFFFFDF" ) port map ( I0 => curr_wrap_burst_reg, I1 => wrap_burst_total(1), I2 => wrap_burst_total(2), I3 => wrap_burst_total(0), I4 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\, I5 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0\, O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\ ); \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \^bram_addr_ld_en\, I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\, O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\ ); \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8\: unisim.vcomponents.LUT6 generic map( INIT => X"000000008F00C000" ) port map ( I0 => bram_addr_a(2), I1 => bram_addr_a(1), I2 => wrap_burst_total(1), I3 => bram_addr_a(0), I4 => wrap_burst_total(0), I5 => wrap_burst_total(2), O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0\ ); \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"B800B800B800FFFF" ) port map ( I0 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\, I1 => axi_awaddr_full, I2 => s_axi_awaddr(0), I3 => \^bram_addr_ld_en\, I4 => \^bram_addr_ld_en_mod\, I5 => bram_addr_a(0), O => \^d\(0) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"8BB8" ) port map ( I0 => bram_addr_ld(1), I1 => \^bram_addr_ld_en_mod\, I2 => bram_addr_a(1), I3 => bram_addr_a(0), O => \^d\(1) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"8BB8B8B8" ) port map ( I0 => bram_addr_ld(2), I1 => \^bram_addr_ld_en_mod\, I2 => bram_addr_a(2), I3 => bram_addr_a(0), I4 => bram_addr_a(1), O => \^d\(2) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"8BB8B8B8B8B8B8B8" ) port map ( I0 => bram_addr_ld(3), I1 => \^bram_addr_ld_en_mod\, I2 => bram_addr_a(3), I3 => bram_addr_a(2), I4 => bram_addr_a(0), I5 => bram_addr_a(1), O => \^d\(3) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[6]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"B88B" ) port map ( I0 => bram_addr_ld(4), I1 => \^bram_addr_ld_en_mod\, I2 => bram_addr_a(4), I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\, O => \^d\(4) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[7]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B88BB8B8" ) port map ( I0 => bram_addr_ld(5), I1 => \^bram_addr_ld_en_mod\, I2 => bram_addr_a(5), I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\, I4 => bram_addr_a(4), O => \^d\(5) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"B8B88BB8B8B8B8B8" ) port map ( I0 => bram_addr_ld(6), I1 => \^bram_addr_ld_en_mod\, I2 => bram_addr_a(6), I3 => bram_addr_a(4), I4 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\, I5 => bram_addr_a(5), O => \^d\(6) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_2__0\: unisim.vcomponents.LUT4 generic map( INIT => X"7FFF" ) port map ( I0 => bram_addr_a(1), I1 => bram_addr_a(0), I2 => bram_addr_a(2), I3 => bram_addr_a(3), O => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\ ); \GEN_DUAL_ADDR_CNT.bram_addr_int[9]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B88BB8B8" ) port map ( I0 => bram_addr_ld(7), I1 => \^bram_addr_ld_en_mod\, I2 => bram_addr_a(7), I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\, I4 => bram_addr_a(6), O => \^d\(7) ); \curr_fixed_burst_reg_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"00E2" ) port map ( I0 => curr_fixed_burst_reg, I1 => \^bram_addr_ld_en\, I2 => curr_fixed_burst, I3 => \^sr\(0), O => curr_fixed_burst_reg_reg ); \curr_wrap_burst_reg_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"00E2" ) port map ( I0 => curr_wrap_burst_reg, I1 => \^bram_addr_ld_en\, I2 => curr_wrap_burst, I3 => \^sr\(0), O => curr_wrap_burst_reg_reg ); \save_init_bram_addr_ld[10]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => save_init_bram_addr_ld(10), I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\, I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\, I3 => axi_awaddr_full, I4 => s_axi_awaddr(8), O => bram_addr_ld(8) ); \save_init_bram_addr_ld[11]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => save_init_bram_addr_ld(11), I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\, I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\, I3 => axi_awaddr_full, I4 => s_axi_awaddr(9), O => bram_addr_ld(9) ); \save_init_bram_addr_ld[15]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0808080808AA0808" ) port map ( I0 => \GEN_AWREADY.axi_aresetn_d2_reg\, I1 => \^save_init_bram_addr_ld_reg[15]_0\, I2 => wr_addr_sm_cs, I3 => \^save_init_bram_addr_ld_reg[15]_1\, I4 => last_data_ack_mod, I5 => \^save_init_bram_addr_ld_reg[15]_2\, O => \^bram_addr_ld_en\ ); \save_init_bram_addr_ld[15]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"007F007F007F0000" ) port map ( I0 => bvalid_cnt(2), I1 => bvalid_cnt(0), I2 => bvalid_cnt(1), I3 => aw_active, I4 => axi_awaddr_full, I5 => s_axi_awvalid, O => \^save_init_bram_addr_ld_reg[15]_0\ ); \save_init_bram_addr_ld[15]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"80" ) port map ( I0 => bvalid_cnt(2), I1 => bvalid_cnt(0), I2 => bvalid_cnt(1), O => \^save_init_bram_addr_ld_reg[15]_1\ ); \save_init_bram_addr_ld[15]_i_4\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFD" ) port map ( I0 => axi_awaddr_full, I1 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\, I2 => axi_awlen_pipe_1_or_2, I3 => curr_awlen_reg_1_or_2, O => \^save_init_bram_addr_ld_reg[15]_2\ ); \save_init_bram_addr_ld[3]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \save_init_bram_addr_ld[3]_i_2__0_n_0\, I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\, I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\, I3 => axi_awaddr_full, I4 => s_axi_awaddr(1), O => bram_addr_ld(1) ); \save_init_bram_addr_ld[3]_i_2__0\: unisim.vcomponents.LUT4 generic map( INIT => X"C80C" ) port map ( I0 => wrap_burst_total(0), I1 => save_init_bram_addr_ld(3), I2 => wrap_burst_total(1), I3 => wrap_burst_total(2), O => \save_init_bram_addr_ld[3]_i_2__0_n_0\ ); \save_init_bram_addr_ld[4]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \save_init_bram_addr_ld[4]_i_2__0_n_0\, I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\, I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\, I3 => axi_awaddr_full, I4 => s_axi_awaddr(2), O => bram_addr_ld(2) ); \save_init_bram_addr_ld[4]_i_2__0\: unisim.vcomponents.LUT4 generic map( INIT => X"A28A" ) port map ( I0 => save_init_bram_addr_ld(4), I1 => wrap_burst_total(0), I2 => wrap_burst_total(2), I3 => wrap_burst_total(1), O => \save_init_bram_addr_ld[4]_i_2__0_n_0\ ); \save_init_bram_addr_ld[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"8F808F8F8F808080" ) port map ( I0 => save_init_bram_addr_ld(5), I1 => \save_init_bram_addr_ld[5]_i_2__0_n_0\, I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\, I3 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\, I4 => axi_awaddr_full, I5 => s_axi_awaddr(3), O => bram_addr_ld(3) ); \save_init_bram_addr_ld[5]_i_2__0\: unisim.vcomponents.LUT3 generic map( INIT => X"FB" ) port map ( I0 => wrap_burst_total(0), I1 => wrap_burst_total(2), I2 => wrap_burst_total(1), O => \save_init_bram_addr_ld[5]_i_2__0_n_0\ ); \save_init_bram_addr_ld[6]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => save_init_bram_addr_ld(6), I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\, I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\, I3 => axi_awaddr_full, I4 => s_axi_awaddr(4), O => bram_addr_ld(4) ); \save_init_bram_addr_ld[7]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => save_init_bram_addr_ld(7), I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\, I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\, I3 => axi_awaddr_full, I4 => s_axi_awaddr(5), O => bram_addr_ld(5) ); \save_init_bram_addr_ld[8]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => save_init_bram_addr_ld(8), I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\, I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\, I3 => axi_awaddr_full, I4 => s_axi_awaddr(6), O => bram_addr_ld(6) ); \save_init_bram_addr_ld[9]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => save_init_bram_addr_ld(9), I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\, I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\, I3 => axi_awaddr_full, I4 => s_axi_awaddr(7), O => bram_addr_ld(7) ); \save_init_bram_addr_ld_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => bram_addr_ld(8), Q => save_init_bram_addr_ld(10), R => s_axi_aresetn_0 ); \save_init_bram_addr_ld_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => bram_addr_ld(9), Q => save_init_bram_addr_ld(11), R => s_axi_aresetn_0 ); \save_init_bram_addr_ld_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \^d\(10), Q => save_init_bram_addr_ld(12), R => s_axi_aresetn_0 ); \save_init_bram_addr_ld_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \^d\(11), Q => save_init_bram_addr_ld(13), R => s_axi_aresetn_0 ); \save_init_bram_addr_ld_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \^d\(12), Q => save_init_bram_addr_ld(14), R => s_axi_aresetn_0 ); \save_init_bram_addr_ld_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \^d\(13), Q => save_init_bram_addr_ld(15), R => s_axi_aresetn_0 ); \save_init_bram_addr_ld_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => bram_addr_ld(1), Q => save_init_bram_addr_ld(3), R => s_axi_aresetn_0 ); \save_init_bram_addr_ld_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => bram_addr_ld(2), Q => save_init_bram_addr_ld(4), R => s_axi_aresetn_0 ); \save_init_bram_addr_ld_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => bram_addr_ld(3), Q => save_init_bram_addr_ld(5), R => s_axi_aresetn_0 ); \save_init_bram_addr_ld_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => bram_addr_ld(4), Q => save_init_bram_addr_ld(6), R => s_axi_aresetn_0 ); \save_init_bram_addr_ld_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => bram_addr_ld(5), Q => save_init_bram_addr_ld(7), R => s_axi_aresetn_0 ); \save_init_bram_addr_ld_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => bram_addr_ld(6), Q => save_init_bram_addr_ld(8), R => s_axi_aresetn_0 ); \save_init_bram_addr_ld_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => bram_addr_ld(7), Q => save_init_bram_addr_ld(9), R => s_axi_aresetn_0 ); \wrap_burst_total[0]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"F909090900000000" ) port map ( I0 => \wrap_burst_total[0]_i_2__0_n_0\, I1 => \^wrap_burst_total_reg[0]_0\, I2 => \wrap_burst_total[0]_i_4__0_n_0\, I3 => Q(1), I4 => Q(2), I5 => \wrap_burst_total[0]_i_5_n_0\, O => \wrap_burst_total[0]_i_1__0_n_0\ ); \wrap_burst_total[0]_i_2__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => Q(2), I1 => axi_awaddr_full, I2 => s_axi_awlen(2), O => \wrap_burst_total[0]_i_2__0_n_0\ ); \wrap_burst_total[0]_i_3__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => Q(1), I1 => axi_awaddr_full, I2 => s_axi_awlen(1), O => \^wrap_burst_total_reg[0]_0\ ); \wrap_burst_total[0]_i_4__0\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => axi_awaddr_full, I1 => axi_awsize_pipe(0), O => \wrap_burst_total[0]_i_4__0_n_0\ ); \wrap_burst_total[0]_i_5\: unisim.vcomponents.LUT5 generic map( INIT => X"000ACC0A" ) port map ( I0 => s_axi_awlen(0), I1 => Q(0), I2 => s_axi_awlen(3), I3 => axi_awaddr_full, I4 => Q(3), O => \wrap_burst_total[0]_i_5_n_0\ ); \wrap_burst_total[1]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"000008F3" ) port map ( I0 => Q(2), I1 => axi_awaddr_full, I2 => axi_awsize_pipe(0), I3 => \^wrap_burst_total_reg[2]_0\, I4 => \wrap_burst_total[2]_i_2__0_n_0\, O => \wrap_burst_total[1]_i_1__0_n_0\ ); \wrap_burst_total[2]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"5000000044004400" ) port map ( I0 => \wrap_burst_total[2]_i_2__0_n_0\, I1 => s_axi_awlen(2), I2 => Q(2), I3 => \^wrap_burst_total_reg[2]_0\, I4 => axi_awsize_pipe(0), I5 => axi_awaddr_full, O => \wrap_burst_total[2]_i_1__0_n_0\ ); \wrap_burst_total[2]_i_2__0\: unisim.vcomponents.LUT5 generic map( INIT => X"335FFF5F" ) port map ( I0 => s_axi_awlen(1), I1 => Q(1), I2 => s_axi_awlen(0), I3 => axi_awaddr_full, I4 => Q(0), O => \wrap_burst_total[2]_i_2__0_n_0\ ); \wrap_burst_total[2]_i_3__0\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => Q(3), I1 => axi_awaddr_full, I2 => s_axi_awlen(3), O => \^wrap_burst_total_reg[2]_0\ ); \wrap_burst_total_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \wrap_burst_total[0]_i_1__0_n_0\, Q => wrap_burst_total(0), R => s_axi_aresetn_0 ); \wrap_burst_total_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \wrap_burst_total[1]_i_1__0_n_0\, Q => wrap_burst_total(1), R => s_axi_aresetn_0 ); \wrap_burst_total_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \wrap_burst_total[2]_i_1__0_n_0\, Q => wrap_burst_total(2), R => s_axi_aresetn_0 ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst_0 is port ( \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ : out STD_LOGIC; SR : out STD_LOGIC_VECTOR ( 0 to 0 ); \wrap_burst_total_reg[0]_0\ : out STD_LOGIC; \wrap_burst_total_reg[0]_1\ : out STD_LOGIC; \wrap_burst_total_reg[0]_2\ : out STD_LOGIC; \wrap_burst_total_reg[0]_3\ : out STD_LOGIC; E : out STD_LOGIC_VECTOR ( 1 downto 0 ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0\ : out STD_LOGIC; D : out STD_LOGIC_VECTOR ( 13 downto 0 ); bram_addr_ld_en : out STD_LOGIC; \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ : out STD_LOGIC; \rd_data_sm_cs_reg[1]\ : out STD_LOGIC; \save_init_bram_addr_ld_reg[15]_0\ : out STD_LOGIC; \save_init_bram_addr_ld_reg[15]_1\ : out STD_LOGIC; Q : in STD_LOGIC_VECTOR ( 3 downto 0 ); axi_rvalid_int_reg : in STD_LOGIC; s_axi_rready : in STD_LOGIC; end_brst_rd : in STD_LOGIC; brst_zero : in STD_LOGIC; s_axi_aresetn : in STD_LOGIC; \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 ); axi_arsize_pipe : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 ); axi_araddr_full : in STD_LOGIC; curr_fixed_burst_reg : in STD_LOGIC; s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 ); \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\ : in STD_LOGIC; \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 ); \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\ : in STD_LOGIC; \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\ : in STD_LOGIC; \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\ : in STD_LOGIC; \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\ : in STD_LOGIC; \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\ : in STD_LOGIC; \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\ : in STD_LOGIC; \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\ : in STD_LOGIC; \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\ : in STD_LOGIC; \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\ : in STD_LOGIC; \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ : in STD_LOGIC; \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\ : in STD_LOGIC; \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\ : in STD_LOGIC; \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\ : in STD_LOGIC; \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\ : in STD_LOGIC; \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\ : in STD_LOGIC; curr_wrap_burst_reg : in STD_LOGIC; axi_rd_burst_two_reg : in STD_LOGIC; axi_rd_burst : in STD_LOGIC; axi_aresetn_d2 : in STD_LOGIC; last_bram_addr : in STD_LOGIC; rd_addr_sm_cs : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC; no_ar_ack : in STD_LOGIC; pend_rd_op : in STD_LOGIC; ar_active : in STD_LOGIC; axi_b2b_brst : in STD_LOGIC; axi_arsize_pipe_max : in STD_LOGIC; disable_b2b_brst : in STD_LOGIC; \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\ : in STD_LOGIC; axi_arlen_pipe_1_or_2 : in STD_LOGIC; s_axi_aclk : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst_0 : entity is "wrap_brst"; end zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst_0; architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst_0 is signal \^d\ : STD_LOGIC_VECTOR ( 13 downto 0 ); signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0\ : STD_LOGIC; signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0\ : STD_LOGIC; signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\ : STD_LOGIC; signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\ : STD_LOGIC; signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0\ : STD_LOGIC; signal \^gen_dual_addr_cnt.bram_addr_int_reg[11]\ : STD_LOGIC; signal \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\ : STD_LOGIC; signal \^gen_dual_addr_cnt.bram_addr_int_reg[6]\ : STD_LOGIC; signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^bram_addr_ld_en\ : STD_LOGIC; signal \^rd_data_sm_cs_reg[1]\ : STD_LOGIC; signal \save_init_bram_addr_ld[10]_i_1__0_n_0\ : STD_LOGIC; signal \save_init_bram_addr_ld[11]_i_1__0_n_0\ : STD_LOGIC; signal \save_init_bram_addr_ld[15]_i_2__0_n_0\ : STD_LOGIC; signal \save_init_bram_addr_ld[15]_i_3__0_n_0\ : STD_LOGIC; signal \save_init_bram_addr_ld[3]_i_1__0_n_0\ : STD_LOGIC; signal \save_init_bram_addr_ld[3]_i_2_n_0\ : STD_LOGIC; signal \save_init_bram_addr_ld[4]_i_1__0_n_0\ : STD_LOGIC; signal \save_init_bram_addr_ld[4]_i_2_n_0\ : STD_LOGIC; signal \save_init_bram_addr_ld[5]_i_1__0_n_0\ : STD_LOGIC; signal \save_init_bram_addr_ld[5]_i_2_n_0\ : STD_LOGIC; signal \save_init_bram_addr_ld[6]_i_1__0_n_0\ : STD_LOGIC; signal \save_init_bram_addr_ld[7]_i_1__0_n_0\ : STD_LOGIC; signal \save_init_bram_addr_ld[8]_i_1__0_n_0\ : STD_LOGIC; signal \save_init_bram_addr_ld[9]_i_1__0_n_0\ : STD_LOGIC; signal \^save_init_bram_addr_ld_reg[15]_0\ : STD_LOGIC; signal \^save_init_bram_addr_ld_reg[15]_1\ : STD_LOGIC; signal \save_init_bram_addr_ld_reg_n_0_[10]\ : STD_LOGIC; signal \save_init_bram_addr_ld_reg_n_0_[11]\ : STD_LOGIC; signal \save_init_bram_addr_ld_reg_n_0_[12]\ : STD_LOGIC; signal \save_init_bram_addr_ld_reg_n_0_[13]\ : STD_LOGIC; signal \save_init_bram_addr_ld_reg_n_0_[14]\ : STD_LOGIC; signal \save_init_bram_addr_ld_reg_n_0_[15]\ : STD_LOGIC; signal \save_init_bram_addr_ld_reg_n_0_[3]\ : STD_LOGIC; signal \save_init_bram_addr_ld_reg_n_0_[4]\ : STD_LOGIC; signal \save_init_bram_addr_ld_reg_n_0_[5]\ : STD_LOGIC; signal \save_init_bram_addr_ld_reg_n_0_[6]\ : STD_LOGIC; signal \save_init_bram_addr_ld_reg_n_0_[7]\ : STD_LOGIC; signal \save_init_bram_addr_ld_reg_n_0_[8]\ : STD_LOGIC; signal \save_init_bram_addr_ld_reg_n_0_[9]\ : STD_LOGIC; signal \wrap_burst_total[0]_i_1_n_0\ : STD_LOGIC; signal \wrap_burst_total[0]_i_5__0_n_0\ : STD_LOGIC; signal \wrap_burst_total[1]_i_1_n_0\ : STD_LOGIC; signal \wrap_burst_total[2]_i_1_n_0\ : STD_LOGIC; signal \wrap_burst_total[2]_i_2_n_0\ : STD_LOGIC; signal \^wrap_burst_total_reg[0]_0\ : STD_LOGIC; signal \^wrap_burst_total_reg[0]_1\ : STD_LOGIC; signal \^wrap_burst_total_reg[0]_2\ : STD_LOGIC; signal \^wrap_burst_total_reg[0]_3\ : STD_LOGIC; signal \wrap_burst_total_reg_n_0_[0]\ : STD_LOGIC; signal \wrap_burst_total_reg_n_0_[1]\ : STD_LOGIC; signal \wrap_burst_total_reg_n_0_[2]\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_1\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1__0\ : label is "soft_lutpair1"; attribute SOFT_HLUTNM of \save_init_bram_addr_ld[15]_i_4__0\ : label is "soft_lutpair2"; attribute SOFT_HLUTNM of \save_init_bram_addr_ld[3]_i_2\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \save_init_bram_addr_ld[5]_i_2\ : label is "soft_lutpair3"; attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_2\ : label is "soft_lutpair4"; attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_3\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_4\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_5__0\ : label is "soft_lutpair5"; attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_2\ : label is "soft_lutpair0"; attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_3\ : label is "soft_lutpair4"; begin D(13 downto 0) <= \^d\(13 downto 0); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[11]\; \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\; \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[6]\; SR(0) <= \^sr\(0); bram_addr_ld_en <= \^bram_addr_ld_en\; \rd_data_sm_cs_reg[1]\ <= \^rd_data_sm_cs_reg[1]\; \save_init_bram_addr_ld_reg[15]_0\ <= \^save_init_bram_addr_ld_reg[15]_0\; \save_init_bram_addr_ld_reg[15]_1\ <= \^save_init_bram_addr_ld_reg[15]_1\; \wrap_burst_total_reg[0]_0\ <= \^wrap_burst_total_reg[0]_0\; \wrap_burst_total_reg[0]_1\ <= \^wrap_burst_total_reg[0]_1\; \wrap_burst_total_reg[0]_2\ <= \^wrap_burst_total_reg[0]_2\; \wrap_burst_total_reg[0]_3\ <= \^wrap_burst_total_reg[0]_3\; \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"DF20FFFFDF200000" ) port map ( I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(6), I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\, I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(7), I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(8), I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\, I5 => \save_init_bram_addr_ld[10]_i_1__0_n_0\, O => \^d\(8) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_1__0\: unisim.vcomponents.LUT3 generic map( INIT => X"5D" ) port map ( I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\, I1 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\, I2 => curr_fixed_burst_reg, O => E(0) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_2__0\: unisim.vcomponents.LUT5 generic map( INIT => X"9AFF9A00" ) port map ( I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(9), I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\, I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(8), I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\, I4 => \save_init_bram_addr_ld[11]_i_1__0_n_0\, O => \^d\(9) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"E0F0E0FFE0F0E0F0" ) port map ( I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0\, I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0\, I2 => \^rd_data_sm_cs_reg[1]\, I3 => Q(1), I4 => Q(3), I5 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\, O => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\ ); \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => axi_rd_burst_two_reg, I1 => Q(0), O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0\ ); \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6\: unisim.vcomponents.LUT6 generic map( INIT => X"0D00000000000000" ) port map ( I0 => end_brst_rd, I1 => axi_b2b_brst, I2 => brst_zero, I3 => axi_rvalid_int_reg, I4 => s_axi_rready, I5 => Q(0), O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0\ ); \GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \save_init_bram_addr_ld_reg_n_0_[12]\, I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\, I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\, I3 => axi_araddr_full, I4 => s_axi_araddr(10), O => \^d\(10) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[13]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \save_init_bram_addr_ld_reg_n_0_[13]\, I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\, I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\, I3 => axi_araddr_full, I4 => s_axi_araddr(11), O => \^d\(11) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[14]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \save_init_bram_addr_ld_reg_n_0_[14]\, I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\, I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\, I3 => axi_araddr_full, I4 => s_axi_araddr(12), O => \^d\(12) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\, O => E(1) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_2__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \save_init_bram_addr_ld_reg_n_0_[15]\, I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\, I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\, I3 => axi_araddr_full, I4 => s_axi_araddr(13), O => \^d\(13) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => \^bram_addr_ld_en\, I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\, O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\ ); \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0\: unisim.vcomponents.LUT5 generic map( INIT => X"88A80000" ) port map ( I0 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\, I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0\, I2 => \save_init_bram_addr_ld[5]_i_2_n_0\, I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\, I4 => curr_wrap_burst_reg, O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\ ); \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0\: unisim.vcomponents.LUT6 generic map( INIT => X"000000008F00A000" ) port map ( I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1), I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2), I2 => \wrap_burst_total_reg_n_0_[1]\, I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0), I4 => \wrap_burst_total_reg_n_0_[0]\, I5 => \wrap_burst_total_reg_n_0_[2]\, O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0\ ); \GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"00000000A808FD5D" ) port map ( I0 => \^bram_addr_ld_en\, I1 => s_axi_araddr(0), I2 => axi_araddr_full, I3 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\, I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0), I5 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\, O => \^d\(0) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[3]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"6F60" ) port map ( I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1), I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0), I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\, I3 => \save_init_bram_addr_ld[3]_i_1__0_n_0\, O => \^d\(1) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"6AFF6A00" ) port map ( I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2), I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0), I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1), I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\, I4 => \save_init_bram_addr_ld[4]_i_1__0_n_0\, O => \^d\(2) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[5]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"6AAAFFFF6AAA0000" ) port map ( I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(3), I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2), I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0), I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1), I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\, I5 => \save_init_bram_addr_ld[5]_i_1__0_n_0\, O => \^d\(3) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[6]_i_1__0\: unisim.vcomponents.LUT4 generic map( INIT => X"9F90" ) port map ( I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(4), I1 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\, I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\, I3 => \save_init_bram_addr_ld[6]_i_1__0_n_0\, O => \^d\(4) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[7]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"9AFF9A00" ) port map ( I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(5), I1 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\, I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(4), I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\, I4 => \save_init_bram_addr_ld[7]_i_1__0_n_0\, O => \^d\(5) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"A6AAFFFFA6AA0000" ) port map ( I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(6), I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(4), I2 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\, I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(5), I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\, I5 => \save_init_bram_addr_ld[8]_i_1__0_n_0\, O => \^d\(6) ); \GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"7FFF" ) port map ( I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1), I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0), I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2), I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(3), O => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\ ); \GEN_DUAL_ADDR_CNT.bram_addr_int[9]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"9AFF9A00" ) port map ( I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(7), I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\, I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(6), I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\, I4 => \save_init_bram_addr_ld[9]_i_1__0_n_0\, O => \^d\(7) ); bram_en_int_i_8: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000004000" ) port map ( I0 => Q(0), I1 => Q(2), I2 => axi_rvalid_int_reg, I3 => s_axi_rready, I4 => end_brst_rd, I5 => brst_zero, O => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\ ); bram_rst_b_INST_0: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => s_axi_aresetn, O => \^sr\(0) ); \rd_data_sm_cs[1]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"0302030203020300" ) port map ( I0 => Q(0), I1 => Q(3), I2 => Q(2), I3 => Q(1), I4 => axi_rd_burst_two_reg, I5 => axi_rd_burst, O => \^rd_data_sm_cs_reg[1]\ ); \save_init_bram_addr_ld[10]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \save_init_bram_addr_ld_reg_n_0_[10]\, I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\, I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\, I3 => axi_araddr_full, I4 => s_axi_araddr(8), O => \save_init_bram_addr_ld[10]_i_1__0_n_0\ ); \save_init_bram_addr_ld[11]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \save_init_bram_addr_ld_reg_n_0_[11]\, I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\, I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\, I3 => axi_araddr_full, I4 => s_axi_araddr(9), O => \save_init_bram_addr_ld[11]_i_1__0_n_0\ ); \save_init_bram_addr_ld[15]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"8888888A88888888" ) port map ( I0 => axi_aresetn_d2, I1 => \save_init_bram_addr_ld[15]_i_2__0_n_0\, I2 => \save_init_bram_addr_ld[15]_i_3__0_n_0\, I3 => \^save_init_bram_addr_ld_reg[15]_0\, I4 => \^save_init_bram_addr_ld_reg[15]_1\, I5 => last_bram_addr, O => \^bram_addr_ld_en\ ); \save_init_bram_addr_ld[15]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000054" ) port map ( I0 => rd_addr_sm_cs, I1 => axi_araddr_full, I2 => s_axi_arvalid, I3 => no_ar_ack, I4 => pend_rd_op, I5 => ar_active, O => \save_init_bram_addr_ld[15]_i_2__0_n_0\ ); \save_init_bram_addr_ld[15]_i_3__0\: unisim.vcomponents.LUT3 generic map( INIT => X"2A" ) port map ( I0 => brst_zero, I1 => s_axi_rready, I2 => axi_rvalid_int_reg, O => \save_init_bram_addr_ld[15]_i_3__0_n_0\ ); \save_init_bram_addr_ld[15]_i_4__0\: unisim.vcomponents.LUT4 generic map( INIT => X"0040" ) port map ( I0 => Q(3), I1 => Q(2), I2 => Q(1), I3 => Q(0), O => \^save_init_bram_addr_ld_reg[15]_0\ ); \save_init_bram_addr_ld[15]_i_5\: unisim.vcomponents.LUT5 generic map( INIT => X"FFFDFFFF" ) port map ( I0 => axi_arsize_pipe_max, I1 => disable_b2b_brst, I2 => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\, I3 => axi_arlen_pipe_1_or_2, I4 => axi_araddr_full, O => \^save_init_bram_addr_ld_reg[15]_1\ ); \save_init_bram_addr_ld[3]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \save_init_bram_addr_ld[3]_i_2_n_0\, I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\, I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\, I3 => axi_araddr_full, I4 => s_axi_araddr(1), O => \save_init_bram_addr_ld[3]_i_1__0_n_0\ ); \save_init_bram_addr_ld[3]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"A282" ) port map ( I0 => \save_init_bram_addr_ld_reg_n_0_[3]\, I1 => \wrap_burst_total_reg_n_0_[1]\, I2 => \wrap_burst_total_reg_n_0_[2]\, I3 => \wrap_burst_total_reg_n_0_[0]\, O => \save_init_bram_addr_ld[3]_i_2_n_0\ ); \save_init_bram_addr_ld[4]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \save_init_bram_addr_ld[4]_i_2_n_0\, I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\, I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\, I3 => axi_araddr_full, I4 => s_axi_araddr(2), O => \save_init_bram_addr_ld[4]_i_1__0_n_0\ ); \save_init_bram_addr_ld[4]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"A28A" ) port map ( I0 => \save_init_bram_addr_ld_reg_n_0_[4]\, I1 => \wrap_burst_total_reg_n_0_[0]\, I2 => \wrap_burst_total_reg_n_0_[2]\, I3 => \wrap_burst_total_reg_n_0_[1]\, O => \save_init_bram_addr_ld[4]_i_2_n_0\ ); \save_init_bram_addr_ld[5]_i_1__0\: unisim.vcomponents.LUT6 generic map( INIT => X"2F202F2F2F202020" ) port map ( I0 => \save_init_bram_addr_ld_reg_n_0_[5]\, I1 => \save_init_bram_addr_ld[5]_i_2_n_0\, I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\, I3 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\, I4 => axi_araddr_full, I5 => s_axi_araddr(3), O => \save_init_bram_addr_ld[5]_i_1__0_n_0\ ); \save_init_bram_addr_ld[5]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"04" ) port map ( I0 => \wrap_burst_total_reg_n_0_[0]\, I1 => \wrap_burst_total_reg_n_0_[2]\, I2 => \wrap_burst_total_reg_n_0_[1]\, O => \save_init_bram_addr_ld[5]_i_2_n_0\ ); \save_init_bram_addr_ld[6]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \save_init_bram_addr_ld_reg_n_0_[6]\, I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\, I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\, I3 => axi_araddr_full, I4 => s_axi_araddr(4), O => \save_init_bram_addr_ld[6]_i_1__0_n_0\ ); \save_init_bram_addr_ld[7]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \save_init_bram_addr_ld_reg_n_0_[7]\, I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\, I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\, I3 => axi_araddr_full, I4 => s_axi_araddr(5), O => \save_init_bram_addr_ld[7]_i_1__0_n_0\ ); \save_init_bram_addr_ld[8]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \save_init_bram_addr_ld_reg_n_0_[8]\, I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\, I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\, I3 => axi_araddr_full, I4 => s_axi_araddr(6), O => \save_init_bram_addr_ld[8]_i_1__0_n_0\ ); \save_init_bram_addr_ld[9]_i_1__0\: unisim.vcomponents.LUT5 generic map( INIT => X"B8BBB888" ) port map ( I0 => \save_init_bram_addr_ld_reg_n_0_[9]\, I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\, I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\, I3 => axi_araddr_full, I4 => s_axi_araddr(7), O => \save_init_bram_addr_ld[9]_i_1__0_n_0\ ); \save_init_bram_addr_ld_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \save_init_bram_addr_ld[10]_i_1__0_n_0\, Q => \save_init_bram_addr_ld_reg_n_0_[10]\, R => \^sr\(0) ); \save_init_bram_addr_ld_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \save_init_bram_addr_ld[11]_i_1__0_n_0\, Q => \save_init_bram_addr_ld_reg_n_0_[11]\, R => \^sr\(0) ); \save_init_bram_addr_ld_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \^d\(10), Q => \save_init_bram_addr_ld_reg_n_0_[12]\, R => \^sr\(0) ); \save_init_bram_addr_ld_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \^d\(11), Q => \save_init_bram_addr_ld_reg_n_0_[13]\, R => \^sr\(0) ); \save_init_bram_addr_ld_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \^d\(12), Q => \save_init_bram_addr_ld_reg_n_0_[14]\, R => \^sr\(0) ); \save_init_bram_addr_ld_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \^d\(13), Q => \save_init_bram_addr_ld_reg_n_0_[15]\, R => \^sr\(0) ); \save_init_bram_addr_ld_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \save_init_bram_addr_ld[3]_i_1__0_n_0\, Q => \save_init_bram_addr_ld_reg_n_0_[3]\, R => \^sr\(0) ); \save_init_bram_addr_ld_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \save_init_bram_addr_ld[4]_i_1__0_n_0\, Q => \save_init_bram_addr_ld_reg_n_0_[4]\, R => \^sr\(0) ); \save_init_bram_addr_ld_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \save_init_bram_addr_ld[5]_i_1__0_n_0\, Q => \save_init_bram_addr_ld_reg_n_0_[5]\, R => \^sr\(0) ); \save_init_bram_addr_ld_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \save_init_bram_addr_ld[6]_i_1__0_n_0\, Q => \save_init_bram_addr_ld_reg_n_0_[6]\, R => \^sr\(0) ); \save_init_bram_addr_ld_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \save_init_bram_addr_ld[7]_i_1__0_n_0\, Q => \save_init_bram_addr_ld_reg_n_0_[7]\, R => \^sr\(0) ); \save_init_bram_addr_ld_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \save_init_bram_addr_ld[8]_i_1__0_n_0\, Q => \save_init_bram_addr_ld_reg_n_0_[8]\, R => \^sr\(0) ); \save_init_bram_addr_ld_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \save_init_bram_addr_ld[9]_i_1__0_n_0\, Q => \save_init_bram_addr_ld_reg_n_0_[9]\, R => \^sr\(0) ); \wrap_burst_total[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"00000000A000C300" ) port map ( I0 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(2), I1 => \^wrap_burst_total_reg[0]_0\, I2 => \^wrap_burst_total_reg[0]_1\, I3 => \^wrap_burst_total_reg[0]_2\, I4 => \wrap_burst_total[0]_i_5__0_n_0\, I5 => \^wrap_burst_total_reg[0]_3\, O => \wrap_burst_total[0]_i_1_n_0\ ); \wrap_burst_total[0]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(2), I1 => axi_araddr_full, I2 => s_axi_arlen(2), O => \^wrap_burst_total_reg[0]_0\ ); \wrap_burst_total[0]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(1), I1 => axi_araddr_full, I2 => s_axi_arlen(1), O => \^wrap_burst_total_reg[0]_1\ ); \wrap_burst_total[0]_i_4\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(0), I1 => axi_araddr_full, I2 => s_axi_arlen(0), O => \^wrap_burst_total_reg[0]_2\ ); \wrap_burst_total[0]_i_5__0\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => axi_araddr_full, I1 => axi_arsize_pipe(0), O => \wrap_burst_total[0]_i_5__0_n_0\ ); \wrap_burst_total[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"220A880A000A880A" ) port map ( I0 => \wrap_burst_total[2]_i_2_n_0\, I1 => axi_arsize_pipe(0), I2 => s_axi_arlen(3), I3 => axi_araddr_full, I4 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(3), I5 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(2), O => \wrap_burst_total[1]_i_1_n_0\ ); \wrap_burst_total[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"A000888800000000" ) port map ( I0 => \wrap_burst_total[2]_i_2_n_0\, I1 => s_axi_arlen(2), I2 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(2), I3 => axi_arsize_pipe(0), I4 => axi_araddr_full, I5 => \^wrap_burst_total_reg[0]_3\, O => \wrap_burst_total[2]_i_1_n_0\ ); \wrap_burst_total[2]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"CCA000A0" ) port map ( I0 => s_axi_arlen(1), I1 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(1), I2 => s_axi_arlen(0), I3 => axi_araddr_full, I4 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(0), O => \wrap_burst_total[2]_i_2_n_0\ ); \wrap_burst_total[2]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(3), I1 => axi_araddr_full, I2 => s_axi_arlen(3), O => \^wrap_burst_total_reg[0]_3\ ); \wrap_burst_total_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \wrap_burst_total[0]_i_1_n_0\, Q => \wrap_burst_total_reg_n_0_[0]\, R => \^sr\(0) ); \wrap_burst_total_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \wrap_burst_total[1]_i_1_n_0\, Q => \wrap_burst_total_reg_n_0_[1]\, R => \^sr\(0) ); \wrap_burst_total_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \^bram_addr_ld_en\, D => \wrap_burst_total[2]_i_1_n_0\, Q => \wrap_burst_total_reg_n_0_[2]\, R => \^sr\(0) ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zqynq_lab_1_design_axi_bram_ctrl_0_0_rd_chnl is port ( bram_rst_a : out STD_LOGIC; s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 ); bram_en_b : out STD_LOGIC; Q : out STD_LOGIC_VECTOR ( 13 downto 0 ); s_axi_arready : out STD_LOGIC; s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 ); s_axi_aclk : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 ); \GEN_AWREADY.axi_aresetn_d2_reg\ : in STD_LOGIC; s_axi_aresetn : in STD_LOGIC; s_axi_rready : in STD_LOGIC; s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); axi_aresetn_d2 : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC; axi_aresetn_re_reg : in STD_LOGIC; s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_bram_ctrl_0_0_rd_chnl : entity is "rd_chnl"; end zqynq_lab_1_design_axi_bram_ctrl_0_0_rd_chnl; architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0_rd_chnl is signal \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0\ : STD_LOGIC; signal \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0\ : STD_LOGIC; signal \/i__n_0\ : STD_LOGIC; signal \FSM_sequential_rlast_sm_cs[0]_i_1_n_0\ : STD_LOGIC; signal \FSM_sequential_rlast_sm_cs[1]_i_1_n_0\ : STD_LOGIC; signal \FSM_sequential_rlast_sm_cs[2]_i_1_n_0\ : STD_LOGIC; signal \GEN_ARREADY.axi_arready_int_i_1_n_0\ : STD_LOGIC; signal \GEN_ARREADY.axi_early_arready_int_i_2_n_0\ : STD_LOGIC; signal \GEN_ARREADY.axi_early_arready_int_i_3_n_0\ : STD_LOGIC; signal \GEN_ARREADY.axi_early_arready_int_i_4_n_0\ : STD_LOGIC; signal \GEN_AR_DUAL.ar_active_i_1_n_0\ : STD_LOGIC; signal \GEN_AR_DUAL.ar_active_i_2_n_0\ : STD_LOGIC; signal \GEN_AR_DUAL.ar_active_i_3_n_0\ : STD_LOGIC; signal \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0\ : STD_LOGIC; signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\ : STD_LOGIC; signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\ : STD_LOGIC; signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\ : STD_LOGIC; signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\ : STD_LOGIC; signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\ : STD_LOGIC; signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\ : STD_LOGIC; signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\ : STD_LOGIC; signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\ : STD_LOGIC; signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\ : STD_LOGIC; signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\ : STD_LOGIC; signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\ : STD_LOGIC; signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\ : STD_LOGIC; signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\ : STD_LOGIC; signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\ : STD_LOGIC; signal \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0\ : STD_LOGIC; signal \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0\ : STD_LOGIC; signal \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\ : STD_LOGIC; signal \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\ : STD_LOGIC; signal \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\ : STD_LOGIC; signal \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0\ : STD_LOGIC; signal \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0\ : STD_LOGIC; signal \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0\ : STD_LOGIC; signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\ : STD_LOGIC; signal \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\ : STD_LOGIC; signal \GEN_RID.axi_rid_int[0]_i_1_n_0\ : STD_LOGIC; signal \GEN_RID.axi_rid_int[0]_i_2_n_0\ : STD_LOGIC; signal \GEN_RID.axi_rid_temp2[0]_i_1_n_0\ : STD_LOGIC; signal \GEN_RID.axi_rid_temp2_full_i_1_n_0\ : STD_LOGIC; signal \GEN_RID.axi_rid_temp2_reg_n_0_[0]\ : STD_LOGIC; signal \GEN_RID.axi_rid_temp[0]_i_1_n_0\ : STD_LOGIC; signal \GEN_RID.axi_rid_temp[0]_i_3_n_0\ : STD_LOGIC; signal \GEN_RID.axi_rid_temp_full_i_1_n_0\ : STD_LOGIC; signal I_WRAP_BRST_n_0 : STD_LOGIC; signal I_WRAP_BRST_n_10 : STD_LOGIC; signal I_WRAP_BRST_n_11 : STD_LOGIC; signal I_WRAP_BRST_n_12 : STD_LOGIC; signal I_WRAP_BRST_n_13 : STD_LOGIC; signal I_WRAP_BRST_n_14 : STD_LOGIC; signal I_WRAP_BRST_n_15 : STD_LOGIC; signal I_WRAP_BRST_n_16 : STD_LOGIC; signal I_WRAP_BRST_n_17 : STD_LOGIC; signal I_WRAP_BRST_n_18 : STD_LOGIC; signal I_WRAP_BRST_n_19 : STD_LOGIC; signal I_WRAP_BRST_n_2 : STD_LOGIC; signal I_WRAP_BRST_n_20 : STD_LOGIC; signal I_WRAP_BRST_n_21 : STD_LOGIC; signal I_WRAP_BRST_n_22 : STD_LOGIC; signal I_WRAP_BRST_n_24 : STD_LOGIC; signal I_WRAP_BRST_n_25 : STD_LOGIC; signal I_WRAP_BRST_n_26 : STD_LOGIC; signal I_WRAP_BRST_n_27 : STD_LOGIC; signal I_WRAP_BRST_n_3 : STD_LOGIC; signal I_WRAP_BRST_n_4 : STD_LOGIC; signal I_WRAP_BRST_n_5 : STD_LOGIC; signal I_WRAP_BRST_n_7 : STD_LOGIC; signal I_WRAP_BRST_n_8 : STD_LOGIC; signal I_WRAP_BRST_n_9 : STD_LOGIC; signal \^q\ : STD_LOGIC_VECTOR ( 13 downto 0 ); signal act_rd_burst : STD_LOGIC; signal act_rd_burst_i_1_n_0 : STD_LOGIC; signal act_rd_burst_i_3_n_0 : STD_LOGIC; signal act_rd_burst_i_4_n_0 : STD_LOGIC; signal act_rd_burst_i_5_n_0 : STD_LOGIC; signal act_rd_burst_set : STD_LOGIC; signal act_rd_burst_two : STD_LOGIC; signal act_rd_burst_two_i_1_n_0 : STD_LOGIC; signal ar_active : STD_LOGIC; signal araddr_pipe_ld43_out : STD_LOGIC; signal axi_araddr_full : STD_LOGIC; signal axi_arburst_pipe : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_arid_pipe : STD_LOGIC; signal axi_arlen_pipe : STD_LOGIC_VECTOR ( 7 downto 0 ); signal axi_arlen_pipe_1_or_2 : STD_LOGIC; signal axi_arready_int : STD_LOGIC; signal axi_arsize_pipe : STD_LOGIC_VECTOR ( 1 to 1 ); signal axi_arsize_pipe_max : STD_LOGIC; signal axi_arsize_pipe_max_i_1_n_0 : STD_LOGIC; signal axi_b2b_brst : STD_LOGIC; signal axi_b2b_brst_i_1_n_0 : STD_LOGIC; signal axi_b2b_brst_i_2_n_0 : STD_LOGIC; signal axi_early_arready_int : STD_LOGIC; signal axi_rd_burst : STD_LOGIC; signal axi_rd_burst_i_1_n_0 : STD_LOGIC; signal axi_rd_burst_i_2_n_0 : STD_LOGIC; signal axi_rd_burst_i_3_n_0 : STD_LOGIC; signal axi_rd_burst_two : STD_LOGIC; signal axi_rd_burst_two_i_1_n_0 : STD_LOGIC; signal axi_rd_burst_two_reg_n_0 : STD_LOGIC; signal axi_rid_temp : STD_LOGIC; signal axi_rid_temp2 : STD_LOGIC; signal axi_rid_temp2_full : STD_LOGIC; signal axi_rid_temp_full : STD_LOGIC; signal axi_rid_temp_full_d1 : STD_LOGIC; signal axi_rlast_int_i_1_n_0 : STD_LOGIC; signal axi_rlast_set : STD_LOGIC; signal axi_rvalid_clr_ok : STD_LOGIC; signal axi_rvalid_clr_ok_i_1_n_0 : STD_LOGIC; signal axi_rvalid_clr_ok_i_2_n_0 : STD_LOGIC; signal axi_rvalid_clr_ok_i_3_n_0 : STD_LOGIC; signal axi_rvalid_int_i_1_n_0 : STD_LOGIC; signal axi_rvalid_set : STD_LOGIC; signal axi_rvalid_set_cmb : STD_LOGIC; signal bram_addr_ld_en : STD_LOGIC; signal bram_addr_ld_en_mod : STD_LOGIC; signal \^bram_en_b\ : STD_LOGIC; signal bram_en_int_i_10_n_0 : STD_LOGIC; signal bram_en_int_i_11_n_0 : STD_LOGIC; signal bram_en_int_i_12_n_0 : STD_LOGIC; signal bram_en_int_i_13_n_0 : STD_LOGIC; signal bram_en_int_i_1_n_0 : STD_LOGIC; signal bram_en_int_i_2_n_0 : STD_LOGIC; signal bram_en_int_i_3_n_0 : STD_LOGIC; signal bram_en_int_i_4_n_0 : STD_LOGIC; signal bram_en_int_i_5_n_0 : STD_LOGIC; signal bram_en_int_i_6_n_0 : STD_LOGIC; signal bram_en_int_i_7_n_0 : STD_LOGIC; signal bram_en_int_i_9_n_0 : STD_LOGIC; signal \^bram_rst_a\ : STD_LOGIC; signal brst_cnt : STD_LOGIC_VECTOR ( 7 downto 0 ); signal \brst_cnt[0]_i_1_n_0\ : STD_LOGIC; signal \brst_cnt[1]_i_1_n_0\ : STD_LOGIC; signal \brst_cnt[2]_i_1_n_0\ : STD_LOGIC; signal \brst_cnt[3]_i_1_n_0\ : STD_LOGIC; signal \brst_cnt[4]_i_1_n_0\ : STD_LOGIC; signal \brst_cnt[4]_i_2_n_0\ : STD_LOGIC; signal \brst_cnt[5]_i_1_n_0\ : STD_LOGIC; signal \brst_cnt[6]_i_1_n_0\ : STD_LOGIC; signal \brst_cnt[6]_i_2_n_0\ : STD_LOGIC; signal \brst_cnt[7]_i_1_n_0\ : STD_LOGIC; signal \brst_cnt[7]_i_2_n_0\ : STD_LOGIC; signal \brst_cnt[7]_i_3_n_0\ : STD_LOGIC; signal \brst_cnt[7]_i_4_n_0\ : STD_LOGIC; signal brst_cnt_max : STD_LOGIC; signal brst_cnt_max_d1 : STD_LOGIC; signal brst_one : STD_LOGIC; signal brst_one_i_1_n_0 : STD_LOGIC; signal brst_one_i_2_n_0 : STD_LOGIC; signal brst_zero : STD_LOGIC; signal brst_zero_i_1_n_0 : STD_LOGIC; signal brst_zero_i_2_n_0 : STD_LOGIC; signal curr_fixed_burst : STD_LOGIC; signal curr_fixed_burst_reg : STD_LOGIC; signal curr_wrap_burst : STD_LOGIC; signal curr_wrap_burst_reg : STD_LOGIC; signal disable_b2b_brst : STD_LOGIC; signal disable_b2b_brst_cmb : STD_LOGIC; signal disable_b2b_brst_i_2_n_0 : STD_LOGIC; signal disable_b2b_brst_i_3_n_0 : STD_LOGIC; signal disable_b2b_brst_i_4_n_0 : STD_LOGIC; signal end_brst_rd : STD_LOGIC; signal end_brst_rd_clr : STD_LOGIC; signal end_brst_rd_clr_i_1_n_0 : STD_LOGIC; signal end_brst_rd_i_1_n_0 : STD_LOGIC; signal last_bram_addr : STD_LOGIC; signal last_bram_addr0 : STD_LOGIC; signal last_bram_addr_i_2_n_0 : STD_LOGIC; signal last_bram_addr_i_3_n_0 : STD_LOGIC; signal last_bram_addr_i_4_n_0 : STD_LOGIC; signal last_bram_addr_i_5_n_0 : STD_LOGIC; signal last_bram_addr_i_6_n_0 : STD_LOGIC; signal last_bram_addr_i_7_n_0 : STD_LOGIC; signal last_bram_addr_i_8_n_0 : STD_LOGIC; signal last_bram_addr_i_9_n_0 : STD_LOGIC; signal no_ar_ack : STD_LOGIC; signal no_ar_ack_i_1_n_0 : STD_LOGIC; signal p_0_in13_in : STD_LOGIC; signal p_13_out : STD_LOGIC; signal p_48_out : STD_LOGIC; signal p_4_out : STD_LOGIC; signal p_9_out : STD_LOGIC; signal pend_rd_op : STD_LOGIC; signal pend_rd_op_i_1_n_0 : STD_LOGIC; signal pend_rd_op_i_2_n_0 : STD_LOGIC; signal pend_rd_op_i_3_n_0 : STD_LOGIC; signal pend_rd_op_i_4_n_0 : STD_LOGIC; signal pend_rd_op_i_5_n_0 : STD_LOGIC; signal pend_rd_op_i_6_n_0 : STD_LOGIC; signal pend_rd_op_i_7_n_0 : STD_LOGIC; signal pend_rd_op_i_8_n_0 : STD_LOGIC; signal rd_addr_sm_cs : STD_LOGIC; signal rd_adv_buf67_out : STD_LOGIC; signal rd_data_sm_cs : STD_LOGIC_VECTOR ( 3 downto 0 ); signal \rd_data_sm_cs[0]_i_1_n_0\ : STD_LOGIC; signal \rd_data_sm_cs[0]_i_2_n_0\ : STD_LOGIC; signal \rd_data_sm_cs[0]_i_3_n_0\ : STD_LOGIC; signal \rd_data_sm_cs[0]_i_4_n_0\ : STD_LOGIC; signal \rd_data_sm_cs[1]_i_1_n_0\ : STD_LOGIC; signal \rd_data_sm_cs[1]_i_2_n_0\ : STD_LOGIC; signal \rd_data_sm_cs[2]_i_1_n_0\ : STD_LOGIC; signal \rd_data_sm_cs[2]_i_2_n_0\ : STD_LOGIC; signal \rd_data_sm_cs[2]_i_3_n_0\ : STD_LOGIC; signal \rd_data_sm_cs[2]_i_4_n_0\ : STD_LOGIC; signal \rd_data_sm_cs[2]_i_5_n_0\ : STD_LOGIC; signal \rd_data_sm_cs[3]_i_2_n_0\ : STD_LOGIC; signal \rd_data_sm_cs[3]_i_3_n_0\ : STD_LOGIC; signal \rd_data_sm_cs[3]_i_4_n_0\ : STD_LOGIC; signal \rd_data_sm_cs[3]_i_5_n_0\ : STD_LOGIC; signal \rd_data_sm_cs[3]_i_6_n_0\ : STD_LOGIC; signal \rd_data_sm_cs[3]_i_7_n_0\ : STD_LOGIC; signal rd_data_sm_ns : STD_LOGIC; signal rd_skid_buf : STD_LOGIC_VECTOR ( 31 downto 0 ); signal rd_skid_buf_ld : STD_LOGIC; signal rd_skid_buf_ld_cmb : STD_LOGIC; signal rd_skid_buf_ld_reg : STD_LOGIC; signal rddata_mux_sel : STD_LOGIC; signal rddata_mux_sel_cmb : STD_LOGIC; signal rddata_mux_sel_i_1_n_0 : STD_LOGIC; signal rddata_mux_sel_i_3_n_0 : STD_LOGIC; signal rlast_sm_cs : STD_LOGIC_VECTOR ( 2 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of rlast_sm_cs : signal is "yes"; signal \^s_axi_rid\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^s_axi_rlast\ : STD_LOGIC; signal \^s_axi_rvalid\ : STD_LOGIC; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \FSM_sequential_rlast_sm_cs[2]_i_2\ : label is "soft_lutpair14"; attribute KEEP : string; attribute KEEP of \FSM_sequential_rlast_sm_cs_reg[0]\ : label is "yes"; attribute KEEP of \FSM_sequential_rlast_sm_cs_reg[1]\ : label is "yes"; attribute KEEP of \FSM_sequential_rlast_sm_cs_reg[2]\ : label is "yes"; attribute SOFT_HLUTNM of \GEN_ARREADY.axi_arready_int_i_1\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \GEN_ARREADY.axi_early_arready_int_i_3\ : label is "soft_lutpair7"; attribute SOFT_HLUTNM of \GEN_AR_DUAL.ar_active_i_3\ : label is "soft_lutpair15"; attribute SOFT_HLUTNM of \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3\ : label is "soft_lutpair27"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1\ : label is "soft_lutpair23"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1\ : label is "soft_lutpair32"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1\ : label is "soft_lutpair29"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1\ : label is "soft_lutpair34"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1\ : label is "soft_lutpair34"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1\ : label is "soft_lutpair35"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1\ : label is "soft_lutpair36"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1\ : label is "soft_lutpair37"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1\ : label is "soft_lutpair38"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1\ : label is "soft_lutpair37"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1\ : label is "soft_lutpair38"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1\ : label is "soft_lutpair25"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1\ : label is "soft_lutpair39"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1\ : label is "soft_lutpair40"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1\ : label is "soft_lutpair41"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1\ : label is "soft_lutpair42"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1\ : label is "soft_lutpair42"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1\ : label is "soft_lutpair41"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1\ : label is "soft_lutpair40"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1\ : label is "soft_lutpair39"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1\ : label is "soft_lutpair36"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1\ : label is "soft_lutpair35"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1\ : label is "soft_lutpair23"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1\ : label is "soft_lutpair30"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3\ : label is "soft_lutpair33"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_5\ : label is "soft_lutpair16"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1\ : label is "soft_lutpair28"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1\ : label is "soft_lutpair29"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1\ : label is "soft_lutpair30"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1\ : label is "soft_lutpair32"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1\ : label is "soft_lutpair33"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1\ : label is "soft_lutpair25"; attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1\ : label is "soft_lutpair28"; attribute SOFT_HLUTNM of \GEN_RID.axi_rid_int[0]_i_2\ : label is "soft_lutpair21"; attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp[0]_i_2\ : label is "soft_lutpair26"; attribute SOFT_HLUTNM of act_rd_burst_i_4 : label is "soft_lutpair14"; attribute SOFT_HLUTNM of act_rd_burst_i_5 : label is "soft_lutpair43"; attribute SOFT_HLUTNM of axi_rd_burst_two_i_2 : label is "soft_lutpair13"; attribute SOFT_HLUTNM of axi_rvalid_clr_ok_i_2 : label is "soft_lutpair8"; attribute SOFT_HLUTNM of axi_rvalid_set_i_1 : label is "soft_lutpair19"; attribute SOFT_HLUTNM of bram_en_int_i_10 : label is "soft_lutpair9"; attribute SOFT_HLUTNM of bram_en_int_i_11 : label is "soft_lutpair15"; attribute SOFT_HLUTNM of bram_en_int_i_13 : label is "soft_lutpair22"; attribute SOFT_HLUTNM of bram_en_int_i_6 : label is "soft_lutpair16"; attribute SOFT_HLUTNM of bram_en_int_i_9 : label is "soft_lutpair18"; attribute SOFT_HLUTNM of \brst_cnt[4]_i_2\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of \brst_cnt[6]_i_1\ : label is "soft_lutpair10"; attribute SOFT_HLUTNM of \brst_cnt[6]_i_2\ : label is "soft_lutpair11"; attribute SOFT_HLUTNM of \brst_cnt[7]_i_3\ : label is "soft_lutpair26"; attribute SOFT_HLUTNM of \brst_cnt[7]_i_4\ : label is "soft_lutpair12"; attribute SOFT_HLUTNM of brst_one_i_2 : label is "soft_lutpair31"; attribute SOFT_HLUTNM of brst_zero_i_1 : label is "soft_lutpair18"; attribute SOFT_HLUTNM of brst_zero_i_2 : label is "soft_lutpair13"; attribute SOFT_HLUTNM of curr_fixed_burst_reg_i_1 : label is "soft_lutpair6"; attribute SOFT_HLUTNM of curr_wrap_burst_reg_i_1 : label is "soft_lutpair6"; attribute SOFT_HLUTNM of disable_b2b_brst_i_2 : label is "soft_lutpair43"; attribute SOFT_HLUTNM of last_bram_addr_i_2 : label is "soft_lutpair31"; attribute SOFT_HLUTNM of last_bram_addr_i_7 : label is "soft_lutpair10"; attribute SOFT_HLUTNM of last_bram_addr_i_9 : label is "soft_lutpair11"; attribute SOFT_HLUTNM of pend_rd_op_i_5 : label is "soft_lutpair27"; attribute SOFT_HLUTNM of pend_rd_op_i_6 : label is "soft_lutpair22"; attribute SOFT_HLUTNM of pend_rd_op_i_7 : label is "soft_lutpair20"; attribute SOFT_HLUTNM of \rd_data_sm_cs[0]_i_3\ : label is "soft_lutpair24"; attribute SOFT_HLUTNM of \rd_data_sm_cs[1]_i_2\ : label is "soft_lutpair24"; attribute SOFT_HLUTNM of \rd_data_sm_cs[2]_i_3\ : label is "soft_lutpair17"; attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_4\ : label is "soft_lutpair8"; attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_5\ : label is "soft_lutpair19"; attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_6\ : label is "soft_lutpair20"; attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_7\ : label is "soft_lutpair9"; attribute SOFT_HLUTNM of rddata_mux_sel_i_1 : label is "soft_lutpair17"; attribute SOFT_HLUTNM of s_axi_arready_INST_0 : label is "soft_lutpair21"; begin Q(13 downto 0) <= \^q\(13 downto 0); bram_en_b <= \^bram_en_b\; bram_rst_a <= \^bram_rst_a\; s_axi_rid(0) <= \^s_axi_rid\(0); s_axi_rlast <= \^s_axi_rlast\; s_axi_rvalid <= \^s_axi_rvalid\; \/FSM_sequential_rlast_sm_cs[0]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"0011001300130013" ) port map ( I0 => axi_rd_burst, I1 => rlast_sm_cs(1), I2 => act_rd_burst_two, I3 => axi_rd_burst_two_reg_n_0, I4 => \^s_axi_rvalid\, I5 => s_axi_rready, O => \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0\ ); \/FSM_sequential_rlast_sm_cs[1]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"003F007F003F0055" ) port map ( I0 => axi_rd_burst, I1 => s_axi_rready, I2 => \^s_axi_rvalid\, I3 => rlast_sm_cs(1), I4 => axi_rd_burst_two_reg_n_0, I5 => act_rd_burst_two, O => \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0\ ); \/i_\: unisim.vcomponents.LUT6 generic map( INIT => X"F000F111F000E000" ) port map ( I0 => rlast_sm_cs(2), I1 => rlast_sm_cs(1), I2 => \^s_axi_rvalid\, I3 => s_axi_rready, I4 => rlast_sm_cs(0), I5 => last_bram_addr, O => \/i__n_0\ ); \/i___0\: unisim.vcomponents.LUT6 generic map( INIT => X"00008080000F8080" ) port map ( I0 => s_axi_rready, I1 => \^s_axi_rvalid\, I2 => rlast_sm_cs(0), I3 => rlast_sm_cs(1), I4 => rlast_sm_cs(2), I5 => \^s_axi_rlast\, O => axi_rlast_set ); \FSM_sequential_rlast_sm_cs[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"01FF0100" ) port map ( I0 => rlast_sm_cs(2), I1 => rlast_sm_cs(0), I2 => \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0\, I3 => \/i__n_0\, I4 => rlast_sm_cs(0), O => \FSM_sequential_rlast_sm_cs[0]_i_1_n_0\ ); \FSM_sequential_rlast_sm_cs[1]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"01FF0100" ) port map ( I0 => rlast_sm_cs(2), I1 => rlast_sm_cs(0), I2 => \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0\, I3 => \/i__n_0\, I4 => rlast_sm_cs(1), O => \FSM_sequential_rlast_sm_cs[1]_i_1_n_0\ ); \FSM_sequential_rlast_sm_cs[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"00A4FFFF00A40000" ) port map ( I0 => rlast_sm_cs(1), I1 => p_0_in13_in, I2 => rlast_sm_cs(0), I3 => rlast_sm_cs(2), I4 => \/i__n_0\, I5 => rlast_sm_cs(2), O => \FSM_sequential_rlast_sm_cs[2]_i_1_n_0\ ); \FSM_sequential_rlast_sm_cs[2]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => axi_rd_burst_two_reg_n_0, I1 => axi_rd_burst, O => p_0_in13_in ); \FSM_sequential_rlast_sm_cs_reg[0]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => \FSM_sequential_rlast_sm_cs[0]_i_1_n_0\, Q => rlast_sm_cs(0), R => \^bram_rst_a\ ); \FSM_sequential_rlast_sm_cs_reg[1]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => \FSM_sequential_rlast_sm_cs[1]_i_1_n_0\, Q => rlast_sm_cs(1), R => \^bram_rst_a\ ); \FSM_sequential_rlast_sm_cs_reg[2]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => \FSM_sequential_rlast_sm_cs[2]_i_1_n_0\, Q => rlast_sm_cs(2), R => \^bram_rst_a\ ); \GEN_ARREADY.axi_arready_int_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAEEE" ) port map ( I0 => p_9_out, I1 => axi_arready_int, I2 => s_axi_arvalid, I3 => axi_araddr_full, I4 => araddr_pipe_ld43_out, O => \GEN_ARREADY.axi_arready_int_i_1_n_0\ ); \GEN_ARREADY.axi_arready_int_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"BAAA" ) port map ( I0 => axi_aresetn_re_reg, I1 => axi_early_arready_int, I2 => axi_araddr_full, I3 => bram_addr_ld_en, O => p_9_out ); \GEN_ARREADY.axi_arready_int_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \GEN_ARREADY.axi_arready_int_i_1_n_0\, Q => axi_arready_int, R => \^bram_rst_a\ ); \GEN_ARREADY.axi_early_arready_int_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000200" ) port map ( I0 => \GEN_ARREADY.axi_early_arready_int_i_2_n_0\, I1 => \GEN_ARREADY.axi_early_arready_int_i_3_n_0\, I2 => rd_data_sm_cs(3), I3 => brst_one, I4 => axi_arready_int, I5 => \GEN_ARREADY.axi_early_arready_int_i_4_n_0\, O => p_48_out ); \GEN_ARREADY.axi_early_arready_int_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"03C4000400C40004" ) port map ( I0 => axi_rd_burst_two_reg_n_0, I1 => rd_data_sm_cs(1), I2 => rd_data_sm_cs(0), I3 => rd_data_sm_cs(2), I4 => rd_adv_buf67_out, I5 => bram_en_int_i_9_n_0, O => \GEN_ARREADY.axi_early_arready_int_i_2_n_0\ ); \GEN_ARREADY.axi_early_arready_int_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => axi_araddr_full, I1 => s_axi_arvalid, O => \GEN_ARREADY.axi_early_arready_int_i_3_n_0\ ); \GEN_ARREADY.axi_early_arready_int_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"AAEAAAEAFFFFAAEA" ) port map ( I0 => I_WRAP_BRST_n_27, I1 => \rd_data_sm_cs[3]_i_6_n_0\, I2 => rd_data_sm_cs(1), I3 => rd_data_sm_cs(0), I4 => brst_zero, I5 => rd_adv_buf67_out, O => \GEN_ARREADY.axi_early_arready_int_i_4_n_0\ ); \GEN_ARREADY.axi_early_arready_int_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => p_48_out, Q => axi_early_arready_int, R => \^bram_rst_a\ ); \GEN_AR_DUAL.ar_active_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0FBFBFBF0F0F0F0" ) port map ( I0 => \GEN_AR_DUAL.ar_active_i_2_n_0\, I1 => \rd_data_sm_cs[2]_i_3_n_0\, I2 => bram_addr_ld_en, I3 => \rd_data_sm_cs[2]_i_5_n_0\, I4 => rd_adv_buf67_out, I5 => ar_active, O => \GEN_AR_DUAL.ar_active_i_1_n_0\ ); \GEN_AR_DUAL.ar_active_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"B0FFBFFFB0FFBF0F" ) port map ( I0 => \GEN_AR_DUAL.ar_active_i_3_n_0\, I1 => I_WRAP_BRST_n_27, I2 => rd_data_sm_cs(0), I3 => rd_data_sm_cs(1), I4 => axi_rd_burst_two_reg_n_0, I5 => axi_rd_burst, O => \GEN_AR_DUAL.ar_active_i_2_n_0\ ); \GEN_AR_DUAL.ar_active_i_3\: unisim.vcomponents.LUT5 generic map( INIT => X"0DFFFFFF" ) port map ( I0 => end_brst_rd, I1 => axi_b2b_brst, I2 => brst_zero, I3 => s_axi_rready, I4 => \^s_axi_rvalid\, O => \GEN_AR_DUAL.ar_active_i_3_n_0\ ); \GEN_AR_DUAL.ar_active_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \GEN_AR_DUAL.ar_active_i_1_n_0\, Q => ar_active, R => \GEN_AWREADY.axi_aresetn_d2_reg\ ); \GEN_AR_DUAL.rd_addr_sm_cs_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"10001000F0F01000" ) port map ( I0 => rd_addr_sm_cs, I1 => axi_araddr_full, I2 => s_axi_arvalid, I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\, I4 => last_bram_addr, I5 => \GEN_ARREADY.axi_early_arready_int_i_4_n_0\, O => \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0\ ); \GEN_AR_DUAL.rd_addr_sm_cs_reg\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0\, Q => rd_addr_sm_cs, R => \GEN_AWREADY.axi_aresetn_d2_reg\ ); \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_araddr(8), Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\, R => '0' ); \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_araddr(9), Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\, R => '0' ); \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_araddr(10), Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\, R => '0' ); \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_araddr(11), Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\, R => '0' ); \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_araddr(12), Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\, R => '0' ); \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_araddr(13), Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\, R => '0' ); \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_araddr(0), Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\, R => '0' ); \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_araddr(1), Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\, R => '0' ); \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_araddr(2), Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\, R => '0' ); \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_araddr(3), Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\, R => '0' ); \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_araddr(4), Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\, R => '0' ); \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_araddr(5), Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\, R => '0' ); \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_araddr(6), Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\, R => '0' ); \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_araddr(7), Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\, R => '0' ); \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"00C08888CCCC8888" ) port map ( I0 => araddr_pipe_ld43_out, I1 => s_axi_aresetn, I2 => s_axi_arvalid, I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\, I4 => axi_araddr_full, I5 => bram_addr_ld_en, O => \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0\ ); \GEN_AR_PIPE_DUAL.axi_araddr_full_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0\, Q => axi_araddr_full, R => '0' ); \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"03AA" ) port map ( I0 => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\, I1 => s_axi_arburst(0), I2 => s_axi_arburst(1), I3 => araddr_pipe_ld43_out, O => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0\ ); \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0\, Q => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\, R => '0' ); \GEN_AR_PIPE_DUAL.axi_arburst_pipe_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_arburst(0), Q => axi_arburst_pipe(0), R => '0' ); \GEN_AR_PIPE_DUAL.axi_arburst_pipe_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_arburst(1), Q => axi_arburst_pipe(1), R => '0' ); \GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_arid(0), Q => axi_arid_pipe, R => '0' ); \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"220022002A002200" ) port map ( I0 => axi_aresetn_d2, I1 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\, I2 => rd_addr_sm_cs, I3 => s_axi_arvalid, I4 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\, I5 => axi_araddr_full, O => araddr_pipe_ld43_out ); \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFF70FFFFFFFF" ) port map ( I0 => \^s_axi_rvalid\, I1 => s_axi_rready, I2 => brst_zero, I3 => I_WRAP_BRST_n_26, I4 => I_WRAP_BRST_n_27, I5 => last_bram_addr, O => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\ ); \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"FE" ) port map ( I0 => no_ar_ack, I1 => pend_rd_op, I2 => ar_active, O => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\ ); \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => s_axi_arlen(1), I1 => s_axi_arlen(7), I2 => s_axi_arlen(4), I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0\, O => p_13_out ); \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => s_axi_arlen(6), I1 => s_axi_arlen(2), I2 => s_axi_arlen(5), I3 => s_axi_arlen(3), O => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0\ ); \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => p_13_out, Q => axi_arlen_pipe_1_or_2, R => '0' ); \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_arlen(0), Q => axi_arlen_pipe(0), R => '0' ); \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_arlen(1), Q => axi_arlen_pipe(1), R => '0' ); \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_arlen(2), Q => axi_arlen_pipe(2), R => '0' ); \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_arlen(3), Q => axi_arlen_pipe(3), R => '0' ); \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_arlen(4), Q => axi_arlen_pipe(4), R => '0' ); \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_arlen(5), Q => axi_arlen_pipe(5), R => '0' ); \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_arlen(6), Q => axi_arlen_pipe(6), R => '0' ); \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => s_axi_arlen(7), Q => axi_arlen_pipe(7), R => '0' ); \GEN_AR_PIPE_DUAL.axi_arsize_pipe_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => araddr_pipe_ld43_out, D => '1', Q => axi_arsize_pipe(1), R => '0' ); \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"00000000BAAA0000" ) port map ( I0 => brst_cnt_max, I1 => pend_rd_op, I2 => ar_active, I3 => brst_zero, I4 => s_axi_aresetn, I5 => bram_addr_ld_en, O => \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0\ ); \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0\, Q => brst_cnt_max, R => '0' ); \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFFFFFFFFFF" ) port map ( I0 => \^q\(4), I1 => \^q\(1), I2 => \^q\(0), I3 => \^q\(2), I4 => \^q\(3), I5 => \^q\(5), O => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0\ ); \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"F7FFFFFF" ) port map ( I0 => \^q\(6), I1 => \^q\(4), I2 => I_WRAP_BRST_n_24, I3 => \^q\(5), I4 => \^q\(7), O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0\ ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => I_WRAP_BRST_n_7, D => I_WRAP_BRST_n_14, Q => \^q\(8), R => '0' ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => I_WRAP_BRST_n_7, D => I_WRAP_BRST_n_13, Q => \^q\(9), R => '0' ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => bram_addr_ld_en_mod, D => I_WRAP_BRST_n_12, Q => \^q\(10), R => '0' ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => bram_addr_ld_en_mod, D => I_WRAP_BRST_n_11, Q => \^q\(11), R => '0' ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => bram_addr_ld_en_mod, D => I_WRAP_BRST_n_10, Q => \^q\(12), R => '0' ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => bram_addr_ld_en_mod, D => I_WRAP_BRST_n_9, Q => \^q\(13), R => '0' ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => I_WRAP_BRST_n_7, D => I_WRAP_BRST_n_22, Q => \^q\(0), R => '0' ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => I_WRAP_BRST_n_7, D => I_WRAP_BRST_n_21, Q => \^q\(1), R => '0' ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => I_WRAP_BRST_n_7, D => I_WRAP_BRST_n_20, Q => \^q\(2), R => '0' ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => I_WRAP_BRST_n_7, D => I_WRAP_BRST_n_19, Q => \^q\(3), R => '0' ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => I_WRAP_BRST_n_7, D => I_WRAP_BRST_n_18, Q => \^q\(4), R => '0' ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => I_WRAP_BRST_n_7, D => I_WRAP_BRST_n_17, Q => \^q\(5), R => '0' ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => I_WRAP_BRST_n_7, D => I_WRAP_BRST_n_16, Q => \^q\(6), R => '0' ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => I_WRAP_BRST_n_7, D => I_WRAP_BRST_n_15, Q => \^q\(7), R => '0' ); \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(0), I1 => bram_rddata_b(0), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\, Q => s_axi_rdata(0), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(10), I1 => bram_rddata_b(10), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\, Q => s_axi_rdata(10), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(11), I1 => bram_rddata_b(11), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\, Q => s_axi_rdata(11), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(12), I1 => bram_rddata_b(12), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\, Q => s_axi_rdata(12), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(13), I1 => bram_rddata_b(13), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\, Q => s_axi_rdata(13), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(14), I1 => bram_rddata_b(14), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\, Q => s_axi_rdata(14), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(15), I1 => bram_rddata_b(15), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\, Q => s_axi_rdata(15), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(16), I1 => bram_rddata_b(16), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\, Q => s_axi_rdata(16), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(17), I1 => bram_rddata_b(17), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\, Q => s_axi_rdata(17), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(18), I1 => bram_rddata_b(18), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\, Q => s_axi_rdata(18), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(19), I1 => bram_rddata_b(19), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\, Q => s_axi_rdata(19), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(1), I1 => bram_rddata_b(1), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0\, Q => s_axi_rdata(1), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(20), I1 => bram_rddata_b(20), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\, Q => s_axi_rdata(20), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(21), I1 => bram_rddata_b(21), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\, Q => s_axi_rdata(21), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(22), I1 => bram_rddata_b(22), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\, Q => s_axi_rdata(22), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(23), I1 => bram_rddata_b(23), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\, Q => s_axi_rdata(23), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(24), I1 => bram_rddata_b(24), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\, Q => s_axi_rdata(24), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(25), I1 => bram_rddata_b(25), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\, Q => s_axi_rdata(25), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(26), I1 => bram_rddata_b(26), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\, Q => s_axi_rdata(26), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(27), I1 => bram_rddata_b(27), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\, Q => s_axi_rdata(27), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(28), I1 => bram_rddata_b(28), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\, Q => s_axi_rdata(28), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(29), I1 => bram_rddata_b(29), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\, Q => s_axi_rdata(29), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(2), I1 => bram_rddata_b(2), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\, Q => s_axi_rdata(2), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(30), I1 => bram_rddata_b(30), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int_reg[30]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\, Q => s_axi_rdata(30), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"08FF" ) port map ( I0 => s_axi_rready, I1 => \^s_axi_rlast\, I2 => axi_b2b_brst, I3 => s_axi_aresetn, O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"1414545410000404" ) port map ( I0 => rd_data_sm_cs(3), I1 => rd_data_sm_cs(1), I2 => rd_data_sm_cs(2), I3 => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4_n_0\, I4 => rd_data_sm_cs(0), I5 => rd_adv_buf67_out, O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(31), I1 => bram_rddata_b(31), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => act_rd_burst, I1 => act_rd_burst_two, O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_5\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => \^s_axi_rvalid\, I1 => s_axi_rready, O => rd_adv_buf67_out ); \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int_reg[31]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\, Q => s_axi_rdata(31), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(3), I1 => bram_rddata_b(3), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\, Q => s_axi_rdata(3), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(4), I1 => bram_rddata_b(4), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\, Q => s_axi_rdata(4), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(5), I1 => bram_rddata_b(5), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\, Q => s_axi_rdata(5), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(6), I1 => bram_rddata_b(6), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\, Q => s_axi_rdata(6), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(7), I1 => bram_rddata_b(7), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\, Q => s_axi_rdata(7), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(8), I1 => bram_rddata_b(8), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\, Q => s_axi_rdata(8), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"AC" ) port map ( I0 => rd_skid_buf(9), I1 => bram_rddata_b(9), I2 => rddata_mux_sel, O => \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\, D => \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\, Q => s_axi_rdata(9), R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ ); \GEN_RDATA_NO_ECC.rd_skid_buf[31]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAAABAAAAAA" ) port map ( I0 => rd_skid_buf_ld_reg, I1 => rd_data_sm_cs(1), I2 => rd_data_sm_cs(3), I3 => rd_adv_buf67_out, I4 => rd_data_sm_cs(2), I5 => rd_data_sm_cs(0), O => rd_skid_buf_ld ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(0), Q => rd_skid_buf(0), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(10), Q => rd_skid_buf(10), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(11), Q => rd_skid_buf(11), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(12), Q => rd_skid_buf(12), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(13), Q => rd_skid_buf(13), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(14), Q => rd_skid_buf(14), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(15), Q => rd_skid_buf(15), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(16), Q => rd_skid_buf(16), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(17), Q => rd_skid_buf(17), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(18), Q => rd_skid_buf(18), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(19), Q => rd_skid_buf(19), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(1), Q => rd_skid_buf(1), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(20), Q => rd_skid_buf(20), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(21), Q => rd_skid_buf(21), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(22), Q => rd_skid_buf(22), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(23), Q => rd_skid_buf(23), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(24), Q => rd_skid_buf(24), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(25), Q => rd_skid_buf(25), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(26), Q => rd_skid_buf(26), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(27), Q => rd_skid_buf(27), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(28), Q => rd_skid_buf(28), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(29), Q => rd_skid_buf(29), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(2), Q => rd_skid_buf(2), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[30]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(30), Q => rd_skid_buf(30), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[31]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(31), Q => rd_skid_buf(31), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(3), Q => rd_skid_buf(3), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(4), Q => rd_skid_buf(4), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(5), Q => rd_skid_buf(5), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(6), Q => rd_skid_buf(6), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(7), Q => rd_skid_buf(7), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(8), Q => rd_skid_buf(8), R => \^bram_rst_a\ ); \GEN_RDATA_NO_ECC.rd_skid_buf_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => rd_skid_buf_ld, D => bram_rddata_b(9), Q => rd_skid_buf(9), R => \^bram_rst_a\ ); \GEN_RID.axi_rid_int[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"E200E200F0000000" ) port map ( I0 => \^s_axi_rid\(0), I1 => axi_rvalid_set, I2 => axi_rid_temp, I3 => s_axi_aresetn, I4 => axi_b2b_brst, I5 => \GEN_RID.axi_rid_int[0]_i_2_n_0\, O => \GEN_RID.axi_rid_int[0]_i_1_n_0\ ); \GEN_RID.axi_rid_int[0]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"7" ) port map ( I0 => s_axi_rready, I1 => \^s_axi_rlast\, O => \GEN_RID.axi_rid_int[0]_i_2_n_0\ ); \GEN_RID.axi_rid_int_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \GEN_RID.axi_rid_int[0]_i_1_n_0\, Q => \^s_axi_rid\(0), R => '0' ); \GEN_RID.axi_rid_temp2[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"B8FFFFFFB8000000" ) port map ( I0 => axi_arid_pipe, I1 => axi_araddr_full, I2 => s_axi_arid(0), I3 => axi_rid_temp_full, I4 => bram_addr_ld_en, I5 => \GEN_RID.axi_rid_temp2_reg_n_0_[0]\, O => \GEN_RID.axi_rid_temp2[0]_i_1_n_0\ ); \GEN_RID.axi_rid_temp2_full_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"08080000C8C800C0" ) port map ( I0 => bram_addr_ld_en, I1 => s_axi_aresetn, I2 => axi_rid_temp2_full, I3 => axi_rid_temp_full_d1, I4 => axi_rid_temp_full, I5 => p_4_out, O => \GEN_RID.axi_rid_temp2_full_i_1_n_0\ ); \GEN_RID.axi_rid_temp2_full_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \GEN_RID.axi_rid_temp2_full_i_1_n_0\, Q => axi_rid_temp2_full, R => '0' ); \GEN_RID.axi_rid_temp2_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \GEN_RID.axi_rid_temp2[0]_i_1_n_0\, Q => \GEN_RID.axi_rid_temp2_reg_n_0_[0]\, R => \^bram_rst_a\ ); \GEN_RID.axi_rid_temp[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"CFAACFCFC0AAC0C0" ) port map ( I0 => axi_rid_temp2, I1 => \GEN_RID.axi_rid_temp2_reg_n_0_[0]\, I2 => \GEN_RID.axi_rid_temp[0]_i_3_n_0\, I3 => axi_rid_temp_full, I4 => bram_addr_ld_en, I5 => axi_rid_temp, O => \GEN_RID.axi_rid_temp[0]_i_1_n_0\ ); \GEN_RID.axi_rid_temp[0]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axi_arid_pipe, I1 => axi_araddr_full, I2 => s_axi_arid(0), O => axi_rid_temp2 ); \GEN_RID.axi_rid_temp[0]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"AA08AAAAAA08AA08" ) port map ( I0 => axi_rid_temp2_full, I1 => axi_rid_temp_full_d1, I2 => axi_rid_temp_full, I3 => axi_rvalid_set, I4 => \GEN_RID.axi_rid_int[0]_i_2_n_0\, I5 => axi_b2b_brst, O => \GEN_RID.axi_rid_temp[0]_i_3_n_0\ ); \GEN_RID.axi_rid_temp_full_d1_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => axi_rid_temp_full, Q => axi_rid_temp_full_d1, R => \^bram_rst_a\ ); \GEN_RID.axi_rid_temp_full_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"F0F0F0E000F0A0A0" ) port map ( I0 => bram_addr_ld_en, I1 => axi_rid_temp_full_d1, I2 => s_axi_aresetn, I3 => p_4_out, I4 => axi_rid_temp_full, I5 => axi_rid_temp2_full, O => \GEN_RID.axi_rid_temp_full_i_1_n_0\ ); \GEN_RID.axi_rid_temp_full_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"EAAA" ) port map ( I0 => axi_rvalid_set, I1 => s_axi_rready, I2 => \^s_axi_rlast\, I3 => axi_b2b_brst, O => p_4_out ); \GEN_RID.axi_rid_temp_full_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \GEN_RID.axi_rid_temp_full_i_1_n_0\, Q => axi_rid_temp_full, R => '0' ); \GEN_RID.axi_rid_temp_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \GEN_RID.axi_rid_temp[0]_i_1_n_0\, Q => axi_rid_temp, R => \^bram_rst_a\ ); I_WRAP_BRST: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst_0 port map ( D(13) => I_WRAP_BRST_n_9, D(12) => I_WRAP_BRST_n_10, D(11) => I_WRAP_BRST_n_11, D(10) => I_WRAP_BRST_n_12, D(9) => I_WRAP_BRST_n_13, D(8) => I_WRAP_BRST_n_14, D(7) => I_WRAP_BRST_n_15, D(6) => I_WRAP_BRST_n_16, D(5) => I_WRAP_BRST_n_17, D(4) => I_WRAP_BRST_n_18, D(3) => I_WRAP_BRST_n_19, D(2) => I_WRAP_BRST_n_20, D(1) => I_WRAP_BRST_n_21, D(0) => I_WRAP_BRST_n_22, E(1) => bram_addr_ld_en_mod, E(0) => I_WRAP_BRST_n_7, \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\, \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\, \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\, \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\, \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\, \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\, \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\, \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\, \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\, \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\, \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\, \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\, \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\, \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\, \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\ => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\, \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(3 downto 0) => axi_arlen_pipe(3 downto 0), \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ => I_WRAP_BRST_n_0, \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0\ => I_WRAP_BRST_n_8, \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(9 downto 0) => \^q\(9 downto 0), \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ => I_WRAP_BRST_n_24, \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0\, \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0\, Q(3 downto 0) => rd_data_sm_cs(3 downto 0), SR(0) => \^bram_rst_a\, ar_active => ar_active, axi_araddr_full => axi_araddr_full, axi_aresetn_d2 => axi_aresetn_d2, axi_arlen_pipe_1_or_2 => axi_arlen_pipe_1_or_2, axi_arsize_pipe(0) => axi_arsize_pipe(1), axi_arsize_pipe_max => axi_arsize_pipe_max, axi_b2b_brst => axi_b2b_brst, axi_rd_burst => axi_rd_burst, axi_rd_burst_two_reg => axi_rd_burst_two_reg_n_0, axi_rvalid_int_reg => \^s_axi_rvalid\, bram_addr_ld_en => bram_addr_ld_en, brst_zero => brst_zero, curr_fixed_burst_reg => curr_fixed_burst_reg, curr_wrap_burst_reg => curr_wrap_burst_reg, disable_b2b_brst => disable_b2b_brst, end_brst_rd => end_brst_rd, last_bram_addr => last_bram_addr, no_ar_ack => no_ar_ack, pend_rd_op => pend_rd_op, rd_addr_sm_cs => rd_addr_sm_cs, \rd_data_sm_cs_reg[1]\ => I_WRAP_BRST_n_25, s_axi_aclk => s_axi_aclk, s_axi_araddr(13 downto 0) => s_axi_araddr(13 downto 0), s_axi_aresetn => s_axi_aresetn, s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0), s_axi_arvalid => s_axi_arvalid, s_axi_rready => s_axi_rready, \save_init_bram_addr_ld_reg[15]_0\ => I_WRAP_BRST_n_26, \save_init_bram_addr_ld_reg[15]_1\ => I_WRAP_BRST_n_27, \wrap_burst_total_reg[0]_0\ => I_WRAP_BRST_n_2, \wrap_burst_total_reg[0]_1\ => I_WRAP_BRST_n_3, \wrap_burst_total_reg[0]_2\ => I_WRAP_BRST_n_4, \wrap_burst_total_reg[0]_3\ => I_WRAP_BRST_n_5 ); act_rd_burst_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"000000002EEE22E2" ) port map ( I0 => act_rd_burst, I1 => act_rd_burst_set, I2 => bram_addr_ld_en, I3 => axi_rd_burst_two, I4 => axi_rd_burst, I5 => act_rd_burst_i_3_n_0, O => act_rd_burst_i_1_n_0 ); act_rd_burst_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"A8A888A888888888" ) port map ( I0 => \rd_data_sm_cs[2]_i_3_n_0\, I1 => act_rd_burst_i_4_n_0, I2 => act_rd_burst_i_5_n_0, I3 => axi_rd_burst_i_2_n_0, I4 => I_WRAP_BRST_n_4, I5 => bram_addr_ld_en, O => act_rd_burst_set ); act_rd_burst_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"20000040FFFFFFFF" ) port map ( I0 => rd_data_sm_cs(2), I1 => rd_data_sm_cs(3), I2 => \rd_data_sm_cs[3]_i_7_n_0\, I3 => rd_data_sm_cs(1), I4 => rd_data_sm_cs(0), I5 => s_axi_aresetn, O => act_rd_burst_i_3_n_0 ); act_rd_burst_i_4: unisim.vcomponents.LUT5 generic map( INIT => X"5500FC00" ) port map ( I0 => bram_en_int_i_12_n_0, I1 => axi_rd_burst_two_reg_n_0, I2 => axi_rd_burst, I3 => rd_data_sm_cs(0), I4 => rd_data_sm_cs(1), O => act_rd_burst_i_4_n_0 ); act_rd_burst_i_5: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => rd_data_sm_cs(1), I1 => rd_data_sm_cs(0), O => act_rd_burst_i_5_n_0 ); act_rd_burst_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => act_rd_burst_i_1_n_0, Q => act_rd_burst, R => '0' ); act_rd_burst_two_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"00000000E2EEE222" ) port map ( I0 => act_rd_burst_two, I1 => act_rd_burst_set, I2 => axi_rd_burst_two, I3 => bram_addr_ld_en, I4 => axi_rd_burst_two_reg_n_0, I5 => act_rd_burst_i_3_n_0, O => act_rd_burst_two_i_1_n_0 ); act_rd_burst_two_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => act_rd_burst_two_i_1_n_0, Q => act_rd_burst_two, R => '0' ); axi_arsize_pipe_max_i_1: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => araddr_pipe_ld43_out, I1 => axi_arsize_pipe_max, O => axi_arsize_pipe_max_i_1_n_0 ); axi_arsize_pipe_max_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => axi_arsize_pipe_max_i_1_n_0, Q => axi_arsize_pipe_max, R => \^bram_rst_a\ ); axi_b2b_brst_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"F000F074F0F0F074" ) port map ( I0 => I_WRAP_BRST_n_27, I1 => axi_b2b_brst_i_2_n_0, I2 => axi_b2b_brst, I3 => rd_data_sm_cs(3), I4 => rd_data_sm_cs(2), I5 => disable_b2b_brst_i_2_n_0, O => axi_b2b_brst_i_1_n_0 ); axi_b2b_brst_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"00000000AA080000" ) port map ( I0 => \rd_data_sm_cs[0]_i_3_n_0\, I1 => end_brst_rd, I2 => axi_b2b_brst, I3 => brst_zero, I4 => rd_adv_buf67_out, I5 => I_WRAP_BRST_n_27, O => axi_b2b_brst_i_2_n_0 ); axi_b2b_brst_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => axi_b2b_brst_i_1_n_0, Q => axi_b2b_brst, R => \^bram_rst_a\ ); axi_rd_burst_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"303000A0" ) port map ( I0 => axi_rd_burst, I1 => axi_rd_burst_i_2_n_0, I2 => s_axi_aresetn, I3 => brst_zero, I4 => bram_addr_ld_en, O => axi_rd_burst_i_1_n_0 ); axi_rd_burst_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0000000001000111" ) port map ( I0 => I_WRAP_BRST_n_2, I1 => I_WRAP_BRST_n_5, I2 => axi_arlen_pipe(1), I3 => axi_araddr_full, I4 => s_axi_arlen(1), I5 => axi_rd_burst_i_3_n_0, O => axi_rd_burst_i_2_n_0 ); axi_rd_burst_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFBBFCB8" ) port map ( I0 => axi_arlen_pipe(5), I1 => axi_araddr_full, I2 => s_axi_arlen(5), I3 => axi_arlen_pipe(4), I4 => s_axi_arlen(4), I5 => last_bram_addr_i_9_n_0, O => axi_rd_burst_i_3_n_0 ); axi_rd_burst_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => axi_rd_burst_i_1_n_0, Q => axi_rd_burst, R => '0' ); axi_rd_burst_two_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"C0C000A0" ) port map ( I0 => axi_rd_burst_two_reg_n_0, I1 => axi_rd_burst_two, I2 => s_axi_aresetn, I3 => brst_zero, I4 => bram_addr_ld_en, O => axi_rd_burst_two_i_1_n_0 ); axi_rd_burst_two_i_2: unisim.vcomponents.LUT4 generic map( INIT => X"A808" ) port map ( I0 => axi_rd_burst_i_2_n_0, I1 => s_axi_arlen(0), I2 => axi_araddr_full, I3 => axi_arlen_pipe(0), O => axi_rd_burst_two ); axi_rd_burst_two_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => axi_rd_burst_two_i_1_n_0, Q => axi_rd_burst_two_reg_n_0, R => '0' ); axi_rlast_int_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"88A8" ) port map ( I0 => s_axi_aresetn, I1 => axi_rlast_set, I2 => \^s_axi_rlast\, I3 => s_axi_rready, O => axi_rlast_int_i_1_n_0 ); axi_rlast_int_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => axi_rlast_int_i_1_n_0, Q => \^s_axi_rlast\, R => '0' ); axi_rvalid_clr_ok_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"00000000FFFFEEEA" ) port map ( I0 => axi_rvalid_clr_ok, I1 => last_bram_addr, I2 => disable_b2b_brst, I3 => disable_b2b_brst_cmb, I4 => axi_rvalid_clr_ok_i_2_n_0, I5 => axi_rvalid_clr_ok_i_3_n_0, O => axi_rvalid_clr_ok_i_1_n_0 ); axi_rvalid_clr_ok_i_2: unisim.vcomponents.LUT5 generic map( INIT => X"AAAAAEAA" ) port map ( I0 => bram_addr_ld_en, I1 => rd_data_sm_cs(0), I2 => rd_data_sm_cs(1), I3 => rd_data_sm_cs(2), I4 => rd_data_sm_cs(3), O => axi_rvalid_clr_ok_i_2_n_0 ); axi_rvalid_clr_ok_i_3: unisim.vcomponents.LUT3 generic map( INIT => X"4F" ) port map ( I0 => \GEN_ARREADY.axi_early_arready_int_i_4_n_0\, I1 => bram_addr_ld_en, I2 => s_axi_aresetn, O => axi_rvalid_clr_ok_i_3_n_0 ); axi_rvalid_clr_ok_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => axi_rvalid_clr_ok_i_1_n_0, Q => axi_rvalid_clr_ok, R => '0' ); axi_rvalid_int_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"00E0E0E0E0E0E0E0" ) port map ( I0 => \^s_axi_rvalid\, I1 => axi_rvalid_set, I2 => s_axi_aresetn, I3 => axi_rvalid_clr_ok, I4 => \^s_axi_rlast\, I5 => s_axi_rready, O => axi_rvalid_int_i_1_n_0 ); axi_rvalid_int_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => axi_rvalid_int_i_1_n_0, Q => \^s_axi_rvalid\, R => '0' ); axi_rvalid_set_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"0100" ) port map ( I0 => rd_data_sm_cs(2), I1 => rd_data_sm_cs(3), I2 => rd_data_sm_cs(1), I3 => rd_data_sm_cs(0), O => axi_rvalid_set_cmb ); axi_rvalid_set_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => axi_rvalid_set_cmb, Q => axi_rvalid_set, R => \^bram_rst_a\ ); bram_en_int_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFEEFFFA0022000A" ) port map ( I0 => bram_en_int_i_2_n_0, I1 => bram_en_int_i_3_n_0, I2 => bram_en_int_i_4_n_0, I3 => rd_data_sm_cs(3), I4 => rd_data_sm_cs(2), I5 => \^bram_en_b\, O => bram_en_int_i_1_n_0 ); bram_en_int_i_10: unisim.vcomponents.LUT5 generic map( INIT => X"E0000000" ) port map ( I0 => act_rd_burst, I1 => act_rd_burst_two, I2 => \^s_axi_rvalid\, I3 => s_axi_rready, I4 => bram_addr_ld_en, O => bram_en_int_i_10_n_0 ); bram_en_int_i_11: unisim.vcomponents.LUT4 generic map( INIT => X"0111" ) port map ( I0 => end_brst_rd, I1 => brst_zero, I2 => s_axi_rready, I3 => \^s_axi_rvalid\, O => bram_en_int_i_11_n_0 ); bram_en_int_i_12: unisim.vcomponents.LUT6 generic map( INIT => X"BFFFBFBFBFFFBFFF" ) port map ( I0 => I_WRAP_BRST_n_27, I1 => \^s_axi_rvalid\, I2 => s_axi_rready, I3 => brst_zero, I4 => axi_b2b_brst, I5 => end_brst_rd, O => bram_en_int_i_12_n_0 ); bram_en_int_i_13: unisim.vcomponents.LUT3 generic map( INIT => X"45" ) port map ( I0 => brst_zero, I1 => axi_b2b_brst, I2 => end_brst_rd, O => bram_en_int_i_13_n_0 ); bram_en_int_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFFFFF4044" ) port map ( I0 => bram_en_int_i_5_n_0, I1 => rd_data_sm_cs(1), I2 => bram_en_int_i_6_n_0, I3 => rd_data_sm_cs(2), I4 => bram_en_int_i_7_n_0, I5 => I_WRAP_BRST_n_0, O => bram_en_int_i_2_n_0 ); bram_en_int_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"707370707C7F7C7C" ) port map ( I0 => bram_en_int_i_6_n_0, I1 => rd_data_sm_cs(0), I2 => rd_data_sm_cs(1), I3 => rd_adv_buf67_out, I4 => bram_en_int_i_9_n_0, I5 => bram_en_int_i_10_n_0, O => bram_en_int_i_3_n_0 ); bram_en_int_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"A0001111AAAA1111" ) port map ( I0 => rd_data_sm_cs(0), I1 => bram_addr_ld_en, I2 => bram_en_int_i_11_n_0, I3 => brst_one, I4 => rd_data_sm_cs(1), I5 => bram_en_int_i_12_n_0, O => bram_en_int_i_4_n_0 ); bram_en_int_i_5: unisim.vcomponents.LUT6 generic map( INIT => X"0044054455440544" ) port map ( I0 => rd_data_sm_cs(2), I1 => axi_rd_burst_two_reg_n_0, I2 => bram_en_int_i_9_n_0, I3 => rd_data_sm_cs(0), I4 => rd_adv_buf67_out, I5 => bram_en_int_i_13_n_0, O => bram_en_int_i_5_n_0 ); bram_en_int_i_6: unisim.vcomponents.LUT4 generic map( INIT => X"ECCC" ) port map ( I0 => pend_rd_op, I1 => bram_addr_ld_en, I2 => \^s_axi_rvalid\, I3 => s_axi_rready, O => bram_en_int_i_6_n_0 ); bram_en_int_i_7: unisim.vcomponents.LUT6 generic map( INIT => X"5554005500540000" ) port map ( I0 => rd_data_sm_cs(1), I1 => axi_rd_burst_two_reg_n_0, I2 => axi_rd_burst, I3 => rd_data_sm_cs(2), I4 => rd_data_sm_cs(0), I5 => bram_addr_ld_en, O => bram_en_int_i_7_n_0 ); bram_en_int_i_9: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => brst_zero, I1 => end_brst_rd, O => bram_en_int_i_9_n_0 ); bram_en_int_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => bram_en_int_i_1_n_0, Q => \^bram_en_b\, R => \^bram_rst_a\ ); \brst_cnt[0]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"D1DDD111" ) port map ( I0 => brst_cnt(0), I1 => bram_addr_ld_en, I2 => axi_arlen_pipe(0), I3 => axi_araddr_full, I4 => s_axi_arlen(0), O => \brst_cnt[0]_i_1_n_0\ ); \brst_cnt[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"B8FFB800B800B8FF" ) port map ( I0 => axi_arlen_pipe(1), I1 => axi_araddr_full, I2 => s_axi_arlen(1), I3 => bram_addr_ld_en, I4 => brst_cnt(0), I5 => brst_cnt(1), O => \brst_cnt[1]_i_1_n_0\ ); \brst_cnt[2]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B8B8B88B" ) port map ( I0 => I_WRAP_BRST_n_2, I1 => bram_addr_ld_en, I2 => brst_cnt(2), I3 => brst_cnt(1), I4 => brst_cnt(0), O => \brst_cnt[2]_i_1_n_0\ ); \brst_cnt[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"B8B8B8B8B8B8B88B" ) port map ( I0 => I_WRAP_BRST_n_5, I1 => bram_addr_ld_en, I2 => brst_cnt(3), I3 => brst_cnt(2), I4 => brst_cnt(0), I5 => brst_cnt(1), O => \brst_cnt[3]_i_1_n_0\ ); \brst_cnt[4]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"B8FFB800B800B8FF" ) port map ( I0 => axi_arlen_pipe(4), I1 => axi_araddr_full, I2 => s_axi_arlen(4), I3 => bram_addr_ld_en, I4 => brst_cnt(4), I5 => \brst_cnt[4]_i_2_n_0\, O => \brst_cnt[4]_i_1_n_0\ ); \brst_cnt[4]_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"FFFE" ) port map ( I0 => brst_cnt(3), I1 => brst_cnt(2), I2 => brst_cnt(0), I3 => brst_cnt(1), O => \brst_cnt[4]_i_2_n_0\ ); \brst_cnt[5]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"B800B8FFB8FFB800" ) port map ( I0 => axi_arlen_pipe(5), I1 => axi_araddr_full, I2 => s_axi_arlen(5), I3 => bram_addr_ld_en, I4 => brst_cnt(5), I5 => \brst_cnt[7]_i_4_n_0\, O => \brst_cnt[5]_i_1_n_0\ ); \brst_cnt[6]_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"B88BB8B8" ) port map ( I0 => \brst_cnt[6]_i_2_n_0\, I1 => bram_addr_ld_en, I2 => brst_cnt(6), I3 => brst_cnt(5), I4 => \brst_cnt[7]_i_4_n_0\, O => \brst_cnt[6]_i_1_n_0\ ); \brst_cnt[6]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axi_arlen_pipe(6), I1 => axi_araddr_full, I2 => s_axi_arlen(6), O => \brst_cnt[6]_i_2_n_0\ ); \brst_cnt[7]_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => bram_addr_ld_en, I1 => I_WRAP_BRST_n_8, O => \brst_cnt[7]_i_1_n_0\ ); \brst_cnt[7]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"B8B8B88BB8B8B8B8" ) port map ( I0 => \brst_cnt[7]_i_3_n_0\, I1 => bram_addr_ld_en, I2 => brst_cnt(7), I3 => brst_cnt(6), I4 => brst_cnt(5), I5 => \brst_cnt[7]_i_4_n_0\, O => \brst_cnt[7]_i_2_n_0\ ); \brst_cnt[7]_i_3\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axi_arlen_pipe(7), I1 => axi_araddr_full, I2 => s_axi_arlen(7), O => \brst_cnt[7]_i_3_n_0\ ); \brst_cnt[7]_i_4\: unisim.vcomponents.LUT5 generic map( INIT => X"00000001" ) port map ( I0 => brst_cnt(4), I1 => brst_cnt(1), I2 => brst_cnt(0), I3 => brst_cnt(2), I4 => brst_cnt(3), O => \brst_cnt[7]_i_4_n_0\ ); brst_cnt_max_d1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => brst_cnt_max, Q => brst_cnt_max_d1, R => \^bram_rst_a\ ); \brst_cnt_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \brst_cnt[7]_i_1_n_0\, D => \brst_cnt[0]_i_1_n_0\, Q => brst_cnt(0), R => \^bram_rst_a\ ); \brst_cnt_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \brst_cnt[7]_i_1_n_0\, D => \brst_cnt[1]_i_1_n_0\, Q => brst_cnt(1), R => \^bram_rst_a\ ); \brst_cnt_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \brst_cnt[7]_i_1_n_0\, D => \brst_cnt[2]_i_1_n_0\, Q => brst_cnt(2), R => \^bram_rst_a\ ); \brst_cnt_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \brst_cnt[7]_i_1_n_0\, D => \brst_cnt[3]_i_1_n_0\, Q => brst_cnt(3), R => \^bram_rst_a\ ); \brst_cnt_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \brst_cnt[7]_i_1_n_0\, D => \brst_cnt[4]_i_1_n_0\, Q => brst_cnt(4), R => \^bram_rst_a\ ); \brst_cnt_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \brst_cnt[7]_i_1_n_0\, D => \brst_cnt[5]_i_1_n_0\, Q => brst_cnt(5), R => \^bram_rst_a\ ); \brst_cnt_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \brst_cnt[7]_i_1_n_0\, D => \brst_cnt[6]_i_1_n_0\, Q => brst_cnt(6), R => \^bram_rst_a\ ); \brst_cnt_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \brst_cnt[7]_i_1_n_0\, D => \brst_cnt[7]_i_2_n_0\, Q => brst_cnt(7), R => \^bram_rst_a\ ); brst_one_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"00000000F0EE0000" ) port map ( I0 => brst_one, I1 => brst_one_i_2_n_0, I2 => axi_rd_burst_two, I3 => bram_addr_ld_en, I4 => s_axi_aresetn, I5 => last_bram_addr_i_2_n_0, O => brst_one_i_1_n_0 ); brst_one_i_2: unisim.vcomponents.LUT3 generic map( INIT => X"08" ) port map ( I0 => last_bram_addr_i_5_n_0, I1 => brst_cnt(1), I2 => brst_cnt(0), O => brst_one_i_2_n_0 ); brst_one_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => brst_one_i_1_n_0, Q => brst_one, R => '0' ); brst_zero_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"00E0" ) port map ( I0 => brst_zero, I1 => last_bram_addr_i_2_n_0, I2 => s_axi_aresetn, I3 => brst_zero_i_2_n_0, O => brst_zero_i_1_n_0 ); brst_zero_i_2: unisim.vcomponents.LUT5 generic map( INIT => X"8A80AAAA" ) port map ( I0 => bram_addr_ld_en, I1 => axi_arlen_pipe(0), I2 => axi_araddr_full, I3 => s_axi_arlen(0), I4 => axi_rd_burst_i_2_n_0, O => brst_zero_i_2_n_0 ); brst_zero_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => brst_zero_i_1_n_0, Q => brst_zero, R => '0' ); curr_fixed_burst_reg_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"00053305" ) port map ( I0 => s_axi_arburst(0), I1 => axi_arburst_pipe(0), I2 => s_axi_arburst(1), I3 => axi_araddr_full, I4 => axi_arburst_pipe(1), O => curr_fixed_burst ); curr_fixed_burst_reg_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => bram_addr_ld_en, D => curr_fixed_burst, Q => curr_fixed_burst_reg, R => \^bram_rst_a\ ); curr_wrap_burst_reg_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"000ACC0A" ) port map ( I0 => s_axi_arburst(1), I1 => axi_arburst_pipe(1), I2 => s_axi_arburst(0), I3 => axi_araddr_full, I4 => axi_arburst_pipe(0), O => curr_wrap_burst ); curr_wrap_burst_reg_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => bram_addr_ld_en, D => curr_wrap_burst, Q => curr_wrap_burst_reg, R => \^bram_rst_a\ ); disable_b2b_brst_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF000D0000" ) port map ( I0 => axi_rd_burst, I1 => axi_rd_burst_two_reg_n_0, I2 => rd_data_sm_cs(2), I3 => rd_data_sm_cs(3), I4 => disable_b2b_brst_i_2_n_0, I5 => disable_b2b_brst_i_3_n_0, O => disable_b2b_brst_cmb ); disable_b2b_brst_i_2: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => rd_data_sm_cs(0), I1 => rd_data_sm_cs(1), O => disable_b2b_brst_i_2_n_0 ); disable_b2b_brst_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"EEEEEEE00EE0EEEE" ) port map ( I0 => disable_b2b_brst_i_4_n_0, I1 => disable_b2b_brst, I2 => rd_data_sm_cs(2), I3 => rd_data_sm_cs(1), I4 => rd_data_sm_cs(0), I5 => rd_data_sm_cs(3), O => disable_b2b_brst_i_3_n_0 ); disable_b2b_brst_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"0000FE0000000000" ) port map ( I0 => brst_zero, I1 => end_brst_rd, I2 => brst_one, I3 => rd_data_sm_cs(0), I4 => rd_adv_buf67_out, I5 => \rd_data_sm_cs[2]_i_3_n_0\, O => disable_b2b_brst_i_4_n_0 ); disable_b2b_brst_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => disable_b2b_brst_cmb, Q => disable_b2b_brst, R => \^bram_rst_a\ ); end_brst_rd_clr_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFCD00002200" ) port map ( I0 => rd_data_sm_cs(0), I1 => rd_data_sm_cs(1), I2 => bram_addr_ld_en, I3 => rd_data_sm_cs(2), I4 => rd_data_sm_cs(3), I5 => end_brst_rd_clr, O => end_brst_rd_clr_i_1_n_0 ); end_brst_rd_clr_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => end_brst_rd_clr_i_1_n_0, Q => end_brst_rd_clr, R => \^bram_rst_a\ ); end_brst_rd_i_1: unisim.vcomponents.LUT5 generic map( INIT => X"0020F020" ) port map ( I0 => brst_cnt_max, I1 => brst_cnt_max_d1, I2 => s_axi_aresetn, I3 => end_brst_rd, I4 => end_brst_rd_clr, O => end_brst_rd_i_1_n_0 ); end_brst_rd_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => end_brst_rd_i_1_n_0, Q => end_brst_rd, R => '0' ); last_bram_addr_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"FAAAAAAAAAAAAFAB" ) port map ( I0 => last_bram_addr_i_2_n_0, I1 => last_bram_addr_i_3_n_0, I2 => rd_data_sm_cs(2), I3 => last_bram_addr_i_4_n_0, I4 => rd_data_sm_cs(1), I5 => rd_data_sm_cs(0), O => last_bram_addr0 ); last_bram_addr_i_2: unisim.vcomponents.LUT3 generic map( INIT => X"08" ) port map ( I0 => last_bram_addr_i_5_n_0, I1 => brst_cnt(0), I2 => brst_cnt(1), O => last_bram_addr_i_2_n_0 ); last_bram_addr_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"7F7F707F7F7F7F7F" ) port map ( I0 => p_0_in13_in, I1 => rd_adv_buf67_out, I2 => rd_data_sm_cs(3), I3 => bram_addr_ld_en, I4 => I_WRAP_BRST_n_4, I5 => axi_rd_burst_i_2_n_0, O => last_bram_addr_i_3_n_0 ); last_bram_addr_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"A888200000000000" ) port map ( I0 => rd_adv_buf67_out, I1 => bram_addr_ld_en, I2 => pend_rd_op, I3 => p_0_in13_in, I4 => last_bram_addr_i_6_n_0, I5 => \rd_data_sm_cs[3]_i_6_n_0\, O => last_bram_addr_i_4_n_0 ); last_bram_addr_i_5: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000002" ) port map ( I0 => I_WRAP_BRST_n_8, I1 => brst_cnt(7), I2 => brst_cnt(3), I3 => brst_cnt(4), I4 => brst_cnt(2), I5 => last_bram_addr_i_7_n_0, O => last_bram_addr_i_5_n_0 ); last_bram_addr_i_6: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000001" ) port map ( I0 => last_bram_addr_i_8_n_0, I1 => last_bram_addr_i_9_n_0, I2 => I_WRAP_BRST_n_3, I3 => I_WRAP_BRST_n_5, I4 => I_WRAP_BRST_n_2, I5 => I_WRAP_BRST_n_4, O => last_bram_addr_i_6_n_0 ); last_bram_addr_i_7: unisim.vcomponents.LUT2 generic map( INIT => X"E" ) port map ( I0 => brst_cnt(6), I1 => brst_cnt(5), O => last_bram_addr_i_7_n_0 ); last_bram_addr_i_8: unisim.vcomponents.LUT5 generic map( INIT => X"FFFACCFA" ) port map ( I0 => s_axi_arlen(4), I1 => axi_arlen_pipe(4), I2 => s_axi_arlen(5), I3 => axi_araddr_full, I4 => axi_arlen_pipe(5), O => last_bram_addr_i_8_n_0 ); last_bram_addr_i_9: unisim.vcomponents.LUT5 generic map( INIT => X"FFFACCFA" ) port map ( I0 => s_axi_arlen(6), I1 => axi_arlen_pipe(6), I2 => s_axi_arlen(7), I3 => axi_araddr_full, I4 => axi_arlen_pipe(7), O => last_bram_addr_i_9_n_0 ); last_bram_addr_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => last_bram_addr0, Q => last_bram_addr, R => \^bram_rst_a\ ); no_ar_ack_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"88C8AAAAAAAAAAAA" ) port map ( I0 => no_ar_ack, I1 => rd_data_sm_cs(1), I2 => bram_addr_ld_en, I3 => rd_adv_buf67_out, I4 => \rd_data_sm_cs[3]_i_6_n_0\, I5 => rd_data_sm_cs(0), O => no_ar_ack_i_1_n_0 ); no_ar_ack_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => no_ar_ack_i_1_n_0, Q => no_ar_ack, R => \^bram_rst_a\ ); pend_rd_op_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAFFFEAAAA0002" ) port map ( I0 => pend_rd_op_i_2_n_0, I1 => pend_rd_op_i_3_n_0, I2 => rd_data_sm_cs(3), I3 => rd_data_sm_cs(2), I4 => pend_rd_op_i_4_n_0, I5 => pend_rd_op, O => pend_rd_op_i_1_n_0 ); pend_rd_op_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"0FFCC8C80CCCC8C8" ) port map ( I0 => p_0_in13_in, I1 => bram_addr_ld_en, I2 => rd_data_sm_cs(1), I3 => rd_data_sm_cs(0), I4 => rd_data_sm_cs(2), I5 => pend_rd_op_i_5_n_0, O => pend_rd_op_i_2_n_0 ); pend_rd_op_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"0303070733F3FFFF" ) port map ( I0 => p_0_in13_in, I1 => rd_data_sm_cs(0), I2 => rd_data_sm_cs(1), I3 => \^s_axi_rlast\, I4 => pend_rd_op, I5 => bram_addr_ld_en, O => pend_rd_op_i_3_n_0 ); pend_rd_op_i_4: unisim.vcomponents.LUT6 generic map( INIT => X"0000000080FFD5FF" ) port map ( I0 => rd_data_sm_cs(0), I1 => rd_adv_buf67_out, I2 => pend_rd_op, I3 => rd_data_sm_cs(1), I4 => pend_rd_op_i_6_n_0, I5 => pend_rd_op_i_7_n_0, O => pend_rd_op_i_4_n_0 ); pend_rd_op_i_5: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => ar_active, I1 => end_brst_rd, O => pend_rd_op_i_5_n_0 ); pend_rd_op_i_6: unisim.vcomponents.LUT3 generic map( INIT => X"15" ) port map ( I0 => bram_addr_ld_en, I1 => end_brst_rd, I2 => ar_active, O => pend_rd_op_i_6_n_0 ); pend_rd_op_i_7: unisim.vcomponents.LUT4 generic map( INIT => X"F1FF" ) port map ( I0 => pend_rd_op_i_8_n_0, I1 => bram_addr_ld_en, I2 => rd_data_sm_cs(3), I3 => rd_data_sm_cs(2), O => pend_rd_op_i_7_n_0 ); pend_rd_op_i_8: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFF0008888" ) port map ( I0 => pend_rd_op, I1 => \^s_axi_rlast\, I2 => ar_active, I3 => end_brst_rd, I4 => rd_data_sm_cs(0), I5 => rd_data_sm_cs(1), O => pend_rd_op_i_8_n_0 ); pend_rd_op_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => pend_rd_op_i_1_n_0, Q => pend_rd_op, R => \^bram_rst_a\ ); \rd_data_sm_cs[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFF54005555" ) port map ( I0 => \rd_data_sm_cs[0]_i_2_n_0\, I1 => pend_rd_op, I2 => bram_addr_ld_en, I3 => rd_adv_buf67_out, I4 => \rd_data_sm_cs[0]_i_3_n_0\, I5 => \rd_data_sm_cs[0]_i_4_n_0\, O => \rd_data_sm_cs[0]_i_1_n_0\ ); \rd_data_sm_cs[0]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"E000E0E0FFFFFFFF" ) port map ( I0 => act_rd_burst_two, I1 => act_rd_burst, I2 => disable_b2b_brst_i_2_n_0, I3 => bram_addr_ld_en, I4 => rd_adv_buf67_out, I5 => \rd_data_sm_cs[3]_i_6_n_0\, O => \rd_data_sm_cs[0]_i_2_n_0\ ); \rd_data_sm_cs[0]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => rd_data_sm_cs(1), I1 => rd_data_sm_cs(0), O => \rd_data_sm_cs[0]_i_3_n_0\ ); \rd_data_sm_cs[0]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"001100F7001100D5" ) port map ( I0 => rd_data_sm_cs(0), I1 => rd_data_sm_cs(1), I2 => rd_adv_buf67_out, I3 => rd_data_sm_cs(2), I4 => rd_data_sm_cs(3), I5 => p_0_in13_in, O => \rd_data_sm_cs[0]_i_4_n_0\ ); \rd_data_sm_cs[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"AAAEAAAEFFFFAAAE" ) port map ( I0 => \rd_data_sm_cs[2]_i_2_n_0\, I1 => \rd_data_sm_cs[1]_i_2_n_0\, I2 => end_brst_rd, I3 => brst_zero, I4 => I_WRAP_BRST_n_25, I5 => \rd_data_sm_cs[2]_i_4_n_0\, O => \rd_data_sm_cs[1]_i_1_n_0\ ); \rd_data_sm_cs[1]_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"04" ) port map ( I0 => rd_data_sm_cs(3), I1 => rd_data_sm_cs(2), I2 => rd_data_sm_cs(0), O => \rd_data_sm_cs[1]_i_2_n_0\ ); \rd_data_sm_cs[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFFFFFEEEAEAEA" ) port map ( I0 => \rd_data_sm_cs[2]_i_2_n_0\, I1 => \rd_data_sm_cs[2]_i_3_n_0\, I2 => \rd_data_sm_cs[2]_i_4_n_0\, I3 => p_0_in13_in, I4 => disable_b2b_brst_i_2_n_0, I5 => \rd_data_sm_cs[2]_i_5_n_0\, O => \rd_data_sm_cs[2]_i_1_n_0\ ); \rd_data_sm_cs[2]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"000007000F000000" ) port map ( I0 => \rd_data_sm_cs[3]_i_7_n_0\, I1 => bram_addr_ld_en, I2 => rd_data_sm_cs(3), I3 => rd_data_sm_cs(2), I4 => rd_data_sm_cs(1), I5 => rd_data_sm_cs(0), O => \rd_data_sm_cs[2]_i_2_n_0\ ); \rd_data_sm_cs[2]_i_3\: unisim.vcomponents.LUT2 generic map( INIT => X"1" ) port map ( I0 => rd_data_sm_cs(3), I1 => rd_data_sm_cs(2), O => \rd_data_sm_cs[2]_i_3_n_0\ ); \rd_data_sm_cs[2]_i_4\: unisim.vcomponents.LUT6 generic map( INIT => X"C8C8C8C808C8C8C8" ) port map ( I0 => axi_rd_burst_two_reg_n_0, I1 => rd_data_sm_cs(1), I2 => rd_data_sm_cs(0), I3 => s_axi_rready, I4 => \^s_axi_rvalid\, I5 => I_WRAP_BRST_n_27, O => \rd_data_sm_cs[2]_i_4_n_0\ ); \rd_data_sm_cs[2]_i_5\: unisim.vcomponents.LUT6 generic map( INIT => X"0004000400040000" ) port map ( I0 => rd_data_sm_cs(3), I1 => rd_data_sm_cs(2), I2 => rd_data_sm_cs(1), I3 => rd_data_sm_cs(0), I4 => brst_zero, I5 => end_brst_rd, O => \rd_data_sm_cs[2]_i_5_n_0\ ); \rd_data_sm_cs[3]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"7444777730007444" ) port map ( I0 => \rd_data_sm_cs[3]_i_3_n_0\, I1 => \rd_data_sm_cs[3]_i_4_n_0\, I2 => s_axi_rready, I3 => \^s_axi_rvalid\, I4 => \rd_data_sm_cs[3]_i_5_n_0\, I5 => bram_addr_ld_en, O => rd_data_sm_ns ); \rd_data_sm_cs[3]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"00800000AA800000" ) port map ( I0 => \rd_data_sm_cs[3]_i_6_n_0\, I1 => bram_addr_ld_en, I2 => \rd_data_sm_cs[3]_i_7_n_0\, I3 => rd_data_sm_cs(1), I4 => rd_data_sm_cs(0), I5 => rd_adv_buf67_out, O => \rd_data_sm_cs[3]_i_2_n_0\ ); \rd_data_sm_cs[3]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"00000D0000000000" ) port map ( I0 => end_brst_rd, I1 => axi_b2b_brst, I2 => brst_zero, I3 => rd_adv_buf67_out, I4 => rd_data_sm_cs(3), I5 => \rd_data_sm_cs[0]_i_3_n_0\, O => \rd_data_sm_cs[3]_i_3_n_0\ ); \rd_data_sm_cs[3]_i_4\: unisim.vcomponents.LUT4 generic map( INIT => X"BFAD" ) port map ( I0 => rd_data_sm_cs(3), I1 => rd_data_sm_cs(1), I2 => rd_data_sm_cs(2), I3 => rd_data_sm_cs(0), O => \rd_data_sm_cs[3]_i_4_n_0\ ); \rd_data_sm_cs[3]_i_5\: unisim.vcomponents.LUT4 generic map( INIT => X"0053" ) port map ( I0 => rd_data_sm_cs(3), I1 => rd_data_sm_cs(1), I2 => rd_data_sm_cs(2), I3 => rd_data_sm_cs(0), O => \rd_data_sm_cs[3]_i_5_n_0\ ); \rd_data_sm_cs[3]_i_6\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => rd_data_sm_cs(2), I1 => rd_data_sm_cs(3), O => \rd_data_sm_cs[3]_i_6_n_0\ ); \rd_data_sm_cs[3]_i_7\: unisim.vcomponents.LUT4 generic map( INIT => X"8880" ) port map ( I0 => s_axi_rready, I1 => \^s_axi_rvalid\, I2 => act_rd_burst_two, I3 => act_rd_burst, O => \rd_data_sm_cs[3]_i_7_n_0\ ); \rd_data_sm_cs_reg[0]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => rd_data_sm_ns, D => \rd_data_sm_cs[0]_i_1_n_0\, Q => rd_data_sm_cs(0), R => \^bram_rst_a\ ); \rd_data_sm_cs_reg[1]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => rd_data_sm_ns, D => \rd_data_sm_cs[1]_i_1_n_0\, Q => rd_data_sm_cs(1), R => \^bram_rst_a\ ); \rd_data_sm_cs_reg[2]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => rd_data_sm_ns, D => \rd_data_sm_cs[2]_i_1_n_0\, Q => rd_data_sm_cs(2), R => \^bram_rst_a\ ); \rd_data_sm_cs_reg[3]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => rd_data_sm_ns, D => \rd_data_sm_cs[3]_i_2_n_0\, Q => rd_data_sm_cs(3), R => \^bram_rst_a\ ); rd_skid_buf_ld_reg_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"1000111111110000" ) port map ( I0 => rd_data_sm_cs(3), I1 => rd_data_sm_cs(2), I2 => \^s_axi_rvalid\, I3 => s_axi_rready, I4 => rd_data_sm_cs(1), I5 => rd_data_sm_cs(0), O => rd_skid_buf_ld_cmb ); rd_skid_buf_ld_reg_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => rd_skid_buf_ld_cmb, Q => rd_skid_buf_ld_reg, R => \^bram_rst_a\ ); rddata_mux_sel_i_1: unisim.vcomponents.LUT4 generic map( INIT => X"FE02" ) port map ( I0 => rddata_mux_sel_cmb, I1 => rd_data_sm_cs(3), I2 => rddata_mux_sel_i_3_n_0, I3 => rddata_mux_sel, O => rddata_mux_sel_i_1_n_0 ); rddata_mux_sel_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"D208D208D208F208" ) port map ( I0 => rd_data_sm_cs(0), I1 => rd_data_sm_cs(1), I2 => rd_adv_buf67_out, I3 => rd_data_sm_cs(2), I4 => act_rd_burst, I5 => act_rd_burst_two, O => rddata_mux_sel_cmb ); rddata_mux_sel_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"A007AF07AF07AF07" ) port map ( I0 => rd_data_sm_cs(1), I1 => axi_rd_burst_two_reg_n_0, I2 => rd_data_sm_cs(0), I3 => rd_data_sm_cs(2), I4 => \^s_axi_rvalid\, I5 => s_axi_rready, O => rddata_mux_sel_i_3_n_0 ); rddata_mux_sel_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => rddata_mux_sel_i_1_n_0, Q => rddata_mux_sel, R => \^bram_rst_a\ ); s_axi_arready_INST_0: unisim.vcomponents.LUT4 generic map( INIT => X"EAAA" ) port map ( I0 => axi_arready_int, I1 => \^s_axi_rvalid\, I2 => s_axi_rready, I3 => axi_early_arready_int, O => s_axi_arready ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zqynq_lab_1_design_axi_bram_ctrl_0_0_wr_chnl is port ( axi_aresetn_d2 : out STD_LOGIC; axi_aresetn_re_reg : out STD_LOGIC; bram_en_a : out STD_LOGIC; bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_bvalid : out STD_LOGIC; \GEN_AW_DUAL.aw_active_reg_0\ : out STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 ); bram_addr_a : out STD_LOGIC_VECTOR ( 13 downto 0 ); bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_aresetn_0 : in STD_LOGIC; s_axi_aclk : in STD_LOGIC; s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 ); s_axi_aresetn : in STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wvalid : in STD_LOGIC; s_axi_wlast : in STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ) ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_bram_ctrl_0_0_wr_chnl : entity is "wr_chnl"; end zqynq_lab_1_design_axi_bram_ctrl_0_0_wr_chnl; architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0_wr_chnl is signal BID_FIFO_n_1 : STD_LOGIC; signal BID_FIFO_n_4 : STD_LOGIC; signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0\ : STD_LOGIC; signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0\ : STD_LOGIC; signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0\ : STD_LOGIC; signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0\ : STD_LOGIC; signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0\ : STD_LOGIC; signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0\ : STD_LOGIC; signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\ : STD_LOGIC; signal \GEN_AWREADY.axi_awready_int_i_1_n_0\ : STD_LOGIC; signal \GEN_AWREADY.axi_awready_int_i_2_n_0\ : STD_LOGIC; signal \GEN_AWREADY.axi_awready_int_i_3_n_0\ : STD_LOGIC; signal \GEN_AW_DUAL.aw_active_i_2_n_0\ : STD_LOGIC; signal \^gen_aw_dual.aw_active_reg_0\ : STD_LOGIC; signal \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0\ : STD_LOGIC; signal \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0\ : STD_LOGIC; signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\ : STD_LOGIC; signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\ : STD_LOGIC; signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\ : STD_LOGIC; signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\ : STD_LOGIC; signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\ : STD_LOGIC; signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\ : STD_LOGIC; signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\ : STD_LOGIC; signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\ : STD_LOGIC; signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\ : STD_LOGIC; signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\ : STD_LOGIC; signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\ : STD_LOGIC; signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\ : STD_LOGIC; signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\ : STD_LOGIC; signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\ : STD_LOGIC; signal \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0\ : STD_LOGIC; signal \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0\ : STD_LOGIC; signal \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\ : STD_LOGIC; signal \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\ : STD_LOGIC; signal \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\ : STD_LOGIC; signal \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0\ : STD_LOGIC; signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0\ : STD_LOGIC; signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\ : STD_LOGIC; signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0\ : STD_LOGIC; signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0\ : STD_LOGIC; signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0\ : STD_LOGIC; signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0\ : STD_LOGIC; signal \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\ : STD_LOGIC; signal \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\ : STD_LOGIC; signal \I_RD_CHNL/axi_aresetn_d1\ : STD_LOGIC; signal I_WRAP_BRST_n_0 : STD_LOGIC; signal I_WRAP_BRST_n_10 : STD_LOGIC; signal I_WRAP_BRST_n_11 : STD_LOGIC; signal I_WRAP_BRST_n_12 : STD_LOGIC; signal I_WRAP_BRST_n_13 : STD_LOGIC; signal I_WRAP_BRST_n_14 : STD_LOGIC; signal I_WRAP_BRST_n_15 : STD_LOGIC; signal I_WRAP_BRST_n_16 : STD_LOGIC; signal I_WRAP_BRST_n_17 : STD_LOGIC; signal I_WRAP_BRST_n_19 : STD_LOGIC; signal I_WRAP_BRST_n_2 : STD_LOGIC; signal I_WRAP_BRST_n_20 : STD_LOGIC; signal I_WRAP_BRST_n_21 : STD_LOGIC; signal I_WRAP_BRST_n_22 : STD_LOGIC; signal I_WRAP_BRST_n_23 : STD_LOGIC; signal I_WRAP_BRST_n_24 : STD_LOGIC; signal I_WRAP_BRST_n_25 : STD_LOGIC; signal I_WRAP_BRST_n_7 : STD_LOGIC; signal I_WRAP_BRST_n_8 : STD_LOGIC; signal I_WRAP_BRST_n_9 : STD_LOGIC; signal aw_active : STD_LOGIC; signal \^axi_aresetn_d2\ : STD_LOGIC; signal axi_aresetn_re : STD_LOGIC; signal \^axi_aresetn_re_reg\ : STD_LOGIC; signal axi_awaddr_full : STD_LOGIC; signal axi_awburst_pipe : STD_LOGIC_VECTOR ( 1 downto 0 ); signal axi_awid_pipe : STD_LOGIC; signal axi_awlen_pipe : STD_LOGIC_VECTOR ( 7 downto 0 ); signal axi_awlen_pipe_1_or_2 : STD_LOGIC; signal axi_awsize_pipe : STD_LOGIC_VECTOR ( 1 to 1 ); signal axi_bvalid_int_i_1_n_0 : STD_LOGIC; signal axi_wdata_full_cmb : STD_LOGIC; signal axi_wdata_full_cmb114_out : STD_LOGIC; signal axi_wdata_full_reg : STD_LOGIC; signal axi_wr_burst : STD_LOGIC; signal axi_wr_burst_cmb : STD_LOGIC; signal axi_wr_burst_cmb0 : STD_LOGIC; signal axi_wr_burst_i_1_n_0 : STD_LOGIC; signal axi_wr_burst_i_3_n_0 : STD_LOGIC; signal axi_wready_int_mod_i_1_n_0 : STD_LOGIC; signal axi_wready_int_mod_i_3_n_0 : STD_LOGIC; signal bid_gets_fifo_load : STD_LOGIC; signal bid_gets_fifo_load_d1 : STD_LOGIC; signal bid_gets_fifo_load_d1_i_2_n_0 : STD_LOGIC; signal \^bram_addr_a\ : STD_LOGIC_VECTOR ( 13 downto 0 ); signal bram_addr_inc : STD_LOGIC; signal bram_addr_ld : STD_LOGIC_VECTOR ( 13 downto 10 ); signal bram_addr_ld_en : STD_LOGIC; signal bram_addr_ld_en_mod : STD_LOGIC; signal bram_addr_rst_cmb : STD_LOGIC; signal bram_en_cmb : STD_LOGIC; signal bvalid_cnt : STD_LOGIC_VECTOR ( 2 downto 0 ); signal \bvalid_cnt[0]_i_1_n_0\ : STD_LOGIC; signal \bvalid_cnt[1]_i_1_n_0\ : STD_LOGIC; signal \bvalid_cnt[2]_i_1_n_0\ : STD_LOGIC; signal bvalid_cnt_inc : STD_LOGIC; signal bvalid_cnt_inc11_out : STD_LOGIC; signal clr_bram_we : STD_LOGIC; signal clr_bram_we_cmb : STD_LOGIC; signal curr_awlen_reg_1_or_2 : STD_LOGIC; signal curr_awlen_reg_1_or_20 : STD_LOGIC; signal curr_awlen_reg_1_or_2_i_2_n_0 : STD_LOGIC; signal curr_fixed_burst : STD_LOGIC; signal curr_fixed_burst_reg : STD_LOGIC; signal curr_wrap_burst : STD_LOGIC; signal curr_wrap_burst_reg : STD_LOGIC; signal delay_aw_active_clr : STD_LOGIC; signal last_data_ack_mod : STD_LOGIC; signal p_18_out : STD_LOGIC; signal p_9_out : STD_LOGIC; signal \^s_axi_awready\ : STD_LOGIC; signal \^s_axi_bid\ : STD_LOGIC_VECTOR ( 0 to 0 ); signal \^s_axi_bvalid\ : STD_LOGIC; signal \^s_axi_wready\ : STD_LOGIC; signal wr_addr_sm_cs : STD_LOGIC; signal wr_data_sm_cs : STD_LOGIC_VECTOR ( 2 downto 0 ); attribute RTL_KEEP : string; attribute RTL_KEEP of wr_data_sm_cs : signal is "yes"; attribute SOFT_HLUTNM : string; attribute SOFT_HLUTNM of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1\ : label is "soft_lutpair53"; attribute SOFT_HLUTNM of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_3\ : label is "soft_lutpair51"; attribute SOFT_HLUTNM of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1\ : label is "soft_lutpair53"; attribute KEEP : string; attribute KEEP of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[0]\ : label is "yes"; attribute KEEP of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[1]\ : label is "yes"; attribute KEEP of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[2]\ : label is "yes"; attribute SOFT_HLUTNM of \GEN_AW_DUAL.last_data_ack_mod_i_1\ : label is "soft_lutpair52"; attribute SOFT_HLUTNM of \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2\ : label is "soft_lutpair52"; attribute SOFT_HLUTNM of bid_gets_fifo_load_d1_i_2 : label is "soft_lutpair51"; attribute SOFT_HLUTNM of curr_fixed_burst_reg_i_2 : label is "soft_lutpair50"; attribute SOFT_HLUTNM of curr_wrap_burst_reg_i_2 : label is "soft_lutpair50"; begin \GEN_AW_DUAL.aw_active_reg_0\ <= \^gen_aw_dual.aw_active_reg_0\; axi_aresetn_d2 <= \^axi_aresetn_d2\; axi_aresetn_re_reg <= \^axi_aresetn_re_reg\; bram_addr_a(13 downto 0) <= \^bram_addr_a\(13 downto 0); s_axi_awready <= \^s_axi_awready\; s_axi_bid(0) <= \^s_axi_bid\(0); s_axi_bvalid <= \^s_axi_bvalid\; s_axi_wready <= \^s_axi_wready\; BID_FIFO: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_0_SRL_FIFO port map ( \GEN_AWREADY.axi_aresetn_d2_reg\ => \^axi_aresetn_d2\, \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\, aw_active => aw_active, axi_awaddr_full => axi_awaddr_full, axi_awid_pipe => axi_awid_pipe, axi_awlen_pipe_1_or_2 => axi_awlen_pipe_1_or_2, \axi_bid_int_reg[0]\ => BID_FIFO_n_4, axi_bvalid_int_reg => \^s_axi_bvalid\, axi_wdata_full_cmb114_out => axi_wdata_full_cmb114_out, axi_wr_burst => axi_wr_burst, bid_gets_fifo_load => bid_gets_fifo_load, bid_gets_fifo_load_d1 => bid_gets_fifo_load_d1, bid_gets_fifo_load_d1_reg => BID_FIFO_n_1, bram_addr_ld_en => bram_addr_ld_en, bvalid_cnt(2 downto 0) => bvalid_cnt(2 downto 0), bvalid_cnt_inc => bvalid_cnt_inc, \bvalid_cnt_reg[1]\ => bid_gets_fifo_load_d1_i_2_n_0, \bvalid_cnt_reg[2]\ => I_WRAP_BRST_n_20, \bvalid_cnt_reg[2]_0\ => I_WRAP_BRST_n_19, curr_awlen_reg_1_or_2 => curr_awlen_reg_1_or_2, last_data_ack_mod => last_data_ack_mod, \out\(2 downto 0) => wr_data_sm_cs(2 downto 0), s_axi_aclk => s_axi_aclk, s_axi_aresetn => s_axi_aresetn_0, s_axi_awid(0) => s_axi_awid(0), s_axi_awready => \^s_axi_awready\, s_axi_awvalid => s_axi_awvalid, s_axi_bid(0) => \^s_axi_bid\(0), s_axi_bready => s_axi_bready, s_axi_wlast => s_axi_wlast, s_axi_wvalid => s_axi_wvalid, wr_addr_sm_cs => wr_addr_sm_cs ); \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0\, I1 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\, I2 => wr_data_sm_cs(0), O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0\ ); \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"05051F1A" ) port map ( I0 => wr_data_sm_cs(1), I1 => axi_wr_burst_cmb0, I2 => wr_data_sm_cs(0), I3 => axi_wdata_full_cmb114_out, I4 => wr_data_sm_cs(2), O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0\ ); \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_3\: unisim.vcomponents.LUT4 generic map( INIT => X"5515" ) port map ( I0 => I_WRAP_BRST_n_21, I1 => bvalid_cnt(2), I2 => bvalid_cnt(1), I3 => bvalid_cnt(0), O => axi_wr_burst_cmb0 ); \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0\, I1 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\, I2 => wr_data_sm_cs(1), O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0\ ); \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"0000554000555540" ) port map ( I0 => wr_data_sm_cs(1), I1 => s_axi_wlast, I2 => axi_wdata_full_cmb114_out, I3 => wr_data_sm_cs(0), I4 => wr_data_sm_cs(2), I5 => axi_wr_burst, O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0\ ); \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0\, I1 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\, I2 => wr_data_sm_cs(2), O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0\ ); \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"44010001" ) port map ( I0 => wr_data_sm_cs(2), I1 => wr_data_sm_cs(1), I2 => axi_wdata_full_cmb114_out, I3 => wr_data_sm_cs(0), I4 => s_axi_wvalid, O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0\ ); \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"7774777774744444" ) port map ( I0 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\, I1 => wr_data_sm_cs(2), I2 => wr_data_sm_cs(1), I3 => s_axi_wlast, I4 => wr_data_sm_cs(0), I5 => s_axi_wvalid, O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\ ); \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[0]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0\, Q => wr_data_sm_cs(0), R => s_axi_aresetn_0 ); \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[1]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0\, Q => wr_data_sm_cs(1), R => s_axi_aresetn_0 ); \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[2]\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0\, Q => wr_data_sm_cs(2), R => s_axi_aresetn_0 ); \GEN_AWREADY.axi_aresetn_d1_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => s_axi_aresetn, Q => \I_RD_CHNL/axi_aresetn_d1\, R => '0' ); \GEN_AWREADY.axi_aresetn_d2_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \I_RD_CHNL/axi_aresetn_d1\, Q => \^axi_aresetn_d2\, R => '0' ); \GEN_AWREADY.axi_aresetn_re_reg_i_1\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => s_axi_aresetn, I1 => \I_RD_CHNL/axi_aresetn_d1\, O => axi_aresetn_re ); \GEN_AWREADY.axi_aresetn_re_reg_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => axi_aresetn_re, Q => \^axi_aresetn_re_reg\, R => '0' ); \GEN_AWREADY.axi_awready_int_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFBFBFFFFFAA00" ) port map ( I0 => axi_awaddr_full, I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\, I2 => \^axi_aresetn_d2\, I3 => bram_addr_ld_en, I4 => \^axi_aresetn_re_reg\, I5 => \^s_axi_awready\, O => \GEN_AWREADY.axi_awready_int_i_1_n_0\ ); \GEN_AWREADY.axi_awready_int_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"5444444400000000" ) port map ( I0 => \GEN_AWREADY.axi_awready_int_i_3_n_0\, I1 => aw_active, I2 => bvalid_cnt(1), I3 => bvalid_cnt(0), I4 => bvalid_cnt(2), I5 => s_axi_awvalid, O => \GEN_AWREADY.axi_awready_int_i_2_n_0\ ); \GEN_AWREADY.axi_awready_int_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"AABABABABABABABA" ) port map ( I0 => wr_addr_sm_cs, I1 => I_WRAP_BRST_n_21, I2 => last_data_ack_mod, I3 => bvalid_cnt(2), I4 => bvalid_cnt(0), I5 => bvalid_cnt(1), O => \GEN_AWREADY.axi_awready_int_i_3_n_0\ ); \GEN_AWREADY.axi_awready_int_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \GEN_AWREADY.axi_awready_int_i_1_n_0\, Q => \^s_axi_awready\, R => s_axi_aresetn_0 ); \GEN_AW_DUAL.aw_active_i_1\: unisim.vcomponents.LUT1 generic map( INIT => X"1" ) port map ( I0 => \^axi_aresetn_d2\, O => \^gen_aw_dual.aw_active_reg_0\ ); \GEN_AW_DUAL.aw_active_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"FFFFF7FFFFFF0000" ) port map ( I0 => wr_data_sm_cs(1), I1 => wr_data_sm_cs(0), I2 => wr_data_sm_cs(2), I3 => delay_aw_active_clr, I4 => bram_addr_ld_en, I5 => aw_active, O => \GEN_AW_DUAL.aw_active_i_2_n_0\ ); \GEN_AW_DUAL.aw_active_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \GEN_AW_DUAL.aw_active_i_2_n_0\, Q => aw_active, R => \^gen_aw_dual.aw_active_reg_0\ ); \GEN_AW_DUAL.last_data_ack_mod_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"80" ) port map ( I0 => \^s_axi_wready\, I1 => s_axi_wlast, I2 => s_axi_wvalid, O => p_18_out ); \GEN_AW_DUAL.last_data_ack_mod_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => p_18_out, Q => last_data_ack_mod, R => s_axi_aresetn_0 ); \GEN_AW_DUAL.wr_addr_sm_cs_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0010001000100000" ) port map ( I0 => \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0\, I1 => wr_addr_sm_cs, I2 => s_axi_awvalid, I3 => axi_awaddr_full, I4 => I_WRAP_BRST_n_20, I5 => aw_active, O => \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0\ ); \GEN_AW_DUAL.wr_addr_sm_cs_i_2\: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000040" ) port map ( I0 => I_WRAP_BRST_n_20, I1 => last_data_ack_mod, I2 => axi_awaddr_full, I3 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\, I4 => axi_awlen_pipe_1_or_2, I5 => curr_awlen_reg_1_or_2, O => \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0\ ); \GEN_AW_DUAL.wr_addr_sm_cs_reg\: unisim.vcomponents.FDRE port map ( C => s_axi_aclk, CE => '1', D => \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0\, Q => wr_addr_sm_cs, R => \^gen_aw_dual.aw_active_reg_0\ ); \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awaddr(8), Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\, R => '0' ); \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awaddr(9), Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\, R => '0' ); \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awaddr(10), Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\, R => '0' ); \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awaddr(11), Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\, R => '0' ); \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awaddr(12), Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\, R => '0' ); \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awaddr(13), Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\, R => '0' ); \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awaddr(0), Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\, R => '0' ); \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awaddr(1), Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\, R => '0' ); \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awaddr(2), Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\, R => '0' ); \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awaddr(3), Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\, R => '0' ); \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awaddr(4), Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\, R => '0' ); \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awaddr(5), Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\, R => '0' ); \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awaddr(6), Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\, R => '0' ); \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awaddr(7), Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\, R => '0' ); \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"4000EA00" ) port map ( I0 => axi_awaddr_full, I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\, I2 => \^axi_aresetn_d2\, I3 => s_axi_aresetn, I4 => bram_addr_ld_en, O => \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0\ ); \GEN_AW_PIPE_DUAL.axi_awaddr_full_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0\, Q => axi_awaddr_full, R => '0' ); \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"BF00BF00BF00FF40" ) port map ( I0 => axi_awaddr_full, I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\, I2 => \^axi_aresetn_d2\, I3 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\, I4 => s_axi_awburst(0), I5 => s_axi_awburst(1), O => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0\ ); \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0\, Q => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\, R => '0' ); \GEN_AW_PIPE_DUAL.axi_awburst_pipe_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awburst(0), Q => axi_awburst_pipe(0), R => '0' ); \GEN_AW_PIPE_DUAL.axi_awburst_pipe_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awburst(1), Q => axi_awburst_pipe(1), R => '0' ); \GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awid(0), Q => axi_awid_pipe, R => '0' ); \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1\: unisim.vcomponents.LUT3 generic map( INIT => X"40" ) port map ( I0 => axi_awaddr_full, I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\, I2 => \^axi_aresetn_d2\, O => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\ ); \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"0002" ) port map ( I0 => \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\, I1 => s_axi_awlen(3), I2 => s_axi_awlen(2), I3 => s_axi_awlen(1), O => p_9_out ); \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2\: unisim.vcomponents.LUT4 generic map( INIT => X"0001" ) port map ( I0 => s_axi_awlen(4), I1 => s_axi_awlen(6), I2 => s_axi_awlen(7), I3 => s_axi_awlen(5), O => \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\ ); \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => p_9_out, Q => axi_awlen_pipe_1_or_2, R => '0' ); \GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awlen(0), Q => axi_awlen_pipe(0), R => '0' ); \GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awlen(1), Q => axi_awlen_pipe(1), R => '0' ); \GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awlen(2), Q => axi_awlen_pipe(2), R => '0' ); \GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awlen(3), Q => axi_awlen_pipe(3), R => '0' ); \GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awlen(4), Q => axi_awlen_pipe(4), R => '0' ); \GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awlen(5), Q => axi_awlen_pipe(5), R => '0' ); \GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awlen(6), Q => axi_awlen_pipe(6), R => '0' ); \GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => s_axi_awlen(7), Q => axi_awlen_pipe(7), R => '0' ); \GEN_AW_PIPE_DUAL.axi_awsize_pipe_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\, D => '1', Q => axi_awsize_pipe(1), R => '0' ); \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0\: unisim.vcomponents.LUT6 generic map( INIT => X"7FFFFFFFFFFFFFFF" ) port map ( I0 => \^bram_addr_a\(4), I1 => \^bram_addr_a\(1), I2 => \^bram_addr_a\(0), I3 => \^bram_addr_a\(2), I4 => \^bram_addr_a\(3), I5 => \^bram_addr_a\(5), O => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0\ ); \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0\: unisim.vcomponents.LUT5 generic map( INIT => X"F7FFFFFF" ) port map ( I0 => \^bram_addr_a\(6), I1 => \^bram_addr_a\(4), I2 => I_WRAP_BRST_n_17, I3 => \^bram_addr_a\(5), I4 => \^bram_addr_a\(7), O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0\ ); \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4\: unisim.vcomponents.LUT4 generic map( INIT => X"1000" ) port map ( I0 => wr_data_sm_cs(1), I1 => wr_data_sm_cs(2), I2 => wr_data_sm_cs(0), I3 => s_axi_wvalid, O => bram_addr_inc ); \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5\: unisim.vcomponents.LUT4 generic map( INIT => X"1000" ) port map ( I0 => s_axi_wvalid, I1 => wr_data_sm_cs(2), I2 => wr_data_sm_cs(0), I3 => wr_data_sm_cs(1), O => bram_addr_rst_cmb ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => I_WRAP_BRST_n_2, D => I_WRAP_BRST_n_8, Q => \^bram_addr_a\(8), R => I_WRAP_BRST_n_0 ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => I_WRAP_BRST_n_2, D => I_WRAP_BRST_n_7, Q => \^bram_addr_a\(9), R => I_WRAP_BRST_n_0 ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => bram_addr_ld_en_mod, D => bram_addr_ld(10), Q => \^bram_addr_a\(10), R => I_WRAP_BRST_n_0 ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => bram_addr_ld_en_mod, D => bram_addr_ld(11), Q => \^bram_addr_a\(11), R => I_WRAP_BRST_n_0 ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => bram_addr_ld_en_mod, D => bram_addr_ld(12), Q => \^bram_addr_a\(12), R => I_WRAP_BRST_n_0 ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => bram_addr_ld_en_mod, D => bram_addr_ld(13), Q => \^bram_addr_a\(13), R => I_WRAP_BRST_n_0 ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => I_WRAP_BRST_n_2, D => I_WRAP_BRST_n_16, Q => \^bram_addr_a\(0), R => I_WRAP_BRST_n_0 ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => I_WRAP_BRST_n_2, D => I_WRAP_BRST_n_15, Q => \^bram_addr_a\(1), R => I_WRAP_BRST_n_0 ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => I_WRAP_BRST_n_2, D => I_WRAP_BRST_n_14, Q => \^bram_addr_a\(2), R => I_WRAP_BRST_n_0 ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => I_WRAP_BRST_n_2, D => I_WRAP_BRST_n_13, Q => \^bram_addr_a\(3), R => I_WRAP_BRST_n_0 ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => I_WRAP_BRST_n_2, D => I_WRAP_BRST_n_12, Q => \^bram_addr_a\(4), R => I_WRAP_BRST_n_0 ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => I_WRAP_BRST_n_2, D => I_WRAP_BRST_n_11, Q => \^bram_addr_a\(5), R => I_WRAP_BRST_n_0 ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => I_WRAP_BRST_n_2, D => I_WRAP_BRST_n_10, Q => \^bram_addr_a\(6), R => I_WRAP_BRST_n_0 ); \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => I_WRAP_BRST_n_2, D => I_WRAP_BRST_n_9, Q => \^bram_addr_a\(7), R => I_WRAP_BRST_n_0 ); \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.axi_wdata_full_reg_i_1\: unisim.vcomponents.LUT5 generic map( INIT => X"15FF1500" ) port map ( I0 => axi_wdata_full_cmb114_out, I1 => axi_awaddr_full, I2 => bram_addr_ld_en, I3 => wr_data_sm_cs(2), I4 => axi_wready_int_mod_i_3_n_0, O => axi_wdata_full_cmb ); \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.axi_wdata_full_reg_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => axi_wdata_full_cmb, Q => axi_wdata_full_reg, R => s_axi_aresetn_0 ); \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"4777477444444444" ) port map ( I0 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\, I1 => wr_data_sm_cs(2), I2 => wr_data_sm_cs(1), I3 => wr_data_sm_cs(0), I4 => axi_wdata_full_cmb114_out, I5 => s_axi_wvalid, O => bram_en_cmb ); \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"15" ) port map ( I0 => axi_wdata_full_cmb114_out, I1 => axi_awaddr_full, I2 => bram_addr_ld_en, O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\ ); \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => bram_en_cmb, Q => bram_en_a, R => s_axi_aresetn_0 ); \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"0010001000101110" ) port map ( I0 => wr_data_sm_cs(0), I1 => wr_data_sm_cs(1), I2 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0\, I3 => wr_data_sm_cs(2), I4 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\, I5 => axi_wr_burst, O => clr_bram_we_cmb ); \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2\: unisim.vcomponents.LUT3 generic map( INIT => X"80" ) port map ( I0 => axi_wdata_full_cmb114_out, I1 => s_axi_wlast, I2 => s_axi_wvalid, O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0\ ); \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => clr_bram_we_cmb, Q => clr_bram_we, R => s_axi_aresetn_0 ); \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"FEAAFEFF02AA0200" ) port map ( I0 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0\, I1 => axi_wr_burst, I2 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\, I3 => wr_data_sm_cs(2), I4 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0\, I5 => delay_aw_active_clr, O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0\ ); \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2\: unisim.vcomponents.LUT5 generic map( INIT => X"0000222E" ) port map ( I0 => s_axi_wlast, I1 => wr_data_sm_cs(2), I2 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\, I3 => wr_data_sm_cs(0), I4 => wr_data_sm_cs(1), O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0\ ); \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3\: unisim.vcomponents.LUT6 generic map( INIT => X"8B338B0088008800" ) port map ( I0 => delay_aw_active_clr, I1 => wr_data_sm_cs(1), I2 => axi_wr_burst_cmb0, I3 => wr_data_sm_cs(0), I4 => axi_wdata_full_cmb114_out, I5 => bvalid_cnt_inc11_out, O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0\ ); \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_4\: unisim.vcomponents.LUT2 generic map( INIT => X"8" ) port map ( I0 => s_axi_wvalid, I1 => s_axi_wlast, O => bvalid_cnt_inc11_out ); \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_reg\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0\, Q => delay_aw_active_clr, R => s_axi_aresetn_0 ); \GEN_WRDATA[0].bram_wrdata_int_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(0), Q => bram_wrdata_a(0), R => '0' ); \GEN_WRDATA[10].bram_wrdata_int_reg[10]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(10), Q => bram_wrdata_a(10), R => '0' ); \GEN_WRDATA[11].bram_wrdata_int_reg[11]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(11), Q => bram_wrdata_a(11), R => '0' ); \GEN_WRDATA[12].bram_wrdata_int_reg[12]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(12), Q => bram_wrdata_a(12), R => '0' ); \GEN_WRDATA[13].bram_wrdata_int_reg[13]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(13), Q => bram_wrdata_a(13), R => '0' ); \GEN_WRDATA[14].bram_wrdata_int_reg[14]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(14), Q => bram_wrdata_a(14), R => '0' ); \GEN_WRDATA[15].bram_wrdata_int_reg[15]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(15), Q => bram_wrdata_a(15), R => '0' ); \GEN_WRDATA[16].bram_wrdata_int_reg[16]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(16), Q => bram_wrdata_a(16), R => '0' ); \GEN_WRDATA[17].bram_wrdata_int_reg[17]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(17), Q => bram_wrdata_a(17), R => '0' ); \GEN_WRDATA[18].bram_wrdata_int_reg[18]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(18), Q => bram_wrdata_a(18), R => '0' ); \GEN_WRDATA[19].bram_wrdata_int_reg[19]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(19), Q => bram_wrdata_a(19), R => '0' ); \GEN_WRDATA[1].bram_wrdata_int_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(1), Q => bram_wrdata_a(1), R => '0' ); \GEN_WRDATA[20].bram_wrdata_int_reg[20]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(20), Q => bram_wrdata_a(20), R => '0' ); \GEN_WRDATA[21].bram_wrdata_int_reg[21]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(21), Q => bram_wrdata_a(21), R => '0' ); \GEN_WRDATA[22].bram_wrdata_int_reg[22]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(22), Q => bram_wrdata_a(22), R => '0' ); \GEN_WRDATA[23].bram_wrdata_int_reg[23]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(23), Q => bram_wrdata_a(23), R => '0' ); \GEN_WRDATA[24].bram_wrdata_int_reg[24]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(24), Q => bram_wrdata_a(24), R => '0' ); \GEN_WRDATA[25].bram_wrdata_int_reg[25]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(25), Q => bram_wrdata_a(25), R => '0' ); \GEN_WRDATA[26].bram_wrdata_int_reg[26]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(26), Q => bram_wrdata_a(26), R => '0' ); \GEN_WRDATA[27].bram_wrdata_int_reg[27]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(27), Q => bram_wrdata_a(27), R => '0' ); \GEN_WRDATA[28].bram_wrdata_int_reg[28]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(28), Q => bram_wrdata_a(28), R => '0' ); \GEN_WRDATA[29].bram_wrdata_int_reg[29]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(29), Q => bram_wrdata_a(29), R => '0' ); \GEN_WRDATA[2].bram_wrdata_int_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(2), Q => bram_wrdata_a(2), R => '0' ); \GEN_WRDATA[30].bram_wrdata_int_reg[30]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(30), Q => bram_wrdata_a(30), R => '0' ); \GEN_WRDATA[31].bram_wrdata_int_reg[31]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(31), Q => bram_wrdata_a(31), R => '0' ); \GEN_WRDATA[3].bram_wrdata_int_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(3), Q => bram_wrdata_a(3), R => '0' ); \GEN_WRDATA[4].bram_wrdata_int_reg[4]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(4), Q => bram_wrdata_a(4), R => '0' ); \GEN_WRDATA[5].bram_wrdata_int_reg[5]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(5), Q => bram_wrdata_a(5), R => '0' ); \GEN_WRDATA[6].bram_wrdata_int_reg[6]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(6), Q => bram_wrdata_a(6), R => '0' ); \GEN_WRDATA[7].bram_wrdata_int_reg[7]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(7), Q => bram_wrdata_a(7), R => '0' ); \GEN_WRDATA[8].bram_wrdata_int_reg[8]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(8), Q => bram_wrdata_a(8), R => '0' ); \GEN_WRDATA[9].bram_wrdata_int_reg[9]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wdata(9), Q => bram_wrdata_a(9), R => '0' ); \GEN_WR_NO_ECC.bram_we_int[3]_i_1\: unisim.vcomponents.LUT4 generic map( INIT => X"D0FF" ) port map ( I0 => s_axi_wvalid, I1 => wr_data_sm_cs(2), I2 => clr_bram_we, I3 => s_axi_aresetn, O => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\ ); \GEN_WR_NO_ECC.bram_we_int[3]_i_2\: unisim.vcomponents.LUT2 generic map( INIT => X"2" ) port map ( I0 => s_axi_wvalid, I1 => wr_data_sm_cs(2), O => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\ ); \GEN_WR_NO_ECC.bram_we_int_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wstrb(0), Q => bram_we_a(0), R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\ ); \GEN_WR_NO_ECC.bram_we_int_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wstrb(1), Q => bram_we_a(1), R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\ ); \GEN_WR_NO_ECC.bram_we_int_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wstrb(2), Q => bram_we_a(2), R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\ ); \GEN_WR_NO_ECC.bram_we_int_reg[3]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\, D => s_axi_wstrb(3), Q => bram_we_a(3), R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\ ); I_WRAP_BRST: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_0_wrap_brst port map ( D(13 downto 10) => bram_addr_ld(13 downto 10), D(9) => I_WRAP_BRST_n_7, D(8) => I_WRAP_BRST_n_8, D(7) => I_WRAP_BRST_n_9, D(6) => I_WRAP_BRST_n_10, D(5) => I_WRAP_BRST_n_11, D(4) => I_WRAP_BRST_n_12, D(3) => I_WRAP_BRST_n_13, D(2) => I_WRAP_BRST_n_14, D(1) => I_WRAP_BRST_n_15, D(0) => I_WRAP_BRST_n_16, E(0) => I_WRAP_BRST_n_2, \GEN_AWREADY.axi_aresetn_d2_reg\ => \^axi_aresetn_d2\, \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\, \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\, \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\, \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\, \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\, \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\, \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\, \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\, \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\, \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\, \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\, \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\, \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\, \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\, \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\, \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0\, \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ => I_WRAP_BRST_n_17, \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0\, Q(3 downto 0) => axi_awlen_pipe(3 downto 0), SR(0) => I_WRAP_BRST_n_0, aw_active => aw_active, axi_awaddr_full => axi_awaddr_full, axi_awlen_pipe_1_or_2 => axi_awlen_pipe_1_or_2, axi_awsize_pipe(0) => axi_awsize_pipe(1), bram_addr_a(9 downto 0) => \^bram_addr_a\(9 downto 0), bram_addr_inc => bram_addr_inc, bram_addr_ld_en => bram_addr_ld_en, bram_addr_ld_en_mod => bram_addr_ld_en_mod, bram_addr_rst_cmb => bram_addr_rst_cmb, bvalid_cnt(2 downto 0) => bvalid_cnt(2 downto 0), curr_awlen_reg_1_or_2 => curr_awlen_reg_1_or_2, curr_fixed_burst => curr_fixed_burst, curr_fixed_burst_reg => curr_fixed_burst_reg, curr_fixed_burst_reg_reg => I_WRAP_BRST_n_24, curr_wrap_burst => curr_wrap_burst, curr_wrap_burst_reg => curr_wrap_burst_reg, curr_wrap_burst_reg_reg => I_WRAP_BRST_n_25, last_data_ack_mod => last_data_ack_mod, \out\(2 downto 0) => wr_data_sm_cs(2 downto 0), s_axi_aclk => s_axi_aclk, s_axi_aresetn => s_axi_aresetn, s_axi_aresetn_0 => s_axi_aresetn_0, s_axi_awaddr(13 downto 0) => s_axi_awaddr(13 downto 0), s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0), s_axi_awvalid => s_axi_awvalid, s_axi_wvalid => s_axi_wvalid, \save_init_bram_addr_ld_reg[15]_0\ => I_WRAP_BRST_n_19, \save_init_bram_addr_ld_reg[15]_1\ => I_WRAP_BRST_n_20, \save_init_bram_addr_ld_reg[15]_2\ => I_WRAP_BRST_n_21, wr_addr_sm_cs => wr_addr_sm_cs, \wrap_burst_total_reg[0]_0\ => I_WRAP_BRST_n_22, \wrap_burst_total_reg[2]_0\ => I_WRAP_BRST_n_23 ); \axi_bid_int_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => BID_FIFO_n_4, Q => \^s_axi_bid\(0), R => s_axi_aresetn_0 ); axi_bvalid_int_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"AAAAAAAAAAAA8A88" ) port map ( I0 => s_axi_aresetn, I1 => bvalid_cnt_inc, I2 => BID_FIFO_n_1, I3 => bvalid_cnt(0), I4 => bvalid_cnt(2), I5 => bvalid_cnt(1), O => axi_bvalid_int_i_1_n_0 ); axi_bvalid_int_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => axi_bvalid_int_i_1_n_0, Q => \^s_axi_bvalid\, R => '0' ); axi_wr_burst_i_1: unisim.vcomponents.LUT3 generic map( INIT => X"B8" ) port map ( I0 => axi_wr_burst_cmb, I1 => axi_wr_burst_i_3_n_0, I2 => axi_wr_burst, O => axi_wr_burst_i_1_n_0 ); axi_wr_burst_i_2: unisim.vcomponents.LUT5 generic map( INIT => X"3088FCBB" ) port map ( I0 => s_axi_wvalid, I1 => wr_data_sm_cs(1), I2 => axi_wr_burst_cmb0, I3 => wr_data_sm_cs(0), I4 => s_axi_wlast, O => axi_wr_burst_cmb ); axi_wr_burst_i_3: unisim.vcomponents.LUT6 generic map( INIT => X"00000000AAAAA222" ) port map ( I0 => s_axi_wvalid, I1 => wr_data_sm_cs(0), I2 => axi_wr_burst_cmb0, I3 => s_axi_wlast, I4 => wr_data_sm_cs(1), I5 => wr_data_sm_cs(2), O => axi_wr_burst_i_3_n_0 ); axi_wr_burst_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => axi_wr_burst_i_1_n_0, Q => axi_wr_burst, R => s_axi_aresetn_0 ); axi_wready_int_mod_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"EA00EAFF00000000" ) port map ( I0 => axi_wdata_full_cmb114_out, I1 => axi_awaddr_full, I2 => bram_addr_ld_en, I3 => wr_data_sm_cs(2), I4 => axi_wready_int_mod_i_3_n_0, I5 => s_axi_aresetn, O => axi_wready_int_mod_i_1_n_0 ); axi_wready_int_mod_i_3: unisim.vcomponents.LUT5 generic map( INIT => X"F8F9F0F0" ) port map ( I0 => wr_data_sm_cs(1), I1 => wr_data_sm_cs(0), I2 => axi_wdata_full_reg, I3 => axi_wdata_full_cmb114_out, I4 => s_axi_wvalid, O => axi_wready_int_mod_i_3_n_0 ); axi_wready_int_mod_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => axi_wready_int_mod_i_1_n_0, Q => \^s_axi_wready\, R => '0' ); bid_gets_fifo_load_d1_i_2: unisim.vcomponents.LUT3 generic map( INIT => X"EF" ) port map ( I0 => bvalid_cnt(1), I1 => bvalid_cnt(2), I2 => bvalid_cnt(0), O => bid_gets_fifo_load_d1_i_2_n_0 ); bid_gets_fifo_load_d1_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => bid_gets_fifo_load, Q => bid_gets_fifo_load_d1, R => s_axi_aresetn_0 ); \bvalid_cnt[0]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"95956A6A95956AAA" ) port map ( I0 => bvalid_cnt_inc, I1 => s_axi_bready, I2 => \^s_axi_bvalid\, I3 => bvalid_cnt(2), I4 => bvalid_cnt(0), I5 => bvalid_cnt(1), O => \bvalid_cnt[0]_i_1_n_0\ ); \bvalid_cnt[1]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"D5D5BFBF2A2A4000" ) port map ( I0 => bvalid_cnt_inc, I1 => s_axi_bready, I2 => \^s_axi_bvalid\, I3 => bvalid_cnt(2), I4 => bvalid_cnt(0), I5 => bvalid_cnt(1), O => \bvalid_cnt[1]_i_1_n_0\ ); \bvalid_cnt[2]_i_1\: unisim.vcomponents.LUT6 generic map( INIT => X"D52AFF00FF00BF00" ) port map ( I0 => bvalid_cnt_inc, I1 => s_axi_bready, I2 => \^s_axi_bvalid\, I3 => bvalid_cnt(2), I4 => bvalid_cnt(0), I5 => bvalid_cnt(1), O => \bvalid_cnt[2]_i_1_n_0\ ); \bvalid_cnt_reg[0]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \bvalid_cnt[0]_i_1_n_0\, Q => bvalid_cnt(0), R => s_axi_aresetn_0 ); \bvalid_cnt_reg[1]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \bvalid_cnt[1]_i_1_n_0\, Q => bvalid_cnt(1), R => s_axi_aresetn_0 ); \bvalid_cnt_reg[2]\: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => \bvalid_cnt[2]_i_1_n_0\, Q => bvalid_cnt(2), R => s_axi_aresetn_0 ); curr_awlen_reg_1_or_2_i_1: unisim.vcomponents.LUT6 generic map( INIT => X"0000000000000151" ) port map ( I0 => I_WRAP_BRST_n_23, I1 => s_axi_awlen(2), I2 => axi_awaddr_full, I3 => axi_awlen_pipe(2), I4 => I_WRAP_BRST_n_22, I5 => curr_awlen_reg_1_or_2_i_2_n_0, O => curr_awlen_reg_1_or_20 ); curr_awlen_reg_1_or_2_i_2: unisim.vcomponents.LUT6 generic map( INIT => X"F5F5F5F5F5F5F5C5" ) port map ( I0 => \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\, I1 => axi_awlen_pipe(5), I2 => axi_awaddr_full, I3 => axi_awlen_pipe(6), I4 => axi_awlen_pipe(7), I5 => axi_awlen_pipe(4), O => curr_awlen_reg_1_or_2_i_2_n_0 ); curr_awlen_reg_1_or_2_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => bram_addr_ld_en, D => curr_awlen_reg_1_or_20, Q => curr_awlen_reg_1_or_2, R => s_axi_aresetn_0 ); curr_fixed_burst_reg_i_2: unisim.vcomponents.LUT5 generic map( INIT => X"00053305" ) port map ( I0 => s_axi_awburst(1), I1 => axi_awburst_pipe(1), I2 => s_axi_awburst(0), I3 => axi_awaddr_full, I4 => axi_awburst_pipe(0), O => curr_fixed_burst ); curr_fixed_burst_reg_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => I_WRAP_BRST_n_24, Q => curr_fixed_burst_reg, R => '0' ); curr_wrap_burst_reg_i_2: unisim.vcomponents.LUT5 generic map( INIT => X"000ACC0A" ) port map ( I0 => s_axi_awburst(1), I1 => axi_awburst_pipe(1), I2 => s_axi_awburst(0), I3 => axi_awaddr_full, I4 => axi_awburst_pipe(0), O => curr_wrap_burst ); curr_wrap_burst_reg_reg: unisim.vcomponents.FDRE generic map( INIT => '0' ) port map ( C => s_axi_aclk, CE => '1', D => I_WRAP_BRST_n_25, Q => curr_wrap_burst_reg, R => '0' ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zqynq_lab_1_design_axi_bram_ctrl_0_0_full_axi is port ( s_axi_rvalid : out STD_LOGIC; s_axi_rlast : out STD_LOGIC; s_axi_bvalid : out STD_LOGIC; s_axi_awready : out STD_LOGIC; bram_rst_a : out STD_LOGIC; bram_addr_a : out STD_LOGIC_VECTOR ( 13 downto 0 ); bram_en_a : out STD_LOGIC; bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 ); bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 ); bram_addr_b : out STD_LOGIC_VECTOR ( 13 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wready : out STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 ); bram_en_b : out STD_LOGIC; s_axi_aresetn : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wlast : in STD_LOGIC; s_axi_rready : in STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_aclk : in STD_LOGIC; s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 ); s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 ); s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 ); bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_bram_ctrl_0_0_full_axi : entity is "full_axi"; end zqynq_lab_1_design_axi_bram_ctrl_0_0_full_axi; architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0_full_axi is signal I_WR_CHNL_n_36 : STD_LOGIC; signal axi_aresetn_d2 : STD_LOGIC; signal axi_aresetn_re_reg : STD_LOGIC; signal \^bram_rst_a\ : STD_LOGIC; begin bram_rst_a <= \^bram_rst_a\; I_RD_CHNL: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_0_rd_chnl port map ( \GEN_AWREADY.axi_aresetn_d2_reg\ => I_WR_CHNL_n_36, Q(13 downto 0) => bram_addr_b(13 downto 0), axi_aresetn_d2 => axi_aresetn_d2, axi_aresetn_re_reg => axi_aresetn_re_reg, bram_en_b => bram_en_b, bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0), bram_rst_a => \^bram_rst_a\, s_axi_aclk => s_axi_aclk, s_axi_araddr(13 downto 0) => s_axi_araddr(13 downto 0), s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), s_axi_aresetn => s_axi_aresetn, s_axi_arid(0) => s_axi_arid(0), s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0), s_axi_arready => s_axi_arready, s_axi_arvalid => s_axi_arvalid, s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0), s_axi_rid(0) => s_axi_rid(0), s_axi_rlast => s_axi_rlast, s_axi_rready => s_axi_rready, s_axi_rvalid => s_axi_rvalid ); I_WR_CHNL: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_0_wr_chnl port map ( \GEN_AW_DUAL.aw_active_reg_0\ => I_WR_CHNL_n_36, axi_aresetn_d2 => axi_aresetn_d2, axi_aresetn_re_reg => axi_aresetn_re_reg, bram_addr_a(13 downto 0) => bram_addr_a(13 downto 0), bram_en_a => bram_en_a, bram_we_a(3 downto 0) => bram_we_a(3 downto 0), bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0), s_axi_aclk => s_axi_aclk, s_axi_aresetn => s_axi_aresetn, s_axi_aresetn_0 => \^bram_rst_a\, s_axi_awaddr(13 downto 0) => s_axi_awaddr(13 downto 0), s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), s_axi_awid(0) => s_axi_awid(0), s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0), s_axi_awready => s_axi_awready, s_axi_awvalid => s_axi_awvalid, s_axi_bid(0) => s_axi_bid(0), s_axi_bready => s_axi_bready, s_axi_bvalid => s_axi_bvalid, s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0), s_axi_wlast => s_axi_wlast, s_axi_wready => s_axi_wready, s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0), s_axi_wvalid => s_axi_wvalid ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl_top is port ( s_axi_rvalid : out STD_LOGIC; s_axi_rlast : out STD_LOGIC; s_axi_bvalid : out STD_LOGIC; s_axi_awready : out STD_LOGIC; bram_rst_a : out STD_LOGIC; bram_addr_a : out STD_LOGIC_VECTOR ( 13 downto 0 ); bram_en_a : out STD_LOGIC; bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 ); bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 ); bram_addr_b : out STD_LOGIC_VECTOR ( 13 downto 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wready : out STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 ); bram_en_b : out STD_LOGIC; s_axi_aresetn : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wlast : in STD_LOGIC; s_axi_rready : in STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_aclk : in STD_LOGIC; s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 ); s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 ); s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 ); bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_arvalid : in STD_LOGIC ); attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl_top : entity is "axi_bram_ctrl_top"; end zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl_top; architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl_top is begin \GEN_AXI4.I_FULL_AXI\: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_0_full_axi port map ( bram_addr_a(13 downto 0) => bram_addr_a(13 downto 0), bram_addr_b(13 downto 0) => bram_addr_b(13 downto 0), bram_en_a => bram_en_a, bram_en_b => bram_en_b, bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0), bram_rst_a => bram_rst_a, bram_we_a(3 downto 0) => bram_we_a(3 downto 0), bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0), s_axi_aclk => s_axi_aclk, s_axi_araddr(13 downto 0) => s_axi_araddr(13 downto 0), s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), s_axi_aresetn => s_axi_aresetn, s_axi_arid(0) => s_axi_arid(0), s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0), s_axi_arready => s_axi_arready, s_axi_arvalid => s_axi_arvalid, s_axi_awaddr(13 downto 0) => s_axi_awaddr(13 downto 0), s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), s_axi_awid(0) => s_axi_awid(0), s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0), s_axi_awready => s_axi_awready, s_axi_awvalid => s_axi_awvalid, s_axi_bid(0) => s_axi_bid(0), s_axi_bready => s_axi_bready, s_axi_bvalid => s_axi_bvalid, s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0), s_axi_rid(0) => s_axi_rid(0), s_axi_rlast => s_axi_rlast, s_axi_rready => s_axi_rready, s_axi_rvalid => s_axi_rvalid, s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0), s_axi_wlast => s_axi_wlast, s_axi_wready => s_axi_wready, s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0), s_axi_wvalid => s_axi_wvalid ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl is port ( s_axi_aclk : in STD_LOGIC; s_axi_aresetn : in STD_LOGIC; ecc_interrupt : out STD_LOGIC; ecc_ue : out STD_LOGIC; s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awaddr : in STD_LOGIC_VECTOR ( 15 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awlock : in STD_LOGIC; s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 15 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arlock : in STD_LOGIC; s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; s_axi_ctrl_awvalid : in STD_LOGIC; s_axi_ctrl_awready : out STD_LOGIC; s_axi_ctrl_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_ctrl_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_ctrl_wvalid : in STD_LOGIC; s_axi_ctrl_wready : out STD_LOGIC; s_axi_ctrl_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_ctrl_bvalid : out STD_LOGIC; s_axi_ctrl_bready : in STD_LOGIC; s_axi_ctrl_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_ctrl_arvalid : in STD_LOGIC; s_axi_ctrl_arready : out STD_LOGIC; s_axi_ctrl_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_ctrl_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_ctrl_rvalid : out STD_LOGIC; s_axi_ctrl_rready : in STD_LOGIC; bram_rst_a : out STD_LOGIC; bram_clk_a : out STD_LOGIC; bram_en_a : out STD_LOGIC; bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 ); bram_addr_a : out STD_LOGIC_VECTOR ( 15 downto 0 ); bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 ); bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 ); bram_rst_b : out STD_LOGIC; bram_clk_b : out STD_LOGIC; bram_en_b : out STD_LOGIC; bram_we_b : out STD_LOGIC_VECTOR ( 3 downto 0 ); bram_addr_b : out STD_LOGIC_VECTOR ( 15 downto 0 ); bram_wrdata_b : out STD_LOGIC_VECTOR ( 31 downto 0 ); bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 ) ); attribute C_BRAM_ADDR_WIDTH : integer; attribute C_BRAM_ADDR_WIDTH of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 14; attribute C_BRAM_INST_MODE : string; attribute C_BRAM_INST_MODE of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is "EXTERNAL"; attribute C_ECC : integer; attribute C_ECC of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 0; attribute C_ECC_ONOFF_RESET_VALUE : integer; attribute C_ECC_ONOFF_RESET_VALUE of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 0; attribute C_ECC_TYPE : integer; attribute C_ECC_TYPE of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 0; attribute C_FAMILY : string; attribute C_FAMILY of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is "zynq"; attribute C_FAULT_INJECT : integer; attribute C_FAULT_INJECT of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 0; attribute C_MEMORY_DEPTH : integer; attribute C_MEMORY_DEPTH of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 16384; attribute C_SELECT_XPM : integer; attribute C_SELECT_XPM of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 0; attribute C_SINGLE_PORT_BRAM : integer; attribute C_SINGLE_PORT_BRAM of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 0; attribute C_S_AXI_ADDR_WIDTH : integer; attribute C_S_AXI_ADDR_WIDTH of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 16; attribute C_S_AXI_CTRL_ADDR_WIDTH : integer; attribute C_S_AXI_CTRL_ADDR_WIDTH of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 32; attribute C_S_AXI_CTRL_DATA_WIDTH : integer; attribute C_S_AXI_CTRL_DATA_WIDTH of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 32; attribute C_S_AXI_DATA_WIDTH : integer; attribute C_S_AXI_DATA_WIDTH of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 32; attribute C_S_AXI_ID_WIDTH : integer; attribute C_S_AXI_ID_WIDTH of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 1; attribute C_S_AXI_PROTOCOL : string; attribute C_S_AXI_PROTOCOL of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is "AXI4"; attribute C_S_AXI_SUPPORTS_NARROW_BURST : integer; attribute C_S_AXI_SUPPORTS_NARROW_BURST of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is 0; attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is "axi_bram_ctrl"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl : entity is "yes"; end zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl; architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl is signal \<const0>\ : STD_LOGIC; signal \^bram_addr_a\ : STD_LOGIC_VECTOR ( 15 downto 2 ); signal \^bram_addr_b\ : STD_LOGIC_VECTOR ( 15 downto 2 ); signal \^bram_rst_a\ : STD_LOGIC; signal \^s_axi_aclk\ : STD_LOGIC; begin \^s_axi_aclk\ <= s_axi_aclk; bram_addr_a(15 downto 2) <= \^bram_addr_a\(15 downto 2); bram_addr_a(1) <= \<const0>\; bram_addr_a(0) <= \<const0>\; bram_addr_b(15 downto 2) <= \^bram_addr_b\(15 downto 2); bram_addr_b(1) <= \<const0>\; bram_addr_b(0) <= \<const0>\; bram_clk_a <= \^s_axi_aclk\; bram_clk_b <= \^s_axi_aclk\; bram_rst_a <= \^bram_rst_a\; bram_rst_b <= \^bram_rst_a\; bram_we_b(3) <= \<const0>\; bram_we_b(2) <= \<const0>\; bram_we_b(1) <= \<const0>\; bram_we_b(0) <= \<const0>\; bram_wrdata_b(31) <= \<const0>\; bram_wrdata_b(30) <= \<const0>\; bram_wrdata_b(29) <= \<const0>\; bram_wrdata_b(28) <= \<const0>\; bram_wrdata_b(27) <= \<const0>\; bram_wrdata_b(26) <= \<const0>\; bram_wrdata_b(25) <= \<const0>\; bram_wrdata_b(24) <= \<const0>\; bram_wrdata_b(23) <= \<const0>\; bram_wrdata_b(22) <= \<const0>\; bram_wrdata_b(21) <= \<const0>\; bram_wrdata_b(20) <= \<const0>\; bram_wrdata_b(19) <= \<const0>\; bram_wrdata_b(18) <= \<const0>\; bram_wrdata_b(17) <= \<const0>\; bram_wrdata_b(16) <= \<const0>\; bram_wrdata_b(15) <= \<const0>\; bram_wrdata_b(14) <= \<const0>\; bram_wrdata_b(13) <= \<const0>\; bram_wrdata_b(12) <= \<const0>\; bram_wrdata_b(11) <= \<const0>\; bram_wrdata_b(10) <= \<const0>\; bram_wrdata_b(9) <= \<const0>\; bram_wrdata_b(8) <= \<const0>\; bram_wrdata_b(7) <= \<const0>\; bram_wrdata_b(6) <= \<const0>\; bram_wrdata_b(5) <= \<const0>\; bram_wrdata_b(4) <= \<const0>\; bram_wrdata_b(3) <= \<const0>\; bram_wrdata_b(2) <= \<const0>\; bram_wrdata_b(1) <= \<const0>\; bram_wrdata_b(0) <= \<const0>\; ecc_interrupt <= \<const0>\; ecc_ue <= \<const0>\; s_axi_bresp(1) <= \<const0>\; s_axi_bresp(0) <= \<const0>\; s_axi_ctrl_arready <= \<const0>\; s_axi_ctrl_awready <= \<const0>\; s_axi_ctrl_bresp(1) <= \<const0>\; s_axi_ctrl_bresp(0) <= \<const0>\; s_axi_ctrl_bvalid <= \<const0>\; s_axi_ctrl_rdata(31) <= \<const0>\; s_axi_ctrl_rdata(30) <= \<const0>\; s_axi_ctrl_rdata(29) <= \<const0>\; s_axi_ctrl_rdata(28) <= \<const0>\; s_axi_ctrl_rdata(27) <= \<const0>\; s_axi_ctrl_rdata(26) <= \<const0>\; s_axi_ctrl_rdata(25) <= \<const0>\; s_axi_ctrl_rdata(24) <= \<const0>\; s_axi_ctrl_rdata(23) <= \<const0>\; s_axi_ctrl_rdata(22) <= \<const0>\; s_axi_ctrl_rdata(21) <= \<const0>\; s_axi_ctrl_rdata(20) <= \<const0>\; s_axi_ctrl_rdata(19) <= \<const0>\; s_axi_ctrl_rdata(18) <= \<const0>\; s_axi_ctrl_rdata(17) <= \<const0>\; s_axi_ctrl_rdata(16) <= \<const0>\; s_axi_ctrl_rdata(15) <= \<const0>\; s_axi_ctrl_rdata(14) <= \<const0>\; s_axi_ctrl_rdata(13) <= \<const0>\; s_axi_ctrl_rdata(12) <= \<const0>\; s_axi_ctrl_rdata(11) <= \<const0>\; s_axi_ctrl_rdata(10) <= \<const0>\; s_axi_ctrl_rdata(9) <= \<const0>\; s_axi_ctrl_rdata(8) <= \<const0>\; s_axi_ctrl_rdata(7) <= \<const0>\; s_axi_ctrl_rdata(6) <= \<const0>\; s_axi_ctrl_rdata(5) <= \<const0>\; s_axi_ctrl_rdata(4) <= \<const0>\; s_axi_ctrl_rdata(3) <= \<const0>\; s_axi_ctrl_rdata(2) <= \<const0>\; s_axi_ctrl_rdata(1) <= \<const0>\; s_axi_ctrl_rdata(0) <= \<const0>\; s_axi_ctrl_rresp(1) <= \<const0>\; s_axi_ctrl_rresp(0) <= \<const0>\; s_axi_ctrl_rvalid <= \<const0>\; s_axi_ctrl_wready <= \<const0>\; s_axi_rresp(1) <= \<const0>\; s_axi_rresp(0) <= \<const0>\; GND: unisim.vcomponents.GND port map ( G => \<const0>\ ); \gext_inst.abcv4_0_ext_inst\: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl_top port map ( bram_addr_a(13 downto 0) => \^bram_addr_a\(15 downto 2), bram_addr_b(13 downto 0) => \^bram_addr_b\(15 downto 2), bram_en_a => bram_en_a, bram_en_b => bram_en_b, bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0), bram_rst_a => \^bram_rst_a\, bram_we_a(3 downto 0) => bram_we_a(3 downto 0), bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0), s_axi_aclk => \^s_axi_aclk\, s_axi_araddr(13 downto 0) => s_axi_araddr(15 downto 2), s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), s_axi_aresetn => s_axi_aresetn, s_axi_arid(0) => s_axi_arid(0), s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0), s_axi_arready => s_axi_arready, s_axi_arvalid => s_axi_arvalid, s_axi_awaddr(13 downto 0) => s_axi_awaddr(15 downto 2), s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), s_axi_awid(0) => s_axi_awid(0), s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0), s_axi_awready => s_axi_awready, s_axi_awvalid => s_axi_awvalid, s_axi_bid(0) => s_axi_bid(0), s_axi_bready => s_axi_bready, s_axi_bvalid => s_axi_bvalid, s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0), s_axi_rid(0) => s_axi_rid(0), s_axi_rlast => s_axi_rlast, s_axi_rready => s_axi_rready, s_axi_rvalid => s_axi_rvalid, s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0), s_axi_wlast => s_axi_wlast, s_axi_wready => s_axi_wready, s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0), s_axi_wvalid => s_axi_wvalid ); end STRUCTURE; library IEEE; use IEEE.STD_LOGIC_1164.ALL; library UNISIM; use UNISIM.VCOMPONENTS.ALL; entity zqynq_lab_1_design_axi_bram_ctrl_0_0 is port ( s_axi_aclk : in STD_LOGIC; s_axi_aresetn : in STD_LOGIC; s_axi_awaddr : in STD_LOGIC_VECTOR ( 15 downto 0 ); s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_awlock : in STD_LOGIC; s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awvalid : in STD_LOGIC; s_axi_awready : out STD_LOGIC; s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wlast : in STD_LOGIC; s_axi_wvalid : in STD_LOGIC; s_axi_wready : out STD_LOGIC; s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC; s_axi_bready : in STD_LOGIC; s_axi_araddr : in STD_LOGIC_VECTOR ( 15 downto 0 ); s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 ); s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_arlock : in STD_LOGIC; s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arvalid : in STD_LOGIC; s_axi_arready : out STD_LOGIC; s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rlast : out STD_LOGIC; s_axi_rvalid : out STD_LOGIC; s_axi_rready : in STD_LOGIC; bram_rst_a : out STD_LOGIC; bram_clk_a : out STD_LOGIC; bram_en_a : out STD_LOGIC; bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 ); bram_addr_a : out STD_LOGIC_VECTOR ( 15 downto 0 ); bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 ); bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 ); bram_rst_b : out STD_LOGIC; bram_clk_b : out STD_LOGIC; bram_en_b : out STD_LOGIC; bram_we_b : out STD_LOGIC_VECTOR ( 3 downto 0 ); bram_addr_b : out STD_LOGIC_VECTOR ( 15 downto 0 ); bram_wrdata_b : out STD_LOGIC_VECTOR ( 31 downto 0 ); bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 ) ); attribute NotValidForBitStream : boolean; attribute NotValidForBitStream of zqynq_lab_1_design_axi_bram_ctrl_0_0 : entity is true; attribute CHECK_LICENSE_TYPE : string; attribute CHECK_LICENSE_TYPE of zqynq_lab_1_design_axi_bram_ctrl_0_0 : entity is "zqynq_lab_1_design_axi_bram_ctrl_0_0,axi_bram_ctrl,{}"; attribute downgradeipidentifiedwarnings : string; attribute downgradeipidentifiedwarnings of zqynq_lab_1_design_axi_bram_ctrl_0_0 : entity is "yes"; attribute x_core_info : string; attribute x_core_info of zqynq_lab_1_design_axi_bram_ctrl_0_0 : entity is "axi_bram_ctrl,Vivado 2017.2"; end zqynq_lab_1_design_axi_bram_ctrl_0_0; architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_0 is signal NLW_U0_ecc_interrupt_UNCONNECTED : STD_LOGIC; signal NLW_U0_ecc_ue_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_ctrl_arready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_ctrl_awready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_ctrl_wready_UNCONNECTED : STD_LOGIC; signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); signal NLW_U0_s_axi_ctrl_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_U0_s_axi_ctrl_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); signal NLW_U0_s_axi_ctrl_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 ); attribute C_BRAM_ADDR_WIDTH : integer; attribute C_BRAM_ADDR_WIDTH of U0 : label is 14; attribute C_BRAM_INST_MODE : string; attribute C_BRAM_INST_MODE of U0 : label is "EXTERNAL"; attribute C_ECC : integer; attribute C_ECC of U0 : label is 0; attribute C_ECC_ONOFF_RESET_VALUE : integer; attribute C_ECC_ONOFF_RESET_VALUE of U0 : label is 0; attribute C_ECC_TYPE : integer; attribute C_ECC_TYPE of U0 : label is 0; attribute C_FAMILY : string; attribute C_FAMILY of U0 : label is "zynq"; attribute C_FAULT_INJECT : integer; attribute C_FAULT_INJECT of U0 : label is 0; attribute C_MEMORY_DEPTH : integer; attribute C_MEMORY_DEPTH of U0 : label is 16384; attribute C_SELECT_XPM : integer; attribute C_SELECT_XPM of U0 : label is 0; attribute C_SINGLE_PORT_BRAM : integer; attribute C_SINGLE_PORT_BRAM of U0 : label is 0; attribute C_S_AXI_ADDR_WIDTH : integer; attribute C_S_AXI_ADDR_WIDTH of U0 : label is 16; attribute C_S_AXI_CTRL_ADDR_WIDTH : integer; attribute C_S_AXI_CTRL_ADDR_WIDTH of U0 : label is 32; attribute C_S_AXI_CTRL_DATA_WIDTH : integer; attribute C_S_AXI_CTRL_DATA_WIDTH of U0 : label is 32; attribute C_S_AXI_DATA_WIDTH : integer; attribute C_S_AXI_DATA_WIDTH of U0 : label is 32; attribute C_S_AXI_ID_WIDTH : integer; attribute C_S_AXI_ID_WIDTH of U0 : label is 1; attribute C_S_AXI_PROTOCOL : string; attribute C_S_AXI_PROTOCOL of U0 : label is "AXI4"; attribute C_S_AXI_SUPPORTS_NARROW_BURST : integer; attribute C_S_AXI_SUPPORTS_NARROW_BURST of U0 : label is 0; attribute downgradeipidentifiedwarnings of U0 : label is "yes"; begin U0: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_0_axi_bram_ctrl port map ( bram_addr_a(15 downto 0) => bram_addr_a(15 downto 0), bram_addr_b(15 downto 0) => bram_addr_b(15 downto 0), bram_clk_a => bram_clk_a, bram_clk_b => bram_clk_b, bram_en_a => bram_en_a, bram_en_b => bram_en_b, bram_rddata_a(31 downto 0) => bram_rddata_a(31 downto 0), bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0), bram_rst_a => bram_rst_a, bram_rst_b => bram_rst_b, bram_we_a(3 downto 0) => bram_we_a(3 downto 0), bram_we_b(3 downto 0) => bram_we_b(3 downto 0), bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0), bram_wrdata_b(31 downto 0) => bram_wrdata_b(31 downto 0), ecc_interrupt => NLW_U0_ecc_interrupt_UNCONNECTED, ecc_ue => NLW_U0_ecc_ue_UNCONNECTED, s_axi_aclk => s_axi_aclk, s_axi_araddr(15 downto 0) => s_axi_araddr(15 downto 0), s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0), s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0), s_axi_aresetn => s_axi_aresetn, s_axi_arid(0) => '0', s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0), s_axi_arlock => s_axi_arlock, s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0), s_axi_arready => s_axi_arready, s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0), s_axi_arvalid => s_axi_arvalid, s_axi_awaddr(15 downto 0) => s_axi_awaddr(15 downto 0), s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0), s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0), s_axi_awid(0) => '0', s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0), s_axi_awlock => s_axi_awlock, s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0), s_axi_awready => s_axi_awready, s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0), s_axi_awvalid => s_axi_awvalid, s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0), s_axi_bready => s_axi_bready, s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0), s_axi_bvalid => s_axi_bvalid, s_axi_ctrl_araddr(31 downto 0) => B"00000000000000000000000000000000", s_axi_ctrl_arready => NLW_U0_s_axi_ctrl_arready_UNCONNECTED, s_axi_ctrl_arvalid => '0', s_axi_ctrl_awaddr(31 downto 0) => B"00000000000000000000000000000000", s_axi_ctrl_awready => NLW_U0_s_axi_ctrl_awready_UNCONNECTED, s_axi_ctrl_awvalid => '0', s_axi_ctrl_bready => '0', s_axi_ctrl_bresp(1 downto 0) => NLW_U0_s_axi_ctrl_bresp_UNCONNECTED(1 downto 0), s_axi_ctrl_bvalid => NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED, s_axi_ctrl_rdata(31 downto 0) => NLW_U0_s_axi_ctrl_rdata_UNCONNECTED(31 downto 0), s_axi_ctrl_rready => '0', s_axi_ctrl_rresp(1 downto 0) => NLW_U0_s_axi_ctrl_rresp_UNCONNECTED(1 downto 0), s_axi_ctrl_rvalid => NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED, s_axi_ctrl_wdata(31 downto 0) => B"00000000000000000000000000000000", s_axi_ctrl_wready => NLW_U0_s_axi_ctrl_wready_UNCONNECTED, s_axi_ctrl_wvalid => '0', s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0), s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0), s_axi_rlast => s_axi_rlast, s_axi_rready => s_axi_rready, s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0), s_axi_rvalid => s_axi_rvalid, s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0), s_axi_wlast => s_axi_wlast, s_axi_wready => s_axi_wready, s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0), s_axi_wvalid => s_axi_wvalid ); end STRUCTURE;

mit

khaledhassan/vhdl-examples

register/register.vhd

1

1950

-- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net> -- This software is distributed under the terms of the MIT License shown below. -- -- Permission is hereby granted, free of charge, to any person obtaining a copy -- of this software and associated documentation files (the "Software"), to -- deal in the Software without restriction, including without limitation the -- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or -- sell copies of the Software, and to permit persons to whom the Software is -- furnished to do so, subject to the following conditions: -- -- The above copyright notice and this permission notice shall be included in -- all copies or substantial portions of the Software. -- -- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -- IN THE SOFTWARE. -- Implements a synchronous register of a given width with a load signal. library ieee; use ieee.std_logic_1164.all; entity reg is generic ( WIDTH : positive := 1 ); port ( clk : in std_logic; rst : in std_logic; load : in std_logic; input : in std_logic_vector(WIDTH-1 downto 0); output : out std_logic_vector(WIDTH-1 downto 0) ); end reg; architecture BHV of reg is begin process(clk, rst) begin if(rst = '1') then output <= (others => '0'); elsif(rising_edge(clk)) then if(load = '1') then output <= input; end if; end if; end process; end BHV;

mit

MarkBlanco/FPGA_Sandbox

RecComp/Lab1/embedded_lab_1/embedded_lab_1.cache/ip/2017.2/387128e4034068b3/zynq_design_1_processing_system7_0_2_stub.vhdl

1

5748

-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017 -- Date : Tue Sep 19 00:29:47 2017 -- Host : DarkCube running 64-bit major release (build 9200) -- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix -- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_processing_system7_0_2_stub.vhdl -- Design : zynq_design_1_processing_system7_0_2 -- Purpose : Stub declaration of top-level module interface -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is Port ( TTC0_WAVE0_OUT : out STD_LOGIC; TTC0_WAVE1_OUT : out STD_LOGIC; TTC0_WAVE2_OUT : out STD_LOGIC; USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); USB0_VBUS_PWRSELECT : out STD_LOGIC; USB0_VBUS_PWRFAULT : in STD_LOGIC; M_AXI_GP0_ARVALID : out STD_LOGIC; M_AXI_GP0_AWVALID : out STD_LOGIC; M_AXI_GP0_BREADY : out STD_LOGIC; M_AXI_GP0_RREADY : out STD_LOGIC; M_AXI_GP0_WLAST : out STD_LOGIC; M_AXI_GP0_WVALID : out STD_LOGIC; M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); M_AXI_GP0_ACLK : in STD_LOGIC; M_AXI_GP0_ARREADY : in STD_LOGIC; M_AXI_GP0_AWREADY : in STD_LOGIC; M_AXI_GP0_BVALID : in STD_LOGIC; M_AXI_GP0_RLAST : in STD_LOGIC; M_AXI_GP0_RVALID : in STD_LOGIC; M_AXI_GP0_WREADY : in STD_LOGIC; M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); FCLK_CLK0 : out STD_LOGIC; FCLK_RESET0_N : out STD_LOGIC; MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 ); DDR_CAS_n : inout STD_LOGIC; DDR_CKE : inout STD_LOGIC; DDR_Clk_n : inout STD_LOGIC; DDR_Clk : inout STD_LOGIC; DDR_CS_n : inout STD_LOGIC; DDR_DRSTB : inout STD_LOGIC; DDR_ODT : inout STD_LOGIC; DDR_RAS_n : inout STD_LOGIC; DDR_WEB : inout STD_LOGIC; DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 ); DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); DDR_VRN : inout STD_LOGIC; DDR_VRP : inout STD_LOGIC; DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 ); DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 ); PS_SRSTB : inout STD_LOGIC; PS_CLK : inout STD_LOGIC; PS_PORB : inout STD_LOGIC ); end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; attribute black_box_pad_pin of stub : architecture is "TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "processing_system7_v5_5_processing_system7,Vivado 2017.2"; begin end;

mit

MarkBlanco/FPGA_Sandbox

RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_xbar_0/ip_design_xbar_0_stub.vhdl

1

4109

-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017 -- Date : Tue Oct 17 19:50:59 2017 -- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS -- Command : write_vhdl -force -mode synth_stub -- /home/mark/Documents/Repos/FPGA_Sandbox/RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_xbar_0/ip_design_xbar_0_stub.vhdl -- Design : ip_design_xbar_0 -- Purpose : Stub declaration of top-level module interface -- Device : xc7z020clg484-1 -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity ip_design_xbar_0 is Port ( aclk : in STD_LOGIC; aresetn : in STD_LOGIC; s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 ); s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 ); s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 ); s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 ); s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 ); s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 ); m_axi_awaddr : out STD_LOGIC_VECTOR ( 191 downto 0 ); m_axi_awprot : out STD_LOGIC_VECTOR ( 17 downto 0 ); m_axi_awvalid : out STD_LOGIC_VECTOR ( 5 downto 0 ); m_axi_awready : in STD_LOGIC_VECTOR ( 5 downto 0 ); m_axi_wdata : out STD_LOGIC_VECTOR ( 191 downto 0 ); m_axi_wstrb : out STD_LOGIC_VECTOR ( 23 downto 0 ); m_axi_wvalid : out STD_LOGIC_VECTOR ( 5 downto 0 ); m_axi_wready : in STD_LOGIC_VECTOR ( 5 downto 0 ); m_axi_bresp : in STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_bvalid : in STD_LOGIC_VECTOR ( 5 downto 0 ); m_axi_bready : out STD_LOGIC_VECTOR ( 5 downto 0 ); m_axi_araddr : out STD_LOGIC_VECTOR ( 191 downto 0 ); m_axi_arprot : out STD_LOGIC_VECTOR ( 17 downto 0 ); m_axi_arvalid : out STD_LOGIC_VECTOR ( 5 downto 0 ); m_axi_arready : in STD_LOGIC_VECTOR ( 5 downto 0 ); m_axi_rdata : in STD_LOGIC_VECTOR ( 191 downto 0 ); m_axi_rresp : in STD_LOGIC_VECTOR ( 11 downto 0 ); m_axi_rvalid : in STD_LOGIC_VECTOR ( 5 downto 0 ); m_axi_rready : out STD_LOGIC_VECTOR ( 5 downto 0 ) ); end ip_design_xbar_0; architecture stub of ip_design_xbar_0 is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axi_awaddr[31:0],s_axi_awprot[2:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_araddr[31:0],s_axi_arprot[2:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awaddr[191:0],m_axi_awprot[17:0],m_axi_awvalid[5:0],m_axi_awready[5:0],m_axi_wdata[191:0],m_axi_wstrb[23:0],m_axi_wvalid[5:0],m_axi_wready[5:0],m_axi_bresp[11:0],m_axi_bvalid[5:0],m_axi_bready[5:0],m_axi_araddr[191:0],m_axi_arprot[17:0],m_axi_arvalid[5:0],m_axi_arready[5:0],m_axi_rdata[191:0],m_axi_rresp[11:0],m_axi_rvalid[5:0],m_axi_rready[5:0]"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "axi_crossbar_v2_1_15_axi_crossbar,Vivado 2017.3"; begin end;

mit

MarkBlanco/FPGA_Sandbox

RecComp/Lab2/ug871-design-files/Interface_Synthesis/lab4/axi_interfaces_prj/solution2/impl/ip/hdl/vhdl/axi_interfaces.vhd

3

116677

-- ============================================================== -- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2017.2 -- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. -- -- =========================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity axi_interfaces is generic ( C_S_AXI_AXILITES_ADDR_WIDTH : INTEGER := 4; C_S_AXI_AXILITES_DATA_WIDTH : INTEGER := 32 ); port ( ap_clk : IN STD_LOGIC; ap_rst_n : IN STD_LOGIC; d_o_0_TREADY : IN STD_LOGIC; d_o_1_TREADY : IN STD_LOGIC; d_o_2_TREADY : IN STD_LOGIC; d_o_3_TREADY : IN STD_LOGIC; d_o_4_TREADY : IN STD_LOGIC; d_o_5_TREADY : IN STD_LOGIC; d_o_6_TREADY : IN STD_LOGIC; d_o_7_TREADY : IN STD_LOGIC; d_o_0_TDATA : OUT STD_LOGIC_VECTOR (15 downto 0); d_o_0_TVALID : OUT STD_LOGIC; d_o_1_TDATA : OUT STD_LOGIC_VECTOR (15 downto 0); d_o_1_TVALID : OUT STD_LOGIC; d_o_2_TDATA : OUT STD_LOGIC_VECTOR (15 downto 0); d_o_2_TVALID : OUT STD_LOGIC; d_o_3_TDATA : OUT STD_LOGIC_VECTOR (15 downto 0); d_o_3_TVALID : OUT STD_LOGIC; d_o_4_TDATA : OUT STD_LOGIC_VECTOR (15 downto 0); d_o_4_TVALID : OUT STD_LOGIC; d_o_5_TDATA : OUT STD_LOGIC_VECTOR (15 downto 0); d_o_5_TVALID : OUT STD_LOGIC; d_o_6_TDATA : OUT STD_LOGIC_VECTOR (15 downto 0); d_o_6_TVALID : OUT STD_LOGIC; d_o_7_TDATA : OUT STD_LOGIC_VECTOR (15 downto 0); d_o_7_TVALID : OUT STD_LOGIC; d_i_0_TDATA : IN STD_LOGIC_VECTOR (15 downto 0); d_i_0_TVALID : IN STD_LOGIC; d_i_0_TREADY : OUT STD_LOGIC; d_i_1_TDATA : IN STD_LOGIC_VECTOR (15 downto 0); d_i_1_TVALID : IN STD_LOGIC; d_i_1_TREADY : OUT STD_LOGIC; d_i_2_TDATA : IN STD_LOGIC_VECTOR (15 downto 0); d_i_2_TVALID : IN STD_LOGIC; d_i_2_TREADY : OUT STD_LOGIC; d_i_3_TDATA : IN STD_LOGIC_VECTOR (15 downto 0); d_i_3_TVALID : IN STD_LOGIC; d_i_3_TREADY : OUT STD_LOGIC; d_i_4_TDATA : IN STD_LOGIC_VECTOR (15 downto 0); d_i_4_TVALID : IN STD_LOGIC; d_i_4_TREADY : OUT STD_LOGIC; d_i_5_TDATA : IN STD_LOGIC_VECTOR (15 downto 0); d_i_5_TVALID : IN STD_LOGIC; d_i_5_TREADY : OUT STD_LOGIC; d_i_6_TDATA : IN STD_LOGIC_VECTOR (15 downto 0); d_i_6_TVALID : IN STD_LOGIC; d_i_6_TREADY : OUT STD_LOGIC; d_i_7_TDATA : IN STD_LOGIC_VECTOR (15 downto 0); d_i_7_TVALID : IN STD_LOGIC; d_i_7_TREADY : OUT STD_LOGIC; s_axi_AXILiteS_AWVALID : IN STD_LOGIC; s_axi_AXILiteS_AWREADY : OUT STD_LOGIC; s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0); s_axi_AXILiteS_WVALID : IN STD_LOGIC; s_axi_AXILiteS_WREADY : OUT STD_LOGIC; s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0); s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH/8-1 downto 0); s_axi_AXILiteS_ARVALID : IN STD_LOGIC; s_axi_AXILiteS_ARREADY : OUT STD_LOGIC; s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0); s_axi_AXILiteS_RVALID : OUT STD_LOGIC; s_axi_AXILiteS_RREADY : IN STD_LOGIC; s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0); s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0); s_axi_AXILiteS_BVALID : OUT STD_LOGIC; s_axi_AXILiteS_BREADY : IN STD_LOGIC; s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0); interrupt : OUT STD_LOGIC ); end; architecture behav of axi_interfaces is attribute CORE_GENERATION_INFO : STRING; attribute CORE_GENERATION_INFO of behav : architecture is "axi_interfaces,hls_ip_2017_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7k160tfbg484-1,HLS_INPUT_CLOCK=4.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=4.162500,HLS_SYN_LAT=5,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=2139,HLS_SYN_LUT=1196}"; constant ap_const_logic_1 : STD_LOGIC := '1'; constant ap_const_logic_0 : STD_LOGIC := '0'; constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (1 downto 0) := "01"; constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (1 downto 0) := "10"; constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; constant ap_const_boolean_1 : BOOLEAN := true; constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1"; constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001"; constant ap_const_boolean_0 : BOOLEAN := false; constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0"; constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00"; constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10"; constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11"; constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01"; constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20; constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000"; constant ap_const_lv6_8 : STD_LOGIC_VECTOR (5 downto 0) := "001000"; constant ap_const_lv6_20 : STD_LOGIC_VECTOR (5 downto 0) := "100000"; signal ap_rst_n_inv : STD_LOGIC; signal ap_start : STD_LOGIC; signal ap_done : STD_LOGIC; signal ap_idle : STD_LOGIC; signal ap_CS_fsm : STD_LOGIC_VECTOR (1 downto 0) := "01"; attribute fsm_encoding : string; attribute fsm_encoding of ap_CS_fsm : signal is "none"; signal ap_CS_fsm_state1 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none"; signal ap_ready : STD_LOGIC; signal exitcond_fu_246_p2 : STD_LOGIC_VECTOR (0 downto 0); signal ap_CS_fsm_pp0_stage0 : STD_LOGIC; attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none"; signal ap_enable_reg_pp0_iter0 : STD_LOGIC; signal ap_block_state2_pp0_stage0_iter0 : BOOLEAN; signal d_i_0_0_vld_out : STD_LOGIC; signal d_i_1_0_vld_out : STD_LOGIC; signal d_i_2_0_vld_out : STD_LOGIC; signal d_i_3_0_vld_out : STD_LOGIC; signal d_i_4_0_vld_out : STD_LOGIC; signal d_i_5_0_vld_out : STD_LOGIC; signal d_i_6_0_vld_out : STD_LOGIC; signal d_i_7_0_vld_out : STD_LOGIC; signal ap_block_state4_pp0_stage0_iter1 : BOOLEAN; signal d_o_0_1_ack_in : STD_LOGIC; signal d_o_1_1_ack_in : STD_LOGIC; signal d_o_2_1_ack_in : STD_LOGIC; signal d_o_3_1_ack_in : STD_LOGIC; signal d_o_4_1_ack_in : STD_LOGIC; signal d_o_5_1_ack_in : STD_LOGIC; signal d_o_6_1_ack_in : STD_LOGIC; signal d_o_7_1_ack_in : STD_LOGIC; signal ap_block_state4_io : BOOLEAN; signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0'; signal ap_block_state3_pp0_stage0_iter2 : BOOLEAN; signal ap_block_state3_io : BOOLEAN; signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0'; signal ap_block_pp0_stage0_flag00011001 : BOOLEAN; signal d_o_0_1_data_out : STD_LOGIC_VECTOR (15 downto 0); signal d_o_0_1_vld_in : STD_LOGIC; signal d_o_0_1_vld_out : STD_LOGIC; signal d_o_0_1_ack_out : STD_LOGIC; signal d_o_0_1_payload_A : STD_LOGIC_VECTOR (15 downto 0); signal d_o_0_1_payload_B : STD_LOGIC_VECTOR (15 downto 0); signal d_o_0_1_sel_rd : STD_LOGIC := '0'; signal d_o_0_1_sel_wr : STD_LOGIC := '0'; signal d_o_0_1_sel : STD_LOGIC; signal d_o_0_1_load_A : STD_LOGIC; signal d_o_0_1_load_B : STD_LOGIC; signal d_o_0_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00"; signal d_o_0_1_state_cmp_full : STD_LOGIC; signal d_o_1_1_data_out : STD_LOGIC_VECTOR (15 downto 0); signal d_o_1_1_vld_in : STD_LOGIC; signal d_o_1_1_vld_out : STD_LOGIC; signal d_o_1_1_ack_out : STD_LOGIC; signal d_o_1_1_payload_A : STD_LOGIC_VECTOR (15 downto 0); signal d_o_1_1_payload_B : STD_LOGIC_VECTOR (15 downto 0); signal d_o_1_1_sel_rd : STD_LOGIC := '0'; signal d_o_1_1_sel_wr : STD_LOGIC := '0'; signal d_o_1_1_sel : STD_LOGIC; signal d_o_1_1_load_A : STD_LOGIC; signal d_o_1_1_load_B : STD_LOGIC; signal d_o_1_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00"; signal d_o_1_1_state_cmp_full : STD_LOGIC; signal d_o_2_1_data_out : STD_LOGIC_VECTOR (15 downto 0); signal d_o_2_1_vld_in : STD_LOGIC; signal d_o_2_1_vld_out : STD_LOGIC; signal d_o_2_1_ack_out : STD_LOGIC; signal d_o_2_1_payload_A : STD_LOGIC_VECTOR (15 downto 0); signal d_o_2_1_payload_B : STD_LOGIC_VECTOR (15 downto 0); signal d_o_2_1_sel_rd : STD_LOGIC := '0'; signal d_o_2_1_sel_wr : STD_LOGIC := '0'; signal d_o_2_1_sel : STD_LOGIC; signal d_o_2_1_load_A : STD_LOGIC; signal d_o_2_1_load_B : STD_LOGIC; signal d_o_2_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00"; signal d_o_2_1_state_cmp_full : STD_LOGIC; signal d_o_3_1_data_out : STD_LOGIC_VECTOR (15 downto 0); signal d_o_3_1_vld_in : STD_LOGIC; signal d_o_3_1_vld_out : STD_LOGIC; signal d_o_3_1_ack_out : STD_LOGIC; signal d_o_3_1_payload_A : STD_LOGIC_VECTOR (15 downto 0); signal d_o_3_1_payload_B : STD_LOGIC_VECTOR (15 downto 0); signal d_o_3_1_sel_rd : STD_LOGIC := '0'; signal d_o_3_1_sel_wr : STD_LOGIC := '0'; signal d_o_3_1_sel : STD_LOGIC; signal d_o_3_1_load_A : STD_LOGIC; signal d_o_3_1_load_B : STD_LOGIC; signal d_o_3_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00"; signal d_o_3_1_state_cmp_full : STD_LOGIC; signal d_o_4_1_data_out : STD_LOGIC_VECTOR (15 downto 0); signal d_o_4_1_vld_in : STD_LOGIC; signal d_o_4_1_vld_out : STD_LOGIC; signal d_o_4_1_ack_out : STD_LOGIC; signal d_o_4_1_payload_A : STD_LOGIC_VECTOR (15 downto 0); signal d_o_4_1_payload_B : STD_LOGIC_VECTOR (15 downto 0); signal d_o_4_1_sel_rd : STD_LOGIC := '0'; signal d_o_4_1_sel_wr : STD_LOGIC := '0'; signal d_o_4_1_sel : STD_LOGIC; signal d_o_4_1_load_A : STD_LOGIC; signal d_o_4_1_load_B : STD_LOGIC; signal d_o_4_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00"; signal d_o_4_1_state_cmp_full : STD_LOGIC; signal d_o_5_1_data_out : STD_LOGIC_VECTOR (15 downto 0); signal d_o_5_1_vld_in : STD_LOGIC; signal d_o_5_1_vld_out : STD_LOGIC; signal d_o_5_1_ack_out : STD_LOGIC; signal d_o_5_1_payload_A : STD_LOGIC_VECTOR (15 downto 0); signal d_o_5_1_payload_B : STD_LOGIC_VECTOR (15 downto 0); signal d_o_5_1_sel_rd : STD_LOGIC := '0'; signal d_o_5_1_sel_wr : STD_LOGIC := '0'; signal d_o_5_1_sel : STD_LOGIC; signal d_o_5_1_load_A : STD_LOGIC; signal d_o_5_1_load_B : STD_LOGIC; signal d_o_5_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00"; signal d_o_5_1_state_cmp_full : STD_LOGIC; signal d_o_6_1_data_out : STD_LOGIC_VECTOR (15 downto 0); signal d_o_6_1_vld_in : STD_LOGIC; signal d_o_6_1_vld_out : STD_LOGIC; signal d_o_6_1_ack_out : STD_LOGIC; signal d_o_6_1_payload_A : STD_LOGIC_VECTOR (15 downto 0); signal d_o_6_1_payload_B : STD_LOGIC_VECTOR (15 downto 0); signal d_o_6_1_sel_rd : STD_LOGIC := '0'; signal d_o_6_1_sel_wr : STD_LOGIC := '0'; signal d_o_6_1_sel : STD_LOGIC; signal d_o_6_1_load_A : STD_LOGIC; signal d_o_6_1_load_B : STD_LOGIC; signal d_o_6_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00"; signal d_o_6_1_state_cmp_full : STD_LOGIC; signal d_o_7_1_data_out : STD_LOGIC_VECTOR (15 downto 0); signal d_o_7_1_vld_in : STD_LOGIC; signal d_o_7_1_vld_out : STD_LOGIC; signal d_o_7_1_ack_out : STD_LOGIC; signal d_o_7_1_payload_A : STD_LOGIC_VECTOR (15 downto 0); signal d_o_7_1_payload_B : STD_LOGIC_VECTOR (15 downto 0); signal d_o_7_1_sel_rd : STD_LOGIC := '0'; signal d_o_7_1_sel_wr : STD_LOGIC := '0'; signal d_o_7_1_sel : STD_LOGIC; signal d_o_7_1_load_A : STD_LOGIC; signal d_o_7_1_load_B : STD_LOGIC; signal d_o_7_1_state : STD_LOGIC_VECTOR (1 downto 0) := "00"; signal d_o_7_1_state_cmp_full : STD_LOGIC; signal d_i_0_0_data_out : STD_LOGIC_VECTOR (15 downto 0); signal d_i_0_0_vld_in : STD_LOGIC; signal d_i_0_0_ack_in : STD_LOGIC; signal d_i_0_0_ack_out : STD_LOGIC; signal d_i_0_0_payload_A : STD_LOGIC_VECTOR (15 downto 0); signal d_i_0_0_payload_B : STD_LOGIC_VECTOR (15 downto 0); signal d_i_0_0_sel_rd : STD_LOGIC := '0'; signal d_i_0_0_sel_wr : STD_LOGIC := '0'; signal d_i_0_0_sel : STD_LOGIC; signal d_i_0_0_load_A : STD_LOGIC; signal d_i_0_0_load_B : STD_LOGIC; signal d_i_0_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00"; signal d_i_0_0_state_cmp_full : STD_LOGIC; signal d_i_1_0_data_out : STD_LOGIC_VECTOR (15 downto 0); signal d_i_1_0_vld_in : STD_LOGIC; signal d_i_1_0_ack_in : STD_LOGIC; signal d_i_1_0_ack_out : STD_LOGIC; signal d_i_1_0_payload_A : STD_LOGIC_VECTOR (15 downto 0); signal d_i_1_0_payload_B : STD_LOGIC_VECTOR (15 downto 0); signal d_i_1_0_sel_rd : STD_LOGIC := '0'; signal d_i_1_0_sel_wr : STD_LOGIC := '0'; signal d_i_1_0_sel : STD_LOGIC; signal d_i_1_0_load_A : STD_LOGIC; signal d_i_1_0_load_B : STD_LOGIC; signal d_i_1_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00"; signal d_i_1_0_state_cmp_full : STD_LOGIC; signal d_i_2_0_data_out : STD_LOGIC_VECTOR (15 downto 0); signal d_i_2_0_vld_in : STD_LOGIC; signal d_i_2_0_ack_in : STD_LOGIC; signal d_i_2_0_ack_out : STD_LOGIC; signal d_i_2_0_payload_A : STD_LOGIC_VECTOR (15 downto 0); signal d_i_2_0_payload_B : STD_LOGIC_VECTOR (15 downto 0); signal d_i_2_0_sel_rd : STD_LOGIC := '0'; signal d_i_2_0_sel_wr : STD_LOGIC := '0'; signal d_i_2_0_sel : STD_LOGIC; signal d_i_2_0_load_A : STD_LOGIC; signal d_i_2_0_load_B : STD_LOGIC; signal d_i_2_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00"; signal d_i_2_0_state_cmp_full : STD_LOGIC; signal d_i_3_0_data_out : STD_LOGIC_VECTOR (15 downto 0); signal d_i_3_0_vld_in : STD_LOGIC; signal d_i_3_0_ack_in : STD_LOGIC; signal d_i_3_0_ack_out : STD_LOGIC; signal d_i_3_0_payload_A : STD_LOGIC_VECTOR (15 downto 0); signal d_i_3_0_payload_B : STD_LOGIC_VECTOR (15 downto 0); signal d_i_3_0_sel_rd : STD_LOGIC := '0'; signal d_i_3_0_sel_wr : STD_LOGIC := '0'; signal d_i_3_0_sel : STD_LOGIC; signal d_i_3_0_load_A : STD_LOGIC; signal d_i_3_0_load_B : STD_LOGIC; signal d_i_3_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00"; signal d_i_3_0_state_cmp_full : STD_LOGIC; signal d_i_4_0_data_out : STD_LOGIC_VECTOR (15 downto 0); signal d_i_4_0_vld_in : STD_LOGIC; signal d_i_4_0_ack_in : STD_LOGIC; signal d_i_4_0_ack_out : STD_LOGIC; signal d_i_4_0_payload_A : STD_LOGIC_VECTOR (15 downto 0); signal d_i_4_0_payload_B : STD_LOGIC_VECTOR (15 downto 0); signal d_i_4_0_sel_rd : STD_LOGIC := '0'; signal d_i_4_0_sel_wr : STD_LOGIC := '0'; signal d_i_4_0_sel : STD_LOGIC; signal d_i_4_0_load_A : STD_LOGIC; signal d_i_4_0_load_B : STD_LOGIC; signal d_i_4_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00"; signal d_i_4_0_state_cmp_full : STD_LOGIC; signal d_i_5_0_data_out : STD_LOGIC_VECTOR (15 downto 0); signal d_i_5_0_vld_in : STD_LOGIC; signal d_i_5_0_ack_in : STD_LOGIC; signal d_i_5_0_ack_out : STD_LOGIC; signal d_i_5_0_payload_A : STD_LOGIC_VECTOR (15 downto 0); signal d_i_5_0_payload_B : STD_LOGIC_VECTOR (15 downto 0); signal d_i_5_0_sel_rd : STD_LOGIC := '0'; signal d_i_5_0_sel_wr : STD_LOGIC := '0'; signal d_i_5_0_sel : STD_LOGIC; signal d_i_5_0_load_A : STD_LOGIC; signal d_i_5_0_load_B : STD_LOGIC; signal d_i_5_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00"; signal d_i_5_0_state_cmp_full : STD_LOGIC; signal d_i_6_0_data_out : STD_LOGIC_VECTOR (15 downto 0); signal d_i_6_0_vld_in : STD_LOGIC; signal d_i_6_0_ack_in : STD_LOGIC; signal d_i_6_0_ack_out : STD_LOGIC; signal d_i_6_0_payload_A : STD_LOGIC_VECTOR (15 downto 0); signal d_i_6_0_payload_B : STD_LOGIC_VECTOR (15 downto 0); signal d_i_6_0_sel_rd : STD_LOGIC := '0'; signal d_i_6_0_sel_wr : STD_LOGIC := '0'; signal d_i_6_0_sel : STD_LOGIC; signal d_i_6_0_load_A : STD_LOGIC; signal d_i_6_0_load_B : STD_LOGIC; signal d_i_6_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00"; signal d_i_6_0_state_cmp_full : STD_LOGIC; signal d_i_7_0_data_out : STD_LOGIC_VECTOR (15 downto 0); signal d_i_7_0_vld_in : STD_LOGIC; signal d_i_7_0_ack_in : STD_LOGIC; signal d_i_7_0_ack_out : STD_LOGIC; signal d_i_7_0_payload_A : STD_LOGIC_VECTOR (15 downto 0); signal d_i_7_0_payload_B : STD_LOGIC_VECTOR (15 downto 0); signal d_i_7_0_sel_rd : STD_LOGIC := '0'; signal d_i_7_0_sel_wr : STD_LOGIC := '0'; signal d_i_7_0_sel : STD_LOGIC; signal d_i_7_0_load_A : STD_LOGIC; signal d_i_7_0_load_B : STD_LOGIC; signal d_i_7_0_state : STD_LOGIC_VECTOR (1 downto 0) := "00"; signal d_i_7_0_state_cmp_full : STD_LOGIC; signal acc_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; signal acc_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; signal acc_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; signal acc_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; signal acc_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; signal acc_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; signal acc_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; signal acc_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000"; signal d_o_0_TDATA_blk_n : STD_LOGIC; signal ap_block_pp0_stage0_flag00000000 : BOOLEAN; signal d_o_1_TDATA_blk_n : STD_LOGIC; signal d_o_2_TDATA_blk_n : STD_LOGIC; signal d_o_3_TDATA_blk_n : STD_LOGIC; signal d_o_4_TDATA_blk_n : STD_LOGIC; signal d_o_5_TDATA_blk_n : STD_LOGIC; signal d_o_6_TDATA_blk_n : STD_LOGIC; signal d_o_7_TDATA_blk_n : STD_LOGIC; signal d_i_0_TDATA_blk_n : STD_LOGIC; signal d_i_1_TDATA_blk_n : STD_LOGIC; signal d_i_2_TDATA_blk_n : STD_LOGIC; signal d_i_3_TDATA_blk_n : STD_LOGIC; signal d_i_4_TDATA_blk_n : STD_LOGIC; signal d_i_5_TDATA_blk_n : STD_LOGIC; signal d_i_6_TDATA_blk_n : STD_LOGIC; signal d_i_7_TDATA_blk_n : STD_LOGIC; signal i1_reg_218 : STD_LOGIC_VECTOR (4 downto 0); signal tmp_17_fu_242_p1 : STD_LOGIC_VECTOR (4 downto 0); signal tmp_17_reg_502 : STD_LOGIC_VECTOR (4 downto 0); signal exitcond_reg_507 : STD_LOGIC_VECTOR (0 downto 0); signal ap_reg_pp0_iter1_exitcond_reg_507 : STD_LOGIC_VECTOR (0 downto 0); signal tmp_8_fu_278_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_2_1_fu_309_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_2_2_fu_340_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_2_3_fu_371_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_2_4_fu_402_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_2_5_fu_433_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_2_6_fu_464_p2 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_2_7_fu_495_p2 : STD_LOGIC_VECTOR (15 downto 0); signal ap_block_pp0_stage0_flag00011011 : BOOLEAN; signal i1_phi_fu_222_p6 : STD_LOGIC_VECTOR (4 downto 0); signal tmp_1_fu_266_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_1_1_fu_297_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_1_2_fu_328_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_1_3_fu_359_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_1_4_fu_390_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_1_5_fu_421_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_1_6_fu_452_p2 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_1_7_fu_483_p2 : STD_LOGIC_VECTOR (31 downto 0); signal ap_block_pp0_stage0_flag00001001 : BOOLEAN; signal i1_cast_fu_232_p1 : STD_LOGIC_VECTOR (5 downto 0); signal i_1_7_fu_236_p2 : STD_LOGIC_VECTOR (5 downto 0); signal tmp1_fu_258_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_2_fu_262_p1 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_s_fu_289_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_10_fu_293_p1 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_9_fu_320_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_11_fu_324_p1 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_3_fu_351_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_12_fu_355_p1 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_4_fu_382_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_13_fu_386_p1 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_5_fu_413_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_14_fu_417_p1 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_6_fu_444_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_15_fu_448_p1 : STD_LOGIC_VECTOR (15 downto 0); signal tmp_7_fu_475_p1 : STD_LOGIC_VECTOR (31 downto 0); signal tmp_16_fu_479_p1 : STD_LOGIC_VECTOR (15 downto 0); signal ap_NS_fsm : STD_LOGIC_VECTOR (1 downto 0); signal ap_idle_pp0_0to1 : STD_LOGIC; signal ap_reset_idle_pp0 : STD_LOGIC; signal ap_idle_pp0 : STD_LOGIC; signal ap_enable_pp0 : STD_LOGIC; signal ap_condition_1051 : BOOLEAN; component axi_interfaces_AXILiteS_s_axi IS generic ( C_S_AXI_ADDR_WIDTH : INTEGER; C_S_AXI_DATA_WIDTH : INTEGER ); port ( AWVALID : IN STD_LOGIC; AWREADY : OUT STD_LOGIC; AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0); WVALID : IN STD_LOGIC; WREADY : OUT STD_LOGIC; WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0); WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0); ARVALID : IN STD_LOGIC; ARREADY : OUT STD_LOGIC; ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0); RVALID : OUT STD_LOGIC; RREADY : IN STD_LOGIC; RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0); RRESP : OUT STD_LOGIC_VECTOR (1 downto 0); BVALID : OUT STD_LOGIC; BREADY : IN STD_LOGIC; BRESP : OUT STD_LOGIC_VECTOR (1 downto 0); ACLK : IN STD_LOGIC; ARESET : IN STD_LOGIC; ACLK_EN : IN STD_LOGIC; ap_start : OUT STD_LOGIC; interrupt : OUT STD_LOGIC; ap_ready : IN STD_LOGIC; ap_done : IN STD_LOGIC; ap_idle : IN STD_LOGIC ); end component; begin axi_interfaces_AXILiteS_s_axi_U : component axi_interfaces_AXILiteS_s_axi generic map ( C_S_AXI_ADDR_WIDTH => C_S_AXI_AXILITES_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_AXILITES_DATA_WIDTH) port map ( AWVALID => s_axi_AXILiteS_AWVALID, AWREADY => s_axi_AXILiteS_AWREADY, AWADDR => s_axi_AXILiteS_AWADDR, WVALID => s_axi_AXILiteS_WVALID, WREADY => s_axi_AXILiteS_WREADY, WDATA => s_axi_AXILiteS_WDATA, WSTRB => s_axi_AXILiteS_WSTRB, ARVALID => s_axi_AXILiteS_ARVALID, ARREADY => s_axi_AXILiteS_ARREADY, ARADDR => s_axi_AXILiteS_ARADDR, RVALID => s_axi_AXILiteS_RVALID, RREADY => s_axi_AXILiteS_RREADY, RDATA => s_axi_AXILiteS_RDATA, RRESP => s_axi_AXILiteS_RRESP, BVALID => s_axi_AXILiteS_BVALID, BREADY => s_axi_AXILiteS_BREADY, BRESP => s_axi_AXILiteS_BRESP, ACLK => ap_clk, ARESET => ap_rst_n_inv, ACLK_EN => ap_const_logic_1, ap_start => ap_start, interrupt => interrupt, ap_ready => ap_ready, ap_done => ap_done, ap_idle => ap_idle); ap_CS_fsm_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_CS_fsm <= ap_ST_fsm_state1; else ap_CS_fsm <= ap_NS_fsm; end if; end if; end process; ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_enable_reg_pp0_iter1 <= ap_const_logic_0; else if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0))) then ap_enable_reg_pp0_iter1 <= ap_start; elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then ap_enable_reg_pp0_iter1 <= ap_const_logic_0; end if; end if; end if; end process; ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then ap_enable_reg_pp0_iter2 <= ap_const_logic_0; else if ((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0)) then ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1; elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then ap_enable_reg_pp0_iter2 <= ap_const_logic_0; end if; end if; end if; end process; d_i_0_0_sel_rd_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_0_0_sel_rd <= ap_const_logic_0; else if (((ap_const_logic_1 = d_i_0_0_ack_out) and (ap_const_logic_1 = d_i_0_0_vld_out))) then d_i_0_0_sel_rd <= not(d_i_0_0_sel_rd); end if; end if; end if; end process; d_i_0_0_sel_wr_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_0_0_sel_wr <= ap_const_logic_0; else if (((ap_const_logic_1 = d_i_0_0_vld_in) and (ap_const_logic_1 = d_i_0_0_ack_in))) then d_i_0_0_sel_wr <= not(d_i_0_0_sel_wr); end if; end if; end if; end process; d_i_0_0_state_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_0_0_state <= ap_const_lv2_0; else if ((((ap_const_logic_0 = d_i_0_0_vld_in) and (ap_const_logic_1 = d_i_0_0_ack_out) and (ap_const_lv2_3 = d_i_0_0_state)) or ((ap_const_logic_0 = d_i_0_0_vld_in) and (ap_const_lv2_2 = d_i_0_0_state)))) then d_i_0_0_state <= ap_const_lv2_2; elsif ((((ap_const_logic_1 = d_i_0_0_vld_in) and (ap_const_logic_0 = d_i_0_0_ack_out) and (ap_const_lv2_3 = d_i_0_0_state)) or ((ap_const_logic_0 = d_i_0_0_ack_out) and (ap_const_lv2_1 = d_i_0_0_state)))) then d_i_0_0_state <= ap_const_lv2_1; elsif ((((ap_const_logic_1 = d_i_0_0_vld_in) and (ap_const_lv2_2 = d_i_0_0_state)) or ((ap_const_logic_1 = d_i_0_0_ack_out) and (ap_const_lv2_1 = d_i_0_0_state)) or ((ap_const_lv2_3 = d_i_0_0_state) and not(((ap_const_logic_1 = d_i_0_0_vld_in) and (ap_const_logic_0 = d_i_0_0_ack_out))) and not(((ap_const_logic_0 = d_i_0_0_vld_in) and (ap_const_logic_1 = d_i_0_0_ack_out)))))) then d_i_0_0_state <= ap_const_lv2_3; else d_i_0_0_state <= ap_const_lv2_2; end if; end if; end if; end process; d_i_1_0_sel_rd_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_1_0_sel_rd <= ap_const_logic_0; else if (((ap_const_logic_1 = d_i_1_0_ack_out) and (ap_const_logic_1 = d_i_1_0_vld_out))) then d_i_1_0_sel_rd <= not(d_i_1_0_sel_rd); end if; end if; end if; end process; d_i_1_0_sel_wr_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_1_0_sel_wr <= ap_const_logic_0; else if (((ap_const_logic_1 = d_i_1_0_vld_in) and (ap_const_logic_1 = d_i_1_0_ack_in))) then d_i_1_0_sel_wr <= not(d_i_1_0_sel_wr); end if; end if; end if; end process; d_i_1_0_state_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_1_0_state <= ap_const_lv2_0; else if ((((ap_const_logic_0 = d_i_1_0_vld_in) and (ap_const_logic_1 = d_i_1_0_ack_out) and (ap_const_lv2_3 = d_i_1_0_state)) or ((ap_const_logic_0 = d_i_1_0_vld_in) and (ap_const_lv2_2 = d_i_1_0_state)))) then d_i_1_0_state <= ap_const_lv2_2; elsif ((((ap_const_logic_1 = d_i_1_0_vld_in) and (ap_const_logic_0 = d_i_1_0_ack_out) and (ap_const_lv2_3 = d_i_1_0_state)) or ((ap_const_logic_0 = d_i_1_0_ack_out) and (ap_const_lv2_1 = d_i_1_0_state)))) then d_i_1_0_state <= ap_const_lv2_1; elsif ((((ap_const_logic_1 = d_i_1_0_vld_in) and (ap_const_lv2_2 = d_i_1_0_state)) or ((ap_const_logic_1 = d_i_1_0_ack_out) and (ap_const_lv2_1 = d_i_1_0_state)) or ((ap_const_lv2_3 = d_i_1_0_state) and not(((ap_const_logic_1 = d_i_1_0_vld_in) and (ap_const_logic_0 = d_i_1_0_ack_out))) and not(((ap_const_logic_0 = d_i_1_0_vld_in) and (ap_const_logic_1 = d_i_1_0_ack_out)))))) then d_i_1_0_state <= ap_const_lv2_3; else d_i_1_0_state <= ap_const_lv2_2; end if; end if; end if; end process; d_i_2_0_sel_rd_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_2_0_sel_rd <= ap_const_logic_0; else if (((ap_const_logic_1 = d_i_2_0_ack_out) and (ap_const_logic_1 = d_i_2_0_vld_out))) then d_i_2_0_sel_rd <= not(d_i_2_0_sel_rd); end if; end if; end if; end process; d_i_2_0_sel_wr_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_2_0_sel_wr <= ap_const_logic_0; else if (((ap_const_logic_1 = d_i_2_0_vld_in) and (ap_const_logic_1 = d_i_2_0_ack_in))) then d_i_2_0_sel_wr <= not(d_i_2_0_sel_wr); end if; end if; end if; end process; d_i_2_0_state_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_2_0_state <= ap_const_lv2_0; else if ((((ap_const_logic_0 = d_i_2_0_vld_in) and (ap_const_logic_1 = d_i_2_0_ack_out) and (ap_const_lv2_3 = d_i_2_0_state)) or ((ap_const_logic_0 = d_i_2_0_vld_in) and (ap_const_lv2_2 = d_i_2_0_state)))) then d_i_2_0_state <= ap_const_lv2_2; elsif ((((ap_const_logic_1 = d_i_2_0_vld_in) and (ap_const_logic_0 = d_i_2_0_ack_out) and (ap_const_lv2_3 = d_i_2_0_state)) or ((ap_const_logic_0 = d_i_2_0_ack_out) and (ap_const_lv2_1 = d_i_2_0_state)))) then d_i_2_0_state <= ap_const_lv2_1; elsif ((((ap_const_logic_1 = d_i_2_0_vld_in) and (ap_const_lv2_2 = d_i_2_0_state)) or ((ap_const_logic_1 = d_i_2_0_ack_out) and (ap_const_lv2_1 = d_i_2_0_state)) or ((ap_const_lv2_3 = d_i_2_0_state) and not(((ap_const_logic_1 = d_i_2_0_vld_in) and (ap_const_logic_0 = d_i_2_0_ack_out))) and not(((ap_const_logic_0 = d_i_2_0_vld_in) and (ap_const_logic_1 = d_i_2_0_ack_out)))))) then d_i_2_0_state <= ap_const_lv2_3; else d_i_2_0_state <= ap_const_lv2_2; end if; end if; end if; end process; d_i_3_0_sel_rd_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_3_0_sel_rd <= ap_const_logic_0; else if (((ap_const_logic_1 = d_i_3_0_ack_out) and (ap_const_logic_1 = d_i_3_0_vld_out))) then d_i_3_0_sel_rd <= not(d_i_3_0_sel_rd); end if; end if; end if; end process; d_i_3_0_sel_wr_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_3_0_sel_wr <= ap_const_logic_0; else if (((ap_const_logic_1 = d_i_3_0_vld_in) and (ap_const_logic_1 = d_i_3_0_ack_in))) then d_i_3_0_sel_wr <= not(d_i_3_0_sel_wr); end if; end if; end if; end process; d_i_3_0_state_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_3_0_state <= ap_const_lv2_0; else if ((((ap_const_logic_0 = d_i_3_0_vld_in) and (ap_const_logic_1 = d_i_3_0_ack_out) and (ap_const_lv2_3 = d_i_3_0_state)) or ((ap_const_logic_0 = d_i_3_0_vld_in) and (ap_const_lv2_2 = d_i_3_0_state)))) then d_i_3_0_state <= ap_const_lv2_2; elsif ((((ap_const_logic_1 = d_i_3_0_vld_in) and (ap_const_logic_0 = d_i_3_0_ack_out) and (ap_const_lv2_3 = d_i_3_0_state)) or ((ap_const_logic_0 = d_i_3_0_ack_out) and (ap_const_lv2_1 = d_i_3_0_state)))) then d_i_3_0_state <= ap_const_lv2_1; elsif ((((ap_const_logic_1 = d_i_3_0_vld_in) and (ap_const_lv2_2 = d_i_3_0_state)) or ((ap_const_logic_1 = d_i_3_0_ack_out) and (ap_const_lv2_1 = d_i_3_0_state)) or ((ap_const_lv2_3 = d_i_3_0_state) and not(((ap_const_logic_1 = d_i_3_0_vld_in) and (ap_const_logic_0 = d_i_3_0_ack_out))) and not(((ap_const_logic_0 = d_i_3_0_vld_in) and (ap_const_logic_1 = d_i_3_0_ack_out)))))) then d_i_3_0_state <= ap_const_lv2_3; else d_i_3_0_state <= ap_const_lv2_2; end if; end if; end if; end process; d_i_4_0_sel_rd_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_4_0_sel_rd <= ap_const_logic_0; else if (((ap_const_logic_1 = d_i_4_0_ack_out) and (ap_const_logic_1 = d_i_4_0_vld_out))) then d_i_4_0_sel_rd <= not(d_i_4_0_sel_rd); end if; end if; end if; end process; d_i_4_0_sel_wr_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_4_0_sel_wr <= ap_const_logic_0; else if (((ap_const_logic_1 = d_i_4_0_vld_in) and (ap_const_logic_1 = d_i_4_0_ack_in))) then d_i_4_0_sel_wr <= not(d_i_4_0_sel_wr); end if; end if; end if; end process; d_i_4_0_state_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_4_0_state <= ap_const_lv2_0; else if ((((ap_const_logic_0 = d_i_4_0_vld_in) and (ap_const_logic_1 = d_i_4_0_ack_out) and (ap_const_lv2_3 = d_i_4_0_state)) or ((ap_const_logic_0 = d_i_4_0_vld_in) and (ap_const_lv2_2 = d_i_4_0_state)))) then d_i_4_0_state <= ap_const_lv2_2; elsif ((((ap_const_logic_1 = d_i_4_0_vld_in) and (ap_const_logic_0 = d_i_4_0_ack_out) and (ap_const_lv2_3 = d_i_4_0_state)) or ((ap_const_logic_0 = d_i_4_0_ack_out) and (ap_const_lv2_1 = d_i_4_0_state)))) then d_i_4_0_state <= ap_const_lv2_1; elsif ((((ap_const_logic_1 = d_i_4_0_vld_in) and (ap_const_lv2_2 = d_i_4_0_state)) or ((ap_const_logic_1 = d_i_4_0_ack_out) and (ap_const_lv2_1 = d_i_4_0_state)) or ((ap_const_lv2_3 = d_i_4_0_state) and not(((ap_const_logic_1 = d_i_4_0_vld_in) and (ap_const_logic_0 = d_i_4_0_ack_out))) and not(((ap_const_logic_0 = d_i_4_0_vld_in) and (ap_const_logic_1 = d_i_4_0_ack_out)))))) then d_i_4_0_state <= ap_const_lv2_3; else d_i_4_0_state <= ap_const_lv2_2; end if; end if; end if; end process; d_i_5_0_sel_rd_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_5_0_sel_rd <= ap_const_logic_0; else if (((ap_const_logic_1 = d_i_5_0_ack_out) and (ap_const_logic_1 = d_i_5_0_vld_out))) then d_i_5_0_sel_rd <= not(d_i_5_0_sel_rd); end if; end if; end if; end process; d_i_5_0_sel_wr_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_5_0_sel_wr <= ap_const_logic_0; else if (((ap_const_logic_1 = d_i_5_0_vld_in) and (ap_const_logic_1 = d_i_5_0_ack_in))) then d_i_5_0_sel_wr <= not(d_i_5_0_sel_wr); end if; end if; end if; end process; d_i_5_0_state_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_5_0_state <= ap_const_lv2_0; else if ((((ap_const_logic_0 = d_i_5_0_vld_in) and (ap_const_logic_1 = d_i_5_0_ack_out) and (ap_const_lv2_3 = d_i_5_0_state)) or ((ap_const_logic_0 = d_i_5_0_vld_in) and (ap_const_lv2_2 = d_i_5_0_state)))) then d_i_5_0_state <= ap_const_lv2_2; elsif ((((ap_const_logic_1 = d_i_5_0_vld_in) and (ap_const_logic_0 = d_i_5_0_ack_out) and (ap_const_lv2_3 = d_i_5_0_state)) or ((ap_const_logic_0 = d_i_5_0_ack_out) and (ap_const_lv2_1 = d_i_5_0_state)))) then d_i_5_0_state <= ap_const_lv2_1; elsif ((((ap_const_logic_1 = d_i_5_0_vld_in) and (ap_const_lv2_2 = d_i_5_0_state)) or ((ap_const_logic_1 = d_i_5_0_ack_out) and (ap_const_lv2_1 = d_i_5_0_state)) or ((ap_const_lv2_3 = d_i_5_0_state) and not(((ap_const_logic_1 = d_i_5_0_vld_in) and (ap_const_logic_0 = d_i_5_0_ack_out))) and not(((ap_const_logic_0 = d_i_5_0_vld_in) and (ap_const_logic_1 = d_i_5_0_ack_out)))))) then d_i_5_0_state <= ap_const_lv2_3; else d_i_5_0_state <= ap_const_lv2_2; end if; end if; end if; end process; d_i_6_0_sel_rd_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_6_0_sel_rd <= ap_const_logic_0; else if (((ap_const_logic_1 = d_i_6_0_ack_out) and (ap_const_logic_1 = d_i_6_0_vld_out))) then d_i_6_0_sel_rd <= not(d_i_6_0_sel_rd); end if; end if; end if; end process; d_i_6_0_sel_wr_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_6_0_sel_wr <= ap_const_logic_0; else if (((ap_const_logic_1 = d_i_6_0_vld_in) and (ap_const_logic_1 = d_i_6_0_ack_in))) then d_i_6_0_sel_wr <= not(d_i_6_0_sel_wr); end if; end if; end if; end process; d_i_6_0_state_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_6_0_state <= ap_const_lv2_0; else if ((((ap_const_logic_0 = d_i_6_0_vld_in) and (ap_const_logic_1 = d_i_6_0_ack_out) and (ap_const_lv2_3 = d_i_6_0_state)) or ((ap_const_logic_0 = d_i_6_0_vld_in) and (ap_const_lv2_2 = d_i_6_0_state)))) then d_i_6_0_state <= ap_const_lv2_2; elsif ((((ap_const_logic_1 = d_i_6_0_vld_in) and (ap_const_logic_0 = d_i_6_0_ack_out) and (ap_const_lv2_3 = d_i_6_0_state)) or ((ap_const_logic_0 = d_i_6_0_ack_out) and (ap_const_lv2_1 = d_i_6_0_state)))) then d_i_6_0_state <= ap_const_lv2_1; elsif ((((ap_const_logic_1 = d_i_6_0_vld_in) and (ap_const_lv2_2 = d_i_6_0_state)) or ((ap_const_logic_1 = d_i_6_0_ack_out) and (ap_const_lv2_1 = d_i_6_0_state)) or ((ap_const_lv2_3 = d_i_6_0_state) and not(((ap_const_logic_1 = d_i_6_0_vld_in) and (ap_const_logic_0 = d_i_6_0_ack_out))) and not(((ap_const_logic_0 = d_i_6_0_vld_in) and (ap_const_logic_1 = d_i_6_0_ack_out)))))) then d_i_6_0_state <= ap_const_lv2_3; else d_i_6_0_state <= ap_const_lv2_2; end if; end if; end if; end process; d_i_7_0_sel_rd_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_7_0_sel_rd <= ap_const_logic_0; else if (((ap_const_logic_1 = d_i_7_0_ack_out) and (ap_const_logic_1 = d_i_7_0_vld_out))) then d_i_7_0_sel_rd <= not(d_i_7_0_sel_rd); end if; end if; end if; end process; d_i_7_0_sel_wr_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_7_0_sel_wr <= ap_const_logic_0; else if (((ap_const_logic_1 = d_i_7_0_vld_in) and (ap_const_logic_1 = d_i_7_0_ack_in))) then d_i_7_0_sel_wr <= not(d_i_7_0_sel_wr); end if; end if; end if; end process; d_i_7_0_state_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_i_7_0_state <= ap_const_lv2_0; else if ((((ap_const_logic_0 = d_i_7_0_vld_in) and (ap_const_logic_1 = d_i_7_0_ack_out) and (ap_const_lv2_3 = d_i_7_0_state)) or ((ap_const_logic_0 = d_i_7_0_vld_in) and (ap_const_lv2_2 = d_i_7_0_state)))) then d_i_7_0_state <= ap_const_lv2_2; elsif ((((ap_const_logic_1 = d_i_7_0_vld_in) and (ap_const_logic_0 = d_i_7_0_ack_out) and (ap_const_lv2_3 = d_i_7_0_state)) or ((ap_const_logic_0 = d_i_7_0_ack_out) and (ap_const_lv2_1 = d_i_7_0_state)))) then d_i_7_0_state <= ap_const_lv2_1; elsif ((((ap_const_logic_1 = d_i_7_0_vld_in) and (ap_const_lv2_2 = d_i_7_0_state)) or ((ap_const_logic_1 = d_i_7_0_ack_out) and (ap_const_lv2_1 = d_i_7_0_state)) or ((ap_const_lv2_3 = d_i_7_0_state) and not(((ap_const_logic_1 = d_i_7_0_vld_in) and (ap_const_logic_0 = d_i_7_0_ack_out))) and not(((ap_const_logic_0 = d_i_7_0_vld_in) and (ap_const_logic_1 = d_i_7_0_ack_out)))))) then d_i_7_0_state <= ap_const_lv2_3; else d_i_7_0_state <= ap_const_lv2_2; end if; end if; end if; end process; d_o_0_1_sel_rd_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_0_1_sel_rd <= ap_const_logic_0; else if (((ap_const_logic_1 = d_o_0_1_ack_out) and (ap_const_logic_1 = d_o_0_1_vld_out))) then d_o_0_1_sel_rd <= not(d_o_0_1_sel_rd); end if; end if; end if; end process; d_o_0_1_sel_wr_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_0_1_sel_wr <= ap_const_logic_0; else if (((ap_const_logic_1 = d_o_0_1_vld_in) and (ap_const_logic_1 = d_o_0_1_ack_in))) then d_o_0_1_sel_wr <= not(d_o_0_1_sel_wr); end if; end if; end if; end process; d_o_0_1_state_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_0_1_state <= ap_const_lv2_0; else if ((((ap_const_logic_0 = d_o_0_1_vld_in) and (ap_const_logic_1 = d_o_0_1_ack_out) and (d_o_0_1_state = ap_const_lv2_3)) or ((ap_const_logic_0 = d_o_0_1_vld_in) and (d_o_0_1_state = ap_const_lv2_2)))) then d_o_0_1_state <= ap_const_lv2_2; elsif ((((ap_const_logic_1 = d_o_0_1_vld_in) and (ap_const_logic_0 = d_o_0_1_ack_out) and (d_o_0_1_state = ap_const_lv2_3)) or ((ap_const_logic_0 = d_o_0_1_ack_out) and (d_o_0_1_state = ap_const_lv2_1)))) then d_o_0_1_state <= ap_const_lv2_1; elsif ((((ap_const_logic_1 = d_o_0_1_vld_in) and (d_o_0_1_state = ap_const_lv2_2)) or ((ap_const_logic_1 = d_o_0_1_ack_out) and (d_o_0_1_state = ap_const_lv2_1)) or ((d_o_0_1_state = ap_const_lv2_3) and not(((ap_const_logic_1 = d_o_0_1_vld_in) and (ap_const_logic_0 = d_o_0_1_ack_out))) and not(((ap_const_logic_0 = d_o_0_1_vld_in) and (ap_const_logic_1 = d_o_0_1_ack_out)))))) then d_o_0_1_state <= ap_const_lv2_3; else d_o_0_1_state <= ap_const_lv2_2; end if; end if; end if; end process; d_o_1_1_sel_rd_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_1_1_sel_rd <= ap_const_logic_0; else if (((ap_const_logic_1 = d_o_1_1_ack_out) and (ap_const_logic_1 = d_o_1_1_vld_out))) then d_o_1_1_sel_rd <= not(d_o_1_1_sel_rd); end if; end if; end if; end process; d_o_1_1_sel_wr_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_1_1_sel_wr <= ap_const_logic_0; else if (((ap_const_logic_1 = d_o_1_1_vld_in) and (ap_const_logic_1 = d_o_1_1_ack_in))) then d_o_1_1_sel_wr <= not(d_o_1_1_sel_wr); end if; end if; end if; end process; d_o_1_1_state_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_1_1_state <= ap_const_lv2_0; else if ((((ap_const_logic_0 = d_o_1_1_vld_in) and (ap_const_logic_1 = d_o_1_1_ack_out) and (ap_const_lv2_3 = d_o_1_1_state)) or ((ap_const_logic_0 = d_o_1_1_vld_in) and (ap_const_lv2_2 = d_o_1_1_state)))) then d_o_1_1_state <= ap_const_lv2_2; elsif ((((ap_const_logic_1 = d_o_1_1_vld_in) and (ap_const_logic_0 = d_o_1_1_ack_out) and (ap_const_lv2_3 = d_o_1_1_state)) or ((ap_const_logic_0 = d_o_1_1_ack_out) and (ap_const_lv2_1 = d_o_1_1_state)))) then d_o_1_1_state <= ap_const_lv2_1; elsif ((((ap_const_logic_1 = d_o_1_1_vld_in) and (ap_const_lv2_2 = d_o_1_1_state)) or ((ap_const_logic_1 = d_o_1_1_ack_out) and (ap_const_lv2_1 = d_o_1_1_state)) or ((ap_const_lv2_3 = d_o_1_1_state) and not(((ap_const_logic_1 = d_o_1_1_vld_in) and (ap_const_logic_0 = d_o_1_1_ack_out))) and not(((ap_const_logic_0 = d_o_1_1_vld_in) and (ap_const_logic_1 = d_o_1_1_ack_out)))))) then d_o_1_1_state <= ap_const_lv2_3; else d_o_1_1_state <= ap_const_lv2_2; end if; end if; end if; end process; d_o_2_1_sel_rd_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_2_1_sel_rd <= ap_const_logic_0; else if (((ap_const_logic_1 = d_o_2_1_ack_out) and (ap_const_logic_1 = d_o_2_1_vld_out))) then d_o_2_1_sel_rd <= not(d_o_2_1_sel_rd); end if; end if; end if; end process; d_o_2_1_sel_wr_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_2_1_sel_wr <= ap_const_logic_0; else if (((ap_const_logic_1 = d_o_2_1_vld_in) and (ap_const_logic_1 = d_o_2_1_ack_in))) then d_o_2_1_sel_wr <= not(d_o_2_1_sel_wr); end if; end if; end if; end process; d_o_2_1_state_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_2_1_state <= ap_const_lv2_0; else if ((((ap_const_logic_0 = d_o_2_1_vld_in) and (ap_const_logic_1 = d_o_2_1_ack_out) and (ap_const_lv2_3 = d_o_2_1_state)) or ((ap_const_logic_0 = d_o_2_1_vld_in) and (ap_const_lv2_2 = d_o_2_1_state)))) then d_o_2_1_state <= ap_const_lv2_2; elsif ((((ap_const_logic_1 = d_o_2_1_vld_in) and (ap_const_logic_0 = d_o_2_1_ack_out) and (ap_const_lv2_3 = d_o_2_1_state)) or ((ap_const_logic_0 = d_o_2_1_ack_out) and (ap_const_lv2_1 = d_o_2_1_state)))) then d_o_2_1_state <= ap_const_lv2_1; elsif ((((ap_const_logic_1 = d_o_2_1_vld_in) and (ap_const_lv2_2 = d_o_2_1_state)) or ((ap_const_logic_1 = d_o_2_1_ack_out) and (ap_const_lv2_1 = d_o_2_1_state)) or ((ap_const_lv2_3 = d_o_2_1_state) and not(((ap_const_logic_1 = d_o_2_1_vld_in) and (ap_const_logic_0 = d_o_2_1_ack_out))) and not(((ap_const_logic_0 = d_o_2_1_vld_in) and (ap_const_logic_1 = d_o_2_1_ack_out)))))) then d_o_2_1_state <= ap_const_lv2_3; else d_o_2_1_state <= ap_const_lv2_2; end if; end if; end if; end process; d_o_3_1_sel_rd_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_3_1_sel_rd <= ap_const_logic_0; else if (((ap_const_logic_1 = d_o_3_1_ack_out) and (ap_const_logic_1 = d_o_3_1_vld_out))) then d_o_3_1_sel_rd <= not(d_o_3_1_sel_rd); end if; end if; end if; end process; d_o_3_1_sel_wr_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_3_1_sel_wr <= ap_const_logic_0; else if (((ap_const_logic_1 = d_o_3_1_vld_in) and (ap_const_logic_1 = d_o_3_1_ack_in))) then d_o_3_1_sel_wr <= not(d_o_3_1_sel_wr); end if; end if; end if; end process; d_o_3_1_state_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_3_1_state <= ap_const_lv2_0; else if ((((ap_const_logic_0 = d_o_3_1_vld_in) and (ap_const_logic_1 = d_o_3_1_ack_out) and (ap_const_lv2_3 = d_o_3_1_state)) or ((ap_const_logic_0 = d_o_3_1_vld_in) and (ap_const_lv2_2 = d_o_3_1_state)))) then d_o_3_1_state <= ap_const_lv2_2; elsif ((((ap_const_logic_1 = d_o_3_1_vld_in) and (ap_const_logic_0 = d_o_3_1_ack_out) and (ap_const_lv2_3 = d_o_3_1_state)) or ((ap_const_logic_0 = d_o_3_1_ack_out) and (ap_const_lv2_1 = d_o_3_1_state)))) then d_o_3_1_state <= ap_const_lv2_1; elsif ((((ap_const_logic_1 = d_o_3_1_vld_in) and (ap_const_lv2_2 = d_o_3_1_state)) or ((ap_const_logic_1 = d_o_3_1_ack_out) and (ap_const_lv2_1 = d_o_3_1_state)) or ((ap_const_lv2_3 = d_o_3_1_state) and not(((ap_const_logic_1 = d_o_3_1_vld_in) and (ap_const_logic_0 = d_o_3_1_ack_out))) and not(((ap_const_logic_0 = d_o_3_1_vld_in) and (ap_const_logic_1 = d_o_3_1_ack_out)))))) then d_o_3_1_state <= ap_const_lv2_3; else d_o_3_1_state <= ap_const_lv2_2; end if; end if; end if; end process; d_o_4_1_sel_rd_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_4_1_sel_rd <= ap_const_logic_0; else if (((ap_const_logic_1 = d_o_4_1_ack_out) and (ap_const_logic_1 = d_o_4_1_vld_out))) then d_o_4_1_sel_rd <= not(d_o_4_1_sel_rd); end if; end if; end if; end process; d_o_4_1_sel_wr_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_4_1_sel_wr <= ap_const_logic_0; else if (((ap_const_logic_1 = d_o_4_1_vld_in) and (ap_const_logic_1 = d_o_4_1_ack_in))) then d_o_4_1_sel_wr <= not(d_o_4_1_sel_wr); end if; end if; end if; end process; d_o_4_1_state_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_4_1_state <= ap_const_lv2_0; else if ((((ap_const_logic_0 = d_o_4_1_vld_in) and (ap_const_logic_1 = d_o_4_1_ack_out) and (ap_const_lv2_3 = d_o_4_1_state)) or ((ap_const_logic_0 = d_o_4_1_vld_in) and (ap_const_lv2_2 = d_o_4_1_state)))) then d_o_4_1_state <= ap_const_lv2_2; elsif ((((ap_const_logic_1 = d_o_4_1_vld_in) and (ap_const_logic_0 = d_o_4_1_ack_out) and (ap_const_lv2_3 = d_o_4_1_state)) or ((ap_const_logic_0 = d_o_4_1_ack_out) and (ap_const_lv2_1 = d_o_4_1_state)))) then d_o_4_1_state <= ap_const_lv2_1; elsif ((((ap_const_logic_1 = d_o_4_1_vld_in) and (ap_const_lv2_2 = d_o_4_1_state)) or ((ap_const_logic_1 = d_o_4_1_ack_out) and (ap_const_lv2_1 = d_o_4_1_state)) or ((ap_const_lv2_3 = d_o_4_1_state) and not(((ap_const_logic_1 = d_o_4_1_vld_in) and (ap_const_logic_0 = d_o_4_1_ack_out))) and not(((ap_const_logic_0 = d_o_4_1_vld_in) and (ap_const_logic_1 = d_o_4_1_ack_out)))))) then d_o_4_1_state <= ap_const_lv2_3; else d_o_4_1_state <= ap_const_lv2_2; end if; end if; end if; end process; d_o_5_1_sel_rd_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_5_1_sel_rd <= ap_const_logic_0; else if (((ap_const_logic_1 = d_o_5_1_ack_out) and (ap_const_logic_1 = d_o_5_1_vld_out))) then d_o_5_1_sel_rd <= not(d_o_5_1_sel_rd); end if; end if; end if; end process; d_o_5_1_sel_wr_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_5_1_sel_wr <= ap_const_logic_0; else if (((ap_const_logic_1 = d_o_5_1_vld_in) and (ap_const_logic_1 = d_o_5_1_ack_in))) then d_o_5_1_sel_wr <= not(d_o_5_1_sel_wr); end if; end if; end if; end process; d_o_5_1_state_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_5_1_state <= ap_const_lv2_0; else if ((((ap_const_logic_0 = d_o_5_1_vld_in) and (ap_const_logic_1 = d_o_5_1_ack_out) and (ap_const_lv2_3 = d_o_5_1_state)) or ((ap_const_logic_0 = d_o_5_1_vld_in) and (ap_const_lv2_2 = d_o_5_1_state)))) then d_o_5_1_state <= ap_const_lv2_2; elsif ((((ap_const_logic_1 = d_o_5_1_vld_in) and (ap_const_logic_0 = d_o_5_1_ack_out) and (ap_const_lv2_3 = d_o_5_1_state)) or ((ap_const_logic_0 = d_o_5_1_ack_out) and (ap_const_lv2_1 = d_o_5_1_state)))) then d_o_5_1_state <= ap_const_lv2_1; elsif ((((ap_const_logic_1 = d_o_5_1_vld_in) and (ap_const_lv2_2 = d_o_5_1_state)) or ((ap_const_logic_1 = d_o_5_1_ack_out) and (ap_const_lv2_1 = d_o_5_1_state)) or ((ap_const_lv2_3 = d_o_5_1_state) and not(((ap_const_logic_1 = d_o_5_1_vld_in) and (ap_const_logic_0 = d_o_5_1_ack_out))) and not(((ap_const_logic_0 = d_o_5_1_vld_in) and (ap_const_logic_1 = d_o_5_1_ack_out)))))) then d_o_5_1_state <= ap_const_lv2_3; else d_o_5_1_state <= ap_const_lv2_2; end if; end if; end if; end process; d_o_6_1_sel_rd_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_6_1_sel_rd <= ap_const_logic_0; else if (((ap_const_logic_1 = d_o_6_1_ack_out) and (ap_const_logic_1 = d_o_6_1_vld_out))) then d_o_6_1_sel_rd <= not(d_o_6_1_sel_rd); end if; end if; end if; end process; d_o_6_1_sel_wr_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_6_1_sel_wr <= ap_const_logic_0; else if (((ap_const_logic_1 = d_o_6_1_vld_in) and (ap_const_logic_1 = d_o_6_1_ack_in))) then d_o_6_1_sel_wr <= not(d_o_6_1_sel_wr); end if; end if; end if; end process; d_o_6_1_state_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_6_1_state <= ap_const_lv2_0; else if ((((ap_const_logic_0 = d_o_6_1_vld_in) and (ap_const_logic_1 = d_o_6_1_ack_out) and (ap_const_lv2_3 = d_o_6_1_state)) or ((ap_const_logic_0 = d_o_6_1_vld_in) and (ap_const_lv2_2 = d_o_6_1_state)))) then d_o_6_1_state <= ap_const_lv2_2; elsif ((((ap_const_logic_1 = d_o_6_1_vld_in) and (ap_const_logic_0 = d_o_6_1_ack_out) and (ap_const_lv2_3 = d_o_6_1_state)) or ((ap_const_logic_0 = d_o_6_1_ack_out) and (ap_const_lv2_1 = d_o_6_1_state)))) then d_o_6_1_state <= ap_const_lv2_1; elsif ((((ap_const_logic_1 = d_o_6_1_vld_in) and (ap_const_lv2_2 = d_o_6_1_state)) or ((ap_const_logic_1 = d_o_6_1_ack_out) and (ap_const_lv2_1 = d_o_6_1_state)) or ((ap_const_lv2_3 = d_o_6_1_state) and not(((ap_const_logic_1 = d_o_6_1_vld_in) and (ap_const_logic_0 = d_o_6_1_ack_out))) and not(((ap_const_logic_0 = d_o_6_1_vld_in) and (ap_const_logic_1 = d_o_6_1_ack_out)))))) then d_o_6_1_state <= ap_const_lv2_3; else d_o_6_1_state <= ap_const_lv2_2; end if; end if; end if; end process; d_o_7_1_sel_rd_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_7_1_sel_rd <= ap_const_logic_0; else if (((ap_const_logic_1 = d_o_7_1_ack_out) and (ap_const_logic_1 = d_o_7_1_vld_out))) then d_o_7_1_sel_rd <= not(d_o_7_1_sel_rd); end if; end if; end if; end process; d_o_7_1_sel_wr_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_7_1_sel_wr <= ap_const_logic_0; else if (((ap_const_logic_1 = d_o_7_1_vld_in) and (ap_const_logic_1 = d_o_7_1_ack_in))) then d_o_7_1_sel_wr <= not(d_o_7_1_sel_wr); end if; end if; end if; end process; d_o_7_1_state_assign_proc : process(ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (ap_rst_n_inv = '1') then d_o_7_1_state <= ap_const_lv2_0; else if ((((ap_const_logic_0 = d_o_7_1_vld_in) and (ap_const_logic_1 = d_o_7_1_ack_out) and (ap_const_lv2_3 = d_o_7_1_state)) or ((ap_const_logic_0 = d_o_7_1_vld_in) and (ap_const_lv2_2 = d_o_7_1_state)))) then d_o_7_1_state <= ap_const_lv2_2; elsif ((((ap_const_logic_1 = d_o_7_1_vld_in) and (ap_const_logic_0 = d_o_7_1_ack_out) and (ap_const_lv2_3 = d_o_7_1_state)) or ((ap_const_logic_0 = d_o_7_1_ack_out) and (ap_const_lv2_1 = d_o_7_1_state)))) then d_o_7_1_state <= ap_const_lv2_1; elsif ((((ap_const_logic_1 = d_o_7_1_vld_in) and (ap_const_lv2_2 = d_o_7_1_state)) or ((ap_const_logic_1 = d_o_7_1_ack_out) and (ap_const_lv2_1 = d_o_7_1_state)) or ((ap_const_lv2_3 = d_o_7_1_state) and not(((ap_const_logic_1 = d_o_7_1_vld_in) and (ap_const_logic_0 = d_o_7_1_ack_out))) and not(((ap_const_logic_0 = d_o_7_1_vld_in) and (ap_const_logic_1 = d_o_7_1_ack_out)))))) then d_o_7_1_state <= ap_const_lv2_3; else d_o_7_1_state <= ap_const_lv2_2; end if; end if; end if; end process; i1_reg_218_assign_proc : process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_0 = exitcond_reg_507))) then i1_reg_218 <= tmp_17_reg_502; elsif ((((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_1 = exitcond_reg_507)))) then i1_reg_218 <= ap_const_lv5_0; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then acc_0 <= tmp_1_fu_266_p2; acc_1 <= tmp_1_1_fu_297_p2; acc_2 <= tmp_1_2_fu_328_p2; acc_3 <= tmp_1_3_fu_359_p2; acc_4 <= tmp_1_4_fu_390_p2; acc_5 <= tmp_1_5_fu_421_p2; acc_6 <= tmp_1_6_fu_452_p2; acc_7 <= tmp_1_7_fu_483_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then ap_reg_pp0_iter1_exitcond_reg_507 <= exitcond_reg_507; exitcond_reg_507 <= exitcond_fu_246_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_i_0_0_load_A)) then d_i_0_0_payload_A <= d_i_0_TDATA; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_i_0_0_load_B)) then d_i_0_0_payload_B <= d_i_0_TDATA; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_i_1_0_load_A)) then d_i_1_0_payload_A <= d_i_1_TDATA; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_i_1_0_load_B)) then d_i_1_0_payload_B <= d_i_1_TDATA; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_i_2_0_load_A)) then d_i_2_0_payload_A <= d_i_2_TDATA; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_i_2_0_load_B)) then d_i_2_0_payload_B <= d_i_2_TDATA; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_i_3_0_load_A)) then d_i_3_0_payload_A <= d_i_3_TDATA; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_i_3_0_load_B)) then d_i_3_0_payload_B <= d_i_3_TDATA; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_i_4_0_load_A)) then d_i_4_0_payload_A <= d_i_4_TDATA; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_i_4_0_load_B)) then d_i_4_0_payload_B <= d_i_4_TDATA; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_i_5_0_load_A)) then d_i_5_0_payload_A <= d_i_5_TDATA; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_i_5_0_load_B)) then d_i_5_0_payload_B <= d_i_5_TDATA; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_i_6_0_load_A)) then d_i_6_0_payload_A <= d_i_6_TDATA; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_i_6_0_load_B)) then d_i_6_0_payload_B <= d_i_6_TDATA; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_i_7_0_load_A)) then d_i_7_0_payload_A <= d_i_7_TDATA; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_i_7_0_load_B)) then d_i_7_0_payload_B <= d_i_7_TDATA; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_o_0_1_load_A)) then d_o_0_1_payload_A <= tmp_8_fu_278_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_o_0_1_load_B)) then d_o_0_1_payload_B <= tmp_8_fu_278_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_o_1_1_load_A)) then d_o_1_1_payload_A <= tmp_2_1_fu_309_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_o_1_1_load_B)) then d_o_1_1_payload_B <= tmp_2_1_fu_309_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_o_2_1_load_A)) then d_o_2_1_payload_A <= tmp_2_2_fu_340_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_o_2_1_load_B)) then d_o_2_1_payload_B <= tmp_2_2_fu_340_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_o_3_1_load_A)) then d_o_3_1_payload_A <= tmp_2_3_fu_371_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_o_3_1_load_B)) then d_o_3_1_payload_B <= tmp_2_3_fu_371_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_o_4_1_load_A)) then d_o_4_1_payload_A <= tmp_2_4_fu_402_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_o_4_1_load_B)) then d_o_4_1_payload_B <= tmp_2_4_fu_402_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_o_5_1_load_A)) then d_o_5_1_payload_A <= tmp_2_5_fu_433_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_o_5_1_load_B)) then d_o_5_1_payload_B <= tmp_2_5_fu_433_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_o_6_1_load_A)) then d_o_6_1_payload_A <= tmp_2_6_fu_464_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_o_6_1_load_B)) then d_o_6_1_payload_B <= tmp_2_6_fu_464_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_o_7_1_load_A)) then d_o_7_1_payload_A <= tmp_2_7_fu_495_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if ((ap_const_logic_1 = d_o_7_1_load_B)) then d_o_7_1_payload_B <= tmp_2_7_fu_495_p2; end if; end if; end process; process (ap_clk) begin if (ap_clk'event and ap_clk = '1') then if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then tmp_17_reg_502 <= tmp_17_fu_242_p1; end if; end if; end process; ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, ap_block_pp0_stage0_flag00011011, ap_reset_idle_pp0) begin case ap_CS_fsm is when ap_ST_fsm_state1 => if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then ap_NS_fsm <= ap_ST_fsm_pp0_stage0; else ap_NS_fsm <= ap_ST_fsm_state1; end if; when ap_ST_fsm_pp0_stage0 => if ((ap_reset_idle_pp0 = ap_const_logic_0)) then ap_NS_fsm <= ap_ST_fsm_pp0_stage0; elsif (((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_reset_idle_pp0))) then ap_NS_fsm <= ap_ST_fsm_state1; else ap_NS_fsm <= ap_ST_fsm_pp0_stage0; end if; when others => ap_NS_fsm <= "XX"; end case; end process; ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(1); ap_CS_fsm_state1 <= ap_CS_fsm(0); ap_block_pp0_stage0_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_pp0_stage0_flag00001001_assign_proc : process(d_i_0_0_vld_out, d_i_1_0_vld_out, d_i_2_0_vld_out, d_i_3_0_vld_out, d_i_4_0_vld_out, d_i_5_0_vld_out, d_i_6_0_vld_out, d_i_7_0_vld_out, d_o_0_1_ack_in, d_o_1_1_ack_in, d_o_2_1_ack_in, d_o_3_1_ack_in, d_o_4_1_ack_in, d_o_5_1_ack_in, d_o_6_1_ack_in, d_o_7_1_ack_in, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2) begin ap_block_pp0_stage0_flag00001001 <= ((((ap_const_logic_0 = d_i_0_0_vld_out) or (ap_const_logic_0 = d_i_1_0_vld_out) or (ap_const_logic_0 = d_i_2_0_vld_out) or (ap_const_logic_0 = d_i_3_0_vld_out) or (ap_const_logic_0 = d_i_4_0_vld_out) or (ap_const_logic_0 = d_i_5_0_vld_out) or (ap_const_logic_0 = d_i_6_0_vld_out) or (ap_const_logic_0 = d_i_7_0_vld_out)) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or (((ap_const_logic_0 = d_o_0_1_ack_in) or (ap_const_logic_0 = d_o_1_1_ack_in) or (ap_const_logic_0 = d_o_2_1_ack_in) or (ap_const_logic_0 = d_o_3_1_ack_in) or (ap_const_logic_0 = d_o_4_1_ack_in) or (ap_const_logic_0 = d_o_5_1_ack_in) or (ap_const_logic_0 = d_o_6_1_ack_in) or (ap_const_logic_0 = d_o_7_1_ack_in)) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))); end process; ap_block_pp0_stage0_flag00011001_assign_proc : process(d_i_0_0_vld_out, d_i_1_0_vld_out, d_i_2_0_vld_out, d_i_3_0_vld_out, d_i_4_0_vld_out, d_i_5_0_vld_out, d_i_6_0_vld_out, d_i_7_0_vld_out, d_o_0_1_ack_in, d_o_1_1_ack_in, d_o_2_1_ack_in, d_o_3_1_ack_in, d_o_4_1_ack_in, d_o_5_1_ack_in, d_o_6_1_ack_in, d_o_7_1_ack_in, ap_block_state4_io, ap_enable_reg_pp0_iter1, ap_block_state3_io, ap_enable_reg_pp0_iter2) begin ap_block_pp0_stage0_flag00011001 <= ((((ap_const_logic_0 = d_i_0_0_vld_out) or (ap_const_logic_0 = d_i_1_0_vld_out) or (ap_const_logic_0 = d_i_2_0_vld_out) or (ap_const_logic_0 = d_i_3_0_vld_out) or (ap_const_logic_0 = d_i_4_0_vld_out) or (ap_const_logic_0 = d_i_5_0_vld_out) or (ap_const_logic_0 = d_i_6_0_vld_out) or (ap_const_logic_0 = d_i_7_0_vld_out) or (ap_const_boolean_1 = ap_block_state4_io)) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or (((ap_const_logic_0 = d_o_0_1_ack_in) or (ap_const_logic_0 = d_o_1_1_ack_in) or (ap_const_logic_0 = d_o_2_1_ack_in) or (ap_const_logic_0 = d_o_3_1_ack_in) or (ap_const_logic_0 = d_o_4_1_ack_in) or (ap_const_logic_0 = d_o_5_1_ack_in) or (ap_const_logic_0 = d_o_6_1_ack_in) or (ap_const_logic_0 = d_o_7_1_ack_in) or (ap_const_boolean_1 = ap_block_state3_io)) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))); end process; ap_block_pp0_stage0_flag00011011_assign_proc : process(d_i_0_0_vld_out, d_i_1_0_vld_out, d_i_2_0_vld_out, d_i_3_0_vld_out, d_i_4_0_vld_out, d_i_5_0_vld_out, d_i_6_0_vld_out, d_i_7_0_vld_out, d_o_0_1_ack_in, d_o_1_1_ack_in, d_o_2_1_ack_in, d_o_3_1_ack_in, d_o_4_1_ack_in, d_o_5_1_ack_in, d_o_6_1_ack_in, d_o_7_1_ack_in, ap_block_state4_io, ap_enable_reg_pp0_iter1, ap_block_state3_io, ap_enable_reg_pp0_iter2) begin ap_block_pp0_stage0_flag00011011 <= ((((ap_const_logic_0 = d_i_0_0_vld_out) or (ap_const_logic_0 = d_i_1_0_vld_out) or (ap_const_logic_0 = d_i_2_0_vld_out) or (ap_const_logic_0 = d_i_3_0_vld_out) or (ap_const_logic_0 = d_i_4_0_vld_out) or (ap_const_logic_0 = d_i_5_0_vld_out) or (ap_const_logic_0 = d_i_6_0_vld_out) or (ap_const_logic_0 = d_i_7_0_vld_out) or (ap_const_boolean_1 = ap_block_state4_io)) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or (((ap_const_logic_0 = d_o_0_1_ack_in) or (ap_const_logic_0 = d_o_1_1_ack_in) or (ap_const_logic_0 = d_o_2_1_ack_in) or (ap_const_logic_0 = d_o_3_1_ack_in) or (ap_const_logic_0 = d_o_4_1_ack_in) or (ap_const_logic_0 = d_o_5_1_ack_in) or (ap_const_logic_0 = d_o_6_1_ack_in) or (ap_const_logic_0 = d_o_7_1_ack_in) or (ap_const_boolean_1 = ap_block_state3_io)) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))); end process; ap_block_state2_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1)); ap_block_state3_io_assign_proc : process(d_o_0_1_ack_in, d_o_1_1_ack_in, d_o_2_1_ack_in, d_o_3_1_ack_in, d_o_4_1_ack_in, d_o_5_1_ack_in, d_o_6_1_ack_in, d_o_7_1_ack_in) begin ap_block_state3_io <= ((ap_const_logic_0 = d_o_0_1_ack_in) or (ap_const_logic_0 = d_o_1_1_ack_in) or (ap_const_logic_0 = d_o_2_1_ack_in) or (ap_const_logic_0 = d_o_3_1_ack_in) or (ap_const_logic_0 = d_o_4_1_ack_in) or (ap_const_logic_0 = d_o_5_1_ack_in) or (ap_const_logic_0 = d_o_6_1_ack_in) or (ap_const_logic_0 = d_o_7_1_ack_in)); end process; ap_block_state3_pp0_stage0_iter2_assign_proc : process(d_o_0_1_ack_in, d_o_1_1_ack_in, d_o_2_1_ack_in, d_o_3_1_ack_in, d_o_4_1_ack_in, d_o_5_1_ack_in, d_o_6_1_ack_in, d_o_7_1_ack_in) begin ap_block_state3_pp0_stage0_iter2 <= ((ap_const_logic_0 = d_o_0_1_ack_in) or (ap_const_logic_0 = d_o_1_1_ack_in) or (ap_const_logic_0 = d_o_2_1_ack_in) or (ap_const_logic_0 = d_o_3_1_ack_in) or (ap_const_logic_0 = d_o_4_1_ack_in) or (ap_const_logic_0 = d_o_5_1_ack_in) or (ap_const_logic_0 = d_o_6_1_ack_in) or (ap_const_logic_0 = d_o_7_1_ack_in)); end process; ap_block_state4_io_assign_proc : process(d_o_0_1_ack_in, d_o_1_1_ack_in, d_o_2_1_ack_in, d_o_3_1_ack_in, d_o_4_1_ack_in, d_o_5_1_ack_in, d_o_6_1_ack_in, d_o_7_1_ack_in) begin ap_block_state4_io <= ((ap_const_logic_0 = d_o_0_1_ack_in) or (ap_const_logic_0 = d_o_1_1_ack_in) or (ap_const_logic_0 = d_o_2_1_ack_in) or (ap_const_logic_0 = d_o_3_1_ack_in) or (ap_const_logic_0 = d_o_4_1_ack_in) or (ap_const_logic_0 = d_o_5_1_ack_in) or (ap_const_logic_0 = d_o_6_1_ack_in) or (ap_const_logic_0 = d_o_7_1_ack_in)); end process; ap_block_state4_pp0_stage0_iter1_assign_proc : process(d_i_0_0_vld_out, d_i_1_0_vld_out, d_i_2_0_vld_out, d_i_3_0_vld_out, d_i_4_0_vld_out, d_i_5_0_vld_out, d_i_6_0_vld_out, d_i_7_0_vld_out) begin ap_block_state4_pp0_stage0_iter1 <= ((ap_const_logic_0 = d_i_0_0_vld_out) or (ap_const_logic_0 = d_i_1_0_vld_out) or (ap_const_logic_0 = d_i_2_0_vld_out) or (ap_const_logic_0 = d_i_3_0_vld_out) or (ap_const_logic_0 = d_i_4_0_vld_out) or (ap_const_logic_0 = d_i_5_0_vld_out) or (ap_const_logic_0 = d_i_6_0_vld_out) or (ap_const_logic_0 = d_i_7_0_vld_out)); end process; ap_condition_1051_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00000000) begin ap_condition_1051 <= ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)); end process; ap_done_assign_proc : process(ap_enable_reg_pp0_iter2, ap_block_pp0_stage0_flag00011001, ap_reg_pp0_iter1_exitcond_reg_507) begin if (((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_lv1_1 = ap_reg_pp0_iter1_exitcond_reg_507))) then ap_done <= ap_const_logic_1; else ap_done <= ap_const_logic_0; end if; end process; ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1); ap_enable_reg_pp0_iter0 <= ap_start; ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1) begin if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then ap_idle <= ap_const_logic_1; else ap_idle <= ap_const_logic_0; end if; end process; ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2) begin if (((ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter1) and (ap_const_logic_0 = ap_enable_reg_pp0_iter2))) then ap_idle_pp0 <= ap_const_logic_1; else ap_idle_pp0 <= ap_const_logic_0; end if; end process; ap_idle_pp0_0to1_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1) begin if (((ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter1))) then ap_idle_pp0_0to1 <= ap_const_logic_1; else ap_idle_pp0_0to1 <= ap_const_logic_0; end if; end process; ap_ready_assign_proc : process(exitcond_fu_246_p2, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_block_pp0_stage0_flag00011001) begin if (((exitcond_fu_246_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then ap_ready <= ap_const_logic_1; else ap_ready <= ap_const_logic_0; end if; end process; ap_reset_idle_pp0_assign_proc : process(ap_start, ap_idle_pp0_0to1) begin if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_idle_pp0_0to1))) then ap_reset_idle_pp0 <= ap_const_logic_1; else ap_reset_idle_pp0 <= ap_const_logic_0; end if; end process; ap_rst_n_inv_assign_proc : process(ap_rst_n) begin ap_rst_n_inv <= not(ap_rst_n); end process; d_i_0_0_ack_in <= d_i_0_0_state(1); d_i_0_0_ack_out_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then d_i_0_0_ack_out <= ap_const_logic_1; else d_i_0_0_ack_out <= ap_const_logic_0; end if; end process; d_i_0_0_data_out_assign_proc : process(d_i_0_0_payload_A, d_i_0_0_payload_B, d_i_0_0_sel) begin if ((ap_const_logic_1 = d_i_0_0_sel)) then d_i_0_0_data_out <= d_i_0_0_payload_B; else d_i_0_0_data_out <= d_i_0_0_payload_A; end if; end process; d_i_0_0_load_A <= (d_i_0_0_state_cmp_full and not(d_i_0_0_sel_wr)); d_i_0_0_load_B <= (d_i_0_0_sel_wr and d_i_0_0_state_cmp_full); d_i_0_0_sel <= d_i_0_0_sel_rd; d_i_0_0_state_cmp_full <= '0' when (d_i_0_0_state = ap_const_lv2_1) else '1'; d_i_0_0_vld_in <= d_i_0_TVALID; d_i_0_0_vld_out <= d_i_0_0_state(0); d_i_0_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, d_i_0_0_state, ap_block_pp0_stage0_flag00000000) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then d_i_0_TDATA_blk_n <= d_i_0_0_state(0); else d_i_0_TDATA_blk_n <= ap_const_logic_1; end if; end process; d_i_0_TREADY <= d_i_0_0_state(1); d_i_1_0_ack_in <= d_i_1_0_state(1); d_i_1_0_ack_out_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then d_i_1_0_ack_out <= ap_const_logic_1; else d_i_1_0_ack_out <= ap_const_logic_0; end if; end process; d_i_1_0_data_out_assign_proc : process(d_i_1_0_payload_A, d_i_1_0_payload_B, d_i_1_0_sel) begin if ((ap_const_logic_1 = d_i_1_0_sel)) then d_i_1_0_data_out <= d_i_1_0_payload_B; else d_i_1_0_data_out <= d_i_1_0_payload_A; end if; end process; d_i_1_0_load_A <= (d_i_1_0_state_cmp_full and not(d_i_1_0_sel_wr)); d_i_1_0_load_B <= (d_i_1_0_sel_wr and d_i_1_0_state_cmp_full); d_i_1_0_sel <= d_i_1_0_sel_rd; d_i_1_0_state_cmp_full <= '0' when (d_i_1_0_state = ap_const_lv2_1) else '1'; d_i_1_0_vld_in <= d_i_1_TVALID; d_i_1_0_vld_out <= d_i_1_0_state(0); d_i_1_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, d_i_1_0_state, ap_block_pp0_stage0_flag00000000) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then d_i_1_TDATA_blk_n <= d_i_1_0_state(0); else d_i_1_TDATA_blk_n <= ap_const_logic_1; end if; end process; d_i_1_TREADY <= d_i_1_0_state(1); d_i_2_0_ack_in <= d_i_2_0_state(1); d_i_2_0_ack_out_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then d_i_2_0_ack_out <= ap_const_logic_1; else d_i_2_0_ack_out <= ap_const_logic_0; end if; end process; d_i_2_0_data_out_assign_proc : process(d_i_2_0_payload_A, d_i_2_0_payload_B, d_i_2_0_sel) begin if ((ap_const_logic_1 = d_i_2_0_sel)) then d_i_2_0_data_out <= d_i_2_0_payload_B; else d_i_2_0_data_out <= d_i_2_0_payload_A; end if; end process; d_i_2_0_load_A <= (d_i_2_0_state_cmp_full and not(d_i_2_0_sel_wr)); d_i_2_0_load_B <= (d_i_2_0_sel_wr and d_i_2_0_state_cmp_full); d_i_2_0_sel <= d_i_2_0_sel_rd; d_i_2_0_state_cmp_full <= '0' when (d_i_2_0_state = ap_const_lv2_1) else '1'; d_i_2_0_vld_in <= d_i_2_TVALID; d_i_2_0_vld_out <= d_i_2_0_state(0); d_i_2_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, d_i_2_0_state, ap_block_pp0_stage0_flag00000000) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then d_i_2_TDATA_blk_n <= d_i_2_0_state(0); else d_i_2_TDATA_blk_n <= ap_const_logic_1; end if; end process; d_i_2_TREADY <= d_i_2_0_state(1); d_i_3_0_ack_in <= d_i_3_0_state(1); d_i_3_0_ack_out_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then d_i_3_0_ack_out <= ap_const_logic_1; else d_i_3_0_ack_out <= ap_const_logic_0; end if; end process; d_i_3_0_data_out_assign_proc : process(d_i_3_0_payload_A, d_i_3_0_payload_B, d_i_3_0_sel) begin if ((ap_const_logic_1 = d_i_3_0_sel)) then d_i_3_0_data_out <= d_i_3_0_payload_B; else d_i_3_0_data_out <= d_i_3_0_payload_A; end if; end process; d_i_3_0_load_A <= (d_i_3_0_state_cmp_full and not(d_i_3_0_sel_wr)); d_i_3_0_load_B <= (d_i_3_0_sel_wr and d_i_3_0_state_cmp_full); d_i_3_0_sel <= d_i_3_0_sel_rd; d_i_3_0_state_cmp_full <= '0' when (d_i_3_0_state = ap_const_lv2_1) else '1'; d_i_3_0_vld_in <= d_i_3_TVALID; d_i_3_0_vld_out <= d_i_3_0_state(0); d_i_3_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, d_i_3_0_state, ap_block_pp0_stage0_flag00000000) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then d_i_3_TDATA_blk_n <= d_i_3_0_state(0); else d_i_3_TDATA_blk_n <= ap_const_logic_1; end if; end process; d_i_3_TREADY <= d_i_3_0_state(1); d_i_4_0_ack_in <= d_i_4_0_state(1); d_i_4_0_ack_out_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then d_i_4_0_ack_out <= ap_const_logic_1; else d_i_4_0_ack_out <= ap_const_logic_0; end if; end process; d_i_4_0_data_out_assign_proc : process(d_i_4_0_payload_A, d_i_4_0_payload_B, d_i_4_0_sel) begin if ((ap_const_logic_1 = d_i_4_0_sel)) then d_i_4_0_data_out <= d_i_4_0_payload_B; else d_i_4_0_data_out <= d_i_4_0_payload_A; end if; end process; d_i_4_0_load_A <= (d_i_4_0_state_cmp_full and not(d_i_4_0_sel_wr)); d_i_4_0_load_B <= (d_i_4_0_sel_wr and d_i_4_0_state_cmp_full); d_i_4_0_sel <= d_i_4_0_sel_rd; d_i_4_0_state_cmp_full <= '0' when (d_i_4_0_state = ap_const_lv2_1) else '1'; d_i_4_0_vld_in <= d_i_4_TVALID; d_i_4_0_vld_out <= d_i_4_0_state(0); d_i_4_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, d_i_4_0_state, ap_block_pp0_stage0_flag00000000) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then d_i_4_TDATA_blk_n <= d_i_4_0_state(0); else d_i_4_TDATA_blk_n <= ap_const_logic_1; end if; end process; d_i_4_TREADY <= d_i_4_0_state(1); d_i_5_0_ack_in <= d_i_5_0_state(1); d_i_5_0_ack_out_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then d_i_5_0_ack_out <= ap_const_logic_1; else d_i_5_0_ack_out <= ap_const_logic_0; end if; end process; d_i_5_0_data_out_assign_proc : process(d_i_5_0_payload_A, d_i_5_0_payload_B, d_i_5_0_sel) begin if ((ap_const_logic_1 = d_i_5_0_sel)) then d_i_5_0_data_out <= d_i_5_0_payload_B; else d_i_5_0_data_out <= d_i_5_0_payload_A; end if; end process; d_i_5_0_load_A <= (d_i_5_0_state_cmp_full and not(d_i_5_0_sel_wr)); d_i_5_0_load_B <= (d_i_5_0_sel_wr and d_i_5_0_state_cmp_full); d_i_5_0_sel <= d_i_5_0_sel_rd; d_i_5_0_state_cmp_full <= '0' when (d_i_5_0_state = ap_const_lv2_1) else '1'; d_i_5_0_vld_in <= d_i_5_TVALID; d_i_5_0_vld_out <= d_i_5_0_state(0); d_i_5_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, d_i_5_0_state, ap_block_pp0_stage0_flag00000000) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then d_i_5_TDATA_blk_n <= d_i_5_0_state(0); else d_i_5_TDATA_blk_n <= ap_const_logic_1; end if; end process; d_i_5_TREADY <= d_i_5_0_state(1); d_i_6_0_ack_in <= d_i_6_0_state(1); d_i_6_0_ack_out_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then d_i_6_0_ack_out <= ap_const_logic_1; else d_i_6_0_ack_out <= ap_const_logic_0; end if; end process; d_i_6_0_data_out_assign_proc : process(d_i_6_0_payload_A, d_i_6_0_payload_B, d_i_6_0_sel) begin if ((ap_const_logic_1 = d_i_6_0_sel)) then d_i_6_0_data_out <= d_i_6_0_payload_B; else d_i_6_0_data_out <= d_i_6_0_payload_A; end if; end process; d_i_6_0_load_A <= (d_i_6_0_state_cmp_full and not(d_i_6_0_sel_wr)); d_i_6_0_load_B <= (d_i_6_0_sel_wr and d_i_6_0_state_cmp_full); d_i_6_0_sel <= d_i_6_0_sel_rd; d_i_6_0_state_cmp_full <= '0' when (d_i_6_0_state = ap_const_lv2_1) else '1'; d_i_6_0_vld_in <= d_i_6_TVALID; d_i_6_0_vld_out <= d_i_6_0_state(0); d_i_6_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, d_i_6_0_state, ap_block_pp0_stage0_flag00000000) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then d_i_6_TDATA_blk_n <= d_i_6_0_state(0); else d_i_6_TDATA_blk_n <= ap_const_logic_1; end if; end process; d_i_6_TREADY <= d_i_6_0_state(1); d_i_7_0_ack_in <= d_i_7_0_state(1); d_i_7_0_ack_out_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then d_i_7_0_ack_out <= ap_const_logic_1; else d_i_7_0_ack_out <= ap_const_logic_0; end if; end process; d_i_7_0_data_out_assign_proc : process(d_i_7_0_payload_A, d_i_7_0_payload_B, d_i_7_0_sel) begin if ((ap_const_logic_1 = d_i_7_0_sel)) then d_i_7_0_data_out <= d_i_7_0_payload_B; else d_i_7_0_data_out <= d_i_7_0_payload_A; end if; end process; d_i_7_0_load_A <= (d_i_7_0_state_cmp_full and not(d_i_7_0_sel_wr)); d_i_7_0_load_B <= (d_i_7_0_sel_wr and d_i_7_0_state_cmp_full); d_i_7_0_sel <= d_i_7_0_sel_rd; d_i_7_0_state_cmp_full <= '0' when (d_i_7_0_state = ap_const_lv2_1) else '1'; d_i_7_0_vld_in <= d_i_7_TVALID; d_i_7_0_vld_out <= d_i_7_0_state(0); d_i_7_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, d_i_7_0_state, ap_block_pp0_stage0_flag00000000) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then d_i_7_TDATA_blk_n <= d_i_7_0_state(0); else d_i_7_TDATA_blk_n <= ap_const_logic_1; end if; end process; d_i_7_TREADY <= d_i_7_0_state(1); d_o_0_1_ack_in <= d_o_0_1_state(1); d_o_0_1_ack_out <= d_o_0_TREADY; d_o_0_1_data_out_assign_proc : process(d_o_0_1_payload_A, d_o_0_1_payload_B, d_o_0_1_sel) begin if ((ap_const_logic_1 = d_o_0_1_sel)) then d_o_0_1_data_out <= d_o_0_1_payload_B; else d_o_0_1_data_out <= d_o_0_1_payload_A; end if; end process; d_o_0_1_load_A <= (d_o_0_1_state_cmp_full and not(d_o_0_1_sel_wr)); d_o_0_1_load_B <= (d_o_0_1_sel_wr and d_o_0_1_state_cmp_full); d_o_0_1_sel <= d_o_0_1_sel_rd; d_o_0_1_state_cmp_full <= '0' when (d_o_0_1_state = ap_const_lv2_1) else '1'; d_o_0_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then d_o_0_1_vld_in <= ap_const_logic_1; else d_o_0_1_vld_in <= ap_const_logic_0; end if; end process; d_o_0_1_vld_out <= d_o_0_1_state(0); d_o_0_TDATA <= d_o_0_1_data_out; d_o_0_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, d_o_0_1_state, ap_block_pp0_stage0_flag00000000) begin if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)))) then d_o_0_TDATA_blk_n <= d_o_0_1_state(1); else d_o_0_TDATA_blk_n <= ap_const_logic_1; end if; end process; d_o_0_TVALID <= d_o_0_1_state(0); d_o_1_1_ack_in <= d_o_1_1_state(1); d_o_1_1_ack_out <= d_o_1_TREADY; d_o_1_1_data_out_assign_proc : process(d_o_1_1_payload_A, d_o_1_1_payload_B, d_o_1_1_sel) begin if ((ap_const_logic_1 = d_o_1_1_sel)) then d_o_1_1_data_out <= d_o_1_1_payload_B; else d_o_1_1_data_out <= d_o_1_1_payload_A; end if; end process; d_o_1_1_load_A <= (d_o_1_1_state_cmp_full and not(d_o_1_1_sel_wr)); d_o_1_1_load_B <= (d_o_1_1_sel_wr and d_o_1_1_state_cmp_full); d_o_1_1_sel <= d_o_1_1_sel_rd; d_o_1_1_state_cmp_full <= '0' when (d_o_1_1_state = ap_const_lv2_1) else '1'; d_o_1_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then d_o_1_1_vld_in <= ap_const_logic_1; else d_o_1_1_vld_in <= ap_const_logic_0; end if; end process; d_o_1_1_vld_out <= d_o_1_1_state(0); d_o_1_TDATA <= d_o_1_1_data_out; d_o_1_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, d_o_1_1_state, ap_block_pp0_stage0_flag00000000) begin if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)))) then d_o_1_TDATA_blk_n <= d_o_1_1_state(1); else d_o_1_TDATA_blk_n <= ap_const_logic_1; end if; end process; d_o_1_TVALID <= d_o_1_1_state(0); d_o_2_1_ack_in <= d_o_2_1_state(1); d_o_2_1_ack_out <= d_o_2_TREADY; d_o_2_1_data_out_assign_proc : process(d_o_2_1_payload_A, d_o_2_1_payload_B, d_o_2_1_sel) begin if ((ap_const_logic_1 = d_o_2_1_sel)) then d_o_2_1_data_out <= d_o_2_1_payload_B; else d_o_2_1_data_out <= d_o_2_1_payload_A; end if; end process; d_o_2_1_load_A <= (d_o_2_1_state_cmp_full and not(d_o_2_1_sel_wr)); d_o_2_1_load_B <= (d_o_2_1_sel_wr and d_o_2_1_state_cmp_full); d_o_2_1_sel <= d_o_2_1_sel_rd; d_o_2_1_state_cmp_full <= '0' when (d_o_2_1_state = ap_const_lv2_1) else '1'; d_o_2_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then d_o_2_1_vld_in <= ap_const_logic_1; else d_o_2_1_vld_in <= ap_const_logic_0; end if; end process; d_o_2_1_vld_out <= d_o_2_1_state(0); d_o_2_TDATA <= d_o_2_1_data_out; d_o_2_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, d_o_2_1_state, ap_block_pp0_stage0_flag00000000) begin if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)))) then d_o_2_TDATA_blk_n <= d_o_2_1_state(1); else d_o_2_TDATA_blk_n <= ap_const_logic_1; end if; end process; d_o_2_TVALID <= d_o_2_1_state(0); d_o_3_1_ack_in <= d_o_3_1_state(1); d_o_3_1_ack_out <= d_o_3_TREADY; d_o_3_1_data_out_assign_proc : process(d_o_3_1_payload_A, d_o_3_1_payload_B, d_o_3_1_sel) begin if ((ap_const_logic_1 = d_o_3_1_sel)) then d_o_3_1_data_out <= d_o_3_1_payload_B; else d_o_3_1_data_out <= d_o_3_1_payload_A; end if; end process; d_o_3_1_load_A <= (d_o_3_1_state_cmp_full and not(d_o_3_1_sel_wr)); d_o_3_1_load_B <= (d_o_3_1_sel_wr and d_o_3_1_state_cmp_full); d_o_3_1_sel <= d_o_3_1_sel_rd; d_o_3_1_state_cmp_full <= '0' when (d_o_3_1_state = ap_const_lv2_1) else '1'; d_o_3_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then d_o_3_1_vld_in <= ap_const_logic_1; else d_o_3_1_vld_in <= ap_const_logic_0; end if; end process; d_o_3_1_vld_out <= d_o_3_1_state(0); d_o_3_TDATA <= d_o_3_1_data_out; d_o_3_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, d_o_3_1_state, ap_block_pp0_stage0_flag00000000) begin if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)))) then d_o_3_TDATA_blk_n <= d_o_3_1_state(1); else d_o_3_TDATA_blk_n <= ap_const_logic_1; end if; end process; d_o_3_TVALID <= d_o_3_1_state(0); d_o_4_1_ack_in <= d_o_4_1_state(1); d_o_4_1_ack_out <= d_o_4_TREADY; d_o_4_1_data_out_assign_proc : process(d_o_4_1_payload_A, d_o_4_1_payload_B, d_o_4_1_sel) begin if ((ap_const_logic_1 = d_o_4_1_sel)) then d_o_4_1_data_out <= d_o_4_1_payload_B; else d_o_4_1_data_out <= d_o_4_1_payload_A; end if; end process; d_o_4_1_load_A <= (d_o_4_1_state_cmp_full and not(d_o_4_1_sel_wr)); d_o_4_1_load_B <= (d_o_4_1_sel_wr and d_o_4_1_state_cmp_full); d_o_4_1_sel <= d_o_4_1_sel_rd; d_o_4_1_state_cmp_full <= '0' when (d_o_4_1_state = ap_const_lv2_1) else '1'; d_o_4_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then d_o_4_1_vld_in <= ap_const_logic_1; else d_o_4_1_vld_in <= ap_const_logic_0; end if; end process; d_o_4_1_vld_out <= d_o_4_1_state(0); d_o_4_TDATA <= d_o_4_1_data_out; d_o_4_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, d_o_4_1_state, ap_block_pp0_stage0_flag00000000) begin if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)))) then d_o_4_TDATA_blk_n <= d_o_4_1_state(1); else d_o_4_TDATA_blk_n <= ap_const_logic_1; end if; end process; d_o_4_TVALID <= d_o_4_1_state(0); d_o_5_1_ack_in <= d_o_5_1_state(1); d_o_5_1_ack_out <= d_o_5_TREADY; d_o_5_1_data_out_assign_proc : process(d_o_5_1_payload_A, d_o_5_1_payload_B, d_o_5_1_sel) begin if ((ap_const_logic_1 = d_o_5_1_sel)) then d_o_5_1_data_out <= d_o_5_1_payload_B; else d_o_5_1_data_out <= d_o_5_1_payload_A; end if; end process; d_o_5_1_load_A <= (d_o_5_1_state_cmp_full and not(d_o_5_1_sel_wr)); d_o_5_1_load_B <= (d_o_5_1_sel_wr and d_o_5_1_state_cmp_full); d_o_5_1_sel <= d_o_5_1_sel_rd; d_o_5_1_state_cmp_full <= '0' when (d_o_5_1_state = ap_const_lv2_1) else '1'; d_o_5_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then d_o_5_1_vld_in <= ap_const_logic_1; else d_o_5_1_vld_in <= ap_const_logic_0; end if; end process; d_o_5_1_vld_out <= d_o_5_1_state(0); d_o_5_TDATA <= d_o_5_1_data_out; d_o_5_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, d_o_5_1_state, ap_block_pp0_stage0_flag00000000) begin if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)))) then d_o_5_TDATA_blk_n <= d_o_5_1_state(1); else d_o_5_TDATA_blk_n <= ap_const_logic_1; end if; end process; d_o_5_TVALID <= d_o_5_1_state(0); d_o_6_1_ack_in <= d_o_6_1_state(1); d_o_6_1_ack_out <= d_o_6_TREADY; d_o_6_1_data_out_assign_proc : process(d_o_6_1_payload_A, d_o_6_1_payload_B, d_o_6_1_sel) begin if ((ap_const_logic_1 = d_o_6_1_sel)) then d_o_6_1_data_out <= d_o_6_1_payload_B; else d_o_6_1_data_out <= d_o_6_1_payload_A; end if; end process; d_o_6_1_load_A <= (d_o_6_1_state_cmp_full and not(d_o_6_1_sel_wr)); d_o_6_1_load_B <= (d_o_6_1_sel_wr and d_o_6_1_state_cmp_full); d_o_6_1_sel <= d_o_6_1_sel_rd; d_o_6_1_state_cmp_full <= '0' when (d_o_6_1_state = ap_const_lv2_1) else '1'; d_o_6_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then d_o_6_1_vld_in <= ap_const_logic_1; else d_o_6_1_vld_in <= ap_const_logic_0; end if; end process; d_o_6_1_vld_out <= d_o_6_1_state(0); d_o_6_TDATA <= d_o_6_1_data_out; d_o_6_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, d_o_6_1_state, ap_block_pp0_stage0_flag00000000) begin if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)))) then d_o_6_TDATA_blk_n <= d_o_6_1_state(1); else d_o_6_TDATA_blk_n <= ap_const_logic_1; end if; end process; d_o_6_TVALID <= d_o_6_1_state(0); d_o_7_1_ack_in <= d_o_7_1_state(1); d_o_7_1_ack_out <= d_o_7_TREADY; d_o_7_1_data_out_assign_proc : process(d_o_7_1_payload_A, d_o_7_1_payload_B, d_o_7_1_sel) begin if ((ap_const_logic_1 = d_o_7_1_sel)) then d_o_7_1_data_out <= d_o_7_1_payload_B; else d_o_7_1_data_out <= d_o_7_1_payload_A; end if; end process; d_o_7_1_load_A <= (d_o_7_1_state_cmp_full and not(d_o_7_1_sel_wr)); d_o_7_1_load_B <= (d_o_7_1_sel_wr and d_o_7_1_state_cmp_full); d_o_7_1_sel <= d_o_7_1_sel_rd; d_o_7_1_state_cmp_full <= '0' when (d_o_7_1_state = ap_const_lv2_1) else '1'; d_o_7_1_vld_in_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0_flag00011001) begin if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then d_o_7_1_vld_in <= ap_const_logic_1; else d_o_7_1_vld_in <= ap_const_logic_0; end if; end process; d_o_7_1_vld_out <= d_o_7_1_state(0); d_o_7_TDATA <= d_o_7_1_data_out; d_o_7_TDATA_blk_n_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, d_o_7_1_state, ap_block_pp0_stage0_flag00000000) begin if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter2) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0)))) then d_o_7_TDATA_blk_n <= d_o_7_1_state(1); else d_o_7_TDATA_blk_n <= ap_const_logic_1; end if; end process; d_o_7_TVALID <= d_o_7_1_state(0); exitcond_fu_246_p2 <= "1" when (i_1_7_fu_236_p2 = ap_const_lv6_20) else "0"; i1_cast_fu_232_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i1_phi_fu_222_p6),6)); i1_phi_fu_222_p6_assign_proc : process(i1_reg_218, tmp_17_reg_502, exitcond_reg_507, ap_condition_1051) begin if ((ap_condition_1051 = ap_const_boolean_1)) then if ((ap_const_lv1_1 = exitcond_reg_507)) then i1_phi_fu_222_p6 <= ap_const_lv5_0; elsif ((ap_const_lv1_0 = exitcond_reg_507)) then i1_phi_fu_222_p6 <= tmp_17_reg_502; else i1_phi_fu_222_p6 <= i1_reg_218; end if; else i1_phi_fu_222_p6 <= i1_reg_218; end if; end process; i_1_7_fu_236_p2 <= std_logic_vector(unsigned(ap_const_lv6_8) + unsigned(i1_cast_fu_232_p1)); tmp1_fu_258_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_0_0_data_out),32)); tmp_10_fu_293_p1 <= acc_1(16 - 1 downto 0); tmp_11_fu_324_p1 <= acc_2(16 - 1 downto 0); tmp_12_fu_355_p1 <= acc_3(16 - 1 downto 0); tmp_13_fu_386_p1 <= acc_4(16 - 1 downto 0); tmp_14_fu_417_p1 <= acc_5(16 - 1 downto 0); tmp_15_fu_448_p1 <= acc_6(16 - 1 downto 0); tmp_16_fu_479_p1 <= acc_7(16 - 1 downto 0); tmp_17_fu_242_p1 <= i_1_7_fu_236_p2(5 - 1 downto 0); tmp_1_1_fu_297_p2 <= std_logic_vector(signed(tmp_s_fu_289_p1) + signed(acc_1)); tmp_1_2_fu_328_p2 <= std_logic_vector(signed(tmp_9_fu_320_p1) + signed(acc_2)); tmp_1_3_fu_359_p2 <= std_logic_vector(signed(tmp_3_fu_351_p1) + signed(acc_3)); tmp_1_4_fu_390_p2 <= std_logic_vector(signed(tmp_4_fu_382_p1) + signed(acc_4)); tmp_1_5_fu_421_p2 <= std_logic_vector(signed(tmp_5_fu_413_p1) + signed(acc_5)); tmp_1_6_fu_452_p2 <= std_logic_vector(signed(tmp_6_fu_444_p1) + signed(acc_6)); tmp_1_7_fu_483_p2 <= std_logic_vector(signed(tmp_7_fu_475_p1) + signed(acc_7)); tmp_1_fu_266_p2 <= std_logic_vector(signed(tmp1_fu_258_p1) + signed(acc_0)); tmp_2_1_fu_309_p2 <= std_logic_vector(unsigned(tmp_10_fu_293_p1) + unsigned(d_i_1_0_data_out)); tmp_2_2_fu_340_p2 <= std_logic_vector(unsigned(tmp_11_fu_324_p1) + unsigned(d_i_2_0_data_out)); tmp_2_3_fu_371_p2 <= std_logic_vector(unsigned(tmp_12_fu_355_p1) + unsigned(d_i_3_0_data_out)); tmp_2_4_fu_402_p2 <= std_logic_vector(unsigned(tmp_13_fu_386_p1) + unsigned(d_i_4_0_data_out)); tmp_2_5_fu_433_p2 <= std_logic_vector(unsigned(tmp_14_fu_417_p1) + unsigned(d_i_5_0_data_out)); tmp_2_6_fu_464_p2 <= std_logic_vector(unsigned(tmp_15_fu_448_p1) + unsigned(d_i_6_0_data_out)); tmp_2_7_fu_495_p2 <= std_logic_vector(unsigned(tmp_16_fu_479_p1) + unsigned(d_i_7_0_data_out)); tmp_2_fu_262_p1 <= acc_0(16 - 1 downto 0); tmp_3_fu_351_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_3_0_data_out),32)); tmp_4_fu_382_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_4_0_data_out),32)); tmp_5_fu_413_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_5_0_data_out),32)); tmp_6_fu_444_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_6_0_data_out),32)); tmp_7_fu_475_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_7_0_data_out),32)); tmp_8_fu_278_p2 <= std_logic_vector(unsigned(tmp_2_fu_262_p1) + unsigned(d_i_0_0_data_out)); tmp_9_fu_320_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_2_0_data_out),32)); tmp_s_fu_289_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(d_i_1_0_data_out),32)); end behav;

mit

VerkhovtsovPavel/BSUIR_Labs

Labs/POCP/POCP-4/src/REGn.vhd

1

674

library ieee; use ieee.std_logic_1164.all; entity REGn is generic (n : integer := 4); port( Din : in std_logic_vector(n-1 downto 0); EN : in std_logic; Dout : out std_logic_vector(n-1 downto 0) ); end REGn; architecture behavior of REGn is signal reg : std_logic_vector(n-1 downto 0); begin main : process(Din, EN) begin if EN='1' then reg <= Din; end if; end process; Dout <= reg; end behavior; architecture structual of REGn is component DEL port(D, E : in std_logic; Q: out std_logic); end component DEL; begin G_1 : for I in 0 to N-1 generate DEL_I : DEL port map (Din(I), EN, Dout(I)); end generate; end architecture structual;

mit

MarkBlanco/FPGA_Sandbox

RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ipshared/cb07/hdl/axi_gpio_v2_0_vh_rfs.vhd

3

76385

------------------------------------------------------------------------------- -- gpio_core - entity/architecture pair ------------------------------------------------------------------------------- -- *************************************************************************** -- DISCLAIMER OF LIABILITY -- -- This file contains proprietary and confidential information of -- Xilinx, Inc. ("Xilinx"), that is distributed under a license -- from Xilinx, and may be used, copied and/or disclosed only -- pursuant to the terms of a valid license agreement with Xilinx. -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION -- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER -- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT -- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, -- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx -- does not warrant that functions included in the Materials will -- meet the requirements of Licensee, or that the operation of the -- Materials will be uninterrupted or error-free, or that defects -- in the Materials will be corrected. Furthermore, Xilinx does -- not warrant or make any representations regarding use, or the -- results of the use, of the Materials in terms of correctness, -- accuracy, reliability or otherwise. -- -- Xilinx products are not designed or intended to be fail-safe, -- or for use in any application requiring fail-safe performance, -- such as life-support or safety devices or systems, Class III -- medical devices, nuclear facilities, applications related to -- the deployment of airbags, or any other applications that could -- lead to death, personal injury or severe property or -- environmental damage (individually and collectively, "critical -- applications"). Customer assumes the sole risk and liability -- of any use of Xilinx products in critical applications, -- subject only to applicable laws and regulations governing -- limitations on product liability. -- -- Copyright 2009 Xilinx, Inc. -- All rights reserved. -- -- This disclaimer and copyright notice must be retained as part -- of this file at all times. -- *************************************************************************** -- ------------------------------------------------------------------------------- -- Filename: gpio_core.vhd -- Version: v1.01a -- Description: General Purpose I/O for AXI Interface -- ------------------------------------------------------------------------------- -- Structure: -- axi_gpio.vhd -- -- axi_lite_ipif.vhd -- -- interrupt_control.vhd -- -- gpio_core.vhd -- ------------------------------------------------------------------------------- -- -- Author: KSB -- History: -- ~~~~~~~~~~~~~~ -- KSB 09/15/09 -- ^^^^^^^^^^^^^^ -- ~~~~~~~~~~~~~~ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_cmb" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; library lib_cdc_v1_0_2; ------------------------------------------------------------------------------- -- Definition of Generics : -- ------------------------------------------------------------------------------- -- C_DW -- Data width of PLB BUS. -- C_AW -- Address width of PLB BUS. -- C_GPIO_WIDTH -- GPIO Data Bus width. -- C_GPIO2_WIDTH -- GPIO2 Data Bus width. -- C_INTERRUPT_PRESENT -- GPIO Interrupt. -- C_DOUT_DEFAULT -- GPIO_DATA Register reset value. -- C_TRI_DEFAULT -- GPIO_TRI Register reset value. -- C_IS_DUAL -- Dual Channel GPIO. -- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value. -- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value. -- C_FAMILY -- XILINX FPGA family ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Definition of Ports -- ------------------------------------------------------------------------------- -- Clk -- Input clock -- Rst -- Reset -- ABus_Reg -- Bus to IP address -- BE_Reg -- Bus to IP byte enables -- DBus_Reg -- Bus to IP data bus -- RNW_Reg -- Bus to IP read write control -- GPIO_DBus -- IP to Bus data bus -- GPIO_xferAck -- GPIO transfer acknowledge -- GPIO_intr -- GPIO channel 1 interrupt to IPIC -- GPIO2_intr -- GPIO channel 2 interrupt to IPIC -- GPIO_Select -- GPIO select -- -- GPIO_IO_I -- Channel 1 General purpose I/O in port -- GPIO_IO_O -- Channel 1 General purpose I/O out port -- GPIO_IO_T -- Channel 1 General purpose I/O TRI-STATE control port -- GPIO2_IO_I -- Channel 2 General purpose I/O in port -- GPIO2_IO_O -- Channel 2 General purpose I/O out port -- GPIO2_IO_T -- Channel 2 General purpose I/O TRI-STATE control port ------------------------------------------------------------------------------- entity GPIO_Core is generic ( C_DW : integer := 32; C_AW : integer := 32; C_GPIO_WIDTH : integer := 32; C_GPIO2_WIDTH : integer := 32; C_MAX_GPIO_WIDTH : integer := 32; C_INTERRUPT_PRESENT : integer := 0; C_DOUT_DEFAULT : std_logic_vector (0 to 31) := X"0000_0000"; C_TRI_DEFAULT : std_logic_vector (0 to 31) := X"FFFF_FFFF"; C_IS_DUAL : integer := 0; C_ALL_OUTPUTS : integer range 0 to 1 := 0;--2/28/2013 C_ALL_OUTPUTS_2 : integer range 0 to 1 := 0;--2/28/2013 C_ALL_INPUTS : integer range 0 to 1 := 0; C_ALL_INPUTS_2 : integer range 0 to 1 := 0; C_DOUT_DEFAULT_2 : std_logic_vector (0 to 31) := X"0000_0000"; C_TRI_DEFAULT_2 : std_logic_vector (0 to 31) := X"FFFF_FFFF"; C_FAMILY : string := "virtex7" ); port ( Clk : in std_logic; Rst : in std_logic; ABus_Reg : in std_logic_vector(0 to C_AW-1); BE_Reg : in std_logic_vector(0 to C_DW/8-1); DBus_Reg : in std_logic_vector(0 to C_MAX_GPIO_WIDTH-1); RNW_Reg : in std_logic; GPIO_DBus : out std_logic_vector(0 to C_DW-1); GPIO_xferAck : out std_logic; GPIO_intr : out std_logic; GPIO2_intr : out std_logic; GPIO_Select : in std_logic; GPIO_IO_I : in std_logic_vector(0 to C_GPIO_WIDTH-1); GPIO_IO_O : out std_logic_vector(0 to C_GPIO_WIDTH-1); GPIO_IO_T : out std_logic_vector(0 to C_GPIO_WIDTH-1); GPIO2_IO_I : in std_logic_vector(0 to C_GPIO2_WIDTH-1); GPIO2_IO_O : out std_logic_vector(0 to C_GPIO2_WIDTH-1); GPIO2_IO_T : out std_logic_vector(0 to C_GPIO2_WIDTH-1) ); end entity GPIO_Core; ------------------------------------------------------------------------------- -- Architecture section ------------------------------------------------------------------------------- architecture IMP of GPIO_Core is -- Pragma Added to supress synth warnings attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of IMP : architecture is "yes"; ---------------------------------------------------------------------- -- Function for Reduction OR ---------------------------------------------------------------------- function or_reduce(l : std_logic_vector) return std_logic is variable v : std_logic := '0'; begin for i in l'range loop v := v or l(i); end loop; return v; end; --------------------------------------------------------------------- -- End of Function ------------------------------------------------------------------- --constant GPIO_G_W : integer = C_GPIO_WIDTH when (C_GPIO_WIDTH > C_GPIO2_WIDTH) else C_GPIO2_; signal gpio_Data_Select : std_logic_vector(0 to C_IS_DUAL); signal gpio_OE_Select : std_logic_vector(0 to C_IS_DUAL); signal Read_Reg_Rst : STD_LOGIC; signal Read_Reg_In : std_logic_vector(0 to C_GPIO_WIDTH-1); signal Read_Reg_CE : std_logic_vector(0 to C_GPIO_WIDTH-1); signal gpio_Data_Out : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_DOUT_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1); signal gpio_Data_In : std_logic_vector(0 to C_GPIO_WIDTH-1); signal gpio_in_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1); signal gpio_in_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1); signal gpio_io_i_d1 : std_logic_vector(0 to C_GPIO_WIDTH-1); signal gpio_io_i_d2 : std_logic_vector(0 to C_GPIO_WIDTH-1); signal gpio_OE : std_logic_vector(0 to C_GPIO_WIDTH-1) := C_TRI_DEFAULT(C_DW-C_GPIO_WIDTH to C_DW-1); signal GPIO_DBus_i : std_logic_vector(0 to C_DW-1); signal gpio_data_in_xor : std_logic_vector(0 to C_GPIO_WIDTH-1); signal gpio_data_in_xor_reg : std_logic_vector(0 to C_GPIO_WIDTH-1); signal or_ints : std_logic_vector(0 to 0); signal or_ints2 : std_logic_vector(0 to 0); signal iGPIO_xferAck : STD_LOGIC; signal gpio_xferAck_Reg : STD_LOGIC; signal dout_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1); signal tri_default_i : std_logic_vector(0 to C_GPIO_WIDTH-1); signal reset_zeros : std_logic_vector(0 to C_GPIO_WIDTH-1); signal dout2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal tri2_default_i : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal reset2_zeros : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio_reg_en : std_logic; begin -- architecture IMP reset_zeros <= (others => '0'); reset2_zeros <= (others => '0'); TIE_DEFAULTS_GENERATE : if C_DW >= C_GPIO_WIDTH generate SELECT_BITS_GENERATE : for i in 0 to C_GPIO_WIDTH-1 generate dout_default_i(i) <= C_DOUT_DEFAULT(i-C_GPIO_WIDTH+C_DW); tri_default_i(i) <= C_TRI_DEFAULT(i-C_GPIO_WIDTH+C_DW); end generate SELECT_BITS_GENERATE; end generate TIE_DEFAULTS_GENERATE; TIE_DEFAULTS_2_GENERATE : if C_DW >= C_GPIO2_WIDTH generate SELECT_BITS_2_GENERATE : for i in 0 to C_GPIO2_WIDTH-1 generate dout2_default_i(i) <= C_DOUT_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW); tri2_default_i(i) <= C_TRI_DEFAULT_2(i-C_GPIO2_WIDTH+C_DW); end generate SELECT_BITS_2_GENERATE; end generate TIE_DEFAULTS_2_GENERATE; Read_Reg_Rst <= iGPIO_xferAck or gpio_xferAck_Reg or (not GPIO_Select) or (GPIO_Select and not RNW_Reg); gpio_reg_en <= GPIO_Select when (ABus_Reg(0) = '0') else '0'; ----------------------------------------------------------------------------- -- XFER_ACK_PROCESS ----------------------------------------------------------------------------- -- Generation of Transfer Ack signal for one clock pulse ----------------------------------------------------------------------------- XFER_ACK_PROCESS : process (Clk) is begin if (Clk'EVENT and Clk = '1') then if (Rst = '1') then iGPIO_xferAck <= '0'; else iGPIO_xferAck <= GPIO_Select and not gpio_xferAck_Reg; if iGPIO_xferAck = '1' then iGPIO_xferAck <= '0'; end if; end if; end if; end process XFER_ACK_PROCESS; ----------------------------------------------------------------------------- -- DELAYED_XFER_ACK_PROCESS ----------------------------------------------------------------------------- -- Single Reg stage to make Transfer Ack period one clock pulse wide ----------------------------------------------------------------------------- DELAYED_XFER_ACK_PROCESS : process (Clk) is begin if (Clk'EVENT and Clk = '1') then if (Rst = '1') then gpio_xferAck_Reg <= '0'; else gpio_xferAck_Reg <= iGPIO_xferAck; end if; end if; end process DELAYED_XFER_ACK_PROCESS; GPIO_xferAck <= iGPIO_xferAck; ----------------------------------------------------------------------------- -- Drive GPIO interrupts to '0' when interrupt not present ----------------------------------------------------------------------------- DONT_GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate gpio_intr <= '0'; gpio2_intr <= '0'; end generate DONT_GEN_INTERRUPT; ---------------------------------------------------------------------------- -- When only one channel is used, the additional logic for the second -- channel ports is not present ----------------------------------------------------------------------------- Not_Dual : if (C_IS_DUAL = 0) generate GPIO2_IO_O <= C_DOUT_DEFAULT(0 to C_GPIO2_WIDTH-1); GPIO2_IO_T <= C_TRI_DEFAULT_2(0 to C_GPIO2_WIDTH-1); ALLOUT_ND : if (C_ALL_OUTPUTS = 1) generate READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate ---------------------------------------------------------------------------- -- XFER_ACK_PROCESS ---------------------------------------------------------------------------- -- Generation of Transfer Ack signal for one clock pulse ---------------------------------------------------------------------------- GPIO_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0'; else GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i); end if; end if; end process; end generate READ_REG_GEN; end generate ALLOUT_ND; ALLIN1_ND : if (C_ALL_INPUTS = 1) generate READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate ---------------------------------------------------------------------------- -- XFER_ACK_PROCESS ---------------------------------------------------------------------------- -- Generation of Transfer Ack signal for one clock pulse ---------------------------------------------------------------------------- GPIO_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0'; else GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i); end if; end if; end process; end generate READ_REG_GEN; end generate ALLIN1_ND; ALLOUT0_ND : if (C_ALL_OUTPUTS = 0 and C_ALL_INPUTS = 0) generate READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate ---------------------------------------------------------------------------- -- XFER_ACK_PROCESS ---------------------------------------------------------------------------- -- Generation of Transfer Ack signal for one clock pulse ---------------------------------------------------------------------------- GPIO_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0'; else if (gpio_OE(i) = '0' and gpio_OE_Select(0) = '0')then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i); else GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i); end if; --GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i) when (gpio_OE(i) = '1') else Read_Reg_In(i); end if; end if; end process; end generate READ_REG_GEN; end generate ALLOUT0_ND; TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0'); end generate TIE_DBUS_GENERATE; ----------------------------------------------------------------------------- -- GPIO_DBUS_PROCESS ----------------------------------------------------------------------------- -- This process generates the GPIO DATA BUS from the GPIO_DBUS_I based on -- the channel select signals ----------------------------------------------------------------------------- GPIO_DBus <= GPIO_DBus_i; ----------------------------------------------------------------------------- -- REG_SELECT_PROCESS ----------------------------------------------------------------------------- -- GPIO REGISTER selection decoder for single channel configuration ----------------------------------------------------------------------------- --REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is begin gpio_Data_Select(0) <= '0'; gpio_OE_Select(0) <= '0'; --if GPIO_Select = '1' then if gpio_reg_en = '1' then if (ABus_Reg(5) = '0') then case ABus_Reg(6) is -- bit A29 when '0' => gpio_Data_Select(0) <= '1'; when '1' => gpio_OE_Select(0) <= '1'; -- coverage off when others => null; -- coverage on end case; end if; end if; end process REG_SELECT_PROCESS; INPUT_DOUBLE_REGS3 : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 0, C_VECTOR_WIDTH => C_GPIO_WIDTH, C_MTBF_STAGES => 4 ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => '0', prmry_vect_in => GPIO_IO_I, scndry_aclk => Clk, scndry_resetn => '0', scndry_out => open, scndry_vect_out => gpio_io_i_d2 ); --------------------------------------------------------------------------- -- GPIO_INDATA_BIRDIR_PROCESS --------------------------------------------------------------------------- -- Reading of channel 1 data from Bidirectional GPIO port -- to GPIO_DATA REGISTER --------------------------------------------------------------------------- GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is begin if Clk = '1' and Clk'EVENT then -- gpio_io_i_d1 <= GPIO_IO_I; -- gpio_io_i_d2 <= gpio_io_i_d1; gpio_Data_In <= gpio_io_i_d2; end if; end process GPIO_INDATA_BIRDIR_PROCESS; --------------------------------------------------------------------------- -- GPIO_OUTDATA_PROCESS --------------------------------------------------------------------------- -- Writing to Channel 1 GPIO_DATA REGISTER --------------------------------------------------------------------------- GPIO_OUTDATA_PROCESS : process(Clk) is begin if Clk = '1' and Clk'EVENT then if (Rst = '1') then gpio_Data_Out <= dout_default_i; elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then for i in 0 to C_GPIO_WIDTH-1 loop gpio_Data_Out(i) <= DBus_Reg(i); end loop; end if; end if; end process GPIO_OUTDATA_PROCESS; --------------------------------------------------------------------------- -- READ_MUX_PROCESS --------------------------------------------------------------------------- -- Selects GPIO_TRI control or GPIO_DATA Register to be read --------------------------------------------------------------------------- READ_MUX_PROCESS : process (gpio_Data_In, gpio_Data_Select, gpio_OE, gpio_OE_Select,gpio_Data_Out) is begin Read_Reg_In <= (others => '0'); if gpio_Data_Select(0) = '1' then Read_Reg_In <= gpio_Data_In; --Read_Reg_In <= gpio_Data_In; elsif gpio_OE_Select(0) = '1' then Read_Reg_In <= gpio_OE; end if; end process READ_MUX_PROCESS; --------------------------------------------------------------------------- -- GPIO_OE_PROCESS --------------------------------------------------------------------------- -- Writing to Channel 1 GPIO_TRI Control REGISTER --------------------------------------------------------------------------- GPIO_OE_PROCESS : process(Clk) is begin if Clk = '1' and Clk'EVENT then if (Rst = '1') then gpio_OE <= tri_default_i; elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then for i in 0 to C_GPIO_WIDTH-1 loop gpio_OE(i) <= DBus_Reg(i); end loop; end if; end if; end process GPIO_OE_PROCESS; GPIO_IO_O <= gpio_Data_Out; GPIO_IO_T <= gpio_OE; ---------------------------------------------------------------------------- -- INTERRUPT IS PRESENT ---------------------------------------------------------------------------- -- When the C_INTERRUPT_PRESENT=1, the interrupt is driven based on whether -- there is a change in the data coming in at the GPIO_IO_I port or GPIO_In -- port ---------------------------------------------------------------------------- GEN_INTERRUPT : if (C_INTERRUPT_PRESENT = 1) generate gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2; ------------------------------------------------------------------------- -- An interrupt conditon exists if there is a change on any bit. ------------------------------------------------------------------------- or_ints(0) <= or_reduce(gpio_data_in_xor_reg); ------------------------------------------------------------------------- -- Registering Interrupt condition ------------------------------------------------------------------------- REGISTER_XOR_INTR : process (Clk) is begin if (Clk'EVENT and Clk = '1') then if (Rst = '1') then gpio_data_in_xor_reg <= reset_zeros; GPIO_intr <= '0'; else gpio_data_in_xor_reg <= gpio_data_in_xor; GPIO_intr <= or_ints(0); end if; end if; end process REGISTER_XOR_INTR; gpio2_intr <= '0'; -- Channel 2 interrupt is driven low end generate GEN_INTERRUPT; end generate Not_Dual; ---)(------------------------------------------------------------------------ -- When both the channels are used, the additional logic for the second -- channel ports ----------------------------------------------------------------------------- Dual : if (C_IS_DUAL = 1) generate signal gpio2_Data_In : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio2_in_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio2_in_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio2_io_i_d1 : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio2_io_i_d2 : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio2_data_in_xor : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio2_data_in_xor_reg : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal gpio2_Data_Out : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_DOUT_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1); signal gpio2_OE : std_logic_vector(0 to C_GPIO2_WIDTH-1) := C_TRI_DEFAULT_2(C_DW-C_GPIO2_WIDTH to C_DW-1); signal Read_Reg2_In : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal Read_Reg2_CE : std_logic_vector(0 to C_GPIO2_WIDTH-1); signal GPIO2_DBus_i : std_logic_vector(0 to C_DW-1); begin ALLOUT0_ND_G0 : if (C_ALL_OUTPUTS = 0 and C_ALL_INPUTS = 0) generate READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate ---------------------------------------------------------------------------- -- XFER_ACK_PROCESS ---------------------------------------------------------------------------- -- Generation of Transfer Ack signal for one clock pulse ---------------------------------------------------------------------------- GPIO_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0'; else if (gpio_OE(i) = '0' and gpio_OE_Select(0) = '0') then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i); else GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i); end if; --GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i) when (gpio_OE(i) = '1') else Read_Reg_In(i); end if; end if; end process; end generate READ_REG_GEN; end generate ALLOUT0_ND_G0; ALLIN0_ND_G0 : if (C_ALL_INPUTS = 1) generate READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate ---------------------------------------------------------------------------- -- XFER_ACK_PROCESS ---------------------------------------------------------------------------- -- Generation of Transfer Ack signal for one clock pulse ---------------------------------------------------------------------------- GPIO_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0'; else GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= Read_Reg_In(i); end if; end if; end process; end generate READ_REG_GEN; end generate ALLIN0_ND_G0; ALLOUT0_ND_G1 : if (C_ALL_OUTPUTS = 1) generate READ_REG_GEN : for i in 0 to C_GPIO_WIDTH-1 generate begin -------------------------------------------------------------------------- -- GPIO_DBUS_I_PROCESS -------------------------------------------------------------------------- -- This process generates the GPIO CHANNEL1 DATA BUS -------------------------------------------------------------------------- GPIO_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= '0'; else GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i); end if; end if; end process; end generate READ_REG_GEN; end generate ALLOUT0_ND_G1; TIE_DBUS_GENERATE : if C_DW > C_GPIO_WIDTH generate GPIO_DBus_i(0 to C_DW-C_GPIO_WIDTH-1) <= (others => '0'); end generate TIE_DBUS_GENERATE; ALLIN0_ND_G2 : if (C_ALL_OUTPUTS_2 = 0 and C_ALL_INPUTS_2 = 1) generate READ_REG2_GEN : for i in 0 to C_GPIO2_WIDTH-1 generate -------------------------------------------------------------------------- -- GPIO2_DBUS_I_PROCESS -------------------------------------------------------------------------- -- This process generates the GPIO CHANNEL2 DATA BUS -------------------------------------------------------------------------- GPIO2_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= '0'; else GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= Read_Reg2_In(i); --GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i) when (gpio_OE(i) = '1') else Read_Reg_In(i); end if; end if; end process; end generate READ_REG2_GEN; end generate ALLIN0_ND_G2; ALLOUT0_ND_G2 : if (C_ALL_OUTPUTS_2 = 0 and C_ALL_INPUTS_2 = 0) generate READ_REG2_GEN : for i in 0 to C_GPIO2_WIDTH-1 generate -------------------------------------------------------------------------- -- GPIO2_DBUS_I_PROCESS -------------------------------------------------------------------------- -- This process generates the GPIO CHANNEL2 DATA BUS -------------------------------------------------------------------------- GPIO2_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= '0'; else if (gpio2_OE(i) = '0' and gpio_OE_Select(1) = '0') then GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= gpio2_Data_Out(i); else GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= Read_Reg2_In(i); end if; -- GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= gpio2_Data_Out(i) when (gpio2_OE(i) = '1') else Read_Reg2_In(i); --GPIO_DBus_i(i-C_GPIO_WIDTH+C_DW) <= gpio_Data_Out(i) when (gpio_OE(i) = '1') else Read_Reg_In(i); end if; end if; end process; end generate READ_REG2_GEN; end generate ALLOUT0_ND_G2; ALLOUT1_ND_G2 : if (C_ALL_OUTPUTS_2 = 1) generate READ_REG2_GEN : for i in 0 to C_GPIO2_WIDTH-1 generate -------------------------------------------------------------------------- -- GPIO2_DBUS_I_PROCESS -------------------------------------------------------------------------- -- This process generates the GPIO CHANNEL2 DATA BUS -------------------------------------------------------------------------- GPIO2_DBUS_I_PROC : process(Clk) begin if Clk'event and Clk = '1' then if Read_Reg_Rst = '1' then GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= '0'; else GPIO2_DBus_i(i-C_GPIO2_WIDTH+C_DW) <= gpio2_Data_Out(i); end if; end if; end process; end generate READ_REG2_GEN; end generate ALLOUT1_ND_G2; TIE_DBUS2_GENERATE : if C_DW > C_GPIO2_WIDTH generate GPIO2_DBus_i(0 to C_DW-C_GPIO2_WIDTH-1) <= (others => '0'); end generate TIE_DBUS2_GENERATE; --------------------------------------------------------------------------- -- GPIO_DBUS_PROCESS --------------------------------------------------------------------------- -- This process generates the GPIO DATA BUS from the GPIO_DBUS_I and -- GPIO2_DBUS_I based on which channel is selected --------------------------------------------------------------------------- GPIO_DBus <= GPIO_DBus_i when (((gpio_Data_Select(0) = '1') or (gpio_OE_Select(0) = '1')) and (RNW_Reg = '1')) else GPIO2_DBus_i; ----------------------------------------------------------------------------- -- DUAL_REG_SELECT_PROCESS ----------------------------------------------------------------------------- -- GPIO REGISTER selection decoder for Dual channel configuration ----------------------------------------------------------------------------- --DUAL_REG_SELECT_PROCESS : process (GPIO_Select, ABus_Reg) is DUAL_REG_SELECT_PROCESS : process (gpio_reg_en, ABus_Reg) is variable ABus_reg_select : std_logic_vector(0 to 1); begin ABus_reg_select := ABus_Reg(5 to 6); gpio_Data_Select <= (others => '0'); gpio_OE_Select <= (others => '0'); --if GPIO_Select = '1' then if gpio_reg_en = '1' then -- case ABus_Reg(28 to 29) is -- bit A28,A29 for dual case ABus_reg_select is -- bit A28,A29 for dual when "00" => gpio_Data_Select(0) <= '1'; when "01" => gpio_OE_Select(0) <= '1'; when "10" => gpio_Data_Select(1) <= '1'; when "11" => gpio_OE_Select(1) <= '1'; -- coverage off when others => null; -- coverage on end case; end if; end process DUAL_REG_SELECT_PROCESS; --------------------------------------------------------------------------- -- GPIO_INDATA_BIRDIR_PROCESS --------------------------------------------------------------------------- -- Reading of channel 1 data from Bidirectional GPIO port -- to GPIO_DATA REGISTER --------------------------------------------------------------------------- INPUT_DOUBLE_REGS4 : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 0, C_VECTOR_WIDTH => C_GPIO_WIDTH, C_MTBF_STAGES => 4 ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => '0', prmry_vect_in => GPIO_IO_I, scndry_aclk => Clk, scndry_resetn => '0', scndry_out => open, scndry_vect_out => gpio_io_i_d2 ); GPIO_INDATA_BIRDIR_PROCESS : process(Clk) is begin if Clk = '1' and Clk'EVENT then -- gpio_io_i_d1 <= GPIO_IO_I; -- gpio_io_i_d2 <= gpio_io_i_d1; --if (C_ALL_OUTPUTS = '1') then -- gpio_Data_In <= gpio_Data_Out; -- else gpio_Data_In <= gpio_io_i_d2; -- end if; end if; end process GPIO_INDATA_BIRDIR_PROCESS; INPUT_DOUBLE_REGS5 : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 0, C_VECTOR_WIDTH => C_GPIO2_WIDTH, C_MTBF_STAGES => 4 ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => '0', prmry_vect_in => GPIO2_IO_I, scndry_aclk => Clk, scndry_resetn => '0', scndry_out => open, scndry_vect_out => gpio2_io_i_d2 ); --------------------------------------------------------------------------- -- GPIO2_INDATA_BIRDIR_PROCESS --------------------------------------------------------------------------- -- Reading of channel 2 data from Bidirectional GPIO2 port -- to GPIO2_DATA REGISTER --------------------------------------------------------------------------- GPIO2_INDATA_BIRDIR_PROCESS : process(Clk) is begin if Clk = '1' and Clk'EVENT then -- gpio2_io_i_d1 <= GPIO2_IO_I; -- gpio2_io_i_d2 <= gpio2_io_i_d1; -- if (C_ALL_OUTPUTS = '1') then -- gpio2_Data_In <= gpio2_Data_Out; -- else gpio2_Data_In <= gpio2_io_i_d2; -- end if; end if; end process GPIO2_INDATA_BIRDIR_PROCESS; --------------------------------------------------------------------------- -- GPIO_OUTDATA_PROCESS_0_0 --------------------------------------------------------------------------- -- Writing to Channel 1 GPIO_DATA REGISTER --------------------------------------------------------------------------- GPIO_OUTDATA_PROCESS_0_0 : process(Clk) is begin if Clk = '1' and Clk'EVENT then if (Rst = '1') then gpio_Data_Out <= dout_default_i; elsif gpio_Data_Select(0) = '1' and RNW_Reg = '0' then for i in 0 to C_GPIO_WIDTH-1 loop gpio_Data_Out(i) <= DBus_Reg(i); end loop; end if; end if; end process GPIO_OUTDATA_PROCESS_0_0; --------------------------------------------------------------------------- -- GPIO_OE_PROCESS_0_0 --------------------------------------------------------------------------- -- Writing to Channel 1 GPIO_TRI Control REGISTER --------------------------------------------------------------------------- GPIO_OE_PROCESS : process(Clk) is begin if Clk = '1' and Clk'EVENT then if (Rst = '1') then gpio_OE <= tri_default_i; elsif gpio_OE_Select(0) = '1' and RNW_Reg = '0' then for i in 0 to C_GPIO_WIDTH-1 loop gpio_OE(i) <= DBus_Reg(i); -- end if; end loop; end if; end if; end process GPIO_OE_PROCESS; --------------------------------------------------------------------------- -- GPIO2_OUTDATA_PROCESS_0_0 --------------------------------------------------------------------------- -- Writing to Channel 2 GPIO2_DATA REGISTER --------------------------------------------------------------------------- GPIO2_OUTDATA_PROCESS_0_0 : process(Clk) is begin if Clk = '1' and Clk'EVENT then if (Rst = '1') then gpio2_Data_Out <= dout2_default_i; elsif gpio_Data_Select(1) = '1' and RNW_Reg = '0' then for i in 0 to C_GPIO2_WIDTH-1 loop gpio2_Data_Out(i) <= DBus_Reg(i); -- end if; end loop; end if; end if; end process GPIO2_OUTDATA_PROCESS_0_0; --------------------------------------------------------------------------- -- GPIO2_OE_PROCESS_0_0 --------------------------------------------------------------------------- -- Writing to Channel 2 GPIO2_TRI Control REGISTER --------------------------------------------------------------------------- GPIO2_OE_PROCESS_0_0 : process(Clk) is begin if Clk = '1' and Clk'EVENT then if (Rst = '1') then gpio2_OE <= tri2_default_i; elsif gpio_OE_Select(1) = '1' and RNW_Reg = '0' then for i in 0 to C_GPIO2_WIDTH-1 loop gpio2_OE(i) <= DBus_Reg(i); end loop; end if; end if; end process GPIO2_OE_PROCESS_0_0; GPIO_IO_O <= gpio_Data_Out; GPIO_IO_T <= gpio_OE; GPIO2_IO_O <= gpio2_Data_Out; GPIO2_IO_T <= gpio2_OE; --------------------------------------------------------------------------- -- READ_MUX_PROCESS_0_0 --------------------------------------------------------------------------- -- Selects among Channel 1 GPIO_DATA ,GPIO_TRI and Channel 2 GPIO2_DATA -- GPIO2_TRI REGISTERS for reading --------------------------------------------------------------------------- READ_MUX_PROCESS_0_0 : process (gpio2_Data_In, gpio2_OE, gpio_Data_In, gpio_Data_Select, gpio_OE, gpio_OE_Select,gpio_Data_Out,gpio2_Data_Out) is begin Read_Reg_In <= (others => '0'); Read_Reg2_In <= (others => '0'); if gpio_Data_Select(0) = '1' then Read_Reg_In <= gpio_Data_In; --Read_Reg_In <= gpio_Data_In; elsif gpio_OE_Select(0) = '1' then Read_Reg_In <= gpio_OE; elsif gpio_Data_Select(1) = '1' then Read_Reg2_In <= gpio2_Data_In; --Read_Reg2_In <= gpio2_Data_In; --Read_Reg2_In<= gpio2_Data_In; elsif gpio_OE_Select(1) = '1' then Read_Reg2_In <= gpio2_OE; end if; end process READ_MUX_PROCESS_0_0; --------------------------------------------------------------------------- -- INTERRUPT IS PRESENT --------------------------------------------------------------------------- gen_interrupt_dual : if (C_INTERRUPT_PRESENT = 1) generate gpio_data_in_xor <= gpio_Data_In xor gpio_io_i_d2; gpio2_data_in_xor <= gpio2_Data_In xor gpio2_io_i_d2; ------------------------------------------------------------------------- -- An interrupt conditon exists if there is a change any bit. ------------------------------------------------------------------------- or_ints(0) <= or_reduce(gpio_data_in_xor_reg); or_ints2(0) <= or_reduce(gpio2_data_in_xor_reg); ------------------------------------------------------------------------- -- Registering Interrupt condition ------------------------------------------------------------------------- REGISTER_XORs_INTRs : process (Clk) is begin if (Clk'EVENT and Clk = '1') then if (Rst = '1') then gpio_data_in_xor_reg <= reset_zeros; gpio2_data_in_xor_reg <= reset2_zeros; GPIO_intr <= '0'; GPIO2_intr <= '0'; else gpio_data_in_xor_reg <= gpio_data_in_xor; gpio2_data_in_xor_reg <= gpio2_data_in_xor; GPIO_intr <= or_ints(0); GPIO2_intr <= or_ints2(0); end if; end if; end process REGISTER_XORs_INTRs; end generate gen_interrupt_dual; end generate Dual; end architecture IMP; ------------------------------------------------------------------------------- -- AXI_GPIO - entity/architecture pair ------------------------------------------------------------------------------- -- -- *************************************************************************** -- DISCLAIMER OF LIABILITY -- -- This file contains proprietary and confidential information of -- Xilinx, Inc. ("Xilinx"), that is distributed under a license -- from Xilinx, and may be used, copied and/or disclosed only -- pursuant to the terms of a valid license agreement with Xilinx. -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION -- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER -- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT -- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, -- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx -- does not warrant that functions included in the Materials will -- meet the requirements of Licensee, or that the operation of the -- Materials will be uninterrupted or error-free, or that defects -- in the Materials will be corrected. Furthermore, Xilinx does -- not warrant or make any representations regarding use, or the -- results of the use, of the Materials in terms of correctness, -- accuracy, reliability or otherwise. -- -- Xilinx products are not designed or intended to be fail-safe, -- or for use in any application requiring fail-safe performance, -- such as life-support or safety devices or systems, Class III -- medical devices, nuclear facilities, applications related to -- the deployment of airbags, or any other applications that could -- lead to death, personal injury or severe property or -- environmental damage (individually and collectively, "critical -- applications"). Customer assumes the sole risk and liability -- of any use of Xilinx products in critical applications, -- subject only to applicable laws and regulations governing -- limitations on product liability. -- -- Copyright 2009 Xilinx, Inc. -- All rights reserved. -- -- This disclaimer and copyright notice must be retained as part -- of this file at all times. -- *************************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_gpio.vhd -- Version: v2.0 -- Description: General Purpose I/O for AXI Interface -- ------------------------------------------------------------------------------- -- Structure: -- axi_gpio.vhd -- -- axi_lite_ipif.vhd -- -- interrupt_control.vhd -- -- gpio_core.vhd ------------------------------------------------------------------------------- -- Author: KSB -- History: -- ~~~~~~~~~~~~~~ -- KSB 07/28/09 -- ^^^^^^^^^^^^^^ -- First version of axi_gpio. Based on xps_gpio 2.00a -- -- KSB 05/20/10 -- ^^^^^^^^^^^^^^ -- Updated for holes in address range -- ~~~~~~~~~~~~~~ -- VB 09/23/10 -- ^^^^^^^^^^^^^^ -- Updated for axi_lite_ipfi_v1_01_a -- ~~~~~~~~~~~~~~ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_cmb" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; use std.textio.all; ------------------------------------------------------------------------------- -- AXI common package of the proc common library is used for different -- function declarations ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- axi_gpio_v2_0_15 library is used for axi4 component declarations ------------------------------------------------------------------------------- library axi_lite_ipif_v3_0_4; use axi_lite_ipif_v3_0_4.ipif_pkg.calc_num_ce; use axi_lite_ipif_v3_0_4.ipif_pkg.INTEGER_ARRAY_TYPE; use axi_lite_ipif_v3_0_4.ipif_pkg.SLV64_ARRAY_TYPE; ------------------------------------------------------------------------------- -- axi_gpio_v2_0_15 library is used for interrupt controller component -- declarations ------------------------------------------------------------------------------- library interrupt_control_v3_1_4; ------------------------------------------------------------------------------- -- axi_gpio_v2_0_15 library is used for axi_gpio component declarations ------------------------------------------------------------------------------- library axi_gpio_v2_0_15; ------------------------------------------------------------------------------- -- Defination of Generics : -- ------------------------------------------------------------------------------- -- AXI generics -- C_BASEADDR -- Base address of the core -- C_HIGHADDR -- Permits alias of address space -- by making greater than xFFF -- C_S_AXI_ADDR_WIDTH -- Width of AXI Address interface (in bits) -- C_S_AXI_DATA_WIDTH -- Width of the AXI Data interface (in bits) -- C_FAMILY -- XILINX FPGA family -- C_INSTANCE -- Instance name ot the core in the EDK system -- C_GPIO_WIDTH -- GPIO Data Bus width. -- C_ALL_INPUTS -- Inputs Only. -- C_INTERRUPT_PRESENT -- GPIO Interrupt. -- C_IS_BIDIR -- Selects gpio_io_i as input. -- C_DOUT_DEFAULT -- GPIO_DATA Register reset value. -- C_TRI_DEFAULT -- GPIO_TRI Register reset value. -- C_IS_DUAL -- Dual Channel GPIO. -- C_ALL_INPUTS_2 -- Channel2 Inputs only. -- C_IS_BIDIR_2 -- Selects gpio2_io_i as input. -- C_DOUT_DEFAULT_2 -- GPIO2_DATA Register reset value. -- C_TRI_DEFAULT_2 -- GPIO2_TRI Register reset value. ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Defination of Ports -- ------------------------------------------------------------------------------- -- AXI signals -- s_axi_awaddr -- AXI Write address -- s_axi_awvalid -- Write address valid -- s_axi_awready -- Write address ready -- s_axi_wdata -- Write data -- s_axi_wstrb -- Write strobes -- s_axi_wvalid -- Write valid -- s_axi_wready -- Write ready -- s_axi_bresp -- Write response -- s_axi_bvalid -- Write response valid -- s_axi_bready -- Response ready -- s_axi_araddr -- Read address -- s_axi_arvalid -- Read address valid -- s_axi_arready -- Read address ready -- s_axi_rdata -- Read data -- s_axi_rresp -- Read response -- s_axi_rvalid -- Read valid -- s_axi_rready -- Read ready -- GPIO Signals -- gpio_io_i -- Channel 1 General purpose I/O in port -- gpio_io_o -- Channel 1 General purpose I/O out port -- gpio_io_t -- Channel 1 General purpose I/O -- TRI-STATE control port -- gpio2_io_i -- Channel 2 General purpose I/O in port -- gpio2_io_o -- Channel 2 General purpose I/O out port -- gpio2_io_t -- Channel 2 General purpose I/O -- TRI-STATE control port -- System Signals -- s_axi_aclk -- AXI Clock -- s_axi_aresetn -- AXI Reset -- ip2intc_irpt -- AXI GPIO Interrupt ------------------------------------------------------------------------------- entity axi_gpio is generic ( -- -- System Parameter C_FAMILY : string := "virtex7"; -- -- AXI Parameters C_S_AXI_ADDR_WIDTH : integer range 9 to 9 := 9; C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32; -- -- GPIO Parameter C_GPIO_WIDTH : integer range 1 to 32 := 32; C_GPIO2_WIDTH : integer range 1 to 32 := 32; C_ALL_INPUTS : integer range 0 to 1 := 0; C_ALL_INPUTS_2 : integer range 0 to 1 := 0; C_ALL_OUTPUTS : integer range 0 to 1 := 0;--2/28/2013 C_ALL_OUTPUTS_2 : integer range 0 to 1 := 0;--2/28/2013 C_INTERRUPT_PRESENT : integer range 0 to 1 := 0; C_DOUT_DEFAULT : std_logic_vector (31 downto 0) := X"0000_0000"; C_TRI_DEFAULT : std_logic_vector (31 downto 0) := X"FFFF_FFFF"; C_IS_DUAL : integer range 0 to 1 := 0; C_DOUT_DEFAULT_2 : std_logic_vector (31 downto 0) := X"0000_0000"; C_TRI_DEFAULT_2 : std_logic_vector (31 downto 0) := X"FFFF_FFFF" ); port ( -- AXI interface Signals -------------------------------------------------- s_axi_aclk : in std_logic; s_axi_aresetn : in std_logic; s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); s_axi_awvalid : in std_logic; s_axi_awready : out std_logic; s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); s_axi_wvalid : in std_logic; s_axi_wready : out std_logic; s_axi_bresp : out std_logic_vector(1 downto 0); s_axi_bvalid : out std_logic; s_axi_bready : in std_logic; s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); s_axi_arvalid : in std_logic; s_axi_arready : out std_logic; s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); s_axi_rresp : out std_logic_vector(1 downto 0); s_axi_rvalid : out std_logic; s_axi_rready : in std_logic; -- Interrupt--------------------------------------------------------------- ip2intc_irpt : out std_logic; -- GPIO Signals------------------------------------------------------------ gpio_io_i : in std_logic_vector(C_GPIO_WIDTH-1 downto 0); gpio_io_o : out std_logic_vector(C_GPIO_WIDTH-1 downto 0); gpio_io_t : out std_logic_vector(C_GPIO_WIDTH-1 downto 0); gpio2_io_i : in std_logic_vector(C_GPIO2_WIDTH-1 downto 0); gpio2_io_o : out std_logic_vector(C_GPIO2_WIDTH-1 downto 0); gpio2_io_t : out std_logic_vector(C_GPIO2_WIDTH-1 downto 0) ); ------------------------------------------------------------------------------- -- fan-out attributes for XST ------------------------------------------------------------------------------- attribute MAX_FANOUT : string; attribute MAX_FANOUT of s_axi_aclk : signal is "10000"; attribute MAX_FANOUT of s_axi_aresetn : signal is "10000"; ------------------------------------------------------------------------------- -- Attributes for MPD file ------------------------------------------------------------------------------- attribute IP_GROUP : string ; attribute IP_GROUP of axi_gpio : entity is "LOGICORE"; attribute SIGIS : string ; attribute SIGIS of s_axi_aclk : signal is "Clk"; attribute SIGIS of s_axi_aresetn : signal is "Rst"; attribute SIGIS of ip2intc_irpt : signal is "INTR_LEVEL_HIGH"; end entity axi_gpio; ------------------------------------------------------------------------------- -- Architecture Section ------------------------------------------------------------------------------- architecture imp of axi_gpio is -- Pragma Added to supress synth warnings attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes"; ------------------------------------------------------------------------------- -- constant added for webtalk information ------------------------------------------------------------------------------- --function chr(sl: std_logic) return character is -- variable c: character; -- begin -- case sl is -- when '0' => c:= '0'; -- when '1' => c:= '1'; -- when 'Z' => c:= 'Z'; -- when 'U' => c:= 'U'; -- when 'X' => c:= 'X'; -- when 'W' => c:= 'W'; -- when 'L' => c:= 'L'; -- when 'H' => c:= 'H'; -- when '-' => c:= '-'; -- end case; -- return c; -- end chr; -- --function str(slv: std_logic_vector) return string is -- variable result : string (1 to slv'length); -- variable r : integer; -- begin -- r := 1; -- for i in slv'range loop -- result(r) := chr(slv(i)); -- r := r + 1; -- end loop; -- return result; -- end str; type bo2na_type is array (boolean) of natural; -- boolean to --natural conversion constant bo2na : bo2na_type := (false => 0, true => 1); ------------------------------------------------------------------------------- -- Function Declarations ------------------------------------------------------------------------------- type BOOLEAN_ARRAY_TYPE is array(natural range <>) of boolean; ---------------------------------------------------------------------------- -- This function returns the number of elements that are true in -- a boolean array. ---------------------------------------------------------------------------- function num_set( ba : BOOLEAN_ARRAY_TYPE ) return natural is variable n : natural := 0; begin for i in ba'range loop n := n + bo2na(ba(i)); end loop; return n; end; ---------------------------------------------------------------------------- -- This function returns a num_ce integer array that is constructed by -- taking only those elements of superset num_ce integer array -- that will be defined by the current case. -- The superset num_ce array is given by parameter num_ce_by_ard. -- The current case the ard elements that will be used is given -- by parameter defined_ards. ---------------------------------------------------------------------------- function qual_ard_num_ce_array( defined_ards : BOOLEAN_ARRAY_TYPE; num_ce_by_ard : INTEGER_ARRAY_TYPE ) return INTEGER_ARRAY_TYPE is variable res : INTEGER_ARRAY_TYPE(num_set(defined_ards)-1 downto 0); variable i : natural := 0; variable j : natural := defined_ards'left; begin while i /= res'length loop -- coverage off while defined_ards(j) = false loop j := j+1; end loop; -- coverage on res(i) := num_ce_by_ard(j); i := i+1; j := j+1; end loop; return res; end; ---------------------------------------------------------------------------- -- This function returns a addr_range array that is constructed by -- taking only those elements of superset addr_range array -- that will be defined by the current case. -- The superset addr_range array is given by parameter addr_range_by_ard. -- The current case the ard elements that will be used is given -- by parameter defined_ards. ---------------------------------------------------------------------------- function qual_ard_addr_range_array( defined_ards : BOOLEAN_ARRAY_TYPE; addr_range_by_ard : SLV64_ARRAY_TYPE ) return SLV64_ARRAY_TYPE is variable res : SLV64_ARRAY_TYPE(0 to 2*num_set(defined_ards)-1); variable i : natural := 0; variable j : natural := defined_ards'left; begin while i /= res'length loop -- coverage off while defined_ards(j) = false loop j := j+1; end loop; -- coverage on res(i) := addr_range_by_ard(2*j); res(i+1) := addr_range_by_ard((2*j)+1); i := i+2; j := j+1; end loop; return res; end; function qual_ard_ce_valid( defined_ards : BOOLEAN_ARRAY_TYPE ) return std_logic_vector is variable res : std_logic_vector(0 to 31); begin res := (others => '0'); if defined_ards(defined_ards'right) then res(0 to 3) := "1111"; res(12) := '1'; res(13) := '1'; res(15) := '1'; else res(0 to 3) := "1111"; end if; return res; end; ---------------------------------------------------------------------------- -- This function returns the maximum width amongst the two GPIO Channels -- and if there is only one channel, it returns just the width of that -- channel. ---------------------------------------------------------------------------- function max_width( dual_channel : INTEGER; channel1_width : INTEGER; channel2_width : INTEGER ) return INTEGER is begin if (dual_channel = 0) then return channel1_width; else if (channel1_width > channel2_width) then return channel1_width; else return channel2_width; end if; end if; end; ------------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- constant C_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF"; constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0'); constant INTR_TYPE : integer := 5; constant INTR_BASEADDR : std_logic_vector(0 to 31):= X"00000100"; constant INTR_HIGHADDR : std_logic_vector(0 to 31):= X"000001FF"; constant GPIO_HIGHADDR : std_logic_vector(0 to 31):= X"0000000F"; constant MAX_GPIO_WIDTH : integer := max_width (C_IS_DUAL,C_GPIO_WIDTH,C_GPIO2_WIDTH); constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := qual_ard_addr_range_array( (true,C_INTERRUPT_PRESENT=1), (ZERO_ADDR_PAD & X"00000000", ZERO_ADDR_PAD & GPIO_HIGHADDR, ZERO_ADDR_PAD & INTR_BASEADDR, ZERO_ADDR_PAD & INTR_HIGHADDR ) ); constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := qual_ard_num_ce_array( (true,C_INTERRUPT_PRESENT=1), (4,16) ); constant ARD_CE_VALID : std_logic_vector(0 to 31) := qual_ard_ce_valid( (true,C_INTERRUPT_PRESENT=1) ); constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE(0 to 0+bo2na(C_IS_DUAL=1)) := (others => 5); constant C_USE_WSTRB : integer := 0; constant C_DPHASE_TIMEOUT : integer := 8; ------------------------------------------------------------------------------- -- Signal and Type Declarations ------------------------------------------------------------------------------- signal ip2bus_intrevent : std_logic_vector(0 to 1); signal GPIO_xferAck_i : std_logic; signal Bus2IP_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal Bus2IP1_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal Bus2IP2_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); -- IPIC Used Signals signal ip2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal bus2ip_addr : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1); signal bus2ip_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal bus2ip_rnw : std_logic; signal bus2ip_cs : std_logic_vector(0 to 0 + bo2na (C_INTERRUPT_PRESENT=1)); signal bus2ip_rdce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1); signal bus2ip_wrce : std_logic_vector(0 to calc_num_ce(ARD_NUM_CE_ARRAY)-1); signal Intrpt_bus2ip_rdce : std_logic_vector(0 to 15); signal Intrpt_bus2ip_wrce : std_logic_vector(0 to 15); signal intr_wr_ce_or_reduce : std_logic; signal intr_rd_ce_or_reduce : std_logic; signal ip2Bus_RdAck_intr_reg_hole : std_logic; signal ip2Bus_RdAck_intr_reg_hole_d1 : std_logic; signal ip2Bus_WrAck_intr_reg_hole : std_logic; signal ip2Bus_WrAck_intr_reg_hole_d1 : std_logic; signal bus2ip_be : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH / 8) - 1); signal bus2ip_clk : std_logic; signal bus2ip_reset : std_logic; signal bus2ip_resetn : std_logic; signal intr2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal intr2bus_wrack : std_logic; signal intr2bus_rdack : std_logic; signal intr2bus_error : std_logic; signal ip2bus_data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal ip2bus_data_i_D1 : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1); signal ip2bus_wrack_i : std_logic; signal ip2bus_wrack_i_D1 : std_logic; signal ip2bus_rdack_i : std_logic; signal ip2bus_rdack_i_D1 : std_logic; signal ip2bus_error_i : std_logic; signal IP2INTC_Irpt_i : std_logic; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- begin -- architecture IMP AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0_4.axi_lite_ipif generic map ( C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH, C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH, C_S_AXI_MIN_SIZE => C_AXI_MIN_SIZE, C_USE_WSTRB => C_USE_WSTRB, C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT, C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY, C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY, C_FAMILY => C_FAMILY ) port map ( S_AXI_ACLK => s_axi_aclk, S_AXI_ARESETN => s_axi_aresetn, S_AXI_AWADDR => s_axi_awaddr, S_AXI_AWVALID => s_axi_awvalid, S_AXI_AWREADY => s_axi_awready, S_AXI_WDATA => s_axi_wdata, S_AXI_WSTRB => s_axi_wstrb, S_AXI_WVALID => s_axi_wvalid, S_AXI_WREADY => s_axi_wready, S_AXI_BRESP => s_axi_bresp, S_AXI_BVALID => s_axi_bvalid, S_AXI_BREADY => s_axi_bready, S_AXI_ARADDR => s_axi_araddr, S_AXI_ARVALID => s_axi_arvalid, S_AXI_ARREADY => s_axi_arready, S_AXI_RDATA => s_axi_rdata, S_AXI_RRESP => s_axi_rresp, S_AXI_RVALID => s_axi_rvalid, S_AXI_RREADY => s_axi_rready, -- IP Interconnect (IPIC) port signals Bus2IP_Clk => bus2ip_clk, Bus2IP_Resetn => bus2ip_resetn, IP2Bus_Data => ip2bus_data_i_D1, IP2Bus_WrAck => ip2bus_wrack_i_D1, IP2Bus_RdAck => ip2bus_rdack_i_D1, --IP2Bus_WrAck => ip2bus_wrack_i, --IP2Bus_RdAck => ip2bus_rdack_i, IP2Bus_Error => ip2bus_error_i, Bus2IP_Addr => bus2ip_addr, Bus2IP_Data => bus2ip_data, Bus2IP_RNW => bus2ip_rnw, Bus2IP_BE => bus2ip_be, Bus2IP_CS => bus2ip_cs, Bus2IP_RdCE => bus2ip_rdce, Bus2IP_WrCE => bus2ip_wrce ); ip2bus_data_i <= intr2bus_data or ip2bus_data; ip2bus_wrack_i <= intr2bus_wrack or (GPIO_xferAck_i and not(bus2ip_rnw)) or ip2Bus_WrAck_intr_reg_hole;-- Holes in Address range ip2bus_rdack_i <= intr2bus_rdack or (GPIO_xferAck_i and bus2ip_rnw) or ip2Bus_RdAck_intr_reg_hole; -- Holes in Address range I_WRACK_RDACK_DELAYS: process(Bus2IP_Clk) is begin if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then if (bus2ip_reset = '1') then ip2bus_wrack_i_D1 <= '0'; ip2bus_rdack_i_D1 <= '0'; ip2bus_data_i_D1 <= (others => '0'); else ip2bus_wrack_i_D1 <= ip2bus_wrack_i; ip2bus_rdack_i_D1 <= ip2bus_rdack_i; ip2bus_data_i_D1 <= ip2bus_data_i; end if; end if; end process I_WRACK_RDACK_DELAYS; ip2bus_error_i <= intr2bus_error; ---------------------- --REG_RESET_FROM_IPIF: convert active low to active hig reset to rest of -- the core. ---------------------- REG_RESET_FROM_IPIF: process (s_axi_aclk) is begin if(s_axi_aclk'event and s_axi_aclk = '1') then bus2ip_reset <= not(bus2ip_resetn); end if; end process REG_RESET_FROM_IPIF; --------------------------------------------------------------------------- -- Interrupts --------------------------------------------------------------------------- INTR_CTRLR_GEN : if (C_INTERRUPT_PRESENT = 1) generate constant NUM_IPIF_IRPT_SRC : natural := 1; constant NUM_CE : integer := 16; signal errack_reserved : std_logic_vector(0 to 1); signal ipif_lvl_interrupts : std_logic_vector(0 to NUM_IPIF_IRPT_SRC-1); begin ipif_lvl_interrupts <= (others => '0'); errack_reserved <= (others => '0'); --- Addr 0X11c, 0X120, 0X128 valid addresses, remaining are holes Intrpt_bus2ip_rdce <= "0000000" & bus2ip_rdce(11) & bus2ip_rdce(12) & '0' & bus2ip_rdce(14) & "00000"; Intrpt_bus2ip_wrce <= "0000000" & bus2ip_wrce(11) & bus2ip_wrce(12) & '0' & bus2ip_wrce(14) & "00000"; intr_rd_ce_or_reduce <= or_reduce(bus2ip_rdce(4 to 10)) or Bus2IP_RdCE(13) or or_reduce(Bus2IP_RdCE(15 to 19)); intr_wr_ce_or_reduce <= or_reduce(bus2ip_wrce(4 to 10)) or bus2ip_wrce(13) or or_reduce(bus2ip_wrce(15 to 19)); I_READ_ACK_INTR_HOLES: process(Bus2IP_Clk) is begin if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then if (bus2ip_reset = '1') then ip2Bus_RdAck_intr_reg_hole <= '0'; ip2Bus_RdAck_intr_reg_hole_d1 <= '0'; else ip2Bus_RdAck_intr_reg_hole_d1 <= intr_rd_ce_or_reduce; ip2Bus_RdAck_intr_reg_hole <= intr_rd_ce_or_reduce and (not ip2Bus_RdAck_intr_reg_hole_d1); end if; end if; end process I_READ_ACK_INTR_HOLES; I_WRITE_ACK_INTR_HOLES: process(Bus2IP_Clk) is begin if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then if (bus2ip_reset = '1') then ip2Bus_WrAck_intr_reg_hole <= '0'; ip2Bus_WrAck_intr_reg_hole_d1 <= '0'; else ip2Bus_WrAck_intr_reg_hole_d1 <= intr_wr_ce_or_reduce; ip2Bus_WrAck_intr_reg_hole <= intr_wr_ce_or_reduce and (not ip2Bus_WrAck_intr_reg_hole_d1); end if; end if; end process I_WRITE_ACK_INTR_HOLES; INTERRUPT_CONTROL_I : entity interrupt_control_v3_1_4.interrupt_control generic map ( C_NUM_CE => NUM_CE, C_NUM_IPIF_IRPT_SRC => NUM_IPIF_IRPT_SRC, C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY, C_INCLUDE_DEV_PENCODER => false, C_INCLUDE_DEV_ISC => false, C_IPIF_DWIDTH => C_S_AXI_DATA_WIDTH ) port map ( -- Inputs From the IPIF Bus Bus2IP_Clk => Bus2IP_Clk, Bus2IP_Reset => bus2ip_reset, Bus2IP_Data => bus2ip_data, Bus2IP_BE => bus2ip_be, Interrupt_RdCE => Intrpt_bus2ip_rdce, Interrupt_WrCE => Intrpt_bus2ip_wrce, -- Interrupt inputs from the IPIF sources that will -- get registered in this design IPIF_Reg_Interrupts => errack_reserved, -- Level Interrupt inputs from the IPIF sources IPIF_Lvl_Interrupts => ipif_lvl_interrupts, -- Inputs from the IP Interface IP2Bus_IntrEvent => ip2bus_intrevent(IP_INTR_MODE_ARRAY'range), -- Final Device Interrupt Output Intr2Bus_DevIntr => IP2INTC_Irpt_i, -- Status Reply Outputs to the Bus Intr2Bus_DBus => intr2bus_data, Intr2Bus_WrAck => intr2bus_wrack, Intr2Bus_RdAck => intr2bus_rdack, Intr2Bus_Error => intr2bus_error, Intr2Bus_Retry => open, Intr2Bus_ToutSup => open ); -- registering interrupt I_INTR_DELAY: process(Bus2IP_Clk) is begin if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then if (bus2ip_reset = '1') then ip2intc_irpt <= '0'; else ip2intc_irpt <= IP2INTC_Irpt_i; end if; end if; end process I_INTR_DELAY; end generate INTR_CTRLR_GEN; ----------------------------------------------------------------------- -- Assigning the intr2bus signal to zero's when interrupt is not -- present ----------------------------------------------------------------------- REMOVE_INTERRUPT : if (C_INTERRUPT_PRESENT = 0) generate intr2bus_data <= (others => '0'); ip2intc_irpt <= '0'; intr2bus_error <= '0'; intr2bus_rdack <= '0'; intr2bus_wrack <= '0'; ip2Bus_WrAck_intr_reg_hole <= '0'; ip2Bus_RdAck_intr_reg_hole <= '0'; end generate REMOVE_INTERRUPT; gpio_core_1 : entity axi_gpio_v2_0_15.gpio_core generic map ( C_DW => C_S_AXI_DATA_WIDTH, C_AW => C_S_AXI_ADDR_WIDTH, C_GPIO_WIDTH => C_GPIO_WIDTH, C_GPIO2_WIDTH => C_GPIO2_WIDTH, C_MAX_GPIO_WIDTH => MAX_GPIO_WIDTH, C_INTERRUPT_PRESENT => C_INTERRUPT_PRESENT, C_DOUT_DEFAULT => C_DOUT_DEFAULT, C_TRI_DEFAULT => C_TRI_DEFAULT, C_IS_DUAL => C_IS_DUAL, C_ALL_OUTPUTS => C_ALL_OUTPUTS, C_ALL_INPUTS => C_ALL_INPUTS, C_ALL_INPUTS_2 => C_ALL_INPUTS_2, C_ALL_OUTPUTS_2 => C_ALL_OUTPUTS_2, C_DOUT_DEFAULT_2 => C_DOUT_DEFAULT_2, C_TRI_DEFAULT_2 => C_TRI_DEFAULT_2, C_FAMILY => C_FAMILY ) port map ( Clk => Bus2IP_Clk, Rst => bus2ip_reset, ABus_Reg => Bus2IP_Addr, BE_Reg => Bus2IP_BE(0 to C_S_AXI_DATA_WIDTH/8-1), DBus_Reg => Bus2IP_Data_i(0 to MAX_GPIO_WIDTH-1), RNW_Reg => Bus2IP_RNW, GPIO_DBus => IP2Bus_Data(0 to C_S_AXI_DATA_WIDTH-1), GPIO_xferAck => GPIO_xferAck_i, GPIO_Select => bus2ip_cs(0), GPIO_intr => ip2bus_intrevent(0), GPIO2_intr => ip2bus_intrevent(1), GPIO_IO_I => gpio_io_i, GPIO_IO_O => gpio_io_o, GPIO_IO_T => gpio_io_t, GPIO2_IO_I => gpio2_io_i, GPIO2_IO_O => gpio2_io_o, GPIO2_IO_T => gpio2_io_t ); Bus2IP_Data_i <= Bus2IP1_Data_i when bus2ip_cs(0) = '1' and bus2ip_addr (5) = '0'else Bus2IP2_Data_i; BUS_CONV_ch1 : for i in 0 to C_GPIO_WIDTH-1 generate Bus2IP1_Data_i(i) <= Bus2IP_Data(i+ C_S_AXI_DATA_WIDTH-C_GPIO_WIDTH); end generate BUS_CONV_ch1; BUS_CONV_ch2 : for i in 0 to C_GPIO2_WIDTH-1 generate Bus2IP2_Data_i(i) <= Bus2IP_Data(i+ C_S_AXI_DATA_WIDTH-C_GPIO2_WIDTH); end generate BUS_CONV_ch2; end architecture imp;

mit

MarkBlanco/FPGA_Sandbox

RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_6/impl/ip/tmp.srcs/sources_1/ip/convolve_kernel_ap_fmul_6_max_dsp_32/synth/convolve_kernel_ap_fmul_6_max_dsp_32.vhd

3

12822

-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:floating_point:7.1 -- IP Revision: 4 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY floating_point_v7_1_4; USE floating_point_v7_1_4.floating_point_v7_1_4; ENTITY convolve_kernel_ap_fmul_6_max_dsp_32 IS PORT ( aclk : IN STD_LOGIC; aclken : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_b_tvalid : IN STD_LOGIC; s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_result_tvalid : OUT STD_LOGIC; m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END convolve_kernel_ap_fmul_6_max_dsp_32; ARCHITECTURE convolve_kernel_ap_fmul_6_max_dsp_32_arch OF convolve_kernel_ap_fmul_6_max_dsp_32 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF convolve_kernel_ap_fmul_6_max_dsp_32_arch: ARCHITECTURE IS "yes"; COMPONENT floating_point_v7_1_4 IS GENERIC ( C_XDEVICEFAMILY : STRING; C_HAS_ADD : INTEGER; C_HAS_SUBTRACT : INTEGER; C_HAS_MULTIPLY : INTEGER; C_HAS_DIVIDE : INTEGER; C_HAS_SQRT : INTEGER; C_HAS_COMPARE : INTEGER; C_HAS_FIX_TO_FLT : INTEGER; C_HAS_FLT_TO_FIX : INTEGER; C_HAS_FLT_TO_FLT : INTEGER; C_HAS_RECIP : INTEGER; C_HAS_RECIP_SQRT : INTEGER; C_HAS_ABSOLUTE : INTEGER; C_HAS_LOGARITHM : INTEGER; C_HAS_EXPONENTIAL : INTEGER; C_HAS_FMA : INTEGER; C_HAS_FMS : INTEGER; C_HAS_ACCUMULATOR_A : INTEGER; C_HAS_ACCUMULATOR_S : INTEGER; C_A_WIDTH : INTEGER; C_A_FRACTION_WIDTH : INTEGER; C_B_WIDTH : INTEGER; C_B_FRACTION_WIDTH : INTEGER; C_C_WIDTH : INTEGER; C_C_FRACTION_WIDTH : INTEGER; C_RESULT_WIDTH : INTEGER; C_RESULT_FRACTION_WIDTH : INTEGER; C_COMPARE_OPERATION : INTEGER; C_LATENCY : INTEGER; C_OPTIMIZATION : INTEGER; C_MULT_USAGE : INTEGER; C_BRAM_USAGE : INTEGER; C_RATE : INTEGER; C_ACCUM_INPUT_MSB : INTEGER; C_ACCUM_MSB : INTEGER; C_ACCUM_LSB : INTEGER; C_HAS_UNDERFLOW : INTEGER; C_HAS_OVERFLOW : INTEGER; C_HAS_INVALID_OP : INTEGER; C_HAS_DIVIDE_BY_ZERO : INTEGER; C_HAS_ACCUM_OVERFLOW : INTEGER; C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER; C_HAS_ACLKEN : INTEGER; C_HAS_ARESETN : INTEGER; C_THROTTLE_SCHEME : INTEGER; C_HAS_A_TUSER : INTEGER; C_HAS_A_TLAST : INTEGER; C_HAS_B : INTEGER; C_HAS_B_TUSER : INTEGER; C_HAS_B_TLAST : INTEGER; C_HAS_C : INTEGER; C_HAS_C_TUSER : INTEGER; C_HAS_C_TLAST : INTEGER; C_HAS_OPERATION : INTEGER; C_HAS_OPERATION_TUSER : INTEGER; C_HAS_OPERATION_TLAST : INTEGER; C_HAS_RESULT_TUSER : INTEGER; C_HAS_RESULT_TLAST : INTEGER; C_TLAST_RESOLUTION : INTEGER; C_A_TDATA_WIDTH : INTEGER; C_A_TUSER_WIDTH : INTEGER; C_B_TDATA_WIDTH : INTEGER; C_B_TUSER_WIDTH : INTEGER; C_C_TDATA_WIDTH : INTEGER; C_C_TUSER_WIDTH : INTEGER; C_OPERATION_TDATA_WIDTH : INTEGER; C_OPERATION_TUSER_WIDTH : INTEGER; C_RESULT_TDATA_WIDTH : INTEGER; C_RESULT_TUSER_WIDTH : INTEGER; C_FIXED_DATA_UNSIGNED : INTEGER ); PORT ( aclk : IN STD_LOGIC; aclken : IN STD_LOGIC; aresetn : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tready : OUT STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_a_tlast : IN STD_LOGIC; s_axis_b_tvalid : IN STD_LOGIC; s_axis_b_tready : OUT STD_LOGIC; s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_b_tlast : IN STD_LOGIC; s_axis_c_tvalid : IN STD_LOGIC; s_axis_c_tready : OUT STD_LOGIC; s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_c_tlast : IN STD_LOGIC; s_axis_operation_tvalid : IN STD_LOGIC; s_axis_operation_tready : OUT STD_LOGIC; s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_operation_tlast : IN STD_LOGIC; m_axis_result_tvalid : OUT STD_LOGIC; m_axis_result_tready : IN STD_LOGIC; m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_result_tlast : OUT STD_LOGIC ); END COMPONENT floating_point_v7_1_4; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF convolve_kernel_ap_fmul_6_max_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_4,Vivado 2017.2"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF convolve_kernel_ap_fmul_6_max_dsp_32_arch : ARCHITECTURE IS "convolve_kernel_ap_fmul_6_max_dsp_32,floating_point_v7_1_4,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF convolve_kernel_ap_fmul_6_max_dsp_32_arch: ARCHITECTURE IS "convolve_kernel_ap_fmul_6_max_dsp_32,floating_point_v7_1_4,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=" & "0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=6,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_" & "THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK"; ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA"; BEGIN U0 : floating_point_v7_1_4 GENERIC MAP ( C_XDEVICEFAMILY => "zynq", C_HAS_ADD => 0, C_HAS_SUBTRACT => 0, C_HAS_MULTIPLY => 1, C_HAS_DIVIDE => 0, C_HAS_SQRT => 0, C_HAS_COMPARE => 0, C_HAS_FIX_TO_FLT => 0, C_HAS_FLT_TO_FIX => 0, C_HAS_FLT_TO_FLT => 0, C_HAS_RECIP => 0, C_HAS_RECIP_SQRT => 0, C_HAS_ABSOLUTE => 0, C_HAS_LOGARITHM => 0, C_HAS_EXPONENTIAL => 0, C_HAS_FMA => 0, C_HAS_FMS => 0, C_HAS_ACCUMULATOR_A => 0, C_HAS_ACCUMULATOR_S => 0, C_A_WIDTH => 32, C_A_FRACTION_WIDTH => 24, C_B_WIDTH => 32, C_B_FRACTION_WIDTH => 24, C_C_WIDTH => 32, C_C_FRACTION_WIDTH => 24, C_RESULT_WIDTH => 32, C_RESULT_FRACTION_WIDTH => 24, C_COMPARE_OPERATION => 8, C_LATENCY => 6, C_OPTIMIZATION => 1, C_MULT_USAGE => 3, C_BRAM_USAGE => 0, C_RATE => 1, C_ACCUM_INPUT_MSB => 32, C_ACCUM_MSB => 32, C_ACCUM_LSB => -31, C_HAS_UNDERFLOW => 0, C_HAS_OVERFLOW => 0, C_HAS_INVALID_OP => 0, C_HAS_DIVIDE_BY_ZERO => 0, C_HAS_ACCUM_OVERFLOW => 0, C_HAS_ACCUM_INPUT_OVERFLOW => 0, C_HAS_ACLKEN => 1, C_HAS_ARESETN => 0, C_THROTTLE_SCHEME => 3, C_HAS_A_TUSER => 0, C_HAS_A_TLAST => 0, C_HAS_B => 1, C_HAS_B_TUSER => 0, C_HAS_B_TLAST => 0, C_HAS_C => 0, C_HAS_C_TUSER => 0, C_HAS_C_TLAST => 0, C_HAS_OPERATION => 0, C_HAS_OPERATION_TUSER => 0, C_HAS_OPERATION_TLAST => 0, C_HAS_RESULT_TUSER => 0, C_HAS_RESULT_TLAST => 0, C_TLAST_RESOLUTION => 0, C_A_TDATA_WIDTH => 32, C_A_TUSER_WIDTH => 1, C_B_TDATA_WIDTH => 32, C_B_TUSER_WIDTH => 1, C_C_TDATA_WIDTH => 32, C_C_TUSER_WIDTH => 1, C_OPERATION_TDATA_WIDTH => 8, C_OPERATION_TUSER_WIDTH => 1, C_RESULT_TDATA_WIDTH => 32, C_RESULT_TUSER_WIDTH => 1, C_FIXED_DATA_UNSIGNED => 0 ) PORT MAP ( aclk => aclk, aclken => aclken, aresetn => '1', s_axis_a_tvalid => s_axis_a_tvalid, s_axis_a_tdata => s_axis_a_tdata, s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_a_tlast => '0', s_axis_b_tvalid => s_axis_b_tvalid, s_axis_b_tdata => s_axis_b_tdata, s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_b_tlast => '0', s_axis_c_tvalid => '0', s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_c_tlast => '0', s_axis_operation_tvalid => '0', s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_operation_tlast => '0', m_axis_result_tvalid => m_axis_result_tvalid, m_axis_result_tready => '0', m_axis_result_tdata => m_axis_result_tdata ); END convolve_kernel_ap_fmul_6_max_dsp_32_arch;

mit

kloboves/sicxe

vhdl/seg7.vhd

1

6838

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; -- Data bit connections on display: -- -- --0-- -- | | -- 1 2 -- | | -- --3-- -- | | -- 4 5 -- | | -- --6-- [7] (dot) entity seg7 is Port ( clock_i : in std_logic; reset_i : in std_logic; -- special display modes error_i : in std_logic; stop_i : in std_logic; -- register access data_i : in std_logic_vector(7 downto 0); write_mode_i : in std_logic; write_raw_i : std_logic_vector(3 downto 0); write_hex_i : std_logic_vector(1 downto 0); -- display output cathode_o : out std_logic_vector(7 downto 0); anode_o : out std_logic_vector(3 downto 0) ); end seg7; architecture behavioral of seg7 is -- registers signal reg_mode : std_logic_vector(1 downto 0); signal reg_raw : std_logic_vector(31 downto 0); signal reg_hex : std_logic_vector(15 downto 0); -- delay counter signal delay_counter : std_logic_vector(14 downto 0); signal delay_counter_done : std_logic; -- current digit signal digit_counter : std_logic_vector(1 downto 0); signal digit_raw : std_logic_vector(7 downto 0); signal digit_hex : std_logic_vector(3 downto 0); -- output signal cathode : std_logic_vector(7 downto 0); signal anode : std_logic_vector(3 downto 0); signal cathode_delay1 : std_logic_vector(7 downto 0); signal anode_delay1 : std_logic_vector(3 downto 0); begin -- registers reg_proc : process(clock_i) begin if (rising_edge(clock_i)) then if (reset_i = '1') then reg_mode <= (others => '0'); reg_raw <= (others => '0'); reg_hex <= (others => '0'); else reg_mode <= reg_mode; reg_raw <= reg_raw; reg_hex <= reg_hex; if (write_mode_i = '1') then reg_mode <= data_i(1 downto 0); end if; if (write_raw_i(3) = '1') then reg_raw(31 downto 24) <= data_i; end if; if (write_raw_i(2) = '1') then reg_raw(23 downto 16) <= data_i; end if; if (write_raw_i(1) = '1') then reg_raw(15 downto 8) <= data_i; end if; if (write_raw_i(0) = '1') then reg_raw(7 downto 0) <= data_i; end if; if (write_hex_i(1) = '1') then reg_hex(15 downto 8) <= data_i; end if; if (write_hex_i(0) = '1') then reg_hex(7 downto 0) <= data_i; end if; end if; end if; end process; -- delay counter delay_counter_proc : process(clock_i) begin if (rising_edge(clock_i)) then if (reset_i = '1') then delay_counter <= (others => '0'); else if (delay_counter = "111111111111111") then delay_counter <= (others => '0'); else delay_counter <= delay_counter + 1; end if; end if; end if; end process; delay_counter_done_proc : process(delay_counter) begin if (delay_counter = "111111111111111") then delay_counter_done <= '1'; else delay_counter_done <= '0'; end if; end process; -- current digit digit_counter_proc : process(clock_i) begin if (rising_edge(clock_i)) then if (reset_i = '1') then digit_counter <= (others => '0'); else if (delay_counter_done = '1') then digit_counter <= digit_counter + 1; else digit_counter <= digit_counter; end if; end if; end if; end process; digit_proc : process(digit_counter, reg_raw, reg_hex) begin case (digit_counter) is when "00" => digit_raw <= reg_raw(7 downto 0); digit_hex <= reg_hex(3 downto 0); when "01" => digit_raw <= reg_raw(15 downto 8); digit_hex <= reg_hex(7 downto 4); when "10" => digit_raw <= reg_raw(23 downto 16); digit_hex <= reg_hex(11 downto 8); when "11" => digit_raw <= reg_raw(31 downto 24); digit_hex <= reg_hex(15 downto 12); when others => digit_raw <= (others => '0'); digit_hex <= (others => '0'); end case; end process; -- output cathode_o <= cathode_delay1; anode_o <= anode_delay1; delay_proc : process(clock_i) begin if (rising_edge(clock_i)) then if (reset_i = '1') then cathode_delay1 <= (others => '0'); anode_delay1 <= (others => '1'); else cathode_delay1 <= cathode; anode_delay1 <= anode; end if; end if; end process; anode_proc : process(digit_counter) begin case (digit_counter) is when "00" => anode <= "1110"; when "01" => anode <= "1101"; when "10" => anode <= "1011"; when "11" => anode <= "0111"; when others => anode <= (others => '1'); end case; end process; cathode_proc : process(error_i, stop_i, digit_counter, reg_mode, digit_raw, digit_hex) begin if (error_i = '1') then case (digit_counter) is when "00" => cathode <= "11111111"; -- blank when "01" => cathode <= "11100111"; -- r when "10" => cathode <= "11100111"; -- r when "11" => cathode <= "10100100"; -- E when others => cathode <= (others => '1'); end case; elsif (stop_i = '1') then case (digit_counter) is when "00" => cathode <= "11100000"; -- P when "01" => cathode <= "10001000"; -- O when "10" => cathode <= "10100101"; -- t when "11" => cathode <= "10010100"; -- S when others => cathode <= (others => '1'); end case; else if (reg_mode = "00") then cathode <= not digit_raw; else if ((reg_mode = "01" and (digit_counter = "10" or digit_counter = "11")) or (reg_mode = "10" and (digit_counter = "00" or digit_counter = "01"))) then cathode <= not digit_raw; else case digit_hex is when "0000" => cathode <= "10001000"; when "0001" => cathode <= "11011011"; when "0010" => cathode <= "10100010"; when "0011" => cathode <= "10010010"; when "0100" => cathode <= "11010001"; when "0101" => cathode <= "10010100"; when "0110" => cathode <= "10000100"; when "0111" => cathode <= "11011010"; when "1000" => cathode <= "10000000"; when "1001" => cathode <= "10010000"; when "1010" => cathode <= "11000000"; when "1011" => cathode <= "10000101"; when "1100" => cathode <= "10101100"; when "1101" => cathode <= "10000011"; when "1110" => cathode <= "10100100"; when "1111" => cathode <= "11100100"; when others => cathode <= (others => '1'); end case; end if; end if; end if; end process; end behavioral;

mit

kloboves/sicxe

vhdl/gio_device.vhd

1

4795

library ieee; use ieee.std_logic_1164.all; entity gio_device is Port ( clock_i : in std_logic; reset_i : in std_logic; -- device access switches_data_o : out std_logic_vector(7 downto 0); buttons_data_o : out std_logic_vector(7 downto 0); event_o : out std_logic; data_i : in std_logic_vector(7 downto 0); write_leds_i : std_logic; -- physical connections leds_o : out std_logic_vector(7 downto 0); switches_i : in std_logic_vector(7 downto 0); buttons_i : in std_logic_vector(1 downto 0) ); end gio_device; architecture behavioral of gio_device is component debouncer Port ( clock_i : in std_logic; reset_i : in std_logic; input_i : in std_logic; output_o : out std_logic; change_on_o : out std_logic; change_off_o : out std_logic ); end component; -- leds signal reg_leds : std_logic_vector(7 downto 0); -- switches and buttons signal switches : std_logic_vector(7 downto 0); signal buttons : std_logic_vector(1 downto 0); -- events signal switches_event1 : std_logic_vector(7 downto 0); signal switches_event2 : std_logic_vector(7 downto 0); signal buttons_event1 : std_logic_vector(1 downto 0); signal buttons_event2 : std_logic_vector(1 downto 0); begin leds_proc : process(clock_i) begin if (rising_edge(clock_i)) then if (reset_i = '1') then reg_leds <= (others => '0'); else if (write_leds_i = '1') then reg_leds <= data_i; else reg_leds <= reg_leds; end if; end if; end if; end process; leds_o <= reg_leds; switches_data_o <= switches; buttons_data_o <= "000000" & buttons; event_o <= switches_event1(0) or switches_event1(1) or switches_event1(2) or switches_event1(3) or switches_event1(4) or switches_event1(5) or switches_event1(6) or switches_event1(7) or switches_event2(0) or switches_event2(1) or switches_event2(2) or switches_event2(3) or switches_event2(4) or switches_event2(5) or switches_event2(6) or switches_event2(7) or buttons_event1(0) or buttons_event1(1) or buttons_event2(0) or buttons_event2(1); sw0_debounce_cmpt : debouncer port map ( clock_i => clock_i, reset_i => reset_i, input_i => switches_i(0), output_o => switches(0), change_on_o => switches_event1(0), change_off_o => switches_event2(0) ); sw1_debounce_cmpt : debouncer port map ( clock_i => clock_i, reset_i => reset_i, input_i => switches_i(1), output_o => switches(1), change_on_o => switches_event1(1), change_off_o => switches_event2(1) ); sw2_debounce_cmpt : debouncer port map ( clock_i => clock_i, reset_i => reset_i, input_i => switches_i(2), output_o => switches(2), change_on_o => switches_event1(2), change_off_o => switches_event2(2) ); sw3_debounce_cmpt : debouncer port map ( clock_i => clock_i, reset_i => reset_i, input_i => switches_i(3), output_o => switches(3), change_on_o => switches_event1(3), change_off_o => switches_event2(3) ); sw4_debounce_cmpt : debouncer port map ( clock_i => clock_i, reset_i => reset_i, input_i => switches_i(4), output_o => switches(4), change_on_o => switches_event1(4), change_off_o => switches_event2(4) ); sw5_debounce_cmpt : debouncer port map ( clock_i => clock_i, reset_i => reset_i, input_i => switches_i(5), output_o => switches(5), change_on_o => switches_event1(5), change_off_o => switches_event2(5) ); sw6_debounce_cmpt : debouncer port map ( clock_i => clock_i, reset_i => reset_i, input_i => switches_i(6), output_o => switches(6), change_on_o => switches_event1(6), change_off_o => switches_event2(6) ); sw7_debounce_cmpt : debouncer port map ( clock_i => clock_i, reset_i => reset_i, input_i => switches_i(7), output_o => switches(7), change_on_o => switches_event1(7), change_off_o => switches_event2(7) ); btn0_debounce_cmpt : debouncer port map ( clock_i => clock_i, reset_i => reset_i, input_i => buttons_i(0), output_o => buttons(0), change_on_o => buttons_event1(0), change_off_o => buttons_event2(0) ); btn1_debounce_cmpt : debouncer port map ( clock_i => clock_i, reset_i => reset_i, input_i => buttons_i(1), output_o => buttons(1), change_on_o => buttons_event1(1), change_off_o => buttons_event2(1) ); end behavioral;

mit

nathdwek/vhdltree

test/dummy_project/.vhd

7

--test

mit

MarkBlanco/FPGA_Sandbox

RecComp/Lab3/ip_repo/zed_audio_ctrl/zed_audio_ctrl.srcs/sources_1/imports/i2s_audio/slave_attachment.vhd

7

21369

------------------------------------------------------------------- -- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. -- -- -- -- This file contains confidential and proprietary information -- -- of Xilinx, Inc. and is protected under U.S. and -- -- international copyright and other intellectual property -- -- laws. -- -- -- -- DISCLAIMER -- -- This disclaimer is not a license and does not grant any -- -- rights to the materials distributed herewith. Except as -- -- otherwise provided in a valid license issued to you by -- -- Xilinx, and to the maximum extent permitted by applicable -- -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- -- (2) Xilinx shall not be liable (whether in contract or tort, -- -- including negligence, or under any other theory of -- -- liability) for any loss or damage of any kind or nature -- -- related to, arising under or in connection with these -- -- materials, including for any direct, or any indirect, -- -- special, incidental, or consequential loss or damage -- -- (including loss of data, profits, goodwill, or any type of -- -- loss or damage suffered as a result of any action brought -- -- by a third party) even if such damage or loss was -- -- reasonably foreseeable or Xilinx had been advised of the -- -- possibility of the same. -- -- -- -- CRITICAL APPLICATIONS -- -- Xilinx products are not designed or intended to be fail- -- -- safe, or for use in any application requiring fail-safe -- -- performance, such as life-support or safety devices or -- -- systems, Class III medical devices, nuclear facilities, -- -- applications related to the deployment of airbags, or any -- -- other applications that could lead to death, personal -- -- injury, or severe property or environmental damage -- -- (individually and collectively, "Critical -- -- Applications"). Customer assumes the sole risk and -- -- liability of any use of Xilinx products in Critical -- -- Applications, subject only to applicable laws and -- -- regulations governing limitations on product liability. -- -- -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- -- PART OF THIS FILE AT ALL TIMES. -- ------------------------------------------------------------------- -- ************************************************************************ -- ------------------------------------------------------------------------------- -- Filename: slave_attachment.vhd -- Version: v1.01.a -- Description: AXI slave attachment supporting single transfers ------------------------------------------------------------------------------- -- Structure: This section shows the hierarchical structure of axi_lite_ipif. -- -- --axi_lite_ipif.vhd -- --slave_attachment.vhd -- --address_decoder.vhd ------------------------------------------------------------------------------- -- Author: BSB -- -- History: -- -- BSB 05/20/10 -- First version -- ~~~~~~ -- - Created the first version v1.00.a -- ^^^^^^ -- ~~~~~~ -- SK 06/09/10 -- updated to reduce the utilization -- 1. State machine is re-designed -- 2. R and B channels are registered and AW, AR, W channels are non-registered -- 3. Address decoding is done only for the required address bits and not complete -- 32 bits -- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux -- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg -- function. -- ^^^^^^ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- access_cs machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_cmb" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_misc.all; use work.common_types.all; ------------------------------------------------------------------------------- -- Definition of Generics ------------------------------------------------------------------------------- -- C_IPIF_ABUS_WIDTH -- IPIF Address bus width -- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width -- C_S_AXI_MIN_SIZE -- Minimum address range of the IP -- C_USE_WSTRB -- Use write strobs or not -- C_DPHASE_TIMEOUT -- Data phase time out counter -- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range -- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range -- C_FAMILY -- Target FPGA family ------------------------------------------------------------------------------- -- Definition of Ports ------------------------------------------------------------------------------- -- S_AXI_ACLK -- AXI Clock -- S_AXI_ARESET -- AXI Reset -- S_AXI_AWADDR -- AXI Write address -- S_AXI_AWVALID -- Write address valid -- S_AXI_AWREADY -- Write address ready -- S_AXI_WDATA -- Write data -- S_AXI_WSTRB -- Write strobes -- S_AXI_WVALID -- Write valid -- S_AXI_WREADY -- Write ready -- S_AXI_BRESP -- Write response -- S_AXI_BVALID -- Write response valid -- S_AXI_BREADY -- Response ready -- S_AXI_ARADDR -- Read address -- S_AXI_ARVALID -- Read address valid -- S_AXI_ARREADY -- Read address ready -- S_AXI_RDATA -- Read data -- S_AXI_RRESP -- Read response -- S_AXI_RVALID -- Read valid -- S_AXI_RREADY -- Read ready -- Bus2IP_Clk -- Synchronization clock provided to User IP -- Bus2IP_Reset -- Active high reset for use by the User IP -- Bus2IP_Addr -- Desired address of read or write operation -- Bus2IP_RNW -- Read or write indicator for the transaction -- Bus2IP_BE -- Byte enables for the data bus -- Bus2IP_CS -- Chip select for the transcations -- Bus2IP_RdCE -- Chip enables for the read -- Bus2IP_WrCE -- Chip enables for the write -- Bus2IP_Data -- Write data bus to the User IP -- IP2Bus_Data -- Input Read Data bus from the User IP -- IP2Bus_WrAck -- Active high Write Data qualifier from the IP -- IP2Bus_RdAck -- Active high Read Data qualifier from the IP -- IP2Bus_Error -- Error signal from the IP ------------------------------------------------------------------------------- entity slave_attachment is generic ( C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := ( X"0000_0000_7000_0000", -- IP user0 base address X"0000_0000_7000_00FF", -- IP user0 high address X"0000_0000_7000_0100", -- IP user1 base address X"0000_0000_7000_01FF" -- IP user1 high address ); C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := ( 1, -- User0 CE Number 8 -- User1 CE Number ); C_IPIF_ABUS_WIDTH : integer := 32; C_IPIF_DBUS_WIDTH : integer := 32; C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF"; C_USE_WSTRB : integer := 0; C_DPHASE_TIMEOUT : integer range 0 to 512 := 16; C_FAMILY : string := "virtex6" ); port( -- AXI signals S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; S_AXI_AWADDR : in std_logic_vector (C_IPIF_ABUS_WIDTH-1 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_AWREADY : out std_logic; S_AXI_WDATA : in std_logic_vector (C_IPIF_DBUS_WIDTH-1 downto 0); S_AXI_WSTRB : in std_logic_vector ((C_IPIF_DBUS_WIDTH/8)-1 downto 0); S_AXI_WVALID : in std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector (C_IPIF_ABUS_WIDTH-1 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector (C_IPIF_DBUS_WIDTH-1 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_RREADY : in std_logic; -- Controls to the IP/IPIF modules Bus2IP_Clk : out std_logic; Bus2IP_Resetn : out std_logic; Bus2IP_Addr : out std_logic_vector (C_IPIF_ABUS_WIDTH-1 downto 0); Bus2IP_RNW : out std_logic; Bus2IP_BE : out std_logic_vector (((C_IPIF_DBUS_WIDTH/8) - 1) downto 0); Bus2IP_CS : out std_logic_vector (((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0); Bus2IP_RdCE : out std_logic_vector ((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0); Bus2IP_WrCE : out std_logic_vector ((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0); Bus2IP_Data : out std_logic_vector ((C_IPIF_DBUS_WIDTH-1) downto 0); IP2Bus_Data : in std_logic_vector ((C_IPIF_DBUS_WIDTH-1) downto 0); IP2Bus_WrAck : in std_logic; IP2Bus_RdAck : in std_logic; IP2Bus_Error : in std_logic ); end entity slave_attachment; ------------------------------------------------------------------------------- architecture imp of slave_attachment is ------------------------------------------------------------------------------- -- Get_Addr_Bits: Function Declarations ------------------------------------------------------------------------------- function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is variable i : integer := 0; begin for i in 31 downto 0 loop if y(i)='1' then return (i); end if; end loop; return -1; end function Get_Addr_Bits; ------------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2; constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY); constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE); constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1; constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto (C_ADDR_DECODE_BITS+1)) := (others=>'0'); ------------------------------------------------------------------------------- -- Signal and Type Declarations ------------------------------------------------------------------------------- signal s_axi_bvalid_i : std_logic:= '0'; signal s_axi_arready_i : std_logic; signal s_axi_rvalid_i : std_logic:= '0'; signal start : std_logic; -- Intermediate IPIC signals signal bus2ip_addr_i : std_logic_vector ((C_IPIF_ABUS_WIDTH-1) downto 0); signal timeout : std_logic; signal rd_done,wr_done : std_logic; signal rst : std_logic; signal temp_i : std_logic; type BUS_ACCESS_STATES is ( SM_IDLE, SM_READ, SM_WRITE, SM_RESP ); signal state : BUS_ACCESS_STATES; signal cs_for_gaps_i : std_logic; signal bus2ip_rnw_i : std_logic; signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0'); signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0'); signal s_axi_rdata_i : std_logic_vector (C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0'); ------------------------------------------------------------------------------- -- begin the architecture logic ------------------------------------------------------------------------------- begin ------------------------------------------------------------------------------- -- Address registered ------------------------------------------------------------------------------- Bus2IP_Clk <= S_AXI_ACLK; Bus2IP_Resetn <= S_AXI_ARESETN; bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1' else '0'; BUS2IP_RNW <= bus2ip_rnw_i; Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0')) else (others => '1'); Bus2IP_Data <= S_AXI_WDATA; Bus2IP_Addr <= bus2ip_addr_i; -- For AXI Lite interface, interconnect will duplicate the addresses on both the -- read and write channel. so onlyone address is used for decoding as well as -- passing it to IP. bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0) when (S_AXI_ARVALID='1') else ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0); -------------------------------------------------------------------------------- -- start signal will be used to latch the incoming address start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID)) when (state = SM_IDLE) else '0'; -- x_done signals are used to release the hold from AXI, it will generate "ready" -- signal on the read and write address channels. rd_done <= IP2Bus_RdAck or timeout; wr_done <= IP2Bus_WrAck or timeout; temp_i <= rd_done or wr_done; ------------------------------------------------------------------------------- -- Address Decoder Component Instance -- -- This component decodes the specified base address pairs and outputs the -- specified number of chip enables and the target bus size. ------------------------------------------------------------------------------- I_DECODER : entity work.address_decoder generic map ( C_BUS_AWIDTH => C_NUM_DECODE_BITS, C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE, C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY, C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY, C_FAMILY => "nofamily" ) port map ( Bus_clk => S_AXI_ACLK, Bus_rst => S_AXI_ARESETN, Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0), Address_Valid_Erly => start, Bus_RNW => S_AXI_ARVALID, Bus_RNW_Erly => S_AXI_ARVALID, CS_CE_ld_enable => start, Clear_CS_CE_Reg => temp_i, RW_CE_ld_enable => start, CS_for_gaps => open, -- Decode output signals CS_Out => Bus2IP_CS, RdCE_Out => Bus2IP_RdCE, WrCE_Out => Bus2IP_WrCE ); -- REGISTERING_RESET_P: Invert the reset coming from AXI ----------------------- REGISTERING_RESET_P : process (S_AXI_ACLK) is begin if S_AXI_ACLK'event and S_AXI_ACLK = '1' then rst <= not S_AXI_ARESETN; end if; end process REGISTERING_RESET_P; ------------------------------------------------------------------------------- -- AXI Transaction Controller ------------------------------------------------------------------------------- -- Access_Control: As per suggestion to optimize the core, the below state machine -- is re-coded. Latches are removed from original suggestions Access_Control : process (S_AXI_ACLK) is begin if S_AXI_ACLK'event and S_AXI_ACLK = '1' then if rst = '1' then state <= SM_IDLE; else case state is when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write state <= SM_READ; elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then state <= SM_WRITE; else state <= SM_IDLE; end if; when SM_READ => if rd_done = '1' then state <= SM_RESP; else state <= SM_READ; end if; when SM_WRITE=> if (wr_done = '1') then state <= SM_RESP; else state <= SM_WRITE; end if; when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or (s_axi_rvalid_i and S_AXI_RREADY)) = '1' then state <= SM_IDLE; else state <= SM_RESP; end if; -- coverage off when others => state <= SM_IDLE; -- coverage on end case; end if; end if; end process Access_Control; ------------------------------------------------------------------------------- -- AXI Transaction Controller signals registered ------------------------------------------------------------------------------- -- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI ----------------------- S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is begin if S_AXI_ACLK'event and S_AXI_ACLK = '1' then if (rst = '1') then s_axi_rresp_i <= (others => '0'); s_axi_rdata_i <= (others => '0'); elsif state = SM_READ then s_axi_rresp_i <= (IP2Bus_Error) & '0'; s_axi_rdata_i <= IP2Bus_Data; end if; end if; end process S_AXI_RDATA_RESP_P; S_AXI_RRESP <= s_axi_rresp_i; S_AXI_RDATA <= s_axi_rdata_i; ----------------------------- -- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel ---------------------- S_AXI_RVALID_I_P : process (S_AXI_ACLK) is begin if S_AXI_ACLK'event and S_AXI_ACLK = '1' then if (rst = '1') then s_axi_rvalid_i <= '0'; elsif ((state = SM_READ) and rd_done = '1') then s_axi_rvalid_i <= '1'; elsif (S_AXI_RREADY = '1') then s_axi_rvalid_i <= '0'; end if; end if; end process S_AXI_RVALID_I_P; -- -- S_AXI_BRESP_P: Below process provides logic for write response -- ----------------- S_AXI_BRESP_P : process (S_AXI_ACLK) is begin if S_AXI_ACLK'event and S_AXI_ACLK = '1' then if (rst = '1') then s_axi_bresp_i <= (others => '0'); elsif (state = SM_WRITE) then s_axi_bresp_i <= (IP2Bus_Error) & '0'; end if; end if; end process S_AXI_BRESP_P; S_AXI_BRESP <= s_axi_bresp_i; --S_AXI_BVALID_I_P: below process provides logic for valid write response signal ------------------- S_AXI_BVALID_I_P : process (S_AXI_ACLK) is begin if S_AXI_ACLK'event and S_AXI_ACLK = '1' then if rst = '1' then s_axi_bvalid_i <= '0'; elsif ((state = SM_WRITE) and wr_done = '1') then s_axi_bvalid_i <= '1'; elsif (S_AXI_BREADY = '1') then s_axi_bvalid_i <= '0'; end if; end if; end process S_AXI_BVALID_I_P; ----------------------------------------------------------------------------- -- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero. -------------- INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT)); signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0); -- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout -- condition to be captured as a carry into this "extra" bit. begin DPTO_CNT_P : process (S_AXI_ACLK) is begin if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then if ((state = SM_IDLE) or (state = SM_RESP)) then dpto_cnt <= (others=>'0'); else dpto_cnt <= dpto_cnt + 1; end if; end if; end process DPTO_CNT_P; timeout <= dpto_cnt(COUNTER_WIDTH); end generate INCLUDE_DPHASE_TIMER; EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate timeout <= '0'; end generate EXCLUDE_DPHASE_TIMER; ----------------------------------------------------------------------------- S_AXI_BVALID <= s_axi_bvalid_i; S_AXI_RVALID <= s_axi_rvalid_i; ----------------------------------------------------------------------------- S_AXI_ARREADY <= rd_done; S_AXI_AWREADY <= wr_done; S_AXI_WREADY <= wr_done; ------------------------------------------------------------------------------- end imp;

mit

MarkBlanco/FPGA_Sandbox

RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ipshared/1288/zed_audio_ctrl.srcs/sources_1/imports/i2s_audio/slave_attachment.vhd

7

21369

------------------------------------------------------------------- -- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. -- -- -- -- This file contains confidential and proprietary information -- -- of Xilinx, Inc. and is protected under U.S. and -- -- international copyright and other intellectual property -- -- laws. -- -- -- -- DISCLAIMER -- -- This disclaimer is not a license and does not grant any -- -- rights to the materials distributed herewith. Except as -- -- otherwise provided in a valid license issued to you by -- -- Xilinx, and to the maximum extent permitted by applicable -- -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- -- (2) Xilinx shall not be liable (whether in contract or tort, -- -- including negligence, or under any other theory of -- -- liability) for any loss or damage of any kind or nature -- -- related to, arising under or in connection with these -- -- materials, including for any direct, or any indirect, -- -- special, incidental, or consequential loss or damage -- -- (including loss of data, profits, goodwill, or any type of -- -- loss or damage suffered as a result of any action brought -- -- by a third party) even if such damage or loss was -- -- reasonably foreseeable or Xilinx had been advised of the -- -- possibility of the same. -- -- -- -- CRITICAL APPLICATIONS -- -- Xilinx products are not designed or intended to be fail- -- -- safe, or for use in any application requiring fail-safe -- -- performance, such as life-support or safety devices or -- -- systems, Class III medical devices, nuclear facilities, -- -- applications related to the deployment of airbags, or any -- -- other applications that could lead to death, personal -- -- injury, or severe property or environmental damage -- -- (individually and collectively, "Critical -- -- Applications"). Customer assumes the sole risk and -- -- liability of any use of Xilinx products in Critical -- -- Applications, subject only to applicable laws and -- -- regulations governing limitations on product liability. -- -- -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- -- PART OF THIS FILE AT ALL TIMES. -- ------------------------------------------------------------------- -- ************************************************************************ -- ------------------------------------------------------------------------------- -- Filename: slave_attachment.vhd -- Version: v1.01.a -- Description: AXI slave attachment supporting single transfers ------------------------------------------------------------------------------- -- Structure: This section shows the hierarchical structure of axi_lite_ipif. -- -- --axi_lite_ipif.vhd -- --slave_attachment.vhd -- --address_decoder.vhd ------------------------------------------------------------------------------- -- Author: BSB -- -- History: -- -- BSB 05/20/10 -- First version -- ~~~~~~ -- - Created the first version v1.00.a -- ^^^^^^ -- ~~~~~~ -- SK 06/09/10 -- updated to reduce the utilization -- 1. State machine is re-designed -- 2. R and B channels are registered and AW, AR, W channels are non-registered -- 3. Address decoding is done only for the required address bits and not complete -- 32 bits -- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux -- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg -- function. -- ^^^^^^ ------------------------------------------------------------------------------- -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- access_cs machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_cmb" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port "*_i" -- device pins: "*_pin" -- ports: - Names begin with Uppercase -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC> ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_misc.all; use work.common_types.all; ------------------------------------------------------------------------------- -- Definition of Generics ------------------------------------------------------------------------------- -- C_IPIF_ABUS_WIDTH -- IPIF Address bus width -- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width -- C_S_AXI_MIN_SIZE -- Minimum address range of the IP -- C_USE_WSTRB -- Use write strobs or not -- C_DPHASE_TIMEOUT -- Data phase time out counter -- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range -- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range -- C_FAMILY -- Target FPGA family ------------------------------------------------------------------------------- -- Definition of Ports ------------------------------------------------------------------------------- -- S_AXI_ACLK -- AXI Clock -- S_AXI_ARESET -- AXI Reset -- S_AXI_AWADDR -- AXI Write address -- S_AXI_AWVALID -- Write address valid -- S_AXI_AWREADY -- Write address ready -- S_AXI_WDATA -- Write data -- S_AXI_WSTRB -- Write strobes -- S_AXI_WVALID -- Write valid -- S_AXI_WREADY -- Write ready -- S_AXI_BRESP -- Write response -- S_AXI_BVALID -- Write response valid -- S_AXI_BREADY -- Response ready -- S_AXI_ARADDR -- Read address -- S_AXI_ARVALID -- Read address valid -- S_AXI_ARREADY -- Read address ready -- S_AXI_RDATA -- Read data -- S_AXI_RRESP -- Read response -- S_AXI_RVALID -- Read valid -- S_AXI_RREADY -- Read ready -- Bus2IP_Clk -- Synchronization clock provided to User IP -- Bus2IP_Reset -- Active high reset for use by the User IP -- Bus2IP_Addr -- Desired address of read or write operation -- Bus2IP_RNW -- Read or write indicator for the transaction -- Bus2IP_BE -- Byte enables for the data bus -- Bus2IP_CS -- Chip select for the transcations -- Bus2IP_RdCE -- Chip enables for the read -- Bus2IP_WrCE -- Chip enables for the write -- Bus2IP_Data -- Write data bus to the User IP -- IP2Bus_Data -- Input Read Data bus from the User IP -- IP2Bus_WrAck -- Active high Write Data qualifier from the IP -- IP2Bus_RdAck -- Active high Read Data qualifier from the IP -- IP2Bus_Error -- Error signal from the IP ------------------------------------------------------------------------------- entity slave_attachment is generic ( C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := ( X"0000_0000_7000_0000", -- IP user0 base address X"0000_0000_7000_00FF", -- IP user0 high address X"0000_0000_7000_0100", -- IP user1 base address X"0000_0000_7000_01FF" -- IP user1 high address ); C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := ( 1, -- User0 CE Number 8 -- User1 CE Number ); C_IPIF_ABUS_WIDTH : integer := 32; C_IPIF_DBUS_WIDTH : integer := 32; C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF"; C_USE_WSTRB : integer := 0; C_DPHASE_TIMEOUT : integer range 0 to 512 := 16; C_FAMILY : string := "virtex6" ); port( -- AXI signals S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; S_AXI_AWADDR : in std_logic_vector (C_IPIF_ABUS_WIDTH-1 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_AWREADY : out std_logic; S_AXI_WDATA : in std_logic_vector (C_IPIF_DBUS_WIDTH-1 downto 0); S_AXI_WSTRB : in std_logic_vector ((C_IPIF_DBUS_WIDTH/8)-1 downto 0); S_AXI_WVALID : in std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector (C_IPIF_ABUS_WIDTH-1 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector (C_IPIF_DBUS_WIDTH-1 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_RREADY : in std_logic; -- Controls to the IP/IPIF modules Bus2IP_Clk : out std_logic; Bus2IP_Resetn : out std_logic; Bus2IP_Addr : out std_logic_vector (C_IPIF_ABUS_WIDTH-1 downto 0); Bus2IP_RNW : out std_logic; Bus2IP_BE : out std_logic_vector (((C_IPIF_DBUS_WIDTH/8) - 1) downto 0); Bus2IP_CS : out std_logic_vector (((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0); Bus2IP_RdCE : out std_logic_vector ((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0); Bus2IP_WrCE : out std_logic_vector ((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0); Bus2IP_Data : out std_logic_vector ((C_IPIF_DBUS_WIDTH-1) downto 0); IP2Bus_Data : in std_logic_vector ((C_IPIF_DBUS_WIDTH-1) downto 0); IP2Bus_WrAck : in std_logic; IP2Bus_RdAck : in std_logic; IP2Bus_Error : in std_logic ); end entity slave_attachment; ------------------------------------------------------------------------------- architecture imp of slave_attachment is ------------------------------------------------------------------------------- -- Get_Addr_Bits: Function Declarations ------------------------------------------------------------------------------- function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is variable i : integer := 0; begin for i in 31 downto 0 loop if y(i)='1' then return (i); end if; end loop; return -1; end function Get_Addr_Bits; ------------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2; constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY); constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE); constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1; constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto (C_ADDR_DECODE_BITS+1)) := (others=>'0'); ------------------------------------------------------------------------------- -- Signal and Type Declarations ------------------------------------------------------------------------------- signal s_axi_bvalid_i : std_logic:= '0'; signal s_axi_arready_i : std_logic; signal s_axi_rvalid_i : std_logic:= '0'; signal start : std_logic; -- Intermediate IPIC signals signal bus2ip_addr_i : std_logic_vector ((C_IPIF_ABUS_WIDTH-1) downto 0); signal timeout : std_logic; signal rd_done,wr_done : std_logic; signal rst : std_logic; signal temp_i : std_logic; type BUS_ACCESS_STATES is ( SM_IDLE, SM_READ, SM_WRITE, SM_RESP ); signal state : BUS_ACCESS_STATES; signal cs_for_gaps_i : std_logic; signal bus2ip_rnw_i : std_logic; signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0'); signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0'); signal s_axi_rdata_i : std_logic_vector (C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0'); ------------------------------------------------------------------------------- -- begin the architecture logic ------------------------------------------------------------------------------- begin ------------------------------------------------------------------------------- -- Address registered ------------------------------------------------------------------------------- Bus2IP_Clk <= S_AXI_ACLK; Bus2IP_Resetn <= S_AXI_ARESETN; bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1' else '0'; BUS2IP_RNW <= bus2ip_rnw_i; Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0')) else (others => '1'); Bus2IP_Data <= S_AXI_WDATA; Bus2IP_Addr <= bus2ip_addr_i; -- For AXI Lite interface, interconnect will duplicate the addresses on both the -- read and write channel. so onlyone address is used for decoding as well as -- passing it to IP. bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0) when (S_AXI_ARVALID='1') else ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0); -------------------------------------------------------------------------------- -- start signal will be used to latch the incoming address start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID)) when (state = SM_IDLE) else '0'; -- x_done signals are used to release the hold from AXI, it will generate "ready" -- signal on the read and write address channels. rd_done <= IP2Bus_RdAck or timeout; wr_done <= IP2Bus_WrAck or timeout; temp_i <= rd_done or wr_done; ------------------------------------------------------------------------------- -- Address Decoder Component Instance -- -- This component decodes the specified base address pairs and outputs the -- specified number of chip enables and the target bus size. ------------------------------------------------------------------------------- I_DECODER : entity work.address_decoder generic map ( C_BUS_AWIDTH => C_NUM_DECODE_BITS, C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE, C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY, C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY, C_FAMILY => "nofamily" ) port map ( Bus_clk => S_AXI_ACLK, Bus_rst => S_AXI_ARESETN, Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0), Address_Valid_Erly => start, Bus_RNW => S_AXI_ARVALID, Bus_RNW_Erly => S_AXI_ARVALID, CS_CE_ld_enable => start, Clear_CS_CE_Reg => temp_i, RW_CE_ld_enable => start, CS_for_gaps => open, -- Decode output signals CS_Out => Bus2IP_CS, RdCE_Out => Bus2IP_RdCE, WrCE_Out => Bus2IP_WrCE ); -- REGISTERING_RESET_P: Invert the reset coming from AXI ----------------------- REGISTERING_RESET_P : process (S_AXI_ACLK) is begin if S_AXI_ACLK'event and S_AXI_ACLK = '1' then rst <= not S_AXI_ARESETN; end if; end process REGISTERING_RESET_P; ------------------------------------------------------------------------------- -- AXI Transaction Controller ------------------------------------------------------------------------------- -- Access_Control: As per suggestion to optimize the core, the below state machine -- is re-coded. Latches are removed from original suggestions Access_Control : process (S_AXI_ACLK) is begin if S_AXI_ACLK'event and S_AXI_ACLK = '1' then if rst = '1' then state <= SM_IDLE; else case state is when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write state <= SM_READ; elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then state <= SM_WRITE; else state <= SM_IDLE; end if; when SM_READ => if rd_done = '1' then state <= SM_RESP; else state <= SM_READ; end if; when SM_WRITE=> if (wr_done = '1') then state <= SM_RESP; else state <= SM_WRITE; end if; when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or (s_axi_rvalid_i and S_AXI_RREADY)) = '1' then state <= SM_IDLE; else state <= SM_RESP; end if; -- coverage off when others => state <= SM_IDLE; -- coverage on end case; end if; end if; end process Access_Control; ------------------------------------------------------------------------------- -- AXI Transaction Controller signals registered ------------------------------------------------------------------------------- -- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI ----------------------- S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is begin if S_AXI_ACLK'event and S_AXI_ACLK = '1' then if (rst = '1') then s_axi_rresp_i <= (others => '0'); s_axi_rdata_i <= (others => '0'); elsif state = SM_READ then s_axi_rresp_i <= (IP2Bus_Error) & '0'; s_axi_rdata_i <= IP2Bus_Data; end if; end if; end process S_AXI_RDATA_RESP_P; S_AXI_RRESP <= s_axi_rresp_i; S_AXI_RDATA <= s_axi_rdata_i; ----------------------------- -- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel ---------------------- S_AXI_RVALID_I_P : process (S_AXI_ACLK) is begin if S_AXI_ACLK'event and S_AXI_ACLK = '1' then if (rst = '1') then s_axi_rvalid_i <= '0'; elsif ((state = SM_READ) and rd_done = '1') then s_axi_rvalid_i <= '1'; elsif (S_AXI_RREADY = '1') then s_axi_rvalid_i <= '0'; end if; end if; end process S_AXI_RVALID_I_P; -- -- S_AXI_BRESP_P: Below process provides logic for write response -- ----------------- S_AXI_BRESP_P : process (S_AXI_ACLK) is begin if S_AXI_ACLK'event and S_AXI_ACLK = '1' then if (rst = '1') then s_axi_bresp_i <= (others => '0'); elsif (state = SM_WRITE) then s_axi_bresp_i <= (IP2Bus_Error) & '0'; end if; end if; end process S_AXI_BRESP_P; S_AXI_BRESP <= s_axi_bresp_i; --S_AXI_BVALID_I_P: below process provides logic for valid write response signal ------------------- S_AXI_BVALID_I_P : process (S_AXI_ACLK) is begin if S_AXI_ACLK'event and S_AXI_ACLK = '1' then if rst = '1' then s_axi_bvalid_i <= '0'; elsif ((state = SM_WRITE) and wr_done = '1') then s_axi_bvalid_i <= '1'; elsif (S_AXI_BREADY = '1') then s_axi_bvalid_i <= '0'; end if; end if; end process S_AXI_BVALID_I_P; ----------------------------------------------------------------------------- -- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero. -------------- INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT)); signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0); -- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout -- condition to be captured as a carry into this "extra" bit. begin DPTO_CNT_P : process (S_AXI_ACLK) is begin if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then if ((state = SM_IDLE) or (state = SM_RESP)) then dpto_cnt <= (others=>'0'); else dpto_cnt <= dpto_cnt + 1; end if; end if; end process DPTO_CNT_P; timeout <= dpto_cnt(COUNTER_WIDTH); end generate INCLUDE_DPHASE_TIMER; EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate timeout <= '0'; end generate EXCLUDE_DPHASE_TIMER; ----------------------------------------------------------------------------- S_AXI_BVALID <= s_axi_bvalid_i; S_AXI_RVALID <= s_axi_rvalid_i; ----------------------------------------------------------------------------- S_AXI_ARREADY <= rd_done; S_AXI_AWREADY <= wr_done; S_AXI_WREADY <= wr_done; ------------------------------------------------------------------------------- end imp;

mit

VerkhovtsovPavel/BSUIR_Labs

Labs/POCP/POCP-6/src/RegFile.vhd

2

1417

library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; entity RegFile is generic ( INITREG: std_logic_vector := "0000"; a: integer := 2); port ( INIT: in std_logic; WDP: in std_logic_vector(INITREG'range); WA: in std_logic_vector(a-1 downto 0); RA: in std_logic_vector(a-1 downto 0); WE: in std_logic; RDP: out std_logic_vector(INITREG'range)); end RegFile; architecture Beh of RegFile is component RegN is generic ( initreg: std_logic_vector := "1001"); port ( Din: in std_logic_vector(initreg'range); EN: in std_logic; INIT: in std_logic; CLK: in std_logic; OE: in std_logic; Dout: out std_logic_vector(initreg'range)); end component; signal wen: std_logic_vector(2**a-1 downto 0); signal ren: std_logic_vector(2**a-1 downto 0); signal readd: std_logic_vector (initreg'range); Begin WAD: process (WA) begin for i in 0 to 2**a - 1 loop if i = conv_integer(WA) then wen (i) <= '1'; else wen (i) <= '0'; end if; end loop; end process; RAD: process (RA) begin for i in 0 to 2**a - 1 loop if i = conv_integer(RA) then ren (i) <= '1'; else ren (i) <= '0'; end if; end loop; end process; Regi: for i in 2**a - 1 downto 0 generate Regi: Regn generic map (initreg) port map (WDP, wen(i), init, we, ren(i), readd); end generate; RDP <= readd; End Beh;

mit

MarkBlanco/FPGA_Sandbox

RecComp/Lab3/lab3_project_default.xpr/project_1/project_1.ipdefs/ip_0/hdl/vhdl/convolve_kernel_fbkb.vhd

1

3167

-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2017.2 -- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. -- -- ============================================================== Library ieee; use ieee.std_logic_1164.all; entity convolve_kernel_fbkb is generic ( ID : integer := 0; NUM_STAGE : integer := 5; din0_WIDTH : integer := 32; din1_WIDTH : integer := 32; dout_WIDTH : integer := 32 ); port ( clk : in std_logic; reset : in std_logic; ce : in std_logic; din0 : in std_logic_vector(din0_WIDTH-1 downto 0); din1 : in std_logic_vector(din1_WIDTH-1 downto 0); dout : out std_logic_vector(dout_WIDTH-1 downto 0) ); end entity; architecture arch of convolve_kernel_fbkb is --------------------- Component --------------------- component convolve_kernel_ap_fadd_3_full_dsp_32 is port ( aclk : in std_logic; aclken : in std_logic; s_axis_a_tvalid : in std_logic; s_axis_a_tdata : in std_logic_vector(31 downto 0); s_axis_b_tvalid : in std_logic; s_axis_b_tdata : in std_logic_vector(31 downto 0); m_axis_result_tvalid : out std_logic; m_axis_result_tdata : out std_logic_vector(31 downto 0) ); end component; --------------------- Local signal ------------------ signal aclk : std_logic; signal aclken : std_logic; signal a_tvalid : std_logic; signal a_tdata : std_logic_vector(31 downto 0); signal b_tvalid : std_logic; signal b_tdata : std_logic_vector(31 downto 0); signal r_tvalid : std_logic; signal r_tdata : std_logic_vector(31 downto 0); signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0); signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0); begin --------------------- Instantiation ----------------- convolve_kernel_ap_fadd_3_full_dsp_32_u : component convolve_kernel_ap_fadd_3_full_dsp_32 port map ( aclk => aclk, aclken => aclken, s_axis_a_tvalid => a_tvalid, s_axis_a_tdata => a_tdata, s_axis_b_tvalid => b_tvalid, s_axis_b_tdata => b_tdata, m_axis_result_tvalid => r_tvalid, m_axis_result_tdata => r_tdata ); --------------------- Assignment -------------------- aclk <= clk; aclken <= ce; a_tvalid <= '1'; a_tdata <= din0_buf1; b_tvalid <= '1'; b_tdata <= din1_buf1; dout <= r_tdata; --------------------- Input buffer ------------------ process (clk) begin if clk'event and clk = '1' then if ce = '1' then din0_buf1 <= din0; din1_buf1 <= din1; end if; end if; end process; end architecture;

mit

VerkhovtsovPavel/BSUIR_Labs

Labs/POCP/POCP-6/src/FIFO.vhd

1

1506

library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; entity FIFO is generic( -- øèíà àäðåñà m: integer := 2; -- øèíà äàííûõ n: integer := 2 ); port ( -- ñèíõðîíèçàöèÿ CLK: in std_logic; -- ñèãíàë óïðàâëåíèÿ ÷òåíèåì/çàïèñüþ WR: in std_logic; -- äâóíàïðàâëåííàÿ øèíà äàííûõ DB: inout std_logic_vector (n-1 downto 0); EMPTY: out std_logic; FULL: out std_logic ); end FIFO; architecture Beh of FIFO is -- òèï õðàíèìîãî ñëîâà subtype word is std_logic_vector (n-1 downto 0); -- íåïîñðåäñòâåííî òèï õðàíèëèùà äàííûõ type tram is array (0 to 2**m - 1) of word; signal sRAM: tram; signal head: integer := 0; constant Limit: integer := 2 ** m -1; Begin SH: process (CLK) begin if rising_edge(CLK) then if (WR = '0') then if (head <= Limit) then head <= head + 1; end if; elsif (WR = '1') then if (head > 0) then head <= head - 1; end if; end if; end if; if (head = 0) then empty <= '1'; full <= '0'; elsif (head = Limit + 1) then empty <= '0'; full <= '1'; else empty <= '0'; full <= '0'; end if; end process; WRP: process (head) begin if WR = '0' then if (head > 0 and head <= Limit + 1) then sRAM(head - 1) <= DB; end if; end if; end process; RDP: process(head) begin if WR = '1' then if (head >= 0 and head <= Limit) then DB <= sRAM (head); end if; else DB <= (others => 'Z'); end if; end process; end Beh;

mit

MarkBlanco/FPGA_Sandbox

RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_bram_ctrl_0_bram_0/synth/zqynq_lab_1_design_axi_bram_ctrl_0_bram_0.vhd

1

15765

-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3 -- IP Revision: 6 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY blk_mem_gen_v8_3_6; USE blk_mem_gen_v8_3_6.blk_mem_gen_v8_3_6; ENTITY zqynq_lab_1_design_axi_bram_ctrl_0_bram_0 IS PORT ( clka : IN STD_LOGIC; rsta : IN STD_LOGIC; ena : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); clkb : IN STD_LOGIC; rstb : IN STD_LOGIC; enb : IN STD_LOGIC; web : IN STD_LOGIC_VECTOR(3 DOWNTO 0); addrb : IN STD_LOGIC_VECTOR(31 DOWNTO 0); dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0); doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END zqynq_lab_1_design_axi_bram_ctrl_0_bram_0; ARCHITECTURE zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_arch OF zqynq_lab_1_design_axi_bram_ctrl_0_bram_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING; ATTRIBUTE DowngradeIPIdentifiedWarnings OF zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_arch: ARCHITECTURE IS "yes"; COMPONENT blk_mem_gen_v8_3_6 IS GENERIC ( C_FAMILY : STRING; C_XDEVICEFAMILY : STRING; C_ELABORATION_DIR : STRING; C_INTERFACE_TYPE : INTEGER; C_AXI_TYPE : INTEGER; C_AXI_SLAVE_TYPE : INTEGER; C_USE_BRAM_BLOCK : INTEGER; C_ENABLE_32BIT_ADDRESS : INTEGER; C_CTRL_ECC_ALGO : STRING; C_HAS_AXI_ID : INTEGER; C_AXI_ID_WIDTH : INTEGER; C_MEM_TYPE : INTEGER; C_BYTE_SIZE : INTEGER; C_ALGORITHM : INTEGER; C_PRIM_TYPE : INTEGER; C_LOAD_INIT_FILE : INTEGER; C_INIT_FILE_NAME : STRING; C_INIT_FILE : STRING; C_USE_DEFAULT_DATA : INTEGER; C_DEFAULT_DATA : STRING; C_HAS_RSTA : INTEGER; C_RST_PRIORITY_A : STRING; C_RSTRAM_A : INTEGER; C_INITA_VAL : STRING; C_HAS_ENA : INTEGER; C_HAS_REGCEA : INTEGER; C_USE_BYTE_WEA : INTEGER; C_WEA_WIDTH : INTEGER; C_WRITE_MODE_A : STRING; C_WRITE_WIDTH_A : INTEGER; C_READ_WIDTH_A : INTEGER; C_WRITE_DEPTH_A : INTEGER; C_READ_DEPTH_A : INTEGER; C_ADDRA_WIDTH : INTEGER; C_HAS_RSTB : INTEGER; C_RST_PRIORITY_B : STRING; C_RSTRAM_B : INTEGER; C_INITB_VAL : STRING; C_HAS_ENB : INTEGER; C_HAS_REGCEB : INTEGER; C_USE_BYTE_WEB : INTEGER; C_WEB_WIDTH : INTEGER; C_WRITE_MODE_B : STRING; C_WRITE_WIDTH_B : INTEGER; C_READ_WIDTH_B : INTEGER; C_WRITE_DEPTH_B : INTEGER; C_READ_DEPTH_B : INTEGER; C_ADDRB_WIDTH : INTEGER; C_HAS_MEM_OUTPUT_REGS_A : INTEGER; C_HAS_MEM_OUTPUT_REGS_B : INTEGER; C_HAS_MUX_OUTPUT_REGS_A : INTEGER; C_HAS_MUX_OUTPUT_REGS_B : INTEGER; C_MUX_PIPELINE_STAGES : INTEGER; C_HAS_SOFTECC_INPUT_REGS_A : INTEGER; C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER; C_USE_SOFTECC : INTEGER; C_USE_ECC : INTEGER; C_EN_ECC_PIPE : INTEGER; C_HAS_INJECTERR : INTEGER; C_SIM_COLLISION_CHECK : STRING; C_COMMON_CLK : INTEGER; C_DISABLE_WARN_BHV_COLL : INTEGER; C_EN_SLEEP_PIN : INTEGER; C_USE_URAM : INTEGER; C_EN_RDADDRA_CHG : INTEGER; C_EN_RDADDRB_CHG : INTEGER; C_EN_DEEPSLEEP_PIN : INTEGER; C_EN_SHUTDOWN_PIN : INTEGER; C_EN_SAFETY_CKT : INTEGER; C_DISABLE_WARN_BHV_RANGE : INTEGER; C_COUNT_36K_BRAM : STRING; C_COUNT_18K_BRAM : STRING; C_EST_POWER_SUMMARY : STRING ); PORT ( clka : IN STD_LOGIC; rsta : IN STD_LOGIC; ena : IN STD_LOGIC; regcea : IN STD_LOGIC; wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0); addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0); dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0); douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); clkb : IN STD_LOGIC; rstb : IN STD_LOGIC; enb : IN STD_LOGIC; regceb : IN STD_LOGIC; web : IN STD_LOGIC_VECTOR(3 DOWNTO 0); addrb : IN STD_LOGIC_VECTOR(31 DOWNTO 0); dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0); doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); injectsbiterr : IN STD_LOGIC; injectdbiterr : IN STD_LOGIC; eccpipece : IN STD_LOGIC; sbiterr : OUT STD_LOGIC; dbiterr : OUT STD_LOGIC; rdaddrecc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); sleep : IN STD_LOGIC; deepsleep : IN STD_LOGIC; shutdown : IN STD_LOGIC; rsta_busy : OUT STD_LOGIC; rstb_busy : OUT STD_LOGIC; s_aclk : IN STD_LOGIC; s_aresetn : IN STD_LOGIC; s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_awvalid : IN STD_LOGIC; s_axi_awready : OUT STD_LOGIC; s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_wlast : IN STD_LOGIC; s_axi_wvalid : IN STD_LOGIC; s_axi_wready : OUT STD_LOGIC; s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_bvalid : OUT STD_LOGIC; s_axi_bready : IN STD_LOGIC; s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0); s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_arvalid : IN STD_LOGIC; s_axi_arready : OUT STD_LOGIC; s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); s_axi_rlast : OUT STD_LOGIC; s_axi_rvalid : OUT STD_LOGIC; s_axi_rready : IN STD_LOGIC; s_axi_injectsbiterr : IN STD_LOGIC; s_axi_injectdbiterr : IN STD_LOGIC; s_axi_sbiterr : OUT STD_LOGIC; s_axi_dbiterr : OUT STD_LOGIC; s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END COMPONENT blk_mem_gen_v8_3_6; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_6,Vivado 2017.2"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_arch : ARCHITECTURE IS "zqynq_lab_1_design_axi_bram_ctrl_0_bram_0,blk_mem_gen_v8_3_6,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_arch: ARCHITECTURE IS "zqynq_lab_1_design_axi_bram_ctrl_0_bram_0,blk_mem_gen_v8_3_6,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=1,C_ENABLE_32BIT_ADDRESS=1,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=2,C_BYTE_SIZE=8,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=" & "0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=NONE,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=1,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=1,C_WEA_WIDTH=4,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=32,C_READ_WIDTH_A=32,C_WRITE_DEPTH_A=16384,C_READ_DEPTH_A=16384,C_ADDRA_WIDTH=32,C_HAS_RSTB=1,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=1,C_WEB_WIDTH=4,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=32,C" & "_READ_WIDTH_B=32,C_WRITE_DEPTH_B=16384,C_READ_DEPTH_B=16384,C_ADDRB_WIDTH=32,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=" & "0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=16,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 20.388 mW}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK"; ATTRIBUTE X_INTERFACE_INFO OF rsta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST"; ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN"; ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE"; ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR"; ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN"; ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT"; ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK"; ATTRIBUTE X_INTERFACE_INFO OF rstb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB RST"; ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN"; ATTRIBUTE X_INTERFACE_INFO OF web: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE"; ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR"; ATTRIBUTE X_INTERFACE_INFO OF dinb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN"; ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT"; BEGIN U0 : blk_mem_gen_v8_3_6 GENERIC MAP ( C_FAMILY => "zynq", C_XDEVICEFAMILY => "zynq", C_ELABORATION_DIR => "./", C_INTERFACE_TYPE => 0, C_AXI_TYPE => 1, C_AXI_SLAVE_TYPE => 0, C_USE_BRAM_BLOCK => 1, C_ENABLE_32BIT_ADDRESS => 1, C_CTRL_ECC_ALGO => "NONE", C_HAS_AXI_ID => 0, C_AXI_ID_WIDTH => 4, C_MEM_TYPE => 2, C_BYTE_SIZE => 8, C_ALGORITHM => 1, C_PRIM_TYPE => 1, C_LOAD_INIT_FILE => 0, C_INIT_FILE_NAME => "no_coe_file_loaded", C_INIT_FILE => "NONE", C_USE_DEFAULT_DATA => 0, C_DEFAULT_DATA => "0", C_HAS_RSTA => 1, C_RST_PRIORITY_A => "CE", C_RSTRAM_A => 0, C_INITA_VAL => "0", C_HAS_ENA => 1, C_HAS_REGCEA => 0, C_USE_BYTE_WEA => 1, C_WEA_WIDTH => 4, C_WRITE_MODE_A => "WRITE_FIRST", C_WRITE_WIDTH_A => 32, C_READ_WIDTH_A => 32, C_WRITE_DEPTH_A => 16384, C_READ_DEPTH_A => 16384, C_ADDRA_WIDTH => 32, C_HAS_RSTB => 1, C_RST_PRIORITY_B => "CE", C_RSTRAM_B => 0, C_INITB_VAL => "0", C_HAS_ENB => 1, C_HAS_REGCEB => 0, C_USE_BYTE_WEB => 1, C_WEB_WIDTH => 4, C_WRITE_MODE_B => "WRITE_FIRST", C_WRITE_WIDTH_B => 32, C_READ_WIDTH_B => 32, C_WRITE_DEPTH_B => 16384, C_READ_DEPTH_B => 16384, C_ADDRB_WIDTH => 32, C_HAS_MEM_OUTPUT_REGS_A => 0, C_HAS_MEM_OUTPUT_REGS_B => 0, C_HAS_MUX_OUTPUT_REGS_A => 0, C_HAS_MUX_OUTPUT_REGS_B => 0, C_MUX_PIPELINE_STAGES => 0, C_HAS_SOFTECC_INPUT_REGS_A => 0, C_HAS_SOFTECC_OUTPUT_REGS_B => 0, C_USE_SOFTECC => 0, C_USE_ECC => 0, C_EN_ECC_PIPE => 0, C_HAS_INJECTERR => 0, C_SIM_COLLISION_CHECK => "ALL", C_COMMON_CLK => 0, C_DISABLE_WARN_BHV_COLL => 0, C_EN_SLEEP_PIN => 0, C_USE_URAM => 0, C_EN_RDADDRA_CHG => 0, C_EN_RDADDRB_CHG => 0, C_EN_DEEPSLEEP_PIN => 0, C_EN_SHUTDOWN_PIN => 0, C_EN_SAFETY_CKT => 0, C_DISABLE_WARN_BHV_RANGE => 0, C_COUNT_36K_BRAM => "16", C_COUNT_18K_BRAM => "0", C_EST_POWER_SUMMARY => "Estimated Power for IP : 20.388 mW" ) PORT MAP ( clka => clka, rsta => rsta, ena => ena, regcea => '0', wea => wea, addra => addra, dina => dina, douta => douta, clkb => clkb, rstb => rstb, enb => enb, regceb => '0', web => web, addrb => addrb, dinb => dinb, doutb => doutb, injectsbiterr => '0', injectdbiterr => '0', eccpipece => '0', sleep => '0', deepsleep => '0', shutdown => '0', s_aclk => '0', s_aresetn => '0', s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_awvalid => '0', s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_wlast => '0', s_axi_wvalid => '0', s_axi_bready => '0', s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)), s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)), s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)), s_axi_arvalid => '0', s_axi_rready => '0', s_axi_injectsbiterr => '0', s_axi_injectdbiterr => '0' ); END zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_arch;

mit