repo_name
stringlengths 6
79
| path
stringlengths 5
236
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stringclasses 54
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stringlengths 1
8
| content
stringlengths 0
1.04M
⌀ | license
stringclasses 15
values |
|---|---|---|---|---|---|
Given-Jiang/Gray_Processing
|
tb_Gray_Processing/altera_lnsim/common_28nm_ram_register/_primary.vhd
|
5
|
799
|
library verilog;
use verilog.vl_types.all;
entity common_28nm_ram_register is
generic(
width : integer := 1;
preset : vl_logic := Hi0
);
port(
d : in vl_logic_vector;
clk : in vl_logic;
aclr : in vl_logic;
devclrn : in vl_logic;
devpor : in vl_logic;
stall : in vl_logic;
ena : in vl_logic;
q : out vl_logic_vector;
aclrout : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of width : constant is 1;
attribute mti_svvh_generic_type of preset : constant is 1;
end common_28nm_ram_register;
|
mit
|
Andy46/OV7670-VHDL
|
OV7670/src/mod_7SEG/mod_bcd.vhd
|
1
|
1668
|
----------------------------------------------------------------------------------
-- Company: *
-- Engineer: Andres Gamboa
--
-- Create Date: 09:50:50 10/11/2013
-- Design Name:
-- Module Name: sevseg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mod_bcd is
port ( bcd : in std_logic_vector(3 downto 0);
g : in std_logic;
segment7 : out std_logic_vector(6 downto 0));
end mod_bcd;
architecture Behavioral of mod_bcd is
begin
process(bcd, g)
begin
if g = '0' then
segment7 <= "0111111"; -- '-'
else
case bcd is
when "0000"=> segment7 <="1000000"; -- '0'
when "0001"=> segment7 <="1111001"; -- '1'
when "0010"=> segment7 <="0100100"; -- '2'
when "0011"=> segment7 <="0110000"; -- '3'
when "0100"=> segment7 <="0011001"; -- '4'
when "0101"=> segment7 <="0010010"; -- '5'
when "0110"=> segment7 <="0000010"; -- '6'
when "0111"=> segment7 <="1111000"; -- '7'
when "1000"=> segment7 <="0000000"; -- '8'
when "1001"=> segment7 <="0010000"; -- '9'
when "1010"=> segment7 <="0001000"; -- 'A'
when "1011"=> segment7 <="0000011"; -- 'B'
when "1100"=> segment7 <="1000110"; -- 'C'
when "1101"=> segment7 <="0100001"; -- 'D'
when "1110"=> segment7 <="0000110"; -- 'E'
when "1111"=> segment7 <="0001110"; -- 'F'
when others=> segment7 <="0111111"; -- '-'
end case;
end if;
end process;
end Behavioral;
|
mit
|
Given-Jiang/Gray_Processing
|
Gray_Processing_dspbuilder/db/alt_dspbuilder_testbench_capture_GNQX2JTRTZ.vhd
|
20
|
1755
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_capture_GNQX2JTRTZ is
generic ( XFILE : string := "default";
DSPBTYPE : string := "");
port(
clock : in std_logic;
aclr : in std_logic;
input : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_testbench_capture_GNQX2JTRTZ is
function str(sl: std_logic) return character is
variable c: character;
begin
case sl is
when '0' => c := '0';
when '1' => c := '1';
when others => c := 'X';
end case;
return c;
end str;
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := str(slv(i));
r := r + 1;
end loop;
return result;
end str;
procedure write_type_header(file f:text) is
use STD.textio.all;
variable my_line : line;
begin
write ( my_line, DSPBTYPE);
writeline ( f, my_line );
end procedure write_type_header ;
file oFile : text open write_mode is XFILE;
Begin
-- data capture
-- write type information to output file
write_type_header(oFile);
-- Writing Output Signal into file
Output:process(clock)
variable traceline : line ;
begin
if (aclr ='1') then
-- do not record
elsif clock'event and clock='1' then
write(traceline, str(input),justified=>left);
writeline(oFile,traceline);
end if ;
end process ;
end architecture;
|
mit
|
Given-Jiang/Gray_Processing
|
tb_Gray_Processing/db/alt_dspbuilder_testbench_capture_GNQX2JTRTZ.vhd
|
20
|
1755
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_capture_GNQX2JTRTZ is
generic ( XFILE : string := "default";
DSPBTYPE : string := "");
port(
clock : in std_logic;
aclr : in std_logic;
input : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_testbench_capture_GNQX2JTRTZ is
function str(sl: std_logic) return character is
variable c: character;
begin
case sl is
when '0' => c := '0';
when '1' => c := '1';
when others => c := 'X';
end case;
return c;
end str;
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := str(slv(i));
r := r + 1;
end loop;
return result;
end str;
procedure write_type_header(file f:text) is
use STD.textio.all;
variable my_line : line;
begin
write ( my_line, DSPBTYPE);
writeline ( f, my_line );
end procedure write_type_header ;
file oFile : text open write_mode is XFILE;
Begin
-- data capture
-- write type information to output file
write_type_header(oFile);
-- Writing Output Signal into file
Output:process(clock)
variable traceline : line ;
begin
if (aclr ='1') then
-- do not record
elsif clock'event and clock='1' then
write(traceline, str(input),justified=>left);
writeline(oFile,traceline);
end if ;
end process ;
end architecture;
|
mit
|
inmcm/Simon_Speck_Ciphers
|
VHDL/SIMON_CIPHER_TB.vhd
|
1
|
14458
|
-- SIMON_CIPHER_TB.vhd
-- Copyright 2016 Michael Calvin McCoy
-- [email protected]
-- see LICENSE.md
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:00:46 10/04/2015
-- Design Name:
-- Module Name: D:/Work/Code/Simon_Speck_Ciphers/VHDL/SIMON_CIPHER_TB.vhd
-- Project Name: Simon
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: SIMON_CIPHER
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use work.SIMON_CONSTANTS.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY SIMON_CIPHER_TB IS
END SIMON_CIPHER_TB;
ARCHITECTURE behavior OF SIMON_CIPHER_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT SIMON_CIPHER
GENERIC(KEY_SIZE : integer range 0 to 256;
BLOCK_SIZE : integer range 0 to 128;
ROUND_LIMIT: integer range 0 to 72);
PORT(
SYS_CLK : IN std_logic;
RST : IN std_logic;
BUSY : OUT std_logic;
CONTROL : IN std_logic_vector(1 downto 0);
KEY : IN std_logic_vector(KEY_SIZE - 1 downto 0);
BLOCK_INPUT : IN std_logic_vector(BLOCK_SIZE - 1 downto 0);
BLOCK_OUTPUT : OUT std_logic_vector(BLOCK_SIZE - 1 downto 0)
);
END COMPONENT;
--Global Inputs
signal SYS_CLK : std_logic := '0';
signal RST : std_logic := '0';
signal CONTROL : std_logic_vector(1 downto 0) := (others => '0');
--UUT 1
signal KEY_1 : std_logic_vector(63 downto 0) := (others => '0');
signal BLOCK_INPUT_1 : std_logic_vector(31 downto 0) := (others => '0');
signal BUSY_1 : std_logic;
signal BLOCK_OUTPUT_1 : std_logic_vector(31 downto 0);
--UUT 2
signal KEY_2 : std_logic_vector(71 downto 0) := (others => '0');
signal BLOCK_INPUT_2 : std_logic_vector(47 downto 0) := (others => '0');
signal BUSY_2 : std_logic;
signal BLOCK_OUTPUT_2 : std_logic_vector(47 downto 0);
--UUT 3
signal KEY_3 : std_logic_vector(95 downto 0) := (others => '0');
signal BLOCK_INPUT_3 : std_logic_vector(47 downto 0) := (others => '0');
signal BUSY_3 : std_logic;
signal BLOCK_OUTPUT_3 : std_logic_vector(47 downto 0);
--UUT 4
signal KEY_4 : std_logic_vector(95 downto 0) := (others => '0');
signal BLOCK_INPUT_4 : std_logic_vector(63 downto 0) := (others => '0');
signal BUSY_4 : std_logic;
signal BLOCK_OUTPUT_4 : std_logic_vector(63 downto 0);
--UUT 5
signal KEY_5 : std_logic_vector(127 downto 0) := (others => '0');
signal BLOCK_INPUT_5 : std_logic_vector(63 downto 0) := (others => '0');
signal BUSY_5 : std_logic;
signal BLOCK_OUTPUT_5 : std_logic_vector(63 downto 0);
--UUT 6
signal KEY_6 : std_logic_vector(95 downto 0) := (others => '0');
signal BLOCK_INPUT_6 : std_logic_vector(95 downto 0) := (others => '0');
signal BUSY_6 : std_logic;
signal BLOCK_OUTPUT_6 : std_logic_vector(95 downto 0);
--UUT 7
signal KEY_7 : std_logic_vector(143 downto 0) := (others => '0');
signal BLOCK_INPUT_7 : std_logic_vector(95 downto 0) := (others => '0');
signal BUSY_7 : std_logic;
signal BLOCK_OUTPUT_7 : std_logic_vector(95 downto 0);
--UUT 8
signal KEY_8 : std_logic_vector(127 downto 0) := (others => '0');
signal BLOCK_INPUT_8 : std_logic_vector(127 downto 0) := (others => '0');
signal BUSY_8 : std_logic;
signal BLOCK_OUTPUT_8 : std_logic_vector(127 downto 0);
--UUT 9
signal KEY_9 : std_logic_vector(191 downto 0) := (others => '0');
signal BLOCK_INPUT_9 : std_logic_vector(127 downto 0) := (others => '0');
signal BUSY_9 : std_logic;
signal BLOCK_OUTPUT_9 : std_logic_vector(127 downto 0);
--UUT 10
signal KEY_10 : std_logic_vector(255 downto 0) := (others => '0');
signal BLOCK_INPUT_10 : std_logic_vector(127 downto 0) := (others => '0');
signal BUSY_10 : std_logic;
signal BLOCK_OUTPUT_10 : std_logic_vector(127 downto 0);
-- Clock period definitions
constant SYS_CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut_1: SIMON_CIPHER
GENERIC MAP (KEY_SIZE => 64,
BLOCK_SIZE => 32,
ROUND_LIMIT => Round_Count_Lookup(64, 32))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_1,
CONTROL => CONTROL,
KEY => KEY_1,
BLOCK_INPUT => BLOCK_INPUT_1,
BLOCK_OUTPUT => BLOCK_OUTPUT_1
);
uut_2: SIMON_CIPHER
GENERIC MAP (KEY_SIZE => 72,
BLOCK_SIZE => 48,
ROUND_LIMIT => Round_Count_Lookup(72, 48))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_2,
CONTROL => CONTROL,
KEY => KEY_2,
BLOCK_INPUT => BLOCK_INPUT_2,
BLOCK_OUTPUT => BLOCK_OUTPUT_2
);
uut_3: SIMON_CIPHER
GENERIC MAP (KEY_SIZE => 96,
BLOCK_SIZE => 48,
ROUND_LIMIT => Round_Count_Lookup(96, 48))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_3,
CONTROL => CONTROL,
KEY => KEY_3,
BLOCK_INPUT => BLOCK_INPUT_3,
BLOCK_OUTPUT => BLOCK_OUTPUT_3
);
uut_4: SIMON_CIPHER
GENERIC MAP (KEY_SIZE => 96,
BLOCK_SIZE => 64,
ROUND_LIMIT => Round_Count_Lookup(96, 64))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_4,
CONTROL => CONTROL,
KEY => KEY_4,
BLOCK_INPUT => BLOCK_INPUT_4,
BLOCK_OUTPUT => BLOCK_OUTPUT_4
);
uut_5: SIMON_CIPHER
GENERIC MAP (KEY_SIZE => 128,
BLOCK_SIZE => 64,
ROUND_LIMIT => Round_Count_Lookup(128, 64))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_5,
CONTROL => CONTROL,
KEY => KEY_5,
BLOCK_INPUT => BLOCK_INPUT_5,
BLOCK_OUTPUT => BLOCK_OUTPUT_5
);
uut_6: SIMON_CIPHER
GENERIC MAP (KEY_SIZE => 96,
BLOCK_SIZE => 96,
ROUND_LIMIT => Round_Count_Lookup(96, 96))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_6,
CONTROL => CONTROL,
KEY => KEY_6,
BLOCK_INPUT => BLOCK_INPUT_6,
BLOCK_OUTPUT => BLOCK_OUTPUT_6
);
uut_7: SIMON_CIPHER
GENERIC MAP (KEY_SIZE => 144,
BLOCK_SIZE => 96,
ROUND_LIMIT => Round_Count_Lookup(144, 96))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_7,
CONTROL => CONTROL,
KEY => KEY_7,
BLOCK_INPUT => BLOCK_INPUT_7,
BLOCK_OUTPUT => BLOCK_OUTPUT_7
);
uut_8: SIMON_CIPHER
GENERIC MAP (KEY_SIZE => 128,
BLOCK_SIZE => 128,
ROUND_LIMIT => Round_Count_Lookup(128, 128))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_8,
CONTROL => CONTROL,
KEY => KEY_8,
BLOCK_INPUT => BLOCK_INPUT_8,
BLOCK_OUTPUT => BLOCK_OUTPUT_8
);
uut_9: SIMON_CIPHER
GENERIC MAP (KEY_SIZE => 192,
BLOCK_SIZE => 128,
ROUND_LIMIT => Round_Count_Lookup(192, 128))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_9,
CONTROL => CONTROL,
KEY => KEY_9,
BLOCK_INPUT => BLOCK_INPUT_9,
BLOCK_OUTPUT => BLOCK_OUTPUT_9
);
uut_10: SIMON_CIPHER
GENERIC MAP (KEY_SIZE => 256,
BLOCK_SIZE => 128,
ROUND_LIMIT => Round_Count_Lookup(256, 128))
PORT MAP (
SYS_CLK => SYS_CLK,
RST => RST,
BUSY => BUSY_10,
CONTROL => CONTROL,
KEY => KEY_10,
BLOCK_INPUT => BLOCK_INPUT_10,
BLOCK_OUTPUT => BLOCK_OUTPUT_10
);
-- Clock process definitions
SYS_CLK_process :process
begin
for i in 0 to 500 loop
SYS_CLK <= '0';
wait for SYS_CLK_period/2;
SYS_CLK <= '1';
wait for SYS_CLK_period/2;
end loop ;
wait;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for SYS_CLK_period*10;
KEY_1 <= X"1918111009080100";
KEY_2 <= X"1211100a0908020100";
KEY_3 <= X"1a19181211100a0908020100";
KEY_4 <= X"131211100b0a090803020100";
KEY_5 <= X"1b1a1918131211100b0a090803020100";
KEY_6 <= X"0d0c0b0a0908050403020100";
KEY_7 <= X"1514131211100d0c0b0a0908050403020100";
KEY_8 <= X"0f0e0d0c0b0a09080706050403020100";
KEY_9 <= X"17161514131211100f0e0d0c0b0a09080706050403020100";
KEY_10 <= X"1f1e1d1c1b1a191817161514131211100f0e0d0c0b0a09080706050403020100";
CONTROL <= "01";
wait for SYS_CLK_period*3;
CONTROL <= "00";
wait for SYS_CLK_period*100;
BLOCK_INPUT_1 <= X"65656877";
BLOCK_INPUT_2 <= X"6120676e696c";
BLOCK_INPUT_3 <= X"72696320646e";
BLOCK_INPUT_4 <= X"6f7220676e696c63";
BLOCK_INPUT_5 <= X"656b696c20646e75";
BLOCK_INPUT_6 <= X"2072616c6c69702065687420";
BLOCK_INPUT_7 <= X"74616874207473756420666f";
BLOCK_INPUT_8 <= X"63736564207372656c6c657661727420";
BLOCK_INPUT_9 <= X"206572656874206e6568772065626972";
BLOCK_INPUT_10 <= X"74206e69206d6f6f6d69732061207369";
CONTROL <= "11";
wait for SYS_CLK_period*3;
CONTROL <= "00";
wait for SYS_CLK_period*100;
assert BLOCK_OUTPUT_1 /= X"c69be9bb" report "UUT1 Encryption Success" severity note;
assert BLOCK_OUTPUT_1 = X"c69be9bb" report "UUT1 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_2 /= X"dae5ac292cac" report "UUT2 Encryption Success" severity note;
assert BLOCK_OUTPUT_2 = X"dae5ac292cac" report "UUT2 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_3 /= X"6e06a5acf156" report "UUT3 Encryption Success" severity note;
assert BLOCK_OUTPUT_3 = X"6e06a5acf156" report "UUT3 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_4 /= X"5ca2e27f111a8fc8" report "UUT4 Encryption Success" severity note;
assert BLOCK_OUTPUT_4 = X"5ca2e27f111a8fc8" report "UUT4 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_5 /= X"44c8fc20b9dfa07a" report "UUT5 Encryption Success" severity note;
assert BLOCK_OUTPUT_5 = X"44c8fc20b9dfa07a" report "UUT5 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_6 /= X"602807a462b469063d8ff082" report "UUT6 Encryption Success" severity note;
assert BLOCK_OUTPUT_6 = X"602807a462b469063d8ff082" report "UUT6 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_7 /= X"ecad1c6c451e3f59c5db1ae9" report "UUT7 Encryption Success" severity note;
assert BLOCK_OUTPUT_7 = X"ecad1c6c451e3f59c5db1ae9" report "UUT7 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_8 /= X"49681b1e1e54fe3f65aa832af84e0bbc" report "UUT8 Encryption Success" severity note;
assert BLOCK_OUTPUT_8 = X"49681b1e1e54fe3f65aa832af84e0bbc" report "UUT8 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_9 /= X"c4ac61effcdc0d4f6c9c8d6e2597b85b" report "UUT9 Encryption Success" severity note;
assert BLOCK_OUTPUT_9 = X"c4ac61effcdc0d4f6c9c8d6e2597b85b" report "UUT9 Encryption Failed" severity failure;
assert BLOCK_OUTPUT_10 /= X"8d2b5579afc8a3a03bf72a87efe7b868" report "UUT10 Encryption Success" severity note;
assert BLOCK_OUTPUT_10 = X"8d2b5579afc8a3a03bf72a87efe7b868" report "UUT10 Encryption Failed" severity failure;
BLOCK_INPUT_1 <= X"c69be9bb";
BLOCK_INPUT_2 <= X"dae5ac292cac";
BLOCK_INPUT_3 <= X"6e06a5acf156";
BLOCK_INPUT_4 <= X"5ca2e27f111a8fc8";
BLOCK_INPUT_5 <= X"44c8fc20b9dfa07a";
BLOCK_INPUT_6 <= X"602807a462b469063d8ff082";
BLOCK_INPUT_7 <= X"ecad1c6c451e3f59c5db1ae9";
BLOCK_INPUT_8 <= X"49681b1e1e54fe3f65aa832af84e0bbc";
BLOCK_INPUT_9 <= X"c4ac61effcdc0d4f6c9c8d6e2597b85b";
BLOCK_INPUT_10 <= X"8d2b5579afc8a3a03bf72a87efe7b868";
CONTROL <= "10";
wait for SYS_CLK_period*3;
CONTROL <= "00";
wait for SYS_CLK_period*100;
assert BLOCK_OUTPUT_1 /= X"65656877" report "UUT1 Decryption Success" severity note;
assert BLOCK_OUTPUT_1 = X"65656877" report "UUT1 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_2 /= X"6120676e696c" report "UUT2 Decryption Success" severity note;
assert BLOCK_OUTPUT_2 = X"6120676e696c" report "UUT2 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_3 /= X"72696320646e" report "UUT3 Decryption Success" severity note;
assert BLOCK_OUTPUT_3 = X"72696320646e" report "UUT3 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_4 /= X"6f7220676e696c63" report "UUT4 Decryption Success" severity note;
assert BLOCK_OUTPUT_4 = X"6f7220676e696c63" report "UUT4 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_5 /= X"656b696c20646e75" report "UUT5 Decryption Success" severity note;
assert BLOCK_OUTPUT_5 = X"656b696c20646e75" report "UUT5 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_6 /= X"2072616c6c69702065687420" report "UUT6 Decryption Success" severity note;
assert BLOCK_OUTPUT_6 = X"2072616c6c69702065687420" report "UUT6 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_7 /= X"74616874207473756420666f" report "UUT7 Decryption Success" severity note;
assert BLOCK_OUTPUT_7 = X"74616874207473756420666f" report "UUT7 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_8 /= X"63736564207372656c6c657661727420" report "UUT8 Decryption Success" severity note;
assert BLOCK_OUTPUT_8 = X"63736564207372656c6c657661727420" report "UUT8 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_9 /= X"206572656874206e6568772065626972" report "UUT9 Decryption Success" severity note;
assert BLOCK_OUTPUT_9 = X"206572656874206e6568772065626972" report "UUT9 Decryption Failed" severity failure;
assert BLOCK_OUTPUT_10 /= X"74206e69206d6f6f6d69732061207369" report "UUT10 Decryption Success" severity note;
assert BLOCK_OUTPUT_10 = X"74206e69206d6f6f6d69732061207369" report "UUT10 Decryption Failed" severity failure;
wait;
end process;
END behavior;
|
mit
|
Given-Jiang/Gray_Processing
|
Gray_Processing_dspbuilder/db/alt_dspbuilder_testbench_salt.vhd
|
10
|
667
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_testbench_salt is
end entity alt_dspbuilder_testbench_salt;
architecture rtl of alt_dspbuilder_testbench_salt is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
mit
|
inmcm/Simon_Speck_Ciphers
|
VHDL/AXI_IP/Speck_Block_Cipher_1.0/src/Speck.vhd
|
3
|
11909
|
-- Speck.vhd
-- Copyright 2016 Michael Calvin McCoy
-- [email protected]
-- see LICENSE.md
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use work.SPECK_CONSTANTS.all;
entity SPECK_CIPHER is
Generic(KEY_SIZE : integer range 0 to 256 := 256;
BLOCK_SIZE : integer range 0 to 128 := 128;
ROUND_LIMIT: integer range 0 to 34 := 34);
Port (SYS_CLK,RST : in std_logic;
BUSY : out std_logic;
CONTROL : in std_logic_vector(1 downto 0);
KEY : in std_logic_vector (KEY_SIZE - 1 downto 0);
BLOCK_INPUT : in std_logic_vector (BLOCK_SIZE - 1 downto 0);
BLOCK_OUTPUT : out std_logic_vector (BLOCK_SIZE - 1 downto 0));
end SPECK_CIPHER;
architecture Behavioral of SPECK_CIPHER is
-------------------------------------------------------------
-- Cipher Constants
constant WORD_SIZE : integer range 0 to 64 := BLOCK_SIZE / 2;
constant KEY_WORDS_M : integer range 0 to 4 := KEY_SIZE / WORD_SIZE;
constant ALPHA_SHIFT : integer range 0 to 15 := Alpha_Lookup(KEY_SIZE, BLOCK_SIZE);
constant BETA_SHIFT : integer range 0 to 3 := Beta_Lookup(KEY_SIZE, BLOCK_SIZE);
-------------------------------------------------------------
-- Key Schedule Storage Array
type ARRAY_ROUNDxWORDSIZE is array(0 to (ROUND_LIMIT - 1)) of std_logic_vector(WORD_SIZE - 1 downto 0);
signal key_schedule: ARRAY_ROUNDxWORDSIZE;
signal round_key : std_logic_vector(WORD_SIZE - 1 downto 0);
type ARRAY_PARTKEYxWORD is array (0 to KEY_WORDS_M-1) of std_logic_vector(WORD_SIZE - 1 downto 0);
signal key_l : ARRAY_PARTKEYxWORD;
signal key_feedback : ARRAY_PARTKEYxWORD;
signal key_gen_round_output : STD_LOGIC_VECTOR(BLOCK_SIZE - 1 downto 0);
------------------------------------------------------
-- Fiestel Structure Signals
signal b_buf : STD_LOGIC_VECTOR(WORD_SIZE - 1 downto 0);
signal a_buf : STD_LOGIC_VECTOR(WORD_SIZE - 1 downto 0);
signal encryption_round_output : STD_LOGIC_VECTOR(BLOCK_SIZE - 1 downto 0);
signal decryption_round_output : STD_LOGIC_VECTOR(BLOCK_SIZE - 1 downto 0);
--------------------------------------------------------
--------------------------------------------------------
-- State Machine Signals
type state is (Reset,Idle,Key_Schedule_Generation_Run,Key_Schedule_Generation_Finish,
Cipher_Start,Cipher_Run,Cipher_Finish_1,Cipher_Finish_2,Cipher_Latch);
signal pr_state,nx_state : state;
--------------------------------------------------------
--------------------------------------------------------
-- Round Counting Signals
signal round_count : integer range 0 to (ROUND_LIMIT - 1);
signal inv_round_count : integer range 0 to (ROUND_LIMIT - 1);
signal round_count_mux : integer range 0 to (ROUND_LIMIT - 1);
signal cipher_direction : std_logic;
--------------------------------------------------------
function Encrypt_Round(b, a, key_i : std_logic_vector(WORD_SIZE -1 downto 0)) return std_logic_vector is
variable b_unsigned : unsigned(WORD_SIZE - 1 downto 0);
variable a_unsigned : unsigned(WORD_SIZE - 1 downto 0);
variable r_shift_alpha : unsigned(WORD_SIZE - 1 downto 0);
variable l_shift_beta : unsigned(WORD_SIZE - 1 downto 0);
variable adder: unsigned(WORD_SIZE - 1 downto 0);
variable key_xor : unsigned(WORD_SIZE - 1 downto 0);
variable cross_xor : unsigned(WORD_SIZE - 1 downto 0);
variable encrypt_output : std_logic_vector(BLOCK_SIZE - 1 downto 0);
begin
b_unsigned := unsigned(b);
a_unsigned := unsigned(a);
r_shift_alpha := b_unsigned(ALPHA_SHIFT - 1 downto 0) & b_unsigned(WORD_SIZE -1 downto ALPHA_SHIFT);
l_shift_beta := a_unsigned(WORD_SIZE - (BETA_SHIFT + 1) downto 0) & a_unsigned((WORD_SIZE -1) downto (WORD_SIZE - BETA_SHIFT));
adder := r_shift_alpha + a_unsigned;
key_xor := adder xor unsigned(key_i);
cross_xor := l_shift_beta xor key_xor;
encrypt_output := std_logic_vector(key_xor) & std_logic_vector(cross_xor);
return encrypt_output;
end Encrypt_Round;
function Decrypt_Round(b, a, key_i : std_logic_vector(WORD_SIZE -1 downto 0)) return std_logic_vector is
variable b_unsigned : unsigned(WORD_SIZE - 1 downto 0);
variable a_unsigned : unsigned(WORD_SIZE - 1 downto 0);
variable l_shift_alpha : unsigned(WORD_SIZE - 1 downto 0);
variable r_shift_beta : unsigned(WORD_SIZE - 1 downto 0);
variable subtractor: unsigned(WORD_SIZE - 1 downto 0);
variable key_xor : unsigned(WORD_SIZE - 1 downto 0);
variable cross_xor : unsigned(WORD_SIZE - 1 downto 0);
variable decrypt_output : std_logic_vector(BLOCK_SIZE - 1 downto 0);
begin
b_unsigned := unsigned(b);
a_unsigned := unsigned(a);
cross_xor := b_unsigned xor a_unsigned;
r_shift_beta := cross_xor(BETA_SHIFT - 1 downto 0) & cross_xor(WORD_SIZE -1 downto BETA_SHIFT);
key_xor := b_unsigned xor unsigned(key_i);
subtractor := key_xor - r_shift_beta;
l_shift_alpha := subtractor(WORD_SIZE - (ALPHA_SHIFT + 1) downto 0) & subtractor((WORD_SIZE -1) downto (WORD_SIZE - ALPHA_SHIFT));
decrypt_output := std_logic_vector(l_shift_alpha) & std_logic_vector(r_shift_beta);
return decrypt_output;
end Decrypt_Round;
begin
----------------------------------------------------------------------
-- State Machine Processes
----------------------------------------------------------------------
State_Machine_Head : process (SYS_CLK) ----State Machine Master Control
begin
if (SYS_CLK'event and SYS_CLK='1') then
if (RST = '1') then
pr_state <= RESET;
else
pr_state <= nx_state;
end if;
end if;
end process; -- State_Machine_Head
State_Machine_Body : process (CONTROL, round_count, pr_state) ---State Machine State Definitions
begin
case pr_state is
when Reset => --Master Reset State
nx_state <= Idle;
when Idle =>
if (CONTROL = "01") then
nx_state <= Key_Schedule_Generation_Run;
elsif (CONTROL = "11" or CONTROL = "10") then
nx_state <= Cipher_Start;
else
nx_state <= Idle;
end if;
when Key_Schedule_Generation_Run =>
if (round_count = ROUND_LIMIT - 2) then
nx_state <= Key_Schedule_Generation_Finish;
else
nx_state <= Key_Schedule_Generation_Run;
end if;
when Key_Schedule_Generation_Finish =>
nx_state <= Idle;
when Cipher_Start =>
nx_state <= Cipher_Run;
when Cipher_Run =>
if (round_count = ROUND_LIMIT - 2) then
nx_state <= Cipher_Finish_1;
else
nx_state <= Cipher_Run;
end if;
when Cipher_Finish_1 =>
nx_state <= Cipher_Finish_2;
when Cipher_Finish_2 =>
nx_state <= Cipher_Latch;
when Cipher_Latch =>
nx_state <= Idle;
end case;
end process;
----------------------------------------------------------------------
-- END State Machine Processes
----------------------------------------------------------------------
----------------------------------------------------------------------
-- Register Processes
----------------------------------------------------------------------
Cipher_Direction_Flag : process(SYS_CLK)
begin
if SYS_CLK'event and SYS_CLK = '1' then
if (pr_state = Reset) then
cipher_direction <= '0';
elsif (pr_state = Idle) then
cipher_direction <= CONTROL(0);
end if ;
end if;
end process;
Busy_Flag_Generator : process(SYS_CLK)
begin
if SYS_CLK'event and SYS_CLK = '1' then
if (pr_state = Reset or (pr_state = Idle and CONTROL /= "00")) then
BUSY <= '1';
elsif ((pr_state = Idle and CONTROL = "00") or pr_state = Cipher_Latch or pr_state = Key_Schedule_Generation_Finish) then
BUSY <= '0';
end if;
end if;
end process ; -- Busy_Flag_Generator
Key_Schedule_Generator : process(SYS_CLK)
begin
if SYS_CLK'event and SYS_CLK = '1' then
if (pr_state = Idle) then
Init_Gen_Regs : for i in 0 to (KEY_WORDS_M -1) loop
key_l(i) <= key(((i + 1) * WORD_SIZE) - 1 downto (i * WORD_SIZE));
end loop ; -- Update_Gen_Regs
elsif (pr_state = Key_Schedule_Generation_Run or pr_state = Key_Schedule_Generation_Finish) then
for i in 0 to (KEY_WORDS_M - 1) loop
key_l(i) <= key_feedback(i);
end loop;
end if;
end if;
end process ; -- Key_Schedule_Generator
Main_Cipher_Process : process(SYS_CLK)
begin
if SYS_CLK'event and SYS_CLK = '1' then
-- Load for Encryption/Decryption
if (pr_state = Idle) then
if (CONTROL(1) = '1') then
a_buf <= BLOCK_INPUT(WORD_SIZE - 1 downto 0);
b_buf <= BLOCK_INPUT(BLOCK_SIZE - 1 downto WORD_SIZE);
end if;
-- Run Cipher Engine
elsif (pr_state = Cipher_Run or pr_state = Cipher_Finish_1 or pr_state = Cipher_Finish_2) then
if (cipher_direction = '1') then -- Encryption
a_buf <= encryption_round_output(WORD_SIZE - 1 downto 0);
b_buf <= encryption_round_output(BLOCK_SIZE - 1 downto WORD_SIZE);
else -- Decryption
a_buf <= decryption_round_output(WORD_SIZE - 1 downto 0);
b_buf <= decryption_round_output(BLOCK_SIZE - 1 downto WORD_SIZE);
end if;
end if;
end if;
end process ;
Output_Buffer : process(SYS_CLK)
begin
if SYS_CLK'event and SYS_CLK = '1' then
if (pr_state = Cipher_Latch) then
BLOCK_OUTPUT <= b_buf & a_buf;
end if;
end if;
end process ; -- Output_Buffer
----------------------------------------------------------------------
-- END Register Processes
----------------------------------------------------------------------
----------------------------------------------------------------------
-- RAM Processes
----------------------------------------------------------------------
Key_Schedule_Array: process (SYS_CLK)
begin
if (SYS_CLK'event and SYS_CLK = '1') then
round_key <= key_schedule(round_count_mux);
if (pr_state = Key_Schedule_Generation_Run or pr_state = Key_Schedule_Generation_Finish) then
key_schedule(round_count) <= key_l(0);
end if;
end if;
end process;
----------------------------------------------------------------------
-- End RAM Processes
----------------------------------------------------------------------
----------------------------------------------------------------------
-- Counter Processes
----------------------------------------------------------------------
Round_Counter : process(SYS_CLK)
begin
if (SYS_CLK'event and SYS_CLK = '1') then
if (pr_state = Reset) then
round_count <= 0;
inv_round_count <= 0;
elsif (pr_state = Idle) then
round_count <= 0;
inv_round_count <= ROUND_LIMIT - 1;
elsif (pr_state = Cipher_Start or pr_state = Cipher_Run or pr_state = Key_Schedule_Generation_Run) then
round_count <= round_count + 1;
inv_round_count <= inv_round_count - 1;
end if ;
end if ;
end process;
----------------------------------------------------------------------
-- END Counter Processes
----------------------------------------------------------------------
----------------------------------------------------------------------
-- Async Signals
----------------------------------------------------------------------
round_count_mux <= round_count when cipher_direction = '1' else inv_round_count;
key_gen_round_output <= Encrypt_Round(key_l(1), key_l(0), std_logic_vector(to_unsigned(round_count, WORD_SIZE)));
encryption_round_output <= Encrypt_Round(b_buf, a_buf, round_key);
decryption_round_output <= Decrypt_Round(b_buf, a_buf, round_key);
key_feedback(0) <= key_gen_round_output(WORD_SIZE - 1 downto 0);
key_feedback(KEY_WORDS_M - 1) <= key_gen_round_output(BLOCK_SIZE - 1 downto WORD_SIZE);
Keys_3 : if (KEY_WORDS_M = 3) generate
begin
key_feedback(1) <= key_l(2);
end generate;
Keys_4 : if (KEY_WORDS_M = 4) generate
begin
key_feedback(1) <= key_l(2);
key_feedback(2) <= key_l(3);
end generate;
end Behavioral;
|
mit
|
Given-Jiang/Gray_Processing
|
Gray_Processing_dspbuilder/hdl/alt_dspbuilder_sMuxAltr.vhd
|
20
|
3446
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library altera;
use altera.alt_dspbuilder_package.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity alt_dspbuilder_sMuxAltr is
generic ( lpm_pipeline : natural:=0;
lpm_size : positive:=5;
lpm_widths : positive:=3;
lpm_width : positive:=8;
SelOneHot : natural:=0);
PORT ( clock : in std_logic ;
aclr : in std_logic := '0';
user_aclr : in std_logic := '0';
ena : in std_logic := '1';
data : in std_logic_vector (lpm_width*lpm_size-1 downto 0);
sel : in std_logic_vector (lpm_widths-1 downto 0);
result : out std_logic_vector (lpm_width-1 downto 0));
end alt_dspbuilder_sMuxAltr;
architecture synth of alt_dspbuilder_sMuxAltr is
function salive( ipp : integer; w : natural ) return std_logic_vector is
variable sxbus : std_logic_vector(w-1 downto 0);
begin
for i in 0 to w-1 loop
if ipp=i then
sxbus(i) :='1';
else
sxbus(i) :='0';
end if;
end loop;
return sxbus;
end;
signal selint : std_logic_vector(nbitnecessary(lpm_size)-1 downto 0);
signal dataa : std_logic_2d (lpm_size-1 downto 0, lpm_width-1 downto 0);
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
gnoh:if SelOneHot=0 generate
selint <= sel;
end generate gnoh;
g_one_hot:if SelOneHot>0 generate
gi:for i in 0 to lpm_size-1 generate
selint <= int2ustd(i,nbitnecessary(lpm_size)) when sel = salive(i, lpm_size) else (others=>'Z');
end generate gi;
end generate g_one_hot;
g2d:for i in 1 to lpm_size generate
gw:for j in 0 to lpm_width-1 generate
dataa(i-1,j) <= data(j+(i-1)*lpm_width);
end generate gw;
end generate g2d;
gp:if lpm_pipeline>0 generate
U0 : lpm_mux generic map ( lpm_pipeline => lpm_pipeline,
lpm_size => lpm_size,
lpm_widths => nbitnecessary(lpm_size),
lpm_width => lpm_width,
lpm_type => "LPM_MUX")
port map ( sel => selint,
clken => ena,
aclr => aclr_i,
clock => clock,
data => dataa,
result => result);
end generate gp;
gc:if lpm_pipeline=0 generate
U0 : lpm_mux generic map ( lpm_size => lpm_size,
lpm_widths => nbitnecessary(lpm_size),
lpm_width => lpm_width,
lpm_type => "LPM_MUX")
port map ( sel => selint,
data => dataa,
result => result);
end generate gc;
end synth;
|
mit
|
Given-Jiang/Gray_Processing
|
tb_Gray_Processing/db/alt_dspbuilder_constant_GNPXZ5JSVR.vhd
|
8
|
550
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNPXZ5JSVR is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "1000";
width : natural := 4);
port(
output : out std_logic_vector(3 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNPXZ5JSVR is
Begin
-- Constant
output <= "1000";
end architecture;
|
mit
|
Given-Jiang/Gray_Processing
|
Gray_Processing_dspbuilder/db/alt_dspbuilder_vcc_GN.vhd
|
20
|
373
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_vcc_GN is
port(
output : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_vcc_GN is
Begin
output <= '1';
end architecture;
|
mit
|
Given-Jiang/Gray_Processing
|
Gray_Processing_dspbuilder/hdl/alt_dspbuilder_vcc_GN.vhd
|
20
|
373
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_vcc_GN is
port(
output : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_vcc_GN is
Begin
output <= '1';
end architecture;
|
mit
|
Given-Jiang/Gray_Processing
|
tb_Gray_Processing/hdl/alt_dspbuilder_delay_GNHYCSAEGT.vhd
|
16
|
1037
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNHYCSAEGT is
generic ( ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "0";
width : positive := 1);
port(
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
input : in std_logic_vector((width)-1 downto 0);
output : out std_logic_vector((width)-1 downto 0);
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_delay_GNHYCSAEGT is
Begin
-- Delay Element
Delay1i : alt_dspbuilder_SDelay generic map (
LPM_WIDTH => 1,
LPM_DELAY => 1,
SequenceLength => 1,
SequenceValue => "1")
port map (
dataa => input,
clock => clock,
ena => ena,
sclr => sclr,
aclr => aclr,
user_aclr => '0',
result => output);
end architecture;
|
mit
|
Given-Jiang/Gray_Processing
|
Gray_Processing_dspbuilder/db/alt_dspbuilder_delay_GNHYCSAEGT.vhd
|
16
|
1037
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNHYCSAEGT is
generic ( ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "0";
width : positive := 1);
port(
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
input : in std_logic_vector((width)-1 downto 0);
output : out std_logic_vector((width)-1 downto 0);
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_delay_GNHYCSAEGT is
Begin
-- Delay Element
Delay1i : alt_dspbuilder_SDelay generic map (
LPM_WIDTH => 1,
LPM_DELAY => 1,
SequenceLength => 1,
SequenceValue => "1")
port map (
dataa => input,
clock => clock,
ena => ena,
sclr => sclr,
aclr => aclr,
user_aclr => '0',
result => output);
end architecture;
|
mit
|
Given-Jiang/Gray_Processing
|
tb_Gray_Processing/hdl/alt_dspbuilder_vecseq.vhd
|
20
|
2951
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_vecseq is
generic (
SequenceLength : positive :=15;
SequenceValue : std_logic_vector := "100001110001001"
);
port (
clock : in std_logic ;
ena : in std_logic :='1';
sclr : in std_logic :='0';
aclr : in std_logic :='0';
yout : out std_logic
);
end alt_dspbuilder_vecseq;
architecture seq_SYNTH of alt_dspbuilder_vecseq is
signal clr_signal : STD_LOGIC;
signal lclr_signal : STD_LOGIC;
signal counter : std_logic_vector(ToNatural(nbitnecessary(SequenceLength)-1) downto 0);
signal yout_int : STD_LOGIC;
signal yout_comb : STD_LOGIC;
begin
u0: alt_dspbuilder_sAltrBitPropagate generic map(QTB=>DSPBuilderQTB, QTB_PRODUCT => DSPBuilderProduct, QTB_VERSION => DSPBuilderVersion)
port map (d => yout_int, r => yout);
fixed_constant:if SequenceLength=1 generate
yout_int <=SequenceValue(0);
end generate fixed_constant;
resetable_sequence:if SequenceLength>1 generate
process(clock, aclr)
begin
if aclr='1' then
yout_int <= '0';
counter <= (OTHERS => '0');
elsif clock'event and clock='1' then
if sclr='1' then
yout_int <= '0';
counter <= (OTHERS => '0');
elsif ena='1' then
if counter < int2ustd(SequenceLength-1 ,nbitnecessary(SequenceLength)+1) then
counter <= counter + '1';
else
counter <= (OTHERS => '0');
end if;
yout_int <= yout_comb;
end if;
end if;
end process;
gen:for i in 0 to SequenceLength-1 generate
yout_comb <= SequenceValue(i) when (counter=int2ustd(i,nbitnecessary(SequenceLength)+1)) else 'Z';
end generate;
end generate resetable_sequence;
end seq_SYNTH;
|
mit
|
Given-Jiang/Gray_Processing
|
tb_Gray_Processing/db/alt_dspbuilder_testbench_salt_GNDBMPYDND.vhd
|
20
|
1717
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GNDBMPYDND is
generic ( XFILE : string := "default");
port(
clock : in std_logic;
aclr : in std_logic;
output : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_testbench_salt_GNDBMPYDND is
function to_std_logic (B: character) return std_logic is
begin
case B is
when '0' => return '0';
when '1' => return '1';
when OTHERS => return 'X';
end case;
end;
function to_std_logic_vector (B: string) return
std_logic_vector is
variable res: std_logic_vector (B'range);
begin
for i in B'range loop
case B(i) is
when '0' => res(i) := '0';
when '1' => res(i) := '1';
when OTHERS => res(i) := 'X';
end case;
end loop;
return res;
end;
procedure skip_type_header(file f:text) is
use STD.textio.all;
variable in_line : line;
begin
readline(f, in_line);
end procedure skip_type_header ;
file InputFile : text open read_mode is XFILE;
Begin
-- salt generator
skip_type_header(InputFile);
-- Reading Simulink Input
Input_pInput:process(clock, aclr)
variable s : string(1 to 1) ;
variable ptr : line ;
begin
if (aclr = '1') then
output <= '0';
elsif (not endfile(InputFile)) then
if clock'event and clock='0' then
readline(Inputfile, ptr);
read(ptr, s);
output <= to_std_logic(s(1));
end if ;
end if ;
end process ;
end architecture;
|
mit
|
Given-Jiang/Gray_Processing
|
Gray_Processing_dspbuilder/db/alt_dspbuilder_bus_concat_GN55ETJ4VI.vhd
|
12
|
654
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GN55ETJ4VI is
generic ( widthB : natural := 16;
widthA : natural := 8);
port(
a : in std_logic_vector((widthA)-1 downto 0);
aclr : in std_logic;
b : in std_logic_vector((widthB)-1 downto 0);
clock : in std_logic;
output : out std_logic_vector((widthA+widthB)-1 downto 0));
end entity;
architecture rtl of alt_dspbuilder_bus_concat_GN55ETJ4VI is
Begin
output <= a & b;
end architecture;
|
mit
|
Given-Jiang/Gray_Processing
|
tb_Gray_Processing/db/alt_dspbuilder_bus_concat_GN55ETJ4VI.vhd
|
12
|
654
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GN55ETJ4VI is
generic ( widthB : natural := 16;
widthA : natural := 8);
port(
a : in std_logic_vector((widthA)-1 downto 0);
aclr : in std_logic;
b : in std_logic_vector((widthB)-1 downto 0);
clock : in std_logic;
output : out std_logic_vector((widthA+widthB)-1 downto 0));
end entity;
architecture rtl of alt_dspbuilder_bus_concat_GN55ETJ4VI is
Begin
output <= a & b;
end architecture;
|
mit
|
Pajeh/mips1
|
test/vhdl/tb_execution.vhd
|
1
|
3300
|
-- revision history:
-- 05.08.2015 Patrick Appenheimer created
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.ALL;
library WORK;
use WORK.cpu_pack.all;
entity tb_execution is
end entity tb_execution;
architecture behav_tb_execution of tb_execution is
-- -------- SIMULATION CONSTANTS -----
constant CLK_TIME : time := 2500 ps;
constant RST_TIME : time := 30 ns;
-- -------- ALU INTERFACE -----------------
signal clk : std_logic := '0';
signal rst : std_logic;
signal test_alu_result : std_logic_vector(31 downto 0);
signal test_data_out : std_logic_vector(31 downto 0);
signal test_destreg_out : std_logic_vector(4 downto 0);
signal test_alu_zero_out : std_logic_vector(0 downto 0);
signal test_a_in : std_logic_vector(31 downto 0);
signal test_b_in : std_logic_vector(31 downto 0);
signal test_destreg_in : std_logic_vector(4 downto 0);
signal test_imm_in : std_logic_vector(31 downto 0);
signal test_ip_in : std_logic_vector(31 downto 0);
signal test_shift_in : std_logic_vector(4 downto 0);
signal test_mux1_control_in : std_logic_vector(1 downto 0);
signal test_mux2_control_in : std_logic_vector(1 downto 0);
signal test_alu_instruction_in : std_logic_vector(5 downto 0);
-- ------ SIMULATION CONTROL ---------------
signal sim_finish : std_logic;
begin
-- GENERAL CONTROL SIGNALS
clk <= not clk after CLK_TIME;
rst <= '1', '0' after RST_TIME;
-- ALU
u1_execution: entity work.execution(behave)
PORT MAP(clk, rst, test_alu_result, test_data_out, test_destreg_out, test_alu_zero_out,
test_a_in, test_b_in, test_destreg_in, test_imm_in, test_ip_in, test_shift_in, test_mux1_control_in,
test_mux2_control_in, test_alu_instruction_in);
-- TEST PROCESS
test_process:
process
begin
sim_finish <= '0';
test_shift_in <= b"1_0101";
test_a_in <= x"0000_0002";
test_b_in <= x"0000_0003";
test_destreg_in <= b"0_1111";
test_imm_in <= x"0000_000A";
test_ip_in <= x"0000_0004";
test_alu_instruction_in <= b"10_0000";
wait for 1 ns;
test_mux1_control_in <= b"00";
test_mux2_control_in <= b"00";
wait for 1 ns;
test_mux1_control_in <= b"00";
test_mux2_control_in <= b"01";
wait for 1 ns;
test_mux1_control_in <= b"00";
test_mux2_control_in <= b"10";
wait for 1 ns;
test_mux1_control_in <= b"01";
test_mux2_control_in <= b"00";
wait for 1 ns;
test_mux1_control_in <= b"01";
test_mux2_control_in <= b"01";
wait for 1 ns;
test_mux1_control_in <= b"01";
test_mux2_control_in <= b"10";
wait for 1 ns;
test_mux1_control_in <= b"10";
test_mux2_control_in <= b"00";
wait for 1 ns;
test_mux1_control_in <= b"10";
test_mux2_control_in <= b"01";
wait for 1 ns;
test_mux1_control_in <= b"10";
test_mux2_control_in <= b"10";
wait for 1 ns;
sim_finish <= '1';
wait;
end process;
end architecture behav_tb_execution;
|
mit
|
plac-lab/TMIIaTest
|
Firmware/src/gig_eth/KC705/gig_eth.vhd
|
2
|
47994
|
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_example_design.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2004-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This is the Verilog example design for the Tri-Mode
-- Ethernet MAC core. It is intended that this example design
-- can be quickly adapted and downloaded onto an FPGA to provide
-- a real hardware test environment.
--
-- This level:
--
-- * Instantiates the FIFO Block wrapper, containing the
-- block level wrapper and an RX and TX FIFO with an
-- AXI-S interface;
--
-- * Instantiates a simple AXI-S example design,
-- providing an address swap and a simple
-- loopback function;
--
-- * Instantiates transmitter clocking circuitry
-- -the User side of the FIFOs are clocked at gtx_clk
-- at all times
--
-- * Instantiates a state machine which drives the AXI Lite
-- interface to bring the TEMAC up in the correct state
--
-- * Serializes the Statistics vectors to prevent logic being
-- optimized out
--
-- * Ties unused inputs off to reduce the number of IO
--
-- Please refer to the Datasheet, Getting Started Guide, and
-- the Tri-Mode Ethernet MAC User Gude for further information.
--
--
-- --------------------------------------------------
-- | EXAMPLE DESIGN WRAPPER |
-- | |
-- | |
-- | ------------------- ------------------- |
-- | | | | | |
-- | | Clocking | | Resets | |
-- | | | | | |
-- | ------------------- ------------------- |
-- | -------------------------------------|
-- | |FIFO BLOCK WRAPPER |
-- | | |
-- | | |
-- | | ----------------------|
-- | | | SUPPORT LEVEL |
-- | -------- | | |
-- | | | | | |
-- | | AXI |->|------------->| |
-- | | LITE | | | |
-- | | SM | | | |
-- | | |<-|<-------------| |
-- | | | | | |
-- | -------- | | |
-- | | | |
-- | -------- | ---------- | |
-- | | | | | | | |
-- | | |->|->| |->| |
-- | | PAT | | | | | |
-- | | GEN | | | | | |
-- | |(ADDR | | | AXI-S | | |
-- | | SWAP)| | | FIFO | | |
-- | | | | | | | |
-- | | | | | | | |
-- | | | | | | | |
-- | | |<-|<-| |<-| |
-- | | | | | | | |
-- | -------- | ---------- | |
-- | | | |
-- | | ----------------------|
-- | -------------------------------------|
-- --------------------------------------------------
--------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.com5402pkg.all;
--------------------------------------------------------------------------------
-- The entity declaration for the example_design level wrapper.
--------------------------------------------------------------------------------
entity gig_eth is
port (
-- asynchronous reset
glbl_rst : in std_logic;
-- clocks
gtx_clk : in std_logic; -- 125MHz
ref_clk : in std_logic; -- 200MHz
-- PHY interface
phy_resetn : out std_logic;
-- RGMII Interface
------------------
rgmii_txd : out std_logic_vector(3 downto 0);
rgmii_tx_ctl : out std_logic;
rgmii_txc : out std_logic;
rgmii_rxd : in std_logic_vector(3 downto 0);
rgmii_rx_ctl : in std_logic;
rgmii_rxc : in std_logic;
-- MDIO Interface
-----------------
mdio : inout std_logic;
mdc : out std_logic;
-- TCP
MAC_ADDR : IN std_logic_vector(47 DOWNTO 0);
IPv4_ADDR : IN std_logic_vector(31 DOWNTO 0);
IPv6_ADDR : IN std_logic_vector(127 DOWNTO 0);
SUBNET_MASK : IN std_logic_vector(31 DOWNTO 0);
GATEWAY_IP_ADDR : IN std_logic_vector(31 DOWNTO 0);
TCP_CONNECTION_RESET : IN std_logic;
TX_TDATA : IN std_logic_vector(7 downto 0);
TX_TVALID : IN std_logic;
TX_TREADY : OUT std_logic;
RX_TDATA : OUT std_logic_vector(7 downto 0);
RX_TVALID : OUT std_logic;
RX_TREADY : IN std_logic;
-- FIFO
TCP_USE_FIFO : IN std_logic;
TX_FIFO_WRCLK : IN std_logic;
TX_FIFO_Q : IN std_logic_vector(31 downto 0);
TX_FIFO_WREN : IN std_logic;
TX_FIFO_FULL : OUT std_logic;
RX_FIFO_RDCLK : IN std_logic;
RX_FIFO_Q : OUT std_logic_vector(31 downto 0);
RX_FIFO_RDEN : IN std_logic;
RX_FIFO_EMPTY : OUT std_logic
);
end gig_eth;
architecture wrapper of gig_eth is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of wrapper : architecture is "yes";
COMPONENT COM5402 IS
GENERIC (
CLK_FREQUENCY : integer := 125;
-- CLK frequency in MHz. Needed to compute actual delays.
TX_IDLE_TIMEOUT : integer RANGE 0 TO 50 := 50;
-- inactive input timeout, expressed in 4us units. -- 50*4us = 200us
-- Controls the transmit stream segmentation: data in the elastic buffer will be transmitted if
-- no input is received within TX_IDLE_TIMEOUT, without waiting for the transmit frame to be filled with MSS data bytes.
SIMULATION : std_logic := '0'
-- 1 during simulation with Wireshark .cap file, '0' otherwise
-- Wireshark many not be able to collect offloaded checksum computations.
-- when SIMULATION = '1': (a) IP header checksum is valid if 0000,
-- (b) TCP checksum computation is forced to a valid 00001 irrespective of the 16-bit checksum
-- captured by Wireshark.
);
PORT (
--//-- CLK, RESET
CLK : IN std_logic;
-- All signals are synchronous with CLK
-- CLK must be a global clock 125 MHz or faster to match the Gbps MAC speed.
ASYNC_RESET : IN std_logic; -- to be phased out. replace with SYNC_RESET
SYNC_RESET : IN std_logic;
--//-- CONFIGURATION
-- configuration signals are synchonous with CLK
-- Synchronous with CLK clock.
MAC_ADDR : IN std_logic_vector(47 DOWNTO 0);
IPv4_ADDR : IN std_logic_vector(31 DOWNTO 0);
IPv6_ADDR : IN std_logic_vector(127 DOWNTO 0);
SUBNET_MASK : IN std_logic_vector(31 DOWNTO 0);
GATEWAY_IP_ADDR : IN std_logic_vector(31 DOWNTO 0);
-- local IP address. 4 bytes for IPv4, 16 bytes for IPv6
-- Natural order (MSB) 172.16.1.128 (LSB) as transmitted in the IP frame.
--// User-initiated connection reset for stream I
CONNECTION_RESET : IN std_logic_vector((NTCPSTREAMS-1) DOWNTO 0);
--//-- Protocol -> Transmit MAC Interface
-- 32-bit CRC is automatically appended by the MAC layer. User should not supply it.
-- Synchonous with the user-side CLK
MAC_TX_DATA : OUT std_logic_vector(7 DOWNTO 0);
-- MAC reads the data at the rising edge of CLK when MAC_TX_DATA_VALID = '1'
MAC_TX_DATA_VALID : OUT std_logic;
-- data valid
MAC_TX_SOF : out std_logic;
-- start of frame: '1' when sending the first byte.
MAC_TX_EOF : OUT std_logic;
-- '1' when sending the last byte in a packet to be transmitted.
-- Aligned with MAC_TX_DATA_VALID
MAC_TX_CTS : IN std_logic;
-- MAC-generated Clear To Send flow control signal, indicating room in the
-- MAC tx elastic buffer for a complete maximum size frame 1518B.
-- The user should check that this signal is high before deciding to send
-- sending the next frame.
-- Note: MAC_TX_CTS may go low while the frame is transfered in. Ignore it as space is guaranteed
-- at the start of frame.
--//-- Receive MAC -> Protocol
-- Valid rx packets only: packets with bad CRC or invalid address are discarded.
-- The 32-bit CRC is always removed by the MAC layer.
-- Synchonous with the user-side CLK
MAC_RX_DATA : IN std_logic_vector(7 DOWNTO 0);
-- USER reads the data at the rising edge of CLK when MAC_RX_DATA_VALID = '1'
MAC_RX_DATA_VALID : IN std_logic;
-- data valid
MAC_RX_SOF : IN std_logic;
-- '1' when sending the first byte in a received packet.
-- Aligned with MAC_RX_DATA_VALID
MAC_RX_EOF : IN std_logic;
-- '1' when sending the last byte in a received packet.
-- Aligned with MAC_RX_DATA_VALID
--//-- Application <- UDP rx
UDP_RX_DATA : OUT std_logic_vector(7 DOWNTO 0);
UDP_RX_DATA_VALID : OUT std_logic;
UDP_RX_SOF : OUT std_logic;
UDP_RX_EOF : OUT std_logic;
-- 1 CLK pulse indicating that UDP_RX_DATA is the last byte in the UDP data field.
-- ALWAYS CHECK UDP_RX_DATA_VALID at the end of packet (UDP_RX_EOF = '1') to confirm
-- that the UDP packet is valid. External buffer may have to backtrack to the the last
-- valid pointer to discard an invalid UDP packet.
-- Reason: we only knows about bad UDP packets at the end.
UDP_RX_DEST_PORT_NO : IN std_logic_vector(15 DOWNTO 0);
--//-- Application -> UDP tx
UDP_TX_DATA : IN std_logic_vector(7 DOWNTO 0);
UDP_TX_DATA_VALID : IN std_logic;
UDP_TX_SOF : IN std_logic; -- 1 CLK-wide pulse to mark the first byte in the tx UDP frame
UDP_TX_EOF : IN std_logic; -- 1 CLK-wide pulse to mark the last byte in the tx UDP frame
UDP_TX_CTS : OUT std_logic;
UDP_TX_ACK : OUT std_logic; -- 1 CLK-wide pulse indicating that the previous UDP frame is being sent
UDP_TX_NAK : OUT std_logic; -- 1 CLK-wide pulse indicating that the previous UDP frame could not be sent
UDP_TX_DEST_IP_ADDR : IN std_logic_vector(127 DOWNTO 0);
UDP_TX_DEST_PORT_NO : IN std_logic_vector(15 DOWNTO 0);
UDP_TX_SOURCE_PORT_NO : IN std_logic_vector(15 DOWNTO 0);
--//-- Application <- TCP rx
-- NTCPSTREAMS can operate independently. Only one stream active at any given time.
-- Data is pushed out. Limited flow-control here. Receipient must be able to accept data
-- at any time (in other words, it is the receipient's responsibility to have elastic
-- buffer if needed).
TCP_RX_DATA : OUT SLV8xNTCPSTREAMStype;
TCP_RX_DATA_VALID : OUT std_logic_vector((NTCPSTREAMS-1) DOWNTO 0);
TCP_RX_RTS : OUT std_logic;
TCP_RX_CTS : IN std_logic;
-- Optional Clear-To-Send. pull to '1' when output flow control is unused.
-- WARNING: pulling CTS down will stop the flow for ALL streams.
--//-- Application -> TCP tx
-- NTCPSTREAMS can operate independently and concurrently. No scheduling arbitration needed here.
TCP_TX_DATA : IN SLV8xNTCPSTREAMStype;
TCP_TX_DATA_VALID : IN std_logic_vector((NTCPSTREAMS-1) DOWNTO 0);
TCP_TX_CTS : OUT std_logic_vector((NTCPSTREAMS-1) DOWNTO 0);
-- Clear To Send = transmit flow control.
-- App is responsible for checking the CTS signal before sending APP_DATA
--//-- TEST POINTS, COMSCOPE TRACES
CS1 : OUT std_logic_vector(7 DOWNTO 0);
CS1_CLK : OUT std_logic;
CS2 : OUT std_logic_vector(7 DOWNTO 0);
CS2_CLK : OUT std_logic;
TP : OUT std_logic_vector(10 DOWNTO 1)
);
END COMPONENT;
-- Must have programmable full with single-threshold of 61
-- out of total write-depth 64
COMPONENT fifo8to32
PORT (
rst : IN std_logic;
wr_clk : IN std_logic;
rd_clk : IN std_logic;
din : IN std_logic_vector(7 DOWNTO 0);
wr_en : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_vector(31 DOWNTO 0);
full : OUT std_logic;
prog_full : OUT std_logic;
empty : OUT std_logic
);
END COMPONENT;
COMPONENT fifo32to8
PORT (
rst : IN std_logic;
wr_clk : IN std_logic;
rd_clk : IN std_logic;
din : IN std_logic_vector(31 DOWNTO 0);
wr_en : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_vector(7 DOWNTO 0);
full : OUT std_logic;
empty : OUT std_logic
);
END COMPONENT;
------------------------------------------------------------------------------
-- Component Declaration for the Tri-Mode EMAC core FIFO Block wrapper
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_fifo_block
port(
gtx_clk : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Reference clock for IDELAYCTRL's
refclk : in std_logic;
-- Receiver Statistics Interface
-----------------------------------------
rx_mac_aclk : out std_logic;
rx_reset : out std_logic;
rx_statistics_vector : out std_logic_vector(27 downto 0);
rx_statistics_valid : out std_logic;
-- Receiver (AXI-S) Interface
------------------------------------------
rx_fifo_clock : in std_logic;
rx_fifo_resetn : in std_logic;
rx_axis_fifo_tdata : out std_logic_vector(7 downto 0);
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tready : in std_logic;
rx_axis_fifo_tlast : out std_logic;
-- Transmitter Statistics Interface
--------------------------------------------
tx_mac_aclk : out std_logic;
tx_reset : out std_logic;
tx_ifg_delay : in std_logic_vector(7 downto 0);
tx_statistics_vector : out std_logic_vector(31 downto 0);
tx_statistics_valid : out std_logic;
-- Transmitter (AXI-S) Interface
---------------------------------------------
tx_fifo_clock : in std_logic;
tx_fifo_resetn : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tready : out std_logic;
tx_axis_fifo_tlast : in std_logic;
-- MAC Control Interface
--------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(15 downto 0);
-- RGMII Interface
--------------------
rgmii_txd : out std_logic_vector(3 downto 0);
rgmii_tx_ctl : out std_logic;
rgmii_txc : out std_logic;
rgmii_rxd : in std_logic_vector(3 downto 0);
rgmii_rx_ctl : in std_logic;
rgmii_rxc : in std_logic;
-- RGMII Inband Status Registers
----------------------------------
inband_link_status : out std_logic;
inband_clock_speed : out std_logic_vector(1 downto 0);
inband_duplex_status : out std_logic;
-- MDIO Interface
-------------------
mdio : inout std_logic;
mdc : out std_logic;
-- AXI-Lite Interface
-----------------
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic;
s_axi_awaddr : in std_logic_vector(11 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(11 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic
);
end component;
------------------------------------------------------------------------------
-- Component Declaration for the AXI-Lite State machine
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_axi_lite_sm
port (
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic;
mac_speed : in std_logic_vector(1 downto 0);
update_speed : in std_logic;
serial_command : in std_logic;
serial_response : out std_logic;
phy_loopback : in std_logic;
s_axi_awaddr : out std_logic_vector(11 downto 0);
s_axi_awvalid : out std_logic;
s_axi_awready : in std_logic;
s_axi_wdata : out std_logic_vector(31 downto 0);
s_axi_wvalid : out std_logic;
s_axi_wready : in std_logic;
s_axi_bresp : in std_logic_vector(1 downto 0);
s_axi_bvalid : in std_logic;
s_axi_bready : out std_logic;
s_axi_araddr : out std_logic_vector(11 downto 0);
s_axi_arvalid : out std_logic;
s_axi_arready : in std_logic;
s_axi_rdata : in std_logic_vector(31 downto 0);
s_axi_rresp : in std_logic_vector(1 downto 0);
s_axi_rvalid : in std_logic;
s_axi_rready : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the synchroniser
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_sync_block
port (
clk : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the reset logic
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_example_design_resets is
port (
-- clocks
s_axi_aclk : in std_logic;
gtx_clk : in std_logic;
-- asynchronous resets
glbl_rst : in std_logic;
reset_error : in std_logic;
rx_reset : in std_logic;
tx_reset : in std_logic;
dcm_locked : in std_logic;
-- synchronous reset outputs
glbl_rst_intn : out std_logic;
gtx_resetn : out std_logic := '0';
s_axi_resetn : out std_logic := '0';
phy_resetn : out std_logic;
chk_resetn : out std_logic := '0'
);
end component;
------------------------------------------------------------------------------
-- internal signals used in this top level wrapper.
------------------------------------------------------------------------------
-- example design clocks
signal gtx_clk_bufg : std_logic;
signal refclk_bufg : std_logic;
signal s_axi_aclk : std_logic;
signal rx_mac_aclk : std_logic;
signal tx_mac_aclk : std_logic;
signal phy_resetn_int : std_logic;
-- resets (and reset generation)
signal reset_error : std_logic;
signal s_axi_resetn : std_logic;
signal chk_resetn : std_logic;
signal gtx_resetn : std_logic;
signal rx_reset : std_logic;
signal tx_reset : std_logic;
signal dcm_locked : std_logic;
signal glbl_rst_int : std_logic;
signal phy_reset_count : unsigned(5 downto 0) := (others => '0');
signal glbl_rst_intn : std_logic;
signal mac_speed : std_logic_vector(1 downto 0);
signal serial_response : std_logic;
signal frame_error : std_logic;
signal frame_errorn : std_logic;
signal activity_flash : std_logic;
signal activity_flashn : std_logic;
signal update_speed : std_logic := '0';
signal config_board : std_logic := '0';
-- USER side RX AXI-S interface
signal rx_fifo_clock : std_logic;
signal rx_fifo_resetn : std_logic;
signal rx_axis_fifo_tdata : std_logic_vector(7 downto 0);
signal rx_axis_fifo_tvalid : std_logic;
signal rx_axis_fifo_tlast : std_logic;
signal rx_axis_fifo_tready : std_logic;
-- USER side TX AXI-S interface
signal tx_fifo_clock : std_logic;
signal tx_fifo_resetn : std_logic;
signal tx_axis_fifo_tdata : std_logic_vector(7 downto 0);
signal tx_axis_fifo_tvalid : std_logic;
signal tx_axis_fifo_tlast : std_logic;
signal tx_axis_fifo_tready : std_logic;
-- RX Statistics serialisation signals
signal rx_statistics_s : std_logic := '0';
signal rx_statistics_valid : std_logic;
signal rx_statistics_valid_reg : std_logic;
signal rx_statistics_vector : std_logic_vector(27 downto 0);
signal rx_stats : std_logic_vector(27 downto 0);
signal rx_stats_shift : std_logic_vector(29 downto 0);
signal rx_stats_toggle : std_logic := '0';
signal rx_stats_toggle_sync : std_logic;
signal rx_stats_toggle_sync_reg : std_logic := '0';
-- TX Statistics serialisation signals
signal tx_statistics_s : std_logic := '0';
signal tx_statistics_valid : std_logic;
signal tx_statistics_valid_reg : std_logic;
signal tx_statistics_vector : std_logic_vector(31 downto 0);
signal tx_stats : std_logic_vector(31 downto 0);
signal tx_stats_shift : std_logic_vector(33 downto 0);
signal tx_stats_toggle : std_logic := '0';
signal tx_stats_toggle_sync : std_logic;
signal tx_stats_toggle_sync_reg : std_logic := '0';
-- Pause interface DESerialisation
signal pause_req_s : std_logic := '0';
signal pause_shift : std_logic_vector(18 downto 0);
signal pause_req : std_logic;
signal pause_val : std_logic_vector(15 downto 0);
-- AXI-Lite interface
signal s_axi_awaddr : std_logic_vector(11 downto 0);
signal s_axi_awvalid : std_logic;
signal s_axi_awready : std_logic;
signal s_axi_wdata : std_logic_vector(31 downto 0);
signal s_axi_wvalid : std_logic;
signal s_axi_wready : std_logic;
signal s_axi_bresp : std_logic_vector(1 downto 0);
signal s_axi_bvalid : std_logic;
signal s_axi_bready : std_logic;
signal s_axi_araddr : std_logic_vector(11 downto 0);
signal s_axi_arvalid : std_logic;
signal s_axi_arready : std_logic;
signal s_axi_rdata : std_logic_vector(31 downto 0);
signal s_axi_rresp : std_logic_vector(1 downto 0);
signal s_axi_rvalid : std_logic;
signal s_axi_rready : std_logic;
-- signal tie offs
signal tx_ifg_delay : std_logic_vector(7 downto 0) := (others => '0'); -- not used in this example
signal inband_link_status : std_logic;
signal inband_clock_speed : std_logic_vector(1 downto 0);
signal inband_duplex_status : std_logic;
signal int_frame_error : std_logic;
signal int_activity_flash : std_logic;
-- set board defaults - only updated when reprogrammed
signal enable_phy_loopback : std_logic := '0';
-- tcp
SIGNAL tcp_mac_addr : std_logic_vector(47 DOWNTO 0);
SIGNAL tcp_ipv4_addr : std_logic_vector(31 DOWNTO 0);
SIGNAL tcp_ipv6_addr : std_logic_vector(127 DOWNTO 0);
SIGNAL tcp_subnet_mask : std_logic_vector(31 DOWNTO 0);
SIGNAL tcp_gateway_ip_addr : std_logic_vector(31 DOWNTO 0);
--
SIGNAL mac_rx_sof : std_logic;
SIGNAL tcp_rx_data : std_logic_vector(7 DOWNTO 0);
SIGNAL tcp_rx_data_valid : std_logic;
SIGNAL tcp_rx_rts : std_logic;
SIGNAL tcp_rx_cts : std_logic;
SIGNAL tcp_tx_data : std_logic_vector(7 DOWNTO 0);
SIGNAL tcp_tx_data_valid : std_logic;
SIGNAL tcp_tx_cts : std_logic;
--
SIGNAL tcp_rx_data_slv8x : SLV8xNTCPSTREAMStype;
SIGNAL tcp_tx_data_slv8x : SLV8xNTCPSTREAMStype;
SIGNAL tcp_rx_data_valid_vector : std_logic_vector((NTCPSTREAMS-1) DOWNTO 0);
SIGNAL tcp_tx_cts_vector : std_logic_vector((NTCPSTREAMS-1) DOWNTO 0);
--
SIGNAL rx_fifo_full : std_logic;
SIGNAL rx_fifo_fullm3 : std_logic;
SIGNAL tx_fifo_dout : std_logic_vector(7 DOWNTO 0);
SIGNAL tx_fifo_rden : std_logic;
SIGNAL tx_fifo_empty : std_logic;
--
SIGNAL connection_reset_v : std_logic_vector((NTCPSTREAMS-1) DOWNTO 0);
SIGNAL tcp_tx_data_valid_v : std_logic_vector((NTCPSTREAMS-1) DOWNTO 0);
------------------------------------------------------------------------------
-- Begin architecture
------------------------------------------------------------------------------
begin
frame_error <= int_frame_error;
frame_errorn <= not int_frame_error;
activity_flash <= int_activity_flash;
activity_flashn <= not int_activity_flash;
mac_speed <= "11";
----------------------------------------------------------------------------
-- Clock logic to generate required clocks from the 200MHz on board
-- if 125MHz is available directly this can be removed
----------------------------------------------------------------------------
gtx_clk_bufg <= gtx_clk;
refclk_bufg <= ref_clk;
s_axi_aclk <= gtx_clk;
-- generate the user side clocks for the axi fifos
tx_fifo_clock <= gtx_clk_bufg;
rx_fifo_clock <= gtx_clk_bufg;
------------------------------------------------------------------------------
-- Generate resets required for the fifo side signals etc
------------------------------------------------------------------------------
example_resets : tri_mode_ethernet_mac_0_example_design_resets
port map (
-- clocks
s_axi_aclk => s_axi_aclk,
gtx_clk => gtx_clk_bufg,
-- asynchronous resets
glbl_rst => glbl_rst,
reset_error => reset_error,
rx_reset => rx_reset,
tx_reset => tx_reset,
dcm_locked => dcm_locked,
-- synchronous reset outputs
glbl_rst_intn => glbl_rst_intn,
gtx_resetn => gtx_resetn,
s_axi_resetn => s_axi_resetn,
phy_resetn => phy_resetn,
chk_resetn => chk_resetn
);
glbl_rst_int <= NOT glbl_rst_intn;
dcm_locked <= '1';
reset_error <= '0';
-- generate the user side resets for the axi fifos
tx_fifo_resetn <= gtx_resetn;
rx_fifo_resetn <= gtx_resetn;
----------------------------------------------------------------------------
-- Instantiate the AXI-LITE Controller
----------------------------------------------------------------------------
axi_lite_controller : tri_mode_ethernet_mac_0_axi_lite_sm
port map (
s_axi_aclk => s_axi_aclk,
s_axi_resetn => s_axi_resetn,
mac_speed => mac_speed,
update_speed => update_speed,
serial_command => pause_req_s,
serial_response => serial_response,
phy_loopback => enable_phy_loopback,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready
);
------------------------------------------------------------------------------
-- Instantiate the TRIMAC core FIFO Block wrapper
------------------------------------------------------------------------------
trimac_fifo_block : tri_mode_ethernet_mac_0_fifo_block
port map (
gtx_clk => gtx_clk_bufg,
-- asynchronous reset
glbl_rstn => glbl_rst_intn,
rx_axi_rstn => '1',
tx_axi_rstn => '1',
-- Reference clock for IDELAYCTRL's
refclk => refclk_bufg,
-- Receiver Statistics Interface
-----------------------------------------
rx_mac_aclk => rx_mac_aclk,
rx_reset => rx_reset,
rx_statistics_vector => rx_statistics_vector,
rx_statistics_valid => rx_statistics_valid,
-- Receiver => AXI-S Interface
------------------------------------------
rx_fifo_clock => rx_fifo_clock,
rx_fifo_resetn => rx_fifo_resetn,
rx_axis_fifo_tdata => rx_axis_fifo_tdata,
rx_axis_fifo_tvalid => rx_axis_fifo_tvalid,
rx_axis_fifo_tready => rx_axis_fifo_tready,
rx_axis_fifo_tlast => rx_axis_fifo_tlast,
-- Transmitter Statistics Interface
--------------------------------------------
tx_mac_aclk => tx_mac_aclk,
tx_reset => tx_reset,
tx_ifg_delay => tx_ifg_delay,
tx_statistics_vector => tx_statistics_vector,
tx_statistics_valid => tx_statistics_valid,
-- Transmitter => AXI-S Interface
---------------------------------------------
tx_fifo_clock => tx_fifo_clock,
tx_fifo_resetn => tx_fifo_resetn,
tx_axis_fifo_tdata => tx_axis_fifo_tdata,
tx_axis_fifo_tvalid => tx_axis_fifo_tvalid,
tx_axis_fifo_tready => tx_axis_fifo_tready,
tx_axis_fifo_tlast => tx_axis_fifo_tlast,
-- MAC Control Interface
--------------------------
pause_req => pause_req,
pause_val => pause_val,
-- RGMII Interface
--------------------
rgmii_txd => rgmii_txd,
rgmii_tx_ctl => rgmii_tx_ctl,
rgmii_txc => rgmii_txc,
rgmii_rxd => rgmii_rxd,
rgmii_rx_ctl => rgmii_rx_ctl,
rgmii_rxc => rgmii_rxc,
-- RGMII Inband Status Registers
----------------------------------
inband_link_status => inband_link_status,
inband_clock_speed => inband_clock_speed,
inband_duplex_status => inband_duplex_status,
-- MDIO Interface
-------------------
mdio => mdio,
mdc => mdc,
-- AXI-Lite Interface
-----------------
s_axi_aclk => s_axi_aclk,
s_axi_resetn => s_axi_resetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready
);
---------------------------------------------< tcp_server
PROCESS (gtx_clk_bufg) IS
BEGIN -- Make configurations synchronous to CLK125 of the TCP module
IF rising_edge(gtx_clk_bufg) THEN
tcp_mac_addr <= MAC_ADDR;
tcp_ipv4_addr <= IPv4_ADDR;
tcp_ipv6_addr <= IPv6_ADDR;
tcp_subnet_mask <= SUBNET_MASK;
tcp_gateway_ip_addr <= GATEWAY_IP_ADDR;
END IF;
END PROCESS;
-- generate a 1-clk wide pulse SOF (start of frame)
mac_rx_sof_gen : PROCESS (gtx_clk_bufg, glbl_rst_int) IS
VARIABLE state : std_logic;
VARIABLE tvalid_prev : std_logic;
BEGIN
IF glbl_rst_int = '1' THEN
state := '0';
tvalid_prev := '0';
mac_rx_sof <= '0';
ELSIF falling_edge(gtx_clk_bufg) THEN
mac_rx_sof <= '0';
IF state = '0' THEN
IF tvalid_prev = '0' AND rx_axis_fifo_tvalid = '1' THEN
mac_rx_sof <= '1';
state := '1';
END IF;
ELSE -- state = '1'
IF rx_axis_fifo_tlast = '1' THEN
state := '0';
END IF;
END IF;
tvalid_prev := rx_axis_fifo_tvalid;
END IF;
END PROCESS;
rx_axis_fifo_tready <= '1';
tcp_rx_data <= tcp_rx_data_slv8x(0);
tcp_tx_data_slv8x(0) <= tcp_tx_data;
tcp_tx_cts <= tcp_tx_cts_vector(0);
tcp_rx_data_valid <= tcp_rx_data_valid_vector(0);
connection_reset_v <= (OTHERS => tcp_connection_reset);
tcp_tx_data_valid_v <= (OTHERS => tcp_tx_data_valid);
tcp_server_inst : COM5402
GENERIC MAP (
CLK_FREQUENCY => 125,
-- CLK frequency in MHz. Needed to compute actual delays.
TX_IDLE_TIMEOUT => 50,
-- inactive input timeout, expressed in 4us units. -- 50*4us = 200us
-- Controls the transmit stream segmentation: data in the elastic buffer will be transmitted if
-- no input is received within TX_IDLE_TIMEOUT, without waiting for the transmit frame to be filled with MSS data bytes.
SIMULATION => '0'
-- 1 during simulation with Wireshark .cap file, '0' otherwise
-- Wireshark many not be able to collect offloaded checksum computations.
-- when SIMULATION = '1': (a) IP header checksum is valid if 0000,
-- (b) TCP checksum computation is forced to a valid 00001 irrespective of the 16-bit checksum
-- captured by Wireshark.
)
PORT MAP (
--//-- CLK, RESET
CLK => gtx_clk_bufg,
-- All signals are synchronous with CLK
-- CLK must be a global clock 125 MHz or faster to match the Gbps MAC speed.
ASYNC_RESET => glbl_rst_int, -- to be phased out. replace with SYNC_RESET
SYNC_RESET => glbl_rst_int,
--//-- CONFIGURATION
-- configuration signals are synchonous with CLK
-- Synchronous with CLK clock.
MAC_ADDR => tcp_mac_addr,
IPv4_ADDR => tcp_ipv4_addr,
IPv6_ADDR => tcp_ipv6_addr,
SUBNET_MASK => tcp_subnet_mask,
GATEWAY_IP_ADDR => tcp_gateway_ip_addr,
-- local IP address. 4 bytes for IPv4, 16 bytes for IPv6
-- Natural order (MSB) 172.16.1.128 (LSB) as transmitted in the IP frame.
--// User-initiated connection reset for stream I
CONNECTION_RESET => connection_reset_v,
--//-- Protocol -> Transmit MAC Interface
-- 32-bit CRC is automatically appended by the MAC layer. User should not supply it.
-- Synchonous with the user-side CLK
MAC_TX_DATA => tx_axis_fifo_tdata,
-- MAC reads the data at the rising edge of CLK when MAC_TX_DATA_VALID = '1'
MAC_TX_DATA_VALID => tx_axis_fifo_tvalid,
-- data valid
MAC_TX_SOF => OPEN,
-- start of frame: '1' when sending the first byte.
MAC_TX_EOF => tx_axis_fifo_tlast,
-- '1' when sending the last byte in a packet to be transmitted.
-- Aligned with MAC_TX_DATA_VALID
MAC_TX_CTS => tx_axis_fifo_tready,
-- MAC-generated Clear To Send flow control signal, indicating room in the
-- MAC tx elastic buffer for a complete maximum size frame 1518B.
-- The user should check that this signal is high before deciding to send
-- sending the next frame.
-- Note: MAC_TX_CTS may go low while the frame is transfered in. Ignore it as space is guaranteed
-- at the start of frame.
--//-- Receive MAC -> Protocol
-- Valid rx packets only: packets with bad CRC or invalid address are discarded.
-- The 32-bit CRC is always removed by the MAC layer.
-- Synchonous with the user-side CLK
MAC_RX_DATA => rx_axis_fifo_tdata,
-- USER reads the data at the rising edge of CLK when MAC_RX_DATA_VALID = '1'
MAC_RX_DATA_VALID => rx_axis_fifo_tvalid,
-- data valid
MAC_RX_SOF => mac_rx_sof,
-- '1' when sending the first byte in a received packet.
-- Aligned with MAC_RX_DATA_VALID
MAC_RX_EOF => rx_axis_fifo_tlast,
-- '1' when sending the last byte in a received packet.
-- Aligned with MAC_RX_DATA_VALID
--//-- Application <- UDP rx
UDP_RX_DATA => OPEN,
UDP_RX_DATA_VALID => OPEN,
UDP_RX_SOF => OPEN,
UDP_RX_EOF => OPEN,
-- 1 CLK pulse indicating that UDP_RX_DATA is the last byte in the UDP data field.
-- ALWAYS CHECK UDP_RX_DATA_VALID at the end of packet (UDP_RX_EOF = '1') to confirm
-- that the UDP packet is valid. External buffer may have to backtrack to the the last
-- valid pointer to discard an invalid UDP packet.
-- Reason: we only knows about bad UDP packets at the end.
UDP_RX_DEST_PORT_NO => (OTHERS => '0'),
--//-- Application -> UDP tx
UDP_TX_DATA => (OTHERS => '0'),
UDP_TX_DATA_VALID => '0',
UDP_TX_SOF => '0', -- 1 CLK-wide pulse to mark the first byte in the tx UDP frame
UDP_TX_EOF => '0', -- 1 CLK-wide pulse to mark the last byte in the tx UDP frame
UDP_TX_CTS => OPEN,
UDP_TX_ACK => OPEN, -- 1 CLK-wide pulse indicating that the previous UDP frame is being sent
UDP_TX_NAK => OPEN, -- 1 CLK-wide pulse indicating that the previous UDP frame could not be sent
UDP_TX_DEST_IP_ADDR => (OTHERS => '0'),
UDP_TX_DEST_PORT_NO => (OTHERS => '0'),
UDP_TX_SOURCE_PORT_NO => (OTHERS => '0'),
--//-- Application <- TCP rx
-- NTCPSTREAMS can operate independently. Only one stream active at any given time.
-- Data is pushed out. Limited flow-control here. Receipient must be able to accept data
-- at any time (in other words, it is the receipient's responsibility to have elastic
-- buffer if needed).
TCP_RX_DATA => tcp_rx_data_slv8x,
TCP_RX_DATA_VALID => tcp_rx_data_valid_vector,
TCP_RX_RTS => tcp_rx_rts,
TCP_RX_CTS => tcp_rx_cts,
-- Optional Clear-To-Send. pull to '1' when output flow control is unused.
-- WARNING: pulling CTS down will stop the flow for ALL streams.
--//-- Application -> TCP tx
-- NTCPSTREAMS can operate independently and concurrently. No scheduling arbitration needed here.
TCP_TX_DATA => tcp_tx_data_slv8x,
TCP_TX_DATA_VALID => tcp_tx_data_valid_v,
TCP_TX_CTS => tcp_tx_cts_vector,
-- Clear To Send = transmit flow control.
-- App is responsible for checking the CTS signal before sending APP_DATA
--//-- TEST POINTS, COMSCOPE TRACES
CS1 => OPEN,
CS1_CLK => OPEN,
CS2 => OPEN,
CS2_CLK => OPEN,
TP => OPEN
);
-- Must have programmable full with single-threshold of 61
-- out of total write-depth 64.
-- When RX_CTS is low, the Server continues to drive out 3 more bytes of data
-- (observed with ILA). The fifo must be able to accept them, hence the use
-- of prog_full.
rx_fifo_inst : fifo8to32
PORT MAP (
rst => glbl_rst_int,
wr_clk => gtx_clk_bufg,
rd_clk => RX_FIFO_RDCLK,
din => tcp_rx_data,
wr_en => tcp_rx_data_valid,
rd_en => RX_FIFO_RDEN,
dout => RX_FIFO_Q,
full => rx_fifo_full,
prog_full => rx_fifo_fullm3, -- asserted at (full-3) writes
empty => RX_FIFO_EMPTY
);
tcp_rx_cts <= (NOT rx_fifo_fullm3) WHEN TCP_USE_FIFO = '1' ELSE
RX_TREADY;
RX_TDATA <= tcp_rx_data;
RX_TVALID <= tcp_rx_data_valid;
tx_fifo_inst : fifo32to8
PORT MAP (
rst => glbl_rst_int,
wr_clk => TX_FIFO_WRCLK,
rd_clk => gtx_clk_bufg,
din => TX_FIFO_Q,
wr_en => TX_FIFO_WREN,
rd_en => tx_fifo_rden,
dout => tx_fifo_dout,
full => TX_FIFO_FULL,
empty => tx_fifo_empty
);
tcp_tx_data_valid <= ((NOT tx_fifo_empty) AND tcp_tx_cts) WHEN TCP_USE_FIFO = '1' ELSE
TX_TVALID;
tx_fifo_rden <= tcp_tx_data_valid;
tcp_tx_data <= tx_fifo_dout WHEN TCP_USE_FIFO = '1' ELSE
TX_TDATA;
TX_TREADY <= tcp_tx_cts;
end wrapper;
|
mit
|
plac-lab/TMIIaTest
|
Firmware/src/topmetal_analog_scan_diff.vhd
|
1
|
10154
|
--------------------------------------------------------------------------------
--! @file topmetal_analog_scan.vhd
--! @brief Generate appropriate signals for driving the analog scan of Topmetal array.
--! @author Yuan Mei
--!
--! The bram_sdp_w32r4 must have read latency of 1 (select no register on output).
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;
ENTITY topmetal_analog_scan_diff IS
GENERIC (
ROWS : positive := 45; -- number of ROWS in the array
COLS : positive := 216; -- number of COLS in the ARRAY
CLK_DIV_WIDTH : positive := 16;
CLK_DIV_WLOG2 : positive := 4;
CONFIG_WIDTH : positive := 16
);
PORT (
CLK : IN std_logic; -- clock, TM_CLK_S is derived from this one
RESET : IN std_logic; -- reset
-- data input for writing to in-chip SRAM
MEM_CLK : IN std_logic; -- connect to control_interface
MEM_WE : IN std_logic;
MEM_ADDR : IN std_logic_vector(31 DOWNTO 0);
MEM_DIN : IN std_logic_vector(31 DOWNTO 0);
SRAM_WR_START : IN std_logic; -- 1 MEM_CLK wide pulse to initiate in-chip SRAM write
-- configuration
CLK_DIV : IN std_logic_vector(CLK_DIV_WLOG2-1 DOWNTO 0); -- log2(CLK_DIV_WIDTH), CLK/(2**CLK_DIV)
WR_CLK_DIV : IN std_logic_vector(CLK_DIV_WLOG2-1 DOWNTO 0);
STOP_ADDR : IN std_logic_vector(CONFIG_WIDTH-1 DOWNTO 0); --MSB enables
TRIGGER_RATE : IN std_logic_vector(CONFIG_WIDTH-1 DOWNTO 0); --trigger every () frames
TRIGGER_DELAY : IN std_logic_vector(CONFIG_WIDTH-1 DOWNTO 0);
STOP_CLK_S : IN std_logic; -- 1: stop TM_CLK_S, 0: run TM_CLK_S
KEEP_WE : IN std_logic; -- 1: SRAM_WE keep high in writing mode, 0: SRAM_WE runs in writing mode
-- input
MARKER_A : IN std_logic;
-- output
TRIGGER_OUT_P : OUT std_logic;
TRIGGER_OUT_N : OUT std_logic;
--
SRAM_D0_P : OUT std_logic;
SRAM_D0_N : OUT std_logic;
SRAM_D1_P : OUT std_logic;
SRAM_D1_N : OUT std_logic;
SRAM_D2_P : OUT std_logic;
SRAM_D2_N : OUT std_logic;
SRAM_D3_P : OUT std_logic;
SRAM_D3_N : OUT std_logic;
SRAM_WE_P : OUT std_logic;
SRAM_WE_N : OUT std_logic;
TM_RST_P : OUT std_logic; -- digital reset
TM_RST_N : OUT std_logic; -- digital reset
TM_CLK_S_P : OUT std_logic;
TM_CLK_S_N : OUT std_logic;
TM_RST_S_P : OUT std_logic;
TM_RST_S_N : OUT std_logic;
TM_START_S_P : OUT std_logic;
TM_START_S_N : OUT std_logic;
TM_SPEAK_S_P : OUT std_logic;
TM_SPEAK_S_N : OUT std_logic
);
END topmetal_analog_scan_diff;
ARCHITECTURE Behavioral OF topmetal_analog_scan_diff IS
-- components
COMPONENT topmetal_analog_scan IS
GENERIC (
ROWS : positive := 45; -- number of ROWS in the array
COLS : positive := 216; -- number of COLS in the ARRAY
CLK_DIV_WIDTH : positive := 16;
CLK_DIV_WLOG2 : positive := 4;
CONFIG_WIDTH : positive := 16
);
PORT (
CLK : IN std_logic; -- clock, TM_CLK_S is derived from this one
RESET : IN std_logic; -- reset
-- data input for writing to in-chip SRAM
MEM_CLK : IN std_logic; -- connect to control_interface
MEM_WE : IN std_logic;
MEM_ADDR : IN std_logic_vector(31 DOWNTO 0);
MEM_DIN : IN std_logic_vector(31 DOWNTO 0);
SRAM_WR_START : IN std_logic; -- 1 MEM_CLK wide pulse to initiate in-chip SRAM write
-- configuration
CLK_DIV : IN std_logic_vector(CLK_DIV_WLOG2-1 DOWNTO 0); -- log2(CLK_DIV_WIDTH), CLK/(2**CLK_DIV)
WR_CLK_DIV : IN std_logic_vector(CLK_DIV_WLOG2-1 DOWNTO 0);
STOP_ADDR : IN std_logic_vector(CONFIG_WIDTH-1 DOWNTO 0); --MSB enables
TRIGGER_RATE : IN std_logic_vector(CONFIG_WIDTH-1 DOWNTO 0); --trigger every () frames
TRIGGER_DELAY : IN std_logic_vector(CONFIG_WIDTH-1 DOWNTO 0);
STOP_CLK_S : IN std_logic; -- 1: stop TM_CLK_S, 0: run TM_CLK_S
KEEP_WE : IN std_logic; -- 1: SRAM_WE keep high in writing mode, 0: SRAM_WE runs in writing mode
-- input
MARKER_A : IN std_logic;
-- output
TRIGGER_OUT :OUT std_logic;
--
SRAM_D :OUT std_logic_vector(3 DOWNTO 0);
SRAM_WE :OUT std_logic;
TM_RST :OUT std_logic; -- digital reset
TM_CLK_S :OUT std_logic;
TM_RST_S :OUT std_logic;
TM_START_S :OUT std_logic;
TM_SPEAK_S :OUT std_logic
);
END COMPONENT;
--signals
---------------------------------------------< topmetal_analog_scan
SIGNAL TRIGGER_OUT : std_logic;
--
SIGNAL SRAM_D : std_logic_vector(3 DOWNTO 0);
SIGNAL SRAM_WE : std_logic;
SIGNAL TM_RST : std_logic; -- digital reset
SIGNAL TM_CLK_S : std_logic;
SIGNAL TM_RST_S : std_logic;
SIGNAL TM_START_S : std_logic;
SIGNAL TM_SPEAK_S : std_logic;
---------------------------------------------> topmetal_analog_scan
BEGIN
topmetal_analog_scan_inst : topmetal_analog_scan
GENERIC MAP(
ROWS => 45, -- number of ROWS in the array
COLS => 216, -- number of COLS in the ARRAY
CLK_DIV_WIDTH => 16,
CLK_DIV_WLOG2 => 4,
CONFIG_WIDTH => 16
)
PORT MAP (
CLK => CLK, -- clock, TM_CLK_S is derived from this one
RESET => RESET, -- reset
-- data input for writing to in-chip SRAM
MEM_CLK => MEM_CLK, -- connect to control_interface
MEM_WE => MEM_WE,
MEM_ADDR => MEM_ADDR,
MEM_DIN => MEM_DIN,
SRAM_WR_START => SRAM_WR_START, -- 1 MEM_CLK wide pulse to initiate in-chip SRAM write
-- configuration
CLK_DIV => CLK_DIV,-- log2(CLK_DIV_WIDTH), CLK/(2**CLK_DIV)
WR_CLK_DIV => WR_CLK_DIV,
STOP_ADDR => STOP_ADDR,--MSB enables
TRIGGER_RATE => TRIGGER_RATE,--trigger every () frames
TRIGGER_DELAY => TRIGGER_DELAY,
STOP_CLK_S => STOP_CLK_S,
KEEP_WE => KEEP_WE,
-- input
MARKER_A => MARKER_A,
-- output
TRIGGER_OUT => TRIGGER_OUT,
--
SRAM_D => SRAM_D,
SRAM_WE => SRAM_WE,
TM_RST => TM_RST, -- digital reset
TM_CLK_S => TM_CLK_S,
TM_RST_S => TM_RST_S,
TM_START_S => TM_START_S,
TM_SPEAK_S => TM_SPEAK_S
);
---------------------------------------------< topmetal_analog_scan_diff
OBUFDS_inst1 : OBUFDS
PORT MAP (
I => TRIGGER_OUT,
O => TRIGGER_OUT_P, -- Diff_p buffer output (connect directly to top-level port)
OB => TRIGGER_OUT_N -- Diff_n buffer output (connect directly to top-level port)
);
OBUFDS_inst2 : OBUFDS
PORT MAP (
I => SRAM_WE,
O => SRAM_WE_P, -- Diff_p buffer output (connect directly to top-level port)
OB => SRAM_WE_N -- Diff_n buffer output (connect directly to top-level port)
);
OBUFDS_inst3 : OBUFDS
PORT MAP (
I => TM_RST,
O => TM_RST_P, -- Diff_p buffer output (connect directly to top-level port)
OB => TM_RST_N -- Diff_n buffer output (connect directly to top-level port)
);
OBUFDS_inst4 : OBUFDS
PORT MAP (
I => TM_CLK_S,
O => TM_CLK_S_P, -- Diff_p buffer output (connect directly to top-level port)
OB => TM_CLK_S_N -- Diff_n buffer output (connect directly to top-level port)
);
OBUFDS_inst5 : OBUFDS
PORT MAP (
I => TM_RST_S,
O => TM_RST_S_P, -- Diff_p buffer output (connect directly to top-level port)
OB => TM_RST_S_N -- Diff_n buffer output (connect directly to top-level port)
);
OBUFDS_inst6 : OBUFDS
PORT MAP (
I => TM_START_S,
O => TM_START_S_P, -- Diff_p buffer output (connect directly to top-level port)
OB => TM_START_S_N -- Diff_n buffer output (connect directly to top-level port)
);
OBUFDS_inst7 : OBUFDS
PORT MAP (
I => TM_SPEAK_S,
O => TM_SPEAK_S_P, -- Diff_p buffer output (connect directly to top-level port)
OB => TM_SPEAK_S_N -- Diff_n buffer output (connect directly to top-level port)
);
OBUFDS_inst8 : OBUFDS
PORT MAP (
I => SRAM_D(0),
O => SRAM_D0_P, -- Diff_p buffer output (connect directly to top-level port)
OB => SRAM_D0_N -- Diff_n buffer output (connect directly to top-level port)
);
OBUFDS_inst9 : OBUFDS
PORT MAP (
I => SRAM_D(1),
O => SRAM_D1_P, -- Diff_p buffer output (connect directly to top-level port)
OB => SRAM_D1_N -- Diff_n buffer output (connect directly to top-level port)
);
OBUFDS_inst10 : OBUFDS
PORT MAP (
I => SRAM_D(2),
O => SRAM_D2_P, -- Diff_p buffer output (connect directly to top-level port)
OB => SRAM_D2_N -- Diff_n buffer output (connect directly to top-level port)
);
OBUFDS_inst11 : OBUFDS
PORT MAP (
I => SRAM_D(3),
O => SRAM_D3_P, -- Diff_p buffer output (connect directly to top-level port)
OB => SRAM_D3_N -- Diff_n buffer output (connect directly to top-level port)
);
---------------------------------------------> topmetal_analog_scan_diff
END Behavioral;
|
mit
|
plac-lab/TMIIaTest
|
Firmware/src/pulsegen.vhd
|
1
|
1717
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:32:46 08/25/2013
-- Design Name:
-- Module Name: pulsegen - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
LIBRARY UNISIM;
USE UNISIM.VComponents.ALL;
ENTITY pulsegen IS
GENERIC (
COUNTER_WIDTH : positive := 32
);
PORT (
CLK : IN std_logic;
PERIOD : IN std_logic_vector(COUNTER_WIDTH-1 DOWNTO 0);
I : IN std_logic;
O : OUT std_logic
);
END pulsegen;
ARCHITECTURE Behavioral OF pulsegen IS
SIGNAL counter : unsigned(COUNTER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
PROCESS (CLK) IS
VARIABLE zeros : unsigned(COUNTER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
O <= '0';
IF I = '1' THEN
O <= I;
ELSIF rising_edge(CLK) THEN
IF unsigned(PERIOD) = zeros THEN
O <= I;
ELSE
counter <= counter + 1;
O <= '0';
IF counter = unsigned(PERIOD)-1 THEN
O <= '1';
ELSIF counter >= unsigned(PERIOD) THEN
O <= '0';
counter <= (OTHERS => '0');
END IF;
END IF;
END IF;
END PROCESS;
END Behavioral;
|
mit
|
cadesalaberry/digital-system-design
|
lab5/g23_dayfrac_to_MTC.vhd
|
1
|
3060
|
-- Converts an earth time and date into mars time of day.
--
-- entity name: g23_dayfrac_to_MTC
--
-- Copyright (C) 2014 cadesalaberry, grahamludwinski
--
-- Version 1.0
--
-- Author:
-- Charles-Antoine de Salaberry; [email protected],
-- Graham Ludwinski; [email protected]
--
-- Date: 04/04/2014
library ieee; -- allows use of the std_logic_vector type
use ieee.std_logic_1164.all;
use IEEE.numeric_std.all;
entity g23_dayfrac_to_MTC is
PORT (
clock : in STD_LOGIC;
enable : in STD_LOGIC;
Ndays : in STD_LOGIC_VECTOR(13 downto 0);
day_frac : in STD_LOGIC_VECTOR(39 downto 0);
-- Time corresponding to the fraction of the day.
Hours : out STD_LOGIC_VECTOR(4 downto 0);
Minutes : out STD_LOGIC_VECTOR(5 downto 0);
Seconds : out STD_LOGIC_VECTOR(5 downto 0)
);
end g23_dayfrac_to_MTC;
architecture cascading of g23_dayfrac_to_MTC is
-- 14 bits for int and 18 bits for fraction = 32 bits
constant multiplyConst : UNSIGNED := "00000000000000111110010010011010"; -- .973244297 in binary
-- 28 bits for int 0 and 36 bits for fraction = 64 bits
-- 18 bit frac * 18 frac int gives 36 bit frac
constant subConst : UNSIGNED := "0000000000000000000000000000000000000010111100101111100110000000";
-- 5 bits to represent 24 and the rest 0's for the frac (32 bits total)
constant twentyfour : UNSIGNED := "11000000000000000000000000000000";
-- 6 bits for int and 12 bits for frac
constant sixty : UNSIGNED := "111100000000000000";
BEGIN
day_frac_to_MTC : PROCESS(clock, enable, Ndays, day_frac)
variable mult_in_frac : UNSIGNED(63 downto 0);
variable sbct_in_frac : INTEGER;
variable JD2000 : UNSIGNED(31 downto 0);
variable frac : UNSIGNED(31 downto 0);
variable MTC : STD_LOGIC_VECTOR(63 downto 0);
variable int_out : STD_LOGIC_VECTOR(9 downto 0);
variable frac_part : STD_LOGIC_VECTOR(11 downto 0);
variable full_minutes : UNSIGNED(35 downto 0);
variable full_seconds : UNSIGNED(35 downto 0);
BEGIN
IF enable = '0' THEN
Hours <= "00000";
Minutes <= "000000";
Seconds <= "000000";
ELSE
-- JD2000 = NDays.day_frac
-- size = 16 +(39-23) = 32 = 16.16
-- JD2000 <= UNSIGNED(Ndays & STD_LOGIC_VECTOR(day_frac(39 downto 23)));
JD2000 := UNSIGNED(Ndays(13 downto 0) & STD_LOGIC_VECTOR(day_frac(39 downto 22)));
mult_in_frac := JD2000 * multiplyConst - subConst;
frac := "00000" & mult_in_frac(35 downto 9);
-- upper 10 bits are integer, bottom 54 are decimal
MTC := STD_LOGIC_VECTOR(frac * twentyfour);
-- Ignores the first 5 bits, and takes the 5 following as hour.
Hours <= MTC(58 downto 54);
frac_part := MTC(53 downto 42);
full_minutes := sixty * UNSIGNED("000000" & frac_part);
Minutes <= STD_LOGIC_VECTOR(full_minutes(29 downto 24));
full_seconds := sixty * ("000000" & full_minutes(23 downto 12));
Seconds <= STD_LOGIC_VECTOR(full_seconds(29 downto 24));
END IF; --if reset
END PROCESS day_frac_to_MTC;
end cascading;
|
mit
|
jonathanrainer/serial_processors_project
|
simulations/processor_simulations/sources/kuuga_test_harness/ip/kuuga_test_harness_agito_0_0/hdl/vhdl/agito_shift.vhd
|
1
|
15041
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity agito_shift is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
operands_V : IN STD_LOGIC_VECTOR (26 downto 0);
right_flag : IN STD_LOGIC;
arithmetic_flag : IN STD_LOGIC;
registers_V_address0 : OUT STD_LOGIC_VECTOR (3 downto 0);
registers_V_ce0 : OUT STD_LOGIC;
registers_V_q0 : IN STD_LOGIC_VECTOR (31 downto 0);
registers_V_address1 : OUT STD_LOGIC_VECTOR (3 downto 0);
registers_V_ce1 : OUT STD_LOGIC;
registers_V_we1 : OUT STD_LOGIC;
registers_V_d1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of agito_shift is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (4 downto 0) := "00100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (4 downto 0) := "01000";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (4 downto 0) := "10000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv9_0 : STD_LOGIC_VECTOR (8 downto 0) := "000000000";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110";
constant ap_const_lv9_1 : STD_LOGIC_VECTOR (8 downto 0) := "000000001";
constant ap_const_lv32_1F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011111";
constant ap_const_lv30_0 : STD_LOGIC_VECTOR (29 downto 0) := "000000000000000000000000000000";
constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
constant ap_const_lv32_1A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011010";
signal ap_CS_fsm : STD_LOGIC_VECTOR (4 downto 0) := "00001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_23 : BOOLEAN;
signal r_V_reg_254 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_3_fu_140_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_3_reg_259 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_57 : BOOLEAN;
signal input_V_reg_269 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_65 : BOOLEAN;
signal tmp_2_reg_275 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st4_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_76 : BOOLEAN;
signal sel_tmp2_fu_156_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp2_reg_285 : STD_LOGIC_VECTOR (0 downto 0);
signal i_1_fu_167_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_sig_cseq_ST_st5_fsm_4 : STD_LOGIC;
signal ap_sig_bdd_87 : BOOLEAN;
signal p_058_1_fu_228_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal exitcond_fu_162_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal p_1_reg_109 : STD_LOGIC_VECTOR (31 downto 0);
signal i_reg_119 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_fu_144_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_9_fu_244_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal sel_tmp2_fu_156_p0 : STD_LOGIC_VECTOR (0 downto 0);
signal sel_tmp2_fu_156_p1 : STD_LOGIC_VECTOR (0 downto 0);
signal r_V_6_fu_179_p4 : STD_LOGIC_VECTOR (30 downto 0);
signal tmp_7_fu_193_p3 : STD_LOGIC_VECTOR (30 downto 0);
signal tmp_5_fu_206_p3 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_8_fu_200_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal sel_tmp1_fu_221_p0 : STD_LOGIC_VECTOR (0 downto 0);
signal r_V_5_fu_189_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal r_V_7_fu_173_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal r_V_4_fu_213_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal sel_tmp1_fu_221_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal r_V_2_fu_235_p4 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (4 downto 0);
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- i_reg_119 assign process. --
i_reg_119_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) and (exitcond_fu_162_p2 = ap_const_lv1_0))) then
i_reg_119 <= i_1_fu_167_p2;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
i_reg_119 <= ap_const_lv9_0;
end if;
end if;
end process;
-- p_1_reg_109 assign process. --
p_1_reg_109_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) and (exitcond_fu_162_p2 = ap_const_lv1_0))) then
p_1_reg_109 <= p_058_1_fu_228_p3;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
p_1_reg_109 <= input_V_reg_269;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
input_V_reg_269 <= registers_V_q0;
tmp_2_reg_275 <= registers_V_q0(30 downto 30);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
r_V_reg_254 <= operands_V(17 downto 9);
tmp_3_reg_259 <= tmp_3_fu_140_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
sel_tmp2_reg_285 <= sel_tmp2_fu_156_p2;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, exitcond_fu_162_p2)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
ap_NS_fsm <= ap_ST_st3_fsm_2;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st4_fsm_3 =>
ap_NS_fsm <= ap_ST_st5_fsm_4;
when ap_ST_st5_fsm_4 =>
if (not((exitcond_fu_162_p2 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
else
ap_NS_fsm <= ap_ST_st5_fsm_4;
end if;
when others =>
ap_NS_fsm <= "XXXXX";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0, ap_sig_cseq_ST_st5_fsm_4, exitcond_fu_162_p2)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) and not((exitcond_fu_162_p2 = ap_const_lv1_0))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_sig_cseq_ST_st5_fsm_4, exitcond_fu_162_p2)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) and not((exitcond_fu_162_p2 = ap_const_lv1_0)))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_sig_bdd_23 assign process. --
ap_sig_bdd_23_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_23 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_57 assign process. --
ap_sig_bdd_57_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_57 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_bdd_65 assign process. --
ap_sig_bdd_65_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_65 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_bdd_76 assign process. --
ap_sig_bdd_76_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_76 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_87 assign process. --
ap_sig_bdd_87_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_87 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4));
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_23)
begin
if (ap_sig_bdd_23) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_57)
begin
if (ap_sig_bdd_57) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st3_fsm_2 assign process. --
ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_bdd_65)
begin
if (ap_sig_bdd_65) then
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st4_fsm_3 assign process. --
ap_sig_cseq_ST_st4_fsm_3_assign_proc : process(ap_sig_bdd_76)
begin
if (ap_sig_bdd_76) then
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st5_fsm_4 assign process. --
ap_sig_cseq_ST_st5_fsm_4_assign_proc : process(ap_sig_bdd_87)
begin
if (ap_sig_bdd_87) then
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_0;
end if;
end process;
exitcond_fu_162_p2 <= "1" when (i_reg_119 = tmp_3_reg_259) else "0";
i_1_fu_167_p2 <= std_logic_vector(unsigned(i_reg_119) + unsigned(ap_const_lv9_1));
p_058_1_fu_228_p3 <=
r_V_4_fu_213_p3 when (sel_tmp2_reg_285(0) = '1') else
sel_tmp1_fu_221_p3;
r_V_2_fu_235_p4 <= operands_V(26 downto 18);
r_V_4_fu_213_p3 <= (tmp_5_fu_206_p3 & tmp_8_fu_200_p2);
r_V_5_fu_189_p1 <= std_logic_vector(resize(unsigned(r_V_6_fu_179_p4),32));
r_V_6_fu_179_p4 <= p_1_reg_109(31 downto 1);
r_V_7_fu_173_p2 <= std_logic_vector(shift_left(unsigned(p_1_reg_109),to_integer(unsigned('0' & ap_const_lv32_1(31-1 downto 0)))));
registers_V_address0 <= tmp_fu_144_p1(4 - 1 downto 0);
registers_V_address1 <= tmp_9_fu_244_p1(4 - 1 downto 0);
-- registers_V_ce0 assign process. --
registers_V_ce0_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
registers_V_ce0 <= ap_const_logic_1;
else
registers_V_ce0 <= ap_const_logic_0;
end if;
end process;
-- registers_V_ce1 assign process. --
registers_V_ce1_assign_proc : process(ap_sig_cseq_ST_st5_fsm_4)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) then
registers_V_ce1 <= ap_const_logic_1;
else
registers_V_ce1 <= ap_const_logic_0;
end if;
end process;
registers_V_d1 <= p_1_reg_109;
-- registers_V_we1 assign process. --
registers_V_we1_assign_proc : process(ap_sig_cseq_ST_st5_fsm_4, exitcond_fu_162_p2)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4) and not((exitcond_fu_162_p2 = ap_const_lv1_0))))) then
registers_V_we1 <= ap_const_logic_1;
else
registers_V_we1 <= ap_const_logic_0;
end if;
end process;
sel_tmp1_fu_221_p0 <= (0=>right_flag, others=>'-');
sel_tmp1_fu_221_p3 <=
r_V_5_fu_189_p1 when (sel_tmp1_fu_221_p0(0) = '1') else
r_V_7_fu_173_p2;
sel_tmp2_fu_156_p0 <= (0=>right_flag, others=>'-');
sel_tmp2_fu_156_p1 <= (0=>arithmetic_flag, others=>'-');
sel_tmp2_fu_156_p2 <= (sel_tmp2_fu_156_p0 and sel_tmp2_fu_156_p1);
tmp_3_fu_140_p1 <= operands_V(9 - 1 downto 0);
tmp_5_fu_206_p3 <= input_V_reg_269(31 downto 31);
tmp_7_fu_193_p3 <= (tmp_2_reg_275 & ap_const_lv30_0);
tmp_8_fu_200_p2 <= (tmp_7_fu_193_p3 or r_V_6_fu_179_p4);
tmp_9_fu_244_p1 <= std_logic_vector(resize(unsigned(r_V_2_fu_235_p4),64));
tmp_fu_144_p1 <= std_logic_vector(resize(unsigned(r_V_reg_254),64));
end behav;
|
mit
|
plac-lab/TMIIaTest
|
Firmware/src/ten_gig_eth/KC705/fifo/ten_gig_eth_mac_0_fifo_ram.vhd
|
3
|
5184
|
----------------------------------------------------------------------------
-- Title : FIFO BRAM
-- Project : Ten Gigabit Ethernet MAC core
----------------------------------------------------------------------------
-- File : fifo_ram.vhd
-- Author : Xilinx, Inc.
----------------------------------------------------------------------------
-- Description: BRAM used by tx and rx FIFOs
-------------------------------------------------------------------------------
-- (c) Copyright 2004-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ten_gig_eth_mac_0_fifo_ram is
generic (
ADDR_WIDTH : integer := 9);
port (
wr_clk : in std_logic;
wr_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
data_in : in std_logic_vector(63 downto 0);
ctrl_in : in std_logic_vector(3 downto 0);
wr_allow : in std_logic;
rd_clk : in std_logic;
rd_sreset : in std_logic;
rd_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
data_out : out std_logic_vector(63 downto 0);
ctrl_out : out std_logic_vector(3 downto 0);
rd_allow : in std_logic);
end ten_gig_eth_mac_0_fifo_ram;
library ieee;
use ieee.numeric_std.all;
architecture rtl of ten_gig_eth_mac_0_fifo_ram is
constant RAM_DEPTH : integer := 2 ** ADDR_WIDTH;
type ram_typ is array (RAM_DEPTH-1 downto 0)
of std_logic_vector(67 downto 0);
signal ram : ram_typ;
signal wr_data : std_logic_vector(67 downto 0);
signal rd_data : std_logic_vector(67 downto 0);
signal rd_addr_int, wr_addr_int : unsigned(ADDR_WIDTH-1 downto 0);
signal rd_allow_int : std_logic;
attribute ram_style : string;
attribute ram_style of ram : signal is "block";
begin
wr_data(63 downto 0) <= data_in;
wr_data(67 downto 64) <= ctrl_in;
data_out <= rd_data(63 downto 0);
ctrl_out <= rd_data(67 downto 64);
-- Type conversion to allow RAM indexing to work
rd_addr_int <= unsigned(rd_addr);
wr_addr_int <= unsigned(wr_addr);
--Block RAM must be enabled for synchronous reset to work.
rd_allow_int <= rd_allow or rd_sreset;
------------------------------------------------------------------------
-- Infer BRAMs and connect them
-- appropriately.
------------------------------------------------------------------------
p_write_ram : process (wr_clk)
begin
if rising_edge(wr_clk) then
if wr_allow = '1' then
ram(TO_INTEGER(wr_addr_int)) <= wr_data;
end if;
end if;
end process p_write_ram;
p_read_ram : process (rd_clk)
begin
if rising_edge(rd_clk) then
if rd_allow_int = '1' then
if rd_sreset = '1' then
rd_data <= (others => '0');
else
rd_data <= ram(TO_INTEGER(rd_addr_int));
end if;
end if;
end if;
end process p_read_ram;
end rtl;
|
mit
|
Pajeh/mips1
|
test/vhdl/ram.vhd
|
1
|
996
|
-- revision history:
-- 06.07.2015 Alex Schönberger created
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_unsigned.ALL;
entity ram is
port(
clk : in std_logic;
we : in std_logic;
a : in std_logic_vector(7 downto 0);
dpra : in std_logic_vector(7 downto 0);
di : in std_logic_vector(7 downto 0);
spo : out std_logic_vector(7 downto 0);
dpo : out std_logic_vector(7 downto 0);
leds : out std_logic_vector(7 downto 0)
);
end entity ram;
architecture structure_ram of ram is
type t_ram is array(255 downto 0) of std_logic_vector(7 downto 0);
signal ram : t_ram;
begin
process( clk )
begin
if clk'event and clk = '1' then
if we = '1' then
ram( conv_integer(a)) <= di;
end if;
end if;
end process;
spo <= ram(conv_integer(a));
dpo <= ram(conv_integer(dpra));
leds <= ram(127);
end architecture structure_ram;
|
mit
|
cadesalaberry/digital-system-design
|
lab3/g23_HMS_Counter.vhd
|
1
|
2626
|
-- A timer test-bed circuit.
--
-- entity name: g23_mars_timer
--
-- Copyright (C) 2014 cadesalaberry, grahamludwinski
--
-- Version 1.0
--
-- Author:
-- Charles-Antoine de Salaberry; [email protected],
-- Graham Ludwinski; [email protected]
--
-- Date: 13/03/2014
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.all;
USE ieee.numeric_std.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY g23_HMS_counter IS
PORT (
h_set : IN STD_LOGIC_VECTOR(4 downto 0);
m_set : IN STD_LOGIC_VECTOR(5 downto 0);
s_set : IN STD_LOGIC_VECTOR(5 downto 0);
load_enable : IN STD_LOGIC;
count_enable: IN STD_LOGIC;
sec_clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
hours : OUT STD_LOGIC_VECTOR(4 downto 0);
minutes : OUT STD_LOGIC_VECTOR(5 downto 0);
seconds : OUT STD_LOGIC_VECTOR(5 downto 0);
end_of_day : OUT STD_LOGIC
);
END g23_HMS_counter;
ARCHITECTURE alpha OF g23_HMS_counter IS
signal h : STD_LOGIC_VECTOR(4 downto 0);
signal m : STD_LOGIC_VECTOR(5 downto 0);
signal s : STD_LOGIC_VECTOR(5 downto 0);
signal h_maxed : STD_LOGIC;
signal m_maxed : STD_LOGIC;
signal s_maxed : STD_LOGIC;
signal earth_clk : STD_LOGIC;
signal reset_inv : STD_LOGIC;
COMPONENT g23_earth_timer
PORT (
clk : in STD_LOGIC;
enable : in STD_LOGIC;
reset : in STD_LOGIC;
pulse : out STD_LOGIC
);
END COMPONENT;
BEGIN
reset_inv <= NOT reset;
end_of_day <= h_maxed AND m_maxed AND s_maxed;
hours <= h;
minutes <= m;
seconds <= s;
h_maxed <= '1' WHEN (h = "10111") ELSE '0';
m_maxed <= '1' WHEN (m = "111011") ELSE '0';
s_maxed <= '1' WHEN (s = "111011") ELSE '0';
seconds_counter : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_modulus => 60,
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 6
)
PORT MAP (
aload => load_enable,
aclr => reset_inv,
clock => clk,
data => s_set,
cnt_en => sec_clock,
q => s
);
minutes_counter : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_modulus => 60,
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 6
)
PORT MAP (
aload => load_enable,
aclr => reset_inv,
clock => clk,
data => m_set,
cnt_en => sec_clock AND s_maxed,
q => m
);
hours_counter : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_modulus => 24,
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 5
)
PORT MAP (
aload => load_enable,
aclr => reset_inv,
clock => clk,
data => h_set,
cnt_en => sec_clock AND m_maxed AND s_maxed,
q => h
);
END alpha;
|
mit
|
jonathanrainer/serial_processors_project
|
simulations/greendroid_core_simulations/sources/utsa-var-args/complete_utsa_va_args_core.vhd
|
1
|
2750
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity UTSA_VA_ARGSCoreAndMemory is
PORT (
in0 : IN std_logic_vector(31 DOWNTO 0);
in1 : IN std_logic_vector(31 DOWNTO 0);
in2 : IN std_logic_vector(31 DOWNTO 0);
out0 : OUT std_logic_vector(31 DOWNTO 0);
out1 : OUT std_logic_vector(31 DOWNTO 0);
out2 : OUT std_logic_vector(31 DOWNTO 0);
frame_pointer : IN std_logic_vector(31 DOWNTO 0);
frame_pointer_out : OUT std_logic_vector(31 DOWNTO 0);
rst : IN std_logic;
clck : IN std_logic;
mem_wait : IN std_logic;
mem_push : IN std_logic_vector(31 DOWNTO 0)
);
end UTSA_VA_ARGSCoreAndMemory;
architecture Structure of UTSA_VA_ARGSCoreAndMemory is
component GreenDroidUTSA_VA_ARGSCore
PORT (
i00 : IN std_logic_vector(31 DOWNTO 0);
i01 : IN std_logic_vector(31 DOWNTO 0);
i02 : IN std_logic_vector(31 DOWNTO 0);
r00 : OUT std_logic_vector(31 DOWNTO 0);
r01 : OUT std_logic_vector(31 DOWNTO 0);
r02 : OUT std_logic_vector(31 DOWNTO 0);
FP : IN std_logic_vector(31 DOWNTO 0);
FPout : OUT std_logic_vector(31 DOWNTO 0);
M_ADDR : OUT std_logic_vector(31 DOWNTO 0);
M_DATA : INOUT std_logic_vector(31 DOWNTO 0);
M_RD : INOUT std_logic;
M_WR : INOUT std_logic;
M_RDY : IN std_logic;
reset : IN std_logic;
CLK : IN std_logic
);
end component;
component mem
PORT (
M_ADDR : IN std_logic_vector(31 DOWNTO 0);
M_DATA : INOUT std_logic_vector(31 DOWNTO 0);
M_RD : IN std_logic;
M_WR : IN std_logic;
M_RDY : OUT std_logic;
MWAIT : IN std_logic;
MDAT : IN std_logic_vector(31 DOWNTO 0)
);
end component;
signal sig_M_ADDR, sig_M_DATA : std_logic_vector(31 DOWNTO 0);
signal sig_M_RD, sig_M_WR, sig_M_RDY : std_logic;
begin
Core: GreenDroidUTSA_VA_ARGSCore
port map (
i00 => in0, i01 => in1, i02 => in2,
r00 => out0, r01 => out1, r02 => out2,
FP => frame_pointer, FPout => frame_pointer_out,
M_ADDR => sig_M_ADDR,
M_DATA => sig_M_DATA,
M_RD => sig_M_RD,
M_WR => sig_M_WR,
M_RDY => sig_M_RDY,
reset => rst,
CLK => clck
);
mymem: mem
port map(
M_ADDR => sig_M_ADDR,
M_DATA => sig_M_DATA,
M_RD => sig_M_RD,
M_WR => sig_M_WR,
M_RDY => sig_M_RDY,
MWAIT => mem_wait,
MDAT => mem_push
);
end Structure;
|
mit
|
jonathanrainer/serial_processors_project
|
simulations/greendroid_core_simulations/sources/add64/___add64__--00_C.vhd
|
1
|
5265
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;
ENTITY GreenDroidADD64Core IS
PORT (
i00 : IN std_logic_vector(31 DOWNTO 0);
i01 : IN std_logic_vector(31 DOWNTO 0);
i02 : IN std_logic_vector(31 DOWNTO 0);
r00 : OUT std_logic_vector(31 DOWNTO 0);
r01 : OUT std_logic_vector(31 DOWNTO 0);
r02 : OUT std_logic_vector(31 DOWNTO 0);
FP : IN std_logic_vector(31 DOWNTO 0);
FPout : OUT std_logic_vector(31 DOWNTO 0);
M_ADDR : OUT std_logic_vector(31 DOWNTO 0);
M_DATA : INOUT std_logic_vector(31 DOWNTO 0);
M_RD : INOUT std_logic;
M_WR : INOUT std_logic;
M_RDY : IN std_logic;
reset : IN std_logic;
CLK : IN std_logic
);
END ENTITY;
ARCHITECTURE Behavioural OF GreenDroidADD64Core IS
TYPE States IS (ST_INIT,WS_INIT,ST_RESET,ST00,WS00,ST01,WS01,ST02,WS02,ST03,WS03,ST04,WS04,ST_END);
SIGNAL Mstate : States;
BEGIN
-- CONTROL PROCESS --------
PROCESS(clk,reset)
BEGIN
IF reset='1' THEN
Mstate <= ST_RESET;
ELSIF(rising_edge(clk)) THEN
CASE Mstate IS
WHEN ST_RESET => Mstate <= ST_INIT;
WHEN ST_INIT => IF M_RDY='1' THEN Mstate <= ST00; ELSE Mstate <= WS_INIT; END IF;
WHEN WS_INIT => IF M_RDY='1' THEN Mstate <= ST00; END IF;
WHEN ST00 => IF M_RDY='1' THEN Mstate <= ST01; ELSE Mstate <= WS00; END IF;
WHEN WS00 => IF M_RDY='1' THEN Mstate <= ST01; END IF;
WHEN ST01 => IF M_RDY='1' THEN Mstate <= ST02; ELSE Mstate <= WS01; END IF;
WHEN WS01 => IF M_RDY='1' THEN Mstate <= ST02; END IF;
WHEN ST02 => IF M_RDY='1' THEN Mstate <= ST03; ELSE Mstate <= WS02; END IF;
WHEN WS02 => IF M_RDY='1' THEN Mstate <= ST03; END IF;
WHEN ST03 => IF M_RDY='1' THEN Mstate <= ST04; ELSE Mstate <= WS03; END IF;
WHEN WS03 => IF M_RDY='1' THEN Mstate <= ST04; END IF;
WHEN ST04 | WS04| ST_END => WHEN OTHERS =>
END CASE;
END IF;
END PROCESS;
-- EXECUTE PROCESS --------
PROCESS(clk,reset)
VARIABLE T,s0,s1,s2,s3,s4,s5,s6,s7,fpi :std_logic_vector(31 DOWNTO 0);
BEGIN
IF(reset='1') THEN
-- reset any internal states --
s0 := (OTHERS=>'0');
s1 := (OTHERS=>'0');
s2 := (OTHERS=>'0');
s3 := (OTHERS=>'0');
s4 := (OTHERS=>'0');
s5 := (OTHERS=>'0');
s6 := (OTHERS=>'0');
s7 := (OTHERS=>'0');
fpi:=(OTHERS=>'0');
M_ADDR <= (OTHERS=>'Z');
M_DATA <= (OTHERS=>'Z');
M_RD <= 'Z';
M_WR <= 'Z';
ELSIF(rising_edge(clk)) THEN
M_DATA <="ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
CASE Mstate IS
WHEN ST_INIT =>
-- connect 3 input params here --
s0 := i00;
s1 := i01;
s2 := i02;
fpi := FP;
--lit ;
s7 := s6;
s6 := s5;
s5 := s4;
s4 := s3;
s3 := s2;
s2 := s1;
s1 := s0;
s0:= std_logic_vector(to_unsigned(8, 32)); --fp- ;
fpi:=fpi+s0 ;
s0 := s1;
s1 := s2;
s2 := s3;
s3 := s4;
s4 := s5;
s5 := s6;
s6 := s7;
WHEN ST00 =>
--rsd3 ;
T:=s2 ;
s2:=s1 ;
s1:=s0 ;
s0:=T ;
--copy1 ;
s7 := s6;
s6 := s5;
s5 := s4;
s4 := s3;
s3 := s2;
s2 := s1;
s1 := s0;
--copy3 ;
T:= s2 ;
s7 := s6;
s6 := s5;
s5 := s4;
s4 := s3;
s3 := s2;
s2 := s1;
s1 := s0;
s0:=T ;
--add ;
s0:=s0+s1 ;
s1 := s2;
s2 := s3;
s3 := s4;
s4 := s5;
s5 := s6;
s6 := s7;
WHEN ST01 =>
--shr ;
s0 := '0' & s0(31 DOWNTO 1) ;
--rsd2 ;
T:=s0 ;
s0:=s1 ;
s1:=T ;
--shr ;
s0 := '0' & s0(31 DOWNTO 1) ;
--add ;
s0:=s0+s1 ;
s1 := s2;
s2 := s3;
s3 := s4;
s4 := s5;
s5 := s6;
s6 := s7;
--lit ;
s7 := s6;
s6 := s5;
s5 := s4;
s4 := s3;
s3 := s2;
s2 := s1;
s1 := s0;
s0:= std_logic_vector(to_unsigned(31, 32)); --rsd2 ;
T:=s0 ;
s0:=s1 ;
s1:=T ;
--M> @loc 1
M_ADDR <= std_logic_vector(to_unsigned(1,32))+fpi;
M_RD <='1';
M_WR <='Z';
WHEN ST02 =>
s7 := s6;
s6 := s5;
s5 := s4;
s4 := s3;
s3 := s2;
s2 := s1;
s1 := s0;
s0 := M_DATA;
M_RD <='Z';
M_WR <='Z';
--add ;
s0:=s0+s1 ;
s1 := s2;
s2 := s3;
s3 := s4;
s4 := s5;
s5 := s6;
s6 := s7;
--add ;
s0:=s0+s1 ;
s1 := s2;
s2 := s3;
s3 := s4;
s4 := s5;
s5 := s6;
s6 := s7;
--lit ;
s7 := s6;
s6 := s5;
s5 := s4;
s4 := s3;
s3 := s2;
s2 := s1;
s1 := s0;
s0:= std_logic_vector(to_unsigned(32, 32));
--M> @loc 0
M_ADDR <= std_logic_vector(to_unsigned(0,32))+fpi;
M_RD <='1';
M_WR <='Z';
WHEN ST03 =>
s7 := s6;
s6 := s5;
s5 := s4;
s4 := s3;
s3 := s2;
s2 := s1;
s1 := s0;
s0 := M_DATA;
M_RD <='Z';
M_WR <='Z';
--or ;
s0:= s1 OR s0 ;
s1 := s2;
s2 := s3;
s3 := s4;
s4 := s5;
s5 := s6;
s6 := s7;
-- recover 3 results here --
r00 <= s0;
r01 <= s1;
r02 <= s2;
FPout <= fpi;
WHEN OTHERS =>
END CASE;
END IF;
END PROCESS;
END ARCHITECTURE;
|
mit
|
Pajeh/mips1
|
test/vhdl/hdllab.vhd
|
1
|
8253
|
-- revision history:
-- 06.07.2015 Alex Schönberger created
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.ALL;
library WORK;
use WORK.cpu_pack.all;
use WORK.memory_pack.memory;
use WORK.uart_pack.uart;
entity hdllab is
port(
-- general: CLK and RESET
clk_p : in std_logic;
clk_n : in std_logic;
rst : in std_logic;
-- UART interface
rx : in std_logic;
tx : out std_logic;
-- LED indication
leds : out std_logic_vector(7 downto 0)
);
end entity hdllab;
architecture behav_hdllab of hdllab is
-- ____ ____ _ _ ___ ____ _ _ ____ _ _ ___ ____
-- | | | |\/| |__] | | |\ | |___ |\ | | [__
-- |___ |__| | | | |__| | \| |___ | \| | ___]
--
-- PLL for clock generation
--
component hdllab_pll is
port ( CLKIN1_N_IN : in std_logic;
CLKIN1_P_IN : in std_logic;
RST_IN : in std_logic;
CLKFBOUT_OUT : out std_logic;
CLKOUT0_OUT : out std_logic;
LOCKED_OUT : out std_logic);
end component;
--
-- general control signals
--
signal sys_clk : std_logic;
signal pll_lock : std_logic;
--
-- -------- UART interface ------
--
signal t_req : std_logic; -- write request
signal t_ack : std_logic; -- write acknowledge
signal t_data : std_logic_vector(7 downto 0);
signal r_req : std_logic; -- read request
signal r_ack : std_logic; -- read acknowledge
signal r_data : std_logic_vector(7 downto 0);
--
-- -------- CPU INTERFACE --------
--
signal instr_addr : std_logic_vector(31 downto 0);
signal data_addr,
i_data_addr : std_logic_vector(31 downto 0);
signal rd_mask : std_logic_vector(3 downto 0);
signal wr_mask,
i_wr_mask : std_logic_vector(3 downto 0);
signal instr_stall,
i_instr_stall : std_logic;
signal data_stall : std_logic;
signal instr_in : std_logic_vector(31 downto 0);
signal data_to_cpu : std_logic_vector(31 downto 0);
signal data_from_cpu,
i_data_from_cpu : std_logic_vector(31 downto 0);
--
-- TB control signals
--
--
-- state machine
--
type t_state is (sIDLE, sUART, sCPU);
signal state, n_state : t_state;
type t_addr is
record
load : std_logic; -- load initial value
inc : std_logic; -- increment
full : std_logic; -- indicate full memory
val : unsigned(7 downto 0); -- current memory addr
end record;
signal addr : t_addr;
constant MEM_ADDR_INIT : unsigned(7 downto 0) := (others => '0');
--
-- main CPU switch
--
signal cpu_switch : std_logic;
--
-- Full design only with FPGA memory
--
for u2_memory: memory use entity WORK.memory(fpga_memory);
begin ---------------- BEGIN ------------------ BEGIN -------------------------
process( sys_clk )
begin
if rising_edge( sys_clk ) then
if rst = '1' then
state <= sIDLE;
addr.val <= MEM_ADDR_INIT;
else
state <= n_state;
if addr.load = '1' then
addr.val <= MEM_ADDR_INIT + 1;
elsif addr.inc = '1' then
addr.val <= addr.val + 1;
end if;
end if;
end if;
end process;
--
-- address value is counter one round
--
addr.full <= '1' when addr.val = MEM_ADDR_INIT else '0';
--
-- TEST BENCH STATE LOGIC
--
tb_state_logic:
process( state, r_req, addr.full )
begin
--
-- ######## DEFAULT ###########
--
-- memory address contorl
--
addr.load <= '0'; -- no load
addr.inc <= '0'; -- no increment
--
-- UART interface
--
r_ack <= '0'; -- no acknowledge
--
-- main CPU switch
--
cpu_switch <= '0'; -- switch to TB logic
--
-- state
--
n_state <= sIDLE; -- wait for data over UART
--
-- ######### STATE LOGIC ######
--
case state is
-- <<<<<<<<<<< IDLE >>>>>>>>
when sIDLE =>
if r_req = '1' then -- data comes over UART
addr.load <= '1'; -- load initial value
r_ack <= '1'; -- acknowlege data
n_state <= sUART; -- go to UART logic
end if;
-- <<<<<<<<<<<< UART >>>>>>>
when sUART =>
n_state <= sUART; -- remain in the state
if addr.full = '1' then -- all data are written to memory
n_state <= sCPU;
elsif r_req = '1' then -- data are coming over UART
r_ack <= '1'; -- acknowledge them
addr.inc <= '1'; -- get next memory address
end if;
-- <<<<<<<<<<<<< CPU >>>>>>
when sCPU =>
cpu_switch <= '1'; -- apply main CPU switch to CPU <-> MEMORY
n_state <= sCPU; -- remain in the state
end case;
end process;
--
-- UART SEND LOGIC is unused
--
t_req <= '0';
t_data <= (others => '0');
-- _ _ ____ _ _ _ _ _ _ _ _ _
-- |\/| |__| | |\ | |\/| | | \/
-- | | | | | | \| | | |__| _/\_
--
-- connects control signal to TB or CPU
--
i_instr_stall <= instr_stall when cpu_switch = '1' else '1'; -- instruction stall -> stops CPU
i_data_addr <= data_addr when cpu_switch = '1' else x"0000_00" & std_logic_vector(addr.val); -- memory address
i_wr_mask <= wr_mask when cpu_switch = '1' else "0001"; -- write bytes to memory
i_data_from_cpu <= data_from_cpu when cpu_switch = '1' else std_logic_vector(r_data) & -- data to memory
std_logic_vector(r_data) &
std_logic_vector(r_data) &
std_logic_vector(r_data);
-- ____ ___ _ _
-- | |__] | |
-- |___ | |__|
u1_cpu: cpu
PORT MAP(
clk => sys_clk, rst => rst,
instr_in => instr_in, data_to_cpu => data_to_cpu,
instr_stall => i_instr_stall, data_stall => data_stall,
instr_addr => instr_addr, data_addr => data_addr,
rd_mask => rd_mask, wr_mask => wr_mask,
data_from_cpu => data_from_cpu
);
-- _ _ ____ _ _ ____ ____ _ _
-- |\/| |___ |\/| | | |__/ \_/
-- | | |___ | | |__| | \ |
u2_memory: memory
PORT MAP(
clk => sys_clk, rst => rst,
wr_mask => i_wr_mask, rd_mask => rd_mask,
instr_stall => instr_stall, data_stall => data_stall,
prog_addr => instr_addr, data_addr => i_data_addr,
prog_out => instr_in, data_in => i_data_from_cpu,
data_out => data_to_cpu, leds => leds
);
-- _ _ ____ ____ ___
-- | | |__| |__/ |
-- |__| | | | \ |
u3_uart: uart
PORT MAP(
clk => sys_clk, rst => rst,
t_req => t_req, t_ack => t_ack,
t_data => t_data,
r_req => r_req, r_ack => r_ack,
r_data => r_data,
rx => rx, tx => tx
);
-- ___ _ _
-- |__] | |
-- | |___ |___
u4_pll: hdllab_pll
PORT MAP(
CLKIN1_N_IN => clk_n, CLKIN1_P_IN => clk_p,
RST_IN => '0',
CLKFBOUT_OUT => open,
CLKOUT0_OUT => sys_clk,
LOCKED_OUT => pll_lock
);
end behav_hdllab;
|
mit
|
Pajeh/mips1
|
test/syn/hdllab/ipcore_dir/hdllab_pll.vhd
|
1
|
3638
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.5
-- \ \ Application : xaw2vhdl
-- / / Filename : hdllab_pll.vhd
-- /___/ /\ Timestamp : 07/13/2015 11:12:37
-- \ \ / \
-- \___\/\___\
--
--Command: xaw2vhdl-st /home/alexs/LEHRE/IES/HDL-Lab/hdllab/src/test/syn/hdllab/ipcore_dir/./hdllab_pll.xaw /home/alexs/LEHRE/IES/HDL-Lab/hdllab/src/test/syn/hdllab/ipcore_dir/./hdllab_pll
--Design Name: hdllab_pll
--Device: xc5vfx70t-1ff1136
--
-- Module hdllab_pll
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: Synplify
-- For block PLL_ADV_INST, Estimated PLL Jitter for CLKOUT0 = 0.141 ns
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity hdllab_pll is
port ( CLKIN1_N_IN : in std_logic;
CLKIN1_P_IN : in std_logic;
RST_IN : in std_logic;
CLKFBOUT_OUT : out std_logic;
CLKOUT0_OUT : out std_logic;
LOCKED_OUT : out std_logic);
end hdllab_pll;
architecture BEHAVIORAL of hdllab_pll is
signal CLKFBIN_IN : std_logic;
signal CLKFBOUT_BUF : std_logic;
signal CLKIN1_IBUFGDS : std_logic;
signal CLKOUT0_BUF : std_logic;
signal GND_BIT : std_logic;
signal GND_BUS_5 : std_logic_vector (4 downto 0);
signal GND_BUS_16 : std_logic_vector (15 downto 0);
signal VCC_BIT : std_logic;
begin
GND_BIT <= '0';
GND_BUS_5(4 downto 0) <= "00000";
GND_BUS_16(15 downto 0) <= "0000000000000000";
VCC_BIT <= '1';
CLKFBOUT_OUT <= CLKFBIN_IN;
CLKFBOUT_BUFG_INST : BUFG
port map (I=>CLKFBOUT_BUF,
O=>CLKFBIN_IN);
CLKIN1_IBUFGDS_INST : IBUFGDS
port map (I=>CLKIN1_P_IN,
IB=>CLKIN1_N_IN,
O=>CLKIN1_IBUFGDS);
CLKOUT0_BUFG_INST : BUFG
port map (I=>CLKOUT0_BUF,
O=>CLKOUT0_OUT);
PLL_ADV_INST : PLL_ADV
generic map( BANDWIDTH => "OPTIMIZED",
CLKIN1_PERIOD => 5.000,
CLKIN2_PERIOD => 10.000,
CLKOUT0_DIVIDE => 3,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 2,
CLKFBOUT_MULT => 6,
CLKFBOUT_PHASE => 0.0,
REF_JITTER => 0.005000)
port map (CLKFBIN=>CLKFBIN_IN,
CLKINSEL=>VCC_BIT,
CLKIN1=>CLKIN1_IBUFGDS,
CLKIN2=>GND_BIT,
DADDR(4 downto 0)=>GND_BUS_5(4 downto 0),
DCLK=>GND_BIT,
DEN=>GND_BIT,
DI(15 downto 0)=>GND_BUS_16(15 downto 0),
DWE=>GND_BIT,
REL=>GND_BIT,
RST=>RST_IN,
CLKFBDCM=>open,
CLKFBOUT=>CLKFBOUT_BUF,
CLKOUTDCM0=>open,
CLKOUTDCM1=>open,
CLKOUTDCM2=>open,
CLKOUTDCM3=>open,
CLKOUTDCM4=>open,
CLKOUTDCM5=>open,
CLKOUT0=>CLKOUT0_BUF,
CLKOUT1=>open,
CLKOUT2=>open,
CLKOUT3=>open,
CLKOUT4=>open,
CLKOUT5=>open,
DO=>open,
DRDY=>open,
LOCKED=>LOCKED_OUT);
end BEHAVIORAL;
|
mit
|
cadesalaberry/digital-system-design
|
lab4/g23_7_segment_decoder.vhd
|
3
|
2137
|
---- generates the appropriate 7-segment display associated with the input code
--
-- entity name: g23_7_segment_decoder
--
-- Copyright (C) 2014 cadesalaberry, grahamludwinski
--
-- Version 1.0
--
-- Author:
-- Charles-Antoine de Salaberry; [email protected],
-- Graham Ludwinski; [email protected]
--
-- Date: 13/02/2014
library ieee; -- allows use of the std_logic_vector type
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- allows use of the unsigned type
entity g23_7_segment_decoder is
port (
code : in std_logic_vector(3 downto 0);
RippleBlank_In : in std_logic;
RippleBlank_Out : out std_logic;
segments : out std_logic_vector(6 downto 0)
);
end g23_7_segment_decoder;
architecture alpha of g23_7_segment_decoder is
signal temp : std_logic_vector(7 downto 0);
begin
RippleBlank_Out <= temp(7);
segments <= temp(6 downto 0);
with RippleBlank_In & code select
temp <=
"01000000" when "00000", -- '0'
"01111001" when "00001", -- '1'
"00100100" when "00010", -- '2'
"00110000" when "00011", -- '3'
"00011001" when "00100", -- '4'
"00010010" when "00101", -- '5'
"00000010" when "00110", -- '6'
"01111000" when "00111", -- '7'
"00000000" when "01000", -- '8'
"00011000" when "01001", -- '9'
"00001000" when "01010", -- 'A'
"00000011" when "01011", -- 'b'
"00100111" when "01100", -- 'C'
"00100001" when "01101", -- 'd'
"00000110" when "01110", -- 'E'
"00001110" when "01111", -- 'F'
"11111111" when "10000", -- ripple_blank out
"01111001" when "10001", -- '1'
"00100100" when "10010", -- '2'
"00110000" when "10011", -- '3'
"00011001" when "10100", -- '4'
"00010010" when "10101", -- '5'
"00000010" when "10110", -- '6'
"01111000" when "10111", -- '7'
"00000000" when "11000", -- '8'
"00011000" when "11001", -- '9'
"00001000" when "11010", -- 'A'
"00000011" when "11011", -- 'b'
"00100111" when "11100", -- 'C'
"00100001" when "11101", -- 'd'
"00000110" when "11110", -- 'E'
"00001110" when "11111", -- 'F'
"01011010" when others;
end alpha;
|
mit
|
cadesalaberry/digital-system-design
|
lab4/g23_basic_timer.vhd
|
2
|
1210
|
-- A Mars and Earth timer calibrated for a 50MHz clock.
--
-- entity name: g23_mars_timer
--
-- Copyright (C) 2014 cadesalaberry, grahamludwinski
--
-- Version 1.0
--
-- Author:
-- Charles-Antoine de Salaberry; [email protected],
-- Graham Ludwinski; [email protected]
--
-- Date: 13/03/2014
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.all;
ENTITY g23_basic_timer IS
PORT (
clk : in STD_LOGIC;
enable : in STD_LOGIC;
reset : in STD_LOGIC;
EPULSE : out STD_LOGIC;
MPULSE : out STD_LOGIC
);
END g23_basic_timer;
ARCHITECTURE alpha OF g23_basic_timer IS
COMPONENT g23_generic_timer
GENERIC (max : natural := 0);
PORT (
clk : in STD_LOGIC;
enable : in STD_LOGIC;
reset : in STD_LOGIC;
pulse : out STD_LOGIC
);
END COMPONENT;
BEGIN
earth : g23_generic_timer
GENERIC MAP (max => 49999999)
-- GENERIC MAP (max => 1000)
-- GENERIC MAP (max => 100)
PORT MAP (
clk => clk,
enable => enable,
reset => reset,
pulse => EPULSE
);
mars : g23_generic_timer
GENERIC MAP (max => 51374562)
-- GENERIC MAP (max => 1027)
-- GENERIC MAP (max => 102)
PORT MAP (
clk => clk,
enable => enable,
reset => reset,
pulse => MPULSE
);
END alpha;
|
mit
|
plac-lab/TMIIaTest
|
Firmware/src/gig_eth/KC705/gig_eth_mac_fifo_block.vhd
|
3
|
23510
|
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_fifo_block.v
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2004-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This is the FIFO Block level vhdl wrapper for the Tri-Mode
-- Ethernet MAC core. This wrapper enhances the standard MAC core
-- with an example FIFO. The interface to this FIFO is
-- designed to the AXI-S specification.
-- Please refer to core documentation for
-- additional FIFO and AXI-S information.
--
-- _________________________________________________________
-- | |
-- | FIFO BLOCK LEVEL WRAPPER |
-- | |
-- | _____________________ ______________________ |
-- | | _________________ | | | |
-- | | | | | | | |
-- -------->| | TX AXI FIFO | |---->| Tx Tx |--------->
-- | | | | | | AXI-S PHY | |
-- | | |_________________| | | I/F I/F | |
-- | | | | | |
-- AXI | | 10/100/1G | | TRI-MODE ETHERNET | |
-- Stream | | ETHERNET FIFO | | MAC | | PHY I/F
-- | | | | SUPPORT LEVEL | |
-- | | _________________ | | | |
-- | | | | | | | |
-- <--------| | RX AXI FIFO | |<----| Rx Rx |<---------
-- | | | | | | AXI-S PHY | |
-- | | |_________________| | | I/F I/F | |
-- | |_____________________| |______________________| |
-- | |
-- |_________________________________________________________|
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- The module declaration for the fifo block level wrapper.
--------------------------------------------------------------------------------
entity tri_mode_ethernet_mac_0_fifo_block is
port(
gtx_clk : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Reference clock for IDELAYCTRL's
refclk : in std_logic;
-- Receiver Statistics Interface
-----------------------------------------
rx_mac_aclk : out std_logic;
rx_reset : out std_logic;
rx_statistics_vector : out std_logic_vector(27 downto 0);
rx_statistics_valid : out std_logic;
-- Receiver (AXI-S) Interface
------------------------------------------
rx_fifo_clock : in std_logic;
rx_fifo_resetn : in std_logic;
rx_axis_fifo_tready : in std_logic;
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tdata : out std_logic_vector(7 downto 0);
rx_axis_fifo_tlast : out std_logic;
-- Transmitter Statistics Interface
--------------------------------------------
tx_mac_aclk : out std_logic;
tx_reset : out std_logic;
tx_ifg_delay : in std_logic_vector(7 downto 0);
tx_statistics_vector : out std_logic_vector(31 downto 0);
tx_statistics_valid : out std_logic;
-- Transmitter (AXI-S) Interface
---------------------------------------------
tx_fifo_clock : in std_logic;
tx_fifo_resetn : in std_logic;
tx_axis_fifo_tready : out std_logic;
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
tx_axis_fifo_tlast : in std_logic;
-- MAC Control Interface
--------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(15 downto 0);
-- RGMII Interface
--------------------
rgmii_txd : out std_logic_vector(3 downto 0);
rgmii_tx_ctl : out std_logic;
rgmii_txc : out std_logic;
rgmii_rxd : in std_logic_vector(3 downto 0);
rgmii_rx_ctl : in std_logic;
rgmii_rxc : in std_logic;
-- RGMII Inband Status Registers
----------------------------------
inband_link_status : out std_logic;
inband_clock_speed : out std_logic_vector(1 downto 0);
inband_duplex_status : out std_logic;
-- MDIO Interface
-----------------
mdio : inout std_logic;
mdc : out std_logic;
-- AXI-Lite Interface
-----------------
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic;
s_axi_awaddr : in std_logic_vector(11 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(11 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic
);
end tri_mode_ethernet_mac_0_fifo_block;
architecture wrapper of tri_mode_ethernet_mac_0_fifo_block is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of wrapper : architecture is "yes";
------------------------------------------------------------------------------
-- Component declaration for the Tri-Mode Ethernet MAC Support Level wrapper
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_support
port(
gtx_clk : in std_logic;
gtx_clk_out : out std_logic;
gtx_clk90_out : out std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Receiver Interface
----------------------------
rx_enable : out std_logic;
rx_statistics_vector : out std_logic_vector(27 downto 0);
rx_statistics_valid : out std_logic;
rx_mac_aclk : out std_logic;
rx_reset : out std_logic;
rx_axis_mac_tdata : out std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : out std_logic;
rx_axis_mac_tlast : out std_logic;
rx_axis_mac_tuser : out std_logic;
-- Transmitter Interface
-------------------------------
tx_enable : out std_logic;
tx_ifg_delay : in std_logic_vector(7 downto 0);
tx_statistics_vector : out std_logic_vector(31 downto 0);
tx_statistics_valid : out std_logic;
tx_mac_aclk : out std_logic;
tx_reset : out std_logic;
tx_axis_mac_tready : out std_logic;
tx_axis_mac_tvalid : in std_logic;
tx_axis_mac_tdata : in std_logic_vector(7 downto 0);
tx_axis_mac_tlast : in std_logic;
tx_axis_mac_tuser : in std_logic_vector(0 downto 0);
-- MAC Control Interface
------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(15 downto 0);
-- Reference clock for IDELAYCTRL's
refclk : in std_logic;
speedis100 : out std_logic;
speedis10100 : out std_logic;
-- RGMII Interface
------------------
rgmii_txd : out std_logic_vector(3 downto 0);
rgmii_tx_ctl : out std_logic;
rgmii_txc : out std_logic;
rgmii_rxd : in std_logic_vector(3 downto 0);
rgmii_rx_ctl : in std_logic;
rgmii_rxc : in std_logic;
inband_link_status : out std_logic;
inband_clock_speed : out std_logic_vector(1 downto 0);
inband_duplex_status : out std_logic;
-- MDIO Interface
-----------------
mdio : inout std_logic;
mdc : out std_logic;
-- AXI-Lite Interface
-----------------
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic;
s_axi_awaddr : in std_logic_vector(11 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(11 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
mac_irq : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the fifo
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_ten_100_1g_eth_fifo
generic (
FULL_DUPLEX_ONLY : boolean := true); -- If fifo is to be used only in full
-- duplex set to true for optimised implementation
port (
tx_fifo_aclk : in std_logic;
tx_fifo_resetn : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tlast : in std_logic;
tx_axis_fifo_tready : out std_logic;
tx_mac_aclk : in std_logic;
tx_mac_resetn : in std_logic;
tx_axis_mac_tdata : out std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : out std_logic;
tx_axis_mac_tlast : out std_logic;
tx_axis_mac_tready : in std_logic;
tx_axis_mac_tuser : out std_logic;
tx_fifo_overflow : out std_logic;
tx_fifo_status : out std_logic_vector(3 downto 0);
tx_collision : in std_logic;
tx_retransmit : in std_logic;
rx_fifo_aclk : in std_logic;
rx_fifo_resetn : in std_logic;
rx_axis_fifo_tdata : out std_logic_vector(7 downto 0);
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tlast : out std_logic;
rx_axis_fifo_tready : in std_logic;
rx_mac_aclk : in std_logic;
rx_mac_resetn : in std_logic;
rx_axis_mac_tdata : in std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : in std_logic;
rx_axis_mac_tlast : in std_logic;
rx_axis_mac_tuser : in std_logic;
rx_fifo_status : out std_logic_vector(3 downto 0);
rx_fifo_overflow : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the reset synchroniser
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_reset_sync
port (
reset_in : in std_logic; -- Active high asynchronous reset
enable : in std_logic;
clk : in std_logic; -- clock to be sync'ed to
reset_out : out std_logic -- "Synchronised" reset signal
);
end component;
------------------------------------------------------------------------------
-- Internal signals used in this fifo block level wrapper.
------------------------------------------------------------------------------
signal rx_mac_aclk_int : std_logic; -- MAC Rx clock
signal tx_mac_aclk_int : std_logic; -- MAC Tx clock
signal rx_reset_int : std_logic; -- MAC Rx reset
signal tx_reset_int : std_logic; -- MAC Tx reset
signal tx_mac_resetn : std_logic;
signal rx_mac_resetn : std_logic;
signal tx_mac_reset : std_logic;
signal rx_mac_reset : std_logic;
-- MAC receiver client I/F
signal rx_axis_mac_tdata : std_logic_vector(7 downto 0);
signal rx_axis_mac_tvalid : std_logic;
signal rx_axis_mac_tlast : std_logic;
signal rx_axis_mac_tuser : std_logic;
-- MAC transmitter client I/F
signal tx_axis_mac_tdata : std_logic_vector(7 downto 0);
signal tx_axis_mac_tvalid : std_logic;
signal tx_axis_mac_tready : std_logic;
signal tx_axis_mac_tlast : std_logic;
signal tx_axis_mac_tuser : std_logic_vector(0 downto 0);
begin
------------------------------------------------------------------------------
-- Connect the output clock signals
------------------------------------------------------------------------------
rx_mac_aclk <= rx_mac_aclk_int;
tx_mac_aclk <= tx_mac_aclk_int;
rx_reset <= rx_reset_int;
tx_reset <= tx_reset_int;
------------------------------------------------------------------------------
-- Instantiate the Tri-Mode Ethernet MAC Support Level wrapper
------------------------------------------------------------------------------
trimac_sup_block : tri_mode_ethernet_mac_0_support
port map(
gtx_clk => gtx_clk,
gtx_clk_out => open,
gtx_clk90_out => open,
-- asynchronous reset
glbl_rstn => glbl_rstn,
rx_axi_rstn => rx_axi_rstn,
tx_axi_rstn => tx_axi_rstn,
-- Client Receiver Interface
rx_enable => open,
rx_statistics_vector => rx_statistics_vector,
rx_statistics_valid => rx_statistics_valid,
rx_mac_aclk => rx_mac_aclk_int,
rx_reset => rx_reset_int,
rx_axis_mac_tdata => rx_axis_mac_tdata,
rx_axis_mac_tvalid => rx_axis_mac_tvalid,
rx_axis_mac_tlast => rx_axis_mac_tlast,
rx_axis_mac_tuser => rx_axis_mac_tuser,
-- Client Transmitter Interface
tx_enable => open,
tx_ifg_delay => tx_ifg_delay,
tx_statistics_vector => tx_statistics_vector,
tx_statistics_valid => tx_statistics_valid,
tx_mac_aclk => tx_mac_aclk_int,
tx_reset => tx_reset_int,
tx_axis_mac_tdata => tx_axis_mac_tdata ,
tx_axis_mac_tvalid => tx_axis_mac_tvalid,
tx_axis_mac_tlast => tx_axis_mac_tlast,
tx_axis_mac_tuser => tx_axis_mac_tuser,
tx_axis_mac_tready => tx_axis_mac_tready,
-- Flow Control
pause_req => pause_req,
pause_val => pause_val,
-- Reference clock for IDELAYCTRL's
refclk => refclk,
-- speed control
speedis100 => open,
speedis10100 => open,
-- RGMII Interface
rgmii_txd => rgmii_txd,
rgmii_tx_ctl => rgmii_tx_ctl,
rgmii_txc => rgmii_txc,
rgmii_rxd => rgmii_rxd,
rgmii_rx_ctl => rgmii_rx_ctl,
rgmii_rxc => rgmii_rxc,
inband_link_status => inband_link_status,
inband_clock_speed => inband_clock_speed,
inband_duplex_status => inband_duplex_status,
-- MDIO Interface
-----------------
mdio => mdio,
mdc => mdc,
-- AXI lite interface
s_axi_aclk => s_axi_aclk,
s_axi_resetn => s_axi_resetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
mac_irq => open
);
------------------------------------------------------------------------------
-- Instantiate the user side FIFO
------------------------------------------------------------------------------
-- locally reset sync the mac generated resets - the resets are already fully sync
-- so adding a reset sync shouldn't change that
rx_mac_reset_gen : tri_mode_ethernet_mac_0_reset_sync
port map (
clk => rx_mac_aclk_int,
enable => '1',
reset_in => rx_reset_int,
reset_out => rx_mac_reset
);
tx_mac_reset_gen : tri_mode_ethernet_mac_0_reset_sync
port map (
clk => tx_mac_aclk_int,
enable => '1',
reset_in => tx_reset_int,
reset_out => tx_mac_reset
);
-- create inverted mac resets as the FIFO expects AXI compliant resets
tx_mac_resetn <= not tx_mac_reset;
rx_mac_resetn <= not rx_mac_reset;
user_side_FIFO : tri_mode_ethernet_mac_0_ten_100_1g_eth_fifo
generic map(
FULL_DUPLEX_ONLY => true
)
port map(
-- Transmit FIFO MAC TX Interface
tx_fifo_aclk => tx_fifo_clock,
tx_fifo_resetn => tx_fifo_resetn,
tx_axis_fifo_tready => tx_axis_fifo_tready,
tx_axis_fifo_tvalid => tx_axis_fifo_tvalid,
tx_axis_fifo_tdata => tx_axis_fifo_tdata,
tx_axis_fifo_tlast => tx_axis_fifo_tlast,
tx_mac_aclk => tx_mac_aclk_int,
tx_mac_resetn => tx_mac_resetn,
tx_axis_mac_tready => tx_axis_mac_tready,
tx_axis_mac_tvalid => tx_axis_mac_tvalid,
tx_axis_mac_tdata => tx_axis_mac_tdata,
tx_axis_mac_tlast => tx_axis_mac_tlast,
tx_axis_mac_tuser => tx_axis_mac_tuser(0),
tx_fifo_overflow => open,
tx_fifo_status => open,
tx_collision => '0',
tx_retransmit => '0',
rx_fifo_aclk => rx_fifo_clock,
rx_fifo_resetn => rx_fifo_resetn,
rx_axis_fifo_tready => rx_axis_fifo_tready,
rx_axis_fifo_tvalid => rx_axis_fifo_tvalid,
rx_axis_fifo_tdata => rx_axis_fifo_tdata,
rx_axis_fifo_tlast => rx_axis_fifo_tlast,
rx_mac_aclk => rx_mac_aclk_int,
rx_mac_resetn => rx_mac_resetn,
rx_axis_mac_tvalid => rx_axis_mac_tvalid,
rx_axis_mac_tdata => rx_axis_mac_tdata,
rx_axis_mac_tlast => rx_axis_mac_tlast,
rx_axis_mac_tuser => rx_axis_mac_tuser,
rx_fifo_status => open,
rx_fifo_overflow => open
);
end wrapper;
|
mit
|
cadesalaberry/digital-system-design
|
lab2/g23_bigcounter.vhd
|
1
|
1260
|
-- A simple 0-59 up counter.
--
-- entity name: g23_mars_timer
--
-- Copyright (C) 2014 cadesalaberry, grahamludwinski
--
-- Version 1.0
--
-- Author:
-- Charles-Antoine de Salaberry; [email protected],
-- Graham Ludwinski; [email protected]
--
-- Date: 13/03/2014
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
ENTITY g23_count_to_59 IS
PORT (
clk : in STD_LOGIC;
enable : in STD_LOGIC;
reset : in STD_LOGIC;
sec_msd : out STD_LOGIC_VECTOR(2 downto 0);
sec_lsd : out STD_LOGIC_VECTOR(3 downto 0)
);
END g23_count_to_59;
ARCHITECTURE alpha OF g23_count_to_59 IS
signal decade_reached : STD_LOGIC;
signal seconds_msd : STD_LOGIC_VECTOR (2 downto 0);
signal seconds_lsd : STD_LOGIC_VECTOR (3 downto 0);
BEGIN
decade_reached <= '1' when (seconds_lsd = "1001") else '0';
sec_msd <= seconds_msd;
sec_lsd <= seconds_lsd;
count_to_9 : lpm_counter
GENERIC MAP (
lpm_modulus => 10,
lpm_width => 4
)
PORT MAP (
clock => clk,
aclr => reset,
q => seconds_lsd
);
count_to_5 : lpm_counter
GENERIC MAP(
lpm_modulus => 6,
lpm_width => 3
)
PORT MAP(
cnt_en => decade_reached,
clock => clk,
aclr => reset,
q => seconds_msd
);
END alpha;
|
mit
|
agural/FPGA-Oscilloscope
|
osc/vramctrl/lpm_compare5.vhd
|
2
|
4429
|
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COMPARE
-- ============================================================
-- File Name: lpm_compare5.vhd
-- Megafunction Name(s):
-- LPM_COMPARE
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare5 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
alb : OUT STD_LOGIC
);
END lpm_compare5;
ARCHITECTURE SYN OF lpm_compare5 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1_bv : BIT_VECTOR (8 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (8 DOWNTO 0);
COMPONENT lpm_compare
GENERIC (
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
alb : OUT STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1_bv(8 DOWNTO 0) <= "100011100";
sub_wire1 <= To_stdlogicvector(sub_wire1_bv);
alb <= sub_wire0;
LPM_COMPARE_component : LPM_COMPARE
GENERIC MAP (
lpm_hint => "ONE_INPUT_IS_CONSTANT=YES",
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 9
)
PORT MAP (
dataa => dataa,
datab => sub_wire1,
alb => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "0"
-- Retrieval info: PRIVATE: AgeB NUMERIC "0"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "1"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "284"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "9"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=YES"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "9"
-- Retrieval info: USED_PORT: alb 0 0 0 0 OUTPUT NODEFVAL "alb"
-- Retrieval info: USED_PORT: dataa 0 0 9 0 INPUT NODEFVAL "dataa[8..0]"
-- Retrieval info: CONNECT: @dataa 0 0 9 0 dataa 0 0 9 0
-- Retrieval info: CONNECT: @datab 0 0 9 0 284 0 0 9 0
-- Retrieval info: CONNECT: alb 0 0 0 0 @alb 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare5.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare5.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare5.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare5.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare5_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
agural/FPGA-Oscilloscope
|
FPGA/lpm_compare5.vhd
|
2
|
4429
|
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COMPARE
-- ============================================================
-- File Name: lpm_compare5.vhd
-- Megafunction Name(s):
-- LPM_COMPARE
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare5 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
alb : OUT STD_LOGIC
);
END lpm_compare5;
ARCHITECTURE SYN OF lpm_compare5 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1_bv : BIT_VECTOR (8 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (8 DOWNTO 0);
COMPONENT lpm_compare
GENERIC (
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
alb : OUT STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1_bv(8 DOWNTO 0) <= "100011100";
sub_wire1 <= To_stdlogicvector(sub_wire1_bv);
alb <= sub_wire0;
LPM_COMPARE_component : LPM_COMPARE
GENERIC MAP (
lpm_hint => "ONE_INPUT_IS_CONSTANT=YES",
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 9
)
PORT MAP (
dataa => dataa,
datab => sub_wire1,
alb => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "0"
-- Retrieval info: PRIVATE: AgeB NUMERIC "0"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "1"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "284"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "9"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=YES"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "9"
-- Retrieval info: USED_PORT: alb 0 0 0 0 OUTPUT NODEFVAL "alb"
-- Retrieval info: USED_PORT: dataa 0 0 9 0 INPUT NODEFVAL "dataa[8..0]"
-- Retrieval info: CONNECT: @dataa 0 0 9 0 dataa 0 0 9 0
-- Retrieval info: CONNECT: @datab 0 0 9 0 284 0 0 9 0
-- Retrieval info: CONNECT: alb 0 0 0 0 @alb 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare5.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare5.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare5.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare5.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare5_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
agural/FPGA-Oscilloscope
|
osc/lpm_compare0.vhd
|
1
|
4464
|
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COMPARE
-- ============================================================
-- File Name: lpm_compare0.vhd
-- Megafunction Name(s):
-- LPM_COMPARE
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare0 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (16 DOWNTO 0);
ageb : OUT STD_LOGIC
);
END lpm_compare0;
ARCHITECTURE SYN OF lpm_compare0 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1_bv : BIT_VECTOR (16 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (16 DOWNTO 0);
COMPONENT lpm_compare
GENERIC (
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
ageb : OUT STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (16 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (16 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1_bv(16 DOWNTO 0) <= "01000110010100000";
sub_wire1 <= To_stdlogicvector(sub_wire1_bv);
ageb <= sub_wire0;
LPM_COMPARE_component : LPM_COMPARE
GENERIC MAP (
lpm_hint => "ONE_INPUT_IS_CONSTANT=YES",
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 17
)
PORT MAP (
dataa => dataa,
datab => sub_wire1,
ageb => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "0"
-- Retrieval info: PRIVATE: AgeB NUMERIC "1"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "0"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "36000"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "17"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=YES"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "17"
-- Retrieval info: USED_PORT: ageb 0 0 0 0 OUTPUT NODEFVAL "ageb"
-- Retrieval info: USED_PORT: dataa 0 0 17 0 INPUT NODEFVAL "dataa[16..0]"
-- Retrieval info: CONNECT: @dataa 0 0 17 0 dataa 0 0 17 0
-- Retrieval info: CONNECT: @datab 0 0 17 0 36000 0 0 17 0
-- Retrieval info: CONNECT: ageb 0 0 0 0 @ageb 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare0.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/vhls/set/solution/syn/vhdl/set_assign_val.vhd
|
4
|
17258
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity set_assign_val is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
m_axi_dest_AWVALID : OUT STD_LOGIC;
m_axi_dest_AWREADY : IN STD_LOGIC;
m_axi_dest_AWADDR : OUT STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_AWID : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_AWLEN : OUT STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_AWSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_dest_AWBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_AWLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_AWCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_AWPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_dest_AWQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_AWREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_AWUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_WVALID : OUT STD_LOGIC;
m_axi_dest_WREADY : IN STD_LOGIC;
m_axi_dest_WDATA : OUT STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_WSTRB : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_WLAST : OUT STD_LOGIC;
m_axi_dest_WID : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_WUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_ARVALID : OUT STD_LOGIC;
m_axi_dest_ARREADY : IN STD_LOGIC;
m_axi_dest_ARADDR : OUT STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_ARID : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_ARLEN : OUT STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_ARSIZE : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_dest_ARBURST : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_ARLOCK : OUT STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_ARCACHE : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_ARPROT : OUT STD_LOGIC_VECTOR (2 downto 0);
m_axi_dest_ARQOS : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_ARREGION : OUT STD_LOGIC_VECTOR (3 downto 0);
m_axi_dest_ARUSER : OUT STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_RVALID : IN STD_LOGIC;
m_axi_dest_RREADY : OUT STD_LOGIC;
m_axi_dest_RDATA : IN STD_LOGIC_VECTOR (31 downto 0);
m_axi_dest_RLAST : IN STD_LOGIC;
m_axi_dest_RID : IN STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_RUSER : IN STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_RRESP : IN STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_BVALID : IN STD_LOGIC;
m_axi_dest_BREADY : OUT STD_LOGIC;
m_axi_dest_BRESP : IN STD_LOGIC_VECTOR (1 downto 0);
m_axi_dest_BID : IN STD_LOGIC_VECTOR (0 downto 0);
m_axi_dest_BUSER : IN STD_LOGIC_VECTOR (0 downto 0);
data1 : IN STD_LOGIC_VECTOR (29 downto 0);
tmp : IN STD_LOGIC_VECTOR (31 downto 0);
src : IN STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of set_assign_val is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (7 downto 0) := "00000100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (7 downto 0) := "00001000";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (7 downto 0) := "00010000";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (7 downto 0) := "00100000";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (7 downto 0) := "01000000";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (7 downto 0) := "10000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv4_F : STD_LOGIC_VECTOR (3 downto 0) := "1111";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
signal ap_CS_fsm : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_26 : BOOLEAN;
signal dest_addr_reg_86 : STD_LOGIC_VECTOR (31 downto 0);
signal sum_cast_fu_76_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_reg_ioackin_m_axi_dest_AWREADY : STD_LOGIC := '0';
signal ap_sig_ioackin_m_axi_dest_AWREADY : STD_LOGIC;
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_103 : BOOLEAN;
signal ap_reg_ioackin_m_axi_dest_WREADY : STD_LOGIC := '0';
signal ap_sig_ioackin_m_axi_dest_WREADY : STD_LOGIC;
signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_120 : BOOLEAN;
signal ap_sig_cseq_ST_st8_fsm_7 : STD_LOGIC;
signal ap_sig_bdd_136 : BOOLEAN;
signal tmp_cast_cast_fu_62_p1 : STD_LOGIC_VECTOR (32 downto 0);
signal sext_cast_fu_66_p1 : STD_LOGIC_VECTOR (32 downto 0);
signal sum_fu_70_p2 : STD_LOGIC_VECTOR (32 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (7 downto 0);
begin
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ioackin_m_axi_dest_AWREADY assign process. --
ap_reg_ioackin_m_axi_dest_AWREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ioackin_m_axi_dest_AWREADY <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
if (not((ap_const_logic_0 = ap_sig_ioackin_m_axi_dest_AWREADY))) then
ap_reg_ioackin_m_axi_dest_AWREADY <= ap_const_logic_0;
elsif ((ap_const_logic_1 = m_axi_dest_AWREADY)) then
ap_reg_ioackin_m_axi_dest_AWREADY <= ap_const_logic_1;
end if;
end if;
end if;
end if;
end process;
-- ap_reg_ioackin_m_axi_dest_WREADY assign process. --
ap_reg_ioackin_m_axi_dest_WREADY_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ioackin_m_axi_dest_WREADY <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
if (not((ap_const_logic_0 = ap_sig_ioackin_m_axi_dest_WREADY))) then
ap_reg_ioackin_m_axi_dest_WREADY <= ap_const_logic_0;
elsif ((ap_const_logic_1 = m_axi_dest_WREADY)) then
ap_reg_ioackin_m_axi_dest_WREADY <= ap_const_logic_1;
end if;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
dest_addr_reg_86 <= sum_cast_fu_76_p1(32 - 1 downto 0);
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, m_axi_dest_BVALID, ap_sig_ioackin_m_axi_dest_AWREADY, ap_sig_ioackin_m_axi_dest_WREADY)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_m_axi_dest_AWREADY))) then
ap_NS_fsm <= ap_ST_st3_fsm_2;
else
ap_NS_fsm <= ap_ST_st2_fsm_1;
end if;
when ap_ST_st3_fsm_2 =>
if (not((ap_const_logic_0 = ap_sig_ioackin_m_axi_dest_WREADY))) then
ap_NS_fsm <= ap_ST_st4_fsm_3;
else
ap_NS_fsm <= ap_ST_st3_fsm_2;
end if;
when ap_ST_st4_fsm_3 =>
ap_NS_fsm <= ap_ST_st5_fsm_4;
when ap_ST_st5_fsm_4 =>
ap_NS_fsm <= ap_ST_st6_fsm_5;
when ap_ST_st6_fsm_5 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st7_fsm_6 =>
ap_NS_fsm <= ap_ST_st8_fsm_7;
when ap_ST_st8_fsm_7 =>
if (not((m_axi_dest_BVALID = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
else
ap_NS_fsm <= ap_ST_st8_fsm_7;
end if;
when others =>
ap_NS_fsm <= "XXXXXXXX";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0, m_axi_dest_BVALID, ap_sig_cseq_ST_st8_fsm_7)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) and not((m_axi_dest_BVALID = ap_const_logic_0))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(m_axi_dest_BVALID, ap_sig_cseq_ST_st8_fsm_7)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) and not((m_axi_dest_BVALID = ap_const_logic_0)))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_sig_bdd_103 assign process. --
ap_sig_bdd_103_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_103 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_bdd_120 assign process. --
ap_sig_bdd_120_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_120 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_bdd_136 assign process. --
ap_sig_bdd_136_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_136 <= (ap_const_lv1_1 = ap_CS_fsm(7 downto 7));
end process;
-- ap_sig_bdd_26 assign process. --
ap_sig_bdd_26_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_26 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_26)
begin
if (ap_sig_bdd_26) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_103)
begin
if (ap_sig_bdd_103) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st3_fsm_2 assign process. --
ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_bdd_120)
begin
if (ap_sig_bdd_120) then
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st8_fsm_7 assign process. --
ap_sig_cseq_ST_st8_fsm_7_assign_proc : process(ap_sig_bdd_136)
begin
if (ap_sig_bdd_136) then
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_ioackin_m_axi_dest_AWREADY assign process. --
ap_sig_ioackin_m_axi_dest_AWREADY_assign_proc : process(m_axi_dest_AWREADY, ap_reg_ioackin_m_axi_dest_AWREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_m_axi_dest_AWREADY)) then
ap_sig_ioackin_m_axi_dest_AWREADY <= m_axi_dest_AWREADY;
else
ap_sig_ioackin_m_axi_dest_AWREADY <= ap_const_logic_1;
end if;
end process;
-- ap_sig_ioackin_m_axi_dest_WREADY assign process. --
ap_sig_ioackin_m_axi_dest_WREADY_assign_proc : process(m_axi_dest_WREADY, ap_reg_ioackin_m_axi_dest_WREADY)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_m_axi_dest_WREADY)) then
ap_sig_ioackin_m_axi_dest_WREADY <= m_axi_dest_WREADY;
else
ap_sig_ioackin_m_axi_dest_WREADY <= ap_const_logic_1;
end if;
end process;
m_axi_dest_ARADDR <= ap_const_lv32_0;
m_axi_dest_ARBURST <= ap_const_lv2_0;
m_axi_dest_ARCACHE <= ap_const_lv4_0;
m_axi_dest_ARID <= ap_const_lv1_0;
m_axi_dest_ARLEN <= ap_const_lv32_0;
m_axi_dest_ARLOCK <= ap_const_lv2_0;
m_axi_dest_ARPROT <= ap_const_lv3_0;
m_axi_dest_ARQOS <= ap_const_lv4_0;
m_axi_dest_ARREGION <= ap_const_lv4_0;
m_axi_dest_ARSIZE <= ap_const_lv3_0;
m_axi_dest_ARUSER <= ap_const_lv1_0;
m_axi_dest_ARVALID <= ap_const_logic_0;
m_axi_dest_AWADDR <= dest_addr_reg_86;
m_axi_dest_AWBURST <= ap_const_lv2_0;
m_axi_dest_AWCACHE <= ap_const_lv4_0;
m_axi_dest_AWID <= ap_const_lv1_0;
m_axi_dest_AWLEN <= ap_const_lv32_1;
m_axi_dest_AWLOCK <= ap_const_lv2_0;
m_axi_dest_AWPROT <= ap_const_lv3_0;
m_axi_dest_AWQOS <= ap_const_lv4_0;
m_axi_dest_AWREGION <= ap_const_lv4_0;
m_axi_dest_AWSIZE <= ap_const_lv3_0;
m_axi_dest_AWUSER <= ap_const_lv1_0;
-- m_axi_dest_AWVALID assign process. --
m_axi_dest_AWVALID_assign_proc : process(ap_reg_ioackin_m_axi_dest_AWREADY, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_logic_0 = ap_reg_ioackin_m_axi_dest_AWREADY))) then
m_axi_dest_AWVALID <= ap_const_logic_1;
else
m_axi_dest_AWVALID <= ap_const_logic_0;
end if;
end process;
-- m_axi_dest_BREADY assign process. --
m_axi_dest_BREADY_assign_proc : process(m_axi_dest_BVALID, ap_sig_cseq_ST_st8_fsm_7)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) and not((m_axi_dest_BVALID = ap_const_logic_0)))) then
m_axi_dest_BREADY <= ap_const_logic_1;
else
m_axi_dest_BREADY <= ap_const_logic_0;
end if;
end process;
m_axi_dest_RREADY <= ap_const_logic_0;
m_axi_dest_WDATA <= src;
m_axi_dest_WID <= ap_const_lv1_0;
m_axi_dest_WLAST <= ap_const_logic_0;
m_axi_dest_WSTRB <= ap_const_lv4_F;
m_axi_dest_WUSER <= ap_const_lv1_0;
-- m_axi_dest_WVALID assign process. --
m_axi_dest_WVALID_assign_proc : process(ap_reg_ioackin_m_axi_dest_WREADY, ap_sig_cseq_ST_st3_fsm_2)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) and (ap_const_logic_0 = ap_reg_ioackin_m_axi_dest_WREADY))) then
m_axi_dest_WVALID <= ap_const_logic_1;
else
m_axi_dest_WVALID <= ap_const_logic_0;
end if;
end process;
sext_cast_fu_66_p1 <= std_logic_vector(resize(unsigned(data1),33));
sum_cast_fu_76_p1 <= std_logic_vector(resize(unsigned(sum_fu_70_p2),64));
sum_fu_70_p2 <= std_logic_vector(unsigned(tmp_cast_cast_fu_62_p1) + unsigned(sext_cast_fu_66_p1));
tmp_cast_cast_fu_62_p1 <= std_logic_vector(resize(unsigned(tmp),33));
end behav;
|
mit
|
agural/FPGA-Oscilloscope
|
osc/sfl.vhd
|
1
|
3130
|
-- megafunction wizard: %Serial Flash Loader%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altserial_flash_loader
-- ============================================================
-- File Name: sfl.vhd
-- Megafunction Name(s):
-- altserial_flash_loader
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY sfl IS
PORT
(
noe_in : IN STD_LOGIC
);
END sfl;
ARCHITECTURE SYN OF sfl IS
COMPONENT altserial_flash_loader
GENERIC (
enable_quad_spi_support : NATURAL;
enable_shared_access : STRING;
enhanced_mode : NATURAL;
intended_device_family : STRING;
lpm_type : STRING
);
PORT (
noe : IN STD_LOGIC
);
END COMPONENT;
BEGIN
altserial_flash_loader_component : altserial_flash_loader
GENERIC MAP (
enable_quad_spi_support => 0,
enable_shared_access => "OFF",
enhanced_mode => 1,
intended_device_family => "Cyclone III",
lpm_type => "altserial_flash_loader"
)
PORT MAP (
noe => noe_in
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ENABLE_QUAD_SPI_SUPPORT NUMERIC "0"
-- Retrieval info: CONSTANT: ENABLE_SHARED_ACCESS STRING "OFF"
-- Retrieval info: CONSTANT: ENHANCED_MODE NUMERIC "1"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: USED_PORT: noe_in 0 0 0 0 INPUT NODEFVAL "noe_in"
-- Retrieval info: CONNECT: @noe 0 0 0 0 noe_in 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL sfl.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sfl.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sfl.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sfl.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sfl_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
mit
|
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axis_accelerator_adapter_v2_1/hdl/src/vhdl/axis_accelerator_adapter.vhd
|
1
|
102902
|
-------------------------------------------------------------------------------
-- axis_accelerator_adpater.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2013] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Title : AXI4-Stream Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : axis_accelerator_adapter.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2013-10-25
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: This is the Accelerator Adapter top-level module. It is
-- implemented as a wrapper that uses buses for all input/output arguments.
-- This top-level module supports up-to eight input/output arguments.
-- Then, it instantiates the "xd_adapter_core", which is a completely
-- parametrizable module.
-------------------------------------------------------------------------------
-- Structure:
--
-- axis_accelerator_adapter.vhd
-- xd_adapter_pkg.vhd
-- axis_accelerator_adapter_core.vhd
-- |-- axi_lite_adapter
-- |-- cdc_sync.vhd
-- |-- xd_input_args_module.vhd
-- |-- xd_s2m_adapter.vhd
-- |-- xd_s2m_converter.vhd
-- |-- xd_s2m_memory_dc.vhd
-- |-- xd_iarg_s2s_adapter.vhd
-- |-- s2s_async_fifo_wt.vhd
-- |-- xd_output_args_module.vhd
-- |-- cdc_sync.vhd
-- |-- xd_m2s_adapter.vhd
-- |-- xd_m2s_converter.vhd
-- |-- xd_m2s_memory_dc.vhd
-- |-- arg_mem_bank.vhd
-- |-- asymmetric_dp_bank_v6.vhd
-- |-- symmetric_dp_bank_v6.vhd
-- |-- dp_bank_sdp_v6.vhd
-- |-- oarg_columnized_mem_bank.vhd
-- |-- srl_fifo_32_wt.vhd
-- |-- xd_oarg_s2s_adapter.vhd
-- |-- s2s_async_fifo_wt.vhd
-- |-- xd_sync_module.vhd
-- |-- cdc_sync.vhd
-- |-- sync_ap_status.vhd
-- |-- async_fifo_dist_wt.vhd
-- |-- xd_input_scalars_module.vhd
-- |-- xd_input_scalars_fifo.vhd
-- |-- xd_output_scalars_module.vhd
-- |-- xd_output_scalars_fifo.vhd
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "aclk","clk_div#", "clk_#x"
-- reset signals: "rst", "aresetn","rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- History:
-- ~~~~~~
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-- 2013-01-31 1.0 pankajk removed perf mon ports, all ports in lower case
-- 2013-05-10 1.1 pankajk Seperated scalar port and brought those to top
-- entity
-- 2013-07-22 2.0 pankajk New scalar ports (*.vld, *.ack) and parameter
-- scalar_mode added to support accelerator IP
-- interface ap_none, ap_hs, ap_vld
-- 2013-10-25 2.0 pvk Added support for UltraScale primitives.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
use axis_accelerator_adapter_v2_1_6.axis_accelerator_adapter_core;
entity axis_accelerator_adapter is
generic (
-- System generics:
C_FAMILY : string := "virtex7"; -- Xilinx FPGA family
--
C_S_AXI_ADDR_WIDTH : integer := 13;
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
--
C_AP_ADAPTER_ID : integer range 0 to 15 :=1;
C_N_INPUT_ARGS : integer := 2;
C_N_OUTPUT_ARGS : integer := 1;
C_ENABLE_STREAM_CLK : integer := 0;
C_PRMRY_IS_ACLK_ASYNC : integer := 1;
C_S_AXIS_HAS_TSTRB : integer := 0;
C_S_AXIS_HAS_TKEEP : integer := 0;
--
C_S_AXIS_TDATA_WIDTH : integer := 64;
C_S_AXIS_TUSER_WIDTH : integer := 8;
C_S_AXIS_TID_WIDTH : integer := 4;
C_S_AXIS_TDEST_WIDTH : integer := 8;
--
C_AP_IARG_TYPE : std_logic_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
C_AP_IARG_MB_DEPTH : std_logic_vector := X"0000000400000004000000040000000400000004000000040000000400000004";
C_AP_IARG_WIDTH : std_logic_vector := X"0000002000000020000000200000002000000020000000200000002000000020";
C_AP_IARG_N_DIM : std_logic_vector := X"0000000100000001000000010000000100000001000000010000000100000001";
C_AP_IARG_DIM_1 : std_logic_vector := X"0000040000000400000004000000040000000400000004000000040000000400";
C_AP_IARG_DIM_2 : std_logic_vector := X"0000000100000001000000010000000100000001000000010000000100000001";
C_AP_IARG_FORMAT_TYPE : std_logic_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
C_AP_IARG_FORMAT_FACTOR : std_logic_vector := X"0000000100000001000000010000000100000001000000010000000100000001";
C_AP_IARG_FORMAT_DIM : std_logic_vector := X"0000000100000001000000010000000100000001000000010000000100000001";
--
C_AP_IARG_0_DWIDTH : integer := 32;
C_AP_IARG_1_DWIDTH : integer := 32;
C_AP_IARG_2_DWIDTH : integer := 32;
C_AP_IARG_3_DWIDTH : integer := 32;
C_AP_IARG_4_DWIDTH : integer := 32;
C_AP_IARG_5_DWIDTH : integer := 32;
C_AP_IARG_6_DWIDTH : integer := 32;
C_AP_IARG_7_DWIDTH : integer := 32;
--
C_M_AXIS_TDATA_WIDTH : integer := 64;
C_M_AXIS_TUSER_WIDTH : integer := 8;
C_M_AXIS_TID_WIDTH : integer := 4;
C_M_AXIS_TDEST_WIDTH : integer := 8;
--
C_AP_OARG_TYPE : std_logic_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
C_AP_OARG_MB_DEPTH : std_logic_vector := X"0000000400000004000000040000000400000004000000040000000400000004";
C_AP_OARG_WIDTH : std_logic_vector := X"0000002000000020000000200000002000000020000000200000002000000020";
C_AP_OARG_N_DIM : std_logic_vector := X"0000000100000001000000010000000100000001000000010000000100000001";
C_AP_OARG_DIM : std_logic_vector := X"0000000100000001000000010000040000000001000000010000000100000400000000010000000100000001000004000000000100000001000000010000040000000001000000010000000100000400000000010000000100000001000004000000000100000001000000010000080000000001000000010000000100000008";
C_AP_OARG_DIM_1 : std_logic_vector := X"0000040000000400000004000000040000000400000004000000080000000008";
C_AP_OARG_DIM_2 : std_logic_vector := X"0000000100000001000000010000000100000001000000010000000100000001";
C_AP_OARG_FORMAT_TYPE : std_logic_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
C_AP_OARG_FORMAT_FACTOR : std_logic_vector := X"0000000100000001000000010000000100000001000000010000000100000001";
C_AP_OARG_FORMAT_DIM : std_logic_vector := X"0000000100000001000000010000000100000001000000010000000100000001";
--
C_AP_OARG_0_DWIDTH : integer := 32;
C_AP_OARG_1_DWIDTH : integer := 32;
C_AP_OARG_2_DWIDTH : integer := 32;
C_AP_OARG_3_DWIDTH : integer := 32;
C_AP_OARG_4_DWIDTH : integer := 32;
C_AP_OARG_5_DWIDTH : integer := 32;
C_AP_OARG_6_DWIDTH : integer := 32;
C_AP_OARG_7_DWIDTH : integer := 32;
--
C_INPUT_SCALAR_0_WIDTH : integer := 0;
C_INPUT_SCALAR_1_WIDTH : integer := 0;
C_INPUT_SCALAR_2_WIDTH : integer := 0;
C_INPUT_SCALAR_3_WIDTH : integer := 0;
C_INPUT_SCALAR_4_WIDTH : integer := 0;
C_INPUT_SCALAR_5_WIDTH : integer := 0;
C_INPUT_SCALAR_6_WIDTH : integer := 0;
C_INPUT_SCALAR_7_WIDTH : integer := 0;
C_INPUT_SCALAR_8_WIDTH : integer := 0;
C_INPUT_SCALAR_9_WIDTH : integer := 0;
C_INPUT_SCALAR_10_WIDTH : integer := 0;
C_INPUT_SCALAR_11_WIDTH : integer := 0;
C_INPUT_SCALAR_12_WIDTH : integer := 0;
C_INPUT_SCALAR_13_WIDTH : integer := 0;
C_INPUT_SCALAR_14_WIDTH : integer := 0;
C_INPUT_SCALAR_15_WIDTH : integer := 0;
C_OUTPUT_SCALAR_0_WIDTH : integer := 0;
C_OUTPUT_SCALAR_1_WIDTH : integer := 0;
C_OUTPUT_SCALAR_2_WIDTH : integer := 0;
C_OUTPUT_SCALAR_3_WIDTH : integer := 0;
C_OUTPUT_SCALAR_4_WIDTH : integer := 0;
C_OUTPUT_SCALAR_5_WIDTH : integer := 0;
C_OUTPUT_SCALAR_6_WIDTH : integer := 0;
C_OUTPUT_SCALAR_7_WIDTH : integer := 0;
C_OUTPUT_SCALAR_8_WIDTH : integer := 0;
C_OUTPUT_SCALAR_9_WIDTH : integer := 0;
C_OUTPUT_SCALAR_10_WIDTH : integer := 0;
C_OUTPUT_SCALAR_11_WIDTH : integer := 0;
C_OUTPUT_SCALAR_12_WIDTH : integer := 0;
C_OUTPUT_SCALAR_13_WIDTH : integer := 0;
C_OUTPUT_SCALAR_14_WIDTH : integer := 0;
C_OUTPUT_SCALAR_15_WIDTH : integer := 0;
C_N_INOUT_SCALARS : integer := 0;
C_N_INPUT_SCALARS : integer := 0;
C_INPUT_SCALAR_DWIDTH : std_logic_vector := X"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020";
C_AP_ISCALAR_DOUT_WIDTH : integer := 32;
C_INPUT_SCALAR_MODE : std_logic_vector(63 downto 0) := X"0000000000000000";
--
C_N_OUTPUT_SCALARS : integer := 0;
C_OUTPUT_SCALAR_DWIDTH : std_logic_vector := X"00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000020";
C_AP_OSCALAR_DIN_WIDTH : integer := 32;
C_AP_ISCALAR_IO_DOUT_WIDTH : integer := 32;
C_AP_OSCALAR_IO_DIN_WIDTH : integer := 32;
C_OUTPUT_SCALAR_MODE : std_logic_vector(63 downto 0) := X"0000000000000000";
C_NONE : integer := 2);
port (
-------------------------------
-- AXI4-Lite Slave Interface --
-------------------------------
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
----------------------------------------------
-- AXI4-Stream slave interface clock reset
----------------------------------------------
s_axis_aclk : in std_logic;
s_axis_aresetn : in std_logic;
----------------------------------------------
-- AXI4-Stream master interface clock reset
----------------------------------------------
m_axis_aclk : in std_logic;
m_axis_aresetn : in std_logic;
----------------------------------------------
-- Accelerator clock --
----------------------------------------------
aclk : in std_logic;
-------------------------------
-- AXI4-Stream Slave Interface --
-------------------------------
s_axis_0_aclk : in std_logic;
s_axis_0_aresetn : in std_logic;
s_axis_0_tvalid : in std_logic;
s_axis_0_tready : out std_logic;
s_axis_0_tdata : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
s_axis_0_tstrb : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_0_tkeep : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_0_tlast : in std_logic;
s_axis_0_tid : in std_logic_vector(C_S_AXIS_TID_WIDTH-1 downto 0);
s_axis_0_tdest : in std_logic_vector(C_S_AXIS_TDEST_WIDTH-1 downto 0);
s_axis_0_tuser : in std_logic_vector(C_S_AXIS_TUSER_WIDTH-1 downto 0);
s_axis_1_aclk : in std_logic;
s_axis_1_aresetn : in std_logic;
s_axis_1_tvalid : in std_logic;
s_axis_1_tready : out std_logic;
s_axis_1_tdata : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
s_axis_1_tstrb : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_1_tkeep : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_1_tlast : in std_logic;
s_axis_1_tid : in std_logic_vector(C_S_AXIS_TID_WIDTH-1 downto 0);
s_axis_1_tdest : in std_logic_vector(C_S_AXIS_TDEST_WIDTH-1 downto 0);
s_axis_1_tuser : in std_logic_vector(C_S_AXIS_TUSER_WIDTH-1 downto 0);
s_axis_2_aclk : in std_logic;
s_axis_2_aresetn : in std_logic;
s_axis_2_tvalid : in std_logic;
s_axis_2_tready : out std_logic;
s_axis_2_tdata : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
s_axis_2_tstrb : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_2_tkeep : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_2_tlast : in std_logic;
s_axis_2_tid : in std_logic_vector(C_S_AXIS_TID_WIDTH-1 downto 0);
s_axis_2_tdest : in std_logic_vector(C_S_AXIS_TDEST_WIDTH-1 downto 0);
s_axis_2_tuser : in std_logic_vector(C_S_AXIS_TUSER_WIDTH-1 downto 0);
s_axis_3_aclk : in std_logic;
s_axis_3_aresetn : in std_logic;
s_axis_3_tvalid : in std_logic;
s_axis_3_tready : out std_logic;
s_axis_3_tdata : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
s_axis_3_tstrb : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_3_tkeep : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_3_tlast : in std_logic;
s_axis_3_tid : in std_logic_vector(C_S_AXIS_TID_WIDTH-1 downto 0);
s_axis_3_tdest : in std_logic_vector(C_S_AXIS_TDEST_WIDTH-1 downto 0);
s_axis_3_tuser : in std_logic_vector(C_S_AXIS_TUSER_WIDTH-1 downto 0);
s_axis_4_aclk : in std_logic;
s_axis_4_aresetn : in std_logic;
s_axis_4_tvalid : in std_logic;
s_axis_4_tready : out std_logic;
s_axis_4_tdata : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
s_axis_4_tstrb : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_4_tkeep : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_4_tlast : in std_logic;
s_axis_4_tid : in std_logic_vector(C_S_AXIS_TID_WIDTH-1 downto 0);
s_axis_4_tdest : in std_logic_vector(C_S_AXIS_TDEST_WIDTH-1 downto 0);
s_axis_4_tuser : in std_logic_vector(C_S_AXIS_TUSER_WIDTH-1 downto 0);
s_axis_5_aclk : in std_logic;
s_axis_5_aresetn : in std_logic;
s_axis_5_tvalid : in std_logic;
s_axis_5_tready : out std_logic;
s_axis_5_tdata : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
s_axis_5_tstrb : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_5_tkeep : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_5_tlast : in std_logic;
s_axis_5_tid : in std_logic_vector(C_S_AXIS_TID_WIDTH-1 downto 0);
s_axis_5_tdest : in std_logic_vector(C_S_AXIS_TDEST_WIDTH-1 downto 0);
s_axis_5_tuser : in std_logic_vector(C_S_AXIS_TUSER_WIDTH-1 downto 0);
s_axis_6_aclk : in std_logic;
s_axis_6_aresetn : in std_logic;
s_axis_6_tvalid : in std_logic;
s_axis_6_tready : out std_logic;
s_axis_6_tdata : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
s_axis_6_tstrb : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_6_tkeep : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_6_tlast : in std_logic;
s_axis_6_tid : in std_logic_vector(C_S_AXIS_TID_WIDTH-1 downto 0);
s_axis_6_tdest : in std_logic_vector(C_S_AXIS_TDEST_WIDTH-1 downto 0);
s_axis_6_tuser : in std_logic_vector(C_S_AXIS_TUSER_WIDTH-1 downto 0);
s_axis_7_aclk : in std_logic;
s_axis_7_aresetn : in std_logic;
s_axis_7_tvalid : in std_logic;
s_axis_7_tready : out std_logic;
s_axis_7_tdata : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
s_axis_7_tstrb : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_7_tkeep : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0):= (others => '1');
s_axis_7_tlast : in std_logic;
s_axis_7_tid : in std_logic_vector(C_S_AXIS_TID_WIDTH-1 downto 0);
s_axis_7_tdest : in std_logic_vector(C_S_AXIS_TDEST_WIDTH-1 downto 0);
s_axis_7_tuser : in std_logic_vector(C_S_AXIS_TUSER_WIDTH-1 downto 0);
------------------------------------------
-- Accelerator Port input arguments (BRAM)
------------------------------------------
ap_iarg_0_clk : in std_logic;
ap_iarg_0_rst : in std_logic;
ap_iarg_0_addr : in std_logic_vector(31 downto 0);
ap_iarg_0_ce : in std_logic;
ap_iarg_0_we : in std_logic_vector(C_AP_IARG_0_DWIDTH/8-1 downto 0);
ap_iarg_0_din : in std_logic_vector(C_AP_IARG_0_DWIDTH-1 downto 0);
ap_iarg_0_dout : out std_logic_vector(C_AP_IARG_0_DWIDTH-1 downto 0);
---
ap_iarg_1_clk : in std_logic;
ap_iarg_1_rst : in std_logic;
ap_iarg_1_addr : in std_logic_vector(31 downto 0);
ap_iarg_1_ce : in std_logic;
ap_iarg_1_we : in std_logic_vector(C_AP_IARG_1_DWIDTH/8-1 downto 0);
ap_iarg_1_din : in std_logic_vector(C_AP_IARG_1_DWIDTH-1 downto 0);
ap_iarg_1_dout : out std_logic_vector(C_AP_IARG_1_DWIDTH-1 downto 0);
---
ap_iarg_2_clk : in std_logic;
ap_iarg_2_rst : in std_logic;
ap_iarg_2_addr : in std_logic_vector(31 downto 0);
ap_iarg_2_ce : in std_logic;
ap_iarg_2_we : in std_logic_vector(C_AP_IARG_2_DWIDTH/8-1 downto 0);
ap_iarg_2_din : in std_logic_vector(C_AP_IARG_2_DWIDTH-1 downto 0);
ap_iarg_2_dout : out std_logic_vector(C_AP_IARG_2_DWIDTH-1 downto 0);
---
ap_iarg_3_clk : in std_logic;
ap_iarg_3_rst : in std_logic;
ap_iarg_3_addr : in std_logic_vector(31 downto 0);
ap_iarg_3_ce : in std_logic;
ap_iarg_3_we : in std_logic_vector(C_AP_IARG_3_DWIDTH/8-1 downto 0);
ap_iarg_3_din : in std_logic_vector(C_AP_IARG_3_DWIDTH-1 downto 0);
ap_iarg_3_dout : out std_logic_vector(C_AP_IARG_3_DWIDTH-1 downto 0);
---
ap_iarg_4_clk : in std_logic;
ap_iarg_4_rst : in std_logic;
ap_iarg_4_addr : in std_logic_vector(31 downto 0);
ap_iarg_4_ce : in std_logic;
ap_iarg_4_we : in std_logic_vector(C_AP_IARG_4_DWIDTH/8-1 downto 0);
ap_iarg_4_din : in std_logic_vector(C_AP_IARG_4_DWIDTH-1 downto 0);
ap_iarg_4_dout : out std_logic_vector(C_AP_IARG_4_DWIDTH-1 downto 0);
---
ap_iarg_5_clk : in std_logic;
ap_iarg_5_rst : in std_logic;
ap_iarg_5_addr : in std_logic_vector(31 downto 0);
ap_iarg_5_ce : in std_logic;
ap_iarg_5_we : in std_logic_vector(C_AP_IARG_5_DWIDTH/8-1 downto 0);
ap_iarg_5_din : in std_logic_vector(C_AP_IARG_5_DWIDTH-1 downto 0);
ap_iarg_5_dout : out std_logic_vector(C_AP_IARG_5_DWIDTH-1 downto 0);
---
ap_iarg_6_clk : in std_logic;
ap_iarg_6_rst : in std_logic;
ap_iarg_6_addr : in std_logic_vector(31 downto 0);
ap_iarg_6_ce : in std_logic;
ap_iarg_6_we : in std_logic_vector(C_AP_IARG_6_DWIDTH/8-1 downto 0);
ap_iarg_6_din : in std_logic_vector(C_AP_IARG_6_DWIDTH-1 downto 0);
ap_iarg_6_dout : out std_logic_vector(C_AP_IARG_6_DWIDTH-1 downto 0);
---
ap_iarg_7_clk : in std_logic;
ap_iarg_7_rst : in std_logic;
ap_iarg_7_addr : in std_logic_vector(31 downto 0);
ap_iarg_7_ce : in std_logic;
ap_iarg_7_we : in std_logic_vector(C_AP_IARG_7_DWIDTH/8-1 downto 0);
ap_iarg_7_din : in std_logic_vector(C_AP_IARG_7_DWIDTH-1 downto 0);
ap_iarg_7_dout : out std_logic_vector(C_AP_IARG_7_DWIDTH-1 downto 0);
---------------------------------------------
-- Accelerator Port input arguments (FIFO) --
---------------------------------------------
ap_fifo_iarg_0_dout : out std_logic_vector(C_AP_IARG_0_DWIDTH-1 downto 0);
ap_fifo_iarg_0_read : in std_logic;
ap_fifo_iarg_0_empty_n : out std_logic;
ap_fifo_iarg_1_dout : out std_logic_vector(C_AP_IARG_1_DWIDTH-1 downto 0);
ap_fifo_iarg_1_read : in std_logic;
ap_fifo_iarg_1_empty_n : out std_logic;
ap_fifo_iarg_2_dout : out std_logic_vector(C_AP_IARG_2_DWIDTH-1 downto 0);
ap_fifo_iarg_2_read : in std_logic;
ap_fifo_iarg_2_empty_n : out std_logic;
ap_fifo_iarg_3_dout : out std_logic_vector(C_AP_IARG_3_DWIDTH-1 downto 0);
ap_fifo_iarg_3_read : in std_logic;
ap_fifo_iarg_3_empty_n : out std_logic;
ap_fifo_iarg_4_dout : out std_logic_vector(C_AP_IARG_4_DWIDTH-1 downto 0);
ap_fifo_iarg_4_read : in std_logic;
ap_fifo_iarg_4_empty_n : out std_logic;
ap_fifo_iarg_5_dout : out std_logic_vector(C_AP_IARG_5_DWIDTH-1 downto 0);
ap_fifo_iarg_5_read : in std_logic;
ap_fifo_iarg_5_empty_n : out std_logic;
ap_fifo_iarg_6_dout : out std_logic_vector(C_AP_IARG_6_DWIDTH-1 downto 0);
ap_fifo_iarg_6_read : in std_logic;
ap_fifo_iarg_6_empty_n : out std_logic;
ap_fifo_iarg_7_dout : out std_logic_vector(C_AP_IARG_7_DWIDTH-1 downto 0);
ap_fifo_iarg_7_read : in std_logic;
ap_fifo_iarg_7_empty_n : out std_logic;
-------------------------------
--* AXI4-Stream Slave Interface* --
-- Output Arguments
-------------------------------
m_axis_0_aclk : in std_logic;
m_axis_0_aresetn : in std_logic;
m_axis_0_tvalid : out std_logic;
m_axis_0_tready : in std_logic;
m_axis_0_tdata : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
m_axis_0_tstrb : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_0_tkeep : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_0_tlast : out std_logic;
m_axis_0_tid : out std_logic_vector(C_M_AXIS_TID_WIDTH-1 downto 0);
m_axis_0_tdest : out std_logic_vector(C_M_AXIS_TDEST_WIDTH-1 downto 0);
m_axis_0_tuser : out std_logic_vector(C_M_AXIS_TUSER_WIDTH-1 downto 0);
m_axis_1_aclk : in std_logic;
m_axis_1_aresetn : in std_logic;
m_axis_1_tvalid : out std_logic;
m_axis_1_tready : in std_logic;
m_axis_1_tdata : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
m_axis_1_tstrb : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_1_tkeep : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_1_tlast : out std_logic;
m_axis_1_tid : out std_logic_vector(C_M_AXIS_TID_WIDTH-1 downto 0);
m_axis_1_tdest : out std_logic_vector(C_M_AXIS_TDEST_WIDTH-1 downto 0);
m_axis_1_tuser : out std_logic_vector(C_M_AXIS_TUSER_WIDTH-1 downto 0);
m_axis_2_aclk : in std_logic;
m_axis_2_aresetn : in std_logic;
m_axis_2_tvalid : out std_logic;
m_axis_2_tready : in std_logic;
m_axis_2_tdata : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
m_axis_2_tstrb : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_2_tkeep : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_2_tlast : out std_logic;
m_axis_2_tid : out std_logic_vector(C_M_AXIS_TID_WIDTH-1 downto 0);
m_axis_2_tdest : out std_logic_vector(C_M_AXIS_TDEST_WIDTH-1 downto 0);
m_axis_2_tuser : out std_logic_vector(C_M_AXIS_TUSER_WIDTH-1 downto 0);
m_axis_3_aclk : in std_logic;
m_axis_3_aresetn : in std_logic;
m_axis_3_tvalid : out std_logic;
m_axis_3_tready : in std_logic;
m_axis_3_tdata : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
m_axis_3_tstrb : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_3_tkeep : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_3_tlast : out std_logic;
m_axis_3_tid : out std_logic_vector(C_M_AXIS_TID_WIDTH-1 downto 0);
m_axis_3_tdest : out std_logic_vector(C_M_AXIS_TDEST_WIDTH-1 downto 0);
m_axis_3_tuser : out std_logic_vector(C_M_AXIS_TUSER_WIDTH-1 downto 0);
m_axis_4_aclk : in std_logic;
m_axis_4_aresetn : in std_logic;
m_axis_4_tvalid : out std_logic;
m_axis_4_tready : in std_logic;
m_axis_4_tdata : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
m_axis_4_tstrb : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_4_tkeep : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_4_tlast : out std_logic;
m_axis_4_tid : out std_logic_vector(C_M_AXIS_TID_WIDTH-1 downto 0);
m_axis_4_tdest : out std_logic_vector(C_M_AXIS_TDEST_WIDTH-1 downto 0);
m_axis_4_tuser : out std_logic_vector(C_M_AXIS_TUSER_WIDTH-1 downto 0);
m_axis_5_aclk : in std_logic;
m_axis_5_aresetn : in std_logic;
m_axis_5_tvalid : out std_logic;
m_axis_5_tready : in std_logic;
m_axis_5_tdata : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
m_axis_5_tstrb : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_5_tkeep : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_5_tlast : out std_logic;
m_axis_5_tid : out std_logic_vector(C_M_AXIS_TID_WIDTH-1 downto 0);
m_axis_5_tdest : out std_logic_vector(C_M_AXIS_TDEST_WIDTH-1 downto 0);
m_axis_5_tuser : out std_logic_vector(C_M_AXIS_TUSER_WIDTH-1 downto 0);
m_axis_6_aclk : in std_logic;
m_axis_6_aresetn : in std_logic;
m_axis_6_tvalid : out std_logic;
m_axis_6_tready : in std_logic;
m_axis_6_tdata : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
m_axis_6_tstrb : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_6_tkeep : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_6_tlast : out std_logic;
m_axis_6_tid : out std_logic_vector(C_M_AXIS_TID_WIDTH-1 downto 0);
m_axis_6_tdest : out std_logic_vector(C_M_AXIS_TDEST_WIDTH-1 downto 0);
m_axis_6_tuser : out std_logic_vector(C_M_AXIS_TUSER_WIDTH-1 downto 0);
m_axis_7_aclk : in std_logic;
m_axis_7_aresetn : in std_logic;
m_axis_7_tvalid : out std_logic;
m_axis_7_tready : in std_logic;
m_axis_7_tdata : out std_logic_vector(C_M_AXIS_TDATA_WIDTH-1 downto 0);
m_axis_7_tstrb : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_7_tkeep : out std_logic_vector(C_M_AXIS_TDATA_WIDTH/8-1 downto 0);
m_axis_7_tlast : out std_logic;
m_axis_7_tid : out std_logic_vector(C_M_AXIS_TID_WIDTH-1 downto 0);
m_axis_7_tdest : out std_logic_vector(C_M_AXIS_TDEST_WIDTH-1 downto 0);
m_axis_7_tuser : out std_logic_vector(C_M_AXIS_TUSER_WIDTH-1 downto 0);
----------------------------------------------
-- Accelerator Port output arguments (BRAM) --
----------------------------------------------
--- AP output arguments
ap_oarg_0_clk : in std_logic;
ap_oarg_0_rst : in std_logic;
ap_oarg_0_addr : in std_logic_vector(31 downto 0);
ap_oarg_0_ce : in std_logic;
ap_oarg_0_we : in std_logic_vector(C_AP_OARG_0_DWIDTH/8-1 downto 0);
ap_oarg_0_din : in std_logic_vector(C_AP_OARG_0_DWIDTH-1 downto 0);
ap_oarg_0_dout : out std_logic_vector(C_AP_OARG_0_DWIDTH-1 downto 0);
---
ap_oarg_1_clk : in std_logic;
ap_oarg_1_rst : in std_logic;
ap_oarg_1_addr : in std_logic_vector(31 downto 0);
ap_oarg_1_ce : in std_logic;
ap_oarg_1_we : in std_logic_vector(C_AP_OARG_1_DWIDTH/8-1 downto 0);
ap_oarg_1_din : in std_logic_vector(C_AP_OARG_1_DWIDTH-1 downto 0);
ap_oarg_1_dout : out std_logic_vector(C_AP_OARG_1_DWIDTH-1 downto 0);
---
ap_oarg_2_clk : in std_logic;
ap_oarg_2_rst : in std_logic;
ap_oarg_2_addr : in std_logic_vector(31 downto 0);
ap_oarg_2_ce : in std_logic;
ap_oarg_2_we : in std_logic_vector(C_AP_OARG_2_DWIDTH/8-1 downto 0);
ap_oarg_2_din : in std_logic_vector(C_AP_OARG_2_DWIDTH-1 downto 0);
ap_oarg_2_dout : out std_logic_vector(C_AP_OARG_2_DWIDTH-1 downto 0);
---
ap_oarg_3_clk : in std_logic;
ap_oarg_3_rst : in std_logic;
ap_oarg_3_addr : in std_logic_vector(31 downto 0);
ap_oarg_3_ce : in std_logic;
ap_oarg_3_we : in std_logic_vector(C_AP_OARG_3_DWIDTH/8-1 downto 0);
ap_oarg_3_din : in std_logic_vector(C_AP_OARG_3_DWIDTH-1 downto 0);
ap_oarg_3_dout : out std_logic_vector(C_AP_OARG_3_DWIDTH-1 downto 0);
---
ap_oarg_4_clk : in std_logic;
ap_oarg_4_rst : in std_logic;
ap_oarg_4_addr : in std_logic_vector(31 downto 0);
ap_oarg_4_ce : in std_logic;
ap_oarg_4_we : in std_logic_vector(C_AP_OARG_4_DWIDTH/8-1 downto 0);
ap_oarg_4_din : in std_logic_vector(C_AP_OARG_4_DWIDTH-1 downto 0);
ap_oarg_4_dout : out std_logic_vector(C_AP_OARG_4_DWIDTH-1 downto 0);
---
ap_oarg_5_clk : in std_logic;
ap_oarg_5_rst : in std_logic;
ap_oarg_5_addr : in std_logic_vector(31 downto 0);
ap_oarg_5_ce : in std_logic;
ap_oarg_5_we : in std_logic_vector(C_AP_OARG_5_DWIDTH/8-1 downto 0);
ap_oarg_5_din : in std_logic_vector(C_AP_OARG_5_DWIDTH-1 downto 0);
ap_oarg_5_dout : out std_logic_vector(C_AP_OARG_5_DWIDTH-1 downto 0);
---
ap_oarg_6_clk : in std_logic;
ap_oarg_6_rst : in std_logic;
ap_oarg_6_addr : in std_logic_vector(31 downto 0);
ap_oarg_6_ce : in std_logic;
ap_oarg_6_we : in std_logic_vector(C_AP_OARG_6_DWIDTH/8-1 downto 0);
ap_oarg_6_din : in std_logic_vector(C_AP_OARG_6_DWIDTH-1 downto 0);
ap_oarg_6_dout : out std_logic_vector(C_AP_OARG_6_DWIDTH-1 downto 0);
---
ap_oarg_7_clk : in std_logic;
ap_oarg_7_rst : in std_logic;
ap_oarg_7_addr : in std_logic_vector(31 downto 0);
ap_oarg_7_ce : in std_logic;
ap_oarg_7_we : in std_logic_vector(C_AP_OARG_7_DWIDTH/8-1 downto 0);
ap_oarg_7_din : in std_logic_vector(C_AP_OARG_7_DWIDTH-1 downto 0);
ap_oarg_7_dout : out std_logic_vector(C_AP_OARG_7_DWIDTH-1 downto 0);
----------------------------------------------
-- Accelerator Port output arguments (FIFO) --
----------------------------------------------
ap_fifo_oarg_0_din : in std_logic_vector(C_AP_OARG_0_DWIDTH-1 downto 0);
ap_fifo_oarg_0_write : in std_logic;
ap_fifo_oarg_0_full_n : out std_logic;
ap_fifo_oarg_1_din : in std_logic_vector(C_AP_OARG_1_DWIDTH-1 downto 0);
ap_fifo_oarg_1_write : in std_logic;
ap_fifo_oarg_1_full_n : out std_logic;
ap_fifo_oarg_2_din : in std_logic_vector(C_AP_OARG_2_DWIDTH-1 downto 0);
ap_fifo_oarg_2_write : in std_logic;
ap_fifo_oarg_2_full_n : out std_logic;
ap_fifo_oarg_3_din : in std_logic_vector(C_AP_OARG_3_DWIDTH-1 downto 0);
ap_fifo_oarg_3_write : in std_logic;
ap_fifo_oarg_3_full_n : out std_logic;
ap_fifo_oarg_4_din : in std_logic_vector(C_AP_OARG_4_DWIDTH-1 downto 0);
ap_fifo_oarg_4_write : in std_logic;
ap_fifo_oarg_4_full_n : out std_logic;
ap_fifo_oarg_5_din : in std_logic_vector(C_AP_OARG_5_DWIDTH-1 downto 0);
ap_fifo_oarg_5_write : in std_logic;
ap_fifo_oarg_5_full_n : out std_logic;
ap_fifo_oarg_6_din : in std_logic_vector(C_AP_OARG_6_DWIDTH-1 downto 0);
ap_fifo_oarg_6_write : in std_logic;
ap_fifo_oarg_6_full_n : out std_logic;
ap_fifo_oarg_7_din : in std_logic_vector(C_AP_OARG_7_DWIDTH-1 downto 0);
ap_fifo_oarg_7_write : in std_logic;
ap_fifo_oarg_7_full_n : out std_logic;
----------------------------------------------
-- Accelerator Control Interface --
----------------------------------------------
ap_start : out std_logic;
ap_ready : in std_logic;
ap_done : in std_logic;
ap_continue : out std_logic;
ap_idle : in std_logic;
aresetn : out std_logic;
----------------------------------------------
-- Accelerator Input Scalar Interface --
----------------------------------------------
ap_iscalar_0_dout : out std_logic_vector(C_INPUT_SCALAR_0_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_1_dout : out std_logic_vector(C_INPUT_SCALAR_1_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_2_dout : out std_logic_vector(C_INPUT_SCALAR_2_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_3_dout : out std_logic_vector(C_INPUT_SCALAR_3_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_4_dout : out std_logic_vector(C_INPUT_SCALAR_4_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_5_dout : out std_logic_vector(C_INPUT_SCALAR_5_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_6_dout : out std_logic_vector(C_INPUT_SCALAR_6_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_7_dout : out std_logic_vector(C_INPUT_SCALAR_7_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_8_dout : out std_logic_vector(C_INPUT_SCALAR_8_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_9_dout : out std_logic_vector(C_INPUT_SCALAR_9_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_10_dout : out std_logic_vector(C_INPUT_SCALAR_10_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_11_dout : out std_logic_vector(C_INPUT_SCALAR_11_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_12_dout : out std_logic_vector(C_INPUT_SCALAR_12_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_13_dout : out std_logic_vector(C_INPUT_SCALAR_13_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_14_dout : out std_logic_vector(C_INPUT_SCALAR_14_WIDTH-1 downto 0) := (others=>'0');
ap_iscalar_15_dout : out std_logic_vector(C_INPUT_SCALAR_15_WIDTH-1 downto 0) := (others=>'0');
-- Inpput scalar Valid signals (valid for AP_HS & AP_VLD modes)
ap_iscalar_0_vld : out std_logic;
ap_iscalar_1_vld : out std_logic;
ap_iscalar_2_vld : out std_logic;
ap_iscalar_3_vld : out std_logic;
ap_iscalar_4_vld : out std_logic;
ap_iscalar_5_vld : out std_logic;
ap_iscalar_6_vld : out std_logic;
ap_iscalar_7_vld : out std_logic;
ap_iscalar_8_vld : out std_logic;
ap_iscalar_9_vld : out std_logic;
ap_iscalar_10_vld : out std_logic;
ap_iscalar_11_vld : out std_logic;
ap_iscalar_12_vld : out std_logic;
ap_iscalar_13_vld : out std_logic;
ap_iscalar_14_vld : out std_logic;
ap_iscalar_15_vld : out std_logic;
-- Input Scalar ack - (valid for AP_HS mode)
ap_iscalar_0_ack : in std_logic;
ap_iscalar_1_ack : in std_logic;
ap_iscalar_2_ack : in std_logic;
ap_iscalar_3_ack : in std_logic;
ap_iscalar_4_ack : in std_logic;
ap_iscalar_5_ack : in std_logic;
ap_iscalar_6_ack : in std_logic;
ap_iscalar_7_ack : in std_logic;
ap_iscalar_8_ack : in std_logic;
ap_iscalar_9_ack : in std_logic;
ap_iscalar_10_ack : in std_logic;
ap_iscalar_11_ack : in std_logic;
ap_iscalar_12_ack : in std_logic;
ap_iscalar_13_ack : in std_logic;
ap_iscalar_14_ack : in std_logic;
ap_iscalar_15_ack : in std_logic;
----------------------------------------------
-- Accelerator Output Scalar Interface --
----------------------------------------------
ap_oscalar_0_din : in std_logic_vector(C_OUTPUT_SCALAR_0_WIDTH-1 downto 0);
ap_oscalar_1_din : in std_logic_vector(C_OUTPUT_SCALAR_1_WIDTH-1 downto 0);
ap_oscalar_2_din : in std_logic_vector(C_OUTPUT_SCALAR_2_WIDTH-1 downto 0);
ap_oscalar_3_din : in std_logic_vector(C_OUTPUT_SCALAR_3_WIDTH-1 downto 0);
ap_oscalar_4_din : in std_logic_vector(C_OUTPUT_SCALAR_4_WIDTH-1 downto 0);
ap_oscalar_5_din : in std_logic_vector(C_OUTPUT_SCALAR_5_WIDTH-1 downto 0);
ap_oscalar_6_din : in std_logic_vector(C_OUTPUT_SCALAR_6_WIDTH-1 downto 0);
ap_oscalar_7_din : in std_logic_vector(C_OUTPUT_SCALAR_7_WIDTH-1 downto 0);
ap_oscalar_8_din : in std_logic_vector(C_OUTPUT_SCALAR_8_WIDTH-1 downto 0);
ap_oscalar_9_din : in std_logic_vector(C_OUTPUT_SCALAR_9_WIDTH-1 downto 0);
ap_oscalar_10_din : in std_logic_vector(C_OUTPUT_SCALAR_10_WIDTH-1 downto 0);
ap_oscalar_11_din : in std_logic_vector(C_OUTPUT_SCALAR_11_WIDTH-1 downto 0);
ap_oscalar_12_din : in std_logic_vector(C_OUTPUT_SCALAR_12_WIDTH-1 downto 0);
ap_oscalar_13_din : in std_logic_vector(C_OUTPUT_SCALAR_13_WIDTH-1 downto 0);
ap_oscalar_14_din : in std_logic_vector(C_OUTPUT_SCALAR_14_WIDTH-1 downto 0);
ap_oscalar_15_din : in std_logic_vector(C_OUTPUT_SCALAR_15_WIDTH-1 downto 0);
-- Output scalar Valid signals (valid for AP_HS & AP_VLD modes)
ap_oscalar_0_vld : in std_logic;
ap_oscalar_1_vld : in std_logic;
ap_oscalar_2_vld : in std_logic;
ap_oscalar_3_vld : in std_logic;
ap_oscalar_4_vld : in std_logic;
ap_oscalar_5_vld : in std_logic;
ap_oscalar_6_vld : in std_logic;
ap_oscalar_7_vld : in std_logic;
ap_oscalar_8_vld : in std_logic;
ap_oscalar_9_vld : in std_logic;
ap_oscalar_10_vld : in std_logic;
ap_oscalar_11_vld : in std_logic;
ap_oscalar_12_vld : in std_logic;
ap_oscalar_13_vld : in std_logic;
ap_oscalar_14_vld : in std_logic;
ap_oscalar_15_vld : in std_logic;
-- Output Scalar ack - (valid for AP_HS mode)
ap_oscalar_0_ack : out std_logic;
ap_oscalar_1_ack : out std_logic;
ap_oscalar_2_ack : out std_logic;
ap_oscalar_3_ack : out std_logic;
ap_oscalar_4_ack : out std_logic;
ap_oscalar_5_ack : out std_logic;
ap_oscalar_6_ack : out std_logic;
ap_oscalar_7_ack : out std_logic;
ap_oscalar_8_ack : out std_logic;
ap_oscalar_9_ack : out std_logic;
ap_oscalar_10_ack : out std_logic;
ap_oscalar_11_ack : out std_logic;
ap_oscalar_12_ack : out std_logic;
ap_oscalar_13_ack : out std_logic;
ap_oscalar_14_ack : out std_logic;
ap_oscalar_15_ack : out std_logic;
---
interrupt : out std_logic);
end entity;
architecture rtl of axis_accelerator_adapter is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of rtl : architecture is "yes";
-- Constant declaration
constant C_S_AXIS_TSTRB_WIDTH : integer := C_S_AXIS_TDATA_WIDTH/8;
constant C_S_AXIS_TKEEP_WIDTH : integer := C_S_AXIS_TDATA_WIDTH/8;
constant C_M_AXIS_TSTRB_WIDTH : integer := C_M_AXIS_TDATA_WIDTH/8;
constant C_M_AXIS_TKEEP_WIDTH : integer := C_M_AXIS_TDATA_WIDTH/8;
constant C_MAX_SCALAR_DWIDTH : integer := 32;
constant C_MAX_ARG_DWIDTH : integer := 1024;
constant C_MAX_ARG_SWIDTH : integer := 16; -- Strobe width
constant C_MAX_ARG_AWIDTH : integer := 16;
constant C_MAX_ARG_N_DIM : integer := 4;
constant C_MAX_MB_DEPTH : integer := 8;
constant C_MAX_N_IARGS : integer := 8;
constant C_MAX_N_OARGS : integer := 8;
constant C_MAX_N_ISCALARS : integer := 8;
constant C_MAX_N_OSCALARS : integer := 8;
constant C_MAX_N_IOSCALARS : integer := 8;
constant C_MTBF_STAGES : integer := 4;
-------------------------
-- Scaler Data Width
-------------------------
-- GENERIC GROUPING: INPUT ARGUMENTS:
function calc_iarg_dwidth return std_logic_vector is
variable value : std_logic_vector(C_MAX_N_IARGS*32-1 downto 0) := (others => '0');
begin
value(32*(0+1)-1 downto 32*0) := int2lv(C_AP_IARG_0_DWIDTH);
value(32*(1+1)-1 downto 32*1) := int2lv(C_AP_IARG_1_DWIDTH);
value(32*(2+1)-1 downto 32*2) := int2lv(C_AP_IARG_2_DWIDTH);
value(32*(3+1)-1 downto 32*3) := int2lv(C_AP_IARG_3_DWIDTH);
value(32*(4+1)-1 downto 32*4) := int2lv(C_AP_IARG_4_DWIDTH);
value(32*(5+1)-1 downto 32*5) := int2lv(C_AP_IARG_5_DWIDTH);
value(32*(6+1)-1 downto 32*6) := int2lv(C_AP_IARG_6_DWIDTH);
value(32*(7+1)-1 downto 32*7) := int2lv(C_AP_IARG_7_DWIDTH);
return value;
end function calc_iarg_dwidth;
---------------------------------------------------------
-- GENERIC GROUPING: OUTPUT ARGUMENTS
function calc_oarg_dwidth return std_logic_vector is
variable value : std_logic_vector(C_MAX_N_OARGS*32-1 downto 0) := (others => '0');
begin
value(32*(0+1)-1 downto 32*0) := int2lv(C_AP_OARG_0_DWIDTH);
value(32*(1+1)-1 downto 32*1) := int2lv(C_AP_OARG_1_DWIDTH);
value(32*(2+1)-1 downto 32*2) := int2lv(C_AP_OARG_2_DWIDTH);
value(32*(3+1)-1 downto 32*3) := int2lv(C_AP_OARG_3_DWIDTH);
value(32*(4+1)-1 downto 32*4) := int2lv(C_AP_OARG_4_DWIDTH);
value(32*(5+1)-1 downto 32*5) := int2lv(C_AP_OARG_5_DWIDTH);
value(32*(6+1)-1 downto 32*6) := int2lv(C_AP_OARG_6_DWIDTH);
value(32*(7+1)-1 downto 32*7) := int2lv(C_AP_OARG_7_DWIDTH);
return value;
end function calc_oarg_dwidth;
-------------------------
-- BRAM PRIMITIVE TYPE
-- 7_SERIES : RAMB36E1, ULRASCALE : RAMB36E2
-------------------------
function calc_bram_type return string is
begin
if (C_FAMILY = "virtexu" or C_FAMILY = "kintexu" or C_FAMILY = "artixu" or C_FAMILY = "virtexuplus" or C_FAMILY = "kintexuplus" or C_FAMILY = "zynquplus") then
return "ULTRASCALE";
else
return "7_SERIES";
end if ;
end function calc_bram_type;
constant BRAM_PRIMITIVE_TYPE : string := calc_bram_type;
constant C_AP_OARG_DWIDTH : std_logic_vector(C_MAX_N_OARGS*32-1 downto 0) := calc_oarg_dwidth;
constant C_AP_IARG_DWIDTH : std_logic_vector(C_MAX_N_IARGS*32-1 downto 0) := calc_iarg_dwidth;
-- SUPERBUSSES DECLARATION:
signal s_axis_aclk_i : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal s_axis_aresetn_i : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal s_axis_tvalid : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal s_axis_tready : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal s_axis_tdata : std_logic_vector(C_MAX_N_IARGS*C_S_AXIS_TDATA_WIDTH-1 downto 0);
signal s_axis_tstrb : std_logic_vector(C_MAX_N_IARGS*C_S_AXIS_TSTRB_WIDTH-1 downto 0);
signal s_axis_tkeep : std_logic_vector(C_MAX_N_IARGS*C_S_AXIS_TKEEP_WIDTH-1 downto 0);
signal s_axis_tlast : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal s_axis_tid : std_logic_vector(C_MAX_N_IARGS*C_S_AXIS_TID_WIDTH-1 downto 0);
signal s_axis_tdest : std_logic_vector(C_MAX_N_IARGS*C_S_AXIS_TDEST_WIDTH-1 downto 0);
signal s_axis_tuser : std_logic_vector(C_MAX_N_IARGS*C_S_AXIS_TUSER_WIDTH-1 downto 0);
signal m_axis_aclk_i : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal m_axis_aresetn_i : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal m_axis_tvalid : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal m_axis_tready : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal m_axis_tdata : std_logic_vector(C_MAX_N_OARGS*C_M_AXIS_TDATA_WIDTH-1 downto 0);
signal m_axis_tstrb : std_logic_vector(C_MAX_N_OARGS*C_M_AXIS_TSTRB_WIDTH-1 downto 0);
signal m_axis_tkeep : std_logic_vector(C_MAX_N_OARGS*C_M_AXIS_TKEEP_WIDTH-1 downto 0);
signal m_axis_tlast : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal m_axis_tid : std_logic_vector(C_MAX_N_OARGS*C_M_AXIS_TID_WIDTH-1 downto 0);
signal m_axis_tdest : std_logic_vector(C_MAX_N_OARGS*C_M_AXIS_TDEST_WIDTH-1 downto 0);
signal m_axis_tuser : std_logic_vector(C_MAX_N_OARGS*C_M_AXIS_TUSER_WIDTH-1 downto 0);
signal ap_iarg_addr : std_logic_vector(C_MAX_N_IARGS*C_MAX_ARG_AWIDTH-1 downto 0);
signal ap_iarg_ce : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal ap_iarg_we : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal ap_iarg_din : std_logic_vector(C_MAX_N_IARGS*C_MAX_ARG_DWIDTH-1 downto 0);
signal ap_iarg_dout : std_logic_vector(C_MAX_N_IARGS*C_MAX_ARG_DWIDTH-1 downto 0);
signal ap_oarg_addr : std_logic_vector(C_MAX_N_OARGS*C_MAX_ARG_AWIDTH-1 downto 0);
signal ap_oarg_ce : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal ap_oarg_we : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal ap_oarg_din : std_logic_vector(C_MAX_N_OARGS*C_MAX_ARG_DWIDTH-1 downto 0);
signal ap_oarg_dout : std_logic_vector(C_MAX_N_OARGS*C_MAX_ARG_DWIDTH-1 downto 0);
-------------------------------------------------------
constant AP_IARG_0_OFFSET : integer := log2(C_AP_IARG_0_DWIDTH/8);
constant AP_IARG_1_OFFSET : integer := log2(C_AP_IARG_1_DWIDTH/8);
constant AP_IARG_2_OFFSET : integer := log2(C_AP_IARG_2_DWIDTH/8);
constant AP_IARG_3_OFFSET : integer := log2(C_AP_IARG_3_DWIDTH/8);
constant AP_IARG_4_OFFSET : integer := log2(C_AP_IARG_4_DWIDTH/8);
constant AP_IARG_5_OFFSET : integer := log2(C_AP_IARG_5_DWIDTH/8);
constant AP_IARG_6_OFFSET : integer := log2(C_AP_IARG_6_DWIDTH/8);
constant AP_IARG_7_OFFSET : integer := log2(C_AP_IARG_7_DWIDTH/8);
constant AP_OARG_0_OFFSET : integer := log2(C_AP_OARG_0_DWIDTH/8);
constant AP_OARG_1_OFFSET : integer := log2(C_AP_OARG_1_DWIDTH/8);
constant AP_OARG_2_OFFSET : integer := log2(C_AP_OARG_2_DWIDTH/8);
constant AP_OARG_3_OFFSET : integer := log2(C_AP_OARG_3_DWIDTH/8);
constant AP_OARG_4_OFFSET : integer := log2(C_AP_OARG_4_DWIDTH/8);
constant AP_OARG_5_OFFSET : integer := log2(C_AP_OARG_5_DWIDTH/8);
constant AP_OARG_6_OFFSET : integer := log2(C_AP_OARG_6_DWIDTH/8);
constant AP_OARG_7_OFFSET : integer := log2(C_AP_OARG_7_DWIDTH/8);
-------------------------------------------------
signal ap_fifo_iarg_dout : std_logic_vector(C_MAX_N_IARGS*C_MAX_ARG_DWIDTH-1 downto 0);
signal ap_fifo_iarg_read : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal ap_fifo_iarg_empty_n : std_logic_vector(C_MAX_N_IARGS-1 downto 0);
signal ap_fifo_oarg_din : std_logic_vector(C_MAX_N_OARGS*C_MAX_ARG_DWIDTH-1 downto 0);
signal ap_fifo_oarg_write : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
signal ap_fifo_oarg_full_n : std_logic_vector(C_MAX_N_OARGS-1 downto 0);
-------------------------------------------------
-- Scaler signals
signal ap_iscalar_dout_i : std_logic_vector(511 downto 0);
signal ap_oscalar_din_i : std_logic_vector(511 downto 0);
signal ap_oscalar_din_int : std_logic_vector(C_AP_OSCALAR_DIN_WIDTH-1 downto 0);
signal ap_ioscalar_din_int : std_logic_vector(C_AP_OSCALAR_IO_DIN_WIDTH-1 downto 0);
signal ap_oscalar_vld_i : std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_OSCALARS-1 downto 0);
signal ap_iscalar_vld_i : std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_ISCALARS-1 downto 0);
signal ap_oscalar_ack_i : std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_OSCALARS-1 downto 0);
signal ap_iscalar_ack_i : std_logic_vector(C_MAX_N_IOSCALARS+C_MAX_N_ISCALARS-1 downto 0);
signal zeros1 : std_logic_vector(256-C_AP_OSCALAR_DIN_WIDTH-1 downto 0);
signal zeros256 : std_logic_vector(255 downto 0);
begin
zeros1 <= (others => '0');
zeros256 <= (others => '0');
----------------------------------------------
-- Scalar signals assignments
----------------------------------------------
ap_oscalar_vld_i <= ap_oscalar_15_vld & ap_oscalar_14_vld & ap_oscalar_13_vld &
ap_oscalar_12_vld & ap_oscalar_11_vld & ap_oscalar_10_vld &
ap_oscalar_9_vld & ap_oscalar_8_vld & ap_oscalar_7_vld &
ap_oscalar_6_vld & ap_oscalar_5_vld & ap_oscalar_4_vld &
ap_oscalar_3_vld & ap_oscalar_2_vld & ap_oscalar_1_vld &
ap_oscalar_0_vld;
ap_iscalar_ack_i <= ap_iscalar_15_ack & ap_iscalar_14_ack & ap_iscalar_13_ack &
ap_iscalar_12_ack & ap_iscalar_11_ack & ap_iscalar_10_ack &
ap_iscalar_9_ack & ap_iscalar_8_ack & ap_iscalar_7_ack &
ap_iscalar_6_ack & ap_iscalar_5_ack & ap_iscalar_4_ack &
ap_iscalar_3_ack & ap_iscalar_2_ack & ap_iscalar_1_ack &
ap_iscalar_0_ack;
-- Output scalar ack generation
ap_oscalar_0_ack <= ap_oscalar_ack_i(0);
ap_oscalar_1_ack <= ap_oscalar_ack_i(1);
ap_oscalar_2_ack <= ap_oscalar_ack_i(2);
ap_oscalar_3_ack <= ap_oscalar_ack_i(3);
ap_oscalar_4_ack <= ap_oscalar_ack_i(4);
ap_oscalar_5_ack <= ap_oscalar_ack_i(5);
ap_oscalar_6_ack <= ap_oscalar_ack_i(6);
ap_oscalar_7_ack <= ap_oscalar_ack_i(7);
ap_oscalar_8_ack <= ap_oscalar_ack_i(8);
ap_oscalar_9_ack <= ap_oscalar_ack_i(9);
ap_oscalar_10_ack <= ap_oscalar_ack_i(10);
ap_oscalar_11_ack <= ap_oscalar_ack_i(11);
ap_oscalar_12_ack <= ap_oscalar_ack_i(12);
ap_oscalar_13_ack <= ap_oscalar_ack_i(13);
ap_oscalar_14_ack <= ap_oscalar_ack_i(14);
ap_oscalar_15_ack <= ap_oscalar_ack_i(15);
-- input scalar valid generation
ap_iscalar_0_vld <= ap_iscalar_vld_i(0);
ap_iscalar_1_vld <= ap_iscalar_vld_i(1);
ap_iscalar_2_vld <= ap_iscalar_vld_i(2);
ap_iscalar_3_vld <= ap_iscalar_vld_i(3);
ap_iscalar_4_vld <= ap_iscalar_vld_i(4);
ap_iscalar_5_vld <= ap_iscalar_vld_i(5);
ap_iscalar_6_vld <= ap_iscalar_vld_i(6);
ap_iscalar_7_vld <= ap_iscalar_vld_i(7);
ap_iscalar_8_vld <= ap_iscalar_vld_i(8);
ap_iscalar_9_vld <= ap_iscalar_vld_i(9);
ap_iscalar_10_vld <= ap_iscalar_vld_i(10);
ap_iscalar_11_vld <= ap_iscalar_vld_i(11);
ap_iscalar_12_vld <= ap_iscalar_vld_i(12);
ap_iscalar_13_vld <= ap_iscalar_vld_i(13);
ap_iscalar_14_vld <= ap_iscalar_vld_i(14);
ap_iscalar_15_vld <= ap_iscalar_vld_i(15);
----------------------------------------------
-- Output Scalar signals assignments
----------------------------------------------
OSCALER_0_GEN : if (C_N_OUTPUT_SCALARS = 0) generate
begin
ap_oscalar_din_int <= (others=>'0');
end generate OSCALER_0_GEN;
OSCALER_1_GEN : if (C_N_OUTPUT_SCALARS = 1) generate
begin
ap_oscalar_din_int <= ap_oscalar_0_din;
end generate OSCALER_1_GEN;
OSCALER_2_GEN : if (C_N_OUTPUT_SCALARS = 2) generate
begin
ap_oscalar_din_int <= ap_oscalar_1_din & ap_oscalar_0_din;
end generate OSCALER_2_GEN;
OSCALER_3_GEN : if (C_N_OUTPUT_SCALARS = 3) generate
begin
ap_oscalar_din_int <= ap_oscalar_2_din & ap_oscalar_1_din & ap_oscalar_0_din;
end generate OSCALER_3_GEN;
OSCALER_4_GEN : if (C_N_OUTPUT_SCALARS = 4) generate
begin
ap_oscalar_din_int <= ap_oscalar_3_din & ap_oscalar_2_din & ap_oscalar_1_din & ap_oscalar_0_din;
end generate OSCALER_4_GEN;
OSCALER_5_GEN : if (C_N_OUTPUT_SCALARS = 5) generate
begin
ap_oscalar_din_int <= ap_oscalar_4_din & ap_oscalar_3_din & ap_oscalar_2_din & ap_oscalar_1_din & ap_oscalar_0_din;
end generate OSCALER_5_GEN;
OSCALER_6_GEN : if (C_N_OUTPUT_SCALARS = 6) generate
begin
ap_oscalar_din_int <= ap_oscalar_5_din & ap_oscalar_4_din & ap_oscalar_3_din & ap_oscalar_2_din & ap_oscalar_1_din & ap_oscalar_0_din;
end generate OSCALER_6_GEN;
OSCALER_7_GEN : if (C_N_OUTPUT_SCALARS = 7) generate
begin
ap_oscalar_din_int <= ap_oscalar_6_din & ap_oscalar_5_din & ap_oscalar_4_din & ap_oscalar_3_din & ap_oscalar_2_din & ap_oscalar_1_din & ap_oscalar_0_din;
end generate OSCALER_7_GEN;
OSCALER_8_GEN : if (C_N_OUTPUT_SCALARS = 8) generate
begin
ap_oscalar_din_int <= ap_oscalar_7_din & ap_oscalar_6_din & ap_oscalar_5_din & ap_oscalar_4_din & ap_oscalar_3_din & ap_oscalar_2_din & ap_oscalar_1_din & ap_oscalar_0_din;
end generate OSCALER_8_GEN;
IOSCALER_0_GEN : if (C_N_INOUT_SCALARS = 0) generate
begin
ap_ioscalar_din_int <= (others=>'0');
end generate IOSCALER_0_GEN;
OSCALER_9_GEN : if (C_N_INOUT_SCALARS = 1) generate
begin
ap_ioscalar_din_int <= ap_oscalar_8_din;
end generate OSCALER_9_GEN;
OSCALER_10_GEN : if (C_N_INOUT_SCALARS = 2) generate
begin
ap_ioscalar_din_int <= ap_oscalar_9_din & ap_oscalar_8_din;
end generate OSCALER_10_GEN;
OSCALER_11_GEN : if (C_N_INOUT_SCALARS = 3) generate
begin
ap_ioscalar_din_int <= ap_oscalar_10_din & ap_oscalar_9_din & ap_oscalar_8_din;
end generate OSCALER_11_GEN;
OSCALER_12_GEN : if (C_N_INOUT_SCALARS = 4) generate
begin
ap_ioscalar_din_int <= ap_oscalar_11_din & ap_oscalar_10_din & ap_oscalar_9_din & ap_oscalar_8_din;
end generate OSCALER_12_GEN;
OSCALER_13_GEN : if (C_N_INOUT_SCALARS = 5) generate
begin
ap_ioscalar_din_int <= ap_oscalar_12_din & ap_oscalar_11_din & ap_oscalar_10_din & ap_oscalar_9_din & ap_oscalar_8_din;
end generate OSCALER_13_GEN;
OSCALER_14_GEN : if (C_N_INOUT_SCALARS = 6) generate
begin
ap_ioscalar_din_int <= ap_oscalar_13_din & ap_oscalar_12_din & ap_oscalar_11_din & ap_oscalar_10_din & ap_oscalar_9_din & ap_oscalar_8_din;
end generate OSCALER_14_GEN;
OSCALER_15_GEN : if (C_N_INOUT_SCALARS = 7) generate
begin
ap_ioscalar_din_int <= ap_oscalar_14_din & ap_oscalar_13_din & ap_oscalar_12_din & ap_oscalar_11_din & ap_oscalar_10_din & ap_oscalar_9_din & ap_oscalar_8_din;
end generate OSCALER_15_GEN;
OSCALER_16_GEN : if (C_N_INOUT_SCALARS = 8) generate
begin
ap_ioscalar_din_int <= ap_oscalar_15_din & ap_oscalar_14_din & ap_oscalar_13_din & ap_oscalar_12_din & ap_oscalar_11_din & ap_oscalar_10_din & ap_oscalar_9_din & ap_oscalar_8_din;
end generate OSCALER_16_GEN;
OSCALER_GEN_1 : if (C_N_INOUT_SCALARS > 0 and C_N_OUTPUT_SCALARS > 0) generate
begin
ap_oscalar_din_i(256+C_AP_OSCALAR_IO_DIN_WIDTH-1 downto 0) <= ap_ioscalar_din_int & zeros1 & ap_oscalar_din_int;
OSCALER_ZERO_GEN_1 : if (C_AP_OSCALAR_IO_DIN_WIDTH < 256 ) generate
ap_oscalar_din_i(511 downto 256+C_AP_OSCALAR_IO_DIN_WIDTH) <= (others =>'0') ;
end generate OSCALER_ZERO_GEN_1;
end generate OSCALER_GEN_1;
OSCALER_GEN_2 : if (C_N_INOUT_SCALARS = 0 and C_N_OUTPUT_SCALARS > 0) generate
begin
ap_oscalar_din_i(C_AP_OSCALAR_DIN_WIDTH-1 downto 0) <= ap_oscalar_din_int;
ap_oscalar_din_i(511 downto C_AP_OSCALAR_DIN_WIDTH) <= (others => '0');
end generate OSCALER_GEN_2;
OSCALER_GEN_3 : if (C_N_INOUT_SCALARS > 0 and C_N_OUTPUT_SCALARS = 0) generate
begin
ap_oscalar_din_i(256+C_AP_OSCALAR_IO_DIN_WIDTH-1 downto 0) <= ap_ioscalar_din_int & zeros256 ;
OSCALER_ZERO_GEN_3 : if (C_AP_OSCALAR_IO_DIN_WIDTH < 256 ) generate
ap_oscalar_din_i(511 downto 256+C_AP_OSCALAR_IO_DIN_WIDTH) <= (others =>'0') ;
end generate OSCALER_ZERO_GEN_3;
end generate OSCALER_GEN_3;
OSCALER_GEN_4 : if (C_N_INOUT_SCALARS = 0 and C_N_OUTPUT_SCALARS = 0) generate
begin
ap_oscalar_din_i <= (others => '0');
end generate OSCALER_GEN_4;
----------------------------------------------
-- Input Scalar signals assignments
----------------------------------------------
ISCALER_1_GEN : if (C_N_INPUT_SCALARS > 0) generate
begin
ap_iscalar_0_dout <= ap_iscalar_dout_i((get_compact_MSB(C_INPUT_SCALAR_DWIDTH, 0)) downto (get_compact_LSB(C_INPUT_SCALAR_DWIDTH, 0)));
end generate ISCALER_1_GEN;
ISCALER_2_GEN : if (C_N_INPUT_SCALARS > 1) generate
begin
ap_iscalar_1_dout <= ap_iscalar_dout_i((get_compact_MSB(C_INPUT_SCALAR_DWIDTH, 1)) downto (get_compact_LSB(C_INPUT_SCALAR_DWIDTH, 1)));
end generate ISCALER_2_GEN;
ISCALER_3_GEN : if (C_N_INPUT_SCALARS > 2) generate
begin
ap_iscalar_2_dout <= ap_iscalar_dout_i((get_compact_MSB(C_INPUT_SCALAR_DWIDTH, 2)) downto (get_compact_LSB(C_INPUT_SCALAR_DWIDTH, 2)));
end generate ISCALER_3_GEN;
ISCALER_4_GEN : if (C_N_INPUT_SCALARS > 3) generate
begin
ap_iscalar_3_dout <= ap_iscalar_dout_i((get_compact_MSB(C_INPUT_SCALAR_DWIDTH, 3)) downto (get_compact_LSB(C_INPUT_SCALAR_DWIDTH, 3)));
end generate ISCALER_4_GEN;
ISCALER_5_GEN : if (C_N_INPUT_SCALARS > 4) generate
begin
ap_iscalar_4_dout <= ap_iscalar_dout_i((get_compact_MSB(C_INPUT_SCALAR_DWIDTH, 4)) downto (get_compact_LSB(C_INPUT_SCALAR_DWIDTH, 4)));
end generate ISCALER_5_GEN;
ISCALER_6_GEN : if (C_N_INPUT_SCALARS > 5) generate
begin
ap_iscalar_5_dout <= ap_iscalar_dout_i((get_compact_MSB(C_INPUT_SCALAR_DWIDTH, 5)) downto (get_compact_LSB(C_INPUT_SCALAR_DWIDTH, 5)));
end generate ISCALER_6_GEN;
ISCALER_7_GEN : if (C_N_INPUT_SCALARS > 6) generate
begin
ap_iscalar_6_dout <= ap_iscalar_dout_i((get_compact_MSB(C_INPUT_SCALAR_DWIDTH, 6)) downto (get_compact_LSB(C_INPUT_SCALAR_DWIDTH, 6)));
end generate ISCALER_7_GEN;
ISCALER_8_GEN : if (C_N_INPUT_SCALARS > 7) generate
begin
ap_iscalar_7_dout <= ap_iscalar_dout_i((get_compact_MSB(C_INPUT_SCALAR_DWIDTH, 7)) downto (get_compact_LSB(C_INPUT_SCALAR_DWIDTH, 7)));
end generate ISCALER_8_GEN;
ISCALER_9_GEN : if (C_N_INOUT_SCALARS > 0) generate
begin
ap_iscalar_8_dout <= ap_iscalar_dout_i((get_compact_MSB_IO(C_INPUT_SCALAR_DWIDTH, 8)) downto (get_compact_LSB_IO(C_INPUT_SCALAR_DWIDTH, 8)));
end generate ISCALER_9_GEN;
ISCALER_10_GEN : if (C_N_INOUT_SCALARS > 1) generate
begin
ap_iscalar_9_dout <= ap_iscalar_dout_i((get_compact_MSB_IO(C_INPUT_SCALAR_DWIDTH, 9)) downto (get_compact_LSB_IO(C_INPUT_SCALAR_DWIDTH, 9)));
end generate ISCALER_10_GEN;
ISCALER_11_GEN : if (C_N_INOUT_SCALARS > 2) generate
begin
ap_iscalar_10_dout <= ap_iscalar_dout_i((get_compact_MSB_IO(C_INPUT_SCALAR_DWIDTH, 10)) downto (get_compact_LSB_IO(C_INPUT_SCALAR_DWIDTH, 10)));
end generate ISCALER_11_GEN;
ISCALER_12_GEN : if (C_N_INOUT_SCALARS > 3) generate
begin
ap_iscalar_11_dout <= ap_iscalar_dout_i((get_compact_MSB_IO(C_INPUT_SCALAR_DWIDTH, 11)) downto (get_compact_LSB_IO(C_INPUT_SCALAR_DWIDTH, 11)));
end generate ISCALER_12_GEN;
ISCALER_13_GEN : if (C_N_INOUT_SCALARS > 4) generate
begin
ap_iscalar_12_dout <= ap_iscalar_dout_i((get_compact_MSB_IO(C_INPUT_SCALAR_DWIDTH, 12)) downto (get_compact_LSB_IO(C_INPUT_SCALAR_DWIDTH, 12)));
end generate ISCALER_13_GEN;
ISCALER_14_GEN : if (C_N_INOUT_SCALARS > 5) generate
begin
ap_iscalar_13_dout <= ap_iscalar_dout_i((get_compact_MSB_IO(C_INPUT_SCALAR_DWIDTH, 13)) downto (get_compact_LSB_IO(C_INPUT_SCALAR_DWIDTH, 13)));
end generate ISCALER_14_GEN;
ISCALER_15_GEN : if (C_N_INOUT_SCALARS > 6) generate
begin
ap_iscalar_14_dout <= ap_iscalar_dout_i((get_compact_MSB_IO(C_INPUT_SCALAR_DWIDTH, 14)) downto (get_compact_LSB_IO(C_INPUT_SCALAR_DWIDTH, 14)));
end generate ISCALER_15_GEN;
ISCALER_16_GEN : if (C_N_INOUT_SCALARS > 7) generate
begin
ap_iscalar_15_dout <= ap_iscalar_dout_i((get_compact_MSB_IO(C_INPUT_SCALAR_DWIDTH, 15)) downto (get_compact_LSB_IO(C_INPUT_SCALAR_DWIDTH, 15)));
end generate ISCALER_16_GEN;
-----------------------------------------------------------------------------------------
-- AXI4-Stream Slave interface signal Generation
-- Single stremaing clock and reset port exposed to user. Asynchronous clocks between the
-- different streaming channel not supported
-----------------------------------------------------------------------------------------
SINGLE_CLK_RST_GEN : if (C_ENABLE_STREAM_CLK = 0) generate
s_axis_aclk_i(0) <= s_axis_aclk;
s_axis_aclk_i(1) <= s_axis_aclk;
s_axis_aclk_i(2) <= s_axis_aclk;
s_axis_aclk_i(3) <= s_axis_aclk;
s_axis_aclk_i(4) <= s_axis_aclk;
s_axis_aclk_i(5) <= s_axis_aclk;
s_axis_aclk_i(6) <= s_axis_aclk;
s_axis_aclk_i(7) <= s_axis_aclk;
s_axis_aresetn_i(0) <= s_axis_aresetn;
s_axis_aresetn_i(1) <= s_axis_aresetn;
s_axis_aresetn_i(2) <= s_axis_aresetn;
s_axis_aresetn_i(3) <= s_axis_aresetn;
s_axis_aresetn_i(4) <= s_axis_aresetn;
s_axis_aresetn_i(5) <= s_axis_aresetn;
s_axis_aresetn_i(6) <= s_axis_aresetn;
s_axis_aresetn_i(7) <= s_axis_aresetn;
m_axis_aclk_i(0) <= m_axis_aclk;
m_axis_aclk_i(1) <= m_axis_aclk;
m_axis_aclk_i(2) <= m_axis_aclk;
m_axis_aclk_i(3) <= m_axis_aclk;
m_axis_aclk_i(4) <= m_axis_aclk;
m_axis_aclk_i(5) <= m_axis_aclk;
m_axis_aclk_i(6) <= m_axis_aclk;
m_axis_aclk_i(7) <= m_axis_aclk;
m_axis_aresetn_i(0) <= m_axis_aresetn;
m_axis_aresetn_i(1) <= m_axis_aresetn;
m_axis_aresetn_i(2) <= m_axis_aresetn;
m_axis_aresetn_i(3) <= m_axis_aresetn;
m_axis_aresetn_i(4) <= m_axis_aresetn;
m_axis_aresetn_i(5) <= m_axis_aresetn;
m_axis_aresetn_i(6) <= m_axis_aresetn;
m_axis_aresetn_i(7) <= m_axis_aresetn;
end generate SINGLE_CLK_RST_GEN;
-----------------------------------------------------------------------------------------
-- AXI4-Stream Slave interface signal Generation
-- Asynchronous clocks between the different streaming channel supported
-----------------------------------------------------------------------------------------
ASYNC_CLK_RST_GEN : if (C_ENABLE_STREAM_CLK = 1) generate
s_axis_aclk_i(0) <= s_axis_0_aclk;
s_axis_aclk_i(1) <= s_axis_1_aclk;
s_axis_aclk_i(2) <= s_axis_2_aclk;
s_axis_aclk_i(3) <= s_axis_3_aclk;
s_axis_aclk_i(4) <= s_axis_4_aclk;
s_axis_aclk_i(5) <= s_axis_5_aclk;
s_axis_aclk_i(6) <= s_axis_6_aclk;
s_axis_aclk_i(7) <= s_axis_7_aclk;
s_axis_aresetn_i(0) <= s_axis_0_aresetn;
s_axis_aresetn_i(1) <= s_axis_1_aresetn;
s_axis_aresetn_i(2) <= s_axis_2_aresetn;
s_axis_aresetn_i(3) <= s_axis_3_aresetn;
s_axis_aresetn_i(4) <= s_axis_4_aresetn;
s_axis_aresetn_i(5) <= s_axis_5_aresetn;
s_axis_aresetn_i(6) <= s_axis_6_aresetn;
s_axis_aresetn_i(7) <= s_axis_7_aresetn;
m_axis_aclk_i(0) <= m_axis_0_aclk;
m_axis_aclk_i(1) <= m_axis_1_aclk;
m_axis_aclk_i(2) <= m_axis_2_aclk;
m_axis_aclk_i(3) <= m_axis_3_aclk;
m_axis_aclk_i(4) <= m_axis_4_aclk;
m_axis_aclk_i(5) <= m_axis_5_aclk;
m_axis_aclk_i(6) <= m_axis_6_aclk;
m_axis_aclk_i(7) <= m_axis_7_aclk;
m_axis_aresetn_i(0) <= m_axis_0_aresetn;
m_axis_aresetn_i(1) <= m_axis_1_aresetn;
m_axis_aresetn_i(2) <= m_axis_2_aresetn;
m_axis_aresetn_i(3) <= m_axis_3_aresetn;
m_axis_aresetn_i(4) <= m_axis_4_aresetn;
m_axis_aresetn_i(5) <= m_axis_5_aresetn;
m_axis_aresetn_i(6) <= m_axis_6_aresetn;
m_axis_aresetn_i(7) <= m_axis_7_aresetn;
end generate ASYNC_CLK_RST_GEN;
-------------------------------------------------------------------------------------------------
-- Assiging default value '1' when TSTRB and TKEEP signals are not present in the Input stream.
-- When Input stream STROBE and KEEP are available, no need to drive default values.
-- This is work around to resolve the Vivado wrapper issue which does not drive default input '1'
-- properly when signla widht is less than 4 bits.
-------------------------------------------------------------------------------------------------
EN_TSTRB_GEN : if (C_S_AXIS_HAS_TSTRB = 1) generate
s_axis_tstrb(C_S_AXIS_TSTRB_WIDTH*(0+1)-1 downto C_S_AXIS_TSTRB_WIDTH*0) <= s_axis_0_tstrb;
s_axis_tstrb(C_S_AXIS_TSTRB_WIDTH*(1+1)-1 downto C_S_AXIS_TSTRB_WIDTH*1) <= s_axis_1_tstrb;
s_axis_tstrb(C_S_AXIS_TSTRB_WIDTH*(2+1)-1 downto C_S_AXIS_TSTRB_WIDTH*2) <= s_axis_2_tstrb;
s_axis_tstrb(C_S_AXIS_TSTRB_WIDTH*(3+1)-1 downto C_S_AXIS_TSTRB_WIDTH*3) <= s_axis_3_tstrb;
s_axis_tstrb(C_S_AXIS_TSTRB_WIDTH*(4+1)-1 downto C_S_AXIS_TSTRB_WIDTH*4) <= s_axis_4_tstrb;
s_axis_tstrb(C_S_AXIS_TSTRB_WIDTH*(5+1)-1 downto C_S_AXIS_TSTRB_WIDTH*5) <= s_axis_5_tstrb;
s_axis_tstrb(C_S_AXIS_TSTRB_WIDTH*(6+1)-1 downto C_S_AXIS_TSTRB_WIDTH*6) <= s_axis_6_tstrb;
s_axis_tstrb(C_S_AXIS_TSTRB_WIDTH*(7+1)-1 downto C_S_AXIS_TSTRB_WIDTH*7) <= s_axis_7_tstrb;
end generate EN_TSTRB_GEN;
NO_TSTRB_GEN : if (C_S_AXIS_HAS_TSTRB = 0) generate
s_axis_tstrb <= (others => '1') ;
end generate NO_TSTRB_GEN;
-- TKEEP generation
EN_TKEEP_GEN : if (C_S_AXIS_HAS_TKEEP = 1) generate
s_axis_tkeep(C_S_AXIS_TKEEP_WIDTH*(0+1)-1 downto C_S_AXIS_TKEEP_WIDTH*0) <= s_axis_0_tkeep;
s_axis_tkeep(C_S_AXIS_TKEEP_WIDTH*(1+1)-1 downto C_S_AXIS_TKEEP_WIDTH*1) <= s_axis_1_tkeep;
s_axis_tkeep(C_S_AXIS_TKEEP_WIDTH*(2+1)-1 downto C_S_AXIS_TKEEP_WIDTH*2) <= s_axis_2_tkeep;
s_axis_tkeep(C_S_AXIS_TKEEP_WIDTH*(3+1)-1 downto C_S_AXIS_TKEEP_WIDTH*3) <= s_axis_3_tkeep;
s_axis_tkeep(C_S_AXIS_TKEEP_WIDTH*(4+1)-1 downto C_S_AXIS_TKEEP_WIDTH*4) <= s_axis_4_tkeep;
s_axis_tkeep(C_S_AXIS_TKEEP_WIDTH*(5+1)-1 downto C_S_AXIS_TKEEP_WIDTH*5) <= s_axis_5_tkeep;
s_axis_tkeep(C_S_AXIS_TKEEP_WIDTH*(6+1)-1 downto C_S_AXIS_TKEEP_WIDTH*6) <= s_axis_6_tkeep;
s_axis_tkeep(C_S_AXIS_TKEEP_WIDTH*(7+1)-1 downto C_S_AXIS_TKEEP_WIDTH*7) <= s_axis_7_tkeep;
end generate EN_TKEEP_GEN;
NO_TKEEP_GEN : if (C_S_AXIS_HAS_TKEEP = 0) generate
s_axis_tkeep <= (others => '1') ;
end generate NO_TKEEP_GEN;
-----------------------------------------------------------------------------------------
-- AXI4-Stream Slave interface signal Generation
-- SUPERBUSES BUILDING: SLAVE AXI STREAMS (INPUT ARGUMENTS):
-- NOTE FOR SIMULATION: This concatenation inserts a delta delay for clocks signals. In
-- the case of input signals causality is preserved becouse another delta delay is
-- inserted during their concatenation. For input signals, there is no problem
-----------------------------------------------------------------------------------------
--AXI4-Stream slave interface TVALID generation
s_axis_tvalid(0) <= s_axis_0_tvalid;
s_axis_tvalid(1) <= s_axis_1_tvalid;
s_axis_tvalid(2) <= s_axis_2_tvalid;
s_axis_tvalid(3) <= s_axis_3_tvalid;
s_axis_tvalid(4) <= s_axis_4_tvalid;
s_axis_tvalid(5) <= s_axis_5_tvalid;
s_axis_tvalid(6) <= s_axis_6_tvalid;
s_axis_tvalid(7) <= s_axis_7_tvalid;
--AXI4-Stream slave interface TREADY generation
s_axis_0_tready <= s_axis_tready(0);
s_axis_1_tready <= s_axis_tready(1);
s_axis_2_tready <= s_axis_tready(2);
s_axis_3_tready <= s_axis_tready(3);
s_axis_4_tready <= s_axis_tready(4);
s_axis_5_tready <= s_axis_tready(5);
s_axis_6_tready <= s_axis_tready(6);
s_axis_7_tready <= s_axis_tready(7);
--AXI4-Stream slave interface TDATA generation
s_axis_tdata(C_S_AXIS_TDATA_WIDTH*(0+1)-1 downto C_S_AXIS_TDATA_WIDTH*0) <= s_axis_0_tdata;
s_axis_tdata(C_S_AXIS_TDATA_WIDTH*(1+1)-1 downto C_S_AXIS_TDATA_WIDTH*1) <= s_axis_1_tdata;
s_axis_tdata(C_S_AXIS_TDATA_WIDTH*(2+1)-1 downto C_S_AXIS_TDATA_WIDTH*2) <= s_axis_2_tdata;
s_axis_tdata(C_S_AXIS_TDATA_WIDTH*(3+1)-1 downto C_S_AXIS_TDATA_WIDTH*3) <= s_axis_3_tdata;
s_axis_tdata(C_S_AXIS_TDATA_WIDTH*(4+1)-1 downto C_S_AXIS_TDATA_WIDTH*4) <= s_axis_4_tdata;
s_axis_tdata(C_S_AXIS_TDATA_WIDTH*(5+1)-1 downto C_S_AXIS_TDATA_WIDTH*5) <= s_axis_5_tdata;
s_axis_tdata(C_S_AXIS_TDATA_WIDTH*(6+1)-1 downto C_S_AXIS_TDATA_WIDTH*6) <= s_axis_6_tdata;
s_axis_tdata(C_S_AXIS_TDATA_WIDTH*(7+1)-1 downto C_S_AXIS_TDATA_WIDTH*7) <= s_axis_7_tdata;
--AXI4-Stream slave interface TLAST generation
s_axis_tlast(0) <= s_axis_0_tlast;
s_axis_tlast(1) <= s_axis_1_tlast;
s_axis_tlast(2) <= s_axis_2_tlast;
s_axis_tlast(3) <= s_axis_3_tlast;
s_axis_tlast(4) <= s_axis_4_tlast;
s_axis_tlast(5) <= s_axis_5_tlast;
s_axis_tlast(6) <= s_axis_6_tlast;
s_axis_tlast(7) <= s_axis_7_tlast;
--AXI4-Stream slave interface TID generation
s_axis_tid(C_S_AXIS_TID_WIDTH*(0+1)-1 downto C_S_AXIS_TID_WIDTH*0) <= s_axis_0_tid;
s_axis_tid(C_S_AXIS_TID_WIDTH*(1+1)-1 downto C_S_AXIS_TID_WIDTH*1) <= s_axis_1_tid;
s_axis_tid(C_S_AXIS_TID_WIDTH*(2+1)-1 downto C_S_AXIS_TID_WIDTH*2) <= s_axis_2_tid;
s_axis_tid(C_S_AXIS_TID_WIDTH*(3+1)-1 downto C_S_AXIS_TID_WIDTH*3) <= s_axis_3_tid;
s_axis_tid(C_S_AXIS_TID_WIDTH*(4+1)-1 downto C_S_AXIS_TID_WIDTH*4) <= s_axis_4_tid;
s_axis_tid(C_S_AXIS_TID_WIDTH*(5+1)-1 downto C_S_AXIS_TID_WIDTH*5) <= s_axis_5_tid;
s_axis_tid(C_S_AXIS_TID_WIDTH*(6+1)-1 downto C_S_AXIS_TID_WIDTH*6) <= s_axis_6_tid;
s_axis_tid(C_S_AXIS_TID_WIDTH*(7+1)-1 downto C_S_AXIS_TID_WIDTH*7) <= s_axis_7_tid;
--AXI4-Stream slave interface TDEST generation
s_axis_tdest(C_S_AXIS_TDEST_WIDTH*(0+1)-1 downto C_S_AXIS_TDEST_WIDTH*0) <= s_axis_0_tdest;
s_axis_tdest(C_S_AXIS_TDEST_WIDTH*(1+1)-1 downto C_S_AXIS_TDEST_WIDTH*1) <= s_axis_1_tdest;
s_axis_tdest(C_S_AXIS_TDEST_WIDTH*(2+1)-1 downto C_S_AXIS_TDEST_WIDTH*2) <= s_axis_2_tdest;
s_axis_tdest(C_S_AXIS_TDEST_WIDTH*(3+1)-1 downto C_S_AXIS_TDEST_WIDTH*3) <= s_axis_3_tdest;
s_axis_tdest(C_S_AXIS_TDEST_WIDTH*(4+1)-1 downto C_S_AXIS_TDEST_WIDTH*4) <= s_axis_4_tdest;
s_axis_tdest(C_S_AXIS_TDEST_WIDTH*(5+1)-1 downto C_S_AXIS_TDEST_WIDTH*5) <= s_axis_5_tdest;
s_axis_tdest(C_S_AXIS_TDEST_WIDTH*(6+1)-1 downto C_S_AXIS_TDEST_WIDTH*6) <= s_axis_6_tdest;
s_axis_tdest(C_S_AXIS_TDEST_WIDTH*(7+1)-1 downto C_S_AXIS_TDEST_WIDTH*7) <= s_axis_7_tdest;
--AXI4-Stream slave interface TUSER generation
s_axis_tuser(C_S_AXIS_TUSER_WIDTH*(0+1)-1 downto C_S_AXIS_TUSER_WIDTH*0) <= s_axis_0_tuser;
s_axis_tuser(C_S_AXIS_TUSER_WIDTH*(1+1)-1 downto C_S_AXIS_TUSER_WIDTH*1) <= s_axis_1_tuser;
s_axis_tuser(C_S_AXIS_TUSER_WIDTH*(2+1)-1 downto C_S_AXIS_TUSER_WIDTH*2) <= s_axis_2_tuser;
s_axis_tuser(C_S_AXIS_TUSER_WIDTH*(3+1)-1 downto C_S_AXIS_TUSER_WIDTH*3) <= s_axis_3_tuser;
s_axis_tuser(C_S_AXIS_TUSER_WIDTH*(4+1)-1 downto C_S_AXIS_TUSER_WIDTH*4) <= s_axis_4_tuser;
s_axis_tuser(C_S_AXIS_TUSER_WIDTH*(5+1)-1 downto C_S_AXIS_TUSER_WIDTH*5) <= s_axis_5_tuser;
s_axis_tuser(C_S_AXIS_TUSER_WIDTH*(6+1)-1 downto C_S_AXIS_TUSER_WIDTH*6) <= s_axis_6_tuser;
s_axis_tuser(C_S_AXIS_TUSER_WIDTH*(7+1)-1 downto C_S_AXIS_TUSER_WIDTH*7) <= s_axis_7_tuser;
-----------------------------------------------------------------------------------------
-- Accelerator Input Argument interface signal Generation
-- SUPERBUSES BUILDING: AP INPUT ARGUMENTS:
-----------------------------------------------------------------------------------------
-- Input Argument BRAM interface addr generation
ap_iarg_addr(C_MAX_ARG_AWIDTH*(0+1)-1 downto C_MAX_ARG_AWIDTH*0) <= ap_iarg_0_addr(C_MAX_ARG_AWIDTH+AP_IARG_0_OFFSET-1 downto AP_IARG_0_OFFSET);
ap_iarg_addr(C_MAX_ARG_AWIDTH*(1+1)-1 downto C_MAX_ARG_AWIDTH*1) <= ap_iarg_1_addr(C_MAX_ARG_AWIDTH+AP_IARG_1_OFFSET-1 downto AP_IARG_1_OFFSET);
ap_iarg_addr(C_MAX_ARG_AWIDTH*(2+1)-1 downto C_MAX_ARG_AWIDTH*2) <= ap_iarg_2_addr(C_MAX_ARG_AWIDTH+AP_IARG_2_OFFSET-1 downto AP_IARG_2_OFFSET);
ap_iarg_addr(C_MAX_ARG_AWIDTH*(3+1)-1 downto C_MAX_ARG_AWIDTH*3) <= ap_iarg_3_addr(C_MAX_ARG_AWIDTH+AP_IARG_3_OFFSET-1 downto AP_IARG_3_OFFSET);
ap_iarg_addr(C_MAX_ARG_AWIDTH*(4+1)-1 downto C_MAX_ARG_AWIDTH*4) <= ap_iarg_4_addr(C_MAX_ARG_AWIDTH+AP_IARG_4_OFFSET-1 downto AP_IARG_4_OFFSET);
ap_iarg_addr(C_MAX_ARG_AWIDTH*(5+1)-1 downto C_MAX_ARG_AWIDTH*5) <= ap_iarg_5_addr(C_MAX_ARG_AWIDTH+AP_IARG_5_OFFSET-1 downto AP_IARG_5_OFFSET);
ap_iarg_addr(C_MAX_ARG_AWIDTH*(6+1)-1 downto C_MAX_ARG_AWIDTH*6) <= ap_iarg_6_addr(C_MAX_ARG_AWIDTH+AP_IARG_6_OFFSET-1 downto AP_IARG_6_OFFSET);
ap_iarg_addr(C_MAX_ARG_AWIDTH*(7+1)-1 downto C_MAX_ARG_AWIDTH*7) <= ap_iarg_7_addr(C_MAX_ARG_AWIDTH+AP_IARG_7_OFFSET-1 downto AP_IARG_7_OFFSET);
-- Input Argument BRAM interface ce generation
ap_iarg_ce(0) <= ap_iarg_0_ce;
ap_iarg_ce(1) <= ap_iarg_1_ce;
ap_iarg_ce(2) <= ap_iarg_2_ce;
ap_iarg_ce(3) <= ap_iarg_3_ce;
ap_iarg_ce(4) <= ap_iarg_4_ce;
ap_iarg_ce(5) <= ap_iarg_5_ce;
ap_iarg_ce(6) <= ap_iarg_6_ce;
ap_iarg_ce(7) <= ap_iarg_7_ce;
-- Input Argument BRAM interface we generation
ap_iarg_we(0) <= ap_iarg_0_we(0);
ap_iarg_we(1) <= ap_iarg_1_we(0);
ap_iarg_we(2) <= ap_iarg_2_we(0);
ap_iarg_we(3) <= ap_iarg_3_we(0);
ap_iarg_we(4) <= ap_iarg_4_we(0);
ap_iarg_we(5) <= ap_iarg_5_we(0);
ap_iarg_we(6) <= ap_iarg_6_we(0);
ap_iarg_we(7) <= ap_iarg_7_we(0);
-- Input Argument BRAM interface din generation
ap_iarg_din(C_MAX_ARG_DWIDTH*(0+1)-1 downto C_MAX_ARG_DWIDTH*0) <= ext_lv(ap_iarg_0_din, C_MAX_ARG_DWIDTH);
ap_iarg_din(C_MAX_ARG_DWIDTH*(1+1)-1 downto C_MAX_ARG_DWIDTH*1) <= ext_lv(ap_iarg_1_din, C_MAX_ARG_DWIDTH);
ap_iarg_din(C_MAX_ARG_DWIDTH*(2+1)-1 downto C_MAX_ARG_DWIDTH*2) <= ext_lv(ap_iarg_2_din, C_MAX_ARG_DWIDTH);
ap_iarg_din(C_MAX_ARG_DWIDTH*(3+1)-1 downto C_MAX_ARG_DWIDTH*3) <= ext_lv(ap_iarg_3_din, C_MAX_ARG_DWIDTH);
ap_iarg_din(C_MAX_ARG_DWIDTH*(4+1)-1 downto C_MAX_ARG_DWIDTH*4) <= ext_lv(ap_iarg_4_din, C_MAX_ARG_DWIDTH);
ap_iarg_din(C_MAX_ARG_DWIDTH*(5+1)-1 downto C_MAX_ARG_DWIDTH*5) <= ext_lv(ap_iarg_5_din, C_MAX_ARG_DWIDTH);
ap_iarg_din(C_MAX_ARG_DWIDTH*(6+1)-1 downto C_MAX_ARG_DWIDTH*6) <= ext_lv(ap_iarg_6_din, C_MAX_ARG_DWIDTH);
ap_iarg_din(C_MAX_ARG_DWIDTH*(7+1)-1 downto C_MAX_ARG_DWIDTH*7) <= ext_lv(ap_iarg_7_din, C_MAX_ARG_DWIDTH);
-- Input Argument BRAM interface dout generation
ap_iarg_0_dout <= ap_iarg_dout(C_AP_IARG_0_DWIDTH-1+C_MAX_ARG_DWIDTH*0 downto C_MAX_ARG_DWIDTH*0);
ap_iarg_1_dout <= ap_iarg_dout(C_AP_IARG_1_DWIDTH-1+C_MAX_ARG_DWIDTH*1 downto C_MAX_ARG_DWIDTH*1);
ap_iarg_2_dout <= ap_iarg_dout(C_AP_IARG_2_DWIDTH-1+C_MAX_ARG_DWIDTH*2 downto C_MAX_ARG_DWIDTH*2);
ap_iarg_3_dout <= ap_iarg_dout(C_AP_IARG_3_DWIDTH-1+C_MAX_ARG_DWIDTH*3 downto C_MAX_ARG_DWIDTH*3);
ap_iarg_4_dout <= ap_iarg_dout(C_AP_IARG_4_DWIDTH-1+C_MAX_ARG_DWIDTH*4 downto C_MAX_ARG_DWIDTH*4);
ap_iarg_5_dout <= ap_iarg_dout(C_AP_IARG_5_DWIDTH-1+C_MAX_ARG_DWIDTH*5 downto C_MAX_ARG_DWIDTH*5);
ap_iarg_6_dout <= ap_iarg_dout(C_AP_IARG_6_DWIDTH-1+C_MAX_ARG_DWIDTH*6 downto C_MAX_ARG_DWIDTH*6);
ap_iarg_7_dout <= ap_iarg_dout(C_AP_IARG_7_DWIDTH-1+C_MAX_ARG_DWIDTH*7 downto C_MAX_ARG_DWIDTH*7);
-- Input Argument FIFO interface dout generation
ap_fifo_iarg_0_dout <= ap_fifo_iarg_dout(C_AP_IARG_0_DWIDTH-1+C_MAX_ARG_DWIDTH*0 downto C_MAX_ARG_DWIDTH*0);
ap_fifo_iarg_1_dout <= ap_fifo_iarg_dout(C_AP_IARG_1_DWIDTH-1+C_MAX_ARG_DWIDTH*1 downto C_MAX_ARG_DWIDTH*1);
ap_fifo_iarg_2_dout <= ap_fifo_iarg_dout(C_AP_IARG_2_DWIDTH-1+C_MAX_ARG_DWIDTH*2 downto C_MAX_ARG_DWIDTH*2);
ap_fifo_iarg_3_dout <= ap_fifo_iarg_dout(C_AP_IARG_3_DWIDTH-1+C_MAX_ARG_DWIDTH*3 downto C_MAX_ARG_DWIDTH*3);
ap_fifo_iarg_4_dout <= ap_fifo_iarg_dout(C_AP_IARG_4_DWIDTH-1+C_MAX_ARG_DWIDTH*4 downto C_MAX_ARG_DWIDTH*4);
ap_fifo_iarg_5_dout <= ap_fifo_iarg_dout(C_AP_IARG_5_DWIDTH-1+C_MAX_ARG_DWIDTH*5 downto C_MAX_ARG_DWIDTH*5);
ap_fifo_iarg_6_dout <= ap_fifo_iarg_dout(C_AP_IARG_6_DWIDTH-1+C_MAX_ARG_DWIDTH*6 downto C_MAX_ARG_DWIDTH*6);
ap_fifo_iarg_7_dout <= ap_fifo_iarg_dout(C_AP_IARG_7_DWIDTH-1+C_MAX_ARG_DWIDTH*7 downto C_MAX_ARG_DWIDTH*7);
-- Input Argument FIFO interface read generation
ap_fifo_iarg_read(0) <= ap_fifo_iarg_0_read;
ap_fifo_iarg_read(1) <= ap_fifo_iarg_1_read;
ap_fifo_iarg_read(2) <= ap_fifo_iarg_2_read;
ap_fifo_iarg_read(3) <= ap_fifo_iarg_3_read;
ap_fifo_iarg_read(4) <= ap_fifo_iarg_4_read;
ap_fifo_iarg_read(5) <= ap_fifo_iarg_5_read;
ap_fifo_iarg_read(6) <= ap_fifo_iarg_6_read;
ap_fifo_iarg_read(7) <= ap_fifo_iarg_7_read;
-- Input Argument FIFO interface empty generation
ap_fifo_iarg_0_empty_n <= ap_fifo_iarg_empty_n(0);
ap_fifo_iarg_1_empty_n <= ap_fifo_iarg_empty_n(1);
ap_fifo_iarg_2_empty_n <= ap_fifo_iarg_empty_n(2);
ap_fifo_iarg_3_empty_n <= ap_fifo_iarg_empty_n(3);
ap_fifo_iarg_4_empty_n <= ap_fifo_iarg_empty_n(4);
ap_fifo_iarg_5_empty_n <= ap_fifo_iarg_empty_n(5);
ap_fifo_iarg_6_empty_n <= ap_fifo_iarg_empty_n(6);
ap_fifo_iarg_7_empty_n <= ap_fifo_iarg_empty_n(7);
-----------------------------------------------------------------------------------------
-- AXI4-Stream Slave interface signal Generation
-- SUPERBUSES BUILDING: MASTER AXI STREAMS (OUTPUT ARGUMENTS):
-- NOTE FOR SIMULATION: This concatenation inserts a delta delay for clocks signals. In
-- the case of input signals causality is preserved becouse another delta delay is
-- inserted during their concatenation. For input signals, there is no problem
-----------------------------------------------------------------------------------------
--AXI4-Stream master interface TVALID generation
m_axis_0_tvalid <= m_axis_tvalid(0);
m_axis_1_tvalid <= m_axis_tvalid(1);
m_axis_2_tvalid <= m_axis_tvalid(2);
m_axis_3_tvalid <= m_axis_tvalid(3);
m_axis_4_tvalid <= m_axis_tvalid(4);
m_axis_5_tvalid <= m_axis_tvalid(5);
m_axis_6_tvalid <= m_axis_tvalid(6);
m_axis_7_tvalid <= m_axis_tvalid(7);
--AXI4-Stream master interface TREADY generation
m_axis_tready(0) <= m_axis_0_tready;
m_axis_tready(1) <= m_axis_1_tready;
m_axis_tready(2) <= m_axis_2_tready;
m_axis_tready(3) <= m_axis_3_tready;
m_axis_tready(4) <= m_axis_4_tready;
m_axis_tready(5) <= m_axis_5_tready;
m_axis_tready(6) <= m_axis_6_tready;
m_axis_tready(7) <= m_axis_7_tready;
--AXI4-Stream master interface TDATA generation
m_axis_0_tdata <= m_axis_tdata(C_M_AXIS_TDATA_WIDTH*(0+1)-1 downto C_M_AXIS_TDATA_WIDTH*0);
m_axis_1_tdata <= m_axis_tdata(C_M_AXIS_TDATA_WIDTH*(1+1)-1 downto C_M_AXIS_TDATA_WIDTH*1);
m_axis_2_tdata <= m_axis_tdata(C_M_AXIS_TDATA_WIDTH*(2+1)-1 downto C_M_AXIS_TDATA_WIDTH*2);
m_axis_3_tdata <= m_axis_tdata(C_M_AXIS_TDATA_WIDTH*(3+1)-1 downto C_M_AXIS_TDATA_WIDTH*3);
m_axis_4_tdata <= m_axis_tdata(C_M_AXIS_TDATA_WIDTH*(4+1)-1 downto C_M_AXIS_TDATA_WIDTH*4);
m_axis_5_tdata <= m_axis_tdata(C_M_AXIS_TDATA_WIDTH*(5+1)-1 downto C_M_AXIS_TDATA_WIDTH*5);
m_axis_6_tdata <= m_axis_tdata(C_M_AXIS_TDATA_WIDTH*(6+1)-1 downto C_M_AXIS_TDATA_WIDTH*6);
m_axis_7_tdata <= m_axis_tdata(C_M_AXIS_TDATA_WIDTH*(7+1)-1 downto C_M_AXIS_TDATA_WIDTH*7);
--AXI4-Stream master interface TSTRB generation
m_axis_0_tstrb <= m_axis_tstrb(C_M_AXIS_TSTRB_WIDTH*(0+1)-1 downto C_M_AXIS_TSTRB_WIDTH*0);
m_axis_1_tstrb <= m_axis_tstrb(C_M_AXIS_TSTRB_WIDTH*(1+1)-1 downto C_M_AXIS_TSTRB_WIDTH*1);
m_axis_2_tstrb <= m_axis_tstrb(C_M_AXIS_TSTRB_WIDTH*(2+1)-1 downto C_M_AXIS_TSTRB_WIDTH*2);
m_axis_3_tstrb <= m_axis_tstrb(C_M_AXIS_TSTRB_WIDTH*(3+1)-1 downto C_M_AXIS_TSTRB_WIDTH*3);
m_axis_4_tstrb <= m_axis_tstrb(C_M_AXIS_TSTRB_WIDTH*(4+1)-1 downto C_M_AXIS_TSTRB_WIDTH*4);
m_axis_5_tstrb <= m_axis_tstrb(C_M_AXIS_TSTRB_WIDTH*(5+1)-1 downto C_M_AXIS_TSTRB_WIDTH*5);
m_axis_6_tstrb <= m_axis_tstrb(C_M_AXIS_TSTRB_WIDTH*(6+1)-1 downto C_M_AXIS_TSTRB_WIDTH*6);
m_axis_7_tstrb <= m_axis_tstrb(C_M_AXIS_TSTRB_WIDTH*(7+1)-1 downto C_M_AXIS_TSTRB_WIDTH*7);
--AXI4-Stream master interface TKEEP generation
m_axis_0_tkeep <= m_axis_tkeep(C_M_AXIS_TKEEP_WIDTH*(0+1)-1 downto C_M_AXIS_TKEEP_WIDTH*0);
m_axis_1_tkeep <= m_axis_tkeep(C_M_AXIS_TKEEP_WIDTH*(1+1)-1 downto C_M_AXIS_TKEEP_WIDTH*1);
m_axis_2_tkeep <= m_axis_tkeep(C_M_AXIS_TKEEP_WIDTH*(2+1)-1 downto C_M_AXIS_TKEEP_WIDTH*2);
m_axis_3_tkeep <= m_axis_tkeep(C_M_AXIS_TKEEP_WIDTH*(3+1)-1 downto C_M_AXIS_TKEEP_WIDTH*3);
m_axis_4_tkeep <= m_axis_tkeep(C_M_AXIS_TKEEP_WIDTH*(4+1)-1 downto C_M_AXIS_TKEEP_WIDTH*4);
m_axis_5_tkeep <= m_axis_tkeep(C_M_AXIS_TKEEP_WIDTH*(5+1)-1 downto C_M_AXIS_TKEEP_WIDTH*5);
m_axis_6_tkeep <= m_axis_tkeep(C_M_AXIS_TKEEP_WIDTH*(6+1)-1 downto C_M_AXIS_TKEEP_WIDTH*6);
m_axis_7_tkeep <= m_axis_tkeep(C_M_AXIS_TKEEP_WIDTH*(7+1)-1 downto C_M_AXIS_TKEEP_WIDTH*7);
--AXI4-Stream master interface TLAST generation
m_axis_0_tlast <= m_axis_tlast(0);
m_axis_1_tlast <= m_axis_tlast(1);
m_axis_2_tlast <= m_axis_tlast(2);
m_axis_3_tlast <= m_axis_tlast(3);
m_axis_4_tlast <= m_axis_tlast(4);
m_axis_5_tlast <= m_axis_tlast(5);
m_axis_6_tlast <= m_axis_tlast(6);
m_axis_7_tlast <= m_axis_tlast(7);
--AXI4-Stream master interface TID generation
m_axis_0_tid <= m_axis_tid(C_M_AXIS_TID_WIDTH*(0+1)-1 downto C_M_AXIS_TID_WIDTH*0);
m_axis_1_tid <= m_axis_tid(C_M_AXIS_TID_WIDTH*(1+1)-1 downto C_M_AXIS_TID_WIDTH*1);
m_axis_2_tid <= m_axis_tid(C_M_AXIS_TID_WIDTH*(2+1)-1 downto C_M_AXIS_TID_WIDTH*2);
m_axis_3_tid <= m_axis_tid(C_M_AXIS_TID_WIDTH*(3+1)-1 downto C_M_AXIS_TID_WIDTH*3);
m_axis_4_tid <= m_axis_tid(C_M_AXIS_TID_WIDTH*(4+1)-1 downto C_M_AXIS_TID_WIDTH*4);
m_axis_5_tid <= m_axis_tid(C_M_AXIS_TID_WIDTH*(5+1)-1 downto C_M_AXIS_TID_WIDTH*5);
m_axis_6_tid <= m_axis_tid(C_M_AXIS_TID_WIDTH*(6+1)-1 downto C_M_AXIS_TID_WIDTH*6);
m_axis_7_tid <= m_axis_tid(C_M_AXIS_TID_WIDTH*(7+1)-1 downto C_M_AXIS_TID_WIDTH*7);
--AXI4-Stream master interface TDEST generation
m_axis_0_tdest <= m_axis_tdest(C_M_AXIS_TDEST_WIDTH*(0+1)-1 downto C_M_AXIS_TDEST_WIDTH*0);
m_axis_1_tdest <= m_axis_tdest(C_M_AXIS_TDEST_WIDTH*(1+1)-1 downto C_M_AXIS_TDEST_WIDTH*1);
m_axis_2_tdest <= m_axis_tdest(C_M_AXIS_TDEST_WIDTH*(2+1)-1 downto C_M_AXIS_TDEST_WIDTH*2);
m_axis_3_tdest <= m_axis_tdest(C_M_AXIS_TDEST_WIDTH*(3+1)-1 downto C_M_AXIS_TDEST_WIDTH*3);
m_axis_4_tdest <= m_axis_tdest(C_M_AXIS_TDEST_WIDTH*(4+1)-1 downto C_M_AXIS_TDEST_WIDTH*4);
m_axis_5_tdest <= m_axis_tdest(C_M_AXIS_TDEST_WIDTH*(5+1)-1 downto C_M_AXIS_TDEST_WIDTH*5);
m_axis_6_tdest <= m_axis_tdest(C_M_AXIS_TDEST_WIDTH*(6+1)-1 downto C_M_AXIS_TDEST_WIDTH*6);
m_axis_7_tdest <= m_axis_tdest(C_M_AXIS_TDEST_WIDTH*(7+1)-1 downto C_M_AXIS_TDEST_WIDTH*7);
--AXI4-Stream master interface TKEEP generation
m_axis_0_tuser <= m_axis_tuser(C_M_AXIS_TUSER_WIDTH*(0+1)-1 downto C_M_AXIS_TUSER_WIDTH*0);
m_axis_1_tuser <= m_axis_tuser(C_M_AXIS_TUSER_WIDTH*(1+1)-1 downto C_M_AXIS_TUSER_WIDTH*1);
m_axis_2_tuser <= m_axis_tuser(C_M_AXIS_TUSER_WIDTH*(2+1)-1 downto C_M_AXIS_TUSER_WIDTH*2);
m_axis_3_tuser <= m_axis_tuser(C_M_AXIS_TUSER_WIDTH*(3+1)-1 downto C_M_AXIS_TUSER_WIDTH*3);
m_axis_4_tuser <= m_axis_tuser(C_M_AXIS_TUSER_WIDTH*(4+1)-1 downto C_M_AXIS_TUSER_WIDTH*4);
m_axis_5_tuser <= m_axis_tuser(C_M_AXIS_TUSER_WIDTH*(5+1)-1 downto C_M_AXIS_TUSER_WIDTH*5);
m_axis_6_tuser <= m_axis_tuser(C_M_AXIS_TUSER_WIDTH*(6+1)-1 downto C_M_AXIS_TUSER_WIDTH*6);
m_axis_7_tuser <= m_axis_tuser(C_M_AXIS_TUSER_WIDTH*(7+1)-1 downto C_M_AXIS_TUSER_WIDTH*7);
-----------------------------------------------------------------------------------------
-- Accelerator Output Argument interface signal Generation
-- SUPERBUSES BUILDING: AP Output ARGUMENTS:
-----------------------------------------------------------------------------------------
-- Output Argument BRAM interface addr generation
ap_oarg_addr(C_MAX_ARG_AWIDTH*(0+1)-1 downto C_MAX_ARG_AWIDTH*0) <= ap_oarg_0_addr(C_MAX_ARG_AWIDTH+AP_OARG_0_OFFSET-1 downto AP_OARG_0_OFFSET);
ap_oarg_addr(C_MAX_ARG_AWIDTH*(1+1)-1 downto C_MAX_ARG_AWIDTH*1) <= ap_oarg_1_addr(C_MAX_ARG_AWIDTH+AP_OARG_1_OFFSET-1 downto AP_OARG_1_OFFSET);
ap_oarg_addr(C_MAX_ARG_AWIDTH*(2+1)-1 downto C_MAX_ARG_AWIDTH*2) <= ap_oarg_2_addr(C_MAX_ARG_AWIDTH+AP_OARG_2_OFFSET-1 downto AP_OARG_2_OFFSET);
ap_oarg_addr(C_MAX_ARG_AWIDTH*(3+1)-1 downto C_MAX_ARG_AWIDTH*3) <= ap_oarg_3_addr(C_MAX_ARG_AWIDTH+AP_OARG_3_OFFSET-1 downto AP_OARG_3_OFFSET);
ap_oarg_addr(C_MAX_ARG_AWIDTH*(4+1)-1 downto C_MAX_ARG_AWIDTH*4) <= ap_oarg_4_addr(C_MAX_ARG_AWIDTH+AP_OARG_4_OFFSET-1 downto AP_OARG_4_OFFSET);
ap_oarg_addr(C_MAX_ARG_AWIDTH*(5+1)-1 downto C_MAX_ARG_AWIDTH*5) <= ap_oarg_5_addr(C_MAX_ARG_AWIDTH+AP_OARG_5_OFFSET-1 downto AP_OARG_5_OFFSET);
ap_oarg_addr(C_MAX_ARG_AWIDTH*(6+1)-1 downto C_MAX_ARG_AWIDTH*6) <= ap_oarg_6_addr(C_MAX_ARG_AWIDTH+AP_OARG_6_OFFSET-1 downto AP_OARG_6_OFFSET);
ap_oarg_addr(C_MAX_ARG_AWIDTH*(7+1)-1 downto C_MAX_ARG_AWIDTH*7) <= ap_oarg_7_addr(C_MAX_ARG_AWIDTH+AP_OARG_7_OFFSET-1 downto AP_OARG_7_OFFSET);
-- Output Argument BRAM interface ce generation
ap_oarg_ce(0) <= ap_oarg_0_ce;
ap_oarg_ce(1) <= ap_oarg_1_ce;
ap_oarg_ce(2) <= ap_oarg_2_ce;
ap_oarg_ce(3) <= ap_oarg_3_ce;
ap_oarg_ce(4) <= ap_oarg_4_ce;
ap_oarg_ce(5) <= ap_oarg_5_ce;
ap_oarg_ce(6) <= ap_oarg_6_ce;
ap_oarg_ce(7) <= ap_oarg_7_ce;
-- Output Argument BRAM interface we generation
ap_oarg_we(0) <= ap_oarg_0_we(0);
ap_oarg_we(1) <= ap_oarg_1_we(0);
ap_oarg_we(2) <= ap_oarg_2_we(0);
ap_oarg_we(3) <= ap_oarg_3_we(0);
ap_oarg_we(4) <= ap_oarg_4_we(0);
ap_oarg_we(5) <= ap_oarg_5_we(0);
ap_oarg_we(6) <= ap_oarg_6_we(0);
ap_oarg_we(7) <= ap_oarg_7_we(0);
-- Output Argument BRAM interface din generation
ap_oarg_din(C_MAX_ARG_DWIDTH*(0+1)-1 downto C_MAX_ARG_DWIDTH*0) <= ext_lv(ap_oarg_0_din, C_MAX_ARG_DWIDTH);
ap_oarg_din(C_MAX_ARG_DWIDTH*(1+1)-1 downto C_MAX_ARG_DWIDTH*1) <= ext_lv(ap_oarg_1_din, C_MAX_ARG_DWIDTH);
ap_oarg_din(C_MAX_ARG_DWIDTH*(2+1)-1 downto C_MAX_ARG_DWIDTH*2) <= ext_lv(ap_oarg_2_din, C_MAX_ARG_DWIDTH);
ap_oarg_din(C_MAX_ARG_DWIDTH*(3+1)-1 downto C_MAX_ARG_DWIDTH*3) <= ext_lv(ap_oarg_3_din, C_MAX_ARG_DWIDTH);
ap_oarg_din(C_MAX_ARG_DWIDTH*(4+1)-1 downto C_MAX_ARG_DWIDTH*4) <= ext_lv(ap_oarg_4_din, C_MAX_ARG_DWIDTH);
ap_oarg_din(C_MAX_ARG_DWIDTH*(5+1)-1 downto C_MAX_ARG_DWIDTH*5) <= ext_lv(ap_oarg_5_din, C_MAX_ARG_DWIDTH);
ap_oarg_din(C_MAX_ARG_DWIDTH*(6+1)-1 downto C_MAX_ARG_DWIDTH*6) <= ext_lv(ap_oarg_6_din, C_MAX_ARG_DWIDTH);
ap_oarg_din(C_MAX_ARG_DWIDTH*(7+1)-1 downto C_MAX_ARG_DWIDTH*7) <= ext_lv(ap_oarg_7_din, C_MAX_ARG_DWIDTH);
-- Output Argument BRAM interface dout generation
ap_oarg_0_dout <= ap_oarg_dout(C_AP_OARG_0_DWIDTH-1+C_MAX_ARG_DWIDTH*0 downto C_MAX_ARG_DWIDTH*0);
ap_oarg_1_dout <= ap_oarg_dout(C_AP_OARG_1_DWIDTH-1+C_MAX_ARG_DWIDTH*1 downto C_MAX_ARG_DWIDTH*1);
ap_oarg_2_dout <= ap_oarg_dout(C_AP_OARG_2_DWIDTH-1+C_MAX_ARG_DWIDTH*2 downto C_MAX_ARG_DWIDTH*2);
ap_oarg_3_dout <= ap_oarg_dout(C_AP_OARG_3_DWIDTH-1+C_MAX_ARG_DWIDTH*3 downto C_MAX_ARG_DWIDTH*3);
ap_oarg_4_dout <= ap_oarg_dout(C_AP_OARG_4_DWIDTH-1+C_MAX_ARG_DWIDTH*4 downto C_MAX_ARG_DWIDTH*4);
ap_oarg_5_dout <= ap_oarg_dout(C_AP_OARG_5_DWIDTH-1+C_MAX_ARG_DWIDTH*5 downto C_MAX_ARG_DWIDTH*5);
ap_oarg_6_dout <= ap_oarg_dout(C_AP_OARG_6_DWIDTH-1+C_MAX_ARG_DWIDTH*6 downto C_MAX_ARG_DWIDTH*6);
ap_oarg_7_dout <= ap_oarg_dout(C_AP_OARG_7_DWIDTH-1+C_MAX_ARG_DWIDTH*7 downto C_MAX_ARG_DWIDTH*7);
-- Output Argument FIFO interface din generation
ap_fifo_oarg_din(C_AP_OARG_0_DWIDTH-1+C_MAX_ARG_DWIDTH*0 downto C_MAX_ARG_DWIDTH*0) <= ap_fifo_oarg_0_din;
ap_fifo_oarg_din(C_AP_OARG_1_DWIDTH-1+C_MAX_ARG_DWIDTH*1 downto C_MAX_ARG_DWIDTH*1) <= ap_fifo_oarg_1_din;
ap_fifo_oarg_din(C_AP_OARG_2_DWIDTH-1+C_MAX_ARG_DWIDTH*2 downto C_MAX_ARG_DWIDTH*2) <= ap_fifo_oarg_2_din;
ap_fifo_oarg_din(C_AP_OARG_3_DWIDTH-1+C_MAX_ARG_DWIDTH*3 downto C_MAX_ARG_DWIDTH*3) <= ap_fifo_oarg_3_din;
ap_fifo_oarg_din(C_AP_OARG_4_DWIDTH-1+C_MAX_ARG_DWIDTH*4 downto C_MAX_ARG_DWIDTH*4) <= ap_fifo_oarg_4_din;
ap_fifo_oarg_din(C_AP_OARG_5_DWIDTH-1+C_MAX_ARG_DWIDTH*5 downto C_MAX_ARG_DWIDTH*5) <= ap_fifo_oarg_5_din;
ap_fifo_oarg_din(C_AP_OARG_6_DWIDTH-1+C_MAX_ARG_DWIDTH*6 downto C_MAX_ARG_DWIDTH*6) <= ap_fifo_oarg_6_din;
ap_fifo_oarg_din(C_AP_OARG_7_DWIDTH-1+C_MAX_ARG_DWIDTH*7 downto C_MAX_ARG_DWIDTH*7) <= ap_fifo_oarg_7_din;
-- Assining unused bits in the vector to default value to reduce synthesis warnings.
ap_fifo_oarg_din(C_MAX_ARG_DWIDTH-1+C_MAX_ARG_DWIDTH*0 downto C_AP_OARG_0_DWIDTH+C_MAX_ARG_DWIDTH*0) <= (others => '0');
ap_fifo_oarg_din(C_MAX_ARG_DWIDTH-1+C_MAX_ARG_DWIDTH*1 downto C_AP_OARG_1_DWIDTH+C_MAX_ARG_DWIDTH*1) <= (others => '0');
ap_fifo_oarg_din(C_MAX_ARG_DWIDTH-1+C_MAX_ARG_DWIDTH*2 downto C_AP_OARG_2_DWIDTH+C_MAX_ARG_DWIDTH*2) <= (others => '0');
ap_fifo_oarg_din(C_MAX_ARG_DWIDTH-1+C_MAX_ARG_DWIDTH*3 downto C_AP_OARG_3_DWIDTH+C_MAX_ARG_DWIDTH*3) <= (others => '0');
ap_fifo_oarg_din(C_MAX_ARG_DWIDTH-1+C_MAX_ARG_DWIDTH*4 downto C_AP_OARG_4_DWIDTH+C_MAX_ARG_DWIDTH*4) <= (others => '0');
ap_fifo_oarg_din(C_MAX_ARG_DWIDTH-1+C_MAX_ARG_DWIDTH*5 downto C_AP_OARG_5_DWIDTH+C_MAX_ARG_DWIDTH*5) <= (others => '0');
ap_fifo_oarg_din(C_MAX_ARG_DWIDTH-1+C_MAX_ARG_DWIDTH*6 downto C_AP_OARG_6_DWIDTH+C_MAX_ARG_DWIDTH*6) <= (others => '0');
ap_fifo_oarg_din(C_MAX_ARG_DWIDTH-1+C_MAX_ARG_DWIDTH*7 downto C_AP_OARG_7_DWIDTH+C_MAX_ARG_DWIDTH*7) <= (others => '0');
-- Output Argument FIFO interface fifo_write generation
ap_fifo_oarg_write(0) <= ap_fifo_oarg_0_write;
ap_fifo_oarg_write(1) <= ap_fifo_oarg_1_write;
ap_fifo_oarg_write(2) <= ap_fifo_oarg_2_write;
ap_fifo_oarg_write(3) <= ap_fifo_oarg_3_write;
ap_fifo_oarg_write(4) <= ap_fifo_oarg_4_write;
ap_fifo_oarg_write(5) <= ap_fifo_oarg_5_write;
ap_fifo_oarg_write(6) <= ap_fifo_oarg_6_write;
ap_fifo_oarg_write(7) <= ap_fifo_oarg_7_write;
-- Output Argument FIFO interface fifo_full generation
ap_fifo_oarg_0_full_n <= ap_fifo_oarg_full_n(0);
ap_fifo_oarg_1_full_n <= ap_fifo_oarg_full_n(1);
ap_fifo_oarg_2_full_n <= ap_fifo_oarg_full_n(2);
ap_fifo_oarg_3_full_n <= ap_fifo_oarg_full_n(3);
ap_fifo_oarg_4_full_n <= ap_fifo_oarg_full_n(4);
ap_fifo_oarg_5_full_n <= ap_fifo_oarg_full_n(5);
ap_fifo_oarg_6_full_n <= ap_fifo_oarg_full_n(6);
ap_fifo_oarg_7_full_n <= ap_fifo_oarg_full_n(7);
--------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------
-- XD_ADAPTER_CORE_I : Adapter core logic
-----------------------------------------------------------------------------------------
XD_ADAPTER_CORE_I : entity axis_accelerator_adapter_v2_1_6.axis_accelerator_adapter_core
generic map (
-- System generics:
C_FAMILY => C_FAMILY,
C_BRAM_TYPE => BRAM_PRIMITIVE_TYPE,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC,
C_MTBF_STAGES => C_MTBF_STAGES,
--
C_AP_ADAPTER_ID => C_AP_ADAPTER_ID,
C_MAX_SCALAR_DWIDTH => C_MAX_SCALAR_DWIDTH,
C_MAX_ARG_DWIDTH => C_MAX_ARG_DWIDTH,
C_MAX_ARG_AWIDTH => C_MAX_ARG_AWIDTH,
C_MAX_ARG_N_DIM => C_MAX_ARG_N_DIM,
C_MAX_MB_DEPTH => C_MAX_MB_DEPTH,
C_MAX_N_IARGS => C_MAX_N_IARGS,
C_MAX_N_OARGS => C_MAX_N_OARGS,
C_MAX_N_ISCALARS => C_MAX_N_ISCALARS+C_MAX_N_IOSCALARS,
C_MAX_N_OSCALARS => C_MAX_N_OSCALARS+C_MAX_N_IOSCALARS,
C_MAX_N_IOSCALARS => C_MAX_N_IOSCALARS,
--
C_N_INPUT_ARGS => C_N_INPUT_ARGS,
C_N_OUTPUT_ARGS => C_N_OUTPUT_ARGS,
--
C_S_AXIS_TDATA_WIDTH => C_S_AXIS_TDATA_WIDTH,
C_S_AXIS_TUSER_WIDTH => C_S_AXIS_TUSER_WIDTH,
C_S_AXIS_TID_WIDTH => C_S_AXIS_TID_WIDTH,
C_S_AXIS_TDEST_WIDTH => C_S_AXIS_TDEST_WIDTH,
--
C_AP_IARG_TYPE => C_AP_IARG_TYPE,
C_AP_IARG_DWIDTH => C_AP_IARG_DWIDTH,
C_AP_IARG_MB_DEPTH => C_AP_IARG_MB_DEPTH,
--
C_AP_IARG_WIDTH => C_AP_IARG_WIDTH,
C_AP_IARG_N_DIM => C_AP_IARG_N_DIM,
C_AP_IARG_DIM_1 => C_AP_IARG_DIM_1,
C_AP_IARG_DIM_2 => C_AP_IARG_DIM_2,
C_AP_IARG_FORMAT_TYPE => C_AP_IARG_FORMAT_TYPE,
C_AP_IARG_FORMAT_FACTOR => C_AP_IARG_FORMAT_FACTOR,
C_AP_IARG_FORMAT_DIM => C_AP_IARG_FORMAT_DIM,
--
C_M_AXIS_TDATA_WIDTH => C_M_AXIS_TDATA_WIDTH,
C_M_AXIS_TUSER_WIDTH => C_M_AXIS_TUSER_WIDTH,
C_M_AXIS_TID_WIDTH => C_M_AXIS_TID_WIDTH,
C_M_AXIS_TDEST_WIDTH => C_M_AXIS_TDEST_WIDTH,
--
C_AP_OARG_TYPE => C_AP_OARG_TYPE,
C_AP_OARG_DWIDTH => C_AP_OARG_DWIDTH,
C_AP_OARG_MB_DEPTH => C_AP_OARG_MB_DEPTH,
--
C_AP_OARG_WIDTH => C_AP_OARG_WIDTH,
C_AP_OARG_N_DIM => C_AP_OARG_N_DIM,
C_AP_OARG_DIM => C_AP_OARG_DIM,
C_AP_OARG_DIM_1 => C_AP_OARG_DIM_1,
C_AP_OARG_DIM_2 => C_AP_OARG_DIM_2,
C_AP_OARG_FORMAT_TYPE => C_AP_OARG_FORMAT_TYPE,
C_AP_OARG_FORMAT_FACTOR => C_AP_OARG_FORMAT_FACTOR,
C_AP_OARG_FORMAT_DIM => C_AP_OARG_FORMAT_DIM,
--
C_N_INOUT_SCALARS => C_N_INOUT_SCALARS,
C_N_INPUT_SCALARS => C_N_INPUT_SCALARS,
C_INPUT_SCALAR_DWIDTH => C_INPUT_SCALAR_DWIDTH,
C_AP_ISCALAR_DOUT_WIDTH => C_AP_ISCALAR_DOUT_WIDTH,
C_INPUT_SCALAR_MODE => C_INPUT_SCALAR_MODE,
--
C_OUTPUT_SCALAR_MODE => C_OUTPUT_SCALAR_MODE,
C_N_OUTPUT_SCALARS => C_N_OUTPUT_SCALARS,
C_OUTPUT_SCALAR_DWIDTH => C_OUTPUT_SCALAR_DWIDTH,
C_AP_OSCALAR_DIN_WIDTH => C_AP_OSCALAR_DIN_WIDTH,
C_AP_ISCALAR_IO_DOUT_WIDTH => C_AP_ISCALAR_IO_DOUT_WIDTH,
C_AP_OSCALAR_IO_DIN_WIDTH => C_AP_OSCALAR_IO_DIN_WIDTH)
port map (
-- SLAVE AXI LITE:
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
--- Slave AXI streams (input arguments)
s_axis_aclk => s_axis_aclk_i,
s_axis_aresetn => s_axis_aresetn_i,
s_axis_tvalid => s_axis_tvalid,
s_axis_tready => s_axis_tready,
s_axis_tdata => s_axis_tdata,
s_axis_tstrb => s_axis_tstrb,
s_axis_tkeep => s_axis_tkeep,
s_axis_tlast => s_axis_tlast,
s_axis_tid => s_axis_tid,
s_axis_tdest => s_axis_tdest,
s_axis_tuser => s_axis_tuser,
--- AP input arguments
ap_iarg_addr => ap_iarg_addr,
ap_iarg_ce => ap_iarg_ce,
ap_iarg_we => ap_iarg_we,
ap_iarg_din => ap_iarg_din,
ap_iarg_dout => ap_iarg_dout,
---
ap_fifo_iarg_dout => ap_fifo_iarg_dout,
ap_fifo_iarg_read => ap_fifo_iarg_read,
ap_fifo_iarg_empty_n => ap_fifo_iarg_empty_n,
--- Master AXI streams (output arguments)
m_axis_aclk => m_axis_aclk_i,
m_axis_aresetn => m_axis_aresetn_i,
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => m_axis_tready,
m_axis_tdata => m_axis_tdata,
m_axis_tstrb => m_axis_tstrb,
m_axis_tkeep => m_axis_tkeep,
m_axis_tlast => m_axis_tlast,
m_axis_tid => m_axis_tid,
m_axis_tdest => m_axis_tdest,
m_axis_tuser => m_axis_tuser,
--- AP output arguments
ap_oarg_addr => ap_oarg_addr,
ap_oarg_ce => ap_oarg_ce,
ap_oarg_we => ap_oarg_we,
ap_oarg_din => ap_oarg_din,
ap_oarg_dout => ap_oarg_dout,
---
ap_fifo_oarg_din => ap_fifo_oarg_din,
ap_fifo_oarg_write => ap_fifo_oarg_write,
ap_fifo_oarg_full_n => ap_fifo_oarg_full_n,
---
ap_clk => aclk,
ap_rst => aresetn,
-- AP control handshaking:
ap_start => ap_start,
ap_ready => ap_ready,
ap_done => ap_done,
ap_continue => ap_continue,
ap_idle => ap_idle,
---
ap_iscalar_dout => ap_iscalar_dout_i,
ap_oscalar_din => ap_oscalar_din_i,
ap_oscalar_vld => ap_oscalar_vld_i,
ap_oscalar_ack => ap_oscalar_ack_i,
ap_iscalar_vld => ap_iscalar_vld_i,
ap_iscalar_ack => ap_iscalar_ack_i,
---
interrupt => interrupt);
end rtl;
|
mit
|
agural/FPGA-Oscilloscope
|
osc/fifo.vhd
|
1
|
7424
|
-- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: dcfifo
-- ============================================================
-- File Name: fifo.vhd
-- Megafunction Name(s):
-- dcfifo
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY fifo IS
PORT
(
aclr : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
wrfull : OUT STD_LOGIC ;
wrusedw : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END fifo;
ARCHITECTURE SYN OF fifo IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (23 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (8 DOWNTO 0);
COMPONENT dcfifo
GENERIC (
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
rdsync_delaypipe : NATURAL;
read_aclr_synch : STRING;
underflow_checking : STRING;
use_eab : STRING;
write_aclr_synch : STRING;
wrsync_delaypipe : NATURAL
);
PORT (
rdclk : IN STD_LOGIC ;
wrfull : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (23 DOWNTO 0);
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
wrusedw : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
aclr : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (23 DOWNTO 0);
rdreq : IN STD_LOGIC
);
END COMPONENT;
BEGIN
wrfull <= sub_wire0;
q <= sub_wire1(23 DOWNTO 0);
wrusedw <= sub_wire2(8 DOWNTO 0);
dcfifo_component : dcfifo
GENERIC MAP (
intended_device_family => "Cyclone III",
lpm_numwords => 512,
lpm_showahead => "OFF",
lpm_type => "dcfifo",
lpm_width => 24,
lpm_widthu => 9,
overflow_checking => "ON",
rdsync_delaypipe => 5,
read_aclr_synch => "OFF",
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "OFF",
wrsync_delaypipe => 5
)
PORT MAP (
rdclk => rdclk,
wrclk => wrclk,
wrreq => wrreq,
aclr => aclr,
data => data,
rdreq => rdreq,
wrfull => sub_wire0,
q => sub_wire1,
wrusedw => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "4"
-- Retrieval info: PRIVATE: Depth NUMERIC "512"
-- Retrieval info: PRIVATE: Empty NUMERIC "1"
-- Retrieval info: PRIVATE: Full NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: Optimize NUMERIC "2"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
-- Retrieval info: PRIVATE: UsedW NUMERIC "1"
-- Retrieval info: PRIVATE: Width NUMERIC "24"
-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
-- Retrieval info: PRIVATE: diff_widths NUMERIC "0"
-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
-- Retrieval info: PRIVATE: output_width NUMERIC "24"
-- Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: rsFull NUMERIC "0"
-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
-- Retrieval info: PRIVATE: wsFull NUMERIC "1"
-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "24"
-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
-- Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
-- Retrieval info: CONSTANT: USE_EAB STRING "ON"
-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
-- Retrieval info: USED_PORT: data 0 0 24 0 INPUT NODEFVAL "data[23..0]"
-- Retrieval info: USED_PORT: q 0 0 24 0 OUTPUT NODEFVAL "q[23..0]"
-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
-- Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
-- Retrieval info: USED_PORT: wrusedw 0 0 9 0 OUTPUT NODEFVAL "wrusedw[8..0]"
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 24 0 data 0 0 24 0
-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 24 0 @q 0 0 24 0
-- Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
-- Retrieval info: CONNECT: wrusedw 0 0 9 0 @wrusedw 0 0 9 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL fifo_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
mit
|
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/proc_sys_reset_v5_0/hdl/src/vhdl/upcnt_n.vhd
|
44
|
7144
|
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- upcnt_n - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: upcnt_n.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/07/01 -- First Release
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SIZE -- Number of bits in counter
--
--
-- Definition of Ports:
-- Data -- parallel data input
-- Cnt_en -- count enable
-- Load -- Load Data
-- Clr -- reset
-- Clk -- Clock
-- Qout -- Count output
--
-------------------------------------------------------------------------------
entity upcnt_n is
generic(
C_SIZE : Integer
);
port(
Data : in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
Cnt_en : in STD_LOGIC;
Load : in STD_LOGIC;
Clr : in STD_LOGIC;
Clk : in STD_LOGIC;
Qout : out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
);
end upcnt_n;
architecture imp of upcnt_n is
constant CLEAR : std_logic := '0';
signal q_int : UNSIGNED (C_SIZE-1 downto 0) := (others => '1');
begin
process(Clk)
begin
if (Clk'event) and Clk = '1' then
-- Clear output register
if (Clr = CLEAR) then
q_int <= (others => '0');
-- Load in start value
elsif (Load = '1') then
q_int <= UNSIGNED(Data);
-- If count enable is high
elsif Cnt_en = '1' then
q_int <= q_int + 1;
end if;
end if;
end process;
Qout <= STD_LOGIC_VECTOR(q_int);
end imp;
|
mit
|
DacHt/CU_Droptest
|
hdl/Backup/WOLF_CONTROLLER_20170528.vhd
|
1
|
6601
|
--------------------------------------------------------------------------------
-- Company: KTH
--
-- File: WOLF_CONTROLLER.vhd
-- File history:
-- v0.1: 2017-04-15: Initial verision for drop test only
--
-- Description:
-- Controller for the REXUS - WOLF exeriment. Handles the statemachine and status communication.
--
-- Backup version:
-- 2017-05-28: D.R: 19:20: First version, light led at 5 sec, turn off led at 10 sec.
--
-- Targeted device: <Family::ProASIC3> <Die::A3P250> <Package::100 VQFP>
-- Author: David Rozenbeek
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity WOLF_CONTROLLER is
port (
---------------------------------------------------
-- Inputs --
---------------------------------------------------
clk_main : IN std_logic; -- Main clock
clk_1hz : IN std_logic; -- 1 Hz clock
reset : IN std_logic; -- Reset (when 1)
rocket_pin : IN std_logic; -- rocket pin if mounted in RMU = 1, ejected = 0
---------------------------------------------------
-- Outputs --
---------------------------------------------------
cutter_en: OUT std_logic -- Cutter Enable (0=Off, 1=On)
);
end WOLF_CONTROLLER;
architecture architecture_WOLF_CONTROLLER of WOLF_CONTROLLER is
--####################### Constants #####################################
constant sec_cutter_enable : integer := 10; -- Seconds cutter should be enabled
constant sec_to_cutter_enable : integer := 5; -- Seconds from ejection to enable cutter.
--####################### Signals #####################################
----------------------------------------------------------------------------------------------------------------------
-- Control signals |Comments --
----------------------------------------------------------------------------------------------------------------------
signal rocket_pin_old : std_logic; --
-----------------------------------------------------------------------------------------------------------------------
-- Mission counter |Comments --
-----------------------------------------------------------------------------------------------------------------------
signal sec_since_eject : unsigned(12 downto 0) := (others => '0'); -- Variable to keep track of seconds since ejection
-----------------------------------------------------------------------------------------------------------------------
-- State Machine Signals |Comments --
-----------------------------------------------------------------------------------------------------------------------
type state is (START, IDLE, EJECTED, CUTTER_ENABLE, CUTTER_DISABLE, SLEEP); -- State declaration
signal current_state : state; -- Current state value
signal next_state : state := START; -- Next clock cycle state value
--################# Architecture Body ###########################
begin
-----------------------------------------------------------------
-- Signal/Port mapping --
-----------------------------------------------------------------
-----------------------------------------------------------------
-- Mission counter --
-- Description: --
-- Keeps track of seconds since ejected, counts up to --
-- 2^12 = 4096 seconds (68,3 min) and then overflows back to 0.--
-----------------------------------------------------------------
mission_counter: process(clk_1hz, rocket_pin, reset)
begin
if ( reset = '1' ) then
sec_since_eject <= (others => '0');
else
if ( rising_edge(clk_1hz) ) then
sec_since_eject <= sec_since_eject + 1;
end if;
end if;
end process;
-----------------------------------------------------------------
-- Main State Machine --
-- Description: --
-- Makes transitions betweens states --
-----------------------------------------------------------------
main_state_machine : process(clk_main, reset, sec_since_eject, current_state, clk_1hz)
begin
rocket_pin_old <= rocket_pin;
if(reset = '1') then
rocket_pin_old <= '0';
cutter_en <= '0';
current_state <= START;
elsif(rising_edge(clk_main)) then
current_state <= next_state;
case current_state is
-- Starting state
when START =>
rocket_pin_old <= '0';
cutter_en <= '0';
next_state <= IDLE;
-- IDLE state
when IDLE =>
-- if ('1') then --rocket_pin = '0' AND rocket_pin_old = '0') then
next_state <= EJECTED;
--else
-- next_state <= current_state;
--end if;
when EJECTED =>
-- Enable cutter after "sec_to_cutter_enable" from reset
if (sec_since_eject >= To_unsigned(sec_to_cutter_enable, sec_since_eject'length)) then
next_state <= CUTTER_ENABLE;
else
next_state <= current_state;
end if;
-- Enable cutter
when CUTTER_ENABLE =>
cutter_en <= '1';
next_state <= CUTTER_DISABLE;
--Disable cutter
when CUTTER_DISABLE =>
-- Disable cutter after "sec_to_cutter_disable" from reset
if (sec_since_eject >= To_unsigned(sec_cutter_enable, sec_since_eject'length)) then
cutter_en <= '0';
next_state <= SLEEP;
else
next_state <= current_state;
end if;
-- SLEEP state, do nothing
when SLEEP =>
next_state <= current_state;
-- Default go back to start
when others =>
next_state <= START;
end case;
end if;
end process main_state_machine;
end architecture_WOLF_CONTROLLER;
|
mit
|
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axis_accelerator_adapter_v2_1/hdl/src/vhdl/xd_s2m_adapter.vhd
|
1
|
12386
|
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : xd_s2m_adapter.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2013-10-25
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-- 2013-10-25 2.0 pvk Added support for UltraScale primitives.
-------------------------------------------------------------------------------
-- ****************************************************************************
--
-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- ****************************************************************************
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
use axis_accelerator_adapter_v2_1_6.xd_s2m_converter;
use axis_accelerator_adapter_v2_1_6.xd_s2m_memory_dc;
use axis_accelerator_adapter_v2_1_6.srl_fifo_32_wt;
entity xd_s2m_adapter is
generic (
-- System generics:
C_FAMILY : string := "virtex7";
C_MTBF_STAGES : integer;
C_BRAM_TYPE : string := "7_SERIES"; -- 7_SERIES = RAMB36E1. ULTRASCALE = RAMB36E2
C_S_AXIS_TDATA_WIDTH : integer;
C_S_AXIS_TUSER_WIDTH : integer;
C_S_AXIS_TID_WIDTH : integer;
C_S_AXIS_TDEST_WIDTH : integer;
C_AP_ARG_DATA_WIDTH : integer;
C_AP_ARG_ADDR_WIDTH : integer;
C_MULTIBUFFER_DEPTH : integer;
C_AP_ARG_WIDTH : integer;
C_AP_ARG_N_DIM : integer;
C_AP_ARG_DIM_1 : integer;
C_AP_ARG_DIM_2 : integer;
C_AP_ARG_FORMAT_TYPE : integer;
C_AP_ARG_FORMAT_FACTOR : integer;
C_AP_ARG_FORMAT_DIM : integer;
C_EXTRA_SYNCS : integer);
port (
-- Input streams
S_AXIS_ACLK : in std_logic;
S_AXIS_ARESETN : in std_logic;
S_AXIS_TVALID : in std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_TDATA : in std_logic_vector(C_S_AXIS_TDATA_WIDTH-1 downto 0);
S_AXIS_TSTRB : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0);
S_AXIS_TKEEP : in std_logic_vector(C_S_AXIS_TDATA_WIDTH/8-1 downto 0);
S_AXIS_TLAST : in std_logic;
S_AXIS_TID : in std_logic_vector(C_S_AXIS_TID_WIDTH-1 downto 0);
S_AXIS_TDEST : in std_logic_vector(C_S_AXIS_TDEST_WIDTH-1 downto 0);
S_AXIS_TUSER : in std_logic_vector(C_S_AXIS_TUSER_WIDTH-1 downto 0);
dbg_stream_nwords : out std_logic_vector(15 downto 0);
dbg_buffer_nwords : out std_logic_vector(15 downto 0);
dbg_ap_start : in std_logic;
ap_clk : in std_logic;
ap_rst_sync : in std_logic;
ap_rst : in std_logic;
ap_arg_addr : in std_logic_vector(C_AP_ARG_ADDR_WIDTH-1 downto 0);
ap_arg_ce : in std_logic;
ap_arg_we : in std_logic;
ap_arg_din : in std_logic_vector(C_AP_ARG_DATA_WIDTH-1 downto 0);
ap_arg_dout : out std_logic_vector(C_AP_ARG_DATA_WIDTH-1 downto 0);
mb_arg_rdy : out std_logic;
mb_arg_done : in std_logic;
status_empty : out std_logic;
status_full : out std_logic;
status_used : out std_logic_vector(3 downto 0)); -- Number of used buffers
end entity;
architecture rtl of xd_s2m_adapter is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of rtl : architecture is "yes";
signal axi_rst : std_logic;
signal axi_rst1 : std_logic;
signal axi_rst2 : std_logic;
function calc_axi_addr_width return integer is
variable addr_width : integer := 0;
begin
if (C_S_AXIS_TDATA_WIDTH > C_AP_ARG_DATA_WIDTH) then
addr_width := C_AP_ARG_ADDR_WIDTH-log2(C_S_AXIS_TDATA_WIDTH/C_AP_ARG_DATA_WIDTH);
else
addr_width := C_AP_ARG_ADDR_WIDTH+log2(C_AP_ARG_DATA_WIDTH/C_S_AXIS_TDATA_WIDTH);
end if;
return addr_width;
end function calc_axi_addr_width;
constant AXI_DATA_WIDTH : integer := C_S_AXIS_TDATA_WIDTH;
constant AXI_ADDR_WIDTH : integer := calc_axi_addr_width;
signal ap_rst_vec : std_logic_vector(0 downto 0);
-- signal ap_rst_sync : std_logic;
-- signal ap_rst_sync1 : std_logic;
signal axisn_rst : std_logic;
signal conv_addr : std_logic_vector(AXI_ADDR_WIDTH-1 downto 0);
signal conv_ce : std_logic;
signal conv_we : std_logic;
signal conv_last : std_logic;
signal conv_rdy : std_logic;
signal conv_data : std_logic_vector(AXI_DATA_WIDTH-1 downto 0);
-- Control for number of words receided in the stream
signal last_conv_addr_vld : std_logic;
signal stream_nwords : unsigned(AXI_ADDR_WIDTH downto 0);
signal stream_nwords_vld : std_logic;
signal buffer_nwords : std_logic_vector(AXI_ADDR_WIDTH downto 0);
signal buffer_nwords_vld : std_logic;
signal buffer_nwords_rdy : std_logic;
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF axi_rst : SIGNAL IS "true";
ATTRIBUTE async_reg OF axi_rst1 : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF ap_rst_sync1 : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF ap_rst_sync : SIGNAL IS "true";
begin
-- undriven ports
dbg_stream_nwords <= (others => '0');
dbg_buffer_nwords <= (others => '0');
-- core reset generation
-- prd1: PROCESS (S_AXIS_ACLK, ap_rst)
-- BEGIN
-- -- Register Stage #1
-- IF (ap_rst = '1') THEN
-- ap_rst_sync1 <= '1';
-- ap_rst_sync <= '1';
-- ELSIF (S_AXIS_ACLK'event and S_AXIS_ACLK = '1') THEN
-- ap_rst_sync1 <= '0';
-- ap_rst_sync <= ap_rst_sync1;
-- END IF;
-- END PROCESS prd1;
axi_rst2 <= not(S_AXIS_ARESETN) or ap_rst_sync;
prd2: PROCESS (S_AXIS_ACLK, axi_rst2)
BEGIN
-- Register Stage #1
IF (axi_rst2 = '1') THEN
axi_rst1 <= '1';
axi_rst <= '1';
ELSIF (S_AXIS_ACLK'event and S_AXIS_ACLK = '1') THEN
axi_rst1 <= '0';
axi_rst <= axi_rst1;
END IF;
END PROCESS prd2;
CONVERTER_I : entity axis_accelerator_adapter_v2_1_6.xd_s2m_converter
generic map (
C_FAMILY => C_FAMILY,
AXI_DATA_WIDTH => AXI_DATA_WIDTH,
AXI_ADDR_WIDTH => AXI_ADDR_WIDTH,
C_EXTRA_SYNCS => C_EXTRA_SYNCS)
port map (
axi_clk => S_AXIS_ACLK,
axi_rst => axi_rst,
axis_vld => S_AXIS_TVALID,
axis_rdy => S_AXIS_TREADY,
axis_last => S_AXIS_TLAST,
axis_keep => S_AXIS_TKEEP,
axis_data => S_AXIS_TDATA,
conv_addr => conv_addr,
conv_ce => conv_ce,
conv_we => conv_we,
conv_last => conv_last,
conv_rdy => conv_rdy,
conv_data => conv_data);
MEM_CTRL_I : entity axis_accelerator_adapter_v2_1_6.xd_s2m_memory_dc
generic map (
-- System generics:
C_FAMILY => C_FAMILY,
C_MTBF_STAGES => C_MTBF_STAGES,
C_BRAM_TYPE => C_BRAM_TYPE,
CONV_DATA_WIDTH => AXI_DATA_WIDTH,
CONV_ADDR_WIDTH => AXI_ADDR_WIDTH,
C_AP_ARG_WIDTH => C_AP_ARG_WIDTH,
C_AP_ARG_N_DIM => C_AP_ARG_N_DIM,
C_AP_ARG_DIM_1 => C_AP_ARG_DIM_1,
C_AP_ARG_DIM_2 => C_AP_ARG_DIM_2,
C_AP_ARG_FORMAT_TYPE => C_AP_ARG_FORMAT_TYPE,
C_AP_ARG_FORMAT_FACTOR => C_AP_ARG_FORMAT_FACTOR,
C_AP_ARG_FORMAT_DIM => C_AP_ARG_FORMAT_DIM,
C_AP_ARG_DATA_WIDTH => C_AP_ARG_DATA_WIDTH,
C_AP_ARG_ADDR_WIDTH => C_AP_ARG_ADDR_WIDTH,
C_MULTIBUFFER_DEPTH => C_MULTIBUFFER_DEPTH,
C_EXTRA_SYNCS => C_EXTRA_SYNCS)
port map (
clk => S_AXIS_ACLK,
rst => axi_rst,
conv_addr => conv_addr,
conv_ce => conv_ce,
conv_we => conv_we,
conv_last => conv_last,
conv_rdy => conv_rdy,
conv_data => conv_data,
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_arg_addr => ap_arg_addr,
ap_arg_ce => ap_arg_ce,
ap_arg_we => ap_arg_we,
ap_arg_din => ap_arg_din,
ap_arg_dout => ap_arg_dout,
mb_arg_rdy => mb_arg_rdy,
mb_arg_done => mb_arg_done,
status_empty => status_empty,
status_full => status_full,
status_used => status_used);
---------------------------
-- The following logic is used for debugging purposes (provide number of
-- words received in the axi_stream. TODO: design not finished.
last_conv_addr_vld <= conv_ce and conv_rdy and conv_last;
process(S_AXIS_ACLK)
begin
if (S_AXIS_ACLK'event and S_AXIS_ACLK = '1') then
if(last_conv_addr_vld = '1') then
stream_nwords <= unsigned('0' & conv_addr) + 1;
end if;
end if;
end process;
process(S_AXIS_ACLK, axi_rst)
begin
if (axi_rst = '1') then
stream_nwords_vld <= '0';
elsif (S_AXIS_ACLK'event and S_AXIS_ACLK = '1') then
stream_nwords_vld <= last_conv_addr_vld;
end if;
end process;
NWORDS_FIFO_I : entity axis_accelerator_adapter_v2_1_6.srl_fifo_32_wt
generic map (
C_FAMILY => C_FAMILY,
WIDTH => AXI_ADDR_WIDTH+1)
port map (
rst => axi_rst,
clk => S_AXIS_ACLK,
din => std_logic_vector(stream_nwords),
din_vld => stream_nwords_vld,
din_rdy => open,
dout => buffer_nwords,
dout_vld => buffer_nwords_vld,
dout_rdy => buffer_nwords_rdy);
buffer_nwords_rdy <= '0';
end rtl;
|
mit
|
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/proc_sys_reset_v5_0/hdl/src/vhdl/proc_sys_reset.vhd
|
6
|
22296
|
-------------------------------------------------------------------------------
-- proc_sys_reset - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: rolandp
-- History:
-- kc 11/07/01 -- First version
--
-- kc 02/25/2002 -- Changed generic names C_EXT_RST_ACTIVE to
-- C_EXT_RESET_HIGH and C_AUX_RST_ACTIVE to
-- C_AUX_RESET_HIGH to match generics used in
-- MicroBlaze. Added the DCM Lock as an input
-- to keep reset active until after the Lock
-- is valid.
-- lcw 10/11/2004 -- Updated for NCSim
-- Ravi 09/14/2006 -- Added Attributes for synthesis
-- rolandp 04/16/2007 -- version 2.00a
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-- ~~~~~~~
-- SK 05/12/11
-- ^^^^^^^
-- 1. Updated the core so remove the support for PPC related functionality.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_8;
use proc_sys_reset_v5_0_8.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting
-- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting
-- C_EXT_RESET_HIGH -- External Reset Active High or Active Low
-- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low
-- C_NUM_BUS_RST -- Number of Bus Structures reset to generate
-- C_NUM_PERP_RST -- Number of Peripheral resets to generate
--
-- C_NUM_INTERCONNECT_ARESETN -- No. of Active low reset to interconnect
-- C_NUM_PERP_ARESETN -- No. of Active low reset to peripheral
-- Definition of Ports:
-- slowest_sync_clk -- Clock
-- ext_reset_in -- External Reset Input
-- aux_reset_in -- Auxiliary Reset Input
-- mb_debug_sys_rst -- MDM Reset Input
-- dcm_locked -- DCM Locked, hold system in reset until 1
-- mb_reset -- MB core reset out
-- bus_struct_reset -- Bus structure reset out
-- peripheral_reset -- Peripheral reset out
-- interconnect_aresetn -- Interconnect Bus structure registered rst out
-- peripheral_aresetn -- Active Low Peripheral registered reset out
-------------------------------------------------------------------------------
entity proc_sys_reset is
generic (
C_FAMILY : string := "virtex7";
C_EXT_RST_WIDTH : integer := 4;
C_AUX_RST_WIDTH : integer := 4;
C_EXT_RESET_HIGH : std_logic := '0'; -- High active input
C_AUX_RESET_HIGH : std_logic := '1'; -- High active input
C_NUM_BUS_RST : integer := 1;
C_NUM_PERP_RST : integer := 1;
C_NUM_INTERCONNECT_ARESETN : integer := 1; -- 3/15/2010
C_NUM_PERP_ARESETN : integer := 1 -- 3/15/2010
);
port (
slowest_sync_clk : in std_logic;
ext_reset_in : in std_logic;
aux_reset_in : in std_logic;
-- from MDM
mb_debug_sys_rst : in std_logic;
-- DCM locked information
dcm_locked : in std_logic := '1';
-- -- from PPC
-- Core_Reset_Req_0 : in std_logic;
-- Chip_Reset_Req_0 : in std_logic;
-- System_Reset_Req_0 : in std_logic;
-- Core_Reset_Req_1 : in std_logic;
-- Chip_Reset_Req_1 : in std_logic;
-- System_Reset_Req_1 : in std_logic;
-- RstcPPCresetcore_0 : out std_logic := '0';
-- RstcPPCresetchip_0 : out std_logic := '0';
-- RstcPPCresetsys_0 : out std_logic := '0';
-- RstcPPCresetcore_1 : out std_logic := '0';
-- RstcPPCresetchip_1 : out std_logic := '0';
-- RstcPPCresetsys_1 : out std_logic := '0';
-- to Microblaze active high reset
mb_reset : out std_logic := '0';
-- active high resets
bus_struct_reset : out std_logic_vector(0 to C_NUM_BUS_RST - 1)
:= (others => '0');
peripheral_reset : out std_logic_vector(0 to C_NUM_PERP_RST - 1)
:= (others => '0');
-- active low resets
interconnect_aresetn : out
std_logic_vector(0 to (C_NUM_INTERCONNECT_ARESETN-1))
:= (others => '1');
peripheral_aresetn : out std_logic_vector(0 to (C_NUM_PERP_ARESETN-1))
:= (others => '1')
);
end entity proc_sys_reset;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of proc_sys_reset is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-- signal Core_Reset_Req_0_d1 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_0_d2 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_0_d3 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d1 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d2 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d3 : std_logic := '0'; -- delayed Core_Reset_Req
signal core_cnt_en_0 : std_logic := '0'; -- Core_Reset_Req_0 counter enable
signal core_cnt_en_1 : std_logic := '0'; -- Core_Reset_Req_1 counter enable
signal core_req_edge_0 : std_logic := '1'; -- Rising edge of Core_Reset_Req_0
signal core_req_edge_1 : std_logic := '1'; -- Rising edge of Core_Reset_Req_1
signal core_cnt_0 : std_logic_vector(3 downto 0); -- core counter output
signal core_cnt_1 : std_logic_vector(3 downto 0); -- core counter output
signal lpf_reset : std_logic; -- Low pass filtered ext or aux
--signal Chip_Reset_Req : std_logic := '0';
--signal System_Reset_Req : std_logic := '0';
signal Bsr_out : std_logic;
signal Pr_out : std_logic;
-- signal Core_out : std_logic;
-- signal Chip_out : std_logic;
-- signal Sys_out : std_logic;
signal MB_out : std_logic;
-------------------------------------------------------------------------------
-- Attributes to synthesis
-------------------------------------------------------------------------------
attribute equivalent_register_removal: string;
attribute equivalent_register_removal of bus_struct_reset : signal is "no";
attribute equivalent_register_removal of peripheral_reset : signal is "no";
attribute equivalent_register_removal of interconnect_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_aresetn : signal is "no";
begin
-------------------------------------------------------------------------------
-- ---------------------
-- -- MB_RESET_HIGH_GEN: Generate active high reset for Micro-Blaze
-- ---------------------
-- MB_RESET_HIGH_GEN: if C_INT_RESET_HIGH = 1 generate
-- begin
MB_Reset_PROCESS: process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
mb_reset <= MB_out;
end if;
end process;
-- ----------------------------------------------------------------------------
-- -- This For-generate creates D-Flip Flops for the Bus_Struct_Reset output(s)
-- ----------------------------------------------------------------------------
BSR_OUT_DFF: for i in 0 to (C_NUM_BUS_RST-1) generate
BSR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
bus_struct_reset(i) <= Bsr_out;
end if;
end process;
end generate BSR_OUT_DFF;
-- ---------------------------------------------------------------------------
-- This For-generate creates D-Flip Flops for the Interconnect_aresetn op(s)
-- ---------------------------------------------------------------------------
ACTIVE_LOW_BSR_OUT_DFF: for i in 0 to (C_NUM_INTERCONNECT_ARESETN-1) generate
BSR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
interconnect_aresetn(i) <= not (Bsr_out);
end if;
end process;
end generate ACTIVE_LOW_BSR_OUT_DFF;
-------------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
-- -- This For-generate creates D-Flip Flops for the Peripheral_Reset output(s)
-- ----------------------------------------------------------------------------
PR_OUT_DFF: for i in 0 to (C_NUM_PERP_RST-1) generate
PR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
peripheral_reset(i) <= Pr_out;
end if;
end process;
end generate PR_OUT_DFF;
-- ----------------------------------------------------------------------------
-- This For-generate creates D-Flip Flops for the Peripheral_aresetn op(s)
-- ----------------------------------------------------------------------------
ACTIVE_LOW_PR_OUT_DFF: for i in 0 to (C_NUM_PERP_ARESETN-1) generate
ACTIVE_LOW_PR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
peripheral_aresetn(i) <= not(Pr_out);
end if;
end process;
end generate ACTIVE_LOW_PR_OUT_DFF;
-------------------------------------------------------------------------------
-- This process defines the RstcPPCreset and MB_Reset outputs
-------------------------------------------------------------------------------
-- Rstc_output_PROCESS_0: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- RstcPPCresetcore_0 <= not (core_cnt_0(3) and core_cnt_0(2) and
-- core_cnt_0(1) and core_cnt_0(0))
-- or Core_out;
-- RstcPPCresetchip_0 <= Chip_out;
-- RstcPPCresetsys_0 <= Sys_out;
-- end if;
-- end process;
-- Rstc_output_PROCESS_1: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- RstcPPCresetcore_1 <= not (core_cnt_1(3) and core_cnt_1(2) and
-- core_cnt_1(1) and core_cnt_1(0))
-- or Core_out;
-- RstcPPCresetchip_1 <= Chip_out;
-- RstcPPCresetsys_1 <= Sys_out;
-- end if;
-- end process;
-------------------------------------------------------------------------------
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---- Double register to sync up with slowest_sync_clk
---------------------------------------------------------------------------------
-- DELAY_PROCESS_0: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- core_reset_req_0_d1 <= Core_Reset_Req_0;
-- core_reset_req_0_d2 <= core_reset_req_0_d1;
-- core_reset_req_0_d3 <= core_reset_req_0_d2;
-- end if;
-- end process;
--
-- DELAY_PROCESS_1: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- core_reset_req_1_d1 <= Core_Reset_Req_1;
-- core_reset_req_1_d2 <= core_reset_req_1_d1;
-- core_reset_req_1_d3 <= core_reset_req_1_d2;
-- end if;
-- end process;
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- This instantiates a counter to ensure the Core_Reset_Req_* will genereate a
-- ** -- -- RstcPPCresetcore_* that is a mimimum of 15 clocks
-- ** -- -------------------------------------------------------------------------------
-- ** -- CORE_RESET_0 : entity proc_sys_reset_v5_0_8.UPCNT_N
-- ** -- generic map (C_SIZE => 4)
-- ** -- port map(
-- ** -- Data => "0000", -- in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
-- ** -- Cnt_en => core_cnt_en_0, -- in STD_LOGIC;
-- ** -- Load => '0', -- in STD_LOGIC;
-- ** -- Clr => core_req_edge_0, -- in STD_LOGIC;
-- ** -- Clk => Slowest_sync_clk, -- in STD_LOGIC;
-- ** -- Qout => core_cnt_0 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
-- ** -- );
-- ** --
-- ** -- CORE_RESET_1 : entity proc_sys_reset_v5_0_8.UPCNT_N
-- ** -- generic map (C_SIZE => 4)
-- ** -- port map(
-- ** -- Data => "0000", -- in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
-- ** -- Cnt_en => core_cnt_en_1, -- in STD_LOGIC;
-- ** -- Load => '0', -- in STD_LOGIC;
-- ** -- Clr => core_req_edge_1, -- in STD_LOGIC;
-- ** -- Clk => Slowest_sync_clk, -- in STD_LOGIC;
-- ** -- Qout => core_cnt_1 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
-- ** -- );
-- ** --
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- CORE_RESET_PROCESS
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- This generates the reset pulse and the count enable to core reset counter
-- ** -- --
-- ** -- CORE_RESET_PROCESS_0: process (Slowest_sync_clk)
-- ** -- begin
-- ** -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- ** -- core_cnt_en_0 <= not (core_cnt_0(3) and core_cnt_0(2) and core_cnt_0(1));
-- ** -- --or not core_req_edge_0;
-- ** -- --core_req_edge_0 <= not(Core_Reset_Req_0_d2 and not Core_Reset_Req_0_d3);
-- ** -- end if;
-- ** -- end process;
-- ** --
-- ** -- CORE_RESET_PROCESS_1: process (Slowest_sync_clk)
-- ** -- begin
-- ** -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- ** -- core_cnt_en_1 <= not (core_cnt_1(3) and core_cnt_1(2) and core_cnt_1(1));
-- ** -- --or not core_req_edge_1;
-- ** -- --core_req_edge_1 <= not(Core_Reset_Req_1_d2 and not Core_Reset_Req_1_d3);
-- ** -- end if;
-- ** -- end process;
-------------------------------------------------------------------------------
-- This instantiates a low pass filter to filter both External and Auxiliary
-- Reset Inputs.
-------------------------------------------------------------------------------
EXT_LPF : entity proc_sys_reset_v5_0_8.LPF
generic map (
C_EXT_RST_WIDTH => C_EXT_RST_WIDTH,
C_AUX_RST_WIDTH => C_AUX_RST_WIDTH,
C_EXT_RESET_HIGH => C_EXT_RESET_HIGH,
C_AUX_RESET_HIGH => C_AUX_RESET_HIGH
)
port map(
MB_Debug_Sys_Rst => mb_debug_sys_rst, -- in std_logic
Dcm_locked => dcm_locked, -- in std_logic
External_System_Reset => ext_reset_in, -- in std_logic
Auxiliary_System_Reset => aux_reset_in, -- in std_logic
Slowest_Sync_Clk => slowest_sync_clk, -- in std_logic
Lpf_reset => lpf_reset -- out std_logic
);
-------------------------------------------------------------------------------
-- This instantiates the sequencer
-- This controls the time between resets becoming inactive
-------------------------------------------------------------------------------
-- System_Reset_Req <= System_Reset_Req_0 or System_Reset_Req_1;
-- Chip_Reset_Req <= Chip_Reset_Req_0 or Chip_Reset_Req_1;
SEQ : entity proc_sys_reset_v5_0_8.SEQUENCE_PSR
--generic map (
-- C_EXT_RESET_HIGH_1 => C_EXT_RESET_HIGH
--)
port map(
Lpf_reset => lpf_reset, -- in std_logic
--System_Reset_Req => '0', -- System_Reset_Req, -- in std_logic
--Chip_Reset_Req => '0', -- Chip_Reset_Req, -- in std_logic
Slowest_Sync_Clk => slowest_sync_clk, -- in std_logic
Bsr_out => Bsr_out, -- out std_logic
Pr_out => Pr_out, -- out std_logic
--Core_out => open, -- Core_out, -- out std_logic
--Chip_out => open, -- Chip_out, -- out std_logic
--Sys_out => open, -- Sys_out, -- out std_logic
MB_out => MB_out); -- out std_logic
end imp;
--END_SINGLE_FILE_TAG
|
mit
|
DacHt/CU_Droptest
|
component/work/CU_TOP/FPGA_UART/rtl/vhdl/core/Clock_gen.vhd
|
1
|
12618
|
-- ********************************************************************
-- Actel Corporation Proprietary and Confidential
-- Copyright 2008 Actel Corporation. All rights reserved.
--
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
-- ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
-- IN ADVANCE IN WRITING.
--
-- Description: CoreUART/ CoreUARTapb UART core
--
--
-- Revision Information:
-- Date Description
-- Jun09 Revision 4.1
-- Aug10 Revision 4.2
--
-- SVN Revision Information:
-- SVN $Revision: 8508 $
-- SVN $Date: 2009-06-15 16:49:49 -0700 (Mon, 15 Jun 2009) $
--
-- Resolved SARs
-- SAR Date Who Description
-- 20741 2Sep10 AS Increased baud rate by ensuring fifo ctrl runs off
-- sys clk (not baud clock). See note below.
-- Notes:
-- best viewed with tabstops set to "4"
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
entity CU_TOP_FPGA_UART_Clock_gen is
GENERIC (BAUD_VAL_FRCTN_EN : integer := 0;
SYNC_RESET : integer := 0);
port ( clk : in std_logic; -- system clock
reset_n : in std_logic; -- active low async reset
baud_val : in std_logic_vector(12 downto 0); -- value loaded into cntr
BAUD_VAL_FRACTION : in std_logic_vector(2 downto 0); -- fractional part of baud value
baud_clock : out std_logic; -- 16x baud clock pulse
xmit_pulse : out std_logic -- transmit pulse
);
end entity CU_TOP_FPGA_UART_Clock_gen;
architecture rtl of CU_TOP_FPGA_UART_Clock_gen is
signal baud_cntr : std_logic_vector(12 downto 0); -- 16x clock division counter reg.
signal baud_clock_int : std_logic; -- internal 16x baud clock pulse
signal xmit_clock : std_logic;
signal xmit_cntr : std_logic_vector(3 downto 0); -- baud tx counter reg.
signal baud_cntr_one : std_logic;
signal aresetn : std_logic;
signal sresetn : std_logic;
begin
aresetn <= '1' WHEN (SYNC_RESET=1) ELSE reset_n;
sresetn <= reset_n WHEN (SYNC_RESET=1) ELSE '1';
--------------------------------------------------
-- generate a x16 baud clock pulse
--------------------------------------------------
UG09:IF(BAUD_VAL_FRCTN_EN = 1) GENERATE
-- Add one cycle 1/8, 2/8, 3/8, 4/8, 5/8, 6/8, 7/8 of the time by freezing
-- baud_cntr for one cycle when count reaches 0 for certain xmit_cntr values.
-- xmit_cntr values are identifed by looking for bits of this counter
-- being certain combinations.
make_baud_cntr_one: process(clk,aresetn)
begin
if (aresetn = '0') then
baud_cntr_one <= '0';
elsif(clk'event and clk='1') then
if (sresetn = '0') then
baud_cntr_one <= '0';
else
if (baud_cntr = "0000000000001") then
baud_cntr_one <= '1';
else
baud_cntr_one <= '0';
end if;
end if;
end if;
end process make_baud_cntr_one;
make_baud_cntr1: process(clk, aresetn)
begin
if (aresetn = '0') then
baud_cntr <= "0000000000000";
baud_clock_int <= '0';
elsif(clk'event and clk='1') then
if (sresetn = '0') then
baud_cntr <= "0000000000000";
baud_clock_int <= '0';
else
case BAUD_VAL_FRACTION is
when "000" => if (baud_cntr = "0000000000000") then --0
baud_cntr <= baud_val;
baud_clock_int <= '1';
else
baud_cntr <= baud_cntr - '1';
baud_clock_int <= '0';
end if;
when "001" => if (baud_cntr = "0000000000000") then
if (xmit_cntr(2 downto 0) = "111" and baud_cntr_one = '1') then --0.125
baud_cntr <= baud_cntr;
baud_clock_int <= '0';
else
baud_cntr <= baud_val;
baud_clock_int <= '1';
end if;
else
baud_cntr <= baud_cntr - '1';
baud_clock_int <= '0';
end if;
when "010" => if (baud_cntr = "0000000000000") then
if (xmit_cntr(1 downto 0) = "11" and baud_cntr_one = '1') then --0.25
baud_cntr <= baud_cntr;
baud_clock_int <= '0';
else
baud_cntr <= baud_val;
baud_clock_int <= '1';
end if;
else
baud_cntr <= baud_cntr - '1';
baud_clock_int <= '0';
end if;
when "011" => if (baud_cntr = "0000000000000") then
if ((((xmit_cntr(2) = '1') or (xmit_cntr(1) = '1')) and xmit_cntr(0) ='1') and (baud_cntr_one = '1')) then --0.375
baud_cntr <= baud_cntr;
baud_clock_int <= '0';
else
baud_cntr <= baud_val;
baud_clock_int <= '1';
end if;
else
baud_cntr <= baud_cntr - '1';
baud_clock_int <= '0';
end if;
when "100" => if (baud_cntr = "0000000000000") then
if (xmit_cntr(0) = '1' and baud_cntr_one = '1') then --0.5
baud_cntr <= baud_cntr;
baud_clock_int <= '0';
else
baud_cntr <= baud_val;
baud_clock_int <= '1';
end if;
else
baud_cntr <= baud_cntr - '1';
baud_clock_int <= '0';
end if;
when "101" => if (baud_cntr = "0000000000000") then
if (((xmit_cntr(2) = '1' and xmit_cntr(1) = '1') or xmit_cntr(0) = '1') and baud_cntr_one = '1') then --0.625
baud_cntr <= baud_cntr;
baud_clock_int <= '0';
else
baud_cntr <= baud_val;
baud_clock_int <= '1';
end if;
else
baud_cntr <= baud_cntr - '1';
baud_clock_int <= '0';
end if;
when "110" => if (baud_cntr = "0000000000000") then
if ((xmit_cntr(1) = '1' or xmit_cntr(0) = '1') and baud_cntr_one = '1') then -- 0.75
baud_cntr <= baud_cntr;
baud_clock_int <= '0';
else
baud_cntr <= baud_val;
baud_clock_int <= '1';
end if;
else
baud_cntr <= baud_cntr - '1';
baud_clock_int <= '0';
end if;
when "111" => if (baud_cntr = "0000000000000") then
if (((xmit_cntr(1) = '1' or xmit_cntr(0) = '1') or xmit_cntr(2 downto 0) = "100") and baud_cntr_one = '1') then -- 0.875
baud_cntr <= baud_cntr;
baud_clock_int <= '0';
else
baud_cntr <= baud_val;
baud_clock_int <= '1';
end if;
else
baud_cntr <= baud_cntr - '1';
baud_clock_int <= '0';
end if;
when others => if (baud_cntr = "0000000000000") then --0
baud_cntr <= baud_val;
baud_clock_int <= '1';
else
baud_cntr <= baud_cntr - '1';
baud_clock_int <= '0';
end if;
end case;
end if;
end if;
end process make_baud_cntr1;
END GENERATE;
UG10:IF(BAUD_VAL_FRCTN_EN= 0) GENERATE
make_baud_cntr2:process(clk,aresetn)
begin
if (aresetn = '0') then
baud_cntr <= "0000000000000";
baud_clock_int <= '0';
elsif(clk'event and clk='1') then
if (sresetn = '0') then
baud_cntr <= "0000000000000";
baud_clock_int <= '0';
else
if (baud_cntr = "0000000000000") then
baud_cntr <= baud_val;
baud_clock_int <= '1';
else
baud_cntr <= baud_cntr - '1';
baud_clock_int <= '0';
end if;
end if;
end if;
end process make_baud_cntr2;
END GENERATE;
--baud_clock_int <= '1' when baud_cntr = "00000000" else
-- '0';
----------------------------------------------------
-- generate a transmit clock pulse
----------------------------------------------------
make_xmit_clock: process(clk,aresetn)
begin
if(aresetn = '0') then
xmit_cntr <= "0000";
xmit_clock <= '0';
elsif(clk'event and clk='1') then
if(sresetn = '0') then
xmit_cntr <= "0000";
xmit_clock <= '0';
else
if(baud_clock_int = '1') then
xmit_cntr <= xmit_cntr + '1';
if(xmit_cntr = "1111") then
xmit_clock <= '1';
else
xmit_clock <= '0';
end if;
end if;
end if;
end if;
end process;
xmit_pulse <= xmit_clock and baud_clock_int;
baud_clock <= baud_clock_int;
end rtl;
|
mit
|
DacHt/CU_Droptest
|
component/work/CU_TOP/FPGA_UART/coreparameters.vhd
|
1
|
740
|
----------------------------------------------------------------------
-- Created by Microsemi SmartDesign Thu Jun 22 17:22:48 2017
-- Parameters for COREUART
----------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
package coreparameters is
constant BAUD_VAL_FRCTN_EN : integer := 1;
constant FAMILY : integer := 15;
constant HDL_license : string( 1 to 1 ) := "U";
constant RX_FIFO : integer := 0;
constant RX_LEGACY_MODE : integer := 0;
constant testbench : string( 1 to 4 ) := "User";
constant TX_FIFO : integer := 0;
constant USE_SOFT_FIFO : integer := 0;
end coreparameters;
|
mit
|
agural/FPGA-Oscilloscope
|
osc/vramctrl/lpm_counter2.vhd
|
2
|
4645
|
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COUNTER
-- ============================================================
-- File Name: lpm_counter2.vhd
-- Megafunction Name(s):
-- LPM_COUNTER
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_counter2 IS
PORT
(
clock : IN STD_LOGIC ;
cnt_en : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
);
END lpm_counter2;
ARCHITECTURE SYN OF lpm_counter2 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (9 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_modulus : NATURAL;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
cnt_en : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
sclr : IN STD_LOGIC
);
END COMPONENT;
BEGIN
q <= sub_wire0(9 DOWNTO 0);
LPM_COUNTER_component : LPM_COUNTER
GENERIC MAP (
lpm_direction => "UP",
lpm_modulus => 525,
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 10
)
PORT MAP (
clock => clock,
cnt_en => cnt_en,
sclr => sclr,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "1"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "1"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "525"
-- Retrieval info: PRIVATE: SCLR NUMERIC "1"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "10"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "525"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "10"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
-- Retrieval info: USED_PORT: cnt_en 0 0 0 0 INPUT NODEFVAL "cnt_en"
-- Retrieval info: USED_PORT: q 0 0 10 0 OUTPUT NODEFVAL "q[9..0]"
-- Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @cnt_en 0 0 0 0 cnt_en 0 0 0 0
-- Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 10 0 @q 0 0 10 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter2.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter2.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter2_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
chris-wood/yield
|
sdsoc/hash/SDDebug/_sds/p0/ipi/zc702.srcs/sources_1/bd/zc702/ipshared/xilinx.com/axis_accelerator_adapter_v2_1/hdl/src/vhdl/synchronizer_ff.vhd
|
1
|
4646
|
-------------------------------------------------------------------------------
-- $Id: synchronizer_ff.vhd,v 1.1 2011/06/02 09:44:03 robertb Exp $
-- Title : Binary Counter Module for Write Logic
-- Project : FIFO Generator
-------------------------------------------------------------------------------
-- (c) Copyright 2006 - 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- File : synchronizer_ff.vhd
-- Author : Xilinx
-------------------------------------------------------------------------------
-- Structure:
-- synchronizer_ff.vhd
--
-------------------------------------------------------------------------------
-- Description:
-- A basic Flip Flop with asynchronous reset
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
ENTITY synchronizer_ff IS
GENERIC (
C_HAS_RST : integer := 0;
C_WIDTH : integer := 0
);
PORT (
RST : IN std_logic := '0' ;
CLK : IN std_logic := '0' ;
D : IN std_logic_vector(C_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
Q : OUT std_logic_vector(C_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END synchronizer_ff;
ARCHITECTURE xilinx OF synchronizer_ff IS
ATTRIBUTE DowngradeIPIdentifiedWarnings: STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF xilinx : ARCHITECTURE IS "yes";
signal Q_reg : std_logic_vector(C_WIDTH-1 downto 0) := (OTHERS => '0');
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF Q_reg : SIGNAL IS "true";
ATTRIBUTE msgon : STRING;
ATTRIBUTE msgon OF Q_reg : SIGNAL IS "true";
-- attribute dont_touch : string;
-- attribute dont_touch of Q_reg : signal is "true";
-- ATTRIBUTE KEEP_HIERARCHY : STRING;
-- ATTRIBUTE KEEP_HIERARCHY of xilinx : ARCHITECTURE IS "yes";
BEGIN
PROCESS (CLK, RST)
BEGIN
IF (RST = '1' AND C_HAS_RST = 1) THEN
Q_reg <= (OTHERS => '0');
-- Q <= (OTHERS => '0');
ELSIF CLK'EVENT AND CLK = '1' THEN
Q_reg <= D AFTER TFF;
-- Q <= D AFTER TFF;
END IF;
END PROCESS;
Q <= Q_reg;
END xilinx;
|
mit
|
SteelRaven7/soundbox-vhdl
|
Source/Generic Filters/Generic_IIR_Debugger.vhd
|
1
|
1886
|
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Description: --
-- --
-- --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity Generic_IIR_Debugger is
port(clk : in std_logic;
reset : in std_logic;
input : in std_logic_vector(15 downto 0);
output : out std_logic_vector(15 downto 0));
end Generic_IIR_Debugger;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
architecture behaviour of Generic_IIR_Debugger is
begin
Generic_IIR : entity work.Generic_IIR
generic map(ORDER => 2,
IN_WIDTH => 16,
IN_FRACT => 11,
B_WIDTH => 16,
B_FRACT => 13,
A_WIDTH => 16,
A_FRACT => 14,
INTERNAL_WIDTH => 24,
INTERNAL_FRACT => 12,
OUT_WIDTH => 16,
OUT_FRACT => 9)
port map(clk => clk,
reset => reset,
x => input,
B => x"2000" &
x"0000" &
x"0000",
A => x"4000" &
x"4000",
y => output);
end architecture;
|
mit
|
SteelRaven7/soundbox-vhdl
|
Source/AudioIO/DAPwm_tb.vhd
|
1
|
2826
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:43:17 02/10/2014
-- Design Name:
-- Module Name: C:/SoundboxProject/Source/soundbox-vhdl/Source/AudioIO/DAPwm_tb.vhd
-- Project Name: SoundboxProject
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: DAPwm
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all ;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY DAPwm_tb IS
END DAPwm_tb;
ARCHITECTURE behavior OF DAPwm_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT DAPwm
PORT(
input : IN std_logic_vector(11 downto 0);
output : OUT std_logic;
clk : IN std_logic;
reset : IN std_logic
);
END COMPONENT;
--Inputs
signal input : std_logic_vector(11 downto 0) := (others => '0');
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal inputNumber : natural := 0;
--Outputs
signal output : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
constant sample_period : time := 40960 ns;
BEGIN
input <= std_logic_vector(to_unsigned(inputNumber, input'high+1));
-- Instantiate the Unit Under Test (UUT)
uut: DAPwm PORT MAP (
input => input,
output => output,
clk => clk,
reset => reset
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1';
wait for 100 ns;
reset <= '0';
wait for clk_period*10;
wait for 20000 ns;
inputNumber <= 5;
wait for sample_period;
inputNumber <= 4095;
wait for sample_period;
inputNumber <= 4094;
wait for sample_period;
inputNumber <= 4095;
wait for sample_period;
inputNumber <= 5;
wait for sample_period;
-- insert stimulus here
wait;
end process;
END;
|
mit
|
SteelRaven7/soundbox-vhdl
|
Source/Decimator/Mult.vhd
|
1
|
755
|
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity Mult is
generic (
wordLengthA : natural := 8;
wordLengthB : natural := 8;
wordLengthP : natural := 16
);
port (
a : in std_logic_vector(wordLengthA-1 downto 0);
b : in std_logic_vector(wordLengthB-1 downto 0);
p : out std_logic_vector(wordLengthP-1 downto 0)
);
end entity ; -- Mult
architecture arch of Mult is
signal product : signed(wordLengthA+wordLengthB-1 downto 0);
signal pEntire : std_logic_vector(wordLengthA+wordLengthB-1 downto 0);
begin
product <= (signed(a)*signed(b));
pEntire <= std_logic_vector(shift_left(product, 1));
p <= pEntire(wordLengthA+wordLengthB-1 downto wordLengthA+wordLengthB-wordLengthP);
end architecture ; -- arch
|
mit
|
SteelRaven7/soundbox-vhdl
|
Source/Decimator/AdderSat.vhd
|
1
|
512
|
-- Does not saturate currently, only provides built in VHDL addition.
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
entity AdderSat is
generic (
wordLength : natural := 12
);
port (
a : in std_logic_vector(wordLength-1 downto 0);
b : in std_logic_vector(wordLength-1 downto 0);
s : out std_logic_vector(wordLength-1 downto 0)
);
end entity ; -- AdderSat
architecture arch of AdderSat is
begin
s <= std_logic_vector(signed(a) + signed(b));
end architecture ; -- arch
|
mit
|
jakubcabal/mig_ddr3_wrapper_virtex6
|
source/testbench.vhd
|
1
|
8541
|
-- The MIT License (MIT)
--
-- Copyright (c) 2016 Jakub Cabal <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
--
-- Website: https://github.com/jakubcabal/mig_ddr3_wrapper_virtex6
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity TESTBENCH is
end TESTBENCH;
--------------------------------------------------------------------------------
-- THIS TESTBENCH REQUIRES DDR3 MODEL FROM XILINX MIG IP CORE!!!
--------------------------------------------------------------------------------
architecture FULL of TESTBENCH is
-- DO NOT CHANGE THESE VALUES!
constant nCS_PER_RANK : integer := 1; -- # of unique CS outputs per Rank for phy.
constant BANK_WIDTH : integer := 3; -- # of memory Bank Address bits.
constant CK_WIDTH : integer := 1; -- # of CK/CK# outputs to memory.
constant CKE_WIDTH : integer := 1; -- # of CKE outputs to memory.
constant CS_WIDTH : integer := 1; -- # of unique CS outputs to memory.
constant DM_WIDTH : integer := 8; -- # of Data Mask bits.
constant DQ_WIDTH : integer := 64; -- # of Data (DQ) bits.
constant DQS_WIDTH : integer := 8; -- # of DQS/DQS# bits.
constant ROW_WIDTH : integer := 14; -- # of memory Row Address bits.
constant MEMORY_WIDTH : integer := 16;
constant NUM_DDR3 : integer := DQ_WIDTH/MEMORY_WIDTH;
constant TPROP_DQS : time := 0 ps; -- Delay for DQS signal during Write Operation
constant TPROP_DQS_RD : time := 0 ps; -- Delay for DQS signal during Read Operation
constant TPROP_PCB_CTRL : time := 0 ps; -- Delay for Address and Ctrl signals
constant TPROP_PCB_DATA : time := 0 ps; -- Delay for data signal during Write operation
constant TPROP_PCB_DATA_RD : time := 0 ps; -- Delay for data signal during Read operation
component ddr3_model
port(
rst_n : in std_logic;
ck : in std_logic;
ck_n : in std_logic;
cke : in std_logic;
cs_n : in std_logic;
ras_n : in std_logic;
cas_n : in std_logic;
we_n : in std_logic;
dm_tdqs : inout std_logic_vector((MEMORY_WIDTH/16) downto 0);
ba : in std_logic_vector(BANK_WIDTH-1 downto 0);
addr : in std_logic_vector(ROW_WIDTH-1 downto 0);
dq : inout std_logic_vector(MEMORY_WIDTH-1 downto 0);
dqs : inout std_logic_vector((MEMORY_WIDTH/16) downto 0);
dqs_n : inout std_logic_vector((MEMORY_WIDTH/16) downto 0);
tdqs_n : out std_logic_vector((MEMORY_WIDTH/16) downto 0);
odt : in std_logic
);
end component ddr3_model;
signal CLK_REF_P : std_logic := '0';
signal CLK_REF_N : std_logic := '1';
signal RST : std_logic := '0';
signal sys_rst_n : std_logic;
signal rx_uart : std_logic := '1';
signal tx_uart : std_logic;
signal ddr3_dq : std_logic_vector(DQ_WIDTH-1 downto 0);
signal ddr3_dm : std_logic_vector(DM_WIDTH-1 downto 0);
signal ddr3_addr : std_logic_vector(ROW_WIDTH-1 downto 0);
signal ddr3_ba : std_logic_vector(BANK_WIDTH-1 downto 0);
signal ddr3_ras_n : std_logic;
signal ddr3_cas_n : std_logic;
signal ddr3_we_n : std_logic;
signal ddr3_reset_n : std_logic;
signal ddr3_cs_n : std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
signal ddr3_odt : std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
signal ddr3_cke : std_logic_vector(CKE_WIDTH-1 downto 0);
signal ddr3_dqs_p : std_logic_vector(DQS_WIDTH-1 downto 0);
signal ddr3_dqs_n : std_logic_vector(DQS_WIDTH-1 downto 0);
signal ddr3_ck_p : std_logic_vector(CK_WIDTH-1 downto 0);
signal ddr3_ck_n : std_logic_vector(CK_WIDTH-1 downto 0);
signal phy_init_done : std_logic;
constant clk_period : time := 5 ns;
constant uart_period : time := 8681 ns;
constant data_value : std_logic_vector(7 downto 0) := X"13";
constant data_value2 : std_logic_vector(7 downto 0) := X"10";
begin
utt: entity work.TOP
generic map(
nCS_PER_RANK => nCS_PER_RANK,
BANK_WIDTH => BANK_WIDTH,
CK_WIDTH => CK_WIDTH,
CKE_WIDTH => CKE_WIDTH,
CS_WIDTH => CS_WIDTH,
DQ_WIDTH => DQ_WIDTH,
DM_WIDTH => DM_WIDTH,
DQS_WIDTH => DQS_WIDTH,
ROW_WIDTH => ROW_WIDTH,
SIM_BYPASS_INIT_CAL => "FAST"
)
port map (
ASYNC_RST => RST,
CLK_REF_P => CLK_REF_P,
CLK_REF_N => CLK_REF_N,
-- UART INTERFACE
UART_TX => tx_uart,
UART_RX => rx_uart,
-- DDR3 INTERFACE
DDR3_DQ => ddr3_dq,
DDR3_DM => ddr3_dm,
DDR3_ADDR => ddr3_addr,
DDR3_BA => ddr3_ba,
DDR3_RAS_N => ddr3_ras_n,
DDR3_CAS_N => ddr3_cas_n,
DDR3_WE_N => ddr3_we_n,
DDR3_RESET_N => ddr3_reset_n,
DDR3_CS_N => ddr3_cs_n,
DDR3_ODT => ddr3_odt,
DDR3_CKE => ddr3_cke,
DDR3_DQS_P => ddr3_dqs_p,
DDR3_DQS_N => ddr3_dqs_n,
DDR3_CK_P => ddr3_ck_p,
DDR3_CK_N => ddr3_ck_n,
PHY_INIT_DONE => phy_init_done
);
-- DDR3 MODEL FROM XILINX MIG IP CORE
gen_ddr3_mem : for i in 0 to NUM_DDR3-1 generate
ddr3_model_i : ddr3_model
port map(
rst_n => ddr3_reset_n,
ck => ddr3_ck_p((i*MEMORY_WIDTH)/72),
ck_n => ddr3_ck_n((i*MEMORY_WIDTH)/72),
cke => ddr3_cke((i*MEMORY_WIDTH)/72),
cs_n => ddr3_cs_n((i*MEMORY_WIDTH)/72),
ras_n => ddr3_ras_n,
cas_n => ddr3_cas_n,
we_n => ddr3_we_n,
dm_tdqs => ddr3_dm((2*(i+1)-1) downto (2*i)),
ba => ddr3_ba,
addr => ddr3_addr,
dq => ddr3_dq(16*(i+1)-1 downto 16*(i)),
dqs => ddr3_dqs_p((2*(i+1)-1) downto (2*i)),
dqs_n => ddr3_dqs_n((2*(i+1)-1) downto (2*i)),
tdqs_n => open,
odt => ddr3_odt((i*MEMORY_WIDTH)/72)
);
end generate;
clk_process : process
begin
CLK_REF_P <= '0';
CLK_REF_N <= '1';
wait for clk_period/2;
CLK_REF_P <= '1';
CLK_REF_N <= '0';
wait for clk_period/2;
end process;
test_rx_uart : process
begin
rx_uart <= '1';
RST <= '1';
wait for 50 ns;
RST <= '0';
wait for uart_period;
rx_uart <= '0'; -- start bit
wait for uart_period;
for i in 0 to 7 loop
rx_uart <= data_value(i); -- data bits
wait for uart_period;
end loop;
rx_uart <= '1'; -- parity bit
wait for uart_period;
rx_uart <= '1'; -- stop bit
wait for uart_period;
wait for 750 ns;
rx_uart <= '0'; -- start bit
wait for uart_period;
for i in 0 to 7 loop
rx_uart <= data_value2(i); -- data bits
wait for uart_period;
end loop;
rx_uart <= '1'; -- parity bit
wait for uart_period;
rx_uart <= '1'; -- stop bit
wait for uart_period;
wait;
end process;
end FULL;
|
mit
|
SteelRaven7/soundbox-vhdl
|
Source/Generic Filters/Equalizer.vhd
|
1
|
16697
|
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Description: --
-- This file describes the implementation of a generic equalizer. This --
-- equaliser is made up out of three second order, direct IIR-filters with --
-- multipliers between. --
-- --
-- --
-- Generic: --
-- DATA_WIDTH - The width of the input data, output data as well --
-- as the data signals between the IIR-filters and --
-- multipliers --
-- DATA_FRACT - The factrional width of above data --
-- --
-- SCALE_WIDTH_1 - Data width of the first scaling factor --
-- SCALE_FRACT_1 - Fractional width of the first scaling factor --
-- SCALE_WIDTH_2 - Data width of the second scaling factor --
-- SCALE_FRACT_2 - Fractional width of the second scaling factor --
-- SCALE_WIDTH_3 - Data width of the third scaling factor --
-- SCALE_FRACT_3 - Fractional width of the third scaling factor --
-- SCALE_WIDTH_4 - Data width of the fourth scaling factor --
-- SCALE_FRACT_4 - Fractional width of the fourth scaling factor --
-- --
-- INTERNAL_IIR_WIDTH_1 - Width of the internal calculations within the --
-- first IIR-filter --
-- INTERNAL_IIR_FRACT_1 - Fractional width of the internal calculations --
-- within the first IIR-filter --
-- INTERNAL_IIR_WIDTH_2 - Width of the internal calculations within the --
-- second IIR-filter --
-- INTERNAL_IIR_FRACT_2 - Fractional width of the internal calculations --
-- within the second IIR-filter --
-- INTERNAL_IIR_WIDTH_3 - Width of the internal calculations within the --
-- third IIR-filter --
-- INTERNAL_IIR_FRACT_3 - Fractional width of the internal calculations --
-- within the third IIR-filter --
-- --
-- COEFF_WIDTH_1 - Width of the coefficients used in the first --
-- IIR-filter --
-- COEFF_FRACT_1 - Fractional width of the coefficients used in the --
-- first IIR-filter --
-- COEFF_WIDTH_2 - Width of the coefficients used in the second --
-- IIR-filter --
-- COEFF_FRACT_2 - Fractional width of the coefficients used in the --
-- second IIR-filter --
-- COEFF_WIDTH_3 - Width of the coefficients used in the third --
-- IIR-filter --
-- COEFF_FRACT_3 - Fractional width of the coefficients used in the --
-- third IIR-filter --
-- --
-- --
-- Input/Output: --
-- clk - System clock --
-- reset - Resets component when high --
-- write_mode - Write new coefficients when high --
-- x - Input --
-- --
-- scale_1 - First scaling factor --
-- scale_2 - Second scaling factor --
-- scale_3 - Third scaling factor --
-- scale_4 - Fourth scaling factor --
-- --
-- b0_1 - B coefficient of the first IIR filter --
-- b1_1 - B coefficient of the first IIR filter --
-- b2_1 - B coefficient of the first IIR filter --
-- a1_1 - A coefficient of the first IIR filter --
-- a2_1 - A coefficient of the first IIR filter --
-- --
-- b0_2 - B coefficient of the second IIR filter --
-- b1_2 - B coefficient of the second IIR filter --
-- b2_2 - B coefficient of the second IIR filter --
-- a1_2 - A coefficient of the second IIR filter --
-- a2_2 - A coefficient of the second IIR filter --
-- --
-- b0_3 - B coefficient of the third IIR filter --
-- b1_3 - B coefficient of the third IIR filter --
-- b2_3 - B coefficient of the third IIR filter --
-- a1_3 - A coefficient of the third IIR filter --
-- a2_3 - A coefficient of the third IIR filter --
-- --
-- y - Output --
-- --
-- --
-- Internal Constants: --
-- N - Number of coefficients, this number is three for a --
-- second order filter and should not be changed. The --
-- constant is mearly there to simplify creation of --
-- higher order filters. Note that for this to be done --
-- successfully, you have to increase the number of --
-- coefficients as well. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
entity Equalizer is
generic (DATA_WIDTH : natural := 8;
DATA_FRACT : natural := 6;
SCALE_WIDTH_1 : natural := 8;
SCALE_FRACT_1 : natural := 6;
SCALE_WIDTH_2 : natural := 8;
SCALE_FRACT_2 : natural := 6;
SCALE_WIDTH_3 : natural := 8;
SCALE_FRACT_3 : natural := 6;
SCALE_WIDTH_4 : natural := 8;
SCALE_FRACT_4 : natural := 6;
INTERNAL_IIR_WIDTH_1 : natural := 12;
INTERNAL_IIR_FRACT_1 : natural := 8;
INTERNAL_IIR_WIDTH_2 : natural := 12;
INTERNAL_IIR_FRACT_2 : natural := 8;
INTERNAL_IIR_WIDTH_3 : natural := 12;
INTERNAL_IIR_FRACT_3 : natural := 8;
COEFF_WIDTH_1 : natural := 8;
COEFF_FRACT_1 : natural := 6;
COEFF_WIDTH_2 : natural := 8;
COEFF_FRACT_2 : natural := 6;
COEFF_WIDTH_3 : natural := 8;
COEFF_FRACT_3 : natural := 6);
port(clk : in std_logic;
reset : in std_logic;
x : in std_logic_vector(DATA_WIDTH-1 downto 0);
scale_1 : in std_logic_vector(SCALE_WIDTH_1-1 downto 0);
scale_2 : in std_logic_vector(SCALE_WIDTH_2-1 downto 0);
scale_3 : in std_logic_vector(SCALE_WIDTH_3-1 downto 0);
scale_4 : in std_logic_vector(SCALE_WIDTH_4-1 downto 0);
b0_1 : in std_logic_vector(COEFF_WIDTH_1-1 downto 0);
b1_1 : in std_logic_vector(COEFF_WIDTH_1-1 downto 0);
b2_1 : in std_logic_vector(COEFF_WIDTH_1-1 downto 0);
a1_1 : in std_logic_vector(COEFF_WIDTH_1-1 downto 0);
a2_1 : in std_logic_vector(COEFF_WIDTH_1-1 downto 0);
b0_2 : in std_logic_vector(COEFF_WIDTH_2-1 downto 0);
b1_2 : in std_logic_vector(COEFF_WIDTH_2-1 downto 0);
b2_2 : in std_logic_vector(COEFF_WIDTH_2-1 downto 0);
a1_2 : in std_logic_vector(COEFF_WIDTH_2-1 downto 0);
a2_2 : in std_logic_vector(COEFF_WIDTH_2-1 downto 0);
b0_3 : in std_logic_vector(COEFF_WIDTH_3-1 downto 0);
b1_3 : in std_logic_vector(COEFF_WIDTH_3-1 downto 0);
b2_3 : in std_logic_vector(COEFF_WIDTH_3-1 downto 0);
a1_3 : in std_logic_vector(COEFF_WIDTH_3-1 downto 0);
a2_3 : in std_logic_vector(COEFF_WIDTH_3-1 downto 0);
y : out std_logic_vector(DATA_WIDTH-1 downto 0));
end Equalizer;
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
architecture behaviour of Equalizer is
-- Signals ---------------------------------------------------------------------
signal s_scale_1 : std_logic_vector(SCALE_WIDTH_1-1 downto 0);
signal s_scale_2 : std_logic_vector(SCALE_WIDTH_2-1 downto 0);
signal s_scale_3 : std_logic_vector(SCALE_WIDTH_3-1 downto 0);
signal s_scale_4 : std_logic_vector(SCALE_WIDTH_4-1 downto 0);
signal s_b0_1 : std_logic_vector(COEFF_WIDTH_1-1 downto 0);
signal s_b1_1 : std_logic_vector(COEFF_WIDTH_1-1 downto 0);
signal s_b2_1 : std_logic_vector(COEFF_WIDTH_1-1 downto 0);
signal s_a1_1 : std_logic_vector(COEFF_WIDTH_1-1 downto 0);
signal s_a2_1 : std_logic_vector(COEFF_WIDTH_1-1 downto 0);
signal s_b0_2 : std_logic_vector(COEFF_WIDTH_2-1 downto 0);
signal s_b1_2 : std_logic_vector(COEFF_WIDTH_2-1 downto 0);
signal s_b2_2 : std_logic_vector(COEFF_WIDTH_2-1 downto 0);
signal s_a1_2 : std_logic_vector(COEFF_WIDTH_2-1 downto 0);
signal s_a2_2 : std_logic_vector(COEFF_WIDTH_2-1 downto 0);
signal s_b0_3 : std_logic_vector(COEFF_WIDTH_3-1 downto 0);
signal s_b1_3 : std_logic_vector(COEFF_WIDTH_3-1 downto 0);
signal s_b2_3 : std_logic_vector(COEFF_WIDTH_3-1 downto 0);
signal s_a1_3 : std_logic_vector(COEFF_WIDTH_3-1 downto 0);
signal s_a2_3 : std_logic_vector(COEFF_WIDTH_3-1 downto 0);
signal iir_input_1 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal iir_input_2 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal iir_input_3 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal iir_output_1 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal iir_output_2 : std_logic_vector(DATA_WIDTH-1 downto 0);
signal iir_output_3 : std_logic_vector(DATA_WIDTH-1 downto 0);
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
begin
-- Set coefficients
s_scale_1 <= scale_1;
s_scale_2 <= scale_2;
s_scale_3 <= scale_3;
s_scale_4 <= scale_4;
s_b0_1 <= b0_1;
s_b1_1 <= b1_1;
s_b2_1 <= b2_1;
s_a1_1 <= a1_1;
s_a2_1 <= a2_1;
s_b0_2 <= b0_2;
s_b1_2 <= b1_2;
s_b2_2 <= b2_2;
s_a1_2 <= a1_2;
s_a2_2 <= a2_2;
s_b0_3 <= b0_3;
s_b1_3 <= b1_3;
s_b2_3 <= b2_3;
s_a1_3 <= a1_3;
s_a2_3 <= a2_3;
-- Stage 1 -------------------------------------------------------------------
Multiplier_1 : entity work.Multiplier
generic map(X_WIDTH => DATA_WIDTH,
X_FRACTION => DATA_FRACT,
Y_WIDTH => SCALE_WIDTH_1,
Y_FRACTION => SCALE_FRACT_1,
S_WIDTH => DATA_WIDTH,
S_FRACTION => DATA_FRACT)
port map(x => x,
y => s_scale_1,
s => iir_input_1);
Generic_IIR_SO_1 : entity work.Generic_IIR_SO
generic map(IN_WIDTH => DATA_WIDTH,
IN_FRACT => DATA_FRACT,
COEFFICIENT_WIDTH => COEFF_WIDTH_1,
COEFFICIENT_FRACT => COEFF_FRACT_1,
INTERNAL_WIDTH => INTERNAL_IIR_WIDTH_1,
INTERNAL_FRACT => INTERNAL_IIR_FRACT_1,
OUT_WIDTH => DATA_WIDTH,
OUT_FRACT => DATA_FRACT)
port map(clk => clk,
reset => reset,
x => iir_input_1,
B0 => s_b0_1,
B1 => s_b1_1,
B2 => s_b2_1,
A1 => s_a1_1,
A2 => s_a2_1,
y => iir_output_1);
-- Stage 2 -------------------------------------------------------------------
Multiplier_2 : entity work.Multiplier
generic map(X_WIDTH => DATA_WIDTH,
X_FRACTION => DATA_FRACT,
Y_WIDTH => SCALE_WIDTH_2,
Y_FRACTION => SCALE_FRACT_2,
S_WIDTH => DATA_WIDTH,
S_FRACTION => DATA_FRACT)
port map(x => iir_output_1,
y => s_scale_2,
s => iir_input_2);
Generic_IIR_SO_2 : entity work.Generic_IIR_SO
generic map(IN_WIDTH => DATA_WIDTH,
IN_FRACT => DATA_FRACT,
COEFFICIENT_WIDTH => COEFF_WIDTH_2,
COEFFICIENT_FRACT => COEFF_FRACT_2,
INTERNAL_WIDTH => INTERNAL_IIR_WIDTH_2,
INTERNAL_FRACT => INTERNAL_IIR_FRACT_2,
OUT_WIDTH => DATA_WIDTH,
OUT_FRACT => DATA_FRACT)
port map(clk => clk,
reset => reset,
x => iir_input_2,
B0 => s_b0_2,
B1 => s_b1_2,
B2 => s_b2_2,
A1 => s_a1_2,
A2 => s_a2_2,
y => iir_output_2);
-- Stage 3 -------------------------------------------------------------------
Multiplier_3 : entity work.Multiplier
generic map(X_WIDTH => DATA_WIDTH,
X_FRACTION => DATA_FRACT,
Y_WIDTH => SCALE_WIDTH_3,
Y_FRACTION => SCALE_FRACT_3,
S_WIDTH => DATA_WIDTH,
S_FRACTION => DATA_FRACT)
port map(x => iir_output_2,
y => s_scale_3,
s => iir_input_3);
Generic_IIR_SO_3 : entity work.Generic_IIR_SO
generic map(IN_WIDTH => DATA_WIDTH,
IN_FRACT => DATA_FRACT,
COEFFICIENT_WIDTH => COEFF_WIDTH_3,
COEFFICIENT_FRACT => COEFF_FRACT_3,
INTERNAL_WIDTH => INTERNAL_IIR_WIDTH_3,
INTERNAL_FRACT => INTERNAL_IIR_FRACT_3,
OUT_WIDTH => DATA_WIDTH,
OUT_FRACT => DATA_FRACT)
port map(clk => clk,
reset => reset,
x => iir_input_3,
B0 => s_b0_3,
B1 => s_b1_3,
B2 => s_b2_3,
A1 => s_a1_3,
A2 => s_a2_3,
y => iir_output_3);
-- Stage 4 -------------------------------------------------------------------
Multiplier_4 : entity work.Multiplier
generic map(X_WIDTH => DATA_WIDTH,
X_FRACTION => DATA_FRACT,
Y_WIDTH => SCALE_WIDTH_4,
Y_FRACTION => SCALE_FRACT_4,
S_WIDTH => DATA_WIDTH,
S_FRACTION => DATA_FRACT)
port map(x => iir_output_3,
y => s_scale_4,
s => y);
end architecture;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
bin_Gray_Processing/ip/Gray_Processing/hcc_castftoy.vhd
|
10
|
4220
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTFTOY.VHD ***
--*** ***
--*** Function: Cast IEEE754 Single to Internal ***
--*** Double ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
-- castftoy : float <=> internal double
ENTITY hcc_castftoy IS
GENERIC (
target : integer := 0; -- 1 (internal), 0 (multiplier,divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_castftoy;
ARCHITECTURE rtl OF hcc_castftoy IS
signal floatnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal satnode, zipnode : STD_LOGIC;
component hcc_castftox
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castxtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
BEGIN
-- if ftoy target divider or multiplier, need unsigned output
-- if ftoy target = 1 (internal), ftox target = 0, xtoy target = 1
-- if ftoy target = 0 (multiplier, divider), ftox target = 2 (divider), xtoy target = 0 (mult&div)
gaa: IF (target = 1) GENERATE
one: hcc_castftox
GENERIC MAP(target=>0,roundconvert=>roundconvert,
mantissa=>mantissa,outputpipe=>outputpipe)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>floatnode,ccsat=>satnode,cczip=>zipnode);
two: hcc_castxtoy
GENERIC MAP(target=>1,mantissa=>mantissa)
PORT MAP (aa=>floatnode,aasat=>satnode,aazip=>zipnode,
cc=>cc,ccsat=>ccsat,cczip=>cczip);
END GENERATE;
gab: IF (target = 0) GENERATE
one: hcc_castftox
GENERIC MAP(target=>2,roundconvert=>roundconvert,
mantissa=>mantissa,outputpipe=>outputpipe)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>floatnode,ccsat=>satnode,cczip=>zipnode);
two: hcc_castxtoy
GENERIC MAP(target=>0,mantissa=>mantissa)
PORT MAP (aa=>floatnode,aasat=>satnode,aazip=>zipnode,
cc=>cc,ccsat=>ccsat,cczip=>cczip);
END GENERATE;
END rtl;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
bin_Gray_Processing/ip/Gray_Processing/dp_pos.vhd
|
10
|
5994
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION MULTIPLIER - CORE LEVEL ***
--*** ***
--*** DP_POS.VHD ***
--*** ***
--*** Function: Local Count Leading Zeroes ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_pos IS
GENERIC (start : integer := 10);
PORT (
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END dp_pos;
ARCHITECTURE rtl of dp_pos IS
BEGIN
ptab: PROCESS (ingroup)
BEGIN
CASE ingroup IS
WHEN "000000" => position <= conv_std_logic_vector(0,6);
WHEN "000001" => position <= conv_std_logic_vector(start+5,6);
WHEN "000010" => position <= conv_std_logic_vector(start+4,6);
WHEN "000011" => position <= conv_std_logic_vector(start+4,6);
WHEN "000100" => position <= conv_std_logic_vector(start+3,6);
WHEN "000101" => position <= conv_std_logic_vector(start+3,6);
WHEN "000110" => position <= conv_std_logic_vector(start+3,6);
WHEN "000111" => position <= conv_std_logic_vector(start+3,6);
WHEN "001000" => position <= conv_std_logic_vector(start+2,6);
WHEN "001001" => position <= conv_std_logic_vector(start+2,6);
WHEN "001010" => position <= conv_std_logic_vector(start+2,6);
WHEN "001011" => position <= conv_std_logic_vector(start+2,6);
WHEN "001100" => position <= conv_std_logic_vector(start+2,6);
WHEN "001101" => position <= conv_std_logic_vector(start+2,6);
WHEN "001110" => position <= conv_std_logic_vector(start+2,6);
WHEN "001111" => position <= conv_std_logic_vector(start+2,6);
WHEN "010000" => position <= conv_std_logic_vector(start+1,6);
WHEN "010001" => position <= conv_std_logic_vector(start+1,6);
WHEN "010010" => position <= conv_std_logic_vector(start+1,6);
WHEN "010011" => position <= conv_std_logic_vector(start+1,6);
WHEN "010100" => position <= conv_std_logic_vector(start+1,6);
WHEN "010101" => position <= conv_std_logic_vector(start+1,6);
WHEN "010110" => position <= conv_std_logic_vector(start+1,6);
WHEN "010111" => position <= conv_std_logic_vector(start+1,6);
WHEN "011000" => position <= conv_std_logic_vector(start+1,6);
WHEN "011001" => position <= conv_std_logic_vector(start+1,6);
WHEN "011010" => position <= conv_std_logic_vector(start+1,6);
WHEN "011011" => position <= conv_std_logic_vector(start+1,6);
WHEN "011100" => position <= conv_std_logic_vector(start+1,6);
WHEN "011101" => position <= conv_std_logic_vector(start+1,6);
WHEN "011110" => position <= conv_std_logic_vector(start+1,6);
WHEN "011111" => position <= conv_std_logic_vector(start+1,6);
WHEN "100000" => position <= conv_std_logic_vector(start,6);
WHEN "100001" => position <= conv_std_logic_vector(start,6);
WHEN "100010" => position <= conv_std_logic_vector(start,6);
WHEN "100011" => position <= conv_std_logic_vector(start,6);
WHEN "100100" => position <= conv_std_logic_vector(start,6);
WHEN "100101" => position <= conv_std_logic_vector(start,6);
WHEN "100110" => position <= conv_std_logic_vector(start,6);
WHEN "100111" => position <= conv_std_logic_vector(start,6);
WHEN "101000" => position <= conv_std_logic_vector(start,6);
WHEN "101001" => position <= conv_std_logic_vector(start,6);
WHEN "101010" => position <= conv_std_logic_vector(start,6);
WHEN "101011" => position <= conv_std_logic_vector(start,6);
WHEN "101100" => position <= conv_std_logic_vector(start,6);
WHEN "101101" => position <= conv_std_logic_vector(start,6);
WHEN "101110" => position <= conv_std_logic_vector(start,6);
WHEN "101111" => position <= conv_std_logic_vector(start,6);
WHEN "110000" => position <= conv_std_logic_vector(start,6);
WHEN "110001" => position <= conv_std_logic_vector(start,6);
WHEN "110010" => position <= conv_std_logic_vector(start,6);
WHEN "110011" => position <= conv_std_logic_vector(start,6);
WHEN "110100" => position <= conv_std_logic_vector(start,6);
WHEN "110101" => position <= conv_std_logic_vector(start,6);
WHEN "110110" => position <= conv_std_logic_vector(start,6);
WHEN "110111" => position <= conv_std_logic_vector(start,6);
WHEN "111000" => position <= conv_std_logic_vector(start,6);
WHEN "111001" => position <= conv_std_logic_vector(start,6);
WHEN "111010" => position <= conv_std_logic_vector(start,6);
WHEN "111011" => position <= conv_std_logic_vector(start,6);
WHEN "111100" => position <= conv_std_logic_vector(start,6);
WHEN "111101" => position <= conv_std_logic_vector(start,6);
WHEN "111110" => position <= conv_std_logic_vector(start,6);
WHEN "111111" => position <= conv_std_logic_vector(start,6);
WHEN others => position <= conv_std_logic_vector(0,6);
END CASE;
END PROCESS;
END rtl;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
Gray_Processing/ip/Gray_Processing/dp_pos.vhd
|
10
|
5994
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION MULTIPLIER - CORE LEVEL ***
--*** ***
--*** DP_POS.VHD ***
--*** ***
--*** Function: Local Count Leading Zeroes ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_pos IS
GENERIC (start : integer := 10);
PORT (
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END dp_pos;
ARCHITECTURE rtl of dp_pos IS
BEGIN
ptab: PROCESS (ingroup)
BEGIN
CASE ingroup IS
WHEN "000000" => position <= conv_std_logic_vector(0,6);
WHEN "000001" => position <= conv_std_logic_vector(start+5,6);
WHEN "000010" => position <= conv_std_logic_vector(start+4,6);
WHEN "000011" => position <= conv_std_logic_vector(start+4,6);
WHEN "000100" => position <= conv_std_logic_vector(start+3,6);
WHEN "000101" => position <= conv_std_logic_vector(start+3,6);
WHEN "000110" => position <= conv_std_logic_vector(start+3,6);
WHEN "000111" => position <= conv_std_logic_vector(start+3,6);
WHEN "001000" => position <= conv_std_logic_vector(start+2,6);
WHEN "001001" => position <= conv_std_logic_vector(start+2,6);
WHEN "001010" => position <= conv_std_logic_vector(start+2,6);
WHEN "001011" => position <= conv_std_logic_vector(start+2,6);
WHEN "001100" => position <= conv_std_logic_vector(start+2,6);
WHEN "001101" => position <= conv_std_logic_vector(start+2,6);
WHEN "001110" => position <= conv_std_logic_vector(start+2,6);
WHEN "001111" => position <= conv_std_logic_vector(start+2,6);
WHEN "010000" => position <= conv_std_logic_vector(start+1,6);
WHEN "010001" => position <= conv_std_logic_vector(start+1,6);
WHEN "010010" => position <= conv_std_logic_vector(start+1,6);
WHEN "010011" => position <= conv_std_logic_vector(start+1,6);
WHEN "010100" => position <= conv_std_logic_vector(start+1,6);
WHEN "010101" => position <= conv_std_logic_vector(start+1,6);
WHEN "010110" => position <= conv_std_logic_vector(start+1,6);
WHEN "010111" => position <= conv_std_logic_vector(start+1,6);
WHEN "011000" => position <= conv_std_logic_vector(start+1,6);
WHEN "011001" => position <= conv_std_logic_vector(start+1,6);
WHEN "011010" => position <= conv_std_logic_vector(start+1,6);
WHEN "011011" => position <= conv_std_logic_vector(start+1,6);
WHEN "011100" => position <= conv_std_logic_vector(start+1,6);
WHEN "011101" => position <= conv_std_logic_vector(start+1,6);
WHEN "011110" => position <= conv_std_logic_vector(start+1,6);
WHEN "011111" => position <= conv_std_logic_vector(start+1,6);
WHEN "100000" => position <= conv_std_logic_vector(start,6);
WHEN "100001" => position <= conv_std_logic_vector(start,6);
WHEN "100010" => position <= conv_std_logic_vector(start,6);
WHEN "100011" => position <= conv_std_logic_vector(start,6);
WHEN "100100" => position <= conv_std_logic_vector(start,6);
WHEN "100101" => position <= conv_std_logic_vector(start,6);
WHEN "100110" => position <= conv_std_logic_vector(start,6);
WHEN "100111" => position <= conv_std_logic_vector(start,6);
WHEN "101000" => position <= conv_std_logic_vector(start,6);
WHEN "101001" => position <= conv_std_logic_vector(start,6);
WHEN "101010" => position <= conv_std_logic_vector(start,6);
WHEN "101011" => position <= conv_std_logic_vector(start,6);
WHEN "101100" => position <= conv_std_logic_vector(start,6);
WHEN "101101" => position <= conv_std_logic_vector(start,6);
WHEN "101110" => position <= conv_std_logic_vector(start,6);
WHEN "101111" => position <= conv_std_logic_vector(start,6);
WHEN "110000" => position <= conv_std_logic_vector(start,6);
WHEN "110001" => position <= conv_std_logic_vector(start,6);
WHEN "110010" => position <= conv_std_logic_vector(start,6);
WHEN "110011" => position <= conv_std_logic_vector(start,6);
WHEN "110100" => position <= conv_std_logic_vector(start,6);
WHEN "110101" => position <= conv_std_logic_vector(start,6);
WHEN "110110" => position <= conv_std_logic_vector(start,6);
WHEN "110111" => position <= conv_std_logic_vector(start,6);
WHEN "111000" => position <= conv_std_logic_vector(start,6);
WHEN "111001" => position <= conv_std_logic_vector(start,6);
WHEN "111010" => position <= conv_std_logic_vector(start,6);
WHEN "111011" => position <= conv_std_logic_vector(start,6);
WHEN "111100" => position <= conv_std_logic_vector(start,6);
WHEN "111101" => position <= conv_std_logic_vector(start,6);
WHEN "111110" => position <= conv_std_logic_vector(start,6);
WHEN "111111" => position <= conv_std_logic_vector(start,6);
WHEN others => position <= conv_std_logic_vector(0,6);
END CASE;
END PROCESS;
END rtl;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
bin_Gray_Processing/ip/Gray_Processing/dp_invsqr.vhd
|
10
|
10246
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION INVERSE SQUARE ROOT ***
--*** TOP LEVEL ***
--*** ***
--*** DP_INVSQR.VHD ***
--*** ***
--*** Function: IEEE754 DP Inverse Square Root ***
--*** (multiplicative iterative algorithm) ***
--*** ***
--*** 11/08/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** ***
--*** Stratix II ***
--*** Latency = 32 + 2*Speed ***
--*** Speed = 0 : 32 ***
--*** Speed = 1 : 34 ***
--*** ***
--*** Stratix III/IV ***
--*** Latency = 31 + Speed ***
--*** Speed = 0 : 31 ***
--*** Speed = 1 : 32 ***
--*** ***
--***************************************************
ENTITY dp_invsqr IS
GENERIC (
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed : integer := 0; -- 0/1
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin: IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC
);
END dp_invsqr;
ARCHITECTURE rtl OF dp_invsqr IS
constant manwidth : positive := 52;
constant expwidth : positive := 11;
constant coredepth : positive := 31+2*doublespeed - device*(1+doublespeed);
type expfftype IS ARRAY (coredepth+1 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (coredepth+1 DOWNTO 1);
signal correctff : STD_LOGIC_VECTOR (3 DOWNTO 1); -- SPR 383712
signal expff : expfftype;
signal radicand : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal oddexponent : STD_LOGIC;
signal invroot : STD_LOGIC_VECTOR (54 DOWNTO 1);
--signal invroottest : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal manff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal offset : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
-- conditions
signal nanmanff, nanexpff : STD_LOGIC_VECTOR (coredepth-1 DOWNTO 1);
signal zeroexpff, zeromanff : STD_LOGIC_VECTOR (coredepth-2 DOWNTO 1);
signal expinzero, expinmax : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maninzero : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expzero, expmax, manzero : STD_LOGIC;
signal infinityconditionff, nanconditionff, expzeroff : STD_LOGIC;
signal correct_powers_of_two : STD_LOGIC; -- SPR 383712
component dp_invsqr_core IS
GENERIC (
doublespeed : integer := 0; -- 0/1
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radicand : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
odd : IN STD_LOGIC;
invroot : OUT STD_LOGIC_VECTOR (54 DOWNTO 1)
);
end component;
BEGIN
gzva: FOR k IN 1 TO manwidth GENERATE
zerovec(k) <= '0';
END GENERATE;
gxoa: FOR k IN 1 TO expwidth-1 GENERATE
offset(k) <= '1';
END GENERATE;
offset(expwidth) <= '0';
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth LOOP
maninff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth+1 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth+1 LOOP
FOR j IN 1 TO expwidth LOOP
expff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO manwidth LOOP
manff(k) <= '0';
END LOOP;
correctff <= "000"; -- SPR 383712
ELSIF (rising_edge(sysclk)) THEN
maninff <= mantissain;
expinff <= exponentin;
signff(1) <= signin;
FOR k IN 2 TO coredepth+1 LOOP
signff(k) <= signff(k-1);
END LOOP;
expff(1)(expwidth DOWNTO 1) <= exponentin;
expff(2)(expwidth DOWNTO 1) <= expff(1)(expwidth DOWNTO 1) - offset;
expff(3)(expwidth DOWNTO 1) <= expff(2)(expwidth) & expff(2)(expwidth DOWNTO 2);
expff(4)(expwidth DOWNTO 1) <= offset - expff(3)(expwidth DOWNTO 1);
expff(5)(expwidth DOWNTO 1) <= expff(4)(expwidth DOWNTO 1) - 1 + correctff(3);
FOR k IN 6 TO coredepth LOOP
expff(k)(expwidth DOWNTO 1) <= expff(k-1)(expwidth DOWNTO 1);
END LOOP;
FOR k IN 1 TO expwidth LOOP
expff(coredepth+1)(k) <= (expff(coredepth)(k) AND zeroexpff(coredepth-2)) OR nanexpff(coredepth-2);
END LOOP;
-- SPR 383712
correctff(1) <= correct_powers_of_two;
correctff(2) <= correctff(1);
correctff(3) <= correctff(2);
FOR k IN 1 TO manwidth LOOP
manff(k) <= (invroot(k+1) AND zeromanff(coredepth-2)) OR nanmanff(coredepth-2);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** CONDITIONS ***
--*******************
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO coredepth-1 LOOP
nanmanff(k) <= '0';
nanexpff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth-2 LOOP
zeroexpff(k) <= '0';
zeromanff(k) <= '0';
END LOOP;
infinityconditionff <= '0';
nanconditionff <= '0';
expzeroff <= '0';
ELSIF (rising_edge(sysclk)) THEN
infinityconditionff <= manzero AND expmax;
nanconditionff <= signff(1) OR expzero OR (expmax AND manzero);
expzeroff <= expzero;
nanmanff(1) <= nanconditionff; -- level 3
nanexpff(1) <= nanconditionff OR infinityconditionff; -- also max exp when infinity
FOR k IN 2 TO coredepth-1 LOOP
nanmanff(k) <= nanmanff(k-1);
nanexpff(k) <= nanexpff(k-1);
END LOOP;
zeromanff(1) <= NOT(expzeroff) AND NOT(infinityconditionff); -- level 3
zeroexpff(1) <= NOT(expzeroff); -- level 3
FOR k IN 2 TO coredepth-2 LOOP
zeromanff(k) <= zeromanff(k-1);
zeroexpff(k) <= zeroexpff(k-1);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** SQUARE ROOT ***
--*******************
radicand <= '1' & mantissain & '0';
-- sub 1023, so 1023 (odd) = 2^0 => even
oddexponent <= NOT(exponentin(1));
-- does not require rounding, output of core rounded already, LSB always 0
isqr: dp_invsqr_core
GENERIC MAP (doublespeed=>doublespeed,doubleaccuracy=>doubleaccuracy,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
radicand=>radicand,odd=>oddexponent,
invroot=>invroot);
--*********************
--*** SPECIAL CASES ***
--*********************
-- 1. if negative input, invalid operation, NAN
-- 2. 0 in, invalid operation, NAN
-- 3. infinity in, invalid operation, infinity out
-- 4. NAN in, invalid operation, NAN
-- '1' if 0
expinzero(1) <= expinff(1);
gxza: FOR k IN 2 TO expwidth GENERATE
expinzero(k) <= expinzero(k-1) OR expinff(k);
END GENERATE;
expzero <= NOT(expinzero(expwidth)); -- '0' when zero
-- '1' if nan or infinity
expinmax(1) <= expinff(1);
gxia: FOR k IN 2 TO expwidth GENERATE
expinmax(k) <= expinmax(k-1) AND expinff(k);
END GENERATE;
expmax <= expinmax(expwidth); -- '1' when true
-- '1' if zero or infinity
maninzero(1) <= maninff(1);
gmza: FOR k IN 2 TO manwidth GENERATE
maninzero(k) <= maninzero(k-1) OR maninff(k);
END GENERATE;
manzero <= NOT(maninzero(manwidth));
-- 09/03/11 ML
-- if mantissa is 0 and exponent is odd (...123,125,127,129,131...) then dont subtract 1 from offset corrected exponent
-- '1' is subtracted as any value, no matter how small, in the mantissa will reduce the inverse below the mirrored exponent (around 127)
-- if the exponent is odd (with mantissa 0) the value is a power of 2 (...0.25,0.5,1,2,4...) and the mirrored exponent is correct
-- if the exponent is even (with mantissa 0), the inverse square root will have a non zero mantissa and can be handled normally
correct_powers_of_two <= manzero AND expinff(1); -- SPR 383712
--***************
--*** OUTPUTS ***
--***************
signout <= signff(coredepth+1);
exponentout <= expff(coredepth+1)(expwidth DOWNTO 1);
mantissaout <= manff;
-----------------------------------------------
nanout <= nanmanff(coredepth-1);
invalidout <= nanmanff(coredepth-1);
END rtl;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
Gray_Processing/ip/Gray_Processing/hcc_alufp1_dot_sv.vhd
|
10
|
12467
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALUFP1_DOT.VHD ***
--*** ***
--*** Function: Single Precision Floating Point ***
--*** Adder (Signed Magnitude for first level ***
--*** Vector Optimized Structure) ***
--*** ***
--*** 15/10/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--*** TBD - what if exponents negative ***
ENTITY hcc_alufp1_dot IS
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_alufp1_dot;
ARCHITECTURE rtl OF hcc_alufp1_dot IS
type exponentbasefftype IS ARRAY (3+shiftspeed DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
-- input registers and nodes
signal aasignff, bbsignff : STD_LOGIC;
signal aamantissaff, bbmantissaff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aaexponentff, bbexponentff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal aananff, bbnanff : STD_LOGIC;
signal addsubff : STD_LOGIC;
signal aasignnode, bbsignnode : STD_LOGIC;
signal aamantissanode, bbmantissanode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aaexponentnode, bbexponentnode : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aasatnode, aazipnode, bbsatnode, bbzipnode : STD_LOGIC;
signal aanannode, bbnannode : STD_LOGIC;
signal addsubnode : STD_LOGIC;
signal mantissaleftff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal mantissarightff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal mantissaleftdelayff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal exponentshiftff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal exponentbaseff : exponentbasefftype;
signal invertleftff, invertrightff : STD_LOGIC_VECTOR (2+shiftspeed DOWNTO 1);
signal shiftcheckff, shiftcheckdelayff : STD_LOGIC;
signal aluleftff, alurightff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aluff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal ccsatff, cczipff, ccnanff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal mantissaleftnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal zeroaluright : STD_LOGIC;
signal aluleftnode, alurightnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal alucarrybitnode : STD_LOGIC;
signal subexponentone, subexponenttwo : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal switch : STD_LOGIC;
signal shiftcheck : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal shiftcheckbit : STD_LOGIC;
signal shiftbusnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_rsftpipe32
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_rsftpipe36
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_rsftcomb32
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_rsftcomb36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pin: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
aasignff <= '0';
bbsignff <= '0';
FOR k IN 1 TO mantissa LOOP
aamantissaff(k) <= '0';
bbmantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
aaexponentff(k) <= '0';
bbexponentff(k) <= '0';
END LOOP;
aasatff <= '0';
bbsatff <= '0';
aazipff <= '0';
bbzipff <= '0';
aananff <= '0';
bbnanff <= '0';
addsubff <= addsub_resetval;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aasignff <= aa(mantissa+10);
bbsignff <= bb(mantissa+10);
aamantissaff <= '0'& aa(mantissa+9 DOWNTO 11);
bbmantissaff <= '0'& bb(mantissa+9 DOWNTO 11);
aaexponentff <= aa(10 DOWNTO 1);
bbexponentff <= bb(10 DOWNTO 1);
aasatff <= aasat;
bbsatff <= bbsat;
aazipff <= aazip;
bbzipff <= bbzip;
aananff <= aanan;
bbnanff <= bbnan;
addsubff <= addsub;
END IF;
END IF;
END PROCESS;
gina: IF (outputpipe = 1) GENERATE
aasignnode <= aasignff;
aamantissanode <= aamantissaff;
aaexponentnode <= aaexponentff;
bbsignnode <= bbsignff;
bbmantissanode <= bbmantissaff;
bbexponentnode <= bbexponentff;
aasatnode <= aasatff;
bbsatnode <= bbsatff;
aazipnode <= aazipff;
bbzipnode <= bbzipff;
aanannode <= aananff;
bbnannode <= bbnanff;
addsubnode <= addsubff;
END GENERATE;
ginb: IF (outputpipe = 0) GENERATE
aasignnode <= aa(mantissa+10);
bbsignnode <= bb(mantissa+10);
aamantissanode <= '0'& aa(mantissa+9 DOWNTO 11);
bbmantissanode <= '0'& bb(mantissa+9 DOWNTO 11);
aaexponentnode <= aa(10 DOWNTO 1);
bbexponentnode <= bb(10 DOWNTO 1);
aasatnode <= aasat;
bbsatnode <= bbsat;
aazipnode <= aazip;
bbzipnode <= bbzip;
aanannode <= aanan;
bbnannode <= bbnan;
addsubnode <= addsub;
END GENERATE;
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa LOOP
mantissaleftff(k) <= '0';
mantissarightff(k) <= '0';
mantissaleftdelayff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
exponentshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
FOR j IN 1 TO 10 LOOP
exponentbaseff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO 2+shiftspeed LOOP
invertleftff(k) <= '0';
invertrightff(k) <= '0';
END LOOP;
shiftcheckff <= '0';
shiftcheckdelayff <= '0';
FOR k IN 1 TO mantissa LOOP
aluleftff(k) <= '0';
alurightff(k) <= '0';
aluff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
ccsatff(k) <= '0';
cczipff(k) <= '0';
ccnanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO mantissa LOOP
mantissaleftff(k) <= (aamantissanode(k) AND NOT(switch)) OR (bbmantissanode(k) AND switch);
mantissarightff(k) <= (bbmantissanode(k) AND NOT(switch)) OR (aamantissanode(k) AND switch);
END LOOP;
-- only use if shiftspeed = 1
mantissaleftdelayff <= mantissaleftff;
FOR k IN 1 TO 10 LOOP
exponentshiftff(k) <= (subexponentone(k) AND NOT(switch)) OR (subexponenttwo(k) AND switch);
END LOOP;
FOR k IN 1 TO 10 LOOP
exponentbaseff(1)(k) <= (aaexponentnode(k) AND NOT(switch)) OR (bbexponentnode(k) AND switch);
END LOOP;
FOR k IN 2 TO 3+shiftspeed LOOP
exponentbaseff(k)(10 DOWNTO 1) <= exponentbaseff(k-1)(10 DOWNTO 1);
END LOOP;
invertleftff(1) <= ((aasignnode AND NOT(switch)) OR (bbsignnode AND switch)) XOR (addsubnode AND switch);
invertrightff(1) <= ((bbsignnode AND NOT(switch)) OR (aasignnode AND switch)) XOR (addsubnode AND NOT(switch));
FOR k IN 2 TO 2+shiftspeed LOOP
invertleftff(k) <= invertleftff(k-1);
invertrightff(k) <= invertrightff(k-1);
END LOOP;
shiftcheckff <= shiftcheckbit;
shiftcheckdelayff <= shiftcheckff;
aluleftff <= mantissaleftnode;
alurightff <= shiftbusnode;
aluff <= aluleftnode + alurightnode + alucarrybitnode;
ccsatff(1) <= aasatnode OR bbsatnode;
cczipff(1) <= aazipnode AND bbzipnode;
-- add/sub infinity is invalid OP, NAN out
ccnanff(1) <= aanannode OR bbnannode OR aasatnode OR bbsatnode;
FOR k IN 2 TO 3+shiftspeed LOOP
ccsatff(k) <= ccsatff(k-1);
cczipff(k) <= cczipff(k-1);
ccnanff(k) <= ccnanff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
gmsa: IF (shiftspeed = 0) GENERATE
mantissaleftnode <= mantissaleftff;
zeroaluright <= shiftcheckff;
END GENERATE;
gmsb: IF (shiftspeed = 1) GENERATE
mantissaleftnode <= mantissaleftdelayff;
zeroaluright <= shiftcheckdelayff;
END GENERATE;
gma: FOR k IN 1 TO mantissa GENERATE
aluleftnode(k) <= aluleftff(k) XOR invertleftff(2+shiftspeed);
alurightnode(k) <= (alurightff(k) XOR invertrightff(2+shiftspeed)) AND NOT(zeroaluright);
END GENERATE;
-- carrybit into ALU only if larger value is negated
alucarrybitnode <= invertleftff(2+shiftspeed);
subexponentone <= aaexponentnode(10 DOWNTO 1) - bbexponentnode(10 DOWNTO 1);
subexponenttwo <= bbexponentnode(10 DOWNTO 1) - aaexponentnode(10 DOWNTO 1);
switch <= subexponentone(10);
gsa: IF (mantissa = 32) GENERATE
-- 31 ok, 32 not
shiftcheck <= "0000000000";
-- if '1', then zero right bus
shiftcheckbit <= exponentshiftff(10) OR exponentshiftff(9) OR exponentshiftff(8) OR
exponentshiftff(7) OR exponentshiftff(6);
gsb: IF (shiftspeed = 0) GENERATE
shiftone: hcc_rsftcomb32
PORT MAP (inbus=>mantissarightff,shift=>exponentshiftff(5 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
gsc: IF (shiftspeed = 1) GENERATE
shifttwo: hcc_rsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>mantissarightff,shift=>exponentshiftff(5 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
END GENERATE;
gsd: IF (mantissa = 36) GENERATE
-- 35 ok, 36 not
shiftcheck <= exponentshiftff - "0000100100";
-- if '1', then zero right bus
shiftcheckbit <= NOT(shiftcheck(10));
gse: IF (shiftspeed = 0) GENERATE
shiftone: hcc_rsftcomb36
PORT MAP (inbus=>mantissarightff,shift=>exponentshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
gsf: IF (shiftspeed = 1) GENERATE
shifttwo: hcc_rsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>mantissarightff,shift=>exponentshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
END GENERATE;
--*** OUTPUT ***
cc <= aluff & exponentbaseff(3+shiftspeed)(10 DOWNTO 1);
ccsat <= ccsatff(3+shiftspeed);
cczip <= cczipff(3+shiftspeed);
ccnan <= ccnanff(3+shiftspeed);
END rtl;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
Gray_Processing/ip/Gray_Processing/fp_invsqr_trig1.vhd
|
10
|
4091
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
-- for 36 bit mantissa for trig library
--***************************************************
--*** Notes: Latency = 17 ***
--***************************************************
ENTITY fp_invsqr_trig1 IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
exponentin: IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_invsqr_trig1;
ARCHITECTURE rtl OF fp_invsqr_trig1 IS
constant manwidth : positive := 36;
constant expwidth : positive := 8;
constant coredepth : positive := 17;
type expfftype IS ARRAY (coredepth DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal expff : expfftype;
signal radicand : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal oddexponent : STD_LOGIC;
signal invroot : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal offset : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
component fp_invsqr_core IS
GENERIC (synthesize : integer := 1); -- 0/1
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radicand : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
odd : IN STD_LOGIC;
invroot : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
gzva: FOR k IN 1 TO manwidth GENERATE
zerovec(k) <= '0';
END GENERATE;
gxoa: FOR k IN 1 TO expwidth-1 GENERATE
offset(k) <= '1';
END GENERATE;
offset(expwidth) <= '0';
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO coredepth LOOP
FOR j IN 1 TO expwidth LOOP
expff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
expff(1)(expwidth DOWNTO 1) <= exponentin;
expff(2)(expwidth DOWNTO 1) <= expff(1)(expwidth DOWNTO 1) - offset;
expff(3)(expwidth DOWNTO 1) <= expff(2)(expwidth) & expff(2)(expwidth DOWNTO 2);
expff(4)(expwidth DOWNTO 1) <= offset - expff(3)(expwidth DOWNTO 1);
expff(5)(expwidth DOWNTO 1) <= expff(4)(expwidth DOWNTO 1) - 1;
FOR k IN 6 TO coredepth LOOP
expff(k)(expwidth DOWNTO 1) <= expff(k-1)(expwidth DOWNTO 1);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** SQUARE ROOT ***
--*******************
radicand <= mantissain; -- already with leading '1'
-- sub 127, so 127 (odd) = 2^0 => even
oddexponent <= NOT(exponentin(1));
-- does not require rounding, output of core rounded already, LSB always 0
isqr: fp_invsqr_core
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
radicand=>radicand,odd=>oddexponent,
invroot=>invroot);
--***************
--*** OUTPUTS ***
--***************
exponentout <= expff(coredepth)(expwidth DOWNTO 1);
mantissaout <= invroot;
END rtl;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
bin_Gray_Processing/ip/Gray_Processing/fp_invsqr_trig1.vhd
|
10
|
4091
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
-- for 36 bit mantissa for trig library
--***************************************************
--*** Notes: Latency = 17 ***
--***************************************************
ENTITY fp_invsqr_trig1 IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
exponentin: IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_invsqr_trig1;
ARCHITECTURE rtl OF fp_invsqr_trig1 IS
constant manwidth : positive := 36;
constant expwidth : positive := 8;
constant coredepth : positive := 17;
type expfftype IS ARRAY (coredepth DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal expff : expfftype;
signal radicand : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal oddexponent : STD_LOGIC;
signal invroot : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal offset : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
component fp_invsqr_core IS
GENERIC (synthesize : integer := 1); -- 0/1
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radicand : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
odd : IN STD_LOGIC;
invroot : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
gzva: FOR k IN 1 TO manwidth GENERATE
zerovec(k) <= '0';
END GENERATE;
gxoa: FOR k IN 1 TO expwidth-1 GENERATE
offset(k) <= '1';
END GENERATE;
offset(expwidth) <= '0';
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO coredepth LOOP
FOR j IN 1 TO expwidth LOOP
expff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
expff(1)(expwidth DOWNTO 1) <= exponentin;
expff(2)(expwidth DOWNTO 1) <= expff(1)(expwidth DOWNTO 1) - offset;
expff(3)(expwidth DOWNTO 1) <= expff(2)(expwidth) & expff(2)(expwidth DOWNTO 2);
expff(4)(expwidth DOWNTO 1) <= offset - expff(3)(expwidth DOWNTO 1);
expff(5)(expwidth DOWNTO 1) <= expff(4)(expwidth DOWNTO 1) - 1;
FOR k IN 6 TO coredepth LOOP
expff(k)(expwidth DOWNTO 1) <= expff(k-1)(expwidth DOWNTO 1);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** SQUARE ROOT ***
--*******************
radicand <= mantissain; -- already with leading '1'
-- sub 127, so 127 (odd) = 2^0 => even
oddexponent <= NOT(exponentin(1));
-- does not require rounding, output of core rounded already, LSB always 0
isqr: fp_invsqr_core
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
radicand=>radicand,odd=>oddexponent,
invroot=>invroot);
--***************
--*** OUTPUTS ***
--***************
exponentout <= expff(coredepth)(expwidth DOWNTO 1);
mantissaout <= invroot;
END rtl;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
bin_Gray_Processing/ip/Gray_Processing/CosPiDPStratixVf400_safe_path.vhd
|
10
|
437
|
-- safe_path for CosPiDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE CosPiDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END CosPiDPStratixVf400_safe_path;
PACKAGE body CosPiDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./") & path;
END FUNCTION safe_path;
END CosPiDPStratixVf400_safe_path;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
Gray_Processing/ip/Gray_Processing/CosPiDPStratixVf400_safe_path.vhd
|
10
|
437
|
-- safe_path for CosPiDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE CosPiDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END CosPiDPStratixVf400_safe_path;
PACKAGE body CosPiDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./") & path;
END FUNCTION safe_path;
END CosPiDPStratixVf400_safe_path;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
bin_Gray_Processing/ip/Gray_Processing/fp_mul54us_28s.vhd
|
10
|
10055
|
LIBRARY ieee;
LIBRARY work;
LIBRARY lpm;
LIBRARY altera_mf;
USE lpm.all;
USE altera_mf.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FP_MUL54US_28S.VHD ***
--*** ***
--*** Function: 5/6 pipeline stage unsigned 54 ***
--*** bit multiplier ***
--*** 28S: Stratix 2, 8 18x18, synthesizeable ***
--*** ***
--*** 21/04/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. Identical to HCC_MUL54US_28S, except 5 ***
--*** or 6 pipeline parameter and 72 outputs ***
--***************************************************
ENTITY fp_mul54us_28s IS
GENERIC (latency : positive := 5);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (72 DOWNTO 1)
);
END fp_mul54us_28s;
ARCHITECTURE syn of fp_mul54us_28s IS
signal muloneaa, mulonebb : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multwoaa, multwobb, multhraa, multhrbb : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal mulforaa, mulforbb, mulfivaa, mulfivbb : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal muloneout : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal multwoout, multhrout, mulforout, mulfivout : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal vecone, vectwo, vecthr, vecfor, vecfiv : STD_LOGIC_VECTOR (58 DOWNTO 1);
signal vecsix, vecsev : STD_LOGIC_VECTOR (58 DOWNTO 1);
signal vecegt, vecnin, vecten : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumvecone, carvecone : STD_LOGIC_VECTOR (58 DOWNTO 1);
signal sumvectwo, carvectwo : STD_LOGIC_VECTOR (58 DOWNTO 1);
signal sumvecthr, carvecthr : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumoneff, caroneff : STD_LOGIC_VECTOR (58 DOWNTO 1);
signal sumtwoff, cartwoff : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal resultnode : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
component altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (width_b-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (width_result-1 DOWNTO 0)
);
end component;
-- identical component to that above, but fixed at 18x18, latency 2
-- mul18usus generated by Quartus
component hcc_mul18usus
PORT
(
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
end component;
COMPONENT lpm_add_sub
GENERIC (
lpm_direction : STRING;
lpm_hint : STRING;
lpm_pipeline : NATURAL;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (71 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (71 DOWNTO 0);
clken : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (71 DOWNTO 0)
);
END COMPONENT;
BEGIN
gza: FOR k IN 1 TO 36 GENERATE
zerovec(k) <= '0';
END GENERATE;
muloneaa <= mulaa(54 DOWNTO 19);
mulonebb <= mulbb(54 DOWNTO 19);
multwoaa <= mulaa(18 DOWNTO 1);
multwobb <= mulbb(36 DOWNTO 19);
multhraa <= mulaa(18 DOWNTO 1);
multhrbb <= mulbb(54 DOWNTO 37);
mulforaa <= mulbb(18 DOWNTO 1);
mulforbb <= mulaa(36 DOWNTO 19);
mulfivaa <= mulbb(18 DOWNTO 1);
mulfivbb <= mulaa(54 DOWNTO 37);
-- {A,C) * {B,D}
-- AAC
-- BBD
-- AA*BB 36x36=72, latency 3
mulone : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 36,
width_b => 36,
width_result => 72
)
PORT MAP (
dataa => muloneaa,
datab => mulonebb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => muloneout
);
-- Blo*C 18*18 = 36, latency = 2
multwo: hcc_mul18usus
PORT MAP (
dataa_0 => multwoaa,
datab_0 => multwobb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => multwoout
);
-- Bhi*C 18*18 = 36, latency = 2
multhr: hcc_mul18usus
PORT MAP (
dataa_0 => multhraa,
datab_0 => multhrbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => multhrout
);
-- Alo*D 18*18 = 36, latency = 2
mulfor: hcc_mul18usus
PORT MAP (
dataa_0 => mulforaa,
datab_0 => mulforbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulforout
);
-- Ahi*D 18*18 = 36, latency = 2
mulfiv: hcc_mul18usus
PORT MAP (
dataa_0 => mulfivaa,
datab_0 => mulfivbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulfivout
);
vecone <= zerovec(22 DOWNTO 1) & multwoout;
vectwo <= zerovec(4 DOWNTO 1) & multhrout & zerovec(18 DOWNTO 1);
vecthr <= zerovec(22 DOWNTO 1) & mulforout;
vecfor <= zerovec(4 DOWNTO 1) & mulfivout & zerovec(18 DOWNTO 1);
gva: FOR k IN 1 TO 58 GENERATE
sumvecone(k) <= vecone(k) XOR vectwo(k) XOR vecthr(k);
carvecone(k) <= (vecone(k) AND vectwo(k)) OR
(vectwo(k) AND vecthr(k)) OR
(vecone(k) AND vecthr(k));
END GENERATE;
vecfiv <= vecfor;
vecsix <= sumvecone;
vecsev <= carvecone(57 DOWNTO 1) & '0';
gvb: FOR k IN 1 TO 58 GENERATE
sumvectwo(k) <= vecfiv(k) XOR vecsix(k) XOR vecsev(k);
carvectwo(k) <= (vecfiv(k) AND vecsix(k)) OR
(vecsix(k) AND vecsev(k)) OR
(vecfiv(k) AND vecsev(k));
END GENERATE;
paa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 58 LOOP
sumoneff(k) <= '0';
caroneff(k) <= '0';
END LOOP;
FOR k IN 1 TO 72 LOOP
sumtwoff(k) <= '0';
cartwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
sumoneff <= sumvectwo;
caroneff <= carvectwo(57 DOWNTO 1) & '0';
sumtwoff <= sumvecthr;
cartwoff <= carvecthr(71 DOWNTO 1) & '0';
END IF;
END IF;
END PROCESS;
vecegt <= zerovec(32 DOWNTO 1) & sumoneff(58 DOWNTO 19);
vecnin <= zerovec(32 DOWNTO 1) & caroneff(58 DOWNTO 19);
vecten <= muloneout(72 DOWNTO 1);
vecten <= muloneout(72 DOWNTO 1);
gvc: FOR k IN 1 TO 72 GENERATE
sumvecthr(k) <= vecegt(k) XOR vecnin(k) XOR vecten(k);
carvecthr(k) <= (vecegt(k) AND vecnin(k)) OR
(vecnin(k) AND vecten(k)) OR
(vecegt(k) AND vecten(k));
END GENERATE;
adder : lpm_add_sub
GENERIC MAP (
lpm_direction => "ADD",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO",
lpm_pipeline => latency-4,
lpm_type => "LPM_ADD_SUB",
lpm_width => 72
)
PORT MAP (
dataa => sumtwoff(72 DOWNTO 1),
datab => cartwoff(72 DOWNTO 1),
clken => enable,
aclr => reset,
clock => sysclk,
result => resultnode
);
mulcc <= resultnode;
END syn;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
bin_Gray_Processing/ip/Gray_Processing/fp_mul54us_38s.vhd
|
10
|
3962
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FP_MUL54US_38S.VHD ***
--*** ***
--*** Function: 4 pipeline stage unsigned 54 ***
--*** bit multiplier ***
--*** 38S: Stratix 3, 8 18x18, synthesizeable ***
--*** ***
--*** 20/08/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Build explicitlyout of two SIII/SIV ***
--*** DSP Blocks ***
--***************************************************
ENTITY fp_mul54us_38s IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (72 DOWNTO 1)
);
END fp_mul54us_38s;
ARCHITECTURE rtl OF fp_mul54us_38s IS
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multone : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal multtwo : STD_LOGIC_VECTOR (55 DOWNTO 1);
signal addmultff : STD_LOGIC_VECTOR (72 DOWNTO 1);
component fp_mul3s
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_sum36x18
PORT (
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
dataa_1 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (35 DOWNTO 0) := (OTHERS => '0');
datab_1 : IN STD_LOGIC_VECTOR (35 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (54 DOWNTO 0)
);
end component;
BEGIN
gza: FOR k IN 1 TO 36 GENERATE
zerovec(k) <= '0';
END GENERATE;
mone: fp_mul3s
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>72)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>mulaa(54 DOWNTO 19),databb=>mulbb(54 DOWNTO 19),
result=>multone);
mtwo: fp_sum36x18
PORT MAP (aclr3=>reset,clock0=>sysclk,
dataa_0=>mulaa(18 DOWNTO 1),
dataa_1=>mulbb(18 DOWNTO 1),
datab_0=>mulbb(54 DOWNTO 19),
datab_1=>mulaa(54 DOWNTO 19),
ena0=>enable,
result=>multtwo);
paa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 72 LOOP
addmultff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
addmultff <= multone + (zerovec(35 DOWNTO 1) & multtwo(55 DOWNTO 19));
END IF;
END IF;
END PROCESS;
mulcc <= addmultff;
END rtl;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
bin_Gray_Processing/ip/Gray_Processing/dspba_library_package_sv.vhd
|
22
|
1323
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
package dspba_library_package is
component dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end component;
end dspba_library_package;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
bin_Gray_Processing/ip/Gray_Processing/dp_clz64.vhd
|
10
|
6582
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ***
--*** DP_CLZ64.VHD ***
--*** ***
--*** Function: Combinatorial Count Leading ***
--*** Zeroes (64 bits) ***
--*** ***
--*** 01/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_clz64 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END dp_clz64;
ARCHITECTURE rtl of dp_clz64 IS
type positiontype IS ARRAY (11 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position, positionmux : positiontype;
signal zerogroup, firstzero : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal lastman : STD_LOGIC_VECTOR (6 DOWNTO 1);
component dp_pos
GENERIC (start: integer := 0);
PORT
(
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
zerogroup(1) <= mantissa(64) OR mantissa(63) OR mantissa(62) OR mantissa(61) OR mantissa(60) OR mantissa(59);
zerogroup(2) <= mantissa(58) OR mantissa(57) OR mantissa(56) OR mantissa(55) OR mantissa(54) OR mantissa(53);
zerogroup(3) <= mantissa(52) OR mantissa(51) OR mantissa(50) OR mantissa(49) OR mantissa(48) OR mantissa(47);
zerogroup(4) <= mantissa(46) OR mantissa(45) OR mantissa(44) OR mantissa(43) OR mantissa(42) OR mantissa(41);
zerogroup(5) <= mantissa(40) OR mantissa(39) OR mantissa(38) OR mantissa(37) OR mantissa(36) OR mantissa(35);
zerogroup(6) <= mantissa(34) OR mantissa(33) OR mantissa(32) OR mantissa(31) OR mantissa(30) OR mantissa(29);
zerogroup(7) <= mantissa(28) OR mantissa(27) OR mantissa(26) OR mantissa(25) OR mantissa(24) OR mantissa(23);
zerogroup(8) <= mantissa(22) OR mantissa(21) OR mantissa(20) OR mantissa(19) OR mantissa(18) OR mantissa(17);
zerogroup(9) <= mantissa(16) OR mantissa(15) OR mantissa(14) OR mantissa(13) OR mantissa(12) OR mantissa(11);
zerogroup(10) <= mantissa(10) OR mantissa(9) OR mantissa(8) OR mantissa(7) OR mantissa(6) OR mantissa(5);
zerogroup(11) <= mantissa(4) OR mantissa(3) OR mantissa(2) OR mantissa(1);
lastman <= mantissa(4 DOWNTO 1) & "00";
pone: dp_pos
GENERIC MAP (start=>60)
PORT MAP (ingroup=>lastman,position=>position(11)(6 DOWNTO 1));
ptwo: dp_pos
GENERIC MAP (start=>54)
PORT MAP (ingroup=>mantissa(10 DOWNTO 5),position=>position(10)(6 DOWNTO 1));
pthr: dp_pos
GENERIC MAP (start=>48)
PORT MAP (ingroup=>mantissa(16 DOWNTO 11),position=>position(9)(6 DOWNTO 1));
pfor: dp_pos
GENERIC MAP (start=>42)
PORT MAP (ingroup=>mantissa(22 DOWNTO 17),position=>position(8)(6 DOWNTO 1));
pfiv: dp_pos
GENERIC MAP (start=>36)
PORT MAP (ingroup=>mantissa(28 DOWNTO 23),position=>position(7)(6 DOWNTO 1));
psix: dp_pos
GENERIC MAP (start=>30)
PORT MAP (ingroup=>mantissa(34 DOWNTO 29),position=>position(6)(6 DOWNTO 1));
psev: dp_pos
GENERIC MAP (start=>24)
PORT MAP (ingroup=>mantissa(40 DOWNTO 35),position=>position(5)(6 DOWNTO 1));
pegt: dp_pos
GENERIC MAP (start=>18)
PORT MAP (ingroup=>mantissa(46 DOWNTO 41),position=>position(4)(6 DOWNTO 1));
pnin: dp_pos
GENERIC MAP (start=>12)
PORT MAP (ingroup=>mantissa(52 DOWNTO 47),position=>position(3)(6 DOWNTO 1));
pten: dp_pos
GENERIC MAP (start=>6)
PORT MAP (ingroup=>mantissa(58 DOWNTO 53),position=>position(2)(6 DOWNTO 1));
pelv: dp_pos
GENERIC MAP (start=>0)
PORT MAP (ingroup=>mantissa(64 DOWNTO 59),position=>position(1)(6 DOWNTO 1));
firstzero(1) <= zerogroup(1);
firstzero(2) <= NOT(zerogroup(1)) AND zerogroup(2);
firstzero(3) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND zerogroup(3);
firstzero(4) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND zerogroup(4);
firstzero(5) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND zerogroup(5);
firstzero(6) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND zerogroup(6);
firstzero(7) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND zerogroup(7);
firstzero(8) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND NOT(zerogroup(7)) AND zerogroup(8);
firstzero(9) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND NOT(zerogroup(7)) AND NOT(zerogroup(8))
AND zerogroup(9);
firstzero(10) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND NOT(zerogroup(7)) AND NOT(zerogroup(8))
AND NOT(zerogroup(9)) AND zerogroup(10);
firstzero(11) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND NOT(zerogroup(6)) AND NOT(zerogroup(7)) AND NOT(zerogroup(8))
AND NOT(zerogroup(9)) AND NOT(zerogroup(10)) AND zerogroup(11);
gma: FOR k IN 1 TO 6 GENERATE
positionmux(1)(k) <= position(1)(k) AND firstzero(1);
gmb: FOR j IN 2 TO 11 GENERATE
positionmux(j)(k) <= positionmux(j-1)(k) OR (position(j)(k) AND firstzero(j));
END GENERATE;
END GENERATE;
leading <= positionmux(11)(6 DOWNTO 1);
END rtl;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
bin_Gray_Processing/ip/Gray_Processing/dp_explut10.vhd
|
10
|
174445
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_EXPLUT10.VHD ***
--*** ***
--*** Function: Look Up Table - EXP() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_explut10 IS
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1);
exponent : OUT STD_LOGIC
);
END dp_explut10;
ARCHITECTURE rtl OF dp_explut10 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "0000000000" =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
exponent <= '0';
WHEN "0000000001" =>
manhi <= conv_std_logic_vector(16392,24);
manlo <= conv_std_logic_vector(699221,28);
exponent <= '0';
WHEN "0000000010" =>
manhi <= conv_std_logic_vector(32800,24);
manlo <= conv_std_logic_vector(5595137,28);
exponent <= '0';
WHEN "0000000011" =>
manhi <= conv_std_logic_vector(49224,24);
manlo <= conv_std_logic_vector(18888200,28);
exponent <= '0';
WHEN "0000000100" =>
manhi <= conv_std_logic_vector(65664,24);
manlo <= conv_std_logic_vector(44782967,28);
exponent <= '0';
WHEN "0000000101" =>
manhi <= conv_std_logic_vector(82120,24);
manlo <= conv_std_logic_vector(87488104,28);
exponent <= '0';
WHEN "0000000110" =>
manhi <= conv_std_logic_vector(98592,24);
manlo <= conv_std_logic_vector(151216387,28);
exponent <= '0';
WHEN "0000000111" =>
manhi <= conv_std_logic_vector(115080,24);
manlo <= conv_std_logic_vector(240184710,28);
exponent <= '0';
WHEN "0000001000" =>
manhi <= conv_std_logic_vector(131585,24);
manlo <= conv_std_logic_vector(90178630,28);
exponent <= '0';
WHEN "0000001001" =>
manhi <= conv_std_logic_vector(148105,24);
manlo <= conv_std_logic_vector(242294195,28);
exponent <= '0';
WHEN "0000001010" =>
manhi <= conv_std_logic_vector(164642,24);
manlo <= conv_std_logic_vector(163889760,28);
exponent <= '0';
WHEN "0000001011" =>
manhi <= conv_std_logic_vector(181195,24);
manlo <= conv_std_logic_vector(127634178,28);
exponent <= '0';
WHEN "0000001100" =>
manhi <= conv_std_logic_vector(197764,24);
manlo <= conv_std_logic_vector(137764983,28);
exponent <= '0';
WHEN "0000001101" =>
manhi <= conv_std_logic_vector(214349,24);
manlo <= conv_std_logic_vector(198523848,28);
exponent <= '0';
WHEN "0000001110" =>
manhi <= conv_std_logic_vector(230951,24);
manlo <= conv_std_logic_vector(45721136,28);
exponent <= '0';
WHEN "0000001111" =>
manhi <= conv_std_logic_vector(247568,24);
manlo <= conv_std_logic_vector(220477726,28);
exponent <= '0';
WHEN "0000010000" =>
manhi <= conv_std_logic_vector(264202,24);
manlo <= conv_std_logic_vector(190176825,28);
exponent <= '0';
WHEN "0000010001" =>
manhi <= conv_std_logic_vector(280852,24);
manlo <= conv_std_logic_vector(227512164,28);
exponent <= '0';
WHEN "0000010010" =>
manhi <= conv_std_logic_vector(297519,24);
manlo <= conv_std_logic_vector(68310723,28);
exponent <= '0';
WHEN "0000010011" =>
manhi <= conv_std_logic_vector(314201,24);
manlo <= conv_std_logic_vector(253710014,28);
exponent <= '0';
WHEN "0000010100" =>
manhi <= conv_std_logic_vector(330900,24);
manlo <= conv_std_logic_vector(251109895,28);
exponent <= '0';
WHEN "0000010101" =>
manhi <= conv_std_logic_vector(347616,24);
manlo <= conv_std_logic_vector(64785307,28);
exponent <= '0';
WHEN "0000010110" =>
manhi <= conv_std_logic_vector(364347,24);
manlo <= conv_std_logic_vector(235886282,28);
exponent <= '0';
WHEN "0000010111" =>
manhi <= conv_std_logic_vector(381095,24);
manlo <= conv_std_logic_vector(231825206,28);
exponent <= '0';
WHEN "0000011000" =>
manhi <= conv_std_logic_vector(397860,24);
manlo <= conv_std_logic_vector(56889565,28);
exponent <= '0';
WHEN "0000011001" =>
manhi <= conv_std_logic_vector(414640,24);
manlo <= conv_std_logic_vector(252241943,28);
exponent <= '0';
WHEN "0000011010" =>
manhi <= conv_std_logic_vector(431438,24);
manlo <= conv_std_logic_vector(16871840,28);
exponent <= '0';
WHEN "0000011011" =>
manhi <= conv_std_logic_vector(448251,24);
manlo <= conv_std_logic_vector(160385687,28);
exponent <= '0';
WHEN "0000011100" =>
manhi <= conv_std_logic_vector(465081,24);
manlo <= conv_std_logic_vector(150216837,28);
exponent <= '0';
WHEN "0000011101" =>
manhi <= conv_std_logic_vector(481927,24);
manlo <= conv_std_logic_vector(259109217,28);
exponent <= '0';
WHEN "0000011110" =>
manhi <= conv_std_logic_vector(498790,24);
manlo <= conv_std_logic_vector(222940052,28);
exponent <= '0';
WHEN "0000011111" =>
manhi <= conv_std_logic_vector(515670,24);
manlo <= conv_std_logic_vector(46026234,28);
exponent <= '0';
WHEN "0000100000" =>
manhi <= conv_std_logic_vector(532566,24);
manlo <= conv_std_logic_vector(1124333,28);
exponent <= '0';
WHEN "0000100001" =>
manhi <= conv_std_logic_vector(549478,24);
manlo <= conv_std_logic_vector(92559680,28);
exponent <= '0';
WHEN "0000100010" =>
manhi <= conv_std_logic_vector(566407,24);
manlo <= conv_std_logic_vector(56226380,28);
exponent <= '0';
WHEN "0000100011" =>
manhi <= conv_std_logic_vector(583352,24);
manlo <= conv_std_logic_vector(164893679,28);
exponent <= '0';
WHEN "0000100100" =>
manhi <= conv_std_logic_vector(600314,24);
manlo <= conv_std_logic_vector(154464145,28);
exponent <= '0';
WHEN "0000100101" =>
manhi <= conv_std_logic_vector(617293,24);
manlo <= conv_std_logic_vector(29280039,28);
exponent <= '0';
WHEN "0000100110" =>
manhi <= conv_std_logic_vector(634288,24);
manlo <= conv_std_logic_vector(62123323,28);
exponent <= '0';
WHEN "0000100111" =>
manhi <= conv_std_logic_vector(651299,24);
manlo <= conv_std_logic_vector(257344748,28);
exponent <= '0';
WHEN "0000101000" =>
manhi <= conv_std_logic_vector(668328,24);
manlo <= conv_std_logic_vector(82428406,28);
exponent <= '0';
WHEN "0000101001" =>
manhi <= conv_std_logic_vector(685373,24);
manlo <= conv_std_logic_vector(78604464,28);
exponent <= '0';
WHEN "0000101010" =>
manhi <= conv_std_logic_vector(702434,24);
manlo <= conv_std_logic_vector(250236442,28);
exponent <= '0';
WHEN "0000101011" =>
manhi <= conv_std_logic_vector(719513,24);
manlo <= conv_std_logic_vector(64821205,28);
exponent <= '0';
WHEN "0000101100" =>
manhi <= conv_std_logic_vector(736608,24);
manlo <= conv_std_logic_vector(63601714,28);
exponent <= '0';
WHEN "0000101101" =>
manhi <= conv_std_logic_vector(753719,24);
manlo <= conv_std_logic_vector(250954289,28);
exponent <= '0';
WHEN "0000101110" =>
manhi <= conv_std_logic_vector(770848,24);
manlo <= conv_std_logic_vector(94388611,28);
exponent <= '0';
WHEN "0000101111" =>
manhi <= conv_std_logic_vector(787993,24);
manlo <= conv_std_logic_vector(135160468,28);
exponent <= '0';
WHEN "0000110000" =>
manhi <= conv_std_logic_vector(805155,24);
manlo <= conv_std_logic_vector(109223564,28);
exponent <= '0';
WHEN "0000110001" =>
manhi <= conv_std_logic_vector(822334,24);
manlo <= conv_std_logic_vector(20971345,28);
exponent <= '0';
WHEN "0000110010" =>
manhi <= conv_std_logic_vector(839529,24);
manlo <= conv_std_logic_vector(143237009,28);
exponent <= '0';
WHEN "0000110011" =>
manhi <= conv_std_logic_vector(856741,24);
manlo <= conv_std_logic_vector(211987135,28);
exponent <= '0';
WHEN "0000110100" =>
manhi <= conv_std_logic_vector(873970,24);
manlo <= conv_std_logic_vector(231628063,28);
exponent <= '0';
WHEN "0000110101" =>
manhi <= conv_std_logic_vector(891216,24);
manlo <= conv_std_logic_vector(206570434,28);
exponent <= '0';
WHEN "0000110110" =>
manhi <= conv_std_logic_vector(908479,24);
manlo <= conv_std_logic_vector(141229202,28);
exponent <= '0';
WHEN "0000110111" =>
manhi <= conv_std_logic_vector(925759,24);
manlo <= conv_std_logic_vector(40023632,28);
exponent <= '0';
WHEN "0000111000" =>
manhi <= conv_std_logic_vector(943055,24);
manlo <= conv_std_logic_vector(175812765,28);
exponent <= '0';
WHEN "0000111001" =>
manhi <= conv_std_logic_vector(960369,24);
manlo <= conv_std_logic_vector(16153594,28);
exponent <= '0';
WHEN "0000111010" =>
manhi <= conv_std_logic_vector(977699,24);
manlo <= conv_std_logic_vector(102349263,28);
exponent <= '0';
WHEN "0000111011" =>
manhi <= conv_std_logic_vector(995046,24);
manlo <= conv_std_logic_vector(170400879,28);
exponent <= '0';
WHEN "0000111100" =>
manhi <= conv_std_logic_vector(1012410,24);
manlo <= conv_std_logic_vector(224749339,28);
exponent <= '0';
WHEN "0000111101" =>
manhi <= conv_std_logic_vector(1029792,24);
manlo <= conv_std_logic_vector(1404424,28);
exponent <= '0';
WHEN "0000111110" =>
manhi <= conv_std_logic_vector(1047190,24);
manlo <= conv_std_logic_vector(41686624,28);
exponent <= '0';
WHEN "0000111111" =>
manhi <= conv_std_logic_vector(1064605,24);
manlo <= conv_std_logic_vector(81614410,28);
exponent <= '0';
WHEN "0001000000" =>
manhi <= conv_std_logic_vector(1082037,24);
manlo <= conv_std_logic_vector(125646062,28);
exponent <= '0';
WHEN "0001000001" =>
manhi <= conv_std_logic_vector(1099486,24);
manlo <= conv_std_logic_vector(178244212,28);
exponent <= '0';
WHEN "0001000010" =>
manhi <= conv_std_logic_vector(1116952,24);
manlo <= conv_std_logic_vector(243875856,28);
exponent <= '0';
WHEN "0001000011" =>
manhi <= conv_std_logic_vector(1134436,24);
manlo <= conv_std_logic_vector(58576897,28);
exponent <= '0';
WHEN "0001000100" =>
manhi <= conv_std_logic_vector(1151936,24);
manlo <= conv_std_logic_vector(163693974,28);
exponent <= '0';
WHEN "0001000101" =>
manhi <= conv_std_logic_vector(1169454,24);
manlo <= conv_std_logic_vector(26836276,28);
exponent <= '0';
WHEN "0001000110" =>
manhi <= conv_std_logic_vector(1186988,24);
manlo <= conv_std_logic_vector(189359192,28);
exponent <= '0';
WHEN "0001000111" =>
manhi <= conv_std_logic_vector(1204540,24);
manlo <= conv_std_logic_vector(118880671,28);
exponent <= '0';
WHEN "0001001000" =>
manhi <= conv_std_logic_vector(1222109,24);
manlo <= conv_std_logic_vector(88329413,28);
exponent <= '0';
WHEN "0001001001" =>
manhi <= conv_std_logic_vector(1239695,24);
manlo <= conv_std_logic_vector(102203053,28);
exponent <= '0';
WHEN "0001001010" =>
manhi <= conv_std_logic_vector(1257298,24);
manlo <= conv_std_logic_vector(165003622,28);
exponent <= '0';
WHEN "0001001011" =>
manhi <= conv_std_logic_vector(1274919,24);
manlo <= conv_std_logic_vector(12802090,28);
exponent <= '0';
WHEN "0001001100" =>
manhi <= conv_std_logic_vector(1292556,24);
manlo <= conv_std_logic_vector(186980202,28);
exponent <= '0';
WHEN "0001001101" =>
manhi <= conv_std_logic_vector(1310211,24);
manlo <= conv_std_logic_vector(155182284,28);
exponent <= '0';
WHEN "0001001110" =>
manhi <= conv_std_logic_vector(1327883,24);
manlo <= conv_std_logic_vector(190363442,28);
exponent <= '0';
WHEN "0001001111" =>
manhi <= conv_std_logic_vector(1345573,24);
manlo <= conv_std_logic_vector(28612286,28);
exponent <= '0';
WHEN "0001010000" =>
manhi <= conv_std_logic_vector(1363279,24);
manlo <= conv_std_logic_vector(211328214,28);
exponent <= '0';
WHEN "0001010001" =>
manhi <= conv_std_logic_vector(1381003,24);
manlo <= conv_std_logic_vector(206173225,28);
exponent <= '0';
WHEN "0001010010" =>
manhi <= conv_std_logic_vector(1398745,24);
manlo <= conv_std_logic_vector(17684657,28);
exponent <= '0';
WHEN "0001010011" =>
manhi <= conv_std_logic_vector(1416503,24);
manlo <= conv_std_logic_vector(187275197,28);
exponent <= '0';
WHEN "0001010100" =>
manhi <= conv_std_logic_vector(1434279,24);
manlo <= conv_std_logic_vector(182620141,28);
exponent <= '0';
WHEN "0001010101" =>
manhi <= conv_std_logic_vector(1452073,24);
manlo <= conv_std_logic_vector(8270141,28);
exponent <= '0';
WHEN "0001010110" =>
manhi <= conv_std_logic_vector(1469883,24);
manlo <= conv_std_logic_vector(205651209,28);
exponent <= '0';
WHEN "0001010111" =>
manhi <= conv_std_logic_vector(1487711,24);
manlo <= conv_std_logic_vector(242451980,28);
exponent <= '0';
WHEN "0001011000" =>
manhi <= conv_std_logic_vector(1505557,24);
manlo <= conv_std_logic_vector(123236457,28);
exponent <= '0';
WHEN "0001011001" =>
manhi <= conv_std_logic_vector(1523420,24);
manlo <= conv_std_logic_vector(121008560,28);
exponent <= '0';
WHEN "0001011010" =>
manhi <= conv_std_logic_vector(1541300,24);
manlo <= conv_std_logic_vector(240341215,28);
exponent <= '0';
WHEN "0001011011" =>
manhi <= conv_std_logic_vector(1559198,24);
manlo <= conv_std_logic_vector(217376360,28);
exponent <= '0';
WHEN "0001011100" =>
manhi <= conv_std_logic_vector(1577114,24);
manlo <= conv_std_logic_vector(56695861,28);
exponent <= '0';
WHEN "0001011101" =>
manhi <= conv_std_logic_vector(1595047,24);
manlo <= conv_std_logic_vector(31321518,28);
exponent <= '0';
WHEN "0001011110" =>
manhi <= conv_std_logic_vector(1612997,24);
manlo <= conv_std_logic_vector(145844154,28);
exponent <= '0';
WHEN "0001011111" =>
manhi <= conv_std_logic_vector(1630965,24);
manlo <= conv_std_logic_vector(136423623,28);
exponent <= '0';
WHEN "0001100000" =>
manhi <= conv_std_logic_vector(1648951,24);
manlo <= conv_std_logic_vector(7659725,28);
exponent <= '0';
WHEN "0001100001" =>
manhi <= conv_std_logic_vector(1666954,24);
manlo <= conv_std_logic_vector(32592210,28);
exponent <= '0';
WHEN "0001100010" =>
manhi <= conv_std_logic_vector(1684974,24);
manlo <= conv_std_logic_vector(215829868,28);
exponent <= '0';
WHEN "0001100011" =>
manhi <= conv_std_logic_vector(1703013,24);
manlo <= conv_std_logic_vector(25115084,28);
exponent <= '0';
WHEN "0001100100" =>
manhi <= conv_std_logic_vector(1721069,24);
manlo <= conv_std_logic_vector(1936572,28);
exponent <= '0';
WHEN "0001100101" =>
manhi <= conv_std_logic_vector(1739142,24);
manlo <= conv_std_logic_vector(150916647,28);
exponent <= '0';
WHEN "0001100110" =>
manhi <= conv_std_logic_vector(1757233,24);
manlo <= conv_std_logic_vector(208246681,28);
exponent <= '0';
WHEN "0001100111" =>
manhi <= conv_std_logic_vector(1775342,24);
manlo <= conv_std_logic_vector(178558028,28);
exponent <= '0';
WHEN "0001101000" =>
manhi <= conv_std_logic_vector(1793469,24);
manlo <= conv_std_logic_vector(66486562,28);
exponent <= '0';
WHEN "0001101001" =>
manhi <= conv_std_logic_vector(1811613,24);
manlo <= conv_std_logic_vector(145108146,28);
exponent <= '0';
WHEN "0001101010" =>
manhi <= conv_std_logic_vector(1829775,24);
manlo <= conv_std_logic_vector(150632262,28);
exponent <= '0';
WHEN "0001101011" =>
manhi <= conv_std_logic_vector(1847955,24);
manlo <= conv_std_logic_vector(87708388,28);
exponent <= '0';
WHEN "0001101100" =>
manhi <= conv_std_logic_vector(1866152,24);
manlo <= conv_std_logic_vector(229426001,28);
exponent <= '0';
WHEN "0001101101" =>
manhi <= conv_std_logic_vector(1884368,24);
manlo <= conv_std_logic_vector(43572756,28);
exponent <= '0';
WHEN "0001101110" =>
manhi <= conv_std_logic_vector(1902601,24);
manlo <= conv_std_logic_vector(71682684,28);
exponent <= '0';
WHEN "0001101111" =>
manhi <= conv_std_logic_vector(1920852,24);
manlo <= conv_std_logic_vector(49988005,28);
exponent <= '0';
WHEN "0001110000" =>
manhi <= conv_std_logic_vector(1939120,24);
manlo <= conv_std_logic_vector(251596409,28);
exponent <= '0';
WHEN "0001110001" =>
manhi <= conv_std_logic_vector(1957407,24);
manlo <= conv_std_logic_vector(144313787,28);
exponent <= '0';
WHEN "0001110010" =>
manhi <= conv_std_logic_vector(1975712,24);
manlo <= conv_std_logic_vector(1256963,28);
exponent <= '0';
WHEN "0001110011" =>
manhi <= conv_std_logic_vector(1994034,24);
manlo <= conv_std_logic_vector(95547338,28);
exponent <= '0';
WHEN "0001110100" =>
manhi <= conv_std_logic_vector(2012374,24);
manlo <= conv_std_logic_vector(163439978,28);
exponent <= '0';
WHEN "0001110101" =>
manhi <= conv_std_logic_vector(2030732,24);
manlo <= conv_std_logic_vector(209629988,28);
exponent <= '0';
WHEN "0001110110" =>
manhi <= conv_std_logic_vector(2049108,24);
manlo <= conv_std_logic_vector(238817060,28);
exponent <= '0';
WHEN "0001110111" =>
manhi <= conv_std_logic_vector(2067502,24);
manlo <= conv_std_logic_vector(255705480,28);
exponent <= '0';
WHEN "0001111000" =>
manhi <= conv_std_logic_vector(2085914,24);
manlo <= conv_std_logic_vector(265004126,28);
exponent <= '0';
WHEN "0001111001" =>
manhi <= conv_std_logic_vector(2104345,24);
manlo <= conv_std_logic_vector(2991026,28);
exponent <= '0';
WHEN "0001111010" =>
manhi <= conv_std_logic_vector(2122793,24);
manlo <= conv_std_logic_vector(11255176,28);
exponent <= '0';
WHEN "0001111011" =>
manhi <= conv_std_logic_vector(2141259,24);
manlo <= conv_std_logic_vector(26083817,28);
exponent <= '0';
WHEN "0001111100" =>
manhi <= conv_std_logic_vector(2159743,24);
manlo <= conv_std_logic_vector(52204260,28);
exponent <= '0';
WHEN "0001111101" =>
manhi <= conv_std_logic_vector(2178245,24);
manlo <= conv_std_logic_vector(94348435,28);
exponent <= '0';
WHEN "0001111110" =>
manhi <= conv_std_logic_vector(2196765,24);
manlo <= conv_std_logic_vector(157252892,28);
exponent <= '0';
WHEN "0001111111" =>
manhi <= conv_std_logic_vector(2215303,24);
manlo <= conv_std_logic_vector(245658814,28);
exponent <= '0';
WHEN "0010000000" =>
manhi <= conv_std_logic_vector(2233860,24);
manlo <= conv_std_logic_vector(95876557,28);
exponent <= '0';
WHEN "0010000001" =>
manhi <= conv_std_logic_vector(2252434,24);
manlo <= conv_std_logic_vector(249527482,28);
exponent <= '0';
WHEN "0010000010" =>
manhi <= conv_std_logic_vector(2271027,24);
manlo <= conv_std_logic_vector(174495768,28);
exponent <= '0';
WHEN "0010000011" =>
manhi <= conv_std_logic_vector(2289638,24);
manlo <= conv_std_logic_vector(143976608,28);
exponent <= '0';
WHEN "0010000100" =>
manhi <= conv_std_logic_vector(2308267,24);
manlo <= conv_std_logic_vector(162734389,28);
exponent <= '0';
WHEN "0010000101" =>
manhi <= conv_std_logic_vector(2326914,24);
manlo <= conv_std_logic_vector(235538153,28);
exponent <= '0';
WHEN "0010000110" =>
manhi <= conv_std_logic_vector(2345580,24);
manlo <= conv_std_logic_vector(98726147,28);
exponent <= '0';
WHEN "0010000111" =>
manhi <= conv_std_logic_vector(2364264,24);
manlo <= conv_std_logic_vector(25512192,28);
exponent <= '0';
WHEN "0010001000" =>
manhi <= conv_std_logic_vector(2382966,24);
manlo <= conv_std_logic_vector(20679323,28);
exponent <= '0';
WHEN "0010001001" =>
manhi <= conv_std_logic_vector(2401686,24);
manlo <= conv_std_logic_vector(89015247,28);
exponent <= '0';
WHEN "0010001010" =>
manhi <= conv_std_logic_vector(2420424,24);
manlo <= conv_std_logic_vector(235312351,28);
exponent <= '0';
WHEN "0010001011" =>
manhi <= conv_std_logic_vector(2439181,24);
manlo <= conv_std_logic_vector(195932245,28);
exponent <= '0';
WHEN "0010001100" =>
manhi <= conv_std_logic_vector(2457956,24);
manlo <= conv_std_logic_vector(244112142,28);
exponent <= '0';
WHEN "0010001101" =>
manhi <= conv_std_logic_vector(2476750,24);
manlo <= conv_std_logic_vector(116223030,28);
exponent <= '0';
WHEN "0010001110" =>
manhi <= conv_std_logic_vector(2495562,24);
manlo <= conv_std_logic_vector(85511509,28);
exponent <= '0';
WHEN "0010001111" =>
manhi <= conv_std_logic_vector(2514392,24);
manlo <= conv_std_logic_vector(156793422,28);
exponent <= '0';
WHEN "0010010000" =>
manhi <= conv_std_logic_vector(2533241,24);
manlo <= conv_std_logic_vector(66453860,28);
exponent <= '0';
WHEN "0010010001" =>
manhi <= conv_std_logic_vector(2552108,24);
manlo <= conv_std_logic_vector(87753539,28);
exponent <= '0';
WHEN "0010010010" =>
manhi <= conv_std_logic_vector(2570993,24);
manlo <= conv_std_logic_vector(225522431,28);
exponent <= '0';
WHEN "0010010011" =>
manhi <= conv_std_logic_vector(2589897,24);
manlo <= conv_std_logic_vector(216159772,28);
exponent <= '0';
WHEN "0010010100" =>
manhi <= conv_std_logic_vector(2608820,24);
manlo <= conv_std_logic_vector(64504976,28);
exponent <= '0';
WHEN "0010010101" =>
manhi <= conv_std_logic_vector(2627761,24);
manlo <= conv_std_logic_vector(43837645,28);
exponent <= '0';
WHEN "0010010110" =>
manhi <= conv_std_logic_vector(2646720,24);
manlo <= conv_std_logic_vector(159006654,28);
exponent <= '0';
WHEN "0010010111" =>
manhi <= conv_std_logic_vector(2665698,24);
manlo <= conv_std_logic_vector(146430162,28);
exponent <= '0';
WHEN "0010011000" =>
manhi <= conv_std_logic_vector(2684695,24);
manlo <= conv_std_logic_vector(10966526,28);
exponent <= '0';
WHEN "0010011001" =>
manhi <= conv_std_logic_vector(2703710,24);
manlo <= conv_std_logic_vector(25914303,28);
exponent <= '0';
WHEN "0010011010" =>
manhi <= conv_std_logic_vector(2722743,24);
manlo <= conv_std_logic_vector(196141350,28);
exponent <= '0';
WHEN "0010011011" =>
manhi <= conv_std_logic_vector(2741795,24);
manlo <= conv_std_logic_vector(258084820,28);
exponent <= '0';
WHEN "0010011100" =>
manhi <= conv_std_logic_vector(2760866,24);
manlo <= conv_std_logic_vector(216622086,28);
exponent <= '0';
WHEN "0010011101" =>
manhi <= conv_std_logic_vector(2779956,24);
manlo <= conv_std_logic_vector(76635284,28);
exponent <= '0';
WHEN "0010011110" =>
manhi <= conv_std_logic_vector(2799064,24);
manlo <= conv_std_logic_vector(111446777,28);
exponent <= '0';
WHEN "0010011111" =>
manhi <= conv_std_logic_vector(2818191,24);
manlo <= conv_std_logic_vector(57512790,28);
exponent <= '0';
WHEN "0010100000" =>
manhi <= conv_std_logic_vector(2837336,24);
manlo <= conv_std_logic_vector(188165241,28);
exponent <= '0';
WHEN "0010100001" =>
manhi <= conv_std_logic_vector(2856500,24);
manlo <= conv_std_logic_vector(239869919,28);
exponent <= '0';
WHEN "0010100010" =>
manhi <= conv_std_logic_vector(2875683,24);
manlo <= conv_std_logic_vector(217532856,28);
exponent <= '0';
WHEN "0010100011" =>
manhi <= conv_std_logic_vector(2894885,24);
manlo <= conv_std_logic_vector(126064881,28);
exponent <= '0';
WHEN "0010100100" =>
manhi <= conv_std_logic_vector(2914105,24);
manlo <= conv_std_logic_vector(238817075,28);
exponent <= '0';
WHEN "0010100101" =>
manhi <= conv_std_logic_vector(2933345,24);
manlo <= conv_std_logic_vector(23838952,28);
exponent <= '0';
WHEN "0010100110" =>
manhi <= conv_std_logic_vector(2952603,24);
manlo <= conv_std_logic_vector(22926662,28);
exponent <= '0';
WHEN "0010100111" =>
manhi <= conv_std_logic_vector(2971879,24);
manlo <= conv_std_logic_vector(241010251,28);
exponent <= '0';
WHEN "0010101000" =>
manhi <= conv_std_logic_vector(2991175,24);
manlo <= conv_std_logic_vector(146153671,28);
exponent <= '0';
WHEN "0010101001" =>
manhi <= conv_std_logic_vector(3010490,24);
manlo <= conv_std_logic_vector(11732065,28);
exponent <= '0';
WHEN "0010101010" =>
manhi <= conv_std_logic_vector(3029823,24);
manlo <= conv_std_logic_vector(111125401,28);
exponent <= '0';
WHEN "0010101011" =>
manhi <= conv_std_logic_vector(3049175,24);
manlo <= conv_std_logic_vector(180847566,28);
exponent <= '0';
WHEN "0010101100" =>
manhi <= conv_std_logic_vector(3068546,24);
manlo <= conv_std_logic_vector(225852738,28);
exponent <= '0';
WHEN "0010101101" =>
manhi <= conv_std_logic_vector(3087936,24);
manlo <= conv_std_logic_vector(251099938,28);
exponent <= '0';
WHEN "0010101110" =>
manhi <= conv_std_logic_vector(3107345,24);
manlo <= conv_std_logic_vector(261553029,28);
exponent <= '0';
WHEN "0010101111" =>
manhi <= conv_std_logic_vector(3126773,24);
manlo <= conv_std_logic_vector(262180727,28);
exponent <= '0';
WHEN "0010110000" =>
manhi <= conv_std_logic_vector(3146220,24);
manlo <= conv_std_logic_vector(257956599,28);
exponent <= '0';
WHEN "0010110001" =>
manhi <= conv_std_logic_vector(3165686,24);
manlo <= conv_std_logic_vector(253859075,28);
exponent <= '0';
WHEN "0010110010" =>
manhi <= conv_std_logic_vector(3185171,24);
manlo <= conv_std_logic_vector(254871446,28);
exponent <= '0';
WHEN "0010110011" =>
manhi <= conv_std_logic_vector(3204675,24);
manlo <= conv_std_logic_vector(265981875,28);
exponent <= '0';
WHEN "0010110100" =>
manhi <= conv_std_logic_vector(3224199,24);
manlo <= conv_std_logic_vector(23747940,28);
exponent <= '0';
WHEN "0010110101" =>
manhi <= conv_std_logic_vector(3243741,24);
manlo <= conv_std_logic_vector(70038466,28);
exponent <= '0';
WHEN "0010110110" =>
manhi <= conv_std_logic_vector(3263302,24);
manlo <= conv_std_logic_vector(141420795,28);
exponent <= '0';
WHEN "0010110111" =>
manhi <= conv_std_logic_vector(3282882,24);
manlo <= conv_std_logic_vector(242902610,28);
exponent <= '0';
WHEN "0010111000" =>
manhi <= conv_std_logic_vector(3302482,24);
manlo <= conv_std_logic_vector(111061033,28);
exponent <= '0';
WHEN "0010111001" =>
manhi <= conv_std_logic_vector(3322101,24);
manlo <= conv_std_logic_vector(19348994,28);
exponent <= '0';
WHEN "0010111010" =>
manhi <= conv_std_logic_vector(3341738,24);
manlo <= conv_std_logic_vector(241224327,28);
exponent <= '0';
WHEN "0010111011" =>
manhi <= conv_std_logic_vector(3361395,24);
manlo <= conv_std_logic_vector(244843403,28);
exponent <= '0';
WHEN "0010111100" =>
manhi <= conv_std_logic_vector(3381072,24);
manlo <= conv_std_logic_vector(35238419,28);
exponent <= '0';
WHEN "0010111101" =>
manhi <= conv_std_logic_vector(3400767,24);
manlo <= conv_std_logic_vector(154317398,28);
exponent <= '0';
WHEN "0010111110" =>
manhi <= conv_std_logic_vector(3420482,24);
manlo <= conv_std_logic_vector(70251462,28);
exponent <= '0';
WHEN "0010111111" =>
manhi <= conv_std_logic_vector(3440216,24);
manlo <= conv_std_logic_vector(56523029,28);
exponent <= '0';
WHEN "0011000000" =>
manhi <= conv_std_logic_vector(3459969,24);
manlo <= conv_std_logic_vector(118183989,28);
exponent <= '0';
WHEN "0011000001" =>
manhi <= conv_std_logic_vector(3479741,24);
manlo <= conv_std_logic_vector(260291170,28);
exponent <= '0';
WHEN "0011000010" =>
manhi <= conv_std_logic_vector(3499533,24);
manlo <= conv_std_logic_vector(219470882,28);
exponent <= '0';
WHEN "0011000011" =>
manhi <= conv_std_logic_vector(3519345,24);
manlo <= conv_std_logic_vector(789841,28);
exponent <= '0';
WHEN "0011000100" =>
manhi <= conv_std_logic_vector(3539175,24);
manlo <= conv_std_logic_vector(146190621,28);
exponent <= '0';
WHEN "0011000101" =>
manhi <= conv_std_logic_vector(3559025,24);
manlo <= conv_std_logic_vector(123878930,28);
exponent <= '0';
WHEN "0011000110" =>
manhi <= conv_std_logic_vector(3578894,24);
manlo <= conv_std_logic_vector(207371803,28);
exponent <= '0';
WHEN "0011000111" =>
manhi <= conv_std_logic_vector(3598783,24);
manlo <= conv_std_logic_vector(133320328,28);
exponent <= '0';
WHEN "0011001000" =>
manhi <= conv_std_logic_vector(3618691,24);
manlo <= conv_std_logic_vector(175251474,28);
exponent <= '0';
WHEN "0011001001" =>
manhi <= conv_std_logic_vector(3638619,24);
manlo <= conv_std_logic_vector(69826275,28);
exponent <= '0';
WHEN "0011001010" =>
manhi <= conv_std_logic_vector(3658566,24);
manlo <= conv_std_logic_vector(90581653,28);
exponent <= '0';
WHEN "0011001011" =>
manhi <= conv_std_logic_vector(3678532,24);
manlo <= conv_std_logic_vector(242624062,28);
exponent <= '0';
WHEN "0011001100" =>
manhi <= conv_std_logic_vector(3698518,24);
manlo <= conv_std_logic_vector(262629486,28);
exponent <= '0';
WHEN "0011001101" =>
manhi <= conv_std_logic_vector(3718524,24);
manlo <= conv_std_logic_vector(155714362,28);
exponent <= '0';
WHEN "0011001110" =>
manhi <= conv_std_logic_vector(3738549,24);
manlo <= conv_std_logic_vector(195435578,28);
exponent <= '0';
WHEN "0011001111" =>
manhi <= conv_std_logic_vector(3758594,24);
manlo <= conv_std_logic_vector(118484119,28);
exponent <= '0';
WHEN "0011010000" =>
manhi <= conv_std_logic_vector(3778658,24);
manlo <= conv_std_logic_vector(198426886,28);
exponent <= '0';
WHEN "0011010001" =>
manhi <= conv_std_logic_vector(3798742,24);
manlo <= conv_std_logic_vector(171964885,28);
exponent <= '0';
WHEN "0011010010" =>
manhi <= conv_std_logic_vector(3818846,24);
manlo <= conv_std_logic_vector(44239595,28);
exponent <= '0';
WHEN "0011010011" =>
manhi <= conv_std_logic_vector(3838969,24);
manlo <= conv_std_logic_vector(88832973,28);
exponent <= '0';
WHEN "0011010100" =>
manhi <= conv_std_logic_vector(3859112,24);
manlo <= conv_std_logic_vector(42461096,28);
exponent <= '0';
WHEN "0011010101" =>
manhi <= conv_std_logic_vector(3879274,24);
manlo <= conv_std_logic_vector(178715983,28);
exponent <= '0';
WHEN "0011010110" =>
manhi <= conv_std_logic_vector(3899456,24);
manlo <= conv_std_logic_vector(234323781,28);
exponent <= '0';
WHEN "0011010111" =>
manhi <= conv_std_logic_vector(3919658,24);
manlo <= conv_std_logic_vector(214451135,28);
exponent <= '0';
WHEN "0011011000" =>
manhi <= conv_std_logic_vector(3939880,24);
manlo <= conv_std_logic_vector(124269738,28);
exponent <= '0';
WHEN "0011011001" =>
manhi <= conv_std_logic_vector(3960121,24);
manlo <= conv_std_logic_vector(237391794,28);
exponent <= '0';
WHEN "0011011010" =>
manhi <= conv_std_logic_vector(3980383,24);
manlo <= conv_std_logic_vector(22128194,28);
exponent <= '0';
WHEN "0011011011" =>
manhi <= conv_std_logic_vector(4000664,24);
manlo <= conv_std_logic_vector(20536717,28);
exponent <= '0';
WHEN "0011011100" =>
manhi <= conv_std_logic_vector(4020964,24);
manlo <= conv_std_logic_vector(237809299,28);
exponent <= '0';
WHEN "0011011101" =>
manhi <= conv_std_logic_vector(4041285,24);
manlo <= conv_std_logic_vector(142272034,28);
exponent <= '0';
WHEN "0011011110" =>
manhi <= conv_std_logic_vector(4061626,24);
manlo <= conv_std_logic_vector(7562465,28);
exponent <= '0';
WHEN "0011011111" =>
manhi <= conv_std_logic_vector(4081986,24);
manlo <= conv_std_logic_vector(107323215,28);
exponent <= '0';
WHEN "0011100000" =>
manhi <= conv_std_logic_vector(4102366,24);
manlo <= conv_std_logic_vector(178331084,28);
exponent <= '0';
WHEN "0011100001" =>
manhi <= conv_std_logic_vector(4122766,24);
manlo <= conv_std_logic_vector(225803419,28);
exponent <= '0';
WHEN "0011100010" =>
manhi <= conv_std_logic_vector(4143186,24);
manlo <= conv_std_logic_vector(254962667,28);
exponent <= '0';
WHEN "0011100011" =>
manhi <= conv_std_logic_vector(4163627,24);
manlo <= conv_std_logic_vector(2600920,28);
exponent <= '0';
WHEN "0011100100" =>
manhi <= conv_std_logic_vector(4184087,24);
manlo <= conv_std_logic_vector(10821746,28);
exponent <= '0';
WHEN "0011100101" =>
manhi <= conv_std_logic_vector(4204567,24);
manlo <= conv_std_logic_vector(16427456,28);
exponent <= '0';
WHEN "0011100110" =>
manhi <= conv_std_logic_vector(4225067,24);
manlo <= conv_std_logic_vector(24660936,28);
exponent <= '0';
WHEN "0011100111" =>
manhi <= conv_std_logic_vector(4245587,24);
manlo <= conv_std_logic_vector(40770196,28);
exponent <= '0';
WHEN "0011101000" =>
manhi <= conv_std_logic_vector(4266127,24);
manlo <= conv_std_logic_vector(70008370,28);
exponent <= '0';
WHEN "0011101001" =>
manhi <= conv_std_logic_vector(4286687,24);
manlo <= conv_std_logic_vector(117633727,28);
exponent <= '0';
WHEN "0011101010" =>
manhi <= conv_std_logic_vector(4307267,24);
manlo <= conv_std_logic_vector(188909673,28);
exponent <= '0';
WHEN "0011101011" =>
manhi <= conv_std_logic_vector(4327868,24);
manlo <= conv_std_logic_vector(20669300,28);
exponent <= '0';
WHEN "0011101100" =>
manhi <= conv_std_logic_vector(4348488,24);
manlo <= conv_std_logic_vector(155057216,28);
exponent <= '0';
WHEN "0011101101" =>
manhi <= conv_std_logic_vector(4369129,24);
manlo <= conv_std_logic_vector(60481357,28);
exponent <= '0';
WHEN "0011101110" =>
manhi <= conv_std_logic_vector(4389790,24);
manlo <= conv_std_logic_vector(10661187,28);
exponent <= '0';
WHEN "0011101111" =>
manhi <= conv_std_logic_vector(4410471,24);
manlo <= conv_std_logic_vector(10885873,28);
exponent <= '0';
WHEN "0011110000" =>
manhi <= conv_std_logic_vector(4431172,24);
manlo <= conv_std_logic_vector(66449753,28);
exponent <= '0';
WHEN "0011110001" =>
manhi <= conv_std_logic_vector(4451893,24);
manlo <= conv_std_logic_vector(182652336,28);
exponent <= '0';
WHEN "0011110010" =>
manhi <= conv_std_logic_vector(4472635,24);
manlo <= conv_std_logic_vector(96362852,28);
exponent <= '0';
WHEN "0011110011" =>
manhi <= conv_std_logic_vector(4493397,24);
manlo <= conv_std_logic_vector(81326629,28);
exponent <= '0';
WHEN "0011110100" =>
manhi <= conv_std_logic_vector(4514179,24);
manlo <= conv_std_logic_vector(142858724,28);
exponent <= '0';
WHEN "0011110101" =>
manhi <= conv_std_logic_vector(4534982,24);
manlo <= conv_std_logic_vector(17843933,28);
exponent <= '0';
WHEN "0011110110" =>
manhi <= conv_std_logic_vector(4555804,24);
manlo <= conv_std_logic_vector(248478616,28);
exponent <= '0';
WHEN "0011110111" =>
manhi <= conv_std_logic_vector(4576648,24);
manlo <= conv_std_logic_vector(34787059,28);
exponent <= '0';
WHEN "0011111000" =>
manhi <= conv_std_logic_vector(4597511,24);
manlo <= conv_std_logic_vector(187411489,28);
exponent <= '0';
WHEN "0011111001" =>
manhi <= conv_std_logic_vector(4618395,24);
manlo <= conv_std_logic_vector(174822068,28);
exponent <= '0';
WHEN "0011111010" =>
manhi <= conv_std_logic_vector(4639300,24);
manlo <= conv_std_logic_vector(2365090,28);
exponent <= '0';
WHEN "0011111011" =>
manhi <= conv_std_logic_vector(4660224,24);
manlo <= conv_std_logic_vector(212262982,28);
exponent <= '0';
WHEN "0011111100" =>
manhi <= conv_std_logic_vector(4681170,24);
manlo <= conv_std_logic_vector(4566120,28);
exponent <= '0';
WHEN "0011111101" =>
manhi <= conv_std_logic_vector(4702135,24);
manlo <= conv_std_logic_vector(189942850,28);
exponent <= '0';
WHEN "0011111110" =>
manhi <= conv_std_logic_vector(4723121,24);
manlo <= conv_std_logic_vector(236889480,28);
exponent <= '0';
WHEN "0011111111" =>
manhi <= conv_std_logic_vector(4744128,24);
manlo <= conv_std_logic_vector(150778468,28);
exponent <= '0';
WHEN "0100000000" =>
manhi <= conv_std_logic_vector(4765155,24);
manlo <= conv_std_logic_vector(205422982,28);
exponent <= '0';
WHEN "0100000001" =>
manhi <= conv_std_logic_vector(4786203,24);
manlo <= conv_std_logic_vector(137770531,28);
exponent <= '0';
WHEN "0100000010" =>
manhi <= conv_std_logic_vector(4807271,24);
manlo <= conv_std_logic_vector(221644793,28);
exponent <= '0';
WHEN "0100000011" =>
manhi <= conv_std_logic_vector(4828360,24);
manlo <= conv_std_logic_vector(194003802,28);
exponent <= '0';
WHEN "0100000100" =>
manhi <= conv_std_logic_vector(4849470,24);
manlo <= conv_std_logic_vector(60246316,28);
exponent <= '0';
WHEN "0100000101" =>
manhi <= conv_std_logic_vector(4870600,24);
manlo <= conv_std_logic_vector(94211823,28);
exponent <= '0';
WHEN "0100000110" =>
manhi <= conv_std_logic_vector(4891751,24);
manlo <= conv_std_logic_vector(32874180,28);
exponent <= '0';
WHEN "0100000111" =>
manhi <= conv_std_logic_vector(4912922,24);
manlo <= conv_std_logic_vector(150083442,28);
exponent <= '0';
WHEN "0100001000" =>
manhi <= conv_std_logic_vector(4934114,24);
manlo <= conv_std_logic_vector(182824039,28);
exponent <= '0';
WHEN "0100001001" =>
manhi <= conv_std_logic_vector(4955327,24);
manlo <= conv_std_logic_vector(136521157,28);
exponent <= '0';
WHEN "0100001010" =>
manhi <= conv_std_logic_vector(4976561,24);
manlo <= conv_std_logic_vector(16605280,28);
exponent <= '0';
WHEN "0100001011" =>
manhi <= conv_std_logic_vector(4997815,24);
manlo <= conv_std_logic_vector(96947652,28);
exponent <= '0';
WHEN "0100001100" =>
manhi <= conv_std_logic_vector(5019090,24);
manlo <= conv_std_logic_vector(114553920,28);
exponent <= '0';
WHEN "0100001101" =>
manhi <= conv_std_logic_vector(5040386,24);
manlo <= conv_std_logic_vector(74870501,28);
exponent <= '0';
WHEN "0100001110" =>
manhi <= conv_std_logic_vector(5061702,24);
manlo <= conv_std_logic_vector(251784590,28);
exponent <= '0';
WHEN "0100001111" =>
manhi <= conv_std_logic_vector(5083040,24);
manlo <= conv_std_logic_vector(113882338,28);
exponent <= '0';
WHEN "0100010000" =>
manhi <= conv_std_logic_vector(5104398,24);
manlo <= conv_std_logic_vector(203497056,28);
exponent <= '0';
WHEN "0100010001" =>
manhi <= conv_std_logic_vector(5125777,24);
manlo <= conv_std_logic_vector(257661021,28);
exponent <= '0';
WHEN "0100010010" =>
manhi <= conv_std_logic_vector(5147178,24);
manlo <= conv_std_logic_vector(13411854,28);
exponent <= '0';
WHEN "0100010011" =>
manhi <= conv_std_logic_vector(5168599,24);
manlo <= conv_std_logic_vector(13098889,28);
exponent <= '0';
WHEN "0100010100" =>
manhi <= conv_std_logic_vector(5190040,24);
manlo <= conv_std_logic_vector(262205904,28);
exponent <= '0';
WHEN "0100010101" =>
manhi <= conv_std_logic_vector(5211503,24);
manlo <= conv_std_logic_vector(229351119,28);
exponent <= '0';
WHEN "0100010110" =>
manhi <= conv_std_logic_vector(5232987,24);
manlo <= conv_std_logic_vector(188464488,28);
exponent <= '0';
WHEN "0100010111" =>
manhi <= conv_std_logic_vector(5254492,24);
manlo <= conv_std_logic_vector(145045878,28);
exponent <= '0';
WHEN "0100011000" =>
manhi <= conv_std_logic_vector(5276018,24);
manlo <= conv_std_logic_vector(104600525,28);
exponent <= '0';
WHEN "0100011001" =>
manhi <= conv_std_logic_vector(5297565,24);
manlo <= conv_std_logic_vector(72639049,28);
exponent <= '0';
WHEN "0100011010" =>
manhi <= conv_std_logic_vector(5319133,24);
manlo <= conv_std_logic_vector(54677451,28);
exponent <= '0';
WHEN "0100011011" =>
manhi <= conv_std_logic_vector(5340722,24);
manlo <= conv_std_logic_vector(56237123,28);
exponent <= '0';
WHEN "0100011100" =>
manhi <= conv_std_logic_vector(5362332,24);
manlo <= conv_std_logic_vector(82844851,28);
exponent <= '0';
WHEN "0100011101" =>
manhi <= conv_std_logic_vector(5383963,24);
manlo <= conv_std_logic_vector(140032820,28);
exponent <= '0';
WHEN "0100011110" =>
manhi <= conv_std_logic_vector(5405615,24);
manlo <= conv_std_logic_vector(233338622,28);
exponent <= '0';
WHEN "0100011111" =>
manhi <= conv_std_logic_vector(5427289,24);
manlo <= conv_std_logic_vector(99869801,28);
exponent <= '0';
WHEN "0100100000" =>
manhi <= conv_std_logic_vector(5448984,24);
manlo <= conv_std_logic_vector(13610232,28);
exponent <= '0';
WHEN "0100100001" =>
manhi <= conv_std_logic_vector(5470699,24);
manlo <= conv_std_logic_vector(248549207,28);
exponent <= '0';
WHEN "0100100010" =>
manhi <= conv_std_logic_vector(5492437,24);
manlo <= conv_std_logic_vector(4939624,28);
exponent <= '0';
WHEN "0100100011" =>
manhi <= conv_std_logic_vector(5514195,24);
manlo <= conv_std_logic_vector(93652547,28);
exponent <= '0';
WHEN "0100100100" =>
manhi <= conv_std_logic_vector(5535974,24);
manlo <= conv_std_logic_vector(251822653,28);
exponent <= '0';
WHEN "0100100101" =>
manhi <= conv_std_logic_vector(5557775,24);
manlo <= conv_std_logic_vector(216590061,28);
exponent <= '0';
WHEN "0100100110" =>
manhi <= conv_std_logic_vector(5579597,24);
manlo <= conv_std_logic_vector(261971250,28);
exponent <= '0';
WHEN "0100100111" =>
manhi <= conv_std_logic_vector(5601441,24);
manlo <= conv_std_logic_vector(125117240,28);
exponent <= '0';
WHEN "0100101000" =>
manhi <= conv_std_logic_vector(5623306,24);
manlo <= conv_std_logic_vector(80055420,28);
exponent <= '0';
WHEN "0100101001" =>
manhi <= conv_std_logic_vector(5645192,24);
manlo <= conv_std_logic_vector(132383188,28);
exponent <= '0';
WHEN "0100101010" =>
manhi <= conv_std_logic_vector(5667100,24);
manlo <= conv_std_logic_vector(19267955,28);
exponent <= '0';
WHEN "0100101011" =>
manhi <= conv_std_logic_vector(5689029,24);
manlo <= conv_std_logic_vector(14753516,28);
exponent <= '0';
WHEN "0100101100" =>
manhi <= conv_std_logic_vector(5710979,24);
manlo <= conv_std_logic_vector(124453694,28);
exponent <= '0';
WHEN "0100101101" =>
manhi <= conv_std_logic_vector(5732951,24);
manlo <= conv_std_logic_vector(85552334,28);
exponent <= '0';
WHEN "0100101110" =>
manhi <= conv_std_logic_vector(5754944,24);
manlo <= conv_std_logic_vector(172109691,28);
exponent <= '0';
WHEN "0100101111" =>
manhi <= conv_std_logic_vector(5776959,24);
manlo <= conv_std_logic_vector(121320598,28);
exponent <= '0';
WHEN "0100110000" =>
manhi <= conv_std_logic_vector(5798995,24);
manlo <= conv_std_logic_vector(207256304,28);
exponent <= '0';
WHEN "0100110001" =>
manhi <= conv_std_logic_vector(5821053,24);
manlo <= conv_std_logic_vector(167122651,28);
exponent <= '0';
WHEN "0100110010" =>
manhi <= conv_std_logic_vector(5843133,24);
manlo <= conv_std_logic_vector(6566449,28);
exponent <= '0';
WHEN "0100110011" =>
manhi <= conv_std_logic_vector(5865233,24);
manlo <= conv_std_logic_vector(268110937,28);
exponent <= '0';
WHEN "0100110100" =>
manhi <= conv_std_logic_vector(5887356,24);
manlo <= conv_std_logic_vector(152107598,28);
exponent <= '0';
WHEN "0100110101" =>
manhi <= conv_std_logic_vector(5909500,24);
manlo <= conv_std_logic_vector(201090721,28);
exponent <= '0';
WHEN "0100110110" =>
manhi <= conv_std_logic_vector(5931666,24);
manlo <= conv_std_logic_vector(152293761,28);
exponent <= '0';
WHEN "0100110111" =>
manhi <= conv_std_logic_vector(5953854,24);
manlo <= conv_std_logic_vector(11391168,28);
exponent <= '0';
WHEN "0100111000" =>
manhi <= conv_std_logic_vector(5976063,24);
manlo <= conv_std_logic_vector(52498394,28);
exponent <= '0';
WHEN "0100111001" =>
manhi <= conv_std_logic_vector(5998294,24);
manlo <= conv_std_logic_vector(12865523,28);
exponent <= '0';
WHEN "0100111010" =>
manhi <= conv_std_logic_vector(6020546,24);
manlo <= conv_std_logic_vector(166619112,28);
exponent <= '0';
WHEN "0100111011" =>
manhi <= conv_std_logic_vector(6042820,24);
manlo <= conv_std_logic_vector(251020365,28);
exponent <= '0';
WHEN "0100111100" =>
manhi <= conv_std_logic_vector(6065117,24);
manlo <= conv_std_logic_vector(3336048,28);
exponent <= '0';
WHEN "0100111101" =>
manhi <= conv_std_logic_vector(6087434,24);
manlo <= conv_std_logic_vector(234580328,28);
exponent <= '0';
WHEN "0100111110" =>
manhi <= conv_std_logic_vector(6109774,24);
manlo <= conv_std_logic_vector(145160209,28);
exponent <= '0';
WHEN "0100111111" =>
manhi <= conv_std_logic_vector(6132136,24);
manlo <= conv_std_logic_vector(9230102,28);
exponent <= '0';
WHEN "0101000000" =>
manhi <= conv_std_logic_vector(6154519,24);
manlo <= conv_std_logic_vector(100950005,28);
exponent <= '0';
WHEN "0101000001" =>
manhi <= conv_std_logic_vector(6176924,24);
manlo <= conv_std_logic_vector(157614600,28);
exponent <= '0';
WHEN "0101000010" =>
manhi <= conv_std_logic_vector(6199351,24);
manlo <= conv_std_logic_vector(184959620,28);
exponent <= '0';
WHEN "0101000011" =>
manhi <= conv_std_logic_vector(6221800,24);
manlo <= conv_std_logic_vector(188726403,28);
exponent <= '0';
WHEN "0101000100" =>
manhi <= conv_std_logic_vector(6244271,24);
manlo <= conv_std_logic_vector(174661898,28);
exponent <= '0';
WHEN "0101000101" =>
manhi <= conv_std_logic_vector(6266764,24);
manlo <= conv_std_logic_vector(148518669,28);
exponent <= '0';
WHEN "0101000110" =>
manhi <= conv_std_logic_vector(6289279,24);
manlo <= conv_std_logic_vector(116054898,28);
exponent <= '0';
WHEN "0101000111" =>
manhi <= conv_std_logic_vector(6311816,24);
manlo <= conv_std_logic_vector(83034395,28);
exponent <= '0';
WHEN "0101001000" =>
manhi <= conv_std_logic_vector(6334375,24);
manlo <= conv_std_logic_vector(55226600,28);
exponent <= '0';
WHEN "0101001001" =>
manhi <= conv_std_logic_vector(6356956,24);
manlo <= conv_std_logic_vector(38406593,28);
exponent <= '0';
WHEN "0101001010" =>
manhi <= conv_std_logic_vector(6379559,24);
manlo <= conv_std_logic_vector(38355093,28);
exponent <= '0';
WHEN "0101001011" =>
manhi <= conv_std_logic_vector(6402184,24);
manlo <= conv_std_logic_vector(60858469,28);
exponent <= '0';
WHEN "0101001100" =>
manhi <= conv_std_logic_vector(6424831,24);
manlo <= conv_std_logic_vector(111708742,28);
exponent <= '0';
WHEN "0101001101" =>
manhi <= conv_std_logic_vector(6447500,24);
manlo <= conv_std_logic_vector(196703594,28);
exponent <= '0';
WHEN "0101001110" =>
manhi <= conv_std_logic_vector(6470192,24);
manlo <= conv_std_logic_vector(53210914,28);
exponent <= '0';
WHEN "0101001111" =>
manhi <= conv_std_logic_vector(6492905,24);
manlo <= conv_std_logic_vector(223910630,28);
exponent <= '0';
WHEN "0101010000" =>
manhi <= conv_std_logic_vector(6515641,24);
manlo <= conv_std_logic_vector(177746520,28);
exponent <= '0';
WHEN "0101010001" =>
manhi <= conv_std_logic_vector(6538399,24);
manlo <= conv_std_logic_vector(188974414,28);
exponent <= '0';
WHEN "0101010010" =>
manhi <= conv_std_logic_vector(6561179,24);
manlo <= conv_std_logic_vector(263420371,28);
exponent <= '0';
WHEN "0101010011" =>
manhi <= conv_std_logic_vector(6583982,24);
manlo <= conv_std_logic_vector(138480686,28);
exponent <= '0';
WHEN "0101010100" =>
manhi <= conv_std_logic_vector(6606807,24);
manlo <= conv_std_logic_vector(88428264,28);
exponent <= '0';
WHEN "0101010101" =>
manhi <= conv_std_logic_vector(6629654,24);
manlo <= conv_std_logic_vector(119106258,28);
exponent <= '0';
WHEN "0101010110" =>
manhi <= conv_std_logic_vector(6652523,24);
manlo <= conv_std_logic_vector(236363530,28);
exponent <= '0';
WHEN "0101010111" =>
manhi <= conv_std_logic_vector(6675415,24);
manlo <= conv_std_logic_vector(177619200,28);
exponent <= '0';
WHEN "0101011000" =>
manhi <= conv_std_logic_vector(6698329,24);
manlo <= conv_std_logic_vector(217169020,28);
exponent <= '0';
WHEN "0101011001" =>
manhi <= conv_std_logic_vector(6721266,24);
manlo <= conv_std_logic_vector(92443558,28);
exponent <= '0';
WHEN "0101011010" =>
manhi <= conv_std_logic_vector(6744225,24);
manlo <= conv_std_logic_vector(77750021,28);
exponent <= '0';
WHEN "0101011011" =>
manhi <= conv_std_logic_vector(6767206,24);
manlo <= conv_std_logic_vector(178965902,28);
exponent <= '0';
WHEN "0101011100" =>
manhi <= conv_std_logic_vector(6790210,24);
manlo <= conv_std_logic_vector(133538975,28);
exponent <= '0';
WHEN "0101011101" =>
manhi <= conv_std_logic_vector(6813236,24);
manlo <= conv_std_logic_vector(215793680,28);
exponent <= '0';
WHEN "0101011110" =>
manhi <= conv_std_logic_vector(6836285,24);
manlo <= conv_std_logic_vector(163189294,28);
exponent <= '0';
WHEN "0101011111" =>
manhi <= conv_std_logic_vector(6859356,24);
manlo <= conv_std_logic_vector(250061769,28);
exponent <= '0';
WHEN "0101100000" =>
manhi <= conv_std_logic_vector(6882450,24);
manlo <= conv_std_logic_vector(213881907,28);
exponent <= '0';
WHEN "0101100001" =>
manhi <= conv_std_logic_vector(6905567,24);
manlo <= conv_std_logic_vector(60561738,28);
exponent <= '0';
WHEN "0101100010" =>
manhi <= conv_std_logic_vector(6928706,24);
manlo <= conv_std_logic_vector(64454525,28);
exponent <= '0';
WHEN "0101100011" =>
manhi <= conv_std_logic_vector(6951867,24);
manlo <= conv_std_logic_vector(231483856,28);
exponent <= '0';
WHEN "0101100100" =>
manhi <= conv_std_logic_vector(6975052,24);
manlo <= conv_std_logic_vector(30708194,28);
exponent <= '0';
WHEN "0101100101" =>
manhi <= conv_std_logic_vector(6998259,24);
manlo <= conv_std_logic_vector(4933620,28);
exponent <= '0';
WHEN "0101100110" =>
manhi <= conv_std_logic_vector(7021488,24);
manlo <= conv_std_logic_vector(160101103,28);
exponent <= '0';
WHEN "0101100111" =>
manhi <= conv_std_logic_vector(7044740,24);
manlo <= conv_std_logic_vector(233721959,28);
exponent <= '0';
WHEN "0101101000" =>
manhi <= conv_std_logic_vector(7068015,24);
manlo <= conv_std_logic_vector(231748770,28);
exponent <= '0';
WHEN "0101101001" =>
manhi <= conv_std_logic_vector(7091313,24);
manlo <= conv_std_logic_vector(160139936,28);
exponent <= '0';
WHEN "0101101010" =>
manhi <= conv_std_logic_vector(7114634,24);
manlo <= conv_std_logic_vector(24859676,28);
exponent <= '0';
WHEN "0101101011" =>
manhi <= conv_std_logic_vector(7137977,24);
manlo <= conv_std_logic_vector(100313494,28);
exponent <= '0';
WHEN "0101101100" =>
manhi <= conv_std_logic_vector(7161343,24);
manlo <= conv_std_logic_vector(124041814,28);
exponent <= '0';
WHEN "0101101101" =>
manhi <= conv_std_logic_vector(7184732,24);
manlo <= conv_std_logic_vector(102026355,28);
exponent <= '0';
WHEN "0101101110" =>
manhi <= conv_std_logic_vector(7208144,24);
manlo <= conv_std_logic_vector(40254681,28);
exponent <= '0';
WHEN "0101101111" =>
manhi <= conv_std_logic_vector(7231578,24);
manlo <= conv_std_logic_vector(213155662,28);
exponent <= '0';
WHEN "0101110000" =>
manhi <= conv_std_logic_vector(7255036,24);
manlo <= conv_std_logic_vector(89857654,28);
exponent <= '0';
WHEN "0101110001" =>
manhi <= conv_std_logic_vector(7278516,24);
manlo <= conv_std_logic_vector(213236700,28);
exponent <= '0';
WHEN "0101110010" =>
manhi <= conv_std_logic_vector(7302020,24);
manlo <= conv_std_logic_vector(52432888,28);
exponent <= '0';
WHEN "0101110011" =>
manhi <= conv_std_logic_vector(7325546,24);
manlo <= conv_std_logic_vector(150334000,28);
exponent <= '0';
WHEN "0101110100" =>
manhi <= conv_std_logic_vector(7349095,24);
manlo <= conv_std_logic_vector(244527329,28);
exponent <= '0';
WHEN "0101110101" =>
manhi <= conv_std_logic_vector(7372668,24);
manlo <= conv_std_logic_vector(72606054,28);
exponent <= '0';
WHEN "0101110110" =>
manhi <= conv_std_logic_vector(7396263,24);
manlo <= conv_std_logic_vector(177475612,28);
exponent <= '0';
WHEN "0101110111" =>
manhi <= conv_std_logic_vector(7419882,24);
manlo <= conv_std_logic_vector(28305511,28);
exponent <= '0';
WHEN "0101111000" =>
manhi <= conv_std_logic_vector(7443523,24);
manlo <= conv_std_logic_vector(168012985,28);
exponent <= '0';
WHEN "0101111001" =>
manhi <= conv_std_logic_vector(7467188,24);
manlo <= conv_std_logic_vector(65779352,28);
exponent <= '0';
WHEN "0101111010" =>
manhi <= conv_std_logic_vector(7490875,24);
manlo <= conv_std_logic_vector(264533668,28);
exponent <= '0';
WHEN "0101111011" =>
manhi <= conv_std_logic_vector(7514586,24);
manlo <= conv_std_logic_vector(233469080,28);
exponent <= '0';
WHEN "0101111100" =>
manhi <= conv_std_logic_vector(7538320,24);
manlo <= conv_std_logic_vector(247091035,28);
exponent <= '0';
WHEN "0101111101" =>
manhi <= conv_std_logic_vector(7562078,24);
manlo <= conv_std_logic_vector(43039991,28);
exponent <= '0';
WHEN "0101111110" =>
manhi <= conv_std_logic_vector(7585858,24);
manlo <= conv_std_logic_vector(164268716,28);
exponent <= '0';
WHEN "0101111111" =>
manhi <= conv_std_logic_vector(7609662,24);
manlo <= conv_std_logic_vector(79994093,28);
exponent <= '0';
WHEN "0110000000" =>
manhi <= conv_std_logic_vector(7633489,24);
manlo <= conv_std_logic_vector(64745322,28);
exponent <= '0';
WHEN "0110000001" =>
manhi <= conv_std_logic_vector(7657339,24);
manlo <= conv_std_logic_vector(124622102,28);
exponent <= '0';
WHEN "0110000010" =>
manhi <= conv_std_logic_vector(7681212,24);
manlo <= conv_std_logic_vector(265730090,28);
exponent <= '0';
WHEN "0110000011" =>
manhi <= conv_std_logic_vector(7705109,24);
manlo <= conv_std_logic_vector(225745453,28);
exponent <= '0';
WHEN "0110000100" =>
manhi <= conv_std_logic_vector(7729030,24);
manlo <= conv_std_logic_vector(10785785,28);
exponent <= '0';
WHEN "0110000101" =>
manhi <= conv_std_logic_vector(7752973,24);
manlo <= conv_std_logic_vector(163845570,28);
exponent <= '0';
WHEN "0110000110" =>
manhi <= conv_std_logic_vector(7776940,24);
manlo <= conv_std_logic_vector(154183450,28);
exponent <= '0';
WHEN "0110000111" =>
manhi <= conv_std_logic_vector(7800930,24);
manlo <= conv_std_logic_vector(256370426,28);
exponent <= '0';
WHEN "0110001000" =>
manhi <= conv_std_logic_vector(7824944,24);
manlo <= conv_std_logic_vector(208112577,28);
exponent <= '0';
WHEN "0110001001" =>
manhi <= conv_std_logic_vector(7848982,24);
manlo <= conv_std_logic_vector(15557444,28);
exponent <= '0';
WHEN "0110001010" =>
manhi <= conv_std_logic_vector(7873042,24);
manlo <= conv_std_logic_vector(221729482,28);
exponent <= '0';
WHEN "0110001011" =>
manhi <= conv_std_logic_vector(7897127,24);
manlo <= conv_std_logic_vector(27481881,28);
exponent <= '0';
WHEN "0110001100" =>
manhi <= conv_std_logic_vector(7921234,24);
manlo <= conv_std_logic_vector(244286584,28);
exponent <= '0';
WHEN "0110001101" =>
manhi <= conv_std_logic_vector(7945366,24);
manlo <= conv_std_logic_vector(73008824,28);
exponent <= '0';
WHEN "0110001110" =>
manhi <= conv_std_logic_vector(7969521,24);
manlo <= conv_std_logic_vector(56697140,28);
exponent <= '0';
WHEN "0110001111" =>
manhi <= conv_std_logic_vector(7993699,24);
manlo <= conv_std_logic_vector(201535196,28);
exponent <= '0';
WHEN "0110010000" =>
manhi <= conv_std_logic_vector(8017901,24);
manlo <= conv_std_logic_vector(245277246,28);
exponent <= '0';
WHEN "0110010001" =>
manhi <= conv_std_logic_vector(8042127,24);
manlo <= conv_std_logic_vector(194119042,28);
exponent <= '0';
WHEN "0110010010" =>
manhi <= conv_std_logic_vector(8066377,24);
manlo <= conv_std_logic_vector(54262392,28);
exponent <= '0';
WHEN "0110010011" =>
manhi <= conv_std_logic_vector(8090650,24);
manlo <= conv_std_logic_vector(100350618,28);
exponent <= '0';
WHEN "0110010100" =>
manhi <= conv_std_logic_vector(8114947,24);
manlo <= conv_std_logic_vector(70162199,28);
exponent <= '0';
WHEN "0110010101" =>
manhi <= conv_std_logic_vector(8139267,24);
manlo <= conv_std_logic_vector(238352593,28);
exponent <= '0';
WHEN "0110010110" =>
manhi <= conv_std_logic_vector(8163612,24);
manlo <= conv_std_logic_vector(74276969,28);
exponent <= '0';
WHEN "0110010111" =>
manhi <= conv_std_logic_vector(8187980,24);
manlo <= conv_std_logic_vector(121038404,28);
exponent <= '0';
WHEN "0110011000" =>
manhi <= conv_std_logic_vector(8212372,24);
manlo <= conv_std_logic_vector(116439694,28);
exponent <= '0';
WHEN "0110011001" =>
manhi <= conv_std_logic_vector(8236788,24);
manlo <= conv_std_logic_vector(66725186,28);
exponent <= '0';
WHEN "0110011010" =>
manhi <= conv_std_logic_vector(8261227,24);
manlo <= conv_std_logic_vector(246580788,28);
exponent <= '0';
WHEN "0110011011" =>
manhi <= conv_std_logic_vector(8285691,24);
manlo <= conv_std_logic_vector(125392143,28);
exponent <= '0';
WHEN "0110011100" =>
manhi <= conv_std_logic_vector(8310178,24);
manlo <= conv_std_logic_vector(246292830,28);
exponent <= '0';
WHEN "0110011101" =>
manhi <= conv_std_logic_vector(8334690,24);
manlo <= conv_std_logic_vector(78680728,28);
exponent <= '0';
WHEN "0110011110" =>
manhi <= conv_std_logic_vector(8359225,24);
manlo <= conv_std_logic_vector(165701659,28);
exponent <= '0';
WHEN "0110011111" =>
manhi <= conv_std_logic_vector(8383784,24);
manlo <= conv_std_logic_vector(245201212,28);
exponent <= '0';
WHEN "0110100000" =>
manhi <= conv_std_logic_vector(8408368,24);
manlo <= conv_std_logic_vector(55031110,28);
exponent <= '0';
WHEN "0110100001" =>
manhi <= conv_std_logic_vector(8432975,24);
manlo <= conv_std_logic_vector(138355589,28);
exponent <= '0';
WHEN "0110100010" =>
manhi <= conv_std_logic_vector(8457606,24);
manlo <= conv_std_logic_vector(233038665,28);
exponent <= '0';
WHEN "0110100011" =>
manhi <= conv_std_logic_vector(8482262,24);
manlo <= conv_std_logic_vector(76950508,28);
exponent <= '0';
WHEN "0110100100" =>
manhi <= conv_std_logic_vector(8506941,24);
manlo <= conv_std_logic_vector(213273820,28);
exponent <= '0';
WHEN "0110100101" =>
manhi <= conv_std_logic_vector(8531645,24);
manlo <= conv_std_logic_vector(111455640,28);
exponent <= '0';
WHEN "0110100110" =>
manhi <= conv_std_logic_vector(8556373,24);
manlo <= conv_std_logic_vector(46255554,28);
exponent <= '0';
WHEN "0110100111" =>
manhi <= conv_std_logic_vector(8581125,24);
manlo <= conv_std_logic_vector(24003868,28);
exponent <= '0';
WHEN "0110101000" =>
manhi <= conv_std_logic_vector(8605901,24);
manlo <= conv_std_logic_vector(51037072,28);
exponent <= '0';
WHEN "0110101001" =>
manhi <= conv_std_logic_vector(8630701,24);
manlo <= conv_std_logic_vector(133697849,28);
exponent <= '0';
WHEN "0110101010" =>
manhi <= conv_std_logic_vector(8655526,24);
manlo <= conv_std_logic_vector(9899623,28);
exponent <= '0';
WHEN "0110101011" =>
manhi <= conv_std_logic_vector(8680374,24);
manlo <= conv_std_logic_vector(222868388,28);
exponent <= '0';
WHEN "0110101100" =>
manhi <= conv_std_logic_vector(8705247,24);
manlo <= conv_std_logic_vector(242094523,28);
exponent <= '0';
WHEN "0110101101" =>
manhi <= conv_std_logic_vector(8730145,24);
manlo <= conv_std_logic_vector(73945536,28);
exponent <= '0';
WHEN "0110101110" =>
manhi <= conv_std_logic_vector(8755066,24);
manlo <= conv_std_logic_vector(261666066,28);
exponent <= '0';
WHEN "0110101111" =>
manhi <= conv_std_logic_vector(8780013,24);
manlo <= conv_std_logic_vector(6329700,28);
exponent <= '0';
WHEN "0110110000" =>
manhi <= conv_std_logic_vector(8804983,24);
manlo <= conv_std_logic_vector(119628997,28);
exponent <= '0';
WHEN "0110110001" =>
manhi <= conv_std_logic_vector(8829978,24);
manlo <= conv_std_logic_vector(71085473,28);
exponent <= '0';
WHEN "0110110010" =>
manhi <= conv_std_logic_vector(8854997,24);
manlo <= conv_std_logic_vector(135533257,28);
exponent <= '0';
WHEN "0110110011" =>
manhi <= conv_std_logic_vector(8880041,24);
manlo <= conv_std_logic_vector(50941820,28);
exponent <= '0';
WHEN "0110110100" =>
manhi <= conv_std_logic_vector(8905109,24);
manlo <= conv_std_logic_vector(92157802,28);
exponent <= '0';
WHEN "0110110101" =>
manhi <= conv_std_logic_vector(8930201,24);
manlo <= conv_std_logic_vector(265598650,28);
exponent <= '0';
WHEN "0110110110" =>
manhi <= conv_std_logic_vector(8955319,24);
manlo <= conv_std_logic_vector(40817170,28);
exponent <= '0';
WHEN "0110110111" =>
manhi <= conv_std_logic_vector(8980460,24);
manlo <= conv_std_logic_vector(229549724,28);
exponent <= '0';
WHEN "0110111000" =>
manhi <= conv_std_logic_vector(9005627,24);
manlo <= conv_std_logic_vector(32926222,28);
exponent <= '0';
WHEN "0110111001" =>
manhi <= conv_std_logic_vector(9030817,24);
manlo <= conv_std_logic_vector(262695596,28);
exponent <= '0';
WHEN "0110111010" =>
manhi <= conv_std_logic_vector(9056033,24);
manlo <= conv_std_logic_vector(120000337,28);
exponent <= '0';
WHEN "0110111011" =>
manhi <= conv_std_logic_vector(9081273,24);
manlo <= conv_std_logic_vector(148166518,28);
exponent <= '0';
WHEN "0110111100" =>
manhi <= conv_std_logic_vector(9106538,24);
manlo <= conv_std_logic_vector(85220151,28);
exponent <= '0';
WHEN "0110111101" =>
manhi <= conv_std_logic_vector(9131827,24);
manlo <= conv_std_logic_vector(206064472,28);
exponent <= '0';
WHEN "0110111110" =>
manhi <= conv_std_logic_vector(9157141,24);
manlo <= conv_std_logic_vector(248738124,28);
exponent <= '0';
WHEN "0110111111" =>
manhi <= conv_std_logic_vector(9182480,24);
manlo <= conv_std_logic_vector(219721533,28);
exponent <= '0';
WHEN "0111000000" =>
manhi <= conv_std_logic_vector(9207844,24);
manlo <= conv_std_logic_vector(125501456,28);
exponent <= '0';
WHEN "0111000001" =>
manhi <= conv_std_logic_vector(9233232,24);
manlo <= conv_std_logic_vector(241006443,28);
exponent <= '0';
WHEN "0111000010" =>
manhi <= conv_std_logic_vector(9258646,24);
manlo <= conv_std_logic_vector(35865021,28);
exponent <= '0';
WHEN "0111000011" =>
manhi <= conv_std_logic_vector(9284084,24);
manlo <= conv_std_logic_vector(53453891,28);
exponent <= '0';
WHEN "0111000100" =>
manhi <= conv_std_logic_vector(9309547,24);
manlo <= conv_std_logic_vector(31849742,28);
exponent <= '0';
WHEN "0111000101" =>
manhi <= conv_std_logic_vector(9335034,24);
manlo <= conv_std_logic_vector(246006538,28);
exponent <= '0';
WHEN "0111000110" =>
manhi <= conv_std_logic_vector(9360547,24);
manlo <= conv_std_logic_vector(165578245,28);
exponent <= '0';
WHEN "0111000111" =>
manhi <= conv_std_logic_vector(9386085,24);
manlo <= conv_std_logic_vector(65531569,28);
exponent <= '0';
WHEN "0111001000" =>
manhi <= conv_std_logic_vector(9411647,24);
manlo <= conv_std_logic_vector(220839600,28);
exponent <= '0';
WHEN "0111001001" =>
manhi <= conv_std_logic_vector(9437235,24);
manlo <= conv_std_logic_vector(101175446,28);
exponent <= '0';
WHEN "0111001010" =>
manhi <= conv_std_logic_vector(9462847,24);
manlo <= conv_std_logic_vector(249960434,28);
exponent <= '0';
WHEN "0111001011" =>
manhi <= conv_std_logic_vector(9488485,24);
manlo <= conv_std_logic_vector(136880466,28);
exponent <= '0';
WHEN "0111001100" =>
manhi <= conv_std_logic_vector(9514148,24);
manlo <= conv_std_logic_vector(36934219,28);
exponent <= '0';
WHEN "0111001101" =>
manhi <= conv_std_logic_vector(9539835,24);
manlo <= conv_std_logic_vector(225126782,28);
exponent <= '0';
WHEN "0111001110" =>
manhi <= conv_std_logic_vector(9565548,24);
manlo <= conv_std_logic_vector(171163295,28);
exponent <= '0';
WHEN "0111001111" =>
manhi <= conv_std_logic_vector(9591286,24);
manlo <= conv_std_logic_vector(150061692,28);
exponent <= '0';
WHEN "0111010000" =>
manhi <= conv_std_logic_vector(9617049,24);
manlo <= conv_std_logic_vector(168410880,28);
exponent <= '0';
WHEN "0111010001" =>
manhi <= conv_std_logic_vector(9642837,24);
manlo <= conv_std_logic_vector(232806206,28);
exponent <= '0';
WHEN "0111010010" =>
manhi <= conv_std_logic_vector(9668651,24);
manlo <= conv_std_logic_vector(81414002,28);
exponent <= '0';
WHEN "0111010011" =>
manhi <= conv_std_logic_vector(9694489,24);
manlo <= conv_std_logic_vector(257713424,28);
exponent <= '0';
WHEN "0111010100" =>
manhi <= conv_std_logic_vector(9720353,24);
manlo <= conv_std_logic_vector(231448253,28);
exponent <= '0';
WHEN "0111010101" =>
manhi <= conv_std_logic_vector(9746243,24);
manlo <= conv_std_logic_vector(9239650,28);
exponent <= '0';
WHEN "0111010110" =>
manhi <= conv_std_logic_vector(9772157,24);
manlo <= conv_std_logic_vector(134586155,28);
exponent <= '0';
WHEN "0111010111" =>
manhi <= conv_std_logic_vector(9798097,24);
manlo <= conv_std_logic_vector(77250961,28);
exponent <= '0';
WHEN "0111011000" =>
manhi <= conv_std_logic_vector(9824062,24);
manlo <= conv_std_logic_vector(112310110,28);
exponent <= '0';
WHEN "0111011001" =>
manhi <= conv_std_logic_vector(9850052,24);
manlo <= conv_std_logic_vector(246410674,28);
exponent <= '0';
WHEN "0111011010" =>
manhi <= conv_std_logic_vector(9876068,24);
manlo <= conv_std_logic_vector(217770768,28);
exponent <= '0';
WHEN "0111011011" =>
manhi <= conv_std_logic_vector(9902110,24);
manlo <= conv_std_logic_vector(33050459,28);
exponent <= '0';
WHEN "0111011100" =>
manhi <= conv_std_logic_vector(9928176,24);
manlo <= conv_std_logic_vector(235787236,28);
exponent <= '0';
WHEN "0111011101" =>
manhi <= conv_std_logic_vector(9954269,24);
manlo <= conv_std_logic_vector(27347822,28);
exponent <= '0';
WHEN "0111011110" =>
manhi <= conv_std_logic_vector(9980386,24);
manlo <= conv_std_logic_vector(219718194,28);
exponent <= '0';
WHEN "0111011111" =>
manhi <= conv_std_logic_vector(10006530,24);
manlo <= conv_std_logic_vector(14278120,28);
exponent <= '0';
WHEN "0111100000" =>
manhi <= conv_std_logic_vector(10032698,24);
manlo <= conv_std_logic_vector(223026636,28);
exponent <= '0';
WHEN "0111100001" =>
manhi <= conv_std_logic_vector(10058893,24);
manlo <= conv_std_logic_vector(47356582,28);
exponent <= '0';
WHEN "0111100010" =>
manhi <= conv_std_logic_vector(10085113,24);
manlo <= conv_std_logic_vector(30844624,28);
exponent <= '0';
WHEN "0111100011" =>
manhi <= conv_std_logic_vector(10111358,24);
manlo <= conv_std_logic_vector(180203065,28);
exponent <= '0';
WHEN "0111100100" =>
manhi <= conv_std_logic_vector(10137629,24);
manlo <= conv_std_logic_vector(233715314,28);
exponent <= '0';
WHEN "0111100101" =>
manhi <= conv_std_logic_vector(10163926,24);
manlo <= conv_std_logic_vector(198106796,28);
exponent <= '0';
WHEN "0111100110" =>
manhi <= conv_std_logic_vector(10190249,24);
manlo <= conv_std_logic_vector(80109512,28);
exponent <= '0';
WHEN "0111100111" =>
manhi <= conv_std_logic_vector(10216597,24);
manlo <= conv_std_logic_vector(154897493,28);
exponent <= '0';
WHEN "0111101000" =>
manhi <= conv_std_logic_vector(10242971,24);
manlo <= conv_std_logic_vector(160780443,28);
exponent <= '0';
WHEN "0111101001" =>
manhi <= conv_std_logic_vector(10269371,24);
manlo <= conv_std_logic_vector(104510112,28);
exponent <= '0';
WHEN "0111101010" =>
manhi <= conv_std_logic_vector(10295796,24);
manlo <= conv_std_logic_vector(261280303,28);
exponent <= '0';
WHEN "0111101011" =>
manhi <= conv_std_logic_vector(10322248,24);
manlo <= conv_std_logic_vector(100985054,28);
exponent <= '0';
WHEN "0111101100" =>
manhi <= conv_std_logic_vector(10348725,24);
manlo <= conv_std_logic_vector(167266836,28);
exponent <= '0';
WHEN "0111101101" =>
manhi <= conv_std_logic_vector(10375228,24);
manlo <= conv_std_logic_vector(198468370,28);
exponent <= '0';
WHEN "0111101110" =>
manhi <= conv_std_logic_vector(10401757,24);
manlo <= conv_std_logic_vector(201374454,28);
exponent <= '0';
WHEN "0111101111" =>
manhi <= conv_std_logic_vector(10428312,24);
manlo <= conv_std_logic_vector(182776514,28);
exponent <= '0';
WHEN "0111110000" =>
manhi <= conv_std_logic_vector(10454893,24);
manlo <= conv_std_logic_vector(149472614,28);
exponent <= '0';
WHEN "0111110001" =>
manhi <= conv_std_logic_vector(10481500,24);
manlo <= conv_std_logic_vector(108267459,28);
exponent <= '0';
WHEN "0111110010" =>
manhi <= conv_std_logic_vector(10508133,24);
manlo <= conv_std_logic_vector(65972402,28);
exponent <= '0';
WHEN "0111110011" =>
manhi <= conv_std_logic_vector(10534792,24);
manlo <= conv_std_logic_vector(29405451,28);
exponent <= '0';
WHEN "0111110100" =>
manhi <= conv_std_logic_vector(10561477,24);
manlo <= conv_std_logic_vector(5391275,28);
exponent <= '0';
WHEN "0111110101" =>
manhi <= conv_std_logic_vector(10588188,24);
manlo <= conv_std_logic_vector(761213,28);
exponent <= '0';
WHEN "0111110110" =>
manhi <= conv_std_logic_vector(10614925,24);
manlo <= conv_std_logic_vector(22353276,28);
exponent <= '0';
WHEN "0111110111" =>
manhi <= conv_std_logic_vector(10641688,24);
manlo <= conv_std_logic_vector(77012158,28);
exponent <= '0';
WHEN "0111111000" =>
manhi <= conv_std_logic_vector(10668477,24);
manlo <= conv_std_logic_vector(171589240,28);
exponent <= '0';
WHEN "0111111001" =>
manhi <= conv_std_logic_vector(10695293,24);
manlo <= conv_std_logic_vector(44507139,28);
exponent <= '0';
WHEN "0111111010" =>
manhi <= conv_std_logic_vector(10722134,24);
manlo <= conv_std_logic_vector(239501544,28);
exponent <= '0';
WHEN "0111111011" =>
manhi <= conv_std_logic_vector(10749002,24);
manlo <= conv_std_logic_vector(226573024,28);
exponent <= '0';
WHEN "0111111100" =>
manhi <= conv_std_logic_vector(10775897,24);
manlo <= conv_std_logic_vector(12599777,28);
exponent <= '0';
WHEN "0111111101" =>
manhi <= conv_std_logic_vector(10802817,24);
manlo <= conv_std_logic_vector(141337630,28);
exponent <= '0';
WHEN "0111111110" =>
manhi <= conv_std_logic_vector(10829764,24);
manlo <= conv_std_logic_vector(82807315,28);
exponent <= '0';
WHEN "0111111111" =>
manhi <= conv_std_logic_vector(10856737,24);
manlo <= conv_std_logic_vector(112342665,28);
exponent <= '0';
WHEN "1000000000" =>
manhi <= conv_std_logic_vector(10883736,24);
manlo <= conv_std_logic_vector(236848796,28);
exponent <= '0';
WHEN "1000000001" =>
manhi <= conv_std_logic_vector(10910762,24);
manlo <= conv_std_logic_vector(194802116,28);
exponent <= '0';
WHEN "1000000010" =>
manhi <= conv_std_logic_vector(10937814,24);
manlo <= conv_std_logic_vector(261556696,28);
exponent <= '0';
WHEN "1000000011" =>
manhi <= conv_std_logic_vector(10964893,24);
manlo <= conv_std_logic_vector(175602458,28);
exponent <= '0';
WHEN "1000000100" =>
manhi <= conv_std_logic_vector(10991998,24);
manlo <= conv_std_logic_vector(212307000,28);
exponent <= '0';
WHEN "1000000101" =>
manhi <= conv_std_logic_vector(11019130,24);
manlo <= conv_std_logic_vector(110173782,28);
exponent <= '0';
WHEN "1000000110" =>
manhi <= conv_std_logic_vector(11046288,24);
manlo <= conv_std_logic_vector(144583954,28);
exponent <= '0';
WHEN "1000000111" =>
manhi <= conv_std_logic_vector(11073473,24);
manlo <= conv_std_logic_vector(54054542,28);
exponent <= '0';
WHEN "1000001000" =>
manhi <= conv_std_logic_vector(11100684,24);
manlo <= conv_std_logic_vector(113980276,28);
exponent <= '0';
WHEN "1000001001" =>
manhi <= conv_std_logic_vector(11127922,24);
manlo <= conv_std_logic_vector(62891774,28);
exponent <= '0';
WHEN "1000001010" =>
manhi <= conv_std_logic_vector(11155186,24);
manlo <= conv_std_logic_vector(176197372,28);
exponent <= '0';
WHEN "1000001011" =>
manhi <= conv_std_logic_vector(11182477,24);
manlo <= conv_std_logic_vector(192441306,28);
exponent <= '0';
WHEN "1000001100" =>
manhi <= conv_std_logic_vector(11209795,24);
manlo <= conv_std_logic_vector(118610088,28);
exponent <= '0';
WHEN "1000001101" =>
manhi <= conv_std_logic_vector(11237139,24);
manlo <= conv_std_logic_vector(230132514,28);
exponent <= '0';
WHEN "1000001110" =>
manhi <= conv_std_logic_vector(11264510,24);
manlo <= conv_std_logic_vector(265573296,28);
exponent <= '0';
WHEN "1000001111" =>
manhi <= conv_std_logic_vector(11291908,24);
manlo <= conv_std_logic_vector(231939446,28);
exponent <= '0';
WHEN "1000010000" =>
manhi <= conv_std_logic_vector(11319333,24);
manlo <= conv_std_logic_vector(136244820,28);
exponent <= '0';
WHEN "1000010001" =>
manhi <= conv_std_logic_vector(11346784,24);
manlo <= conv_std_logic_vector(253945584,28);
exponent <= '0';
WHEN "1000010010" =>
manhi <= conv_std_logic_vector(11374263,24);
manlo <= conv_std_logic_vector(55198395,28);
exponent <= '0';
WHEN "1000010011" =>
manhi <= conv_std_logic_vector(11401768,24);
manlo <= conv_std_logic_vector(83908598,28);
exponent <= '0';
WHEN "1000010100" =>
manhi <= conv_std_logic_vector(11429300,24);
manlo <= conv_std_logic_vector(78682048,28);
exponent <= '0';
WHEN "1000010101" =>
manhi <= conv_std_logic_vector(11456859,24);
manlo <= conv_std_logic_vector(46566930,28);
exponent <= '0';
WHEN "1000010110" =>
manhi <= conv_std_logic_vector(11484444,24);
manlo <= conv_std_logic_vector(263053774,28);
exponent <= '0';
WHEN "1000010111" =>
manhi <= conv_std_logic_vector(11512057,24);
manlo <= conv_std_logic_vector(198333637,28);
exponent <= '0';
WHEN "1000011000" =>
manhi <= conv_std_logic_vector(11539697,24);
manlo <= conv_std_logic_vector(127910840,28);
exponent <= '0';
WHEN "1000011001" =>
manhi <= conv_std_logic_vector(11567364,24);
manlo <= conv_std_logic_vector(58861158,28);
exponent <= '0';
WHEN "1000011010" =>
manhi <= conv_std_logic_vector(11595057,24);
manlo <= conv_std_logic_vector(266702732,28);
exponent <= '0';
WHEN "1000011011" =>
manhi <= conv_std_logic_vector(11622778,24);
manlo <= conv_std_logic_vector(221654258,28);
exponent <= '0';
WHEN "1000011100" =>
manhi <= conv_std_logic_vector(11650526,24);
manlo <= conv_std_logic_vector(199247725,28);
exponent <= '0';
WHEN "1000011101" =>
manhi <= conv_std_logic_vector(11678301,24);
manlo <= conv_std_logic_vector(206586600,28);
exponent <= '0';
WHEN "1000011110" =>
manhi <= conv_std_logic_vector(11706103,24);
manlo <= conv_std_logic_vector(250781292,28);
exponent <= '0';
WHEN "1000011111" =>
manhi <= conv_std_logic_vector(11733933,24);
manlo <= conv_std_logic_vector(70513697,28);
exponent <= '0';
WHEN "1000100000" =>
manhi <= conv_std_logic_vector(11761789,24);
manlo <= conv_std_logic_vector(209779039,28);
exponent <= '0';
WHEN "1000100001" =>
manhi <= conv_std_logic_vector(11789673,24);
manlo <= conv_std_logic_vector(138837672,28);
exponent <= '0';
WHEN "1000100010" =>
manhi <= conv_std_logic_vector(11817584,24);
manlo <= conv_std_logic_vector(133263292,28);
exponent <= '0';
WHEN "1000100011" =>
manhi <= conv_std_logic_vector(11845522,24);
manlo <= conv_std_logic_vector(200201109,28);
exponent <= '0';
WHEN "1000100100" =>
manhi <= conv_std_logic_vector(11873488,24);
manlo <= conv_std_logic_vector(78367858,28);
exponent <= '0';
WHEN "1000100101" =>
manhi <= conv_std_logic_vector(11901481,24);
manlo <= conv_std_logic_vector(43358178,28);
exponent <= '0';
WHEN "1000100110" =>
manhi <= conv_std_logic_vector(11929501,24);
manlo <= conv_std_logic_vector(102338242,28);
exponent <= '0';
WHEN "1000100111" =>
manhi <= conv_std_logic_vector(11957548,24);
manlo <= conv_std_logic_vector(262481228,28);
exponent <= '0';
WHEN "1000101000" =>
manhi <= conv_std_logic_vector(11985623,24);
manlo <= conv_std_logic_vector(262531864,28);
exponent <= '0';
WHEN "1000101001" =>
manhi <= conv_std_logic_vector(12013726,24);
manlo <= conv_std_logic_vector(109677352,28);
exponent <= '0';
WHEN "1000101010" =>
manhi <= conv_std_logic_vector(12041856,24);
manlo <= conv_std_logic_vector(79547371,28);
exponent <= '0';
WHEN "1000101011" =>
manhi <= conv_std_logic_vector(12070013,24);
manlo <= conv_std_logic_vector(179343172,28);
exponent <= '0';
WHEN "1000101100" =>
manhi <= conv_std_logic_vector(12098198,24);
manlo <= conv_std_logic_vector(147837587,28);
exponent <= '0';
WHEN "1000101101" =>
manhi <= conv_std_logic_vector(12126410,24);
manlo <= conv_std_logic_vector(260681402,28);
exponent <= '0';
WHEN "1000101110" =>
manhi <= conv_std_logic_vector(12154650,24);
manlo <= conv_std_logic_vector(256661542,28);
exponent <= '0';
WHEN "1000101111" =>
manhi <= conv_std_logic_vector(12182918,24);
manlo <= conv_std_logic_vector(143007443,28);
exponent <= '0';
WHEN "1000110000" =>
manhi <= conv_std_logic_vector(12211213,24);
manlo <= conv_std_logic_vector(195391062,28);
exponent <= '0';
WHEN "1000110001" =>
manhi <= conv_std_logic_vector(12239536,24);
manlo <= conv_std_logic_vector(152620513,28);
exponent <= '0';
WHEN "1000110010" =>
manhi <= conv_std_logic_vector(12267887,24);
manlo <= conv_std_logic_vector(21946444,28);
exponent <= '0';
WHEN "1000110011" =>
manhi <= conv_std_logic_vector(12296265,24);
manlo <= conv_std_logic_vector(79062042,28);
exponent <= '0';
WHEN "1000110100" =>
manhi <= conv_std_logic_vector(12324671,24);
manlo <= conv_std_logic_vector(62796676,28);
exponent <= '0';
WHEN "1000110101" =>
manhi <= conv_std_logic_vector(12353104,24);
manlo <= conv_std_logic_vector(248857722,28);
exponent <= '0';
WHEN "1000110110" =>
manhi <= conv_std_logic_vector(12381566,24);
manlo <= conv_std_logic_vector(107653293,28);
exponent <= '0';
WHEN "1000110111" =>
manhi <= conv_std_logic_vector(12410055,24);
manlo <= conv_std_logic_vector(183340440,28);
exponent <= '0';
WHEN "1000111000" =>
manhi <= conv_std_logic_vector(12438572,24);
manlo <= conv_std_logic_vector(214776964,28);
exponent <= '0';
WHEN "1000111001" =>
manhi <= conv_std_logic_vector(12467117,24);
manlo <= conv_std_logic_vector(209263248,28);
exponent <= '0';
WHEN "1000111010" =>
manhi <= conv_std_logic_vector(12495690,24);
manlo <= conv_std_logic_vector(174106806,28);
exponent <= '0';
WHEN "1000111011" =>
manhi <= conv_std_logic_vector(12524291,24);
manlo <= conv_std_logic_vector(116622293,28);
exponent <= '0';
WHEN "1000111100" =>
manhi <= conv_std_logic_vector(12552920,24);
manlo <= conv_std_logic_vector(44131512,28);
exponent <= '0';
WHEN "1000111101" =>
manhi <= conv_std_logic_vector(12581576,24);
manlo <= conv_std_logic_vector(232398874,28);
exponent <= '0';
WHEN "1000111110" =>
manhi <= conv_std_logic_vector(12610261,24);
manlo <= conv_std_logic_vector(151889582,28);
exponent <= '0';
WHEN "1000111111" =>
manhi <= conv_std_logic_vector(12638974,24);
manlo <= conv_std_logic_vector(78382378,28);
exponent <= '0';
WHEN "1001000000" =>
manhi <= conv_std_logic_vector(12667715,24);
manlo <= conv_std_logic_vector(19227718,28);
exponent <= '0';
WHEN "1001000001" =>
manhi <= conv_std_logic_vector(12696483,24);
manlo <= conv_std_logic_vector(250218700,28);
exponent <= '0';
WHEN "1001000010" =>
manhi <= conv_std_logic_vector(12725280,24);
manlo <= conv_std_logic_vector(241849240,28);
exponent <= '0';
WHEN "1001000011" =>
manhi <= conv_std_logic_vector(12754106,24);
manlo <= conv_std_logic_vector(1491364,28);
exponent <= '0';
WHEN "1001000100" =>
manhi <= conv_std_logic_vector(12782959,24);
manlo <= conv_std_logic_vector(73395209,28);
exponent <= '0';
WHEN "1001000101" =>
manhi <= conv_std_logic_vector(12811840,24);
manlo <= conv_std_logic_vector(196511758,28);
exponent <= '0';
WHEN "1001000110" =>
manhi <= conv_std_logic_vector(12840750,24);
manlo <= conv_std_logic_vector(109799208,28);
exponent <= '0';
WHEN "1001000111" =>
manhi <= conv_std_logic_vector(12869688,24);
manlo <= conv_std_logic_vector(89093893,28);
exponent <= '0';
WHEN "1001001000" =>
manhi <= conv_std_logic_vector(12898654,24);
manlo <= conv_std_logic_vector(141803923,28);
exponent <= '0';
WHEN "1001001001" =>
manhi <= conv_std_logic_vector(12927649,24);
manlo <= conv_std_logic_vector(6909187,28);
exponent <= '0';
WHEN "1001001010" =>
manhi <= conv_std_logic_vector(12956671,24);
manlo <= conv_std_logic_vector(228703191,28);
exponent <= '0';
WHEN "1001001011" =>
manhi <= conv_std_logic_vector(12985723,24);
manlo <= conv_std_logic_vector(9309409,28);
exponent <= '0';
WHEN "1001001100" =>
manhi <= conv_std_logic_vector(13014802,24);
manlo <= conv_std_logic_vector(161471314,28);
exponent <= '0';
WHEN "1001001101" =>
manhi <= conv_std_logic_vector(13043910,24);
manlo <= conv_std_logic_vector(155762363,28);
exponent <= '0';
WHEN "1001001110" =>
manhi <= conv_std_logic_vector(13073046,24);
manlo <= conv_std_logic_vector(268069656,28);
exponent <= '0';
WHEN "1001001111" =>
manhi <= conv_std_logic_vector(13102211,24);
manlo <= conv_std_logic_vector(237416659,28);
exponent <= '0';
WHEN "1001010000" =>
manhi <= conv_std_logic_vector(13131405,24);
manlo <= conv_std_logic_vector(71269584,28);
exponent <= '0';
WHEN "1001010001" =>
manhi <= conv_std_logic_vector(13160627,24);
manlo <= conv_std_logic_vector(45537394,28);
exponent <= '0';
WHEN "1001010010" =>
manhi <= conv_std_logic_vector(13189877,24);
manlo <= conv_std_logic_vector(167700897,28);
exponent <= '0';
WHEN "1001010011" =>
manhi <= conv_std_logic_vector(13219156,24);
manlo <= conv_std_logic_vector(176812753,28);
exponent <= '0';
WHEN "1001010100" =>
manhi <= conv_std_logic_vector(13248464,24);
manlo <= conv_std_logic_vector(80368396,28);
exponent <= '0';
WHEN "1001010101" =>
manhi <= conv_std_logic_vector(13277800,24);
manlo <= conv_std_logic_vector(154306039,28);
exponent <= '0';
WHEN "1001010110" =>
manhi <= conv_std_logic_vector(13307165,24);
manlo <= conv_std_logic_vector(137700312,28);
exponent <= '0';
WHEN "1001010111" =>
manhi <= conv_std_logic_vector(13336559,24);
manlo <= conv_std_logic_vector(38068641,28);
exponent <= '0';
WHEN "1001011000" =>
manhi <= conv_std_logic_vector(13365981,24);
manlo <= conv_std_logic_vector(131371250,28);
exponent <= '0';
WHEN "1001011001" =>
manhi <= conv_std_logic_vector(13395432,24);
manlo <= conv_std_logic_vector(156704806,28);
exponent <= '0';
WHEN "1001011010" =>
manhi <= conv_std_logic_vector(13424912,24);
manlo <= conv_std_logic_vector(121608790,28);
exponent <= '0';
WHEN "1001011011" =>
manhi <= conv_std_logic_vector(13454421,24);
manlo <= conv_std_logic_vector(33630048,28);
exponent <= '0';
WHEN "1001011100" =>
manhi <= conv_std_logic_vector(13483958,24);
manlo <= conv_std_logic_vector(168758257,28);
exponent <= '0';
WHEN "1001011101" =>
manhi <= conv_std_logic_vector(13513524,24);
manlo <= conv_std_logic_vector(266119562,28);
exponent <= '0';
WHEN "1001011110" =>
manhi <= conv_std_logic_vector(13543120,24);
manlo <= conv_std_logic_vector(64847498,28);
exponent <= '0';
WHEN "1001011111" =>
manhi <= conv_std_logic_vector(13572744,24);
manlo <= conv_std_logic_vector(109389360,28);
exponent <= '0';
WHEN "1001100000" =>
manhi <= conv_std_logic_vector(13602397,24);
manlo <= conv_std_logic_vector(138893481,28);
exponent <= '0';
WHEN "1001100001" =>
manhi <= conv_std_logic_vector(13632079,24);
manlo <= conv_std_logic_vector(160951056,28);
exponent <= '0';
WHEN "1001100010" =>
manhi <= conv_std_logic_vector(13661790,24);
manlo <= conv_std_logic_vector(183160698,28);
exponent <= '0';
WHEN "1001100011" =>
manhi <= conv_std_logic_vector(13691530,24);
manlo <= conv_std_logic_vector(213128447,28);
exponent <= '0';
WHEN "1001100100" =>
manhi <= conv_std_logic_vector(13721299,24);
manlo <= conv_std_logic_vector(258467771,28);
exponent <= '0';
WHEN "1001100101" =>
manhi <= conv_std_logic_vector(13751098,24);
manlo <= conv_std_logic_vector(58364122,28);
exponent <= '0';
WHEN "1001100110" =>
manhi <= conv_std_logic_vector(13780925,24);
manlo <= conv_std_logic_vector(157316766,28);
exponent <= '0';
WHEN "1001100111" =>
manhi <= conv_std_logic_vector(13810782,24);
manlo <= conv_std_logic_vector(26090597,28);
exponent <= '0';
WHEN "1001101000" =>
manhi <= conv_std_logic_vector(13840667,24);
manlo <= conv_std_logic_vector(209199796,28);
exponent <= '0';
WHEN "1001101001" =>
manhi <= conv_std_logic_vector(13870582,24);
manlo <= conv_std_logic_vector(177424185,28);
exponent <= '0';
WHEN "1001101010" =>
manhi <= conv_std_logic_vector(13900526,24);
manlo <= conv_std_logic_vector(206857431,28);
exponent <= '0';
WHEN "1001101011" =>
manhi <= conv_std_logic_vector(13930500,24);
manlo <= conv_std_logic_vector(36729770,28);
exponent <= '0';
WHEN "1001101100" =>
manhi <= conv_std_logic_vector(13960502,24);
manlo <= conv_std_logic_vector(211585297,28);
exponent <= '0';
WHEN "1001101101" =>
manhi <= conv_std_logic_vector(13990534,24);
manlo <= conv_std_logic_vector(202233780,28);
exponent <= '0';
WHEN "1001101110" =>
manhi <= conv_std_logic_vector(14020596,24);
manlo <= conv_std_logic_vector(16363400,28);
exponent <= '0';
WHEN "1001101111" =>
manhi <= conv_std_logic_vector(14050686,24);
manlo <= conv_std_logic_vector(198540768,28);
exponent <= '0';
WHEN "1001110000" =>
manhi <= conv_std_logic_vector(14080806,24);
manlo <= conv_std_logic_vector(219598184,28);
exponent <= '0';
WHEN "1001110001" =>
manhi <= conv_std_logic_vector(14110956,24);
manlo <= conv_std_logic_vector(87246388,28);
exponent <= '0';
WHEN "1001110010" =>
manhi <= conv_std_logic_vector(14141135,24);
manlo <= conv_std_logic_vector(77639113,28);
exponent <= '0';
WHEN "1001110011" =>
manhi <= conv_std_logic_vector(14171343,24);
manlo <= conv_std_logic_vector(198502173,28);
exponent <= '0';
WHEN "1001110100" =>
manhi <= conv_std_logic_vector(14201581,24);
manlo <= conv_std_logic_vector(189133475,28);
exponent <= '0';
WHEN "1001110101" =>
manhi <= conv_std_logic_vector(14231849,24);
manlo <= conv_std_logic_vector(57273941,28);
exponent <= '0';
WHEN "1001110110" =>
manhi <= conv_std_logic_vector(14262146,24);
manlo <= conv_std_logic_vector(79107508,28);
exponent <= '0';
WHEN "1001110111" =>
manhi <= conv_std_logic_vector(14292472,24);
manlo <= conv_std_logic_vector(262390229,28);
exponent <= '0';
WHEN "1001111000" =>
manhi <= conv_std_logic_vector(14322829,24);
manlo <= conv_std_logic_vector(78014825,28);
exponent <= '0';
WHEN "1001111001" =>
manhi <= conv_std_logic_vector(14353215,24);
manlo <= conv_std_logic_vector(70623424,28);
exponent <= '0';
WHEN "1001111010" =>
manhi <= conv_std_logic_vector(14383630,24);
manlo <= conv_std_logic_vector(247994836,28);
exponent <= '0';
WHEN "1001111011" =>
manhi <= conv_std_logic_vector(14414076,24);
manlo <= conv_std_logic_vector(81044559,28);
exponent <= '0';
WHEN "1001111100" =>
manhi <= conv_std_logic_vector(14444551,24);
manlo <= conv_std_logic_vector(114437521,28);
exponent <= '0';
WHEN "1001111101" =>
manhi <= conv_std_logic_vector(14475056,24);
manlo <= conv_std_logic_vector(87539900,28);
exponent <= '0';
WHEN "1001111110" =>
manhi <= conv_std_logic_vector(14505591,24);
manlo <= conv_std_logic_vector(8160950,28);
exponent <= '0';
WHEN "1001111111" =>
manhi <= conv_std_logic_vector(14536155,24);
manlo <= conv_std_logic_vector(152553012,28);
exponent <= '0';
WHEN "1010000000" =>
manhi <= conv_std_logic_vector(14566749,24);
manlo <= conv_std_logic_vector(260105152,28);
exponent <= '0';
WHEN "1010000001" =>
manhi <= conv_std_logic_vector(14597374,24);
manlo <= conv_std_logic_vector(70214083,28);
exponent <= '0';
WHEN "1010000010" =>
manhi <= conv_std_logic_vector(14628028,24);
manlo <= conv_std_logic_vector(127590534,28);
exponent <= '0';
WHEN "1010000011" =>
manhi <= conv_std_logic_vector(14658712,24);
manlo <= conv_std_logic_vector(171646531,28);
exponent <= '0';
WHEN "1010000100" =>
manhi <= conv_std_logic_vector(14689426,24);
manlo <= conv_std_logic_vector(210237219,28);
exponent <= '0';
WHEN "1010000101" =>
manhi <= conv_std_logic_vector(14720170,24);
manlo <= conv_std_logic_vector(251225419,28);
exponent <= '0';
WHEN "1010000110" =>
manhi <= conv_std_logic_vector(14750945,24);
manlo <= conv_std_logic_vector(34046180,28);
exponent <= '0';
WHEN "1010000111" =>
manhi <= conv_std_logic_vector(14781749,24);
manlo <= conv_std_logic_vector(103448606,28);
exponent <= '0';
WHEN "1010001000" =>
manhi <= conv_std_logic_vector(14812583,24);
manlo <= conv_std_logic_vector(198883134,28);
exponent <= '0';
WHEN "1010001001" =>
manhi <= conv_std_logic_vector(14843448,24);
manlo <= conv_std_logic_vector(59807901,28);
exponent <= '0';
WHEN "1010001010" =>
manhi <= conv_std_logic_vector(14874342,24);
manlo <= conv_std_logic_vector(230995129,28);
exponent <= '0';
WHEN "1010001011" =>
manhi <= conv_std_logic_vector(14905267,24);
manlo <= conv_std_logic_vector(183482934,28);
exponent <= '0';
WHEN "1010001100" =>
manhi <= conv_std_logic_vector(14936222,24);
manlo <= conv_std_logic_vector(193623526,28);
exponent <= '0';
WHEN "1010001101" =>
manhi <= conv_std_logic_vector(14967208,24);
manlo <= conv_std_logic_vector(905939,28);
exponent <= '0';
WHEN "1010001110" =>
manhi <= conv_std_logic_vector(14998223,24);
manlo <= conv_std_logic_vector(150133320,28);
exponent <= '0';
WHEN "1010001111" =>
manhi <= conv_std_logic_vector(15029269,24);
manlo <= conv_std_logic_vector(112374738,28);
exponent <= '0';
WHEN "1010010000" =>
manhi <= conv_std_logic_vector(15060345,24);
manlo <= conv_std_logic_vector(164013390,28);
exponent <= '0';
WHEN "1010010001" =>
manhi <= conv_std_logic_vector(15091452,24);
manlo <= conv_std_logic_vector(44569327,28);
exponent <= '0';
WHEN "1010010010" =>
manhi <= conv_std_logic_vector(15122589,24);
manlo <= conv_std_logic_vector(30441282,28);
exponent <= '0';
WHEN "1010010011" =>
manhi <= conv_std_logic_vector(15153756,24);
manlo <= conv_std_logic_vector(129600316,28);
exponent <= '0';
WHEN "1010010100" =>
manhi <= conv_std_logic_vector(15184954,24);
manlo <= conv_std_logic_vector(81589818,28);
exponent <= '0';
WHEN "1010010101" =>
manhi <= conv_std_logic_vector(15216182,24);
manlo <= conv_std_logic_vector(162831889,28);
exponent <= '0';
WHEN "1010010110" =>
manhi <= conv_std_logic_vector(15247441,24);
manlo <= conv_std_logic_vector(112885518,28);
exponent <= '0';
WHEN "1010010111" =>
manhi <= conv_std_logic_vector(15278730,24);
manlo <= conv_std_logic_vector(208188418,28);
exponent <= '0';
WHEN "1010011000" =>
manhi <= conv_std_logic_vector(15310050,24);
manlo <= conv_std_logic_vector(188315209,28);
exponent <= '0';
WHEN "1010011001" =>
manhi <= conv_std_logic_vector(15341401,24);
manlo <= conv_std_logic_vector(61283792,28);
exponent <= '0';
WHEN "1010011010" =>
manhi <= conv_std_logic_vector(15372782,24);
manlo <= conv_std_logic_vector(103555359,28);
exponent <= '0';
WHEN "1010011011" =>
manhi <= conv_std_logic_vector(15404194,24);
manlo <= conv_std_logic_vector(54728032,28);
exponent <= '0';
WHEN "1010011100" =>
manhi <= conv_std_logic_vector(15435636,24);
manlo <= conv_std_logic_vector(191278690,28);
exponent <= '0';
WHEN "1010011101" =>
manhi <= conv_std_logic_vector(15467109,24);
manlo <= conv_std_logic_vector(252821163,28);
exponent <= '0';
WHEN "1010011110" =>
manhi <= conv_std_logic_vector(15498613,24);
manlo <= conv_std_logic_vector(247412597,28);
exponent <= '0';
WHEN "1010011111" =>
manhi <= conv_std_logic_vector(15530148,24);
manlo <= conv_std_logic_vector(183118012,28);
exponent <= '0';
WHEN "1010100000" =>
manhi <= conv_std_logic_vector(15561714,24);
manlo <= conv_std_logic_vector(68010306,28);
exponent <= '0';
WHEN "1010100001" =>
manhi <= conv_std_logic_vector(15593310,24);
manlo <= conv_std_logic_vector(178605723,28);
exponent <= '0';
WHEN "1010100010" =>
manhi <= conv_std_logic_vector(15624937,24);
manlo <= conv_std_logic_vector(254557489,28);
exponent <= '0';
WHEN "1010100011" =>
manhi <= conv_std_logic_vector(15656596,24);
manlo <= conv_std_logic_vector(35526733,28);
exponent <= '0';
WHEN "1010100100" =>
manhi <= conv_std_logic_vector(15688285,24);
manlo <= conv_std_logic_vector(66488863,28);
exponent <= '0';
WHEN "1010100101" =>
manhi <= conv_std_logic_vector(15720005,24);
manlo <= conv_std_logic_vector(87120837,28);
exponent <= '0';
WHEN "1010100110" =>
manhi <= conv_std_logic_vector(15751756,24);
manlo <= conv_std_logic_vector(105542995,28);
exponent <= '0';
WHEN "1010100111" =>
manhi <= conv_std_logic_vector(15783538,24);
manlo <= conv_std_logic_vector(129883612,28);
exponent <= '0';
WHEN "1010101000" =>
manhi <= conv_std_logic_vector(15815351,24);
manlo <= conv_std_logic_vector(168278902,28);
exponent <= '0';
WHEN "1010101001" =>
manhi <= conv_std_logic_vector(15847195,24);
manlo <= conv_std_logic_vector(228873033,28);
exponent <= '0';
WHEN "1010101010" =>
manhi <= conv_std_logic_vector(15879071,24);
manlo <= conv_std_logic_vector(51382669,28);
exponent <= '0';
WHEN "1010101011" =>
manhi <= conv_std_logic_vector(15910977,24);
manlo <= conv_std_logic_vector(180838811,28);
exponent <= '0';
WHEN "1010101100" =>
manhi <= conv_std_logic_vector(15942915,24);
manlo <= conv_std_logic_vector(88538606,28);
exponent <= '0';
WHEN "1010101101" =>
manhi <= conv_std_logic_vector(15974884,24);
manlo <= conv_std_logic_vector(51093552,28);
exponent <= '0';
WHEN "1010101110" =>
manhi <= conv_std_logic_vector(16006884,24);
manlo <= conv_std_logic_vector(76687676,28);
exponent <= '0';
WHEN "1010101111" =>
manhi <= conv_std_logic_vector(16038915,24);
manlo <= conv_std_logic_vector(173513005,28);
exponent <= '0';
WHEN "1010110000" =>
manhi <= conv_std_logic_vector(16070978,24);
manlo <= conv_std_logic_vector(81334110,28);
exponent <= '0';
WHEN "1010110001" =>
manhi <= conv_std_logic_vector(16103072,24);
manlo <= conv_std_logic_vector(76794490,28);
exponent <= '0';
WHEN "1010110010" =>
manhi <= conv_std_logic_vector(16135197,24);
manlo <= conv_std_logic_vector(168110204,28);
exponent <= '0';
WHEN "1010110011" =>
manhi <= conv_std_logic_vector(16167354,24);
manlo <= conv_std_logic_vector(95069884,28);
exponent <= '0';
WHEN "1010110100" =>
manhi <= conv_std_logic_vector(16199542,24);
manlo <= conv_std_logic_vector(134341108,28);
exponent <= '0';
WHEN "1010110101" =>
manhi <= conv_std_logic_vector(16231762,24);
manlo <= conv_std_logic_vector(25728588,28);
exponent <= '0';
WHEN "1010110110" =>
manhi <= conv_std_logic_vector(16264013,24);
manlo <= conv_std_logic_vector(45915996,28);
exponent <= '0';
WHEN "1010110111" =>
manhi <= conv_std_logic_vector(16296295,24);
manlo <= conv_std_logic_vector(203159607,28);
exponent <= '0';
WHEN "1010111000" =>
manhi <= conv_std_logic_vector(16328609,24);
manlo <= conv_std_logic_vector(237288310,28);
exponent <= '0';
WHEN "1010111001" =>
manhi <= conv_std_logic_vector(16360955,24);
manlo <= conv_std_logic_vector(156574520,28);
exponent <= '0';
WHEN "1010111010" =>
manhi <= conv_std_logic_vector(16393332,24);
manlo <= conv_std_logic_vector(237734194,28);
exponent <= '0';
WHEN "1010111011" =>
manhi <= conv_std_logic_vector(16425741,24);
manlo <= conv_std_logic_vector(220620465,28);
exponent <= '0';
WHEN "1010111100" =>
manhi <= conv_std_logic_vector(16458182,24);
manlo <= conv_std_logic_vector(113530022,28);
exponent <= '0';
WHEN "1010111101" =>
manhi <= conv_std_logic_vector(16490654,24);
manlo <= conv_std_logic_vector(193203116,28);
exponent <= '0';
WHEN "1010111110" =>
manhi <= conv_std_logic_vector(16523158,24);
manlo <= conv_std_logic_vector(199517199,28);
exponent <= '0';
WHEN "1010111111" =>
manhi <= conv_std_logic_vector(16555694,24);
manlo <= conv_std_logic_vector(140793302,28);
exponent <= '0';
WHEN "1011000000" =>
manhi <= conv_std_logic_vector(16588262,24);
manlo <= conv_std_logic_vector(25360585,28);
exponent <= '0';
WHEN "1011000001" =>
manhi <= conv_std_logic_vector(16620861,24);
manlo <= conv_std_logic_vector(129991803,28);
exponent <= '0';
WHEN "1011000010" =>
manhi <= conv_std_logic_vector(16653492,24);
manlo <= conv_std_logic_vector(194596944,28);
exponent <= '0';
WHEN "1011000011" =>
manhi <= conv_std_logic_vector(16686155,24);
manlo <= conv_std_logic_vector(227529607,28);
exponent <= '0';
WHEN "1011000100" =>
manhi <= conv_std_logic_vector(16718850,24);
manlo <= conv_std_logic_vector(237151552,28);
exponent <= '0';
WHEN "1011000101" =>
manhi <= conv_std_logic_vector(16751577,24);
manlo <= conv_std_logic_vector(231832709,28);
exponent <= '0';
WHEN "1011000110" =>
manhi <= conv_std_logic_vector(3560,24);
manlo <= conv_std_logic_vector(109975592,28);
exponent <= '1';
WHEN "1011000111" =>
manhi <= conv_std_logic_vector(19955,24);
manlo <= conv_std_logic_vector(239164365,28);
exponent <= '1';
WHEN "1011001000" =>
manhi <= conv_std_logic_vector(36367,24);
manlo <= conv_std_logic_vector(105026731,28);
exponent <= '1';
WHEN "1011001001" =>
manhi <= conv_std_logic_vector(52794,24);
manlo <= conv_std_logic_vector(248634947,28);
exponent <= '1';
WHEN "1011001010" =>
manhi <= conv_std_logic_vector(69238,24);
manlo <= conv_std_logic_vector(137323551,28);
exponent <= '1';
WHEN "1011001011" =>
manhi <= conv_std_logic_vector(85698,24);
manlo <= conv_std_logic_vector(43737556,28);
exponent <= '1';
WHEN "1011001100" =>
manhi <= conv_std_logic_vector(102173,24);
manlo <= conv_std_logic_vector(240526091,28);
exponent <= '1';
WHEN "1011001101" =>
manhi <= conv_std_logic_vector(118665,24);
manlo <= conv_std_logic_vector(195036030,28);
exponent <= '1';
WHEN "1011001110" =>
manhi <= conv_std_logic_vector(135173,24);
manlo <= conv_std_logic_vector(179924739,28);
exponent <= '1';
WHEN "1011001111" =>
manhi <= conv_std_logic_vector(151697,24);
manlo <= conv_std_logic_vector(199418251,28);
exponent <= '1';
WHEN "1011010000" =>
manhi <= conv_std_logic_vector(168237,24);
manlo <= conv_std_logic_vector(257746730,28);
exponent <= '1';
WHEN "1011010001" =>
manhi <= conv_std_logic_vector(184794,24);
manlo <= conv_std_logic_vector(90709016,28);
exponent <= '1';
WHEN "1011010010" =>
manhi <= conv_std_logic_vector(201366,24);
manlo <= conv_std_logic_vector(239414453,28);
exponent <= '1';
WHEN "1011010011" =>
manhi <= conv_std_logic_vector(217955,24);
manlo <= conv_std_logic_vector(171234704,28);
exponent <= '1';
WHEN "1011010100" =>
manhi <= conv_std_logic_vector(234560,24);
manlo <= conv_std_logic_vector(158851944,28);
exponent <= '1';
WHEN "1011010101" =>
manhi <= conv_std_logic_vector(251181,24);
manlo <= conv_std_logic_vector(206517042,28);
exponent <= '1';
WHEN "1011010110" =>
manhi <= conv_std_logic_vector(267819,24);
manlo <= conv_std_logic_vector(50049563,28);
exponent <= '1';
WHEN "1011010111" =>
manhi <= conv_std_logic_vector(284472,24);
manlo <= conv_std_logic_vector(230579599,28);
exponent <= '1';
WHEN "1011011000" =>
manhi <= conv_std_logic_vector(301142,24);
manlo <= conv_std_logic_vector(215499577,28);
exponent <= '1';
WHEN "1011011001" =>
manhi <= conv_std_logic_vector(317829,24);
manlo <= conv_std_logic_vector(9077005,28);
exponent <= '1';
WHEN "1011011010" =>
manhi <= conv_std_logic_vector(334531,24);
manlo <= conv_std_logic_vector(152454469,28);
exponent <= '1';
WHEN "1011011011" =>
manhi <= conv_std_logic_vector(351250,24);
manlo <= conv_std_logic_vector(113036907,28);
exponent <= '1';
WHEN "1011011100" =>
manhi <= conv_std_logic_vector(367985,24);
manlo <= conv_std_logic_vector(163539801,28);
exponent <= '1';
WHEN "1011011101" =>
manhi <= conv_std_logic_vector(384737,24);
manlo <= conv_std_logic_vector(39811903,28);
exponent <= '1';
WHEN "1011011110" =>
manhi <= conv_std_logic_vector(401505,24);
manlo <= conv_std_logic_vector(14577065,28);
exponent <= '1';
WHEN "1011011111" =>
manhi <= conv_std_logic_vector(418289,24);
manlo <= conv_std_logic_vector(92127870,28);
exponent <= '1';
WHEN "1011100000" =>
manhi <= conv_std_logic_vector(435090,24);
manlo <= conv_std_logic_vector(8325641,28);
exponent <= '1';
WHEN "1011100001" =>
manhi <= conv_std_logic_vector(451907,24);
manlo <= conv_std_logic_vector(35906810,28);
exponent <= '1';
WHEN "1011100010" =>
manhi <= conv_std_logic_vector(468740,24);
manlo <= conv_std_logic_vector(179176556,28);
exponent <= '1';
WHEN "1011100011" =>
manhi <= conv_std_logic_vector(485590,24);
manlo <= conv_std_logic_vector(174008808,28);
exponent <= '1';
WHEN "1011100100" =>
manhi <= conv_std_logic_vector(502457,24);
manlo <= conv_std_logic_vector(24717160,28);
exponent <= '1';
WHEN "1011100101" =>
manhi <= conv_std_logic_vector(519340,24);
manlo <= conv_std_logic_vector(4054880,28);
exponent <= '1';
WHEN "1011100110" =>
manhi <= conv_std_logic_vector(536239,24);
manlo <= conv_std_logic_vector(116343996,28);
exponent <= '1';
WHEN "1011100111" =>
manhi <= conv_std_logic_vector(553155,24);
manlo <= conv_std_logic_vector(97475302,28);
exponent <= '1';
WHEN "1011101000" =>
manhi <= conv_std_logic_vector(570087,24);
manlo <= conv_std_logic_vector(220214735,28);
exponent <= '1';
WHEN "1011101001" =>
manhi <= conv_std_logic_vector(587036,24);
manlo <= conv_std_logic_vector(220461546,28);
exponent <= '1';
WHEN "1011101010" =>
manhi <= conv_std_logic_vector(604002,24);
manlo <= conv_std_logic_vector(102554681,28);
exponent <= '1';
WHEN "1011101011" =>
manhi <= conv_std_logic_vector(620984,24);
manlo <= conv_std_logic_vector(139272779,28);
exponent <= '1';
WHEN "1011101100" =>
manhi <= conv_std_logic_vector(637983,24);
manlo <= conv_std_logic_vector(66527812,28);
exponent <= '1';
WHEN "1011101101" =>
manhi <= conv_std_logic_vector(654998,24);
manlo <= conv_std_logic_vector(157106911,28);
exponent <= '1';
WHEN "1011101110" =>
manhi <= conv_std_logic_vector(672030,24);
manlo <= conv_std_logic_vector(146930546,28);
exponent <= '1';
WHEN "1011101111" =>
manhi <= conv_std_logic_vector(689079,24);
manlo <= conv_std_logic_vector(40358901,28);
exponent <= '1';
WHEN "1011110000" =>
manhi <= conv_std_logic_vector(706144,24);
manlo <= conv_std_logic_vector(110191873,28);
exponent <= '1';
WHEN "1011110001" =>
manhi <= conv_std_logic_vector(723226,24);
manlo <= conv_std_logic_vector(92362714,28);
exponent <= '1';
WHEN "1011110010" =>
manhi <= conv_std_logic_vector(740324,24);
manlo <= conv_std_logic_vector(259679855,28);
exponent <= '1';
WHEN "1011110011" =>
manhi <= conv_std_logic_vector(757440,24);
manlo <= conv_std_logic_vector(79649632,28);
exponent <= '1';
WHEN "1011110100" =>
manhi <= conv_std_logic_vector(774572,24);
manlo <= conv_std_logic_vector(93524482,28);
exponent <= '1';
WHEN "1011110101" =>
manhi <= conv_std_logic_vector(791721,24);
manlo <= conv_std_logic_vector(37254754,28);
exponent <= '1';
WHEN "1011110110" =>
manhi <= conv_std_logic_vector(808886,24);
manlo <= conv_std_logic_vector(183665996,28);
exponent <= '1';
WHEN "1011110111" =>
manhi <= conv_std_logic_vector(826069,24);
manlo <= conv_std_logic_vector(281674,28);
exponent <= '1';
WHEN "1011111000" =>
manhi <= conv_std_logic_vector(843268,24);
manlo <= conv_std_logic_vector(28371374,28);
exponent <= '1';
WHEN "1011111001" =>
manhi <= conv_std_logic_vector(860484,24);
manlo <= conv_std_logic_vector(3902612,28);
exponent <= '1';
WHEN "1011111010" =>
manhi <= conv_std_logic_vector(877716,24);
manlo <= conv_std_logic_vector(199718117,28);
exponent <= '1';
WHEN "1011111011" =>
manhi <= conv_std_logic_vector(894966,24);
manlo <= conv_std_logic_vector(83358555,28);
exponent <= '1';
WHEN "1011111100" =>
manhi <= conv_std_logic_vector(912232,24);
manlo <= conv_std_logic_vector(196110728,28);
exponent <= '1';
WHEN "1011111101" =>
manhi <= conv_std_logic_vector(929516,24);
manlo <= conv_std_logic_vector(5523929,28);
exponent <= '1';
WHEN "1011111110" =>
manhi <= conv_std_logic_vector(946816,24);
manlo <= conv_std_logic_vector(52893590,28);
exponent <= '1';
WHEN "1011111111" =>
manhi <= conv_std_logic_vector(964133,24);
manlo <= conv_std_logic_vector(74213103,28);
exponent <= '1';
WHEN "1100000000" =>
manhi <= conv_std_logic_vector(981467,24);
manlo <= conv_std_logic_vector(73915640,28);
exponent <= '1';
WHEN "1100000001" =>
manhi <= conv_std_logic_vector(998818,24);
manlo <= conv_std_logic_vector(56438704,28);
exponent <= '1';
WHEN "1100000010" =>
manhi <= conv_std_logic_vector(1016186,24);
manlo <= conv_std_logic_vector(26224136,28);
exponent <= '1';
WHEN "1100000011" =>
manhi <= conv_std_logic_vector(1033570,24);
manlo <= conv_std_logic_vector(256153571,28);
exponent <= '1';
WHEN "1100000100" =>
manhi <= conv_std_logic_vector(1050972,24);
manlo <= conv_std_logic_vector(213806620,28);
exponent <= '1';
WHEN "1100000101" =>
manhi <= conv_std_logic_vector(1068391,24);
manlo <= conv_std_logic_vector(172073612,28);
exponent <= '1';
WHEN "1100000110" =>
manhi <= conv_std_logic_vector(1085827,24);
manlo <= conv_std_logic_vector(135413771,28);
exponent <= '1';
WHEN "1100000111" =>
manhi <= conv_std_logic_vector(1103280,24);
manlo <= conv_std_logic_vector(108290679,28);
exponent <= '1';
WHEN "1100001000" =>
manhi <= conv_std_logic_vector(1120750,24);
manlo <= conv_std_logic_vector(95172278,28);
exponent <= '1';
WHEN "1100001001" =>
manhi <= conv_std_logic_vector(1138237,24);
manlo <= conv_std_logic_vector(100530876,28);
exponent <= '1';
WHEN "1100001010" =>
manhi <= conv_std_logic_vector(1155741,24);
manlo <= conv_std_logic_vector(128843150,28);
exponent <= '1';
WHEN "1100001011" =>
manhi <= conv_std_logic_vector(1173262,24);
manlo <= conv_std_logic_vector(184590152,28);
exponent <= '1';
WHEN "1100001100" =>
manhi <= conv_std_logic_vector(1190801,24);
manlo <= conv_std_logic_vector(3821855,28);
exponent <= '1';
WHEN "1100001101" =>
manhi <= conv_std_logic_vector(1208356,24);
manlo <= conv_std_logic_vector(127898983,28);
exponent <= '1';
WHEN "1100001110" =>
manhi <= conv_std_logic_vector(1225929,24);
manlo <= conv_std_logic_vector(24444823,28);
exponent <= '1';
WHEN "1100001111" =>
manhi <= conv_std_logic_vector(1243518,24);
manlo <= conv_std_logic_vector(234828877,28);
exponent <= '1';
WHEN "1100010000" =>
manhi <= conv_std_logic_vector(1261125,24);
manlo <= conv_std_logic_vector(226683218,28);
exponent <= '1';
WHEN "1100010001" =>
manhi <= conv_std_logic_vector(1278750,24);
manlo <= conv_std_logic_vector(4515229,28);
exponent <= '1';
WHEN "1100010010" =>
manhi <= conv_std_logic_vector(1296391,24);
manlo <= conv_std_logic_vector(109707612,28);
exponent <= '1';
WHEN "1100010011" =>
manhi <= conv_std_logic_vector(1314050,24);
manlo <= conv_std_logic_vector(9905652,28);
exponent <= '1';
WHEN "1100010100" =>
manhi <= conv_std_logic_vector(1331725,24);
manlo <= conv_std_logic_vector(246500869,28);
exponent <= '1';
WHEN "1100010101" =>
manhi <= conv_std_logic_vector(1349419,24);
manlo <= conv_std_logic_vector(18711921,28);
exponent <= '1';
WHEN "1100010110" =>
manhi <= conv_std_logic_vector(1367129,24);
manlo <= conv_std_logic_vector(136374624,28);
exponent <= '1';
WHEN "1100010111" =>
manhi <= conv_std_logic_vector(1384857,24);
manlo <= conv_std_logic_vector(67151939,28);
exponent <= '1';
WHEN "1100011000" =>
manhi <= conv_std_logic_vector(1402602,24);
manlo <= conv_std_logic_vector(84017623,28);
exponent <= '1';
WHEN "1100011001" =>
manhi <= conv_std_logic_vector(1420364,24);
manlo <= conv_std_logic_vector(191514413,28);
exponent <= '1';
WHEN "1100011010" =>
manhi <= conv_std_logic_vector(1438144,24);
manlo <= conv_std_logic_vector(125754028,28);
exponent <= '1';
WHEN "1100011011" =>
manhi <= conv_std_logic_vector(1455941,24);
manlo <= conv_std_logic_vector(159723541,28);
exponent <= '1';
WHEN "1100011100" =>
manhi <= conv_std_logic_vector(1473756,24);
manlo <= conv_std_logic_vector(29543561,28);
exponent <= '1';
WHEN "1100011101" =>
manhi <= conv_std_logic_vector(1491588,24);
manlo <= conv_std_logic_vector(8210062,28);
exponent <= '1';
WHEN "1100011110" =>
manhi <= conv_std_logic_vector(1509437,24);
manlo <= conv_std_logic_vector(100288013,28);
exponent <= '1';
WHEN "1100011111" =>
manhi <= conv_std_logic_vector(1527304,24);
manlo <= conv_std_logic_vector(41911392,28);
exponent <= '1';
WHEN "1100100000" =>
manhi <= conv_std_logic_vector(1545188,24);
manlo <= conv_std_logic_vector(106089552,28);
exponent <= '1';
WHEN "1100100001" =>
manhi <= conv_std_logic_vector(1563090,24);
manlo <= conv_std_logic_vector(28965402,28);
exponent <= '1';
WHEN "1100100010" =>
manhi <= conv_std_logic_vector(1581009,24);
manlo <= conv_std_logic_vector(83557236,28);
exponent <= '1';
WHEN "1100100011" =>
manhi <= conv_std_logic_vector(1598946,24);
manlo <= conv_std_logic_vector(6016916,28);
exponent <= '1';
WHEN "1100100100" =>
manhi <= conv_std_logic_vector(1616900,24);
manlo <= conv_std_logic_vector(69371695,28);
exponent <= '1';
WHEN "1100100101" =>
manhi <= conv_std_logic_vector(1634872,24);
manlo <= conv_std_logic_vector(9782402,28);
exponent <= '1';
WHEN "1100100110" =>
manhi <= conv_std_logic_vector(1652861,24);
manlo <= conv_std_logic_vector(100285270,28);
exponent <= '1';
WHEN "1100100111" =>
manhi <= conv_std_logic_vector(1670868,24);
manlo <= conv_std_logic_vector(77050112,28);
exponent <= '1';
WHEN "1100101000" =>
manhi <= conv_std_logic_vector(1688892,24);
manlo <= conv_std_logic_vector(213122155,28);
exponent <= '1';
WHEN "1100101001" =>
manhi <= conv_std_logic_vector(1706934,24);
manlo <= conv_std_logic_vector(244680216,28);
exponent <= '1';
WHEN "1100101010" =>
manhi <= conv_std_logic_vector(1724994,24);
manlo <= conv_std_logic_vector(176343080,28);
exponent <= '1';
WHEN "1100101011" =>
manhi <= conv_std_logic_vector(1743072,24);
manlo <= conv_std_logic_vector(12734040,28);
exponent <= '1';
WHEN "1100101100" =>
manhi <= conv_std_logic_vector(1761167,24);
manlo <= conv_std_logic_vector(26916364,28);
exponent <= '1';
WHEN "1100101101" =>
manhi <= conv_std_logic_vector(1779279,24);
manlo <= conv_std_logic_vector(223522388,28);
exponent <= '1';
WHEN "1100101110" =>
manhi <= conv_std_logic_vector(1797410,24);
manlo <= conv_std_logic_vector(70318058,28);
exponent <= '1';
WHEN "1100101111" =>
manhi <= conv_std_logic_vector(1815558,24);
manlo <= conv_std_logic_vector(108815677,28);
exponent <= '1';
WHEN "1100110000" =>
manhi <= conv_std_logic_vector(1833724,24);
manlo <= conv_std_logic_vector(75225715,28);
exponent <= '1';
WHEN "1100110001" =>
manhi <= conv_std_logic_vector(1851907,24);
manlo <= conv_std_logic_vector(242634090,28);
exponent <= '1';
WHEN "1100110010" =>
manhi <= conv_std_logic_vector(1870109,24);
manlo <= conv_std_logic_vector(78824900,28);
exponent <= '1';
WHEN "1100110011" =>
manhi <= conv_std_logic_vector(1888328,24);
manlo <= conv_std_logic_vector(125328613,28);
exponent <= '1';
WHEN "1100110100" =>
manhi <= conv_std_logic_vector(1906565,24);
manlo <= conv_std_logic_vector(118373881,28);
exponent <= '1';
WHEN "1100110101" =>
manhi <= conv_std_logic_vector(1924820,24);
manlo <= conv_std_logic_vector(62629370,28);
exponent <= '1';
WHEN "1100110110" =>
manhi <= conv_std_logic_vector(1943092,24);
manlo <= conv_std_logic_vector(231203763,28);
exponent <= '1';
WHEN "1100110111" =>
manhi <= conv_std_logic_vector(1961383,24);
manlo <= conv_std_logic_vector(91903942,28);
exponent <= '1';
WHEN "1100111000" =>
manhi <= conv_std_logic_vector(1979691,24);
manlo <= conv_std_logic_vector(186283181,28);
exponent <= '1';
WHEN "1100111001" =>
manhi <= conv_std_logic_vector(1998017,24);
manlo <= conv_std_logic_vector(250592964,28);
exponent <= '1';
WHEN "1100111010" =>
manhi <= conv_std_logic_vector(2016362,24);
manlo <= conv_std_logic_vector(21089351,28);
exponent <= '1';
WHEN "1100111011" =>
manhi <= conv_std_logic_vector(2034724,24);
manlo <= conv_std_logic_vector(39339357,28);
exponent <= '1';
WHEN "1100111100" =>
manhi <= conv_std_logic_vector(2053104,24);
manlo <= conv_std_logic_vector(41608216,28);
exponent <= '1';
WHEN "1100111101" =>
manhi <= conv_std_logic_vector(2071502,24);
manlo <= conv_std_logic_vector(32601209,28);
exponent <= '1';
WHEN "1100111110" =>
manhi <= conv_std_logic_vector(2089918,24);
manlo <= conv_std_logic_vector(17028217,28);
exponent <= '1';
WHEN "1100111111" =>
manhi <= conv_std_logic_vector(2108351,24);
manlo <= conv_std_logic_vector(268039176,28);
exponent <= '1';
WHEN "1101000000" =>
manhi <= conv_std_logic_vector(2126803,24);
manlo <= conv_std_logic_vector(253482264,28);
exponent <= '1';
WHEN "1101000001" =>
manhi <= conv_std_logic_vector(2145273,24);
manlo <= conv_std_logic_vector(246516634,28);
exponent <= '1';
WHEN "1101000010" =>
manhi <= conv_std_logic_vector(2163761,24);
manlo <= conv_std_logic_vector(251870600,28);
exponent <= '1';
WHEN "1101000011" =>
manhi <= conv_std_logic_vector(2182268,24);
manlo <= conv_std_logic_vector(5841640,28);
exponent <= '1';
WHEN "1101000100" =>
manhi <= conv_std_logic_vector(2200792,24);
manlo <= conv_std_logic_vector(50038222,28);
exponent <= '1';
WHEN "1101000101" =>
manhi <= conv_std_logic_vector(2219334,24);
manlo <= conv_std_logic_vector(120767079,28);
exponent <= '1';
WHEN "1101000110" =>
manhi <= conv_std_logic_vector(2237894,24);
manlo <= conv_std_logic_vector(222775030,28);
exponent <= '1';
WHEN "1101000111" =>
manhi <= conv_std_logic_vector(2256473,24);
manlo <= conv_std_logic_vector(92378075,28);
exponent <= '1';
WHEN "1101001000" =>
manhi <= conv_std_logic_vector(2275070,24);
manlo <= conv_std_logic_vector(2767772,28);
exponent <= '1';
WHEN "1101001001" =>
manhi <= conv_std_logic_vector(2293684,24);
manlo <= conv_std_logic_vector(227140324,28);
exponent <= '1';
WHEN "1101001010" =>
manhi <= conv_std_logic_vector(2312317,24);
manlo <= conv_std_logic_vector(233390216,28);
exponent <= '1';
WHEN "1101001011" =>
manhi <= conv_std_logic_vector(2330969,24);
manlo <= conv_std_logic_vector(26287503,28);
exponent <= '1';
WHEN "1101001100" =>
manhi <= conv_std_logic_vector(2349638,24);
manlo <= conv_std_logic_vector(147477811,28);
exponent <= '1';
WHEN "1101001101" =>
manhi <= conv_std_logic_vector(2368326,24);
manlo <= conv_std_logic_vector(64869610,28);
exponent <= '1';
WHEN "1101001110" =>
manhi <= conv_std_logic_vector(2387032,24);
manlo <= conv_std_logic_vector(51682404,28);
exponent <= '1';
WHEN "1101001111" =>
manhi <= conv_std_logic_vector(2405756,24);
manlo <= conv_std_logic_vector(112704917,28);
exponent <= '1';
WHEN "1101010000" =>
manhi <= conv_std_logic_vector(2424498,24);
manlo <= conv_std_logic_vector(252730552,28);
exponent <= '1';
WHEN "1101010001" =>
manhi <= conv_std_logic_vector(2443259,24);
manlo <= conv_std_logic_vector(208121938,28);
exponent <= '1';
WHEN "1101010010" =>
manhi <= conv_std_logic_vector(2462038,24);
manlo <= conv_std_logic_vector(252117306,28);
exponent <= '1';
WHEN "1101010011" =>
manhi <= conv_std_logic_vector(2480836,24);
manlo <= conv_std_logic_vector(121088666,28);
exponent <= '1';
WHEN "1101010100" =>
manhi <= conv_std_logic_vector(2499652,24);
manlo <= conv_std_logic_vector(88283637,28);
exponent <= '1';
WHEN "1101010101" =>
manhi <= conv_std_logic_vector(2518486,24);
manlo <= conv_std_logic_vector(158519085,28);
exponent <= '1';
WHEN "1101010110" =>
manhi <= conv_std_logic_vector(2537339,24);
manlo <= conv_std_logic_vector(68181124,28);
exponent <= '1';
WHEN "1101010111" =>
manhi <= conv_std_logic_vector(2556210,24);
manlo <= conv_std_logic_vector(90531494,28);
exponent <= '1';
WHEN "1101011000" =>
manhi <= conv_std_logic_vector(2575099,24);
manlo <= conv_std_logic_vector(230401190,28);
exponent <= '1';
WHEN "1101011001" =>
manhi <= conv_std_logic_vector(2594007,24);
manlo <= conv_std_logic_vector(224190477,28);
exponent <= '1';
WHEN "1101011010" =>
manhi <= conv_std_logic_vector(2612934,24);
manlo <= conv_std_logic_vector(76739795,28);
exponent <= '1';
WHEN "1101011011" =>
manhi <= conv_std_logic_vector(2631879,24);
manlo <= conv_std_logic_vector(61329773,28);
exponent <= '1';
WHEN "1101011100" =>
manhi <= conv_std_logic_vector(2650842,24);
manlo <= conv_std_logic_vector(182810317,28);
exponent <= '1';
WHEN "1101011101" =>
manhi <= conv_std_logic_vector(2669824,24);
manlo <= conv_std_logic_vector(177600614,28);
exponent <= '1';
WHEN "1101011110" =>
manhi <= conv_std_logic_vector(2688825,24);
manlo <= conv_std_logic_vector(50560052,28);
exponent <= '1';
WHEN "1101011111" =>
manhi <= conv_std_logic_vector(2707844,24);
manlo <= conv_std_logic_vector(74988222,28);
exponent <= '1';
WHEN "1101100000" =>
manhi <= conv_std_logic_vector(2726881,24);
manlo <= conv_std_logic_vector(255754012,28);
exponent <= '1';
WHEN "1101100001" =>
manhi <= conv_std_logic_vector(2745938,24);
manlo <= conv_std_logic_vector(60860155,28);
exponent <= '1';
WHEN "1101100010" =>
manhi <= conv_std_logic_vector(2765013,24);
manlo <= conv_std_logic_vector(32055969,28);
exponent <= '1';
WHEN "1101100011" =>
manhi <= conv_std_logic_vector(2784106,24);
manlo <= conv_std_logic_vector(174224628,28);
exponent <= '1';
WHEN "1101100100" =>
manhi <= conv_std_logic_vector(2803218,24);
manlo <= conv_std_logic_vector(223818618,28);
exponent <= '1';
WHEN "1101100101" =>
manhi <= conv_std_logic_vector(2822349,24);
manlo <= conv_std_logic_vector(185730660,28);
exponent <= '1';
WHEN "1101100110" =>
manhi <= conv_std_logic_vector(2841499,24);
manlo <= conv_std_logic_vector(64858254,28);
exponent <= '1';
WHEN "1101100111" =>
manhi <= conv_std_logic_vector(2860667,24);
manlo <= conv_std_logic_vector(134539142,28);
exponent <= '1';
WHEN "1101101000" =>
manhi <= conv_std_logic_vector(2879854,24);
manlo <= conv_std_logic_vector(131244940,28);
exponent <= '1';
WHEN "1101101001" =>
manhi <= conv_std_logic_vector(2899060,24);
manlo <= conv_std_logic_vector(59887520,28);
exponent <= '1';
WHEN "1101101010" =>
manhi <= conv_std_logic_vector(2918284,24);
manlo <= conv_std_logic_vector(193819006,28);
exponent <= '1';
WHEN "1101101011" =>
manhi <= conv_std_logic_vector(2937528,24);
manlo <= conv_std_logic_vector(1089957,28);
exponent <= '1';
WHEN "1101101100" =>
manhi <= conv_std_logic_vector(2956790,24);
manlo <= conv_std_logic_vector(23497566,28);
exponent <= '1';
WHEN "1101101101" =>
manhi <= conv_std_logic_vector(2976070,24);
manlo <= conv_std_logic_vector(265972927,28);
exponent <= '1';
WHEN "1101101110" =>
manhi <= conv_std_logic_vector(2995370,24);
manlo <= conv_std_logic_vector(196581040,28);
exponent <= '1';
WHEN "1101101111" =>
manhi <= conv_std_logic_vector(3014689,24);
manlo <= conv_std_logic_vector(88698094,28);
exponent <= '1';
WHEN "1101110000" =>
manhi <= conv_std_logic_vector(3034026,24);
manlo <= conv_std_logic_vector(215705108,28);
exponent <= '1';
WHEN "1101110001" =>
manhi <= conv_std_logic_vector(3053383,24);
manlo <= conv_std_logic_vector(45681562,28);
exponent <= '1';
WHEN "1101110010" =>
manhi <= conv_std_logic_vector(3072758,24);
manlo <= conv_std_logic_vector(120453600,28);
exponent <= '1';
WHEN "1101110011" =>
manhi <= conv_std_logic_vector(3092152,24);
manlo <= conv_std_logic_vector(176545836,28);
exponent <= '1';
WHEN "1101110100" =>
manhi <= conv_std_logic_vector(3111565,24);
manlo <= conv_std_logic_vector(218923189,28);
exponent <= '1';
WHEN "1101110101" =>
manhi <= conv_std_logic_vector(3130997,24);
manlo <= conv_std_logic_vector(252555427,28);
exponent <= '1';
WHEN "1101110110" =>
manhi <= conv_std_logic_vector(3150449,24);
manlo <= conv_std_logic_vector(13981719,28);
exponent <= '1';
WHEN "1101110111" =>
manhi <= conv_std_logic_vector(3169919,24);
manlo <= conv_std_logic_vector(45052462,28);
exponent <= '1';
WHEN "1101111000" =>
manhi <= conv_std_logic_vector(3189408,24);
manlo <= conv_std_logic_vector(82316549,28);
exponent <= '1';
WHEN "1101111001" =>
manhi <= conv_std_logic_vector(3208916,24);
manlo <= conv_std_logic_vector(130763202,28);
exponent <= '1';
WHEN "1101111010" =>
manhi <= conv_std_logic_vector(3228443,24);
manlo <= conv_std_logic_vector(195386513,28);
exponent <= '1';
WHEN "1101111011" =>
manhi <= conv_std_logic_vector(3247990,24);
manlo <= conv_std_logic_vector(12750002,28);
exponent <= '1';
WHEN "1101111100" =>
manhi <= conv_std_logic_vector(3267555,24);
manlo <= conv_std_logic_vector(124728439,28);
exponent <= '1';
WHEN "1101111101" =>
manhi <= conv_std_logic_vector(3287139,24);
manlo <= conv_std_logic_vector(267895114,28);
exponent <= '1';
WHEN "1101111110" =>
manhi <= conv_std_logic_vector(3306743,24);
manlo <= conv_std_logic_vector(178828213,28);
exponent <= '1';
WHEN "1101111111" =>
manhi <= conv_std_logic_vector(3326366,24);
manlo <= conv_std_logic_vector(130981732,28);
exponent <= '1';
WHEN "1110000000" =>
manhi <= conv_std_logic_vector(3346008,24);
manlo <= conv_std_logic_vector(129379112,28);
exponent <= '1';
WHEN "1110000001" =>
manhi <= conv_std_logic_vector(3365669,24);
manlo <= conv_std_logic_vector(179048704,28);
exponent <= '1';
WHEN "1110000010" =>
manhi <= conv_std_logic_vector(3385350,24);
manlo <= conv_std_logic_vector(16588318,28);
exponent <= '1';
WHEN "1110000011" =>
manhi <= conv_std_logic_vector(3405049,24);
manlo <= conv_std_logic_vector(183907046,28);
exponent <= '1';
WHEN "1110000100" =>
manhi <= conv_std_logic_vector(3424768,24);
manlo <= conv_std_logic_vector(149177079,28);
exponent <= '1';
WHEN "1110000101" =>
manhi <= conv_std_logic_vector(3444506,24);
manlo <= conv_std_logic_vector(185881906,28);
exponent <= '1';
WHEN "1110000110" =>
manhi <= conv_std_logic_vector(3464264,24);
manlo <= conv_std_logic_vector(30639033,28);
exponent <= '1';
WHEN "1110000111" =>
manhi <= conv_std_logic_vector(3484040,24);
manlo <= conv_std_logic_vector(225377274,28);
exponent <= '1';
WHEN "1110001000" =>
manhi <= conv_std_logic_vector(3503836,24);
manlo <= conv_std_logic_vector(238288557,28);
exponent <= '1';
WHEN "1110001001" =>
manhi <= conv_std_logic_vector(3523652,24);
manlo <= conv_std_logic_vector(74440673,28);
exponent <= '1';
WHEN "1110001010" =>
manhi <= conv_std_logic_vector(3543487,24);
manlo <= conv_std_logic_vector(7341816,28);
exponent <= '1';
WHEN "1110001011" =>
manhi <= conv_std_logic_vector(3563341,24);
manlo <= conv_std_logic_vector(42069684,28);
exponent <= '1';
WHEN "1110001100" =>
manhi <= conv_std_logic_vector(3583214,24);
manlo <= conv_std_logic_vector(183706934,28);
exponent <= '1';
WHEN "1110001101" =>
manhi <= conv_std_logic_vector(3603107,24);
manlo <= conv_std_logic_vector(168905734,28);
exponent <= '1';
WHEN "1110001110" =>
manhi <= conv_std_logic_vector(3623020,24);
manlo <= conv_std_logic_vector(2758677,28);
exponent <= '1';
WHEN "1110001111" =>
manhi <= conv_std_logic_vector(3642951,24);
manlo <= conv_std_logic_vector(227234245,28);
exponent <= '1';
WHEN "1110010000" =>
manhi <= conv_std_logic_vector(3662903,24);
manlo <= conv_std_logic_vector(42128622,28);
exponent <= '1';
WHEN "1110010001" =>
manhi <= conv_std_logic_vector(3682873,24);
manlo <= conv_std_logic_vector(257855711,28);
exponent <= '1';
WHEN "1110010010" =>
manhi <= conv_std_logic_vector(3702864,24);
manlo <= conv_std_logic_vector(74221670,28);
exponent <= '1';
WHEN "1110010011" =>
manhi <= conv_std_logic_vector(3722874,24);
manlo <= conv_std_logic_vector(33214933,28);
exponent <= '1';
WHEN "1110010100" =>
manhi <= conv_std_logic_vector(3742903,24);
manlo <= conv_std_logic_vector(139958020,28);
exponent <= '1';
WHEN "1110010101" =>
manhi <= conv_std_logic_vector(3762952,24);
manlo <= conv_std_logic_vector(131143002,28);
exponent <= '1';
WHEN "1110010110" =>
manhi <= conv_std_logic_vector(3783021,24);
manlo <= conv_std_logic_vector(11902416,28);
exponent <= '1';
WHEN "1110010111" =>
manhi <= conv_std_logic_vector(3803109,24);
manlo <= conv_std_logic_vector(55809266,28);
exponent <= '1';
WHEN "1110011000" =>
manhi <= conv_std_logic_vector(3823216,24);
manlo <= conv_std_logic_vector(268006125,28);
exponent <= '1';
WHEN "1110011001" =>
manhi <= conv_std_logic_vector(3843344,24);
manlo <= conv_std_logic_vector(116769675,28);
exponent <= '1';
WHEN "1110011010" =>
manhi <= conv_std_logic_vector(3863491,24);
manlo <= conv_std_logic_vector(144123451,28);
exponent <= '1';
WHEN "1110011011" =>
manhi <= conv_std_logic_vector(3883658,24);
manlo <= conv_std_logic_vector(86789657,28);
exponent <= '1';
WHEN "1110011100" =>
manhi <= conv_std_logic_vector(3903844,24);
manlo <= conv_std_logic_vector(218366446,28);
exponent <= '1';
WHEN "1110011101" =>
manhi <= conv_std_logic_vector(3924051,24);
manlo <= conv_std_logic_vector(7150648,28);
exponent <= '1';
WHEN "1110011110" =>
manhi <= conv_std_logic_vector(3944276,24);
manlo <= conv_std_logic_vector(263621422,28);
exponent <= '1';
WHEN "1110011111" =>
manhi <= conv_std_logic_vector(3964522,24);
manlo <= conv_std_logic_vector(187650244,28);
exponent <= '1';
WHEN "1110100000" =>
manhi <= conv_std_logic_vector(3984788,24);
manlo <= conv_std_logic_vector(52855476,28);
exponent <= '1';
WHEN "1110100001" =>
manhi <= conv_std_logic_vector(4005073,24);
manlo <= conv_std_logic_vector(132860541,28);
exponent <= '1';
WHEN "1110100010" =>
manhi <= conv_std_logic_vector(4025378,24);
manlo <= conv_std_logic_vector(164423019,28);
exponent <= '1';
WHEN "1110100011" =>
manhi <= conv_std_logic_vector(4045703,24);
manlo <= conv_std_logic_vector(152741021,28);
exponent <= '1';
WHEN "1110100100" =>
manhi <= conv_std_logic_vector(4066048,24);
manlo <= conv_std_logic_vector(103017737,28);
exponent <= '1';
WHEN "1110100101" =>
manhi <= conv_std_logic_vector(4086413,24);
manlo <= conv_std_logic_vector(20461438,28);
exponent <= '1';
WHEN "1110100110" =>
manhi <= conv_std_logic_vector(4106797,24);
manlo <= conv_std_logic_vector(178720944,28);
exponent <= '1';
WHEN "1110100111" =>
manhi <= conv_std_logic_vector(4127202,24);
manlo <= conv_std_logic_vector(46143798,28);
exponent <= '1';
WHEN "1110101000" =>
manhi <= conv_std_logic_vector(4147626,24);
manlo <= conv_std_logic_vector(164824464,28);
exponent <= '1';
WHEN "1110101001" =>
manhi <= conv_std_logic_vector(4168071,24);
manlo <= conv_std_logic_vector(3120689,28);
exponent <= '1';
WHEN "1110101010" =>
manhi <= conv_std_logic_vector(4188535,24);
manlo <= conv_std_logic_vector(103137152,28);
exponent <= '1';
WHEN "1110101011" =>
manhi <= conv_std_logic_vector(4209019,24);
manlo <= conv_std_logic_vector(201677275,28);
exponent <= '1';
WHEN "1110101100" =>
manhi <= conv_std_logic_vector(4229524,24);
manlo <= conv_std_logic_vector(35549602,28);
exponent <= '1';
WHEN "1110101101" =>
manhi <= conv_std_logic_vector(4250048,24);
manlo <= conv_std_logic_vector(146874166,28);
exponent <= '1';
WHEN "1110101110" =>
manhi <= conv_std_logic_vector(4270593,24);
manlo <= conv_std_logic_vector(4034305,28);
exponent <= '1';
WHEN "1110101111" =>
manhi <= conv_std_logic_vector(4291157,24);
manlo <= conv_std_logic_vector(149160317,28);
exponent <= '1';
WHEN "1110110000" =>
manhi <= conv_std_logic_vector(4311742,24);
manlo <= conv_std_logic_vector(50645812,28);
exponent <= '1';
WHEN "1110110001" =>
manhi <= conv_std_logic_vector(4332346,24);
manlo <= conv_std_logic_vector(250631368,28);
exponent <= '1';
WHEN "1110110010" =>
manhi <= conv_std_logic_vector(4352971,24);
manlo <= conv_std_logic_vector(217520889,28);
exponent <= '1';
WHEN "1110110011" =>
manhi <= conv_std_logic_vector(4373616,24);
manlo <= conv_std_logic_vector(225029798,28);
exponent <= '1';
WHEN "1110110100" =>
manhi <= conv_std_logic_vector(4394282,24);
manlo <= conv_std_logic_vector(10007770,28);
exponent <= '1';
WHEN "1110110101" =>
manhi <= conv_std_logic_vector(4414967,24);
manlo <= conv_std_logic_vector(114616005,28);
exponent <= '1';
WHEN "1110110110" =>
manhi <= conv_std_logic_vector(4435673,24);
manlo <= conv_std_logic_vector(7279052,28);
exponent <= '1';
WHEN "1110110111" =>
manhi <= conv_std_logic_vector(4456398,24);
manlo <= conv_std_logic_vector(230168458,28);
exponent <= '1';
WHEN "1110111000" =>
manhi <= conv_std_logic_vector(4477144,24);
manlo <= conv_std_logic_vector(251719124,28);
exponent <= '1';
WHEN "1110111001" =>
manhi <= conv_std_logic_vector(4497911,24);
manlo <= conv_std_logic_vector(77242046,28);
exponent <= '1';
WHEN "1110111010" =>
manhi <= conv_std_logic_vector(4518697,24);
manlo <= conv_std_logic_vector(248924323,28);
exponent <= '1';
WHEN "1110111011" =>
manhi <= conv_std_logic_vector(4539504,24);
manlo <= conv_std_logic_vector(235216422,28);
exponent <= '1';
WHEN "1110111100" =>
manhi <= conv_std_logic_vector(4560332,24);
manlo <= conv_std_logic_vector(41444923,28);
exponent <= '1';
WHEN "1110111101" =>
manhi <= conv_std_logic_vector(4581179,24);
manlo <= conv_std_logic_vector(209812522,28);
exponent <= '1';
WHEN "1110111110" =>
manhi <= conv_std_logic_vector(4602047,24);
manlo <= conv_std_logic_vector(208785300,28);
exponent <= '1';
WHEN "1110111111" =>
manhi <= conv_std_logic_vector(4622936,24);
manlo <= conv_std_logic_vector(43705464,28);
exponent <= '1';
WHEN "1111000000" =>
manhi <= conv_std_logic_vector(4643844,24);
manlo <= conv_std_logic_vector(256791352,28);
exponent <= '1';
WHEN "1111000001" =>
manhi <= conv_std_logic_vector(4664774,24);
manlo <= conv_std_logic_vector(48089250,28);
exponent <= '1';
WHEN "1111000010" =>
manhi <= conv_std_logic_vector(4685723,24);
manlo <= conv_std_logic_vector(228263405,28);
exponent <= '1';
WHEN "1111000011" =>
manhi <= conv_std_logic_vector(4706693,24);
manlo <= conv_std_logic_vector(265806023,28);
exponent <= '1';
WHEN "1111000100" =>
manhi <= conv_std_logic_vector(4727684,24);
manlo <= conv_std_logic_vector(166085460,28);
exponent <= '1';
WHEN "1111000101" =>
manhi <= conv_std_logic_vector(4748695,24);
manlo <= conv_std_logic_vector(202910772,28);
exponent <= '1';
WHEN "1111000110" =>
manhi <= conv_std_logic_vector(4769727,24);
manlo <= conv_std_logic_vector(113225356,28);
exponent <= '1';
WHEN "1111000111" =>
manhi <= conv_std_logic_vector(4790779,24);
manlo <= conv_std_logic_vector(170848774,28);
exponent <= '1';
WHEN "1111001000" =>
manhi <= conv_std_logic_vector(4811852,24);
manlo <= conv_std_logic_vector(112734938,28);
exponent <= '1';
WHEN "1111001001" =>
manhi <= conv_std_logic_vector(4832945,24);
manlo <= conv_std_logic_vector(212713936,28);
exponent <= '1';
WHEN "1111001010" =>
manhi <= conv_std_logic_vector(4854059,24);
manlo <= conv_std_logic_vector(207750218,28);
exponent <= '1';
WHEN "1111001011" =>
manhi <= conv_std_logic_vector(4875194,24);
manlo <= conv_std_logic_vector(103248961,28);
exponent <= '1';
WHEN "1111001100" =>
manhi <= conv_std_logic_vector(4896349,24);
manlo <= conv_std_logic_vector(173056083,28);
exponent <= '1';
WHEN "1111001101" =>
manhi <= conv_std_logic_vector(4917525,24);
manlo <= conv_std_logic_vector(154151876,28);
exponent <= '1';
WHEN "1111001110" =>
manhi <= conv_std_logic_vector(4938722,24);
manlo <= conv_std_logic_vector(51957376,28);
exponent <= '1';
WHEN "1111001111" =>
manhi <= conv_std_logic_vector(4959939,24);
manlo <= conv_std_logic_vector(140334376,28);
exponent <= '1';
WHEN "1111010000" =>
manhi <= conv_std_logic_vector(4981177,24);
manlo <= conv_std_logic_vector(156279056,28);
exponent <= '1';
WHEN "1111010001" =>
manhi <= conv_std_logic_vector(5002436,24);
manlo <= conv_std_logic_vector(105228360,28);
exponent <= '1';
WHEN "1111010010" =>
manhi <= conv_std_logic_vector(5023715,24);
manlo <= conv_std_logic_vector(261060000,28);
exponent <= '1';
WHEN "1111010011" =>
manhi <= conv_std_logic_vector(5045016,24);
manlo <= conv_std_logic_vector(92350636,28);
exponent <= '1';
WHEN "1111010100" =>
manhi <= conv_std_logic_vector(5066337,24);
manlo <= conv_std_logic_vector(141424076,28);
exponent <= '1';
WHEN "1111010101" =>
manhi <= conv_std_logic_vector(5087679,24);
manlo <= conv_std_logic_vector(145303087,28);
exponent <= '1';
WHEN "1111010110" =>
manhi <= conv_std_logic_vector(5109042,24);
manlo <= conv_std_logic_vector(109451226,28);
exponent <= '1';
WHEN "1111010111" =>
manhi <= conv_std_logic_vector(5130426,24);
manlo <= conv_std_logic_vector(39337386,28);
exponent <= '1';
WHEN "1111011000" =>
manhi <= conv_std_logic_vector(5151830,24);
manlo <= conv_std_logic_vector(208871261,28);
exponent <= '1';
WHEN "1111011001" =>
manhi <= conv_std_logic_vector(5173256,24);
manlo <= conv_std_logic_vector(86661526,28);
exponent <= '1';
WHEN "1111011010" =>
manhi <= conv_std_logic_vector(5194702,24);
manlo <= conv_std_logic_vector(215064032,28);
exponent <= '1';
WHEN "1111011011" =>
manhi <= conv_std_logic_vector(5216170,24);
manlo <= conv_std_logic_vector(62698166,28);
exponent <= '1';
WHEN "1111011100" =>
manhi <= conv_std_logic_vector(5237658,24);
manlo <= conv_std_logic_vector(171930504,28);
exponent <= '1';
WHEN "1111011101" =>
manhi <= conv_std_logic_vector(5259168,24);
manlo <= conv_std_logic_vector(11391165,28);
exponent <= '1';
WHEN "1111011110" =>
manhi <= conv_std_logic_vector(5280698,24);
manlo <= conv_std_logic_vector(123457470,28);
exponent <= '1';
WHEN "1111011111" =>
manhi <= conv_std_logic_vector(5302249,24);
manlo <= conv_std_logic_vector(245205748,28);
exponent <= '1';
WHEN "1111100000" =>
manhi <= conv_std_logic_vector(5323822,24);
manlo <= conv_std_logic_vector(113717718,28);
exponent <= '1';
WHEN "1111100001" =>
manhi <= conv_std_logic_vector(5345416,24);
manlo <= conv_std_logic_vector(2951399,28);
exponent <= '1';
WHEN "1111100010" =>
manhi <= conv_std_logic_vector(5367030,24);
manlo <= conv_std_logic_vector(186870204,28);
exponent <= '1';
WHEN "1111100011" =>
manhi <= conv_std_logic_vector(5388666,24);
manlo <= conv_std_logic_vector(134136582,28);
exponent <= '1';
WHEN "1111100100" =>
manhi <= conv_std_logic_vector(5410323,24);
manlo <= conv_std_logic_vector(118724754,28);
exponent <= '1';
WHEN "1111100101" =>
manhi <= conv_std_logic_vector(5432001,24);
manlo <= conv_std_logic_vector(146178900,28);
exponent <= '1';
WHEN "1111100110" =>
manhi <= conv_std_logic_vector(5453700,24);
manlo <= conv_std_logic_vector(222048612,28);
exponent <= '1';
WHEN "1111100111" =>
manhi <= conv_std_logic_vector(5475421,24);
manlo <= conv_std_logic_vector(83453453,28);
exponent <= '1';
WHEN "1111101000" =>
manhi <= conv_std_logic_vector(5497163,24);
manlo <= conv_std_logic_vector(4389322,28);
exponent <= '1';
WHEN "1111101001" =>
manhi <= conv_std_logic_vector(5518925,24);
manlo <= conv_std_logic_vector(258857552,28);
exponent <= '1';
WHEN "1111101010" =>
manhi <= conv_std_logic_vector(5540710,24);
manlo <= conv_std_logic_vector(47123091,28);
exponent <= '1';
WHEN "1111101011" =>
manhi <= conv_std_logic_vector(5562515,24);
manlo <= conv_std_logic_vector(180069064,28);
exponent <= '1';
WHEN "1111101100" =>
manhi <= conv_std_logic_vector(5584342,24);
manlo <= conv_std_logic_vector(126406768,28);
exponent <= '1';
WHEN "1111101101" =>
manhi <= conv_std_logic_vector(5606190,24);
manlo <= conv_std_logic_vector(160159320,28);
exponent <= '1';
WHEN "1111101110" =>
manhi <= conv_std_logic_vector(5628060,24);
manlo <= conv_std_logic_vector(18484384,28);
exponent <= '1';
WHEN "1111101111" =>
manhi <= conv_std_logic_vector(5649950,24);
manlo <= conv_std_logic_vector(243851457,28);
exponent <= '1';
WHEN "1111110000" =>
manhi <= conv_std_logic_vector(5671863,24);
manlo <= conv_std_logic_vector(36558227,28);
exponent <= '1';
WHEN "1111110001" =>
manhi <= conv_std_logic_vector(5693796,24);
manlo <= conv_std_logic_vector(207520592,28);
exponent <= '1';
WHEN "1111110010" =>
manhi <= conv_std_logic_vector(5715751,24);
manlo <= conv_std_logic_vector(225482653,28);
exponent <= '1';
WHEN "1111110011" =>
manhi <= conv_std_logic_vector(5737728,24);
manlo <= conv_std_logic_vector(96064906,28);
exponent <= '1';
WHEN "1111110100" =>
manhi <= conv_std_logic_vector(5759726,24);
manlo <= conv_std_logic_vector(93328797,28);
exponent <= '1';
WHEN "1111110101" =>
manhi <= conv_std_logic_vector(5781745,24);
manlo <= conv_std_logic_vector(222905812,28);
exponent <= '1';
WHEN "1111110110" =>
manhi <= conv_std_logic_vector(5803786,24);
manlo <= conv_std_logic_vector(221997482,28);
exponent <= '1';
WHEN "1111110111" =>
manhi <= conv_std_logic_vector(5825849,24);
manlo <= conv_std_logic_vector(96246303,28);
exponent <= '1';
WHEN "1111111000" =>
manhi <= conv_std_logic_vector(5847933,24);
manlo <= conv_std_logic_vector(119735740,28);
exponent <= '1';
WHEN "1111111001" =>
manhi <= conv_std_logic_vector(5870039,24);
manlo <= conv_std_logic_vector(29683863,28);
exponent <= '1';
WHEN "1111111010" =>
manhi <= conv_std_logic_vector(5892166,24);
manlo <= conv_std_logic_vector(100185179,28);
exponent <= '1';
WHEN "1111111011" =>
manhi <= conv_std_logic_vector(5914315,24);
manlo <= conv_std_logic_vector(68468812,28);
exponent <= '1';
WHEN "1111111100" =>
manhi <= conv_std_logic_vector(5936485,24);
manlo <= conv_std_logic_vector(208640332,28);
exponent <= '1';
WHEN "1111111101" =>
manhi <= conv_std_logic_vector(5958677,24);
manlo <= conv_std_logic_vector(257939938,28);
exponent <= '1';
WHEN "1111111110" =>
manhi <= conv_std_logic_vector(5980891,24);
manlo <= conv_std_logic_vector(222048827,28);
exponent <= '1';
WHEN "1111111111" =>
manhi <= conv_std_logic_vector(6003127,24);
manlo <= conv_std_logic_vector(106653752,28);
exponent <= '1';
WHEN others =>
manhi <= conv_std_logic_vector(0,24);
manlo <= conv_std_logic_vector(0,28);
exponent <= '0';
END CASE;
END PROCESS;
END rtl;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
bin_Gray_Processing/ip/Gray_Processing/fp_acos_prep1.vhd
|
10
|
11182
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_ACOS_PREP1.VHD ***
--*** ***
--*** Function: Single Precision Floating Point ***
--*** ACOS/ASIN Setup - generate 1-x, 1-x*x ***
--*** ***
--*** 23/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: Latency = 8 ***
--***************************************************
ENTITY fp_acos_prep1 IS
GENERIC (synthesize : integer := 0);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin: IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
numerator_exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
numerator_mantissa : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
denominator_exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
denominator_mantissa : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_acos_prep1 ;
ARCHITECTURE rtl OF fp_acos_prep1 IS
type denominator_shiftfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (8 DOWNTO 1);
type numerator_fixedpointfftype IS ARRAY (4 DOWNTO 1) OF STD_LOGIC_VECTOR (36 DOWNTO 1);
type denominator_fixedpointfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (36 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissainff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentinff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissaextendff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal numerator_shiftff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal denominator_shiftff : denominator_shiftfftype;
signal x_fixedpointff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal x_squared_fixedpointff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal numerator_fixedpointff : numerator_fixedpointfftype;
signal denominator_fixedpointff : denominator_fixedpointfftype;
signal numerator_leadingff, denominator_leadingff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal numerator_mantissaff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal denominator_mantissaff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal numerator_exponentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal denominator_exponentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissaextend : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal x_fixedpoint : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal x_squared : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal numerator_mantissanode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal numerator_exponentnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal x_squared_fixedpoint : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal denominator_mantissanode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal denominator_exponentnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal numerator_leading : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal denominator_leading : STD_LOGIC_VECTOR (6 DOWNTO 1);
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_rsft36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_clz36
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_lsft36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
gzva: FOR k IN 1 TO 36 GENERATE
zerovec(k) <= '0';
END GENERATE;
pinx: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 8 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissainff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
mantissaextendff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentinff(k) <= '0';
numerator_shiftff(k) <= '0';
denominator_shiftff(1)(k) <= '0';
denominator_shiftff(2)(k) <= '0';
denominator_shiftff(3)(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
x_fixedpointff(k) <= '0';
x_squared_fixedpointff(k) <= '0';
END LOOP;
FOR k IN 1 TO 4 LOOP
FOR j IN 1 TO 36 LOOP
numerator_fixedpointff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO 2 LOOP
FOR j IN 1 TO 36 LOOP
denominator_fixedpointff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO 6 LOOP
numerator_leadingff(k) <= '0';
denominator_leadingff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
numerator_mantissaff(k) <= '0';
denominator_mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
numerator_exponentff(k) <= '0';
denominator_exponentff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff(1) <= signin;
FOR k IN 2 TO 8 LOOP
signff(k) <= signff(k-1);
END LOOP;
mantissainff <= mantissain; -- level 1
exponentinff <= exponentin; -- level 1
mantissaextendff <= mantissaextend; -- level 2
numerator_shiftff <= 127 - exponentinff; -- exponent will always be 127 or less, level 2
denominator_shiftff(1)(8 DOWNTO 1) <= 253 - (exponentinff(7 DOWNTO 1) & '0'); -- level 2
denominator_shiftff(2)(8 DOWNTO 1) <= denominator_shiftff(1)(8 DOWNTO 1); -- level 3
denominator_shiftff(3)(8 DOWNTO 1) <= denominator_shiftff(2)(8 DOWNTO 1); -- level 4
x_fixedpointff <= x_fixedpoint; -- level 3
numerator_fixedpointff(1)(36 DOWNTO 1) <= ('1' & zerovec(35 DOWNTO 1)) - x_fixedpointff; -- level 4
numerator_fixedpointff(2)(36 DOWNTO 1) <= numerator_fixedpointff(1)(36 DOWNTO 1); -- level 5
numerator_fixedpointff(3)(36 DOWNTO 1) <= numerator_fixedpointff(2)(36 DOWNTO 1); -- level 6
numerator_fixedpointff(4)(36 DOWNTO 1) <= numerator_fixedpointff(3)(36 DOWNTO 1); -- level 7
x_squared_fixedpointff <= x_squared_fixedpoint; -- level 5
denominator_fixedpointff(1)(36 DOWNTO 1) <= ('1' & zerovec(35 DOWNTO 1)) - x_squared_fixedpointff; -- level 6
denominator_fixedpointff(2)(36 DOWNTO 1) <= denominator_fixedpointff(1)(36 DOWNTO 1); -- level 7
numerator_leadingff <= numerator_leading; -- level 7
denominator_leadingff <= denominator_leading; -- level 7
numerator_mantissaff <= numerator_mantissanode;
numerator_exponentff <= numerator_exponentnode;
denominator_mantissaff <= denominator_mantissanode;
denominator_exponentff <= denominator_exponentnode;
END IF;
END IF;
END PROCESS;
mantissaextend <= '1' & mantissainff & zerovec(12 DOWNTO 1);
numsr: fp_rsft36
PORT MAP (inbus=>mantissaextendff,shift=>numerator_shiftff(6 DOWNTO 1),
outbus=>x_fixedpoint);
mulxx: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>36,pipes=>3,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>mantissaextend,databb=>mantissaextend,
result=>x_squared);
-- if x^2 <0.5, 1 bit normalization shift, output exp = 126
densr: fp_rsft36
PORT MAP (inbus=>x_squared,shift=>denominator_shiftff(3)(6 DOWNTO 1),
outbus=>x_squared_fixedpoint);
ccznum: fp_clz36
PORT MAP (mantissa=>numerator_fixedpointff(3)(36 DOWNTO 1),
leading=>numerator_leading);
csftnum: fp_lsft36
PORT MAP (inbus=>numerator_fixedpointff(4)(36 DOWNTO 1),shift=>numerator_leadingff,
outbus=>numerator_mantissanode);
numerator_exponentnode <= 127 - ("00" & numerator_leadingff);
cczd: fp_clz36
PORT MAP (mantissa=>denominator_fixedpointff(1)(36 DOWNTO 1),
leading=>denominator_leading);
cnd: fp_lsft36
PORT MAP (inbus=>denominator_fixedpointff(2)(36 DOWNTO 1),shift=>denominator_leadingff,
outbus=>denominator_mantissanode);
denominator_exponentnode <= 127 - ("00" & denominator_leadingff);
--*** OUTPUTS ***
signout <= signff(8);
numerator_mantissa <= numerator_mantissaff;
numerator_exponent <= numerator_exponentff;
denominator_mantissa <= denominator_mantissaff;
denominator_exponent <= denominator_exponentff;
END rtl;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
bin_Gray_Processing/ip/Gray_Processing/fp_lsft78.vhd
|
10
|
3733
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LSFT78.VHD ***
--*** ***
--*** Function: 78 bit Left Shift ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lsft78 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (78 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (78 DOWNTO 1)
);
END fp_lsft78;
ARCHITECTURE rtl of fp_lsft78 IS
signal levzip, levone, levtwo : STD_LOGIC_VECTOR (78 DOWNTO 1);
signal levthr, levfor, levfiv : STD_LOGIC_VECTOR (78 DOWNTO 1);
signal levsix : STD_LOGIC_VECTOR (78 DOWNTO 1);
BEGIN
levzip <= inbus;
levone(1) <= levzip(1) AND NOT(shift(1));
gaa: FOR k IN 2 TO 78 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(1))) OR (levzip(k-1) AND shift(1));
END GENERATE;
levtwo(1) <= levone(1) AND NOT(shift(2));
levtwo(2) <= levone(2) AND NOT(shift(2));
gba: FOR k IN 3 TO 78 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(2))) OR (levone(k-2) AND shift(2));
END GENERATE;
gca: FOR k IN 1 TO 4 GENERATE
levthr(k) <= levtwo(k) AND NOT(shift(3));
END GENERATE;
gcb: FOR k IN 5 TO 78 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(3))) OR (levtwo(k-4) AND shift(3));
END GENERATE;
gda: FOR k IN 1 TO 8 GENERATE
levfor(k) <= levthr(k) AND NOT(shift(4));
END GENERATE;
gdb: FOR k IN 9 TO 78 GENERATE
levfor(k) <= (levthr(k) AND NOT(shift(4))) OR (levthr(k-8) AND shift(4));
END GENERATE;
gea: FOR k IN 1 TO 16 GENERATE
levfiv(k) <= levfor(k) AND NOT(shift(5));
END GENERATE;
geb: FOR k IN 17 TO 78 GENERATE
levfiv(k) <= (levfor(k) AND NOT(shift(5))) OR (levfor(k-16) AND shift(5));
END GENERATE;
gfa: FOR k IN 1 TO 32 GENERATE
levsix(k) <= levfiv(k) AND NOT(shift(6));
END GENERATE;
gfb: FOR k IN 33 TO 78 GENERATE
levsix(k) <= (levfiv(k) AND NOT(shift(6))) OR (levfiv(k-32) AND shift(6));
END GENERATE;
outbus <= levsix;
END;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
bin_Gray_Processing/ip/Gray_Processing/fp_exprnd.vhd
|
10
|
7830
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_EXPRND.VHD ***
--*** ***
--*** Function: FP Exponent Output Block - ***
--*** Rounded ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_exprnd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentexp : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaexp : IN STD_LOGIC_VECTOR (24 DOWNTO 1); -- includes roundbit
nanin : IN STD_LOGIC;
rangeerror : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
underflowout : OUT STD_LOGIC
);
END fp_exprnd;
ARCHITECTURE rtl OF fp_exprnd IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth-1 DOWNTO 1);
signal nanff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal rangeerrorff : STD_LOGIC;
signal overflownode, underflownode : STD_LOGIC;
signal overflowff, underflowff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal manoverflowbitff : STD_LOGIC;
signal roundmantissaff, mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal manoverflow : STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
signal infinitygen : STD_LOGIC_VECTOR (expwidth+1 DOWNTO 1);
signal zerogen : STD_LOGIC_VECTOR (expwidth+1 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO manwidth-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
nanff <= "00";
rangeerrorff <= '0';
overflowff <= "00";
underflowff <= "00";
manoverflowbitff <= '0';
FOR k IN 1 TO manwidth LOOP
roundmantissaff(k) <= '0';
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth+2 LOOP
exponentoneff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
nanff(1) <= nanin;
nanff(2) <= nanff(1);
rangeerrorff <= rangeerror;
overflowff(1) <= overflownode;
overflowff(2) <= overflowff(1);
underflowff(1) <= underflownode;
underflowff(2) <= underflowff(1);
manoverflowbitff <= manoverflow(manwidth+1);
roundmantissaff <= mantissaexp(manwidth+1 DOWNTO 2) + (zerovec & mantissaexp(1));
-- nan takes precedence (set max)
-- nan takes precedence (set max)
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= (roundmantissaff(k) AND setmanzero) OR setmanmax;
END LOOP;
exponentoneff(expwidth+2 DOWNTO 1) <= "00" & exponentexp;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= (exponentnode(k) AND setexpzero) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
exponentnode <= exponentoneff(expwidth+2 DOWNTO 1) +
(zerovec(expwidth+1 DOWNTO 1) & manoverflowbitff);
--*********************************
--*** PREDICT MANTISSA OVERFLOW ***
--*********************************
manoverflow(1) <= mantissaexp(1);
gmoa: FOR k IN 2 TO manwidth+1 GENERATE
manoverflow(k) <= manoverflow(k-1) AND mantissaexp(k);
END GENERATE;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- infinity if exponent == 255
infinitygen(1) <= exponentnode(1);
gia: FOR k IN 2 TO expwidth GENERATE
infinitygen(k) <= infinitygen(k-1) AND exponentnode(k);
END GENERATE;
infinitygen(expwidth+1) <= infinitygen(expwidth) OR
(exponentnode(expwidth+1) AND
NOT(exponentnode(expwidth+2))); -- '1' if infinity
-- zero if exponent == 0
zerogen(1) <= exponentnode(1);
gza: FOR k IN 2 TO expwidth GENERATE
zerogen(k) <= zerogen(k-1) OR exponentnode(k);
END GENERATE;
zerogen(expwidth+1) <= zerogen(expwidth) AND
NOT(exponentnode(expwidth+2)); -- '0' if zero
-- trap any other overflow errors
-- when sign = 0 and rangeerror = 1, overflow
-- when sign = 1 and rangeerror = 1, underflow
overflownode <= NOT(signin) AND rangeerror;
underflownode <= signin AND rangeerror;
-- set mantissa to 0 when infinity or zero condition
setmanzero <= NOT(infinitygen(expwidth+1)) AND zerogen(expwidth+1) AND NOT(rangeerrorff);
-- setmantissa to "11..11" when nan
setmanmax <= nanin;
-- set exponent to 0 when zero condition
setexpzero <= zerogen(expwidth+1);
-- set exponent to "11..11" when nan, infinity, or divide by 0
setexpmax <= nanin OR infinitygen(expwidth+1) OR rangeerrorff;
--***************
--*** OUTPUTS ***
--***************
signout <= '0';
mantissaout <= mantissaff;
exponentout <= exponenttwoff;
-----------------------------------------------
nanout <= nanff(2);
overflowout <= overflowff(2);
underflowout <= underflowff(2);
END rtl;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
bin_Gray_Processing/ip/Gray_Processing/dp_ln_core.vhd
|
10
|
21706
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION LOG(e) - CORE ***
--*** ***
--*** DP_LN_CORE.VHD ***
--*** ***
--*** Function: Double Precision LOG (LN) Core ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 24/04/09 - SIII/SIV multiplier support ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** SII/SIII/SIV Latency = 26 + 7*doublespeed ***
--*** no 54x54 multipliers ***
--***************************************************
ENTITY dp_ln_core IS
GENERIC (
doublespeed : integer := 0; -- 0/1
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aaman : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
aaexp : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
ccman : OUT STD_LOGIC_VECTOR (53 DOWNTO 1);
ccexp : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
ccsgn : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END dp_ln_core;
ARCHITECTURE rtl OF dp_ln_core IS
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
--*** INPUT BLOCK ***
signal aamanff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal aaexpff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal aaexpabsff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaexppos, aaexpneg : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal aaexpabs : STD_LOGIC_VECTOR (10 DOWNTO 1);
--*** TABLES ***
signal lutpowaddff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal lutoneaddff, luttwoaddff : STD_LOGIC_VECTOR (9 DOWNTO 1);
signal lutpowmanff, lutonemanff, luttwomanff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal lutpowexpff, lutoneexpff, luttwoexpff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal lutoneinvff : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal luttwoinvff : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal lutpowmannode, lutonemannode, luttwomannode : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal lutpowexpnode, lutoneexpnode, luttwoexpnode : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal lutoneinvnode : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal luttwoinvnode : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal aanum, aanumdel : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal invonenum : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal mulonenode : STD_LOGIC_VECTOR (65 DOWNTO 1);
signal mulonenormff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal mulonenumdel : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal multwonode : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal multwonormff : STD_LOGIC_VECTOR (71 DOWNTO 1);
--*** SERIES ***
signal squaredterm : STD_LOGIC_VECTOR (48 DOWNTO 1);
signal onethird : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal scaledterm, scaledtermdel : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal cubedterm : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal xtermdel : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal oneterm, twoterm, thrterm : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal oneplustwoterm : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal seriesterm : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal mantissaseries : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exponentseries : STD_LOGIC_VECTOR (11 DOWNTO 1);
--*** ADD LOGS ***
signal zeropow, zeroone, zerotwo : STD_LOGIC;
signal mantissapowernode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal mantissapower : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exponentpower : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal numberone, numberonedel : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal mantissaone : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exponentone : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal mantissaaddone : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exponentaddone : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal mantissatwo : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exponenttwo : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal numbertwo, numbertwodel : STD_LOGIC_VECTOR (75 DOWNTO 1);
signal mantissaaddtwo : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exponentaddtwo : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal numberthr, numberthrdel : STD_LOGIC_VECTOR (75 DOWNTO 1);
signal mantissasum : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal mantissasumabs : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exponentsum : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal mantissanorm : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exponentnorm : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal zeronorm : STD_LOGIC;
signal signff : STD_LOGIC_VECTOR (25+7*doublespeed DOWNTO 1);
component dp_lnlutpow
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
logman : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
logexp : OUT STD_LOGIC_VECTOR (11 DOWNTO 1)
);
end component;
component dp_lnlut9
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
inv : OUT STD_LOGIC_VECTOR (12 DOWNTO 1);
logman : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
logexp : OUT STD_LOGIC_VECTOR (11 DOWNTO 1)
);
end component;
component dp_lnlut18
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
inv : OUT STD_LOGIC_VECTOR (18 DOWNTO 1);
logman : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
logexp : OUT STD_LOGIC_VECTOR (11 DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component dp_fxadd
GENERIC (
width : positive := 64;
pipes : positive := 1;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component dp_fxsub
GENERIC (
width : positive := 64;
pipes : positive := 1;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component dp_lnadd
GENERIC (
speed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aaman : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
aaexp : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
bbman : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
bbexp : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
ccman : OUT STD_LOGIC_VECTOR (64 DOWNTO 1);
ccexp : OUT STD_LOGIC_VECTOR (11 DOWNTO 1)
);
end component;
component dp_lnnorm
GENERIC (
speed : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inman : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
inexp : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
outman : OUT STD_LOGIC_VECTOR (64 DOWNTO 1);
outexp : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
zero : OUT STD_LOGIC
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
--*******************
--*** INPUT BLOCK ***
--*******************
ppin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
aamanff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
aaexpff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
aaexpabsff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aaman; -- level 1
aaexpff <= aaexp; -- level 1
aaexpabsff <= aaexpabs; -- level 2
END IF;
END IF;
END PROCESS;
aaexppos <= ('0' & aaexpff) - "001111111111";
aaexpneg <= "001111111111" - ('0' & aaexpff);
gaba: FOR k IN 1 TO 10 GENERATE
aaexpabs(k) <= (aaexppos(k) AND NOT(aaexppos(12))) OR (aaexpneg(k) AND aaexppos(12));
END GENERATE;
--******************************************
--*** RANGE REDUCTION THROUGH LUT SERIES ***
--******************************************
plut: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 10 LOOP
lutpowaddff(k) <= '0';
END LOOP;
FOR k IN 1 TO 9 LOOP
lutoneaddff(k) <= '0';
luttwoaddff(k) <= '0';
END LOOP;
FOR k IN 1 TO 52 LOOP
lutpowmanff(k) <= '0';
lutonemanff(k) <= '0';
luttwomanff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
lutpowexpff(k) <= '0';
lutoneexpff(k) <= '0';
luttwoexpff(k) <= '0';
END LOOP;
FOR k IN 1 TO 12 LOOP
lutoneinvff(k) <= '0';
END LOOP;
FOR k IN 1 TO 18 LOOP
luttwoinvff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
lutpowaddff <= aaexpabsff; -- level 3
lutoneaddff <= aamanff(52 DOWNTO 44); -- level 2
luttwoaddff <= mulonenormff(55 DOWNTO 47); -- level 8+speed
lutpowmanff <= lutpowmannode; -- level 4
lutpowexpff <= lutpowexpnode; -- level 4
lutoneinvff <= lutoneinvnode; -- level 3
lutonemanff <= lutonemannode; -- level 3
lutoneexpff <= lutoneexpnode; -- level 3
luttwoinvff <= luttwoinvnode; -- level 9+speed
luttwomanff <= luttwomannode; -- level 9+speed
luttwoexpff <= luttwoexpnode; -- level 9+speed
END IF;
END IF;
END PROCESS;
lutpow: dp_lnlutpow
PORT MAP (add=>lutpowaddff,
logman=>lutpowmannode,logexp=>lutpowexpnode);
lutone: dp_lnlut9
PORT MAP (add=>lutoneaddff,
inv=>lutoneinvnode,logman=>lutonemannode,logexp=>lutoneexpnode);
luttwo: dp_lnlut18
PORT MAP (add=>luttwoaddff,
inv=>luttwoinvnode,logman=>luttwomannode,logexp=>luttwoexpnode);
aanum <= '1' & aamanff & '0';
-- level 1 in, level 3 out
delone: fp_del
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aanum,cc=>aanumdel);
invonenum <= lutoneinvff & "000000";
--mulone <= aanum * invone; -- 53*12 = 65
-- level 3 in, level 6+doublespeed out
mulone: fp_fxmul
GENERIC MAP (widthaa=>54,widthbb=>18,widthcc=>65,
pipes=>3+doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>aanumdel,databb=>invonenum,
result=>mulonenode);
--multwo <= mulonenorm(64 DOWNTO 11) * invtwo; -- 54x18=72
-- level 7+speed in, level 9+speed out
deltwo: fp_del
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>mulonenormff(64 DOWNTO 11),cc=>mulonenumdel);
-- level 9+doublespeed in, level 12+2*doublespeed out
multwo: fp_fxmul
GENERIC MAP (widthaa=>54,widthbb=>18,widthcc=>72,
pipes=>3+doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>mulonenumdel,databb=>luttwoinvff,
result=>multwonode);
pmna: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
mulonenormff(k) <= '0';
END LOOP;
FOR k IN 1 TO 71 LOOP
multwonormff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
-- normalize in case input is 1.000000 and inv is 0.5
-- level 7+speed
FOR k IN 1 TO 64 LOOP
mulonenormff(k) <= (mulonenode(k+1) AND mulonenode(65)) OR
(mulonenode(k) AND NOT(mulonenode(65)));
END LOOP;
-- level 13+2*speed
FOR k IN 1 TO 71 LOOP
multwonormff(k) <= (multwonode(k+1) AND multwonode(72)) OR
(multwonode(k) AND NOT(multwonode(72)));
END LOOP;
END IF;
END IF;
END PROCESS;
--************************************
--*** TAYLOR SERIES OF SMALL RANGE ***
--************************************
-- taylor series expansion of subrange (36 bits)
-- x - x*x/2
-- 16 leading bits, so x*x 16 bits down, +1 bit for 1/2
-- 36 lower bits in multwo(54:19)
--square <= multwonorm(54 DOWNTO 19) * multwonorm(54 DOWNTO 19);
-- level 13+2*doublespeed in, 16+2*doublespeed out
multhr: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>48,
pipes=>3,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multwonormff(54 DOWNTO 19),databb=>multwonormff(54 DOWNTO 19),
result=>squaredterm);
onethird <= "010101010101010101";
-- level 13+2*doublespeed in, level 15+2*doublespeed out
mulfor: fp_fxmul
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>18,
pipes=>2,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multwonormff(54 DOWNTO 37),databb=>onethird,
result=>scaledterm);
--level 15+2*doublespeed in, level 16+2*doublespeed out
delthr: fp_del
GENERIC MAP (width=>18,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>scaledterm,cc=>scaledtermdel);
-- level 16+2*doublespeed in, level 18+2*doublespeed out
mulfiv: fp_fxmul
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>32,
pipes=>2,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>squaredterm(48 DOWNTO 31),databb=>scaledtermdel,
result=>cubedterm);
--level 13+2*doublespeed in, level 16+2*doublespeed out
delfor: fp_del
GENERIC MAP (width=>54,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>multwonormff(54 DOWNTO 1),cc=>xtermdel);
-- level 16+2*doublespeed
oneterm <= xtermdel & zerovec(10 DOWNTO 1);
twoterm <= zerovec(17 DOWNTO 1) & squaredterm(48 DOWNTO 2); -- x*x/2
-- level 18+2*doublespeed
thrterm <= zerovec(32 DOWNTO 1) & cubedterm;
--level 16+2*doublespeed in, level 18+2*doublespeed out
tayone: dp_fxsub
GENERIC MAP (width=>64,pipes=>2,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>oneterm,bb=>twoterm,borrowin=>'1',
cc=>oneplustwoterm);
--level 18+2*doublespeed in, level 19+3*doublespeed out
taytwo: dp_fxadd
GENERIC MAP (width=>64,pipes=>1+doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>oneplustwoterm,bb=>thrterm,carryin=>'0',
cc=>seriesterm);
--mantissaseries <= seriesterm;
mantissaseries <= '0' & seriesterm(64 DOWNTO 2);
exponentseries <= conv_std_logic_vector (1006,11);
--18x18
--cubed <= square(72 DOWNTO 55) * multwonorm(54 DOWNTO 37);
--cubedscale <= cubed(36 DOWNTO 19) * onethird;
--**************************
--*** ADD ALL LOGARITHMS ***
--**************************
zeropow <= lutpowexpff(11) OR lutpowexpff(10) OR lutpowexpff(9) OR
lutpowexpff(8) OR lutpowexpff(7) OR lutpowexpff(6) OR
lutpowexpff(5) OR lutpowexpff(4) OR lutpowexpff(3) OR
lutpowexpff(2) OR lutpowexpff(1);
-- level 4
--mantissapower <= zeropow & lutpowmanff & zerovec(11 DOWNTO 1);
--mantissapower <= '0' & zeropow & lutpowmanff & zerovec(10 DOWNTO 1);
mantissapowernode <= '0' & zeropow & lutpowmanff & zerovec(10 DOWNTO 1);
gmpz: FOR k IN 1 TO 64 GENERATE
mantissapower(k) <= mantissapowernode(k) XOR signff(3);
END GENERATE;
exponentpower <= lutpowexpff;
zeroone <= lutoneexpff(11) OR lutoneexpff(10) OR lutoneexpff(9) OR
lutoneexpff(8) OR lutoneexpff(7) OR lutoneexpff(6) OR
lutoneexpff(5) OR lutoneexpff(4) OR lutoneexpff(3) OR
lutoneexpff(2) OR lutoneexpff(1);
-- level 3
numberone <= zeroone & lutonemanff & lutoneexpff;
-- level 3 in, level 4 out
delfiv: fp_del
GENERIC MAP (width=>64,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>numberone,cc=>numberonedel);
--mantissaone <= numberonedel(64 DOWNTO 12) & zerovec(11 DOWNTO 1);
mantissaone <= '0' & numberonedel(64 DOWNTO 12) & zerovec(10 DOWNTO 1);
exponentone <= numberonedel(11 DOWNTO 1);
-- level 4 in, level 10 out
addone: dp_lnadd
GENERIC MAP (speed=>1,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aaman=>mantissapower,aaexp=>exponentpower,
bbman=>mantissaone,bbexp=>exponentone,
ccman=>mantissaaddone,ccexp=>exponentaddone);
zerotwo <= luttwoexpff(11) OR luttwoexpff(10) OR luttwoexpff(9) OR
luttwoexpff(8) OR luttwoexpff(7) OR luttwoexpff(6) OR
luttwoexpff(5) OR luttwoexpff(4) OR luttwoexpff(3) OR
luttwoexpff(2) OR luttwoexpff(1);
-- level 9+doublespeed
--mantissatwo <= zerotwo & luttwomanff & zerovec(11 DOWNTO 1);
mantissatwo <= '0' & zerotwo & luttwomanff & zerovec(10 DOWNTO 1);
exponenttwo <= luttwoexpff;
numbertwo <= mantissatwo & exponenttwo;
gasa: IF (doublespeed = 0) GENERATE
delsix: fp_del
GENERIC MAP (width=>75,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>numbertwo,cc=>numbertwodel);
END GENERATE;
gasb: IF (doublespeed = 1) GENERATE
numbertwodel <= numbertwo;
END GENERATE;
-- level 10 in, level 16 out
addtwo: dp_lnadd
GENERIC MAP (speed=>1,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aaman=>mantissaaddone,aaexp=>exponentaddone,
bbman=>numbertwodel(75 DOWNTO 12),bbexp=>numbertwodel(11 DOWNTO 1),
ccman=>mantissaaddtwo,ccexp=>exponentaddtwo);
numberthr <= mantissaaddtwo & exponentaddtwo;
-- level 16 in, level 19+3*doublespeed out
delsev: fp_del
GENERIC MAP (width=>75,pipes=>3+3*doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>numberthr,cc=>numberthrdel);
-- level 19+3*doublespeed in, level 23+5*doublespeed out
addthr: dp_lnadd
GENERIC MAP (speed=>doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aaman=>mantissaseries,aaexp=>exponentseries,
bbman=>numberthrdel(75 DOWNTO 12),bbexp=>numberthrdel(11 DOWNTO 1),
ccman=>mantissasum,ccexp=>exponentsum);
gmsa: FOR k IN 1 TO 64 GENERATE
mantissasumabs(k) <= mantissasum(k) XOR signff(22+5*doublespeed);
END GENERATE;
-- level 23+5*doublespeed in, level 26+7*doublespeed out
norm: dp_lnnorm
GENERIC MAP (speed=>doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inman=>mantissasumabs,inexp=>exponentsum,
outman=>mantissanorm,outexp=>exponentnorm,
zero=>zeronorm);
psgna: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 25+7*doublespeed LOOP
signff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
signff(1) <= aaexppos(12);
FOR k IN 2 TO 25+7*doublespeed LOOP
signff(k) <= signff(k-1);
END LOOP;
END IF;
END PROCESS;
--***************
--*** OUTPUTS ***
--***************
ccman <= mantissanorm(63 DOWNTO 11);
ccexp <= exponentnorm;
ccsgn <= signff(25+7*doublespeed);
zeroout <= zeronorm;
END rtl;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
Gray_Processing/ip/Gray_Processing/fp_ln1p_double_s5.vhd
|
10
|
825320
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_ln1p_double_s5
-- VHDL created on Tue Apr 9 11:21:08 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_ln1p_double_s5 is
port (
a : in std_logic_vector(63 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(63 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_ln1p_double_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllZWF_uid8_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal cstBias_uid9_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstBiasMO_uid10_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstBiasPWFP1_uid13_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstBiasMWFP1_uid14_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstAllOWE_uid15_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal cstAllZWE_uid17_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal padConst_uid36_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal maskIncrementTable_uid52_fpLogE1pxTest_q : std_logic_vector(52 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal oPlusOFracXNorm_uid61_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal oPlusOFracXNorm_uid61_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal branEnc_uid77_fpLogE1pxTest_q : std_logic_vector(1 downto 0);
signal expB_uid79_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal expB_uid79_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal o2_uid97_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal z2_uid100_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal wideZero_uid104_fpLogE1pxTest_q : std_logic_vector (66 downto 0);
signal addTermOne_uid105_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal addTermOne_uid105_fpLogE1pxTest_q : std_logic_vector (66 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_a : std_logic_vector(118 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_b : std_logic_vector(118 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_q_i : std_logic_vector(118 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_q : std_logic_vector(118 downto 0);
signal cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal expRExt_uid121_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal expRExt_uid121_fpLogE1pxTest_q : std_logic_vector (12 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid144_fpLogE1pxTest_q : std_logic_vector(1 downto 0);
signal oneFracRPostExc2_uid145_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (47 downto 0);
signal rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (2 downto 0);
signal mO_uid193_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(7 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(7 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(1 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(1 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal p1_uid264_constMult_q : std_logic_vector(68 downto 0);
signal rndBit_uid314_natLogPolyEval_q : std_logic_vector (2 downto 0);
signal zs_uid319_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal mO_uid322_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(7 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(7 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid341_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(1 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(1 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid353_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (95 downto 0);
signal leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (5 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_a : std_logic_vector (16 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_b : std_logic_vector (16 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_s1 : std_logic_vector (33 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_pr : SIGNED (34 downto 0);
signal prodXY_uid402_pT1_uid295_natLogPolyEval_q : std_logic_vector (33 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid407_pT2_uid301_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_a : std_logic_vector (2 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_s1 : std_logic_vector (6 downto 0);
signal sm0_uid410_pT2_uid301_natLogPolyEval_pr : UNSIGNED (6 downto 0);
attribute multstyle : string;
attribute multstyle of sm0_uid410_pT2_uid301_natLogPolyEval_pr: signal is "logic";
signal sm0_uid410_pT2_uid301_natLogPolyEval_q : std_logic_vector (6 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_a : std_logic_vector (5 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_s1 : std_logic_vector (6 downto 0);
signal sm1_uid413_pT2_uid301_natLogPolyEval_pr : SIGNED (7 downto 0);
attribute multstyle of sm1_uid413_pT2_uid301_natLogPolyEval_pr: signal is "logic";
signal sm1_uid413_pT2_uid301_natLogPolyEval_q : std_logic_vector (6 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid420_pT3_uid307_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid437_pT4_uid313_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b0_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_pr : SIGNED (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b0_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_pr : UNSIGNED (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b1_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_pr : SIGNED (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b1_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_pr : SIGNED (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a0_b2_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_a : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_pr : SIGNED (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a1_b2_q : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_a : std_logic_vector(84 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_b : std_logic_vector(84 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o : std_logic_vector (84 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q : std_logic_vector (83 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid269_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid269_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid270_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid270_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid271_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid271_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid272_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid272_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid273_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid273_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid274_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid274_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid276_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid276_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid277_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid277_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid278_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid278_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid279_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid279_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid280_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC1_uid280_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid282_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid282_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid283_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid283_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid284_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid284_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid285_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC2_uid285_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid287_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC3_uid287_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid288_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC3_uid288_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid289_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC3_uid289_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC4_uid291_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC4_uid291_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC4_uid292_natLogTabGen_lutmem_ia : std_logic_vector (6 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_iq : std_logic_vector (6 downto 0);
signal memoryC4_uid292_natLogTabGen_lutmem_q : std_logic_vector (6 downto 0);
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a_type;
attribute preserve : boolean;
attribute preserve of multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a : signal is true;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c_type;
attribute preserve of multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c : signal is true;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l_type is array(0 to 1) of SIGNED(18 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y_type;
type multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s : multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s_type;
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s0 : std_logic_vector(36 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_q : std_logic_vector (36 downto 0);
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a : signal is true;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c : signal is true;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y_type;
type multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s : multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s_type;
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_q : std_logic_vector (54 downto 0);
signal reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q : std_logic_vector (0 downto 0);
signal reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q : std_logic_vector (3 downto 0);
signal reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q : std_logic_vector (5 downto 0);
signal reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q : std_logic_vector (52 downto 0);
signal reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q : std_logic_vector (52 downto 0);
signal reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q : std_logic_vector (52 downto 0);
signal reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q : std_logic_vector (105 downto 0);
signal reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q : std_logic_vector (105 downto 0);
signal reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q : std_logic_vector (105 downto 0);
signal reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q : std_logic_vector (105 downto 0);
signal reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q : std_logic_vector (31 downto 0);
signal reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q : std_logic_vector (104 downto 0);
signal reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q : std_logic_vector (104 downto 0);
signal reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q : std_logic_vector (52 downto 0);
signal reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q : std_logic_vector (52 downto 0);
signal reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q : std_logic_vector (52 downto 0);
signal reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q : std_logic_vector (10 downto 0);
signal reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q : std_logic_vector (7 downto 0);
signal reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q : std_logic_vector (7 downto 0);
signal reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q : std_logic_vector (16 downto 0);
signal reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q : std_logic_vector (16 downto 0);
signal reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q : std_logic_vector (7 downto 0);
signal reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q : std_logic_vector (2 downto 0);
signal reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q : std_logic_vector (3 downto 0);
signal reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q : std_logic_vector (5 downto 0);
signal reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q : std_logic_vector (0 downto 0);
signal reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q : std_logic_vector (39 downto 0);
signal reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q : std_logic_vector (29 downto 0);
signal reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q : std_logic_vector (17 downto 0);
signal reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q : std_logic_vector (17 downto 0);
signal reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q : std_logic_vector (16 downto 0);
signal reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q : std_logic_vector (17 downto 0);
signal reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q : std_logic_vector (49 downto 0);
signal reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q : std_logic_vector (40 downto 0);
signal reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q : std_logic_vector (62 downto 0);
signal reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q : std_logic_vector (51 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q : std_logic_vector (53 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q : std_logic_vector (108 downto 0);
signal reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q : std_logic_vector (10 downto 0);
signal reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q : std_logic_vector (10 downto 0);
signal reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q : std_logic_vector (10 downto 0);
signal reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q : std_logic_vector (66 downto 0);
signal reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q : std_logic_vector (58 downto 0);
signal reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q : std_logic_vector (50 downto 0);
signal reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (63 downto 0);
signal reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (31 downto 0);
signal reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q : std_logic_vector (0 downto 0);
signal reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q : std_logic_vector (119 downto 0);
signal reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (119 downto 0);
signal reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q : std_logic_vector (5 downto 0);
signal reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q : std_logic_vector (12 downto 0);
signal reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q : std_logic_vector (65 downto 0);
signal reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q : std_logic_vector (51 downto 0);
signal reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q : std_logic_vector (10 downto 0);
signal ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q : std_logic_vector (63 downto 0);
signal ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q : std_logic_vector (12 downto 0);
signal ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (101 downto 0);
signal ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (97 downto 0);
signal ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (93 downto 0);
signal ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (104 downto 0);
signal ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (103 downto 0);
signal ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (102 downto 0);
signal ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (103 downto 0);
signal ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (102 downto 0);
signal ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (101 downto 0);
signal ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q : std_logic_vector (5 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q : std_logic_vector (55 downto 0);
signal ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q : std_logic_vector (63 downto 0);
signal ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (117 downto 0);
signal ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (115 downto 0);
signal ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (113 downto 0);
signal ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b_q : std_logic_vector (0 downto 0);
signal ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a_q : std_logic_vector (22 downto 0);
signal ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a_q : std_logic_vector (55 downto 0);
signal ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a_q : std_logic_vector (54 downto 0);
signal ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a_q : std_logic_vector (53 downto 0);
signal ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a_q : std_logic_vector (3 downto 0);
signal ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a_q : std_logic_vector (26 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a_q : std_logic_vector (10 downto 0);
signal ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (106 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg_q : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg_q : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (11 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq : std_logic;
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top_q : std_logic_vector (2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg_q : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_reset0 : std_logic;
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q : signal is true;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (11 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (52 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg_q : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg_q : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq : std_logic;
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top_q : std_logic_vector (6 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top_q : std_logic_vector (6 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0 : std_logic;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq : std_logic;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q : signal is true;
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg_q : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ia : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_iq : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q : std_logic_vector (27 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg_q : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ia : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_iq : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_q : std_logic_vector (37 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ia : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_iq : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_q : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg_q : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ia : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_iq : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_q : std_logic_vector (47 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg_q : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ia : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_iq : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_q : std_logic_vector (59 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg_q : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (87 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (55 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (55 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (55 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg_q : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg_q : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0 : std_logic;
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q : std_logic_vector (119 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ia : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_iq : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_q : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg_q : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg_q : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ia : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_iq : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_q : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q : signal is true;
signal pad_o_uid12_uid40_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal fracXz_uid82_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_q : std_logic_vector (23 downto 0);
signal pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_q : std_logic_vector (25 downto 0);
signal pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal InvExpXIsZero_uid29_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid29_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_a : std_logic_vector(66 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_b : std_logic_vector(66 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_o : std_logic_vector (66 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_q : std_logic_vector (66 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_a : std_logic_vector(56 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_b : std_logic_vector(56 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_o : std_logic_vector (56 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q : std_logic_vector (55 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_a : std_logic_vector(54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_b : std_logic_vector(54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_o : std_logic_vector (54 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q : std_logic_vector (54 downto 0);
signal mO_uid130_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_a : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpLogE1pxTest_in : std_logic_vector (62 downto 0);
signal expX_uid6_fpLogE1pxTest_b : std_logic_vector (10 downto 0);
signal signX_uid7_fpLogE1pxTest_in : std_logic_vector (63 downto 0);
signal signX_uid7_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal xM1_uid131_fpLogE1pxTest_a : std_logic_vector(63 downto 0);
signal xM1_uid131_fpLogE1pxTest_b : std_logic_vector(63 downto 0);
signal xM1_uid131_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_a : std_logic_vector(66 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_b : std_logic_vector(66 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_o : std_logic_vector (66 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_a : std_logic_vector(10 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_b : std_logic_vector(10 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_a : std_logic_vector(10 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_b : std_logic_vector(10 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_a : std_logic_vector(106 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_b : std_logic_vector(106 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_o : std_logic_vector (106 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_q : std_logic_vector (106 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_a : std_logic_vector(53 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_b : std_logic_vector(53 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_o : std_logic_vector (53 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal resIsX_uid62_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal resIsX_uid62_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal resIsX_uid62_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal resIsX_uid62_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal resIsX_uid62_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal branch12_uid63_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal branch12_uid63_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal branch12_uid63_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_n : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal branch22_uid66_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal branch22_uid66_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal branch22_uid66_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_n : std_logic_vector (0 downto 0);
signal fracB_uid83_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal fracB_uid83_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal e_uid84_fpLogE1pxTest_a : std_logic_vector(12 downto 0);
signal e_uid84_fpLogE1pxTest_b : std_logic_vector(12 downto 0);
signal e_uid84_fpLogE1pxTest_o : std_logic_vector (12 downto 0);
signal e_uid84_fpLogE1pxTest_q : std_logic_vector (12 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal c_uid87_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal c_uid87_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal c_uid87_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_a : std_logic_vector(67 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_b : std_logic_vector(67 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_o : std_logic_vector (67 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_q : std_logic_vector (67 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_a : std_logic_vector(119 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_b : std_logic_vector(119 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_o : std_logic_vector (119 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_a : std_logic_vector(6 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_b : std_logic_vector(6 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_o : std_logic_vector (6 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_q : std_logic_vector (6 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_a : std_logic_vector(13 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_b : std_logic_vector(13 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_o : std_logic_vector (13 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_q : std_logic_vector (13 downto 0);
signal fracR_uid126_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal fracR_uid126_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal expR_uid128_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal expR_uid128_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid148_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid148_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal expRPostExc_uid152_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid152_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(31 downto 0);
signal vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(31 downto 0);
signal vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(15 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(15 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal p0_uid265_constMult_q : std_logic_vector(62 downto 0);
signal lev1_a0_uid266_constMult_a : std_logic_vector(70 downto 0);
signal lev1_a0_uid266_constMult_b : std_logic_vector(70 downto 0);
signal lev1_a0_uid266_constMult_o : std_logic_vector (70 downto 0);
signal lev1_a0_uid266_constMult_q : std_logic_vector (69 downto 0);
signal ts2_uid304_natLogPolyEval_a : std_logic_vector(40 downto 0);
signal ts2_uid304_natLogPolyEval_b : std_logic_vector(40 downto 0);
signal ts2_uid304_natLogPolyEval_o : std_logic_vector (40 downto 0);
signal ts2_uid304_natLogPolyEval_q : std_logic_vector (40 downto 0);
signal ts3_uid310_natLogPolyEval_a : std_logic_vector(50 downto 0);
signal ts3_uid310_natLogPolyEval_b : std_logic_vector(50 downto 0);
signal ts3_uid310_natLogPolyEval_o : std_logic_vector (50 downto 0);
signal ts3_uid310_natLogPolyEval_q : std_logic_vector (50 downto 0);
signal ts4_uid316_natLogPolyEval_a : std_logic_vector(63 downto 0);
signal ts4_uid316_natLogPolyEval_b : std_logic_vector(63 downto 0);
signal ts4_uid316_natLogPolyEval_o : std_logic_vector (63 downto 0);
signal ts4_uid316_natLogPolyEval_q : std_logic_vector (63 downto 0);
signal vCount_uid321_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(63 downto 0);
signal vCount_uid321_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(63 downto 0);
signal vCount_uid321_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid329_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(31 downto 0);
signal vCount_uid329_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(31 downto 0);
signal vCount_uid329_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid332_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid332_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal vCount_uid335_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(15 downto 0);
signal vCount_uid335_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(15 downto 0);
signal vCount_uid335_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid338_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid338_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid344_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid344_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid356_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid356_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_a : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_b : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_c : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal add0_uid414_pT2_uid301_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_q : std_logic_vector(0 downto 0);
signal sEz_uid98_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal cIncludingRoundingBit_uid303_natLogPolyEval_q : std_logic_vector (39 downto 0);
signal cIncludingRoundingBit_uid309_natLogPolyEval_q : std_logic_vector (49 downto 0);
signal sEz_uid101_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal cIncludingRoundingBit_uid315_natLogPolyEval_q : std_logic_vector (62 downto 0);
signal leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal cStage_uid324_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_in : std_logic_vector (33 downto 0);
signal prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b : std_logic_vector (18 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_0_q_int : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_0_q : std_logic_vector (53 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_in : std_logic_vector (36 downto 0);
signal multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b : std_logic_vector (32 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b : std_logic_vector (51 downto 0);
signal concExc_uid143_fpLogE1pxTest_q : std_logic_vector (2 downto 0);
signal rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal os_uid275_natLogTabGen_q : std_logic_vector (59 downto 0);
signal os_uid281_natLogTabGen_q : std_logic_vector (47 downto 0);
signal os_uid286_natLogTabGen_q : std_logic_vector (37 downto 0);
signal os_uid293_natLogTabGen_q : std_logic_vector (16 downto 0);
signal os_uid290_natLogTabGen_q : std_logic_vector (27 downto 0);
signal finalSum_uid106_uid109_fpLogE1pxTest_q : std_logic_vector (118 downto 0);
signal leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal frac_uid22_fpLogE1pxTest_in : std_logic_vector (51 downto 0);
signal frac_uid22_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal vStagei_uid326_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid326_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_1_q_int : std_logic_vector (82 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_1_q : std_logic_vector (82 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_2_q_int : std_logic_vector (108 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_2_q : std_logic_vector (108 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_3_q_int : std_logic_vector (134 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_align_3_q : std_logic_vector (134 downto 0);
signal redLO_uid47_fpLogE1pxTest_in : std_logic_vector (104 downto 0);
signal redLO_uid47_fpLogE1pxTest_b : std_logic_vector (104 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_a : std_logic_vector(2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_b : std_logic_vector(2 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal zPPolyEval_uid91_fpLogE1pxTest_in : std_logic_vector (42 downto 0);
signal zPPolyEval_uid91_fpLogE1pxTest_b : std_logic_vector (42 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a : std_logic_vector(6 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b : std_logic_vector(6 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_a : std_logic_vector(6 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_b : std_logic_vector(6 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_a : std_logic_vector(6 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_b : std_logic_vector(6 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal RLn_uid153_fpLogE1pxTest_q : std_logic_vector (63 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal yT3_uid306_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal yT3_uid306_natLogPolyEval_b : std_logic_vector (37 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_q : std_logic_vector(0 downto 0);
signal xTop27Bits_uid435_pT4_uid313_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal xTop27Bits_uid435_pT4_uid313_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_q : std_logic_vector(0 downto 0);
signal fracR0_uid125_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracR0_uid125_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal expR_uid127_fpLogE1pxTest_in : std_logic_vector (63 downto 0);
signal expR_uid127_fpLogE1pxTest_b : std_logic_vector (10 downto 0);
signal branch11_uid64_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch11_uid64_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal shifterAddr_uid35_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal shifterAddr_uid35_fpLogE1pxTest_b : std_logic_vector (5 downto 0);
signal oMfracXRSLZCIn_uid43_fpLogE1pxTest_in : std_logic_vector (104 downto 0);
signal oMfracXRSLZCIn_uid43_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal addrMask_uid51_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal addrMask_uid51_fpLogE1pxTest_b : std_logic_vector (5 downto 0);
signal msbUoPlusOFracX_uid54_fpLogE1pxTest_in : std_logic_vector (53 downto 0);
signal msbUoPlusOFracX_uid54_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal oPlusOFracXNormLow_uid57_fpLogE1pxTest_in : std_logic_vector (51 downto 0);
signal oPlusOFracXNormLow_uid57_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal InvResIsX_uid72_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvResIsX_uid72_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal zAddrLow_uid89_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal zAddrLow_uid89_fpLogE1pxTest_b : std_logic_vector (9 downto 0);
signal fracBRed_uid99_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracBRed_uid99_fpLogE1pxTest_b : std_logic_vector (51 downto 0);
signal xv0_uid262_constMult_in : std_logic_vector (5 downto 0);
signal xv0_uid262_constMult_b : std_logic_vector (5 downto 0);
signal xv1_uid263_constMult_in : std_logic_vector (11 downto 0);
signal xv1_uid263_constMult_b : std_logic_vector (5 downto 0);
signal rVStage_uid320_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (119 downto 0);
signal rVStage_uid320_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (63 downto 0);
signal vStage_uid323_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (55 downto 0);
signal vStage_uid323_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (55 downto 0);
signal X87dto0_uid364_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (87 downto 0);
signal X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (87 downto 0);
signal X23dto0_uid370_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (23 downto 0);
signal X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (23 downto 0);
signal expRExt1Red_uid120_fpLogE1pxTest_in : std_logic_vector (12 downto 0);
signal expRExt1Red_uid120_fpLogE1pxTest_b : std_logic_vector (12 downto 0);
signal InvExcRNaN_uid141_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid141_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (103 downto 0);
signal LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (103 downto 0);
signal LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (102 downto 0);
signal LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (102 downto 0);
signal LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (101 downto 0);
signal LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (101 downto 0);
signal sR_uid267_constMult_in : std_logic_vector (68 downto 0);
signal sR_uid267_constMult_b : std_logic_vector (66 downto 0);
signal s2_uid305_natLogPolyEval_in : std_logic_vector (40 downto 0);
signal s2_uid305_natLogPolyEval_b : std_logic_vector (39 downto 0);
signal s3_uid311_natLogPolyEval_in : std_logic_vector (50 downto 0);
signal s3_uid311_natLogPolyEval_b : std_logic_vector (49 downto 0);
signal s4_uid317_natLogPolyEval_in : std_logic_vector (63 downto 0);
signal s4_uid317_natLogPolyEval_b : std_logic_vector (62 downto 0);
signal rVStage_uid334_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid334_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal vStage_uid336_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal vStage_uid336_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid340_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid340_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal vStage_uid342_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal vStage_uid342_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid346_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid346_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal vStage_uid348_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal vStage_uid348_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid358_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid358_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (117 downto 0);
signal LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (117 downto 0);
signal LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (115 downto 0);
signal LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (115 downto 0);
signal LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (113 downto 0);
signal LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (113 downto 0);
signal R_uid417_pT2_uid301_natLogPolyEval_in : std_logic_vector (53 downto 0);
signal R_uid417_pT2_uid301_natLogPolyEval_b : std_logic_vector (29 downto 0);
signal sEz_uid102_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal sEz_uid102_fpLogE1pxTest_q : std_logic_vector (53 downto 0);
signal lowRangeB_uid296_natLogPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid296_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid297_natLogPolyEval_in : std_logic_vector (18 downto 0);
signal highBBits_uid297_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal lowRangeB_uid430_pT3_uid307_natLogPolyEval_in : std_logic_vector (3 downto 0);
signal lowRangeB_uid430_pT3_uid307_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal highBBits_uid431_pT3_uid307_natLogPolyEval_in : std_logic_vector (32 downto 0);
signal highBBits_uid431_pT3_uid307_natLogPolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid445_pT4_uid313_natLogPolyEval_in : std_logic_vector (22 downto 0);
signal lowRangeB_uid445_pT4_uid313_natLogPolyEval_b : std_logic_vector (22 downto 0);
signal highBBits_uid446_pT4_uid313_natLogPolyEval_in : std_logic_vector (51 downto 0);
signal highBBits_uid446_pT4_uid313_natLogPolyEval_b : std_logic_vector (28 downto 0);
signal RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (104 downto 0);
signal RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (103 downto 0);
signal RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (102 downto 0);
signal fracXRS_uid39_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal fracXRS_uid39_fpLogE1pxTest_b : std_logic_vector (53 downto 0);
signal fracXBranch4_uid49_fpLogE1pxTest_in : std_logic_vector (104 downto 0);
signal fracXBranch4_uid49_fpLogE1pxTest_b : std_logic_vector (53 downto 0);
signal FullSumAB118_uid110_fpLogE1pxTest_in : std_logic_vector (118 downto 0);
signal FullSumAB118_uid110_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (118 downto 0);
signal LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (118 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_a : std_logic_vector(51 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_b : std_logic_vector(51 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal oFracX_uid32_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal rVStage_uid328_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid328_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal vStage_uid330_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal vStage_uid330_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_a : std_logic_vector(135 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_b : std_logic_vector(135 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_o : std_logic_vector (135 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q : std_logic_vector (135 downto 0);
signal X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (88 downto 0);
signal X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (88 downto 0);
signal X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (72 downto 0);
signal X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (72 downto 0);
signal X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (56 downto 0);
signal X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (56 downto 0);
signal yT1_uid294_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal yT1_uid294_natLogPolyEval_b : std_logic_vector (16 downto 0);
signal yT2_uid300_natLogPolyEval_in : std_logic_vector (42 downto 0);
signal yT2_uid300_natLogPolyEval_b : std_logic_vector (27 downto 0);
signal xBottomBits_uid439_pT4_uid313_natLogPolyEval_in : std_logic_vector (15 downto 0);
signal xBottomBits_uid439_pT4_uid313_natLogPolyEval_b : std_logic_vector (15 downto 0);
signal xTop27Bits_uid418_pT3_uid307_natLogPolyEval_in : std_logic_vector (37 downto 0);
signal xTop27Bits_uid418_pT3_uid307_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal xTop18Bits_uid421_pT3_uid307_natLogPolyEval_in : std_logic_vector (37 downto 0);
signal xTop18Bits_uid421_pT3_uid307_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid423_pT3_uid307_natLogPolyEval_in : std_logic_vector (10 downto 0);
signal xBottomBits_uid423_pT3_uid307_natLogPolyEval_b : std_logic_vector (10 downto 0);
signal rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (20 downto 0);
signal vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (20 downto 0);
signal join_uid58_fpLogE1pxTest_q : std_logic_vector (52 downto 0);
signal concBranch_uid76_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal addr_uid90_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal signRFull_uid142_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal signRFull_uid142_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal signRFull_uid142_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(3 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(3 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal yTop27Bits_uid419_pT3_uid307_natLogPolyEval_in : std_logic_vector (39 downto 0);
signal yTop27Bits_uid419_pT3_uid307_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid422_pT3_uid307_natLogPolyEval_in : std_logic_vector (12 downto 0);
signal yBottomBits_uid422_pT3_uid307_natLogPolyEval_b : std_logic_vector (12 downto 0);
signal yTop18Bits_uid424_pT3_uid307_natLogPolyEval_in : std_logic_vector (39 downto 0);
signal yTop18Bits_uid424_pT3_uid307_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid436_pT4_uid313_natLogPolyEval_in : std_logic_vector (49 downto 0);
signal yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid438_pT4_uid313_natLogPolyEval_in : std_logic_vector (22 downto 0);
signal yBottomBits_uid438_pT4_uid313_natLogPolyEval_b : std_logic_vector (22 downto 0);
signal peOR_uid93_fpLogE1pxTest_in : std_logic_vector (61 downto 0);
signal peOR_uid93_fpLogE1pxTest_b : std_logic_vector (55 downto 0);
signal vCount_uid347_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(3 downto 0);
signal vCount_uid347_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(3 downto 0);
signal vCount_uid347_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid350_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid350_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal vCount_uid359_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal vCount_uid359_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal vCount_uid359_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_0_in : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_1_in : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a_1_b : std_logic_vector (26 downto 0);
signal sumAHighB_uid298_natLogPolyEval_a : std_logic_vector(28 downto 0);
signal sumAHighB_uid298_natLogPolyEval_b : std_logic_vector(28 downto 0);
signal sumAHighB_uid298_natLogPolyEval_o : std_logic_vector (28 downto 0);
signal sumAHighB_uid298_natLogPolyEval_q : std_logic_vector (28 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid432_pT3_uid307_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid447_pT4_uid313_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal fracXRSRange_uid81_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracXRSRange_uid81_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal fracXBranch4Red_uid80_fpLogE1pxTest_in : std_logic_vector (52 downto 0);
signal fracXBranch4Red_uid80_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal exc_I_uid24_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid24_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid24_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid25_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid25_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightPaddedIn_uid37_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_a : std_logic_vector(136 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_b : std_logic_vector(136 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_o : std_logic_vector (136 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q : std_logic_vector (136 downto 0);
signal leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal xTop27Bits_uid405_pT2_uid301_natLogPolyEval_in : std_logic_vector (27 downto 0);
signal xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal sSM0W_uid409_pT2_uid301_natLogPolyEval_in : std_logic_vector (27 downto 0);
signal sSM0W_uid409_pT2_uid301_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal sSM1W_uid412_pT2_uid301_natLogPolyEval_in : std_logic_vector (0 downto 0);
signal sSM1W_uid412_pT2_uid301_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_q : std_logic_vector (16 downto 0);
signal cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal r_uid225_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (5 downto 0);
signal spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval_q : std_logic_vector (13 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_0_in : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_1_in : std_logic_vector (53 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_2_in : std_logic_vector (80 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b_2_b : std_logic_vector (26 downto 0);
signal rVStage_uid352_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid352_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal vStage_uid354_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal vStage_uid354_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal r_uid360_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (6 downto 0);
signal s1_uid296_uid299_natLogPolyEval_q : std_logic_vector (29 downto 0);
signal add0_uid430_uid433_pT3_uid307_natLogPolyEval_q : std_logic_vector (58 downto 0);
signal add0_uid445_uid448_pT4_uid313_natLogPolyEval_q : std_logic_vector (77 downto 0);
signal leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal InvExc_I_uid28_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid28_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (89 downto 0);
signal X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (73 downto 0);
signal X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (57 downto 0);
signal lowRangeB_uid106_fpLogE1pxTest_in : std_logic_vector (50 downto 0);
signal lowRangeB_uid106_fpLogE1pxTest_b : std_logic_vector (50 downto 0);
signal highBBits_uid107_fpLogE1pxTest_in : std_logic_vector (109 downto 0);
signal highBBits_uid107_fpLogE1pxTest_b : std_logic_vector (58 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_a : std_logic_vector(11 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_b : std_logic_vector(11 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_o : std_logic_vector (11 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_q : std_logic_vector (17 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_a : std_logic_vector(12 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_b : std_logic_vector(12 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_o : std_logic_vector (12 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_q : std_logic_vector (12 downto 0);
signal leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal yTop27Bits_uid406_pT2_uid301_natLogPolyEval_in : std_logic_vector (29 downto 0);
signal yTop27Bits_uid406_pT2_uid301_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal sSM0H_uid408_pT2_uid301_natLogPolyEval_in : std_logic_vector (2 downto 0);
signal sSM0H_uid408_pT2_uid301_natLogPolyEval_b : std_logic_vector (2 downto 0);
signal sSM1H_uid411_pT2_uid301_natLogPolyEval_in : std_logic_vector (29 downto 0);
signal sSM1H_uid411_pT2_uid301_natLogPolyEval_b : std_logic_vector (5 downto 0);
signal R_uid434_pT3_uid307_natLogPolyEval_in : std_logic_vector (57 downto 0);
signal R_uid434_pT3_uid307_natLogPolyEval_b : std_logic_vector (40 downto 0);
signal R_uid449_pT4_uid313_natLogPolyEval_in : std_logic_vector (76 downto 0);
signal R_uid449_pT4_uid313_natLogPolyEval_b : std_logic_vector (51 downto 0);
signal fracR_uid122_fpLogE1pxTest_in : std_logic_vector (118 downto 0);
signal fracR_uid122_fpLogE1pxTest_b : std_logic_vector (52 downto 0);
signal InvExc_N_uid27_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid27_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal expBran3Pre_uid46_fpLogE1pxTest_in : std_logic_vector (10 downto 0);
signal expBran3Pre_uid46_fpLogE1pxTest_b : std_logic_vector (10 downto 0);
signal leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal expFracConc_uid123_fpLogE1pxTest_q : std_logic_vector (65 downto 0);
signal exc_R_uid30_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (105 downto 0);
signal LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (100 downto 0);
signal LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (100 downto 0);
signal LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (96 downto 0);
signal LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (96 downto 0);
signal LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (92 downto 0);
signal LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (92 downto 0);
signal LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (111 downto 0);
signal LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (111 downto 0);
signal LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (103 downto 0);
signal LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (103 downto 0);
signal LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (95 downto 0);
signal LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (95 downto 0);
signal RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (101 downto 0);
signal RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (97 downto 0);
signal RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (105 downto 0);
signal RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (93 downto 0);
signal leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (104 downto 0);
signal leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
signal leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (119 downto 0);
begin
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable(LOGICAL,1343)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_a <= en;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q <= not ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_a;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor(LOGICAL,1572)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q <= not (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a or ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b);
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top(CONSTANT,1568)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top_q <= "0101111";
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp(LOGICAL,1569)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_a <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_mem_top_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q);
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_q <= "1" when ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_a = ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_b else "0";
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg(REG,1570)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena(REG,1573)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q = "1") THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd(LOGICAL,1574)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b <= en;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a and ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b;
--signX_uid7_fpLogE1pxTest(BITSELECT,6)@0
signX_uid7_fpLogE1pxTest_in <= a;
signX_uid7_fpLogE1pxTest_b <= signX_uid7_fpLogE1pxTest_in(63 downto 63);
--ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b(DELAY,800)@0
ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => signX_uid7_fpLogE1pxTest_b, xout => ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWF_uid8_fpLogE1pxTest(CONSTANT,7)
cstAllZWF_uid8_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000000";
--ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a(DELAY,658)@0
ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => a, xout => ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--frac_uid22_fpLogE1pxTest(BITSELECT,21)@1
frac_uid22_fpLogE1pxTest_in <= ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q(51 downto 0);
frac_uid22_fpLogE1pxTest_b <= frac_uid22_fpLogE1pxTest_in(51 downto 0);
--fracXIsZero_uid23_fpLogE1pxTest(LOGICAL,22)@1
fracXIsZero_uid23_fpLogE1pxTest_a <= frac_uid22_fpLogE1pxTest_b;
fracXIsZero_uid23_fpLogE1pxTest_b <= cstAllZWF_uid8_fpLogE1pxTest_q;
fracXIsZero_uid23_fpLogE1pxTest_q <= "1" when fracXIsZero_uid23_fpLogE1pxTest_a = fracXIsZero_uid23_fpLogE1pxTest_b else "0";
--cstAllOWE_uid15_fpLogE1pxTest(CONSTANT,14)
cstAllOWE_uid15_fpLogE1pxTest_q <= "11111111111";
--expX_uid6_fpLogE1pxTest(BITSELECT,5)@0
expX_uid6_fpLogE1pxTest_in <= a(62 downto 0);
expX_uid6_fpLogE1pxTest_b <= expX_uid6_fpLogE1pxTest_in(62 downto 52);
--expXIsMax_uid21_fpLogE1pxTest(LOGICAL,20)@0
expXIsMax_uid21_fpLogE1pxTest_a <= expX_uid6_fpLogE1pxTest_b;
expXIsMax_uid21_fpLogE1pxTest_b <= cstAllOWE_uid15_fpLogE1pxTest_q;
expXIsMax_uid21_fpLogE1pxTest_q <= "1" when expXIsMax_uid21_fpLogE1pxTest_a = expXIsMax_uid21_fpLogE1pxTest_b else "0";
--ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a(DELAY,660)@0
ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsMax_uid21_fpLogE1pxTest_q, xout => ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_I_uid24_fpLogE1pxTest(LOGICAL,23)@1
exc_I_uid24_fpLogE1pxTest_a <= ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q;
exc_I_uid24_fpLogE1pxTest_b <= fracXIsZero_uid23_fpLogE1pxTest_q;
exc_I_uid24_fpLogE1pxTest_q <= exc_I_uid24_fpLogE1pxTest_a and exc_I_uid24_fpLogE1pxTest_b;
--ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a(DELAY,791)@0
ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid7_fpLogE1pxTest_b, xout => ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--negInf_uid138_fpLogE1pxTest(LOGICAL,137)@1
negInf_uid138_fpLogE1pxTest_a <= ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q;
negInf_uid138_fpLogE1pxTest_b <= exc_I_uid24_fpLogE1pxTest_q;
negInf_uid138_fpLogE1pxTest_q_i <= negInf_uid138_fpLogE1pxTest_a and negInf_uid138_fpLogE1pxTest_b;
negInf_uid138_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => negInf_uid138_fpLogE1pxTest_q, xin => negInf_uid138_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--GND(CONSTANT,0)
GND_q <= "0";
--cstBias_uid9_fpLogE1pxTest(CONSTANT,8)
cstBias_uid9_fpLogE1pxTest_q <= "01111111111";
--mO_uid130_fpLogE1pxTest(BITJOIN,129)@0
mO_uid130_fpLogE1pxTest_q <= VCC_q & cstBias_uid9_fpLogE1pxTest_q & cstAllZWF_uid8_fpLogE1pxTest_q;
--xLTM1_uid133_fpLogE1pxTest(COMPARE,132)@0
xLTM1_uid133_fpLogE1pxTest_cin <= GND_q;
xLTM1_uid133_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & mO_uid130_fpLogE1pxTest_q) & '0';
xLTM1_uid133_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & a) & xLTM1_uid133_fpLogE1pxTest_cin(0);
xLTM1_uid133_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xLTM1_uid133_fpLogE1pxTest_a) - UNSIGNED(xLTM1_uid133_fpLogE1pxTest_b));
xLTM1_uid133_fpLogE1pxTest_c(0) <= xLTM1_uid133_fpLogE1pxTest_o(66);
--ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b(DELAY,794)@0
ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xLTM1_uid133_fpLogE1pxTest_c, xout => ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvFracXIsZero_uid25_fpLogE1pxTest(LOGICAL,24)@1
InvFracXIsZero_uid25_fpLogE1pxTest_a <= fracXIsZero_uid23_fpLogE1pxTest_q;
InvFracXIsZero_uid25_fpLogE1pxTest_q <= not InvFracXIsZero_uid25_fpLogE1pxTest_a;
--exc_N_uid26_fpLogE1pxTest(LOGICAL,25)@1
exc_N_uid26_fpLogE1pxTest_a <= ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q;
exc_N_uid26_fpLogE1pxTest_b <= InvFracXIsZero_uid25_fpLogE1pxTest_q;
exc_N_uid26_fpLogE1pxTest_q <= exc_N_uid26_fpLogE1pxTest_a and exc_N_uid26_fpLogE1pxTest_b;
--InvExc_N_uid27_fpLogE1pxTest(LOGICAL,26)@1
InvExc_N_uid27_fpLogE1pxTest_a <= exc_N_uid26_fpLogE1pxTest_q;
InvExc_N_uid27_fpLogE1pxTest_q <= not InvExc_N_uid27_fpLogE1pxTest_a;
--InvExc_I_uid28_fpLogE1pxTest(LOGICAL,27)@1
InvExc_I_uid28_fpLogE1pxTest_a <= exc_I_uid24_fpLogE1pxTest_q;
InvExc_I_uid28_fpLogE1pxTest_q <= not InvExc_I_uid28_fpLogE1pxTest_a;
--cstAllZWE_uid17_fpLogE1pxTest(CONSTANT,16)
cstAllZWE_uid17_fpLogE1pxTest_q <= "00000000000";
--expXIsZero_uid19_fpLogE1pxTest(LOGICAL,18)@0
expXIsZero_uid19_fpLogE1pxTest_a <= expX_uid6_fpLogE1pxTest_b;
expXIsZero_uid19_fpLogE1pxTest_b <= cstAllZWE_uid17_fpLogE1pxTest_q;
expXIsZero_uid19_fpLogE1pxTest_q <= "1" when expXIsZero_uid19_fpLogE1pxTest_a = expXIsZero_uid19_fpLogE1pxTest_b else "0";
--ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a(DELAY,667)@0
ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid19_fpLogE1pxTest_q, xout => ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExpXIsZero_uid29_fpLogE1pxTest(LOGICAL,28)@1
InvExpXIsZero_uid29_fpLogE1pxTest_a <= ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q;
InvExpXIsZero_uid29_fpLogE1pxTest_q <= not InvExpXIsZero_uid29_fpLogE1pxTest_a;
--exc_R_uid30_fpLogE1pxTest(LOGICAL,29)@1
exc_R_uid30_fpLogE1pxTest_a <= InvExpXIsZero_uid29_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_b <= InvExc_I_uid28_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_c <= InvExc_N_uid27_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_q <= exc_R_uid30_fpLogE1pxTest_a and exc_R_uid30_fpLogE1pxTest_b and exc_R_uid30_fpLogE1pxTest_c;
--excRNaN0_uid139_fpLogE1pxTest(LOGICAL,138)@1
excRNaN0_uid139_fpLogE1pxTest_a <= exc_R_uid30_fpLogE1pxTest_q;
excRNaN0_uid139_fpLogE1pxTest_b <= ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q;
excRNaN0_uid139_fpLogE1pxTest_q_i <= excRNaN0_uid139_fpLogE1pxTest_a and excRNaN0_uid139_fpLogE1pxTest_b;
excRNaN0_uid139_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => excRNaN0_uid139_fpLogE1pxTest_q, xin => excRNaN0_uid139_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1(REG,491)@1
reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q <= exc_N_uid26_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--excRNaN_uid140_fpLogE1pxTest(LOGICAL,139)@2
excRNaN_uid140_fpLogE1pxTest_a <= reg_exc_N_uid26_fpLogE1pxTest_0_to_excRNaN_uid140_fpLogE1pxTest_1_q;
excRNaN_uid140_fpLogE1pxTest_b <= excRNaN0_uid139_fpLogE1pxTest_q;
excRNaN_uid140_fpLogE1pxTest_c <= negInf_uid138_fpLogE1pxTest_q;
excRNaN_uid140_fpLogE1pxTest_q <= excRNaN_uid140_fpLogE1pxTest_a or excRNaN_uid140_fpLogE1pxTest_b or excRNaN_uid140_fpLogE1pxTest_c;
--InvExcRNaN_uid141_fpLogE1pxTest(LOGICAL,140)@2
InvExcRNaN_uid141_fpLogE1pxTest_a <= excRNaN_uid140_fpLogE1pxTest_q;
InvExcRNaN_uid141_fpLogE1pxTest_q <= not InvExcRNaN_uid141_fpLogE1pxTest_a;
--signRFull_uid142_fpLogE1pxTest(LOGICAL,141)@2
signRFull_uid142_fpLogE1pxTest_a <= InvExcRNaN_uid141_fpLogE1pxTest_q;
signRFull_uid142_fpLogE1pxTest_b <= ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q;
signRFull_uid142_fpLogE1pxTest_q <= signRFull_uid142_fpLogE1pxTest_a and signRFull_uid142_fpLogE1pxTest_b;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg(DELAY,1562)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signRFull_uid142_fpLogE1pxTest_q, xout => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt(COUNTER,1564)
-- every=1, low=0, high=47, step=1, init=1
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i = 46 THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_eq = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i - 47;
ELSE
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_i,6));
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg(REG,1565)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux(MUX,1566)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s <= en;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux: PROCESS (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s, ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q, ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q)
BEGIN
CASE ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_s IS
WHEN "0" => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q;
WHEN "1" => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem(DUALMEM,1563)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdreg_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_rdmux_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 48,
width_b => 1,
widthad_b => 6,
numwords_b => 48,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq,
address_a => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa,
data_a => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia
);
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0 <= areset;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq(0 downto 0);
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor(LOGICAL,1546)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q <= not (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a or ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b);
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top(CONSTANT,1542)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top_q <= "0110001";
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp(LOGICAL,1543)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_a <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_mem_top_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q);
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_q <= "1" when ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_a = ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_b else "0";
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg(REG,1544)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena(REG,1547)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd(LOGICAL,1548)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b <= en;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a and ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg(DELAY,1536)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 11, depth => 1 )
PORT MAP ( xin => expX_uid6_fpLogE1pxTest_b, xout => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt(COUNTER,1538)
-- every=1, low=0, high=49, step=1, init=1
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i = 48 THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_eq = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i - 49;
ELSE
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_i,6));
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg(REG,1539)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux(MUX,1540)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s <= en;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux: PROCESS (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s, ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q, ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_s IS
WHEN "0" => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q;
WHEN "1" => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem(DUALMEM,1537)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_rdmux_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 6,
numwords_a => 50,
width_b => 11,
widthad_b => 6,
numwords_b => 50,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia
);
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq(10 downto 0);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor(LOGICAL,1509)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q <= not (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a or ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top(CONSTANT,1505)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q <= "0100011";
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp(LOGICAL,1506)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q <= "1" when ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a = ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b else "0";
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg(REG,1507)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena(REG,1510)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd(LOGICAL,1511)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b <= en;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a and ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b;
--cstBiasMO_uid10_fpLogE1pxTest(CONSTANT,9)
cstBiasMO_uid10_fpLogE1pxTest_q <= "01111111110";
--expXIsMo_uid86_fpLogE1pxTest(COMPARE,85)@0
expXIsMo_uid86_fpLogE1pxTest_cin <= GND_q;
expXIsMo_uid86_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
expXIsMo_uid86_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMO_uid10_fpLogE1pxTest_q) & expXIsMo_uid86_fpLogE1pxTest_cin(0);
expXIsMo_uid86_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXIsMo_uid86_fpLogE1pxTest_a) - UNSIGNED(expXIsMo_uid86_fpLogE1pxTest_b));
expXIsMo_uid86_fpLogE1pxTest_c(0) <= expXIsMo_uid86_fpLogE1pxTest_o(13);
--ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b(DELAY,733)@0
ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => expXIsMo_uid86_fpLogE1pxTest_c, xout => ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstBiasMWFP1_uid14_fpLogE1pxTest(CONSTANT,13)
cstBiasMWFP1_uid14_fpLogE1pxTest_q <= "01111001010";
--resIsX_uid62_fpLogE1pxTest(COMPARE,61)@0
resIsX_uid62_fpLogE1pxTest_cin <= GND_q;
resIsX_uid62_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
resIsX_uid62_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMWFP1_uid14_fpLogE1pxTest_q) & resIsX_uid62_fpLogE1pxTest_cin(0);
resIsX_uid62_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(resIsX_uid62_fpLogE1pxTest_a) - UNSIGNED(resIsX_uid62_fpLogE1pxTest_b));
resIsX_uid62_fpLogE1pxTest_c(0) <= resIsX_uid62_fpLogE1pxTest_o(13);
--InvResIsX_uid72_fpLogE1pxTest(LOGICAL,71)@0
InvResIsX_uid72_fpLogE1pxTest_a <= resIsX_uid62_fpLogE1pxTest_c;
InvResIsX_uid72_fpLogE1pxTest_q <= not InvResIsX_uid72_fpLogE1pxTest_a;
--branch22_uid66_fpLogE1pxTest(COMPARE,65)@0
branch22_uid66_fpLogE1pxTest_cin <= GND_q;
branch22_uid66_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
branch22_uid66_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid9_fpLogE1pxTest_q) & branch22_uid66_fpLogE1pxTest_cin(0);
branch22_uid66_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch22_uid66_fpLogE1pxTest_a) - UNSIGNED(branch22_uid66_fpLogE1pxTest_b));
branch22_uid66_fpLogE1pxTest_c(0) <= branch22_uid66_fpLogE1pxTest_o(13);
branch22_uid66_fpLogE1pxTest_n(0) <= not branch22_uid66_fpLogE1pxTest_o(13);
--branch4_uid75_fpLogE1pxTest(LOGICAL,74)@0
branch4_uid75_fpLogE1pxTest_a <= branch22_uid66_fpLogE1pxTest_c;
branch4_uid75_fpLogE1pxTest_b <= InvResIsX_uid72_fpLogE1pxTest_q;
branch4_uid75_fpLogE1pxTest_c <= signX_uid7_fpLogE1pxTest_b;
branch4_uid75_fpLogE1pxTest_q <= branch4_uid75_fpLogE1pxTest_a and branch4_uid75_fpLogE1pxTest_b and branch4_uid75_fpLogE1pxTest_c;
--ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a(DELAY,732)@0
ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => branch4_uid75_fpLogE1pxTest_q, xout => ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--c_uid87_fpLogE1pxTest(LOGICAL,86)@10
c_uid87_fpLogE1pxTest_a <= ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q;
c_uid87_fpLogE1pxTest_b <= ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q;
c_uid87_fpLogE1pxTest_q <= c_uid87_fpLogE1pxTest_a and c_uid87_fpLogE1pxTest_b;
--reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1(REG,529)@10
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q <= c_uid87_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor(LOGICAL,1496)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_b <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_q <= not (ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_a or ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_b);
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top(CONSTANT,1492)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top_q <= "0111";
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp(LOGICAL,1493)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_a <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_mem_top_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q);
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_q <= "1" when ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_a = ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_b else "0";
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg(REG,1494)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena(REG,1497)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_nor_q = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd(LOGICAL,1498)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_a <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_b <= en;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_a and ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_b;
--shifterAddrExt_uid34_fpLogE1pxTest(SUB,33)@0
shifterAddrExt_uid34_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
shifterAddrExt_uid34_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpLogE1pxTest_b);
shifterAddrExt_uid34_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shifterAddrExt_uid34_fpLogE1pxTest_a) - UNSIGNED(shifterAddrExt_uid34_fpLogE1pxTest_b));
shifterAddrExt_uid34_fpLogE1pxTest_q <= shifterAddrExt_uid34_fpLogE1pxTest_o(11 downto 0);
--shifterAddr_uid35_fpLogE1pxTest(BITSELECT,34)@0
shifterAddr_uid35_fpLogE1pxTest_in <= shifterAddrExt_uid34_fpLogE1pxTest_q(5 downto 0);
shifterAddr_uid35_fpLogE1pxTest_b <= shifterAddr_uid35_fpLogE1pxTest_in(5 downto 0);
--reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0(REG,645)@0
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q <= shifterAddr_uid35_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg(DELAY,1486)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q, xout => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1488)
-- every=1, low=0, high=7, step=1, init=1
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_i,3));
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg(REG,1489)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux(MUX,1490)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s, ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q, ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem(DUALMEM,1487)
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ia <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_inputreg_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_aa <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ab <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 3,
numwords_a => 8,
width_b => 6,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_ia
);
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_q <= ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_iq(5 downto 0);
--branch4ExpCorrection_uid118_fpLogE1pxTest(SUB,117)@11
branch4ExpCorrection_uid118_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & ld_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q_to_branch4ExpCorrection_uid118_fpLogE1pxTest_a_replace_mem_q);
branch4ExpCorrection_uid118_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000" & reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q);
branch4ExpCorrection_uid118_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch4ExpCorrection_uid118_fpLogE1pxTest_a) - UNSIGNED(branch4ExpCorrection_uid118_fpLogE1pxTest_b));
branch4ExpCorrection_uid118_fpLogE1pxTest_q <= branch4ExpCorrection_uid118_fpLogE1pxTest_o(6 downto 0);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg(DELAY,1499)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => branch4ExpCorrection_uid118_fpLogE1pxTest_q, xout => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1501)
-- every=1, low=0, high=35, step=1, init=1
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i = 34 THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i - 35;
ELSE
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i,6));
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg(REG,1502)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux(MUX,1503)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s, ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q, ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem(DUALMEM,1500)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 6,
numwords_a => 36,
width_b => 7,
widthad_b => 6,
numwords_b => 36,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia
);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq(6 downto 0);
--zs_uid319_countZ_uid114_fpLogE1pxTest(CONSTANT,318)
zs_uid319_countZ_uid114_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor(LOGICAL,1433)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_b <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_q <= not (ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_a or ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_b);
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg(REG,1342)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena(REG,1434)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_nor_q = "1") THEN
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd(LOGICAL,1435)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_a <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_sticky_ena_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_b <= en;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_q <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_a and ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_b;
--X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,234)@8
X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(56 downto 0);
X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_in(56 downto 0);
--rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,162)
rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q <= "000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,235)@8
leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X56dto0_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q;
--X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,231)@8
X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(72 downto 0);
X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_in(72 downto 0);
--rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,159)
rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,232)@8
leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X72dto0_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
--X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,228)@8
X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(88 downto 0);
X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_in(88 downto 0);
--rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,156)
rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q <= "0000000000000000";
--leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,229)@8
leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X88dto0_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor(LOGICAL,1344)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_b <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_q <= not (ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_a or ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_b);
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena(REG,1345)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_nor_q = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd(LOGICAL,1346)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_sticky_ena_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_b <= en;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_a and ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_b;
--X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,161)@1
X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_b <= X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 48);
--rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,163)@1
rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx3Pad48_uid163_fracXRSExt_uid36_fpLogE1pxTest_q & X105dto48_uid162_fracXRSExt_uid36_fpLogE1pxTest_b;
--X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,158)@1
X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_b <= X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 32);
--rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,160)@1
rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q & X105dto32_uid159_fracXRSExt_uid36_fpLogE1pxTest_b;
--X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,155)@1
X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_b <= X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 16);
--rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,157)@1
rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q & X105dto16_uid156_fracXRSExt_uid36_fpLogE1pxTest_b;
--oFracX_uid32_fpLogE1pxTest(BITJOIN,31)@1
oFracX_uid32_fpLogE1pxTest_q <= VCC_q & frac_uid22_fpLogE1pxTest_b;
--padConst_uid36_fpLogE1pxTest(CONSTANT,35)
padConst_uid36_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000000";
--rightPaddedIn_uid37_fpLogE1pxTest(BITJOIN,36)@1
rightPaddedIn_uid37_fpLogE1pxTest_q <= oFracX_uid32_fpLogE1pxTest_q & padConst_uid36_fpLogE1pxTest_q;
--rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,164)@0
rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b;
rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_in(5 downto 4);
--reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1(REG,499)@0
reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q <= rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest(MUX,165)@1
rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s <= reg_rightShiftStageSel5Dto4_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q;
rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s, en, rightPaddedIn_uid37_fpLogE1pxTest_q, rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightPaddedIn_uid37_fpLogE1pxTest_q;
WHEN "01" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,172)@1
RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 12);
--ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,829)@1
ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 94, depth => 1 )
PORT MAP ( xin => RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,174)@2
rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage0105dto12_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,170)
rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q <= "00000000";
--RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,169)@1
RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 8);
--ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,827)@1
ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 98, depth => 1 )
PORT MAP ( xin => RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,171)@2
rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage0105dto8_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,167)
rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q <= "0000";
--RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,166)@1
RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 4);
--ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,825)@1
ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 102, depth => 1 )
PORT MAP ( xin => RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,168)@2
rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage0105dto4_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2(REG,501)@1
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,175)@0
rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b(3 downto 0);
rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_in(3 downto 2);
--ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a(DELAY,1183)@0
ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1(REG,500)@1
reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q <= ld_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_b_to_reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_a_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest(MUX,176)@2
rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s <= reg_rightShiftStageSel3Dto2_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q;
rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s, en, reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q, rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q;
WHEN "01" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,183)@2
RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 3);
--ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,841)@2
ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 103, depth => 1 )
PORT MAP ( xin => RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,185)@3
rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage1105dto3_uid184_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--z2_uid100_fpLogE1pxTest(CONSTANT,99)
z2_uid100_fpLogE1pxTest_q <= "00";
--RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,180)@2
RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 2);
--ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,839)@2
ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 104, depth => 1 )
PORT MAP ( xin => RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,182)@3
rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q <= z2_uid100_fpLogE1pxTest_q & ld_RightShiftStage1105dto2_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,177)@2
RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in(105 downto 1);
--ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,837)@2
ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 105, depth => 1 )
PORT MAP ( xin => RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,179)@3
rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q <= GND_q & ld_RightShiftStage1105dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2(REG,503)@2
reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,186)@0
rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b(1 downto 0);
rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_in(1 downto 0);
--reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1(REG,502)@0
reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q <= rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b(DELAY,843)@1
ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q, xout => ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest(MUX,187)@3
rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s <= ld_reg_rightShiftStageSel1Dto0_uid187_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_b_q;
rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s, en, reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q, rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= reg_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_2_q;
WHEN "01" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx2_uid183_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx3_uid186_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1(REG,505)@3
reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q <= rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--pad_o_uid12_uid40_fpLogE1pxTest(BITJOIN,39)@3
pad_o_uid12_uid40_fpLogE1pxTest_q <= VCC_q & STD_LOGIC_VECTOR((104 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0(REG,504)@3
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q <= pad_o_uid12_uid40_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--oMfracXRSExt_uid40_fpLogE1pxTest(SUB,40)@4
oMfracXRSExt_uid40_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q);
oMfracXRSExt_uid40_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & reg_rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q);
oMfracXRSExt_uid40_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMfracXRSExt_uid40_fpLogE1pxTest_a) - UNSIGNED(oMfracXRSExt_uid40_fpLogE1pxTest_b));
oMfracXRSExt_uid40_fpLogE1pxTest_q <= oMfracXRSExt_uid40_fpLogE1pxTest_o(106 downto 0);
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg(DELAY,1336)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 107, depth => 1 )
PORT MAP ( xin => oMfracXRSExt_uid40_fpLogE1pxTest_q, xout => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem(DUALMEM,1337)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ia <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 107,
widthad_a => 1,
numwords_a => 2,
width_b => 107,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_ia
);
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_iq(106 downto 0);
--redLO_uid47_fpLogE1pxTest(BITSELECT,46)@8
redLO_uid47_fpLogE1pxTest_in <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_mem_q(104 downto 0);
redLO_uid47_fpLogE1pxTest_b <= redLO_uid47_fpLogE1pxTest_in(104 downto 0);
--oMfracXRSLZCIn_uid43_fpLogE1pxTest(BITSELECT,42)@4
oMfracXRSLZCIn_uid43_fpLogE1pxTest_in <= oMfracXRSExt_uid40_fpLogE1pxTest_q(104 downto 0);
oMfracXRSLZCIn_uid43_fpLogE1pxTest_b <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_in(104 downto 52);
--rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,190)@4
rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_in <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_b;
rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_in(52 downto 21);
--reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1(REG,506)@4
reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q <= rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid192_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,191)@5
vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_a <= reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q;
vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5(REG,518)@5
reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q <= vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f(DELAY,886)@6
ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q, xout => ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid194_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,193)@4
vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_in <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_b(20 downto 0);
vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_in(20 downto 0);
--mO_uid193_leadingZeros_uid44_fpLogE1pxTest(CONSTANT,192)
mO_uid193_leadingZeros_uid44_fpLogE1pxTest_q <= "11111111111";
--cStage_uid195_leadingZeros_uid44_fpLogE1pxTest(BITJOIN,194)@4
cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_q <= vStage_uid194_leadingZeros_uid44_fpLogE1pxTest_b & mO_uid193_leadingZeros_uid44_fpLogE1pxTest_q;
--reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3(REG,508)@4
reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q <= cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest(MUX,196)@5
vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q, reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid191_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= reg_cStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,198)@5
rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in(31 downto 16);
--reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1(REG,509)@5
reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q <= rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid200_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,199)@6
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a <= reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q;
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4(REG,517)@6
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q <= vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e(DELAY,885)@7
ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q, xout => ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid201_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,200)@5
vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q(15 downto 0);
vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in(15 downto 0);
--reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3(REG,511)@5
reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest(MUX,202)@6
vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q, reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,204)@6
rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in(15 downto 8);
--vCount_uid206_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,205)@6
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_i <= "1" when vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b else "0";
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q, xin => vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d(DELAY,884)@7
ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q, xout => ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid207_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,206)@6
vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q(7 downto 0);
vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in(7 downto 0);
--reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3(REG,513)@6
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2(REG,512)@6
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest(MUX,208)@7
vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q, reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,210)@7
rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in(7 downto 4);
--vCount_uid212_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,211)@7
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2(REG,516)@7
reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q <= vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid213_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,212)@7
vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q(3 downto 0);
vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_in(3 downto 0);
--vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest(MUX,214)@7
vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s, en, rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b, vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b)
BEGIN
CASE vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b;
WHEN "1" => vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q <= vStage_uid213_leadingZeros_uid44_fpLogE1pxTest_b;
WHEN OTHERS => vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,216)@7
rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_in(3 downto 2);
--vCount_uid218_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,217)@7
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_b <= z2_uid100_fpLogE1pxTest_q;
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q_i <= "1" when vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_b else "0";
vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q, xin => vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid219_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,218)@7
vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid215_leadingZeros_uid44_fpLogE1pxTest_q(1 downto 0);
vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_in(1 downto 0);
--reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3(REG,515)@7
reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2(REG,514)@7
reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q <= rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest(MUX,220)@8
vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q, reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid217_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid219_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,222)@8
rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid221_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_in(1 downto 1);
--vCount_uid224_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,223)@8
vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid223_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_b <= GND_q;
vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--r_uid225_leadingZeros_uid44_fpLogE1pxTest(BITJOIN,224)@8
r_uid225_leadingZeros_uid44_fpLogE1pxTest_q <= ld_reg_vCount_uid192_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_5_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_f_q & ld_reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_4_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_e_q & ld_vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_d_q & reg_vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid225_leadingZeros_uid44_fpLogE1pxTest_2_q & vCount_uid218_leadingZeros_uid44_fpLogE1pxTest_q & vCount_uid224_leadingZeros_uid44_fpLogE1pxTest_q;
--leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,236)@8
leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid225_leadingZeros_uid44_fpLogE1pxTest_q;
leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_in(5 downto 4);
--leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,237)@8
leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= leftShiftStageSel5Dto4_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, redLO_uid47_fpLogE1pxTest_b, leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= redLO_uid47_fpLogE1pxTest_b;
WHEN "01" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx1_uid230_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx2_uid233_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx3_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,245)@8
LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q(92 downto 0);
LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_in(92 downto 0);
--rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,173)
rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q <= "000000000000";
--leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,246)@8
leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage092dto0_uid246_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx3Pad12_uid174_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5(REG,523)@8
reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q <= leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,242)@8
LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q(96 downto 0);
LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_in(96 downto 0);
--leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,243)@8
leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage096dto0_uid243_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4(REG,522)@8
reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q <= leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,239)@8
LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q(100 downto 0);
LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_in(100 downto 0);
--leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,240)@8
leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage0100dto0_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3(REG,521)@8
reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q <= leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2(REG,520)@8
reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,247)@8
leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid225_leadingZeros_uid44_fpLogE1pxTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1(REG,519)@8
reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,248)@9
leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= reg_leftShiftStageSel3Dto2_uid248_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q;
leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q, reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q, reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q, reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage0_uid238_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx1_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx2_uid244_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx3_uid247_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,256)@9
LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q(101 downto 0);
LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_in(101 downto 0);
--ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,916)@9
ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 102, depth => 1 )
PORT MAP ( xin => LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b, xout => ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,184)
rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q <= "000";
--leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,257)@10
leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= ld_LeftShiftStage1101dto0_uid257_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q & rightShiftStage2Idx3Pad3_uid185_fracXRSExt_uid36_fpLogE1pxTest_q;
--LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,253)@9
LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q(102 downto 0);
LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_in(102 downto 0);
--ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,914)@9
ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 103, depth => 1 )
PORT MAP ( xin => LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b, xout => ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,254)@10
leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= ld_LeftShiftStage1102dto0_uid254_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q & z2_uid100_fpLogE1pxTest_q;
--LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,250)@9
LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q(103 downto 0);
LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_in(103 downto 0);
--ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,912)@9
ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 104, depth => 1 )
PORT MAP ( xin => LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b, xout => ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,251)@10
leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= ld_LeftShiftStage1103dto0_uid251_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q & GND_q;
--reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2(REG,525)@9
reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,258)@8
leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid225_leadingZeros_uid44_fpLogE1pxTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1(REG,524)@8
reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,918)@9
ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q, xout => ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,259)@10
leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= ld_reg_leftShiftStageSel1Dto0_uid259_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q;
leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q, leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1_uid249_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage2Idx1_uid252_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage2Idx2_uid255_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage2Idx3_uid258_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracXBranch4_uid49_fpLogE1pxTest(BITSELECT,48)@10
fracXBranch4_uid49_fpLogE1pxTest_in <= leftShiftStage2_uid260_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
fracXBranch4_uid49_fpLogE1pxTest_b <= fracXBranch4_uid49_fpLogE1pxTest_in(104 downto 51);
--fracXBranch4Red_uid80_fpLogE1pxTest(BITSELECT,79)@10
fracXBranch4Red_uid80_fpLogE1pxTest_in <= fracXBranch4_uid49_fpLogE1pxTest_b(52 downto 0);
fracXBranch4Red_uid80_fpLogE1pxTest_b <= fracXBranch4Red_uid80_fpLogE1pxTest_in(52 downto 0);
--reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5(REG,528)@10
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q <= fracXBranch4Red_uid80_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor(LOGICAL,1409)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_b <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_q <= not (ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_a or ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_b);
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top(CONSTANT,1353)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top_q <= "0100";
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp(LOGICAL,1354)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_a <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_mem_top_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q);
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_q <= "1" when ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_a = ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_b else "0";
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg(REG,1355)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena(REG,1410)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_nor_q = "1") THEN
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd(LOGICAL,1411)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_a <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_sticky_ena_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_b <= en;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_q <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_a and ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_b;
--fracXRS_uid39_fpLogE1pxTest(BITSELECT,38)@3
fracXRS_uid39_fpLogE1pxTest_in <= rightShiftStage2_uid188_fracXRSExt_uid36_fpLogE1pxTest_q;
fracXRS_uid39_fpLogE1pxTest_b <= fracXRS_uid39_fpLogE1pxTest_in(105 downto 52);
--fracXRSRange_uid81_fpLogE1pxTest(BITSELECT,80)@3
fracXRSRange_uid81_fpLogE1pxTest_in <= fracXRS_uid39_fpLogE1pxTest_b(52 downto 0);
fracXRSRange_uid81_fpLogE1pxTest_b <= fracXRSRange_uid81_fpLogE1pxTest_in(52 downto 0);
--reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4(REG,527)@3
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q <= fracXRSRange_uid81_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg(DELAY,1399)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q, xout => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1349)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i = 3 THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i - 4;
ELSE
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_i,3));
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg(REG,1350)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux(MUX,1351)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s, ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q, ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem(DUALMEM,1400)
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ia <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_inputreg_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_aa <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ab <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 3,
numwords_a => 5,
width_b => 53,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_iq,
address_a => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_aa,
data_a => ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_ia
);
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_reset0 <= areset;
ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_iq(52 downto 0);
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor(LOGICAL,1396)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q <= not (ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a or ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b);
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena(REG,1397)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q = "1") THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd(LOGICAL,1398)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b <= en;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a and ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b;
--addrMaskExt_uid50_fpLogE1pxTest(SUB,49)@0
addrMaskExt_uid50_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpLogE1pxTest_b);
addrMaskExt_uid50_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
addrMaskExt_uid50_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(addrMaskExt_uid50_fpLogE1pxTest_a) - UNSIGNED(addrMaskExt_uid50_fpLogE1pxTest_b));
addrMaskExt_uid50_fpLogE1pxTest_q <= addrMaskExt_uid50_fpLogE1pxTest_o(11 downto 0);
--addrMask_uid51_fpLogE1pxTest(BITSELECT,50)@0
addrMask_uid51_fpLogE1pxTest_in <= addrMaskExt_uid50_fpLogE1pxTest_q(5 downto 0);
addrMask_uid51_fpLogE1pxTest_b <= addrMask_uid51_fpLogE1pxTest_in(5 downto 0);
--reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0(REG,494)@0
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q <= addrMask_uid51_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--maskIncrementTable_uid52_fpLogE1pxTest(LOOKUP,51)@1
maskIncrementTable_uid52_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
maskIncrementTable_uid52_fpLogE1pxTest_q <= "10000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q) IS
WHEN "000000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "10000000000000000000000000000000000000000000000000000";
WHEN "000001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "01000000000000000000000000000000000000000000000000000";
WHEN "000010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00100000000000000000000000000000000000000000000000000";
WHEN "000011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00010000000000000000000000000000000000000000000000000";
WHEN "000100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00001000000000000000000000000000000000000000000000000";
WHEN "000101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000100000000000000000000000000000000000000000000000";
WHEN "000110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000010000000000000000000000000000000000000000000000";
WHEN "000111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000001000000000000000000000000000000000000000000000";
WHEN "001000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000100000000000000000000000000000000000000000000";
WHEN "001001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000010000000000000000000000000000000000000000000";
WHEN "001010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000001000000000000000000000000000000000000000000";
WHEN "001011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000100000000000000000000000000000000000000000";
WHEN "001100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000010000000000000000000000000000000000000000";
WHEN "001101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000001000000000000000000000000000000000000000";
WHEN "001110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000100000000000000000000000000000000000000";
WHEN "001111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000010000000000000000000000000000000000000";
WHEN "010000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000001000000000000000000000000000000000000";
WHEN "010001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000100000000000000000000000000000000000";
WHEN "010010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000010000000000000000000000000000000000";
WHEN "010011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000001000000000000000000000000000000000";
WHEN "010100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000100000000000000000000000000000000";
WHEN "010101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000010000000000000000000000000000000";
WHEN "010110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000001000000000000000000000000000000";
WHEN "010111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000100000000000000000000000000000";
WHEN "011000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000010000000000000000000000000000";
WHEN "011001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000001000000000000000000000000000";
WHEN "011010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000100000000000000000000000000";
WHEN "011011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000010000000000000000000000000";
WHEN "011100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000001000000000000000000000000";
WHEN "011101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000100000000000000000000000";
WHEN "011110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000010000000000000000000000";
WHEN "011111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000001000000000000000000000";
WHEN "100000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000100000000000000000000";
WHEN "100001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000010000000000000000000";
WHEN "100010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000001000000000000000000";
WHEN "100011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000100000000000000000";
WHEN "100100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000010000000000000000";
WHEN "100101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000001000000000000000";
WHEN "100110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000100000000000000";
WHEN "100111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000010000000000000";
WHEN "101000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000001000000000000";
WHEN "101001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000100000000000";
WHEN "101010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000010000000000";
WHEN "101011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000001000000000";
WHEN "101100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000100000000";
WHEN "101101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000010000000";
WHEN "101110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000001000000";
WHEN "101111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000100000";
WHEN "110000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000010000";
WHEN "110001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000001000";
WHEN "110010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000100";
WHEN "110011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000010";
WHEN "110100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "00000000000000000000000000000000000000000000000000001";
WHEN OTHERS =>
maskIncrementTable_uid52_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0(REG,495)@1
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q <= oFracX_uid32_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--oPlusOFracX_uid53_fpLogE1pxTest(ADD,52)@2
oPlusOFracX_uid53_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q);
oPlusOFracX_uid53_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & maskIncrementTable_uid52_fpLogE1pxTest_q);
oPlusOFracX_uid53_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oPlusOFracX_uid53_fpLogE1pxTest_a) + UNSIGNED(oPlusOFracX_uid53_fpLogE1pxTest_b));
oPlusOFracX_uid53_fpLogE1pxTest_q <= oPlusOFracX_uid53_fpLogE1pxTest_o(53 downto 0);
--oPlusOFracXNormHigh_uid59_fpLogE1pxTest(BITSELECT,58)@2
oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q(52 downto 0);
oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b <= oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in(52 downto 0);
--reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3(REG,498)@2
reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q <= oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--oPlusOFracXNormLow_uid57_fpLogE1pxTest(BITSELECT,56)@2
oPlusOFracXNormLow_uid57_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q(51 downto 0);
oPlusOFracXNormLow_uid57_fpLogE1pxTest_b <= oPlusOFracXNormLow_uid57_fpLogE1pxTest_in(51 downto 0);
--join_uid58_fpLogE1pxTest(BITJOIN,57)@2
join_uid58_fpLogE1pxTest_q <= oPlusOFracXNormLow_uid57_fpLogE1pxTest_b & GND_q;
--reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2(REG,497)@2
reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q <= join_uid58_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--msbUoPlusOFracX_uid54_fpLogE1pxTest(BITSELECT,53)@2
msbUoPlusOFracX_uid54_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q;
msbUoPlusOFracX_uid54_fpLogE1pxTest_b <= msbUoPlusOFracX_uid54_fpLogE1pxTest_in(53 downto 53);
--reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1(REG,496)@2
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q <= msbUoPlusOFracX_uid54_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--oPlusOFracXNorm_uid61_fpLogE1pxTest(MUX,60)@3
oPlusOFracXNorm_uid61_fpLogE1pxTest_s <= reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q;
oPlusOFracXNorm_uid61_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE oPlusOFracXNorm_uid61_fpLogE1pxTest_s IS
WHEN "0" => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= reg_join_uid58_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_2_q;
WHEN "1" => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= reg_oPlusOFracXNormHigh_uid59_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_3_q;
WHEN OTHERS => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg(DELAY,1386)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => oPlusOFracXNorm_uid61_fpLogE1pxTest_q, xout => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem(DUALMEM,1387)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 3,
numwords_a => 5,
width_b => 53,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia
);
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq(52 downto 0);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor(LOGICAL,1383)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top(CONSTANT,1379)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top_q <= "0110";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp(LOGICAL,1380)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q);
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg(REG,1381)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena(REG,1384)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd(LOGICAL,1385)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg(DELAY,1373)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => frac_uid22_fpLogE1pxTest_b, xout => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1375)
-- every=1, low=0, high=6, step=1, init=1
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i = 5 THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i - 6;
ELSE
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_i,3));
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg(REG,1376)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux(MUX,1377)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s, ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q, ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem(DUALMEM,1374)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 3,
numwords_a => 7,
width_b => 52,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq(51 downto 0);
--fracXz_uid82_fpLogE1pxTest(BITJOIN,81)@10
fracXz_uid82_fpLogE1pxTest_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q & GND_q;
--reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2(REG,526)@10
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q <= fracXz_uid82_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor(LOGICAL,1357)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_b <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_q <= not (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_a or ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_b);
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena(REG,1358)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_nor_q = "1") THEN
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd(LOGICAL,1359)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_a <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_sticky_ena_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_b <= en;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_a and ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_b;
--branch11_uid64_fpLogE1pxTest(LOGICAL,63)@0
branch11_uid64_fpLogE1pxTest_a <= signX_uid7_fpLogE1pxTest_b;
branch11_uid64_fpLogE1pxTest_q <= not branch11_uid64_fpLogE1pxTest_a;
--branch3_uid73_fpLogE1pxTest(LOGICAL,72)@0
branch3_uid73_fpLogE1pxTest_a <= branch22_uid66_fpLogE1pxTest_c;
branch3_uid73_fpLogE1pxTest_b <= InvResIsX_uid72_fpLogE1pxTest_q;
branch3_uid73_fpLogE1pxTest_c <= branch11_uid64_fpLogE1pxTest_q;
branch3_uid73_fpLogE1pxTest_q <= branch3_uid73_fpLogE1pxTest_a and branch3_uid73_fpLogE1pxTest_b and branch3_uid73_fpLogE1pxTest_c;
--cstBiasPWFP1_uid13_fpLogE1pxTest(CONSTANT,12)
cstBiasPWFP1_uid13_fpLogE1pxTest_q <= "10000110100";
--branch12_uid63_fpLogE1pxTest(COMPARE,62)@0
branch12_uid63_fpLogE1pxTest_cin <= GND_q;
branch12_uid63_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
branch12_uid63_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasPWFP1_uid13_fpLogE1pxTest_q) & branch12_uid63_fpLogE1pxTest_cin(0);
branch12_uid63_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch12_uid63_fpLogE1pxTest_a) - UNSIGNED(branch12_uid63_fpLogE1pxTest_b));
branch12_uid63_fpLogE1pxTest_c(0) <= branch12_uid63_fpLogE1pxTest_o(13);
branch12_uid63_fpLogE1pxTest_n(0) <= not branch12_uid63_fpLogE1pxTest_o(13);
--branch2_uid69_fpLogE1pxTest(LOGICAL,68)@0
branch2_uid69_fpLogE1pxTest_a <= branch11_uid64_fpLogE1pxTest_q;
branch2_uid69_fpLogE1pxTest_b <= branch12_uid63_fpLogE1pxTest_c;
branch2_uid69_fpLogE1pxTest_c <= branch22_uid66_fpLogE1pxTest_n;
branch2_uid69_fpLogE1pxTest_q <= branch2_uid69_fpLogE1pxTest_a and branch2_uid69_fpLogE1pxTest_b and branch2_uid69_fpLogE1pxTest_c;
--branch1_uid65_fpLogE1pxTest(LOGICAL,64)@0
branch1_uid65_fpLogE1pxTest_a <= branch11_uid64_fpLogE1pxTest_q;
branch1_uid65_fpLogE1pxTest_b <= branch12_uid63_fpLogE1pxTest_n;
branch1_uid65_fpLogE1pxTest_q <= branch1_uid65_fpLogE1pxTest_a and branch1_uid65_fpLogE1pxTest_b;
--concBranch_uid76_fpLogE1pxTest(BITJOIN,75)@0
concBranch_uid76_fpLogE1pxTest_q <= branch4_uid75_fpLogE1pxTest_q & branch3_uid73_fpLogE1pxTest_q & branch2_uid69_fpLogE1pxTest_q & branch1_uid65_fpLogE1pxTest_q;
--reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0(REG,493)@0
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q <= concBranch_uid76_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg(DELAY,1347)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 4, depth => 1 )
PORT MAP ( xin => reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q, xout => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem(DUALMEM,1348)
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ia <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_inputreg_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_aa <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ab <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 4,
widthad_a => 3,
numwords_a => 5,
width_b => 4,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_ia
);
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_q <= ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_iq(3 downto 0);
--branEnc_uid77_fpLogE1pxTest(LOOKUP,76)@8
branEnc_uid77_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
branEnc_uid77_fpLogE1pxTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_replace_mem_q) IS
WHEN "0000" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0001" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0010" => branEnc_uid77_fpLogE1pxTest_q <= "01";
WHEN "0011" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0100" => branEnc_uid77_fpLogE1pxTest_q <= "10";
WHEN "0101" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0110" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0111" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1000" => branEnc_uid77_fpLogE1pxTest_q <= "11";
WHEN "1001" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1010" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1011" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1100" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1101" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1110" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1111" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN OTHERS =>
branEnc_uid77_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b(DELAY,725)@9
ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 2 )
PORT MAP ( xin => branEnc_uid77_fpLogE1pxTest_q, xout => ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracB_uid83_fpLogE1pxTest(MUX,82)@11
fracB_uid83_fpLogE1pxTest_s <= ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q;
fracB_uid83_fpLogE1pxTest: PROCESS (fracB_uid83_fpLogE1pxTest_s, en, reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q, ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q, ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q, reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q)
BEGIN
CASE fracB_uid83_fpLogE1pxTest_s IS
WHEN "00" => fracB_uid83_fpLogE1pxTest_q <= reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q;
WHEN "01" => fracB_uid83_fpLogE1pxTest_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q;
WHEN "10" => fracB_uid83_fpLogE1pxTest_q <= ld_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q_to_fracB_uid83_fpLogE1pxTest_e_replace_mem_q;
WHEN "11" => fracB_uid83_fpLogE1pxTest_q <= reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q;
WHEN OTHERS => fracB_uid83_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg(DELAY,1425)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => fracB_uid83_fpLogE1pxTest_q, xout => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1338)
-- every=1, low=0, high=1, step=1, init=1
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_i,1));
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg(REG,1339)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux(MUX,1340)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s, ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q, ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem(DUALMEM,1426)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ia <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 53,
widthad_a => 1,
numwords_a => 2,
width_b => 53,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_ia
);
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_q <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_iq(52 downto 0);
--zPPolyEval_uid91_fpLogE1pxTest(BITSELECT,90)@15
zPPolyEval_uid91_fpLogE1pxTest_in <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_replace_mem_q(42 downto 0);
zPPolyEval_uid91_fpLogE1pxTest_b <= zPPolyEval_uid91_fpLogE1pxTest_in(42 downto 0);
--yT2_uid300_natLogPolyEval(BITSELECT,299)@15
yT2_uid300_natLogPolyEval_in <= zPPolyEval_uid91_fpLogE1pxTest_b;
yT2_uid300_natLogPolyEval_b <= yT2_uid300_natLogPolyEval_in(42 downto 15);
--sSM1W_uid412_pT2_uid301_natLogPolyEval(BITSELECT,411)@15
sSM1W_uid412_pT2_uid301_natLogPolyEval_in <= yT2_uid300_natLogPolyEval_b(0 downto 0);
sSM1W_uid412_pT2_uid301_natLogPolyEval_b <= sSM1W_uid412_pT2_uid301_natLogPolyEval_in(0 downto 0);
--reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1(REG,577)@15
reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q <= sSM1W_uid412_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b(DELAY,1072)@16
ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q, xout => ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--zAddrLow_uid89_fpLogE1pxTest(BITSELECT,88)@11
zAddrLow_uid89_fpLogE1pxTest_in <= fracB_uid83_fpLogE1pxTest_q;
zAddrLow_uid89_fpLogE1pxTest_b <= zAddrLow_uid89_fpLogE1pxTest_in(52 downto 43);
--addr_uid90_fpLogE1pxTest(BITJOIN,89)@11
addr_uid90_fpLogE1pxTest_q <= reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q & zAddrLow_uid89_fpLogE1pxTest_b;
--reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0(REG,530)@11
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q <= addr_uid90_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid292_natLogTabGen_lutmem(DUALMEM,488)@12
memoryC4_uid292_natLogTabGen_lutmem_ia <= (others => '0');
memoryC4_uid292_natLogTabGen_lutmem_aa <= (others => '0');
memoryC4_uid292_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC4_uid292_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 11,
numwords_a => 2048,
width_b => 7,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC4_uid292_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC4_uid292_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC4_uid292_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC4_uid292_natLogTabGen_lutmem_iq,
address_a => memoryC4_uid292_natLogTabGen_lutmem_aa,
data_a => memoryC4_uid292_natLogTabGen_lutmem_ia
);
memoryC4_uid292_natLogTabGen_lutmem_reset0 <= areset;
memoryC4_uid292_natLogTabGen_lutmem_q <= memoryC4_uid292_natLogTabGen_lutmem_iq(6 downto 0);
--reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1(REG,563)@14
reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q <= memoryC4_uid292_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid291_natLogTabGen_lutmem(DUALMEM,487)@12
memoryC4_uid291_natLogTabGen_lutmem_ia <= (others => '0');
memoryC4_uid291_natLogTabGen_lutmem_aa <= (others => '0');
memoryC4_uid291_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC4_uid291_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC4_uid291_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC4_uid291_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC4_uid291_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC4_uid291_natLogTabGen_lutmem_iq,
address_a => memoryC4_uid291_natLogTabGen_lutmem_aa,
data_a => memoryC4_uid291_natLogTabGen_lutmem_ia
);
memoryC4_uid291_natLogTabGen_lutmem_reset0 <= areset;
memoryC4_uid291_natLogTabGen_lutmem_q <= memoryC4_uid291_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0(REG,562)@14
reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q <= memoryC4_uid291_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid293_natLogTabGen(BITJOIN,292)@15
os_uid293_natLogTabGen_q <= reg_memoryC4_uid292_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_1_q & reg_memoryC4_uid291_natLogTabGen_lutmem_0_to_os_uid293_natLogTabGen_0_q;
--reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1(REG,565)@15
reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q <= os_uid293_natLogTabGen_q;
END IF;
END IF;
END PROCESS;
--yT1_uid294_natLogPolyEval(BITSELECT,293)@15
yT1_uid294_natLogPolyEval_in <= zPPolyEval_uid91_fpLogE1pxTest_b;
yT1_uid294_natLogPolyEval_b <= yT1_uid294_natLogPolyEval_in(42 downto 26);
--reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0(REG,564)@15
reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q <= yT1_uid294_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid402_pT1_uid295_natLogPolyEval(MULT,401)@16
prodXY_uid402_pT1_uid295_natLogPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid402_pT1_uid295_natLogPolyEval_a),18)) * SIGNED(prodXY_uid402_pT1_uid295_natLogPolyEval_b);
prodXY_uid402_pT1_uid295_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_a <= (others => '0');
prodXY_uid402_pT1_uid295_natLogPolyEval_b <= (others => '0');
prodXY_uid402_pT1_uid295_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_a <= reg_yT1_uid294_natLogPolyEval_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_0_q;
prodXY_uid402_pT1_uid295_natLogPolyEval_b <= reg_os_uid293_natLogTabGen_0_to_prodXY_uid402_pT1_uid295_natLogPolyEval_1_q;
prodXY_uid402_pT1_uid295_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid402_pT1_uid295_natLogPolyEval_pr,34));
END IF;
END IF;
END PROCESS;
prodXY_uid402_pT1_uid295_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid402_pT1_uid295_natLogPolyEval_q <= prodXY_uid402_pT1_uid295_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval(BITSELECT,402)@19
prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_in <= prodXY_uid402_pT1_uid295_natLogPolyEval_q;
prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b <= prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_in(33 downto 15);
--highBBits_uid297_natLogPolyEval(BITSELECT,296)@19
highBBits_uid297_natLogPolyEval_in <= prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b;
highBBits_uid297_natLogPolyEval_b <= highBBits_uid297_natLogPolyEval_in(18 downto 1);
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor(LOGICAL,1583)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_b <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_q <= not (ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_a or ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_b);
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena(REG,1584)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_nor_q = "1") THEN
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd(LOGICAL,1585)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_a <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_sticky_ena_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_b <= en;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_q <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_a and ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_b;
--memoryC3_uid289_natLogTabGen_lutmem(DUALMEM,486)@12
memoryC3_uid289_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid289_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid289_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC3_uid289_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC3_uid289_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid289_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid289_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid289_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid289_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid289_natLogTabGen_lutmem_ia
);
memoryC3_uid289_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid289_natLogTabGen_lutmem_q <= memoryC3_uid289_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2(REG,571)@14
reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q <= memoryC3_uid289_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid288_natLogTabGen_lutmem(DUALMEM,485)@12
memoryC3_uid288_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid288_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid288_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC3_uid288_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC3_uid288_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid288_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid288_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid288_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid288_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid288_natLogTabGen_lutmem_ia
);
memoryC3_uid288_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid288_natLogTabGen_lutmem_q <= memoryC3_uid288_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1(REG,570)@14
reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q <= memoryC3_uid288_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid287_natLogTabGen_lutmem(DUALMEM,484)@12
memoryC3_uid287_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid287_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid287_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC3_uid287_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC3_uid287_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid287_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid287_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid287_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid287_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid287_natLogTabGen_lutmem_ia
);
memoryC3_uid287_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid287_natLogTabGen_lutmem_q <= memoryC3_uid287_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0(REG,569)@14
reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q <= memoryC3_uid287_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid290_natLogTabGen(BITJOIN,289)@15
os_uid290_natLogTabGen_q <= reg_memoryC3_uid289_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_2_q & reg_memoryC3_uid288_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_1_q & reg_memoryC3_uid287_natLogTabGen_lutmem_0_to_os_uid290_natLogTabGen_0_q;
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg(DELAY,1575)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 28, depth => 1 )
PORT MAP ( xin => os_uid290_natLogTabGen_q, xout => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem(DUALMEM,1576)
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ia <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_inputreg_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 28,
widthad_a => 1,
numwords_a => 2,
width_b => 28,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_iq,
address_a => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_aa,
data_a => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_ia
);
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q <= ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_iq(27 downto 0);
--sumAHighB_uid298_natLogPolyEval(ADD,297)@19
sumAHighB_uid298_natLogPolyEval_a <= STD_LOGIC_VECTOR((28 downto 28 => ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q(27)) & ld_os_uid290_natLogTabGen_q_to_sumAHighB_uid298_natLogPolyEval_a_replace_mem_q);
sumAHighB_uid298_natLogPolyEval_b <= STD_LOGIC_VECTOR((28 downto 18 => highBBits_uid297_natLogPolyEval_b(17)) & highBBits_uid297_natLogPolyEval_b);
sumAHighB_uid298_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid298_natLogPolyEval_a) + SIGNED(sumAHighB_uid298_natLogPolyEval_b));
sumAHighB_uid298_natLogPolyEval_q <= sumAHighB_uid298_natLogPolyEval_o(28 downto 0);
--lowRangeB_uid296_natLogPolyEval(BITSELECT,295)@19
lowRangeB_uid296_natLogPolyEval_in <= prodXYTruncFR_uid403_pT1_uid295_natLogPolyEval_b(0 downto 0);
lowRangeB_uid296_natLogPolyEval_b <= lowRangeB_uid296_natLogPolyEval_in(0 downto 0);
--s1_uid296_uid299_natLogPolyEval(BITJOIN,298)@19
s1_uid296_uid299_natLogPolyEval_q <= sumAHighB_uid298_natLogPolyEval_q & lowRangeB_uid296_natLogPolyEval_b;
--sSM1H_uid411_pT2_uid301_natLogPolyEval(BITSELECT,410)@19
sSM1H_uid411_pT2_uid301_natLogPolyEval_in <= s1_uid296_uid299_natLogPolyEval_q;
sSM1H_uid411_pT2_uid301_natLogPolyEval_b <= sSM1H_uid411_pT2_uid301_natLogPolyEval_in(29 downto 24);
--reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0(REG,576)@19
reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q <= sSM1H_uid411_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--sm1_uid413_pT2_uid301_natLogPolyEval(MULT,412)@20
sm1_uid413_pT2_uid301_natLogPolyEval_pr <= SIGNED(sm1_uid413_pT2_uid301_natLogPolyEval_a) * signed(resize(UNSIGNED(sm1_uid413_pT2_uid301_natLogPolyEval_b),2));
sm1_uid413_pT2_uid301_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm1_uid413_pT2_uid301_natLogPolyEval_a <= (others => '0');
sm1_uid413_pT2_uid301_natLogPolyEval_b <= (others => '0');
sm1_uid413_pT2_uid301_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm1_uid413_pT2_uid301_natLogPolyEval_a <= reg_sSM1H_uid411_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_0_q;
sm1_uid413_pT2_uid301_natLogPolyEval_b <= ld_reg_sSM1W_uid412_pT2_uid301_natLogPolyEval_0_to_sm1_uid413_pT2_uid301_natLogPolyEval_1_q_to_sm1_uid413_pT2_uid301_natLogPolyEval_b_q;
sm1_uid413_pT2_uid301_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(sm1_uid413_pT2_uid301_natLogPolyEval_pr,7));
END IF;
END IF;
END PROCESS;
sm1_uid413_pT2_uid301_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm1_uid413_pT2_uid301_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm1_uid413_pT2_uid301_natLogPolyEval_q <= sm1_uid413_pT2_uid301_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval(BITJOIN,414)@23
pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q <= sm1_uid413_pT2_uid301_natLogPolyEval_q & STD_LOGIC_VECTOR((19 downto 1 => GND_q(0)) & GND_q);
--sSM0W_uid409_pT2_uid301_natLogPolyEval(BITSELECT,408)@15
sSM0W_uid409_pT2_uid301_natLogPolyEval_in <= yT2_uid300_natLogPolyEval_b;
sSM0W_uid409_pT2_uid301_natLogPolyEval_b <= sSM0W_uid409_pT2_uid301_natLogPolyEval_in(27 downto 24);
--ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a(DELAY,1258)@15
ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a : dspba_delay
GENERIC MAP ( width => 4, depth => 4 )
PORT MAP ( xin => sSM0W_uid409_pT2_uid301_natLogPolyEval_b, xout => ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1(REG,575)@19
reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q <= ld_sSM0W_uid409_pT2_uid301_natLogPolyEval_b_to_reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_a_q;
END IF;
END IF;
END PROCESS;
--sSM0H_uid408_pT2_uid301_natLogPolyEval(BITSELECT,407)@19
sSM0H_uid408_pT2_uid301_natLogPolyEval_in <= s1_uid296_uid299_natLogPolyEval_q(2 downto 0);
sSM0H_uid408_pT2_uid301_natLogPolyEval_b <= sSM0H_uid408_pT2_uid301_natLogPolyEval_in(2 downto 0);
--reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0(REG,574)@19
reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q <= sSM0H_uid408_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid410_pT2_uid301_natLogPolyEval(MULT,409)@20
sm0_uid410_pT2_uid301_natLogPolyEval_pr <= UNSIGNED(sm0_uid410_pT2_uid301_natLogPolyEval_a) * UNSIGNED(sm0_uid410_pT2_uid301_natLogPolyEval_b);
sm0_uid410_pT2_uid301_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid410_pT2_uid301_natLogPolyEval_a <= (others => '0');
sm0_uid410_pT2_uid301_natLogPolyEval_b <= (others => '0');
sm0_uid410_pT2_uid301_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid410_pT2_uid301_natLogPolyEval_a <= reg_sSM0H_uid408_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_0_q;
sm0_uid410_pT2_uid301_natLogPolyEval_b <= reg_sSM0W_uid409_pT2_uid301_natLogPolyEval_0_to_sm0_uid410_pT2_uid301_natLogPolyEval_1_q;
sm0_uid410_pT2_uid301_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid410_pT2_uid301_natLogPolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid410_pT2_uid301_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid410_pT2_uid301_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid410_pT2_uid301_natLogPolyEval_q <= sm0_uid410_pT2_uid301_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval(BITJOIN,413)@23
pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval_q <= sm0_uid410_pT2_uid301_natLogPolyEval_q & STD_LOGIC_VECTOR((19 downto 1 => GND_q(0)) & GND_q);
--yTop27Bits_uid406_pT2_uid301_natLogPolyEval(BITSELECT,405)@19
yTop27Bits_uid406_pT2_uid301_natLogPolyEval_in <= s1_uid296_uid299_natLogPolyEval_q;
yTop27Bits_uid406_pT2_uid301_natLogPolyEval_b <= yTop27Bits_uid406_pT2_uid301_natLogPolyEval_in(29 downto 3);
--reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1(REG,573)@19
reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q <= yTop27Bits_uid406_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor(LOGICAL,1716)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_b <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_q <= not (ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_a or ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_b);
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena(REG,1717)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_nor_q = "1") THEN
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd(LOGICAL,1718)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_a <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_sticky_ena_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_b <= en;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_q <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_a and ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_b;
--xTop27Bits_uid405_pT2_uid301_natLogPolyEval(BITSELECT,404)@15
xTop27Bits_uid405_pT2_uid301_natLogPolyEval_in <= yT2_uid300_natLogPolyEval_b;
xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b <= xTop27Bits_uid405_pT2_uid301_natLogPolyEval_in(27 downto 1);
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg(DELAY,1708)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b, xout => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem(DUALMEM,1709)
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ia <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_inputreg_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 27,
widthad_a => 1,
numwords_a => 2,
width_b => 27,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_iq,
address_a => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_aa,
data_a => ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_ia
);
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_reset0 <= areset;
ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_q <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_iq(26 downto 0);
--reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0(REG,572)@19
reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q <= ld_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_b_to_reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--topProd_uid407_pT2_uid301_natLogPolyEval(MULT,406)@20
topProd_uid407_pT2_uid301_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid407_pT2_uid301_natLogPolyEval_a),28)) * SIGNED(topProd_uid407_pT2_uid301_natLogPolyEval_b);
topProd_uid407_pT2_uid301_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid407_pT2_uid301_natLogPolyEval_a <= (others => '0');
topProd_uid407_pT2_uid301_natLogPolyEval_b <= (others => '0');
topProd_uid407_pT2_uid301_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid407_pT2_uid301_natLogPolyEval_a <= reg_xTop27Bits_uid405_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_0_q;
topProd_uid407_pT2_uid301_natLogPolyEval_b <= reg_yTop27Bits_uid406_pT2_uid301_natLogPolyEval_0_to_topProd_uid407_pT2_uid301_natLogPolyEval_1_q;
topProd_uid407_pT2_uid301_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid407_pT2_uid301_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid407_pT2_uid301_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid407_pT2_uid301_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid407_pT2_uid301_natLogPolyEval_q <= topProd_uid407_pT2_uid301_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--add0_uid414_pT2_uid301_natLogPolyEval(ADDSUB3,415)@23
add0_uid414_pT2_uid301_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid407_pT2_uid301_natLogPolyEval_q(53)) & topProd_uid407_pT2_uid301_natLogPolyEval_q);
add0_uid414_pT2_uid301_natLogPolyEval_b <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000" & pad_sm0_uid410_uid414_pT2_uid301_natLogPolyEval_q);
add0_uid414_pT2_uid301_natLogPolyEval_c <= STD_LOGIC_VECTOR((54 downto 27 => pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q(26)) & pad_sm1_uid413_uid415_pT2_uid301_natLogPolyEval_q);
add0_uid414_pT2_uid301_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(add0_uid414_pT2_uid301_natLogPolyEval_a) + SIGNED(add0_uid414_pT2_uid301_natLogPolyEval_b) + SIGNED(add0_uid414_pT2_uid301_natLogPolyEval_c));
add0_uid414_pT2_uid301_natLogPolyEval_q <= add0_uid414_pT2_uid301_natLogPolyEval_o(54 downto 0);
--R_uid417_pT2_uid301_natLogPolyEval(BITSELECT,416)@23
R_uid417_pT2_uid301_natLogPolyEval_in <= add0_uid414_pT2_uid301_natLogPolyEval_q(53 downto 0);
R_uid417_pT2_uid301_natLogPolyEval_b <= R_uid417_pT2_uid301_natLogPolyEval_in(53 downto 24);
--reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1(REG,579)@23
reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q <= R_uid417_pT2_uid301_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor(LOGICAL,1596)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_b <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_q <= not (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_a or ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_b);
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top(CONSTANT,1592)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top_q <= "0101";
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp(LOGICAL,1593)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_a <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_mem_top_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_a = ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg(REG,1594)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena(REG,1597)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd(LOGICAL,1598)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_a <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_sticky_ena_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_a and ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_b;
--memoryC2_uid285_natLogTabGen_lutmem(DUALMEM,483)@12
memoryC2_uid285_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid285_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid285_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid285_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid285_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid285_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid285_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid285_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid285_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid285_natLogTabGen_lutmem_ia
);
memoryC2_uid285_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid285_natLogTabGen_lutmem_q <= memoryC2_uid285_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3(REG,559)@14
reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q <= memoryC2_uid285_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid284_natLogTabGen_lutmem(DUALMEM,482)@12
memoryC2_uid284_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid284_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid284_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid284_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid284_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid284_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid284_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid284_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid284_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid284_natLogTabGen_lutmem_ia
);
memoryC2_uid284_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid284_natLogTabGen_lutmem_q <= memoryC2_uid284_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2(REG,558)@14
reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q <= memoryC2_uid284_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid283_natLogTabGen_lutmem(DUALMEM,481)@12
memoryC2_uid283_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid283_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid283_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid283_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid283_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid283_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid283_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid283_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid283_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid283_natLogTabGen_lutmem_ia
);
memoryC2_uid283_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid283_natLogTabGen_lutmem_q <= memoryC2_uid283_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1(REG,557)@14
reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q <= memoryC2_uid283_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid282_natLogTabGen_lutmem(DUALMEM,480)@12
memoryC2_uid282_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid282_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid282_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC2_uid282_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC2_uid282_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid282_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid282_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid282_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid282_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid282_natLogTabGen_lutmem_ia
);
memoryC2_uid282_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid282_natLogTabGen_lutmem_q <= memoryC2_uid282_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0(REG,556)@14
reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q <= memoryC2_uid282_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid286_natLogTabGen(BITJOIN,285)@15
os_uid286_natLogTabGen_q <= reg_memoryC2_uid285_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_3_q & reg_memoryC2_uid284_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_2_q & reg_memoryC2_uid283_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_1_q & reg_memoryC2_uid282_natLogTabGen_lutmem_0_to_os_uid286_natLogTabGen_0_q;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg(DELAY,1586)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 38, depth => 1 )
PORT MAP ( xin => os_uid286_natLogTabGen_q, xout => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt(COUNTER,1588)
-- every=1, low=0, high=5, step=1, init=1
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i = 4 THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i - 5;
ELSE
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_i,3));
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg(REG,1589)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux(MUX,1590)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s, ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q, ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem(DUALMEM,1587)
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ia <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_inputreg_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_aa <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ab <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 38,
widthad_a => 3,
numwords_a => 6,
width_b => 38,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_iq(37 downto 0);
--o2_uid97_fpLogE1pxTest(CONSTANT,96)
o2_uid97_fpLogE1pxTest_q <= "01";
--cIncludingRoundingBit_uid303_natLogPolyEval(BITJOIN,302)@23
cIncludingRoundingBit_uid303_natLogPolyEval_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_mem_q & o2_uid97_fpLogE1pxTest_q;
--reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0(REG,578)@23
reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q <= cIncludingRoundingBit_uid303_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts2_uid304_natLogPolyEval(ADD,303)@24
ts2_uid304_natLogPolyEval_a <= STD_LOGIC_VECTOR((40 downto 40 => reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q(39)) & reg_cIncludingRoundingBit_uid303_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_0_q);
ts2_uid304_natLogPolyEval_b <= STD_LOGIC_VECTOR((40 downto 30 => reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q(29)) & reg_R_uid417_pT2_uid301_natLogPolyEval_0_to_ts2_uid304_natLogPolyEval_1_q);
ts2_uid304_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts2_uid304_natLogPolyEval_a) + SIGNED(ts2_uid304_natLogPolyEval_b));
ts2_uid304_natLogPolyEval_q <= ts2_uid304_natLogPolyEval_o(40 downto 0);
--s2_uid305_natLogPolyEval(BITSELECT,304)@24
s2_uid305_natLogPolyEval_in <= ts2_uid304_natLogPolyEval_q;
s2_uid305_natLogPolyEval_b <= s2_uid305_natLogPolyEval_in(40 downto 1);
--yTop18Bits_uid424_pT3_uid307_natLogPolyEval(BITSELECT,423)@24
yTop18Bits_uid424_pT3_uid307_natLogPolyEval_in <= s2_uid305_natLogPolyEval_b;
yTop18Bits_uid424_pT3_uid307_natLogPolyEval_b <= yTop18Bits_uid424_pT3_uid307_natLogPolyEval_in(39 downto 22);
--reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9(REG,583)@24
reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q <= yTop18Bits_uid424_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor(LOGICAL,1609)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_b <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_q <= not (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_a or ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_b);
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena(REG,1610)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd(LOGICAL,1611)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_b <= en;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_a and ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg(DELAY,1599)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 43, depth => 1 )
PORT MAP ( xin => zPPolyEval_uid91_fpLogE1pxTest_b, xout => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem(DUALMEM,1600)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ia <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_aa <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ab <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_rdmux_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 43,
widthad_a => 3,
numwords_a => 7,
width_b => 43,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_iq(42 downto 0);
--yT3_uid306_natLogPolyEval(BITSELECT,305)@24
yT3_uid306_natLogPolyEval_in <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_replace_mem_q;
yT3_uid306_natLogPolyEval_b <= yT3_uid306_natLogPolyEval_in(42 downto 5);
--xBottomBits_uid423_pT3_uid307_natLogPolyEval(BITSELECT,422)@24
xBottomBits_uid423_pT3_uid307_natLogPolyEval_in <= yT3_uid306_natLogPolyEval_b(10 downto 0);
xBottomBits_uid423_pT3_uid307_natLogPolyEval_b <= xBottomBits_uid423_pT3_uid307_natLogPolyEval_in(10 downto 0);
--pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval(BITJOIN,425)@24
pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_q <= xBottomBits_uid423_pT3_uid307_natLogPolyEval_b & STD_LOGIC_VECTOR((5 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7(REG,582)@24
reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q <= pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid422_pT3_uid307_natLogPolyEval(BITSELECT,421)@24
yBottomBits_uid422_pT3_uid307_natLogPolyEval_in <= s2_uid305_natLogPolyEval_b(12 downto 0);
yBottomBits_uid422_pT3_uid307_natLogPolyEval_b <= yBottomBits_uid422_pT3_uid307_natLogPolyEval_in(12 downto 0);
--spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval(BITJOIN,424)@24
spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval_q <= GND_q & yBottomBits_uid422_pT3_uid307_natLogPolyEval_b;
--pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval(BITJOIN,426)@24
pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_q <= spad_yBottomBits_uid422_uid425_pT3_uid307_natLogPolyEval_q & STD_LOGIC_VECTOR((3 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6(REG,581)@24
reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q <= pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--xTop18Bits_uid421_pT3_uid307_natLogPolyEval(BITSELECT,420)@24
xTop18Bits_uid421_pT3_uid307_natLogPolyEval_in <= yT3_uid306_natLogPolyEval_b;
xTop18Bits_uid421_pT3_uid307_natLogPolyEval_b <= xTop18Bits_uid421_pT3_uid307_natLogPolyEval_in(37 downto 20);
--reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4(REG,580)@24
reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q <= xTop18Bits_uid421_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma(CHAINMULTADD,489)@25
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(0),19));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(1),19));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(0) * multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(0);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(1) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_l(1) * multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(1);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_p(1),38);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_w(0);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_x(0);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid421_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_4_q),18);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid423_uid426_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_7_q),18);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid422_uid427_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_6_q),18);
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid424_pT3_uid307_natLogPolyEval_0_to_multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_9_q),18);
IF (en = "1") THEN
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s(0) <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_y(0);
END IF;
END IF;
END PROCESS;
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 37, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval(BITSELECT,428)@28
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_in <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_cma_q;
multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_in(36 downto 4);
--highBBits_uid431_pT3_uid307_natLogPolyEval(BITSELECT,430)@28
highBBits_uid431_pT3_uid307_natLogPolyEval_in <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b;
highBBits_uid431_pT3_uid307_natLogPolyEval_b <= highBBits_uid431_pT3_uid307_natLogPolyEval_in(32 downto 4);
--yTop27Bits_uid419_pT3_uid307_natLogPolyEval(BITSELECT,418)@24
yTop27Bits_uid419_pT3_uid307_natLogPolyEval_in <= s2_uid305_natLogPolyEval_b;
yTop27Bits_uid419_pT3_uid307_natLogPolyEval_b <= yTop27Bits_uid419_pT3_uid307_natLogPolyEval_in(39 downto 13);
--reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1(REG,585)@24
reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q <= yTop27Bits_uid419_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--xTop27Bits_uid418_pT3_uid307_natLogPolyEval(BITSELECT,417)@24
xTop27Bits_uid418_pT3_uid307_natLogPolyEval_in <= yT3_uid306_natLogPolyEval_b;
xTop27Bits_uid418_pT3_uid307_natLogPolyEval_b <= xTop27Bits_uid418_pT3_uid307_natLogPolyEval_in(37 downto 11);
--reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0(REG,584)@24
reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q <= xTop27Bits_uid418_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid420_pT3_uid307_natLogPolyEval(MULT,419)@25
topProd_uid420_pT3_uid307_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid420_pT3_uid307_natLogPolyEval_a),28)) * SIGNED(topProd_uid420_pT3_uid307_natLogPolyEval_b);
topProd_uid420_pT3_uid307_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid420_pT3_uid307_natLogPolyEval_a <= (others => '0');
topProd_uid420_pT3_uid307_natLogPolyEval_b <= (others => '0');
topProd_uid420_pT3_uid307_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid420_pT3_uid307_natLogPolyEval_a <= reg_xTop27Bits_uid418_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_0_q;
topProd_uid420_pT3_uid307_natLogPolyEval_b <= reg_yTop27Bits_uid419_pT3_uid307_natLogPolyEval_0_to_topProd_uid420_pT3_uid307_natLogPolyEval_1_q;
topProd_uid420_pT3_uid307_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid420_pT3_uid307_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid420_pT3_uid307_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid420_pT3_uid307_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid420_pT3_uid307_natLogPolyEval_q <= topProd_uid420_pT3_uid307_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid432_pT3_uid307_natLogPolyEval(ADD,431)@28
sumAHighB_uid432_pT3_uid307_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid420_pT3_uid307_natLogPolyEval_q(53)) & topProd_uid420_pT3_uid307_natLogPolyEval_q);
sumAHighB_uid432_pT3_uid307_natLogPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid431_pT3_uid307_natLogPolyEval_b(28)) & highBBits_uid431_pT3_uid307_natLogPolyEval_b);
sumAHighB_uid432_pT3_uid307_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid432_pT3_uid307_natLogPolyEval_a) + SIGNED(sumAHighB_uid432_pT3_uid307_natLogPolyEval_b));
sumAHighB_uid432_pT3_uid307_natLogPolyEval_q <= sumAHighB_uid432_pT3_uid307_natLogPolyEval_o(54 downto 0);
--lowRangeB_uid430_pT3_uid307_natLogPolyEval(BITSELECT,429)@28
lowRangeB_uid430_pT3_uid307_natLogPolyEval_in <= multSumOfTwo18_uid425_pT3_uid307_natLogPolyEval_b(3 downto 0);
lowRangeB_uid430_pT3_uid307_natLogPolyEval_b <= lowRangeB_uid430_pT3_uid307_natLogPolyEval_in(3 downto 0);
--add0_uid430_uid433_pT3_uid307_natLogPolyEval(BITJOIN,432)@28
add0_uid430_uid433_pT3_uid307_natLogPolyEval_q <= sumAHighB_uid432_pT3_uid307_natLogPolyEval_q & lowRangeB_uid430_pT3_uid307_natLogPolyEval_b;
--R_uid434_pT3_uid307_natLogPolyEval(BITSELECT,433)@28
R_uid434_pT3_uid307_natLogPolyEval_in <= add0_uid430_uid433_pT3_uid307_natLogPolyEval_q(57 downto 0);
R_uid434_pT3_uid307_natLogPolyEval_b <= R_uid434_pT3_uid307_natLogPolyEval_in(57 downto 17);
--reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1(REG,587)@28
reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q <= "00000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q <= R_uid434_pT3_uid307_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor(LOGICAL,1622)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_b <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_q <= not (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_a or ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_b);
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top(CONSTANT,1618)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top_q <= "01010";
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp(LOGICAL,1619)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_a <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_mem_top_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_a = ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg(REG,1620)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena(REG,1623)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd(LOGICAL,1624)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_a <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_sticky_ena_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_a and ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_b;
--memoryC1_uid280_natLogTabGen_lutmem(DUALMEM,479)@12
memoryC1_uid280_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid280_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid280_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid280_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid280_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid280_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid280_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid280_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid280_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid280_natLogTabGen_lutmem_ia
);
memoryC1_uid280_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid280_natLogTabGen_lutmem_q <= memoryC1_uid280_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4(REG,551)@14
reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q <= memoryC1_uid280_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid279_natLogTabGen_lutmem(DUALMEM,478)@12
memoryC1_uid279_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid279_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid279_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid279_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid279_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid279_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid279_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid279_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid279_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid279_natLogTabGen_lutmem_ia
);
memoryC1_uid279_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid279_natLogTabGen_lutmem_q <= memoryC1_uid279_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3(REG,550)@14
reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q <= memoryC1_uid279_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid278_natLogTabGen_lutmem(DUALMEM,477)@12
memoryC1_uid278_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid278_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid278_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid278_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid278_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid278_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid278_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid278_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid278_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid278_natLogTabGen_lutmem_ia
);
memoryC1_uid278_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid278_natLogTabGen_lutmem_q <= memoryC1_uid278_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2(REG,549)@14
reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q <= memoryC1_uid278_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid277_natLogTabGen_lutmem(DUALMEM,476)@12
memoryC1_uid277_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid277_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid277_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid277_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid277_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid277_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid277_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid277_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid277_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid277_natLogTabGen_lutmem_ia
);
memoryC1_uid277_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid277_natLogTabGen_lutmem_q <= memoryC1_uid277_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1(REG,548)@14
reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q <= memoryC1_uid277_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid276_natLogTabGen_lutmem(DUALMEM,475)@12
memoryC1_uid276_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid276_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid276_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC1_uid276_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC1_uid276_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid276_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid276_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid276_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid276_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid276_natLogTabGen_lutmem_ia
);
memoryC1_uid276_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid276_natLogTabGen_lutmem_q <= memoryC1_uid276_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0(REG,547)@14
reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q <= memoryC1_uid276_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid281_natLogTabGen(BITJOIN,280)@15
os_uid281_natLogTabGen_q <= reg_memoryC1_uid280_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_4_q & reg_memoryC1_uid279_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_3_q & reg_memoryC1_uid278_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_2_q & reg_memoryC1_uid277_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_1_q & reg_memoryC1_uid276_natLogTabGen_lutmem_0_to_os_uid281_natLogTabGen_0_q;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg(DELAY,1612)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 48, depth => 1 )
PORT MAP ( xin => os_uid281_natLogTabGen_q, xout => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt(COUNTER,1614)
-- every=1, low=0, high=10, step=1, init=1
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i = 9 THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i - 10;
ELSE
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_i,4));
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg(REG,1615)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux(MUX,1616)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s, ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q, ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem(DUALMEM,1613)
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ia <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_inputreg_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_aa <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ab <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 48,
widthad_a => 4,
numwords_a => 11,
width_b => 48,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_iq(47 downto 0);
--cIncludingRoundingBit_uid309_natLogPolyEval(BITJOIN,308)@28
cIncludingRoundingBit_uid309_natLogPolyEval_q <= ld_os_uid281_natLogTabGen_q_to_cIncludingRoundingBit_uid309_natLogPolyEval_b_replace_mem_q & o2_uid97_fpLogE1pxTest_q;
--reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0(REG,586)@28
reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q <= "00000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q <= cIncludingRoundingBit_uid309_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts3_uid310_natLogPolyEval(ADD,309)@29
ts3_uid310_natLogPolyEval_a <= STD_LOGIC_VECTOR((50 downto 50 => reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q(49)) & reg_cIncludingRoundingBit_uid309_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_0_q);
ts3_uid310_natLogPolyEval_b <= STD_LOGIC_VECTOR((50 downto 41 => reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q(40)) & reg_R_uid434_pT3_uid307_natLogPolyEval_0_to_ts3_uid310_natLogPolyEval_1_q);
ts3_uid310_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid310_natLogPolyEval_a) + SIGNED(ts3_uid310_natLogPolyEval_b));
ts3_uid310_natLogPolyEval_q <= ts3_uid310_natLogPolyEval_o(50 downto 0);
--s3_uid311_natLogPolyEval(BITSELECT,310)@29
s3_uid311_natLogPolyEval_in <= ts3_uid310_natLogPolyEval_q;
s3_uid311_natLogPolyEval_b <= s3_uid311_natLogPolyEval_in(50 downto 1);
--yTop27Bits_uid436_pT4_uid313_natLogPolyEval(BITSELECT,435)@29
yTop27Bits_uid436_pT4_uid313_natLogPolyEval_in <= s3_uid311_natLogPolyEval_b;
yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b <= yTop27Bits_uid436_pT4_uid313_natLogPolyEval_in(49 downto 23);
--reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9(REG,591)@29
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q <= yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor(LOGICAL,1705)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_b <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_q <= not (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_a or ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_b);
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top(CONSTANT,1701)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top_q <= "01011";
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp(LOGICAL,1702)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_a <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_mem_top_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q);
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_a = ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_b else "0";
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg(REG,1703)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena(REG,1706)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_nor_q = "1") THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd(LOGICAL,1707)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_a <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_sticky_ena_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_b <= en;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_a and ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_b;
--xBottomBits_uid439_pT4_uid313_natLogPolyEval(BITSELECT,438)@15
xBottomBits_uid439_pT4_uid313_natLogPolyEval_in <= zPPolyEval_uid91_fpLogE1pxTest_b(15 downto 0);
xBottomBits_uid439_pT4_uid313_natLogPolyEval_b <= xBottomBits_uid439_pT4_uid313_natLogPolyEval_in(15 downto 0);
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg(DELAY,1695)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => xBottomBits_uid439_pT4_uid313_natLogPolyEval_b, xout => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt(COUNTER,1697)
-- every=1, low=0, high=11, step=1, init=1
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i = 10 THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i - 11;
ELSE
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_i,4));
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg(REG,1698)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux(MUX,1699)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s <= en;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s, ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q, ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem(DUALMEM,1696)
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ia <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_inputreg_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_aa <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdreg_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ab <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_rdmux_q;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 4,
numwords_a => 12,
width_b => 16,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_iq,
address_a => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_aa,
data_a => ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_ia
);
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_iq(15 downto 0);
--pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval(BITJOIN,440)@29
pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_q <= ld_xBottomBits_uid439_pT4_uid313_natLogPolyEval_b_to_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_b_replace_mem_q & STD_LOGIC_VECTOR((9 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7(REG,590)@29
reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q <= pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid438_pT4_uid313_natLogPolyEval(BITSELECT,437)@29
yBottomBits_uid438_pT4_uid313_natLogPolyEval_in <= s3_uid311_natLogPolyEval_b(22 downto 0);
yBottomBits_uid438_pT4_uid313_natLogPolyEval_b <= yBottomBits_uid438_pT4_uid313_natLogPolyEval_in(22 downto 0);
--ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a(DELAY,1104)@29
ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => yBottomBits_uid438_pT4_uid313_natLogPolyEval_b, xout => ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval(BITJOIN,439)@30
spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_q <= GND_q & ld_yBottomBits_uid438_pT4_uid313_natLogPolyEval_b_to_spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_a_q;
--pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval(BITJOIN,441)@30
pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_q <= spad_yBottomBits_uid438_uid440_pT4_uid313_natLogPolyEval_q & STD_LOGIC_VECTOR((2 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6(REG,589)@30
reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q <= pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor(LOGICAL,1692)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_b <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_q <= not (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_a or ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_b);
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top(CONSTANT,1688)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top_q <= "01100";
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp(LOGICAL,1689)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_a <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_mem_top_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_a = ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_b else "0";
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg(REG,1690)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena(REG,1693)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd(LOGICAL,1694)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_b <= en;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_a and ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt(COUNTER,1684)
-- every=1, low=0, high=12, step=1, init=1
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i = 11 THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i - 12;
ELSE
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_i,4));
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg(REG,1685)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux(MUX,1686)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s <= en;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem(DUALMEM,1683)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ia <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_yT3_uid306_natLogPolyEval_a_inputreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_rdmux_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 43,
widthad_a => 4,
numwords_a => 13,
width_b => 43,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_iq(42 downto 0);
--xTop27Bits_uid435_pT4_uid313_natLogPolyEval(BITSELECT,434)@30
xTop27Bits_uid435_pT4_uid313_natLogPolyEval_in <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_a_replace_mem_q;
xTop27Bits_uid435_pT4_uid313_natLogPolyEval_b <= xTop27Bits_uid435_pT4_uid313_natLogPolyEval_in(42 downto 16);
--reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4(REG,588)@30
reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q <= xTop27Bits_uid435_pT4_uid313_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma(CHAINMULTADD,490)@31
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(0),28));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(1),28));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(0) * multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_l(1) * multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(1);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(0),56);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_p(1),56);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_w(1);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(1) + multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_x(1);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q),27);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid439_uid441_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_7_q),27);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid438_uid442_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_6_q),27);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(0) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(0);
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(1) <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval(BITSELECT,443)@34
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_in <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_q;
multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_in(54 downto 3);
--highBBits_uid446_pT4_uid313_natLogPolyEval(BITSELECT,445)@34
highBBits_uid446_pT4_uid313_natLogPolyEval_in <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b;
highBBits_uid446_pT4_uid313_natLogPolyEval_b <= highBBits_uid446_pT4_uid313_natLogPolyEval_in(51 downto 23);
--ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a(DELAY,1276)@29
ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b, xout => ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1(REG,593)@30
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q <= ld_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_b_to_reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_a_q;
END IF;
END IF;
END PROCESS;
--topProd_uid437_pT4_uid313_natLogPolyEval(MULT,436)@31
topProd_uid437_pT4_uid313_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid437_pT4_uid313_natLogPolyEval_a),28)) * SIGNED(topProd_uid437_pT4_uid313_natLogPolyEval_b);
topProd_uid437_pT4_uid313_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid437_pT4_uid313_natLogPolyEval_a <= (others => '0');
topProd_uid437_pT4_uid313_natLogPolyEval_b <= (others => '0');
topProd_uid437_pT4_uid313_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid437_pT4_uid313_natLogPolyEval_a <= reg_xTop27Bits_uid435_pT4_uid313_natLogPolyEval_0_to_multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_cma_4_q;
topProd_uid437_pT4_uid313_natLogPolyEval_b <= reg_yTop27Bits_uid436_pT4_uid313_natLogPolyEval_0_to_topProd_uid437_pT4_uid313_natLogPolyEval_1_q;
topProd_uid437_pT4_uid313_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid437_pT4_uid313_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid437_pT4_uid313_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid437_pT4_uid313_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid437_pT4_uid313_natLogPolyEval_q <= topProd_uid437_pT4_uid313_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid447_pT4_uid313_natLogPolyEval(ADD,446)@34
sumAHighB_uid447_pT4_uid313_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid437_pT4_uid313_natLogPolyEval_q(53)) & topProd_uid437_pT4_uid313_natLogPolyEval_q);
sumAHighB_uid447_pT4_uid313_natLogPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid446_pT4_uid313_natLogPolyEval_b(28)) & highBBits_uid446_pT4_uid313_natLogPolyEval_b);
sumAHighB_uid447_pT4_uid313_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid447_pT4_uid313_natLogPolyEval_a) + SIGNED(sumAHighB_uid447_pT4_uid313_natLogPolyEval_b));
sumAHighB_uid447_pT4_uid313_natLogPolyEval_q <= sumAHighB_uid447_pT4_uid313_natLogPolyEval_o(54 downto 0);
--lowRangeB_uid445_pT4_uid313_natLogPolyEval(BITSELECT,444)@34
lowRangeB_uid445_pT4_uid313_natLogPolyEval_in <= multSumOfTwo27_uid440_pT4_uid313_natLogPolyEval_b(22 downto 0);
lowRangeB_uid445_pT4_uid313_natLogPolyEval_b <= lowRangeB_uid445_pT4_uid313_natLogPolyEval_in(22 downto 0);
--add0_uid445_uid448_pT4_uid313_natLogPolyEval(BITJOIN,447)@34
add0_uid445_uid448_pT4_uid313_natLogPolyEval_q <= sumAHighB_uid447_pT4_uid313_natLogPolyEval_q & lowRangeB_uid445_pT4_uid313_natLogPolyEval_b;
--R_uid449_pT4_uid313_natLogPolyEval(BITSELECT,448)@34
R_uid449_pT4_uid313_natLogPolyEval_in <= add0_uid445_uid448_pT4_uid313_natLogPolyEval_q(76 downto 0);
R_uid449_pT4_uid313_natLogPolyEval_b <= R_uid449_pT4_uid313_natLogPolyEval_in(76 downto 25);
--reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1(REG,595)@34
reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q <= R_uid449_pT4_uid313_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor(LOGICAL,1635)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_b <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_q <= not (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_a or ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_b);
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top(CONSTANT,1631)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top_q <= "010000";
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp(LOGICAL,1632)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_a <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_mem_top_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_a = ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg(REG,1633)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena(REG,1636)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd(LOGICAL,1637)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_a <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_sticky_ena_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_a and ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_b;
--memoryC0_uid274_natLogTabGen_lutmem(DUALMEM,474)@12
memoryC0_uid274_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid274_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid274_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid274_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid274_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid274_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid274_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid274_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid274_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid274_natLogTabGen_lutmem_ia
);
memoryC0_uid274_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid274_natLogTabGen_lutmem_q <= memoryC0_uid274_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5(REG,541)@14
reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q <= memoryC0_uid274_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid273_natLogTabGen_lutmem(DUALMEM,473)@12
memoryC0_uid273_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid273_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid273_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid273_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid273_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid273_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid273_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid273_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid273_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid273_natLogTabGen_lutmem_ia
);
memoryC0_uid273_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid273_natLogTabGen_lutmem_q <= memoryC0_uid273_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4(REG,540)@14
reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q <= memoryC0_uid273_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid272_natLogTabGen_lutmem(DUALMEM,472)@12
memoryC0_uid272_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid272_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid272_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid272_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid272_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid272_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid272_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid272_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid272_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid272_natLogTabGen_lutmem_ia
);
memoryC0_uid272_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid272_natLogTabGen_lutmem_q <= memoryC0_uid272_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3(REG,539)@14
reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q <= memoryC0_uid272_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid271_natLogTabGen_lutmem(DUALMEM,471)@12
memoryC0_uid271_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid271_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid271_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid271_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid271_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid271_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid271_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid271_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid271_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid271_natLogTabGen_lutmem_ia
);
memoryC0_uid271_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid271_natLogTabGen_lutmem_q <= memoryC0_uid271_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2(REG,538)@14
reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q <= memoryC0_uid271_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid270_natLogTabGen_lutmem(DUALMEM,470)@12
memoryC0_uid270_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid270_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid270_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid270_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid270_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid270_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid270_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid270_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid270_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid270_natLogTabGen_lutmem_ia
);
memoryC0_uid270_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid270_natLogTabGen_lutmem_q <= memoryC0_uid270_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1(REG,537)@14
reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q <= memoryC0_uid270_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid269_natLogTabGen_lutmem(DUALMEM,469)@12
memoryC0_uid269_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid269_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid269_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid269_natLogTabGen_lutmem_0_q;
memoryC0_uid269_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1p_double_s5_memoryC0_uid269_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid269_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid269_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid269_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid269_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid269_natLogTabGen_lutmem_ia
);
memoryC0_uid269_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid269_natLogTabGen_lutmem_q <= memoryC0_uid269_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0(REG,536)@14
reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q <= memoryC0_uid269_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid275_natLogTabGen(BITJOIN,274)@15
os_uid275_natLogTabGen_q <= reg_memoryC0_uid274_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_5_q & reg_memoryC0_uid273_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_4_q & reg_memoryC0_uid272_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_3_q & reg_memoryC0_uid271_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_2_q & reg_memoryC0_uid270_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_1_q & reg_memoryC0_uid269_natLogTabGen_lutmem_0_to_os_uid275_natLogTabGen_0_q;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg(DELAY,1625)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => os_uid275_natLogTabGen_q, xout => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt(COUNTER,1627)
-- every=1, low=0, high=16, step=1, init=1
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i = 15 THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i - 16;
ELSE
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_i,5));
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg(REG,1628)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux(MUX,1629)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s, ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q, ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem(DUALMEM,1626)
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ia <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_inputreg_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_aa <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ab <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 60,
widthad_a => 5,
numwords_a => 17,
width_b => 60,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_iq(59 downto 0);
--rndBit_uid314_natLogPolyEval(CONSTANT,313)
rndBit_uid314_natLogPolyEval_q <= "001";
--cIncludingRoundingBit_uid315_natLogPolyEval(BITJOIN,314)@34
cIncludingRoundingBit_uid315_natLogPolyEval_q <= ld_os_uid275_natLogTabGen_q_to_cIncludingRoundingBit_uid315_natLogPolyEval_b_replace_mem_q & rndBit_uid314_natLogPolyEval_q;
--reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0(REG,594)@34
reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q <= cIncludingRoundingBit_uid315_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts4_uid316_natLogPolyEval(ADD,315)@35
ts4_uid316_natLogPolyEval_a <= STD_LOGIC_VECTOR((63 downto 63 => reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q(62)) & reg_cIncludingRoundingBit_uid315_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_0_q);
ts4_uid316_natLogPolyEval_b <= STD_LOGIC_VECTOR((63 downto 52 => reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q(51)) & reg_R_uid449_pT4_uid313_natLogPolyEval_0_to_ts4_uid316_natLogPolyEval_1_q);
ts4_uid316_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid316_natLogPolyEval_a) + SIGNED(ts4_uid316_natLogPolyEval_b));
ts4_uid316_natLogPolyEval_q <= ts4_uid316_natLogPolyEval_o(63 downto 0);
--s4_uid317_natLogPolyEval(BITSELECT,316)@35
s4_uid317_natLogPolyEval_in <= ts4_uid316_natLogPolyEval_q;
s4_uid317_natLogPolyEval_b <= s4_uid317_natLogPolyEval_in(63 downto 1);
--peOR_uid93_fpLogE1pxTest(BITSELECT,92)@35
peOR_uid93_fpLogE1pxTest_in <= s4_uid317_natLogPolyEval_b(61 downto 0);
peOR_uid93_fpLogE1pxTest_b <= peOR_uid93_fpLogE1pxTest_in(61 downto 6);
--postPEMul_uid103_fpLogE1pxTest_b_2(BITSELECT,453)@35
postPEMul_uid103_fpLogE1pxTest_b_2_in <= STD_LOGIC_VECTOR((80 downto 56 => peOR_uid93_fpLogE1pxTest_b(55)) & peOR_uid93_fpLogE1pxTest_b);
postPEMul_uid103_fpLogE1pxTest_b_2_b <= postPEMul_uid103_fpLogE1pxTest_b_2_in(80 downto 54);
--reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1(REG,606)@35
reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q <= postPEMul_uid103_fpLogE1pxTest_b_2_b;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor(LOGICAL,1470)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b);
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top(CONSTANT,1442)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q <= "011111";
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp(LOGICAL,1467)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q);
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg(REG,1468)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena(REG,1471)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd(LOGICAL,1472)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg(REG,1439)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1438)
-- every=1, low=0, high=31, step=1, init=1
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_i,5));
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem(DUALMEM,1463)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 5,
numwords_a => 32,
width_b => 52,
widthad_b => 5,
numwords_b => 32,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => en(0),
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq(51 downto 0);
--sEz_uid98_fpLogE1pxTest(BITJOIN,97)@35
sEz_uid98_fpLogE1pxTest_q <= o2_uid97_fpLogE1pxTest_q & ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor(LOGICAL,1483)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_b <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_q <= not (ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_a or ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_b);
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top(CONSTANT,1455)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top_q <= "010101";
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp(LOGICAL,1456)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_a <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_mem_top_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q);
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_q <= "1" when ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_a = ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_b else "0";
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg(REG,1457)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena(REG,1484)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_nor_q = "1") THEN
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd(LOGICAL,1485)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_a <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_sticky_ena_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_b <= en;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_q <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_a and ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_b;
--fracBRed_uid99_fpLogE1pxTest(BITSELECT,98)@11
fracBRed_uid99_fpLogE1pxTest_in <= fracB_uid83_fpLogE1pxTest_q;
fracBRed_uid99_fpLogE1pxTest_b <= fracBRed_uid99_fpLogE1pxTest_in(52 downto 1);
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg(DELAY,1473)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => fracBRed_uid99_fpLogE1pxTest_b, xout => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1451)
-- every=1, low=0, high=21, step=1, init=1
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i = 20 THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i - 21;
ELSE
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_i,5));
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg(REG,1452)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux(MUX,1453)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s, ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q, ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem(DUALMEM,1474)
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ia <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_inputreg_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_aa <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ab <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 5,
numwords_a => 22,
width_b => 52,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_ia
);
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_q <= ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_iq(51 downto 0);
--sEz_uid101_fpLogE1pxTest(BITJOIN,100)@35
sEz_uid101_fpLogE1pxTest_q <= z2_uid100_fpLogE1pxTest_q & ld_fracBRed_uid99_fpLogE1pxTest_b_to_sEz_uid101_fpLogE1pxTest_a_replace_mem_q;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor(LOGICAL,1459)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_b <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_q <= not (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_a or ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_b);
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena(REG,1460)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_nor_q = "1") THEN
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd(LOGICAL,1461)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_a <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_sticky_ena_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_b <= en;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_a and ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_b;
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg(DELAY,1449)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => c_uid87_fpLogE1pxTest_q, xout => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem(DUALMEM,1450)
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ia <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_inputreg_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_aa <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdreg_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ab <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_rdmux_q;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 22,
width_b => 1,
widthad_b => 5,
numwords_b => 22,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_ia
);
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_q <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_iq(0 downto 0);
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor(LOGICAL,1446)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_b <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_q <= not (ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_a or ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_b);
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp(LOGICAL,1443)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_mem_top_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q);
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_q <= "1" when ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_a = ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_b else "0";
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg(REG,1444)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena(REG,1447)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_nor_q = "1") THEN
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd(LOGICAL,1448)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_sticky_ena_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_b <= en;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_a and ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_b;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg(DELAY,1436)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => branch3_uid73_fpLogE1pxTest_q, xout => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux(MUX,1440)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s, ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q, ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem(DUALMEM,1437)
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ia <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_inputreg_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_aa <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdreg_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ab <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_rdmux_q;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 32,
width_b => 1,
widthad_b => 5,
numwords_b => 32,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_ia
);
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_q <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_iq(0 downto 0);
--branch3OrC_uid94_fpLogE1pxTest(LOGICAL,93)@34
branch3OrC_uid94_fpLogE1pxTest_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_replace_mem_q;
branch3OrC_uid94_fpLogE1pxTest_b <= ld_c_uid87_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_b_replace_mem_q;
branch3OrC_uid94_fpLogE1pxTest_q_i <= branch3OrC_uid94_fpLogE1pxTest_a or branch3OrC_uid94_fpLogE1pxTest_b;
branch3OrC_uid94_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => branch3OrC_uid94_fpLogE1pxTest_q, xin => branch3OrC_uid94_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--sEz_uid102_fpLogE1pxTest(MUX,101)@35
sEz_uid102_fpLogE1pxTest_s <= branch3OrC_uid94_fpLogE1pxTest_q;
sEz_uid102_fpLogE1pxTest: PROCESS (sEz_uid102_fpLogE1pxTest_s, en, sEz_uid101_fpLogE1pxTest_q, sEz_uid98_fpLogE1pxTest_q)
BEGIN
CASE sEz_uid102_fpLogE1pxTest_s IS
WHEN "0" => sEz_uid102_fpLogE1pxTest_q <= sEz_uid101_fpLogE1pxTest_q;
WHEN "1" => sEz_uid102_fpLogE1pxTest_q <= sEz_uid98_fpLogE1pxTest_q;
WHEN OTHERS => sEz_uid102_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a_1(BITSELECT,450)@35
postPEMul_uid103_fpLogE1pxTest_a_1_in <= sEz_uid102_fpLogE1pxTest_q;
postPEMul_uid103_fpLogE1pxTest_a_1_b <= postPEMul_uid103_fpLogE1pxTest_a_1_in(53 downto 27);
--reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0(REG,598)@35
reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q <= postPEMul_uid103_fpLogE1pxTest_a_1_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a1_b2(MULT,459)@36
postPEMul_uid103_fpLogE1pxTest_a1_b2_pr <= SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b2_a) * SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b2_b);
postPEMul_uid103_fpLogE1pxTest_a1_b2_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b2_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b2_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a1_b2_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q;
postPEMul_uid103_fpLogE1pxTest_a1_b2_s1 <= STD_LOGIC_VECTOR(postPEMul_uid103_fpLogE1pxTest_a1_b2_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a1_b2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b2_q <= postPEMul_uid103_fpLogE1pxTest_a1_b2_s1;
END IF;
END IF;
END PROCESS;
--ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a(DELAY,1139)@39
ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a : dspba_delay
GENERIC MAP ( width => 54, depth => 2 )
PORT MAP ( xin => postPEMul_uid103_fpLogE1pxTest_a1_b2_q, xout => ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid103_fpLogE1pxTest_align_3(BITSHIFT,465)@41
postPEMul_uid103_fpLogE1pxTest_align_3_q_int <= ld_postPEMul_uid103_fpLogE1pxTest_a1_b2_q_to_postPEMul_uid103_fpLogE1pxTest_align_3_a_q & "000000000000000000000000000000000000000000000000000000000000000000000000000000000";
postPEMul_uid103_fpLogE1pxTest_align_3_q <= postPEMul_uid103_fpLogE1pxTest_align_3_q_int(134 downto 0);
--postPEMul_uid103_fpLogE1pxTest_a_0(BITSELECT,449)@35
postPEMul_uid103_fpLogE1pxTest_a_0_in <= sEz_uid102_fpLogE1pxTest_q(26 downto 0);
postPEMul_uid103_fpLogE1pxTest_a_0_b <= postPEMul_uid103_fpLogE1pxTest_a_0_in(26 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0(REG,596)@35
reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q <= postPEMul_uid103_fpLogE1pxTest_a_0_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a0_b2(MULT,458)@36
postPEMul_uid103_fpLogE1pxTest_a0_b2_pr <= signed(resize(UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b2_a),28)) * SIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b2_b);
postPEMul_uid103_fpLogE1pxTest_a0_b2_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b2_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b2_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a0_b2_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_2_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b2_1_q;
postPEMul_uid103_fpLogE1pxTest_a0_b2_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid103_fpLogE1pxTest_a0_b2_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a0_b2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b2_q <= postPEMul_uid103_fpLogE1pxTest_a0_b2_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_b_1(BITSELECT,452)@35
postPEMul_uid103_fpLogE1pxTest_b_1_in <= peOR_uid93_fpLogE1pxTest_b(53 downto 0);
postPEMul_uid103_fpLogE1pxTest_b_1_b <= postPEMul_uid103_fpLogE1pxTest_b_1_in(53 downto 27);
--reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1(REG,601)@35
reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q <= postPEMul_uid103_fpLogE1pxTest_b_1_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a1_b1(MULT,457)@36
postPEMul_uid103_fpLogE1pxTest_a1_b1_pr <= SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b1_a) * signed(resize(UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b1_b),28));
postPEMul_uid103_fpLogE1pxTest_a1_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b1_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a1_b1_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q;
postPEMul_uid103_fpLogE1pxTest_a1_b1_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid103_fpLogE1pxTest_a1_b1_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a1_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b1_q <= postPEMul_uid103_fpLogE1pxTest_a1_b1_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0(ADD,461)@39
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_a <= STD_LOGIC_VECTOR((54 downto 54 => postPEMul_uid103_fpLogE1pxTest_a1_b1_q(53)) & postPEMul_uid103_fpLogE1pxTest_a1_b1_q);
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_b <= STD_LOGIC_VECTOR((54 downto 54 => postPEMul_uid103_fpLogE1pxTest_a0_b2_q(53)) & postPEMul_uid103_fpLogE1pxTest_a0_b2_q);
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_b));
postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q <= postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_o(54 downto 0);
--ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a(DELAY,1138)@39
ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a : dspba_delay
GENERIC MAP ( width => 55, depth => 1 )
PORT MAP ( xin => postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q, xout => ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid103_fpLogE1pxTest_align_2(BITSHIFT,464)@40
postPEMul_uid103_fpLogE1pxTest_align_2_q_int <= ld_postPEMul_uid103_fpLogE1pxTest_addcol_2_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
postPEMul_uid103_fpLogE1pxTest_align_2_q <= postPEMul_uid103_fpLogE1pxTest_align_2_q_int(108 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0(REG,609)@40
reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q <= postPEMul_uid103_fpLogE1pxTest_align_2_q;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_result_add_0_1(ADD,467)@41
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_a <= STD_LOGIC_VECTOR((135 downto 109 => reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q(108)) & reg_postPEMul_uid103_fpLogE1pxTest_align_2_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_1_0_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_b <= STD_LOGIC_VECTOR((135 downto 135 => postPEMul_uid103_fpLogE1pxTest_align_3_q(134)) & postPEMul_uid103_fpLogE1pxTest_align_3_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_1_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_1_b));
postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q <= postPEMul_uid103_fpLogE1pxTest_result_add_0_1_o(135 downto 0);
--postPEMul_uid103_fpLogE1pxTest_a0_b1(MULT,456)@36
postPEMul_uid103_fpLogE1pxTest_a0_b1_pr <= UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b1_a) * UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b1_b);
postPEMul_uid103_fpLogE1pxTest_a0_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b1_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a0_b1_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_1_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b1_1_q;
postPEMul_uid103_fpLogE1pxTest_a0_b1_s1 <= STD_LOGIC_VECTOR(postPEMul_uid103_fpLogE1pxTest_a0_b1_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a0_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b1_q <= postPEMul_uid103_fpLogE1pxTest_a0_b1_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_b_0(BITSELECT,451)@35
postPEMul_uid103_fpLogE1pxTest_b_0_in <= peOR_uid93_fpLogE1pxTest_b(26 downto 0);
postPEMul_uid103_fpLogE1pxTest_b_0_b <= postPEMul_uid103_fpLogE1pxTest_b_0_in(26 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1(REG,597)@35
reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q <= postPEMul_uid103_fpLogE1pxTest_b_0_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_a1_b0(MULT,455)@36
postPEMul_uid103_fpLogE1pxTest_a1_b0_pr <= SIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b0_a) * signed(resize(UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a1_b0_b),28));
postPEMul_uid103_fpLogE1pxTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b0_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_1_0_to_postPEMul_uid103_fpLogE1pxTest_a1_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a1_b0_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q;
postPEMul_uid103_fpLogE1pxTest_a1_b0_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid103_fpLogE1pxTest_a1_b0_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a1_b0_q <= postPEMul_uid103_fpLogE1pxTest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0(ADD,460)@39
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_a <= STD_LOGIC_VECTOR((56 downto 54 => postPEMul_uid103_fpLogE1pxTest_a1_b0_q(53)) & postPEMul_uid103_fpLogE1pxTest_a1_b0_q);
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_b <= STD_LOGIC_VECTOR('0' & "00" & postPEMul_uid103_fpLogE1pxTest_a0_b1_q);
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_b));
postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q <= postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_o(55 downto 0);
--ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a(DELAY,1137)@39
ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a : dspba_delay
GENERIC MAP ( width => 56, depth => 1 )
PORT MAP ( xin => postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q, xout => ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid103_fpLogE1pxTest_align_1(BITSHIFT,463)@40
postPEMul_uid103_fpLogE1pxTest_align_1_q_int <= ld_postPEMul_uid103_fpLogE1pxTest_addcol_1_add_0_0_q_to_postPEMul_uid103_fpLogE1pxTest_align_1_a_q & "000000000000000000000000000";
postPEMul_uid103_fpLogE1pxTest_align_1_q <= postPEMul_uid103_fpLogE1pxTest_align_1_q_int(82 downto 0);
--postPEMul_uid103_fpLogE1pxTest_a0_b0(MULT,454)@36
postPEMul_uid103_fpLogE1pxTest_a0_b0_pr <= UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b0_a) * UNSIGNED(postPEMul_uid103_fpLogE1pxTest_a0_b0_b);
postPEMul_uid103_fpLogE1pxTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b0_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_a <= reg_postPEMul_uid103_fpLogE1pxTest_a_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_0_q;
postPEMul_uid103_fpLogE1pxTest_a0_b0_b <= reg_postPEMul_uid103_fpLogE1pxTest_b_0_0_to_postPEMul_uid103_fpLogE1pxTest_a0_b0_1_q;
postPEMul_uid103_fpLogE1pxTest_a0_b0_s1 <= STD_LOGIC_VECTOR(postPEMul_uid103_fpLogE1pxTest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a0_b0_q <= postPEMul_uid103_fpLogE1pxTest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_align_0(BITSHIFT,462)@39
postPEMul_uid103_fpLogE1pxTest_align_0_q_int <= postPEMul_uid103_fpLogE1pxTest_a0_b0_q;
postPEMul_uid103_fpLogE1pxTest_align_0_q <= postPEMul_uid103_fpLogE1pxTest_align_0_q_int(53 downto 0);
--reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0(REG,602)@39
reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q <= postPEMul_uid103_fpLogE1pxTest_align_0_q;
END IF;
END IF;
END PROCESS;
--postPEMul_uid103_fpLogE1pxTest_result_add_0_0(ADD,466)@40
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_a <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000000" & reg_postPEMul_uid103_fpLogE1pxTest_align_0_0_to_postPEMul_uid103_fpLogE1pxTest_result_add_0_0_0_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_b <= STD_LOGIC_VECTOR((84 downto 83 => postPEMul_uid103_fpLogE1pxTest_align_1_q(82)) & postPEMul_uid103_fpLogE1pxTest_align_1_q);
postPEMul_uid103_fpLogE1pxTest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_0_0_b));
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q <= postPEMul_uid103_fpLogE1pxTest_result_add_0_0_o(83 downto 0);
--postPEMul_uid103_fpLogE1pxTest_result_add_1_0(ADD,468)@41
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_a <= STD_LOGIC_VECTOR((136 downto 84 => postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q(83)) & postPEMul_uid103_fpLogE1pxTest_result_add_0_0_q);
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_b <= STD_LOGIC_VECTOR((136 downto 136 => postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q(135)) & postPEMul_uid103_fpLogE1pxTest_result_add_0_1_q);
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_1_0_a) + SIGNED(postPEMul_uid103_fpLogE1pxTest_result_add_1_0_b));
postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q <= postPEMul_uid103_fpLogE1pxTest_result_add_1_0_o(136 downto 0);
--highBBits_uid107_fpLogE1pxTest(BITSELECT,106)@41
highBBits_uid107_fpLogE1pxTest_in <= postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q(109 downto 0);
highBBits_uid107_fpLogE1pxTest_b <= highBBits_uid107_fpLogE1pxTest_in(109 downto 51);
--reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1(REG,617)@41
reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q <= "00000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q <= highBBits_uid107_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--wideZero_uid104_fpLogE1pxTest(CONSTANT,103)
wideZero_uid104_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor(LOGICAL,1422)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q <= not (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a or ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b);
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top(CONSTANT,1418)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q <= "011001";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp(LOGICAL,1419)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q <= "1" when ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a = ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b else "0";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg(REG,1420)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena(REG,1423)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd(LOGICAL,1424)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b <= en;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a and ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b;
--expBran3PreExt_uid45_fpLogE1pxTest(SUB,44)@8
expBran3PreExt_uid45_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstBiasMO_uid10_fpLogE1pxTest_q);
expBran3PreExt_uid45_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000" & r_uid225_leadingZeros_uid44_fpLogE1pxTest_q);
expBran3PreExt_uid45_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expBran3PreExt_uid45_fpLogE1pxTest_a) - UNSIGNED(expBran3PreExt_uid45_fpLogE1pxTest_b));
expBran3PreExt_uid45_fpLogE1pxTest_q <= expBran3PreExt_uid45_fpLogE1pxTest_o(11 downto 0);
--expBran3Pre_uid46_fpLogE1pxTest(BITSELECT,45)@8
expBran3Pre_uid46_fpLogE1pxTest_in <= expBran3PreExt_uid45_fpLogE1pxTest_q(10 downto 0);
expBran3Pre_uid46_fpLogE1pxTest_b <= expBran3Pre_uid46_fpLogE1pxTest_in(10 downto 0);
--reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5(REG,613)@8
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q <= expBran3Pre_uid46_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor(LOGICAL,1370)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_b <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_q <= not (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_a or ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_b);
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top(CONSTANT,1366)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top_q <= "010";
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp(LOGICAL,1367)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_a <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_mem_top_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q);
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_q <= "1" when ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_a = ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_b else "0";
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg(REG,1368)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena(REG,1371)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_nor_q = "1") THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd(LOGICAL,1372)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_a <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_sticky_ena_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_b <= en;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_a and ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_b;
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a(DELAY,1293)@0
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a : dspba_delay
GENERIC MAP ( width => 11, depth => 2 )
PORT MAP ( xin => expX_uid6_fpLogE1pxTest_b, xout => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0(REG,610)@2
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_a_q;
END IF;
END IF;
END PROCESS;
--eUpdateOPOFracX_uid55_fpLogE1pxTest(ADD,54)@3
eUpdateOPOFracX_uid55_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q);
eUpdateOPOFracX_uid55_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00000000000" & reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_oPlusOFracXNorm_uid61_fpLogE1pxTest_1_q);
eUpdateOPOFracX_uid55_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
eUpdateOPOFracX_uid55_fpLogE1pxTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
eUpdateOPOFracX_uid55_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(eUpdateOPOFracX_uid55_fpLogE1pxTest_a) + UNSIGNED(eUpdateOPOFracX_uid55_fpLogE1pxTest_b));
END IF;
END IF;
END PROCESS;
eUpdateOPOFracX_uid55_fpLogE1pxTest_q <= eUpdateOPOFracX_uid55_fpLogE1pxTest_o(11 downto 0);
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg(DELAY,1360)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => eUpdateOPOFracX_uid55_fpLogE1pxTest_q, xout => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt(COUNTER,1362)
-- every=1, low=0, high=2, step=1, init=1
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i = 1 THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_eq = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i - 2;
ELSE
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_i,2));
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg(REG,1363)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux(MUX,1364)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s <= en;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux: PROCESS (ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s, ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q, ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q)
BEGIN
CASE ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_s IS
WHEN "0" => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q;
WHEN "1" => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem(DUALMEM,1361)
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ia <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_inputreg_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_aa <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdreg_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ab <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_rdmux_q;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 2,
numwords_a => 3,
width_b => 12,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_ia
);
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_iq(11 downto 0);
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor(LOGICAL,1729)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_b <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_q <= not (ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_a or ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_b);
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena(REG,1730)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_nor_q = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd(LOGICAL,1731)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_a <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_b <= en;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_a and ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_b;
--ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem(DUALMEM,1720)
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ia <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_aa <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ab <= ld_os_uid286_natLogTabGen_q_to_cIncludingRoundingBit_uid303_natLogPolyEval_b_replace_rdmux_q;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 3,
numwords_a => 6,
width_b => 11,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_iq,
address_a => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_aa,
data_a => ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_ia
);
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_reset0 <= areset;
ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_iq(10 downto 0);
--reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2(REG,612)@8
reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q <= ld_expX_uid6_fpLogE1pxTest_b_to_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--expB_uid79_fpLogE1pxTest(MUX,78)@9
expB_uid79_fpLogE1pxTest_s <= branEnc_uid77_fpLogE1pxTest_q;
expB_uid79_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expB_uid79_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expB_uid79_fpLogE1pxTest_s IS
WHEN "00" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q);
WHEN "01" => expB_uid79_fpLogE1pxTest_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_replace_mem_q;
WHEN "10" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
WHEN "11" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q);
WHEN OTHERS => expB_uid79_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg(DELAY,1412)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => expB_uid79_fpLogE1pxTest_q, xout => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1414)
-- every=1, low=0, high=25, step=1, init=1
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i = 24 THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i - 25;
ELSE
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i,5));
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg(REG,1415)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux(MUX,1416)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s, ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q, ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem(DUALMEM,1413)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 5,
numwords_a => 26,
width_b => 12,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia
);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq(11 downto 0);
--e_uid84_fpLogE1pxTest(SUB,83)@38
e_uid84_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q);
e_uid84_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid9_fpLogE1pxTest_q);
e_uid84_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(e_uid84_fpLogE1pxTest_a) - UNSIGNED(e_uid84_fpLogE1pxTest_b));
e_uid84_fpLogE1pxTest_q <= e_uid84_fpLogE1pxTest_o(12 downto 0);
--xv0_uid262_constMult(BITSELECT,261)@38
xv0_uid262_constMult_in <= e_uid84_fpLogE1pxTest_q(5 downto 0);
xv0_uid262_constMult_b <= xv0_uid262_constMult_in(5 downto 0);
--reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0(REG,615)@38
reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q <= xv0_uid262_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a(DELAY,926)@39
ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q, xout => ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q, ena => en(0), clk => clk, aclr => areset );
--p0_uid265_constMult(LOOKUP,264)@40
p0_uid265_constMult: PROCESS (ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_xv0_uid262_constMult_0_to_p0_uid265_constMult_0_q_to_p0_uid265_constMult_a_q) IS
WHEN "000000" => p0_uid265_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p0_uid265_constMult_q <= "000000101100010111001000010111111101111101000111001111011110000";
WHEN "000010" => p0_uid265_constMult_q <= "000001011000101110010000101111111011111010001110011110111100000";
WHEN "000011" => p0_uid265_constMult_q <= "000010000101000101011001000111111001110111010101101110011010000";
WHEN "000100" => p0_uid265_constMult_q <= "000010110001011100100001011111110111110100011100111101111000000";
WHEN "000101" => p0_uid265_constMult_q <= "000011011101110011101001110111110101110001100100001101010110000";
WHEN "000110" => p0_uid265_constMult_q <= "000100001010001010110010001111110011101110101011011100110100000";
WHEN "000111" => p0_uid265_constMult_q <= "000100110110100001111010100111110001101011110010101100010010000";
WHEN "001000" => p0_uid265_constMult_q <= "000101100010111001000010111111101111101000111001111011110000000";
WHEN "001001" => p0_uid265_constMult_q <= "000110001111010000001011010111101101100110000001001011001110000";
WHEN "001010" => p0_uid265_constMult_q <= "000110111011100111010011101111101011100011001000011010101100000";
WHEN "001011" => p0_uid265_constMult_q <= "000111100111111110011100000111101001100000001111101010001010000";
WHEN "001100" => p0_uid265_constMult_q <= "001000010100010101100100011111100111011101010110111001101000000";
WHEN "001101" => p0_uid265_constMult_q <= "001001000000101100101100110111100101011010011110001001000110000";
WHEN "001110" => p0_uid265_constMult_q <= "001001101101000011110101001111100011010111100101011000100100000";
WHEN "001111" => p0_uid265_constMult_q <= "001010011001011010111101100111100001010100101100101000000010000";
WHEN "010000" => p0_uid265_constMult_q <= "001011000101110010000101111111011111010001110011110111100000000";
WHEN "010001" => p0_uid265_constMult_q <= "001011110010001001001110010111011101001110111011000110111110000";
WHEN "010010" => p0_uid265_constMult_q <= "001100011110100000010110101111011011001100000010010110011100000";
WHEN "010011" => p0_uid265_constMult_q <= "001101001010110111011111000111011001001001001001100101111010000";
WHEN "010100" => p0_uid265_constMult_q <= "001101110111001110100111011111010111000110010000110101011000000";
WHEN "010101" => p0_uid265_constMult_q <= "001110100011100101101111110111010101000011011000000100110110000";
WHEN "010110" => p0_uid265_constMult_q <= "001111001111111100111000001111010011000000011111010100010100000";
WHEN "010111" => p0_uid265_constMult_q <= "001111111100010100000000100111010000111101100110100011110010000";
WHEN "011000" => p0_uid265_constMult_q <= "010000101000101011001000111111001110111010101101110011010000000";
WHEN "011001" => p0_uid265_constMult_q <= "010001010101000010010001010111001100110111110101000010101110000";
WHEN "011010" => p0_uid265_constMult_q <= "010010000001011001011001101111001010110100111100010010001100000";
WHEN "011011" => p0_uid265_constMult_q <= "010010101101110000100010000111001000110010000011100001101010000";
WHEN "011100" => p0_uid265_constMult_q <= "010011011010000111101010011111000110101111001010110001001000000";
WHEN "011101" => p0_uid265_constMult_q <= "010100000110011110110010110111000100101100010010000000100110000";
WHEN "011110" => p0_uid265_constMult_q <= "010100110010110101111011001111000010101001011001010000000100000";
WHEN "011111" => p0_uid265_constMult_q <= "010101011111001101000011100111000000100110100000011111100010000";
WHEN "100000" => p0_uid265_constMult_q <= "010110001011100100001011111110111110100011100111101111000000000";
WHEN "100001" => p0_uid265_constMult_q <= "010110110111111011010100010110111100100000101110111110011110000";
WHEN "100010" => p0_uid265_constMult_q <= "010111100100010010011100101110111010011101110110001101111100000";
WHEN "100011" => p0_uid265_constMult_q <= "011000010000101001100101000110111000011010111101011101011010000";
WHEN "100100" => p0_uid265_constMult_q <= "011000111101000000101101011110110110011000000100101100111000000";
WHEN "100101" => p0_uid265_constMult_q <= "011001101001010111110101110110110100010101001011111100010110000";
WHEN "100110" => p0_uid265_constMult_q <= "011010010101101110111110001110110010010010010011001011110100000";
WHEN "100111" => p0_uid265_constMult_q <= "011011000010000110000110100110110000001111011010011011010010000";
WHEN "101000" => p0_uid265_constMult_q <= "011011101110011101001110111110101110001100100001101010110000000";
WHEN "101001" => p0_uid265_constMult_q <= "011100011010110100010111010110101100001001101000111010001110000";
WHEN "101010" => p0_uid265_constMult_q <= "011101000111001011011111101110101010000110110000001001101100000";
WHEN "101011" => p0_uid265_constMult_q <= "011101110011100010101000000110101000000011110111011001001010000";
WHEN "101100" => p0_uid265_constMult_q <= "011110011111111001110000011110100110000000111110101000101000000";
WHEN "101101" => p0_uid265_constMult_q <= "011111001100010000111000110110100011111110000101111000000110000";
WHEN "101110" => p0_uid265_constMult_q <= "011111111000101000000001001110100001111011001101000111100100000";
WHEN "101111" => p0_uid265_constMult_q <= "100000100100111111001001100110011111111000010100010111000010000";
WHEN "110000" => p0_uid265_constMult_q <= "100001010001010110010001111110011101110101011011100110100000000";
WHEN "110001" => p0_uid265_constMult_q <= "100001111101101101011010010110011011110010100010110101111110000";
WHEN "110010" => p0_uid265_constMult_q <= "100010101010000100100010101110011001101111101010000101011100000";
WHEN "110011" => p0_uid265_constMult_q <= "100011010110011011101011000110010111101100110001010100111010000";
WHEN "110100" => p0_uid265_constMult_q <= "100100000010110010110011011110010101101001111000100100011000000";
WHEN "110101" => p0_uid265_constMult_q <= "100100101111001001111011110110010011100110111111110011110110000";
WHEN "110110" => p0_uid265_constMult_q <= "100101011011100001000100001110010001100100000111000011010100000";
WHEN "110111" => p0_uid265_constMult_q <= "100110000111111000001100100110001111100001001110010010110010000";
WHEN "111000" => p0_uid265_constMult_q <= "100110110100001111010100111110001101011110010101100010010000000";
WHEN "111001" => p0_uid265_constMult_q <= "100111100000100110011101010110001011011011011100110001101110000";
WHEN "111010" => p0_uid265_constMult_q <= "101000001100111101100101101110001001011000100100000001001100000";
WHEN "111011" => p0_uid265_constMult_q <= "101000111001010100101110000110000111010101101011010000101010000";
WHEN "111100" => p0_uid265_constMult_q <= "101001100101101011110110011110000101010010110010100000001000000";
WHEN "111101" => p0_uid265_constMult_q <= "101010010010000010111110110110000011001111111001101111100110000";
WHEN "111110" => p0_uid265_constMult_q <= "101010111110011010000111001110000001001101000000111111000100000";
WHEN "111111" => p0_uid265_constMult_q <= "101011101010110001001111100101111111001010001000001110100010000";
WHEN OTHERS =>
p0_uid265_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv1_uid263_constMult(BITSELECT,262)@38
xv1_uid263_constMult_in <= e_uid84_fpLogE1pxTest_q(11 downto 0);
xv1_uid263_constMult_b <= xv1_uid263_constMult_in(11 downto 6);
--reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0(REG,614)@38
reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q <= xv1_uid263_constMult_b;
END IF;
END IF;
END PROCESS;
--p1_uid264_constMult(LOOKUP,263)@39
p1_uid264_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p1_uid264_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_xv1_uid263_constMult_0_to_p1_uid264_constMult_0_q) IS
WHEN "000000" => p1_uid264_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p1_uid264_constMult_q <= "000000101100010111001000010111111101111101000111001111011110000000000";
WHEN "000010" => p1_uid264_constMult_q <= "000001011000101110010000101111111011111010001110011110111100000000000";
WHEN "000011" => p1_uid264_constMult_q <= "000010000101000101011001000111111001110111010101101110011010000000000";
WHEN "000100" => p1_uid264_constMult_q <= "000010110001011100100001011111110111110100011100111101111000000000000";
WHEN "000101" => p1_uid264_constMult_q <= "000011011101110011101001110111110101110001100100001101010110000000000";
WHEN "000110" => p1_uid264_constMult_q <= "000100001010001010110010001111110011101110101011011100110100000000000";
WHEN "000111" => p1_uid264_constMult_q <= "000100110110100001111010100111110001101011110010101100010010000000000";
WHEN "001000" => p1_uid264_constMult_q <= "000101100010111001000010111111101111101000111001111011110000000000000";
WHEN "001001" => p1_uid264_constMult_q <= "000110001111010000001011010111101101100110000001001011001110000000000";
WHEN "001010" => p1_uid264_constMult_q <= "000110111011100111010011101111101011100011001000011010101100000000000";
WHEN "001011" => p1_uid264_constMult_q <= "000111100111111110011100000111101001100000001111101010001010000000000";
WHEN "001100" => p1_uid264_constMult_q <= "001000010100010101100100011111100111011101010110111001101000000000000";
WHEN "001101" => p1_uid264_constMult_q <= "001001000000101100101100110111100101011010011110001001000110000000000";
WHEN "001110" => p1_uid264_constMult_q <= "001001101101000011110101001111100011010111100101011000100100000000000";
WHEN "001111" => p1_uid264_constMult_q <= "001010011001011010111101100111100001010100101100101000000010000000000";
WHEN "010000" => p1_uid264_constMult_q <= "001011000101110010000101111111011111010001110011110111100000000000000";
WHEN "010001" => p1_uid264_constMult_q <= "001011110010001001001110010111011101001110111011000110111110000000000";
WHEN "010010" => p1_uid264_constMult_q <= "001100011110100000010110101111011011001100000010010110011100000000000";
WHEN "010011" => p1_uid264_constMult_q <= "001101001010110111011111000111011001001001001001100101111010000000000";
WHEN "010100" => p1_uid264_constMult_q <= "001101110111001110100111011111010111000110010000110101011000000000000";
WHEN "010101" => p1_uid264_constMult_q <= "001110100011100101101111110111010101000011011000000100110110000000000";
WHEN "010110" => p1_uid264_constMult_q <= "001111001111111100111000001111010011000000011111010100010100000000000";
WHEN "010111" => p1_uid264_constMult_q <= "001111111100010100000000100111010000111101100110100011110010000000000";
WHEN "011000" => p1_uid264_constMult_q <= "010000101000101011001000111111001110111010101101110011010000000000000";
WHEN "011001" => p1_uid264_constMult_q <= "010001010101000010010001010111001100110111110101000010101110000000000";
WHEN "011010" => p1_uid264_constMult_q <= "010010000001011001011001101111001010110100111100010010001100000000000";
WHEN "011011" => p1_uid264_constMult_q <= "010010101101110000100010000111001000110010000011100001101010000000000";
WHEN "011100" => p1_uid264_constMult_q <= "010011011010000111101010011111000110101111001010110001001000000000000";
WHEN "011101" => p1_uid264_constMult_q <= "010100000110011110110010110111000100101100010010000000100110000000000";
WHEN "011110" => p1_uid264_constMult_q <= "010100110010110101111011001111000010101001011001010000000100000000000";
WHEN "011111" => p1_uid264_constMult_q <= "010101011111001101000011100111000000100110100000011111100010000000000";
WHEN "100000" => p1_uid264_constMult_q <= "101001110100011011110100000001000001011100011000010001000000000000000";
WHEN "100001" => p1_uid264_constMult_q <= "101010100000110010111100011000111111011001011111100000011110000000000";
WHEN "100010" => p1_uid264_constMult_q <= "101011001101001010000100110000111101010110100110101111111100000000000";
WHEN "100011" => p1_uid264_constMult_q <= "101011111001100001001101001000111011010011101101111111011010000000000";
WHEN "100100" => p1_uid264_constMult_q <= "101100100101111000010101100000111001010000110101001110111000000000000";
WHEN "100101" => p1_uid264_constMult_q <= "101101010010001111011101111000110111001101111100011110010110000000000";
WHEN "100110" => p1_uid264_constMult_q <= "101101111110100110100110010000110101001011000011101101110100000000000";
WHEN "100111" => p1_uid264_constMult_q <= "101110101010111101101110101000110011001000001010111101010010000000000";
WHEN "101000" => p1_uid264_constMult_q <= "101111010111010100110111000000110001000101010010001100110000000000000";
WHEN "101001" => p1_uid264_constMult_q <= "110000000011101011111111011000101111000010011001011100001110000000000";
WHEN "101010" => p1_uid264_constMult_q <= "110000110000000011000111110000101100111111100000101011101100000000000";
WHEN "101011" => p1_uid264_constMult_q <= "110001011100011010010000001000101010111100100111111011001010000000000";
WHEN "101100" => p1_uid264_constMult_q <= "110010001000110001011000100000101000111001101111001010101000000000000";
WHEN "101101" => p1_uid264_constMult_q <= "110010110101001000100000111000100110110110110110011010000110000000000";
WHEN "101110" => p1_uid264_constMult_q <= "110011100001011111101001010000100100110011111101101001100100000000000";
WHEN "101111" => p1_uid264_constMult_q <= "110100001101110110110001101000100010110001000100111001000010000000000";
WHEN "110000" => p1_uid264_constMult_q <= "110100111010001101111010000000100000101110001100001000100000000000000";
WHEN "110001" => p1_uid264_constMult_q <= "110101100110100101000010011000011110101011010011010111111110000000000";
WHEN "110010" => p1_uid264_constMult_q <= "110110010010111100001010110000011100101000011010100111011100000000000";
WHEN "110011" => p1_uid264_constMult_q <= "110110111111010011010011001000011010100101100001110110111010000000000";
WHEN "110100" => p1_uid264_constMult_q <= "110111101011101010011011100000011000100010101001000110011000000000000";
WHEN "110101" => p1_uid264_constMult_q <= "111000011000000001100011111000010110011111110000010101110110000000000";
WHEN "110110" => p1_uid264_constMult_q <= "111001000100011000101100010000010100011100110111100101010100000000000";
WHEN "110111" => p1_uid264_constMult_q <= "111001110000101111110100101000010010011001111110110100110010000000000";
WHEN "111000" => p1_uid264_constMult_q <= "111010011101000110111101000000010000010111000110000100010000000000000";
WHEN "111001" => p1_uid264_constMult_q <= "111011001001011110000101011000001110010100001101010011101110000000000";
WHEN "111010" => p1_uid264_constMult_q <= "111011110101110101001101110000001100010001010100100011001100000000000";
WHEN "111011" => p1_uid264_constMult_q <= "111100100010001100010110001000001010001110011011110010101010000000000";
WHEN "111100" => p1_uid264_constMult_q <= "111101001110100011011110100000001000001011100011000010001000000000000";
WHEN "111101" => p1_uid264_constMult_q <= "111101111010111010100110111000000110001000101010010001100110000000000";
WHEN "111110" => p1_uid264_constMult_q <= "111110100111010001101111010000000100000101110001100001000100000000000";
WHEN "111111" => p1_uid264_constMult_q <= "111111010011101000110111101000000010000010111000110000100010000000000";
WHEN OTHERS =>
p1_uid264_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
--lev1_a0_uid266_constMult(ADD,265)@40
lev1_a0_uid266_constMult_a <= STD_LOGIC_VECTOR((70 downto 69 => p1_uid264_constMult_q(68)) & p1_uid264_constMult_q);
lev1_a0_uid266_constMult_b <= STD_LOGIC_VECTOR('0' & "0000000" & p0_uid265_constMult_q);
lev1_a0_uid266_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev1_a0_uid266_constMult_a) + SIGNED(lev1_a0_uid266_constMult_b));
lev1_a0_uid266_constMult_q <= lev1_a0_uid266_constMult_o(69 downto 0);
--sR_uid267_constMult(BITSELECT,266)@40
sR_uid267_constMult_in <= lev1_a0_uid266_constMult_q(68 downto 0);
sR_uid267_constMult_b <= sR_uid267_constMult_in(68 downto 2);
--reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2(REG,616)@40
reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q <= sR_uid267_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b(DELAY,747)@35
ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => branch3OrC_uid94_fpLogE1pxTest_q, xout => ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--addTermOne_uid105_fpLogE1pxTest(MUX,104)@41
addTermOne_uid105_fpLogE1pxTest_s <= ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q;
addTermOne_uid105_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
addTermOne_uid105_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE addTermOne_uid105_fpLogE1pxTest_s IS
WHEN "0" => addTermOne_uid105_fpLogE1pxTest_q <= reg_sR_uid267_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q;
WHEN "1" => addTermOne_uid105_fpLogE1pxTest_q <= wideZero_uid104_fpLogE1pxTest_q;
WHEN OTHERS => addTermOne_uid105_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid108_fpLogE1pxTest(ADD,107)@42
sumAHighB_uid108_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((67 downto 67 => addTermOne_uid105_fpLogE1pxTest_q(66)) & addTermOne_uid105_fpLogE1pxTest_q);
sumAHighB_uid108_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((67 downto 59 => reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q(58)) & reg_highBBits_uid107_fpLogE1pxTest_0_to_sumAHighB_uid108_fpLogE1pxTest_1_q);
sumAHighB_uid108_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid108_fpLogE1pxTest_a) + SIGNED(sumAHighB_uid108_fpLogE1pxTest_b));
sumAHighB_uid108_fpLogE1pxTest_q <= sumAHighB_uid108_fpLogE1pxTest_o(67 downto 0);
--lowRangeB_uid106_fpLogE1pxTest(BITSELECT,105)@41
lowRangeB_uid106_fpLogE1pxTest_in <= postPEMul_uid103_fpLogE1pxTest_result_add_1_0_q(50 downto 0);
lowRangeB_uid106_fpLogE1pxTest_b <= lowRangeB_uid106_fpLogE1pxTest_in(50 downto 0);
--reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0(REG,618)@41
reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q <= "000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q <= lowRangeB_uid106_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--finalSum_uid106_uid109_fpLogE1pxTest(BITJOIN,108)@42
finalSum_uid106_uid109_fpLogE1pxTest_q <= sumAHighB_uid108_fpLogE1pxTest_q & reg_lowRangeB_uid106_fpLogE1pxTest_0_to_finalSum_uid106_uid109_fpLogE1pxTest_0_q;
--FullSumAB118_uid110_fpLogE1pxTest(BITSELECT,109)@42
FullSumAB118_uid110_fpLogE1pxTest_in <= finalSum_uid106_uid109_fpLogE1pxTest_q;
FullSumAB118_uid110_fpLogE1pxTest_b <= FullSumAB118_uid110_fpLogE1pxTest_in(118 downto 118);
--ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b(DELAY,759)@42
ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => FullSumAB118_uid110_fpLogE1pxTest_b, xout => ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalSumOneComp_uid112_fpLogE1pxTest(LOGICAL,111)@42
finalSumOneComp_uid112_fpLogE1pxTest_a <= finalSum_uid106_uid109_fpLogE1pxTest_q;
finalSumOneComp_uid112_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((118 downto 1 => FullSumAB118_uid110_fpLogE1pxTest_b(0)) & FullSumAB118_uid110_fpLogE1pxTest_b);
finalSumOneComp_uid112_fpLogE1pxTest_q_i <= finalSumOneComp_uid112_fpLogE1pxTest_a xor finalSumOneComp_uid112_fpLogE1pxTest_b;
finalSumOneComp_uid112_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 119, depth => 1)
PORT MAP (xout => finalSumOneComp_uid112_fpLogE1pxTest_q, xin => finalSumOneComp_uid112_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--finalSumAbs_uid113_fpLogE1pxTest(ADD,112)@43
finalSumAbs_uid113_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((119 downto 119 => finalSumOneComp_uid112_fpLogE1pxTest_q(118)) & finalSumOneComp_uid112_fpLogE1pxTest_q);
finalSumAbs_uid113_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((119 downto 1 => ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q(0)) & ld_FullSumAB118_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q);
finalSumAbs_uid113_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(finalSumAbs_uid113_fpLogE1pxTest_a) + SIGNED(finalSumAbs_uid113_fpLogE1pxTest_b));
finalSumAbs_uid113_fpLogE1pxTest_q <= finalSumAbs_uid113_fpLogE1pxTest_o(119 downto 0);
--rVStage_uid320_countZ_uid114_fpLogE1pxTest(BITSELECT,319)@43
rVStage_uid320_countZ_uid114_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q;
rVStage_uid320_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid320_countZ_uid114_fpLogE1pxTest_in(119 downto 56);
--reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1(REG,619)@43
reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q <= "0000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid320_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid321_countZ_uid114_fpLogE1pxTest(LOGICAL,320)@44
vCount_uid321_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid320_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid321_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid321_countZ_uid114_fpLogE1pxTest_b <= zs_uid319_countZ_uid114_fpLogE1pxTest_q;
vCount_uid321_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid321_countZ_uid114_fpLogE1pxTest_a = vCount_uid321_countZ_uid114_fpLogE1pxTest_b else "0";
--reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6(REG,633)@44
reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q <= vCount_uid321_countZ_uid114_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g(DELAY,1016)@45
ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q, xout => ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid323_countZ_uid114_fpLogE1pxTest(BITSELECT,322)@43
vStage_uid323_countZ_uid114_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(55 downto 0);
vStage_uid323_countZ_uid114_fpLogE1pxTest_b <= vStage_uid323_countZ_uid114_fpLogE1pxTest_in(55 downto 0);
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b(DELAY,974)@43
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 56, depth => 1 )
PORT MAP ( xin => vStage_uid323_countZ_uid114_fpLogE1pxTest_b, xout => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid322_countZ_uid114_fpLogE1pxTest(CONSTANT,321)
mO_uid322_countZ_uid114_fpLogE1pxTest_q <= "11111111";
--cStage_uid324_countZ_uid114_fpLogE1pxTest(BITJOIN,323)@44
cStage_uid324_countZ_uid114_fpLogE1pxTest_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q & mO_uid322_countZ_uid114_fpLogE1pxTest_q;
--ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c(DELAY,976)@43
ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid320_countZ_uid114_fpLogE1pxTest_b, xout => ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid326_countZ_uid114_fpLogE1pxTest(MUX,325)@44
vStagei_uid326_countZ_uid114_fpLogE1pxTest_s <= vCount_uid321_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid326_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid326_countZ_uid114_fpLogE1pxTest_s, en, ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q, cStage_uid324_countZ_uid114_fpLogE1pxTest_q)
BEGIN
CASE vStagei_uid326_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid326_countZ_uid114_fpLogE1pxTest_q <= ld_rVStage_uid320_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid326_countZ_uid114_fpLogE1pxTest_c_q;
WHEN "1" => vStagei_uid326_countZ_uid114_fpLogE1pxTest_q <= cStage_uid324_countZ_uid114_fpLogE1pxTest_q;
WHEN OTHERS => vStagei_uid326_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid328_countZ_uid114_fpLogE1pxTest(BITSELECT,327)@44
rVStage_uid328_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid326_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid328_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid328_countZ_uid114_fpLogE1pxTest_in(63 downto 32);
--reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1(REG,620)@44
reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid328_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid329_countZ_uid114_fpLogE1pxTest(LOGICAL,328)@45
vCount_uid329_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid329_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid329_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid329_countZ_uid114_fpLogE1pxTest_a = vCount_uid329_countZ_uid114_fpLogE1pxTest_b else "0";
--ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a(DELAY,1315)@45
ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid329_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5(REG,632)@47
reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q <= ld_vCount_uid329_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid330_countZ_uid114_fpLogE1pxTest(BITSELECT,329)@44
vStage_uid330_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid326_countZ_uid114_fpLogE1pxTest_q(31 downto 0);
vStage_uid330_countZ_uid114_fpLogE1pxTest_b <= vStage_uid330_countZ_uid114_fpLogE1pxTest_in(31 downto 0);
--reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3(REG,622)@44
reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid330_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid332_countZ_uid114_fpLogE1pxTest(MUX,331)@45
vStagei_uid332_countZ_uid114_fpLogE1pxTest_s <= vCount_uid329_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid332_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid332_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q, reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid332_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid332_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid328_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid329_countZ_uid114_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid332_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid330_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid332_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid332_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid334_countZ_uid114_fpLogE1pxTest(BITSELECT,333)@45
rVStage_uid334_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid332_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid334_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid334_countZ_uid114_fpLogE1pxTest_in(31 downto 16);
--reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1(REG,623)@45
reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid334_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid335_countZ_uid114_fpLogE1pxTest(LOGICAL,334)@46
vCount_uid335_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid335_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid335_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid335_countZ_uid114_fpLogE1pxTest_a = vCount_uid335_countZ_uid114_fpLogE1pxTest_b else "0";
--ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a(DELAY,1314)@46
ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid335_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4(REG,631)@47
reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q <= ld_vCount_uid335_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid336_countZ_uid114_fpLogE1pxTest(BITSELECT,335)@45
vStage_uid336_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid332_countZ_uid114_fpLogE1pxTest_q(15 downto 0);
vStage_uid336_countZ_uid114_fpLogE1pxTest_b <= vStage_uid336_countZ_uid114_fpLogE1pxTest_in(15 downto 0);
--reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3(REG,625)@45
reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid336_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid338_countZ_uid114_fpLogE1pxTest(MUX,337)@46
vStagei_uid338_countZ_uid114_fpLogE1pxTest_s <= vCount_uid335_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid338_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid338_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q, reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid338_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid338_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid334_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid335_countZ_uid114_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid338_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid336_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid338_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid338_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid340_countZ_uid114_fpLogE1pxTest(BITSELECT,339)@46
rVStage_uid340_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid338_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid340_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid340_countZ_uid114_fpLogE1pxTest_in(15 downto 8);
--vCount_uid341_countZ_uid114_fpLogE1pxTest(LOGICAL,340)@46
vCount_uid341_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid340_countZ_uid114_fpLogE1pxTest_b;
vCount_uid341_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid341_countZ_uid114_fpLogE1pxTest_q_i <= "1" when vCount_uid341_countZ_uid114_fpLogE1pxTest_a = vCount_uid341_countZ_uid114_fpLogE1pxTest_b else "0";
vCount_uid341_countZ_uid114_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid341_countZ_uid114_fpLogE1pxTest_q, xin => vCount_uid341_countZ_uid114_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d(DELAY,1013)@47
ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid341_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid342_countZ_uid114_fpLogE1pxTest(BITSELECT,341)@46
vStage_uid342_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid338_countZ_uid114_fpLogE1pxTest_q(7 downto 0);
vStage_uid342_countZ_uid114_fpLogE1pxTest_b <= vStage_uid342_countZ_uid114_fpLogE1pxTest_in(7 downto 0);
--reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3(REG,627)@46
reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid342_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2(REG,626)@46
reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q <= rVStage_uid340_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid344_countZ_uid114_fpLogE1pxTest(MUX,343)@47
vStagei_uid344_countZ_uid114_fpLogE1pxTest_s <= vCount_uid341_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid344_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid344_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q, reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid344_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid344_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid340_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid344_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid342_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid344_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid344_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid346_countZ_uid114_fpLogE1pxTest(BITSELECT,345)@47
rVStage_uid346_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid344_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid346_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid346_countZ_uid114_fpLogE1pxTest_in(7 downto 4);
--vCount_uid347_countZ_uid114_fpLogE1pxTest(LOGICAL,346)@47
vCount_uid347_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid346_countZ_uid114_fpLogE1pxTest_b;
vCount_uid347_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid347_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid347_countZ_uid114_fpLogE1pxTest_a = vCount_uid347_countZ_uid114_fpLogE1pxTest_b else "0";
--reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2(REG,630)@47
reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q <= vCount_uid347_countZ_uid114_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid348_countZ_uid114_fpLogE1pxTest(BITSELECT,347)@47
vStage_uid348_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid344_countZ_uid114_fpLogE1pxTest_q(3 downto 0);
vStage_uid348_countZ_uid114_fpLogE1pxTest_b <= vStage_uid348_countZ_uid114_fpLogE1pxTest_in(3 downto 0);
--vStagei_uid350_countZ_uid114_fpLogE1pxTest(MUX,349)@47
vStagei_uid350_countZ_uid114_fpLogE1pxTest_s <= vCount_uid347_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid350_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid350_countZ_uid114_fpLogE1pxTest_s, en, rVStage_uid346_countZ_uid114_fpLogE1pxTest_b, vStage_uid348_countZ_uid114_fpLogE1pxTest_b)
BEGIN
CASE vStagei_uid350_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid350_countZ_uid114_fpLogE1pxTest_q <= rVStage_uid346_countZ_uid114_fpLogE1pxTest_b;
WHEN "1" => vStagei_uid350_countZ_uid114_fpLogE1pxTest_q <= vStage_uid348_countZ_uid114_fpLogE1pxTest_b;
WHEN OTHERS => vStagei_uid350_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid352_countZ_uid114_fpLogE1pxTest(BITSELECT,351)@47
rVStage_uid352_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid350_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid352_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid352_countZ_uid114_fpLogE1pxTest_in(3 downto 2);
--vCount_uid353_countZ_uid114_fpLogE1pxTest(LOGICAL,352)@47
vCount_uid353_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid352_countZ_uid114_fpLogE1pxTest_b;
vCount_uid353_countZ_uid114_fpLogE1pxTest_b <= z2_uid100_fpLogE1pxTest_q;
vCount_uid353_countZ_uid114_fpLogE1pxTest_q_i <= "1" when vCount_uid353_countZ_uid114_fpLogE1pxTest_a = vCount_uid353_countZ_uid114_fpLogE1pxTest_b else "0";
vCount_uid353_countZ_uid114_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid353_countZ_uid114_fpLogE1pxTest_q, xin => vCount_uid353_countZ_uid114_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid354_countZ_uid114_fpLogE1pxTest(BITSELECT,353)@47
vStage_uid354_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid350_countZ_uid114_fpLogE1pxTest_q(1 downto 0);
vStage_uid354_countZ_uid114_fpLogE1pxTest_b <= vStage_uid354_countZ_uid114_fpLogE1pxTest_in(1 downto 0);
--reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3(REG,629)@47
reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid354_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2(REG,628)@47
reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q <= rVStage_uid352_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid356_countZ_uid114_fpLogE1pxTest(MUX,355)@48
vStagei_uid356_countZ_uid114_fpLogE1pxTest_s <= vCount_uid353_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid356_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid356_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q, reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid356_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid356_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid352_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid356_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid354_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid356_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid356_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid358_countZ_uid114_fpLogE1pxTest(BITSELECT,357)@48
rVStage_uid358_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid356_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid358_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid358_countZ_uid114_fpLogE1pxTest_in(1 downto 1);
--vCount_uid359_countZ_uid114_fpLogE1pxTest(LOGICAL,358)@48
vCount_uid359_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid358_countZ_uid114_fpLogE1pxTest_b;
vCount_uid359_countZ_uid114_fpLogE1pxTest_b <= GND_q;
vCount_uid359_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid359_countZ_uid114_fpLogE1pxTest_a = vCount_uid359_countZ_uid114_fpLogE1pxTest_b else "0";
--r_uid360_countZ_uid114_fpLogE1pxTest(BITJOIN,359)@48
r_uid360_countZ_uid114_fpLogE1pxTest_q <= ld_reg_vCount_uid321_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_6_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_g_q & reg_vCount_uid329_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_5_q & reg_vCount_uid335_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_4_q & ld_vCount_uid341_countZ_uid114_fpLogE1pxTest_q_to_r_uid360_countZ_uid114_fpLogE1pxTest_d_q & reg_vCount_uid347_countZ_uid114_fpLogE1pxTest_0_to_r_uid360_countZ_uid114_fpLogE1pxTest_2_q & vCount_uid353_countZ_uid114_fpLogE1pxTest_q & vCount_uid359_countZ_uid114_fpLogE1pxTest_q;
--cstMSBFinalSumPBias_uid116_fpLogE1pxTest(CONSTANT,115)
cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q <= "010000001100";
--expRExt0_uid117_fpLogE1pxTest(SUB,116)@48
expRExt0_uid117_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q);
expRExt0_uid117_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000" & r_uid360_countZ_uid114_fpLogE1pxTest_q);
expRExt0_uid117_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRExt0_uid117_fpLogE1pxTest_a) - UNSIGNED(expRExt0_uid117_fpLogE1pxTest_b));
expRExt0_uid117_fpLogE1pxTest_q <= expRExt0_uid117_fpLogE1pxTest_o(12 downto 0);
--reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0(REG,647)@48
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q <= expRExt0_uid117_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--expRExt1_uid119_fpLogE1pxTest(SUB,118)@49
expRExt1_uid119_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((13 downto 13 => reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q(12)) & reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q);
expRExt1_uid119_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((13 downto 7 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q(6)) & ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q);
expRExt1_uid119_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(expRExt1_uid119_fpLogE1pxTest_a) - SIGNED(expRExt1_uid119_fpLogE1pxTest_b));
expRExt1_uid119_fpLogE1pxTest_q <= expRExt1_uid119_fpLogE1pxTest_o(13 downto 0);
--expRExt1Red_uid120_fpLogE1pxTest(BITSELECT,119)@49
expRExt1Red_uid120_fpLogE1pxTest_in <= expRExt1_uid119_fpLogE1pxTest_q(12 downto 0);
expRExt1Red_uid120_fpLogE1pxTest_b <= expRExt1Red_uid120_fpLogE1pxTest_in(12 downto 0);
--ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c(DELAY,767)@48
ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => expRExt0_uid117_fpLogE1pxTest_q, xout => ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b(DELAY,766)@35
ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => branch3OrC_uid94_fpLogE1pxTest_q, xout => ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRExt_uid121_fpLogE1pxTest(MUX,120)@49
expRExt_uid121_fpLogE1pxTest_s <= ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q;
expRExt_uid121_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRExt_uid121_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRExt_uid121_fpLogE1pxTest_s IS
WHEN "0" => expRExt_uid121_fpLogE1pxTest_q <= ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q;
WHEN "1" => expRExt_uid121_fpLogE1pxTest_q <= expRExt1Red_uid120_fpLogE1pxTest_b;
WHEN OTHERS => expRExt_uid121_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest(BITSELECT,396)@50
LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q(118 downto 0);
LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_in(118 downto 0);
--leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest(BITJOIN,397)@50
leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage2118dto0_uid397_normVal_uid115_fpLogE1pxTest_b & GND_q;
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1668)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1669)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1670)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--X23dto0_uid370_normVal_uid115_fpLogE1pxTest(BITSELECT,369)@43
X23dto0_uid370_normVal_uid115_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(23 downto 0);
X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b <= X23dto0_uid370_normVal_uid115_fpLogE1pxTest_in(23 downto 0);
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg(DELAY,1660)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b, xout => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,1661)
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_inputreg_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 1,
numwords_a => 2,
width_b => 24,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(23 downto 0);
--leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest(CONSTANT,368)
leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest(BITJOIN,370)@47
leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_q <= ld_X23dto0_uid370_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & leftShiftStage0Idx3Pad96_uid369_normVal_uid115_fpLogE1pxTest_q;
--reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5(REG,637)@47
reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q <= leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1657)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1658)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1659)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,1650)
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid324_countZ_uid114_fpLogE1pxTest_b_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 56,
widthad_a => 1,
numwords_a => 2,
width_b => 56,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(55 downto 0);
--leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest(BITJOIN,367)@47
leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_q <= ld_vStage_uid323_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & zs_uid319_countZ_uid114_fpLogE1pxTest_q;
--reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4(REG,636)@47
reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q <= leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1646)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1647)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1648)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--X87dto0_uid364_normVal_uid115_fpLogE1pxTest(BITSELECT,363)@43
X87dto0_uid364_normVal_uid115_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(87 downto 0);
X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b <= X87dto0_uid364_normVal_uid115_fpLogE1pxTest_in(87 downto 0);
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg(DELAY,1638)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 88, depth => 1 )
PORT MAP ( xin => X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b, xout => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,1639)
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_inputreg_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 88,
widthad_a => 1,
numwords_a => 2,
width_b => 88,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(87 downto 0);
--leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest(BITJOIN,364)@47
leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_q <= ld_X87dto0_uid364_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & rightShiftStage0Idx2Pad32_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3(REG,635)@47
reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q <= leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor(LOGICAL,1679)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_b <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_q <= not (ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_a or ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_b);
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena(REG,1680)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_nor_q = "1") THEN
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd(LOGICAL,1681)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_a <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_b <= en;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_q <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_a and ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_b;
--reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2(REG,634)@43
reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q <= finalSumAbs_uid113_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg(DELAY,1671)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 120, depth => 1 )
PORT MAP ( xin => reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q, xout => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem(DUALMEM,1672)
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_inputreg_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 120,
widthad_a => 1,
numwords_a => 2,
width_b => 120,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq,
address_a => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa,
data_a => ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia
);
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0 <= areset;
ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq(119 downto 0);
--leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest(BITSELECT,371)@48
leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q;
leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_in(6 downto 5);
--leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest(MUX,372)@48
leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s <= leftShiftStageSel6Dto5_uid372_normVal_uid115_fpLogE1pxTest_b;
leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s, en, ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q, reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q, reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q, reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= ld_reg_finalSumAbs_uid113_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_2_q_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0Idx1_uid365_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0Idx2_uid368_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0Idx3_uid371_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest(BITSELECT,380)@48
LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q(95 downto 0);
LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_in(95 downto 0);
--leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest(CONSTANT,379)
leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest_q <= "000000000000000000000000";
--leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest(BITJOIN,381)@48
leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage095dto0_uid381_normVal_uid115_fpLogE1pxTest_b & leftShiftStage1Idx3Pad24_uid380_normVal_uid115_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5(REG,642)@48
reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q <= leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest(BITSELECT,377)@48
LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q(103 downto 0);
LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_in(103 downto 0);
--leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest(BITJOIN,378)@48
leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage0103dto0_uid378_normVal_uid115_fpLogE1pxTest_b & rightShiftStage0Idx1Pad16_uid157_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4(REG,641)@48
reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q <= leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest(BITSELECT,374)@48
LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q(111 downto 0);
LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_in(111 downto 0);
--leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest(BITJOIN,375)@48
leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage0111dto0_uid375_normVal_uid115_fpLogE1pxTest_b & rightShiftStage1Idx2Pad8_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3(REG,640)@48
reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q <= leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2(REG,639)@48
reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q <= leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest(BITSELECT,382)@48
leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1(REG,638)@48
reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q <= leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest(MUX,383)@49
leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s <= reg_leftShiftStageSel4Dto3_uid383_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_1_q;
leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s, en, reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q, reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q, reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q, reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0_uid373_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx1_uid376_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx2_uid379_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx3_uid382_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest(BITSELECT,391)@49
LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q(113 downto 0);
LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_in(113 downto 0);
--ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b(DELAY,1045)@49
ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 114, depth => 1 )
PORT MAP ( xin => LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest(CONSTANT,390)
leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest_q <= "000000";
--leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest(BITJOIN,392)@50
leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage1113dto0_uid392_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_b_q & leftShiftStage2Idx3Pad6_uid391_normVal_uid115_fpLogE1pxTest_q;
--LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest(BITSELECT,388)@49
LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q(115 downto 0);
LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_in(115 downto 0);
--ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b(DELAY,1043)@49
ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 116, depth => 1 )
PORT MAP ( xin => LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest(BITJOIN,389)@50
leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage1115dto0_uid389_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_b_q & rightShiftStage1Idx1Pad4_uid168_fracXRSExt_uid36_fpLogE1pxTest_q;
--LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest(BITSELECT,385)@49
LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q(117 downto 0);
LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_in(117 downto 0);
--ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b(DELAY,1041)@49
ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 118, depth => 1 )
PORT MAP ( xin => LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest(BITJOIN,386)@50
leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage1117dto0_uid386_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_b_q & z2_uid100_fpLogE1pxTest_q;
--reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2(REG,644)@49
reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q <= leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest(BITSELECT,393)@48
leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1(REG,643)@48
reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q <= leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b(DELAY,1047)@49
ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q, xout => ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest(MUX,394)@50
leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s <= ld_reg_leftShiftStageSel2Dto1_uid394_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_1_q_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_b_q;
leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s, en, reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q, leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q, leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q, leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1_uid384_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx1_uid387_normVal_uid115_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx2_uid390_normVal_uid115_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx3_uid393_normVal_uid115_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest(BITSELECT,398)@48
leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_in <= r_uid360_countZ_uid114_fpLogE1pxTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b(DELAY,1055)@48
ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b, xout => ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest(MUX,399)@50
leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s <= ld_leftShiftStageSel0Dto0_uid399_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_b_q;
leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s, en, leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q, leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_s IS
WHEN "0" => leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2_uid395_normVal_uid115_fpLogE1pxTest_q;
WHEN "1" => leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage3Idx1_uid398_normVal_uid115_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracR_uid122_fpLogE1pxTest(BITSELECT,121)@50
fracR_uid122_fpLogE1pxTest_in <= leftShiftStage3_uid400_normVal_uid115_fpLogE1pxTest_q(118 downto 0);
fracR_uid122_fpLogE1pxTest_b <= fracR_uid122_fpLogE1pxTest_in(118 downto 66);
--expFracConc_uid123_fpLogE1pxTest(BITJOIN,122)@50
expFracConc_uid123_fpLogE1pxTest_q <= expRExt_uid121_fpLogE1pxTest_q & fracR_uid122_fpLogE1pxTest_b;
--reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0(REG,648)@50
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q <= expFracConc_uid123_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--expFracPostRnd_uid124_fpLogE1pxTest(ADD,123)@51
expFracPostRnd_uid124_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q);
expFracPostRnd_uid124_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("000000000000000000000000000000000000000000000000000000000000000000" & VCC_q);
expFracPostRnd_uid124_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracPostRnd_uid124_fpLogE1pxTest_a) + UNSIGNED(expFracPostRnd_uid124_fpLogE1pxTest_b));
expFracPostRnd_uid124_fpLogE1pxTest_q <= expFracPostRnd_uid124_fpLogE1pxTest_o(66 downto 0);
--expR_uid127_fpLogE1pxTest(BITSELECT,126)@51
expR_uid127_fpLogE1pxTest_in <= expFracPostRnd_uid124_fpLogE1pxTest_q(63 downto 0);
expR_uid127_fpLogE1pxTest_b <= expR_uid127_fpLogE1pxTest_in(63 downto 53);
--reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2(REG,652)@51
reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q <= expR_uid127_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor(LOGICAL,1522)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_b <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_q <= not (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_a or ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_b);
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top(CONSTANT,1518)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q <= "0110000";
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp(LOGICAL,1519)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_a <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q);
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_q <= "1" when ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_a = ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_b else "0";
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg(REG,1520)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena(REG,1523)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_nor_q = "1") THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd(LOGICAL,1524)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b <= en;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a and ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b;
--reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1(REG,649)@0
reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q <= resIsX_uid62_fpLogE1pxTest_c;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg(DELAY,1512)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q, xout => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt(COUNTER,1514)
-- every=1, low=0, high=48, step=1, init=1
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i = 47 THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i - 48;
ELSE
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i,6));
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg(REG,1515)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux(MUX,1516)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s, ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q, ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem(DUALMEM,1513)
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 49,
width_b => 1,
widthad_b => 6,
numwords_b => 49,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia
);
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq(0 downto 0);
--expR_uid128_fpLogE1pxTest(MUX,127)@52
expR_uid128_fpLogE1pxTest_s <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q;
expR_uid128_fpLogE1pxTest: PROCESS (expR_uid128_fpLogE1pxTest_s, en, reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q, ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q)
BEGIN
CASE expR_uid128_fpLogE1pxTest_s IS
WHEN "0" => expR_uid128_fpLogE1pxTest_q <= reg_expR_uid127_fpLogE1pxTest_0_to_expR_uid128_fpLogE1pxTest_2_q;
WHEN "1" => expR_uid128_fpLogE1pxTest_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q;
WHEN OTHERS => expR_uid128_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor(LOGICAL,1559)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_b <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_q <= not (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_a or ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_b);
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top(CONSTANT,1555)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top_q <= "0101110";
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp(LOGICAL,1556)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_a <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_mem_top_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q);
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_q <= "1" when ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_a = ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_b else "0";
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg(REG,1557)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena(REG,1560)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_nor_q = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd(LOGICAL,1561)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_a <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_sticky_ena_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_b <= en;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_a and ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_b;
--xM1_uid131_fpLogE1pxTest(LOGICAL,130)@0
xM1_uid131_fpLogE1pxTest_a <= a;
xM1_uid131_fpLogE1pxTest_b <= mO_uid130_fpLogE1pxTest_q;
xM1_uid131_fpLogE1pxTest_q <= "1" when xM1_uid131_fpLogE1pxTest_a = xM1_uid131_fpLogE1pxTest_b else "0";
--ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b(DELAY,786)@0
ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xM1_uid131_fpLogE1pxTest_q, xout => ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excRInf0_uid134_fpLogE1pxTest(LOGICAL,133)@1
excRInf0_uid134_fpLogE1pxTest_a <= exc_R_uid30_fpLogE1pxTest_q;
excRInf0_uid134_fpLogE1pxTest_b <= ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q;
excRInf0_uid134_fpLogE1pxTest_q_i <= excRInf0_uid134_fpLogE1pxTest_a and excRInf0_uid134_fpLogE1pxTest_b;
excRInf0_uid134_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => excRInf0_uid134_fpLogE1pxTest_q, xin => excRInf0_uid134_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a(DELAY,787)@0
ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => branch11_uid64_fpLogE1pxTest_q, xout => ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--posInf_uid136_fpLogE1pxTest(LOGICAL,135)@1
posInf_uid136_fpLogE1pxTest_a <= ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q;
posInf_uid136_fpLogE1pxTest_b <= exc_I_uid24_fpLogE1pxTest_q;
posInf_uid136_fpLogE1pxTest_q_i <= posInf_uid136_fpLogE1pxTest_a and posInf_uid136_fpLogE1pxTest_b;
posInf_uid136_fpLogE1pxTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => posInf_uid136_fpLogE1pxTest_q, xin => posInf_uid136_fpLogE1pxTest_q_i, clk => clk, ena => en(0), aclr => areset);
--excRInf0_uid137_fpLogE1pxTest(LOGICAL,136)@2
excRInf0_uid137_fpLogE1pxTest_a <= posInf_uid136_fpLogE1pxTest_q;
excRInf0_uid137_fpLogE1pxTest_b <= excRInf0_uid134_fpLogE1pxTest_q;
excRInf0_uid137_fpLogE1pxTest_q <= excRInf0_uid137_fpLogE1pxTest_a or excRInf0_uid137_fpLogE1pxTest_b;
--reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0(REG,492)@1
reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q <= ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q;
END IF;
END IF;
END PROCESS;
--concExc_uid143_fpLogE1pxTest(BITJOIN,142)@2
concExc_uid143_fpLogE1pxTest_q <= excRNaN_uid140_fpLogE1pxTest_q & excRInf0_uid137_fpLogE1pxTest_q & reg_expXIsZero_uid19_fpLogE1pxTest_0_to_concExc_uid143_fpLogE1pxTest_0_q;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg(DELAY,1549)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => concExc_uid143_fpLogE1pxTest_q, xout => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt(COUNTER,1551)
-- every=1, low=0, high=46, step=1, init=1
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i = 45 THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i - 46;
ELSE
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_i,6));
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg(REG,1552)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux(MUX,1553)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s, ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q, ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem(DUALMEM,1550)
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ia <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_inputreg_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_aa <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdreg_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ab <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_rdmux_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 6,
numwords_a => 47,
width_b => 3,
widthad_b => 6,
numwords_b => 47,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_ia
);
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_iq(2 downto 0);
--excREnc_uid144_fpLogE1pxTest(LOOKUP,143)@51
excREnc_uid144_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
excREnc_uid144_fpLogE1pxTest_q <= "01";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_concExc_uid143_fpLogE1pxTest_q_to_excREnc_uid144_fpLogE1pxTest_a_replace_mem_q) IS
WHEN "000" => excREnc_uid144_fpLogE1pxTest_q <= "01";
WHEN "001" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "010" => excREnc_uid144_fpLogE1pxTest_q <= "10";
WHEN "011" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "100" => excREnc_uid144_fpLogE1pxTest_q <= "11";
WHEN "101" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "110" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "111" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN OTHERS =>
excREnc_uid144_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRPostExc_uid152_fpLogE1pxTest(MUX,151)@52
expRPostExc_uid152_fpLogE1pxTest_s <= excREnc_uid144_fpLogE1pxTest_q;
expRPostExc_uid152_fpLogE1pxTest: PROCESS (expRPostExc_uid152_fpLogE1pxTest_s, en, cstAllZWE_uid17_fpLogE1pxTest_q, expR_uid128_fpLogE1pxTest_q, cstAllOWE_uid15_fpLogE1pxTest_q, cstAllOWE_uid15_fpLogE1pxTest_q)
BEGIN
CASE expRPostExc_uid152_fpLogE1pxTest_s IS
WHEN "00" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllZWE_uid17_fpLogE1pxTest_q;
WHEN "01" => expRPostExc_uid152_fpLogE1pxTest_q <= expR_uid128_fpLogE1pxTest_q;
WHEN "10" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllOWE_uid15_fpLogE1pxTest_q;
WHEN "11" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllOWE_uid15_fpLogE1pxTest_q;
WHEN OTHERS => expRPostExc_uid152_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid145_fpLogE1pxTest(CONSTANT,144)
oneFracRPostExc2_uid145_fpLogE1pxTest_q <= "0000000000000000000000000000000000000000000000000001";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor(LOGICAL,1533)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp(LOGICAL,1530)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q);
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg(REG,1531)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena(REG,1534)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd(LOGICAL,1535)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem(DUALMEM,1526)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 6,
numwords_a => 49,
width_b => 52,
widthad_b => 6,
numwords_b => 49,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => en(0),
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq(51 downto 0);
--fracR0_uid125_fpLogE1pxTest(BITSELECT,124)@51
fracR0_uid125_fpLogE1pxTest_in <= expFracPostRnd_uid124_fpLogE1pxTest_q(52 downto 0);
fracR0_uid125_fpLogE1pxTest_b <= fracR0_uid125_fpLogE1pxTest_in(52 downto 1);
--reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2(REG,650)@51
reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q <= fracR0_uid125_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--fracR_uid126_fpLogE1pxTest(MUX,125)@52
fracR_uid126_fpLogE1pxTest_s <= ld_reg_resIsX_uid62_fpLogE1pxTest_1_to_fracR_uid126_fpLogE1pxTest_1_q_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q;
fracR_uid126_fpLogE1pxTest: PROCESS (fracR_uid126_fpLogE1pxTest_s, en, reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q, ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q)
BEGIN
CASE fracR_uid126_fpLogE1pxTest_s IS
WHEN "0" => fracR_uid126_fpLogE1pxTest_q <= reg_fracR0_uid125_fpLogE1pxTest_0_to_fracR_uid126_fpLogE1pxTest_2_q;
WHEN "1" => fracR_uid126_fpLogE1pxTest_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q;
WHEN OTHERS => fracR_uid126_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPostExc_uid148_fpLogE1pxTest(MUX,147)@52
fracRPostExc_uid148_fpLogE1pxTest_s <= excREnc_uid144_fpLogE1pxTest_q;
fracRPostExc_uid148_fpLogE1pxTest: PROCESS (fracRPostExc_uid148_fpLogE1pxTest_s, en, cstAllZWF_uid8_fpLogE1pxTest_q, fracR_uid126_fpLogE1pxTest_q, cstAllZWF_uid8_fpLogE1pxTest_q, oneFracRPostExc2_uid145_fpLogE1pxTest_q)
BEGIN
CASE fracRPostExc_uid148_fpLogE1pxTest_s IS
WHEN "00" => fracRPostExc_uid148_fpLogE1pxTest_q <= cstAllZWF_uid8_fpLogE1pxTest_q;
WHEN "01" => fracRPostExc_uid148_fpLogE1pxTest_q <= fracR_uid126_fpLogE1pxTest_q;
WHEN "10" => fracRPostExc_uid148_fpLogE1pxTest_q <= cstAllZWF_uid8_fpLogE1pxTest_q;
WHEN "11" => fracRPostExc_uid148_fpLogE1pxTest_q <= oneFracRPostExc2_uid145_fpLogE1pxTest_q;
WHEN OTHERS => fracRPostExc_uid148_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RLn_uid153_fpLogE1pxTest(BITJOIN,152)@52
RLn_uid153_fpLogE1pxTest_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q & expRPostExc_uid152_fpLogE1pxTest_q & fracRPostExc_uid148_fpLogE1pxTest_q;
--xOut(GPOUT,4)@52
q <= RLn_uid153_fpLogE1pxTest_q;
end normal;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
Gray_Processing/ip/Gray_Processing/hcc_cntsgn32.vhd
|
20
|
5981
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CNTSGN32.VHD ***
--*** ***
--*** Function: Count leading bits in a signed ***
--*** 32 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_cntsgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_cntsgn32;
ARCHITECTURE rtl OF hcc_cntsgn32 IS
type positiontype IS ARRAY (8 DOWNTO 1) OF STD_LOGIC_VECTOR (5 DOWNTO 1);
signal possec, negsec, sec, sel : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal lastfrac : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal position : positiontype;
component hcc_sgnpstn
GENERIC (offset : integer := 0;
width : positive := 5);
PORT (
signbit : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- for single 32 bit mantissa
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- for double 64 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [64][63..60][59][58..7][6..4][321] - NB underflow less than overflow
-- find first leading '1' in inexact portion for 32 bit positive number
possec(1) <= frac(31) OR frac(30) OR frac(29) OR frac(28);
possec(2) <= frac(27) OR frac(26) OR frac(25) OR frac(24);
possec(3) <= frac(23) OR frac(22) OR frac(21) OR frac(20);
possec(4) <= frac(19) OR frac(18) OR frac(17) OR frac(16);
possec(5) <= frac(15) OR frac(14) OR frac(13) OR frac(12);
possec(6) <= frac(11) OR frac(10) OR frac(9) OR frac(8);
possec(7) <= frac(7) OR frac(6) OR frac(5) OR frac(4);
possec(8) <= frac(3) OR frac(2) OR frac(1);
-- find first leading '0' in inexact portion for 32 bit negative number
negsec(1) <= frac(31) AND frac(30) AND frac(29) AND frac(28);
negsec(2) <= frac(27) AND frac(26) AND frac(25) AND frac(24);
negsec(3) <= frac(23) AND frac(22) AND frac(21) AND frac(20);
negsec(4) <= frac(19) AND frac(18) AND frac(17) AND frac(16);
negsec(5) <= frac(15) AND frac(14) AND frac(13) AND frac(12);
negsec(6) <= frac(11) AND frac(10) AND frac(9) AND frac(8);
negsec(7) <= frac(7) AND frac(6) AND frac(5) AND frac(4);
negsec(8) <= frac(3) AND frac(2) AND frac(1);
gaa: FOR k IN 1 TO 8 GENERATE
sec(k) <= (possec(k) AND NOT(frac(32))) OR (NOT(negsec(k)) AND frac(32));
END GENERATE;
sel(1) <= sec(1);
sel(2) <= sec(2) AND NOT(sec(1));
sel(3) <= sec(3) AND NOT(sec(2)) AND NOT(sec(1));
sel(4) <= sec(4) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(5) <= sec(5) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(6) <= sec(6) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(7) <= sec(7) AND NOT(sec(6)) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND
NOT(sec(2)) AND NOT(sec(1));
sel(8) <= sec(8) AND NOT(sec(7)) AND NOT(sec(6)) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND
NOT(sec(2)) AND NOT(sec(1));
pone: hcc_sgnpstn
GENERIC MAP (offset=>0,width=>5)
PORT MAP (signbit=>frac(32),inbus=>frac(31 DOWNTO 28),
position=>position(1)(5 DOWNTO 1));
ptwo: hcc_sgnpstn
GENERIC MAP (offset=>4,width=>5)
PORT MAP (signbit=>frac(32),inbus=>frac(27 DOWNTO 24),
position=>position(2)(5 DOWNTO 1));
pthr: hcc_sgnpstn
GENERIC MAP (offset=>8,width=>5)
PORT MAP (signbit=>frac(32),inbus=>frac(23 DOWNTO 20),
position=>position(3)(5 DOWNTO 1));
pfor: hcc_sgnpstn
GENERIC MAP (offset=>12,width=>5)
PORT MAP (signbit=>frac(32),inbus=>frac(19 DOWNTO 16),
position=>position(4)(5 DOWNTO 1));
pfiv: hcc_sgnpstn
GENERIC MAP (offset=>16,width=>5)
PORT MAP (signbit=>frac(32),inbus=>frac(15 DOWNTO 12),
position=>position(5)(5 DOWNTO 1));
psix: hcc_sgnpstn
GENERIC MAP (offset=>20,width=>5)
PORT MAP (signbit=>frac(32),inbus=>frac(11 DOWNTO 8),
position=>position(6)(5 DOWNTO 1));
psev: hcc_sgnpstn
GENERIC MAP (offset=>24,width=>5)
PORT MAP (signbit=>frac(32),inbus=>frac(7 DOWNTO 4),
position=>position(7)(5 DOWNTO 1));
pegt: hcc_sgnpstn
GENERIC MAP (offset=>28,width=>5)
PORT MAP (signbit=>frac(32),inbus=>lastfrac,
position=>position(8)(5 DOWNTO 1));
lastfrac <= frac(3 DOWNTO 1) & frac(32);
gmc: FOR k IN 1 TO 5 GENERATE
count(k) <= (position(1)(k) AND sel(1)) OR
(position(2)(k) AND sel(2)) OR
(position(3)(k) AND sel(3)) OR
(position(4)(k) AND sel(4)) OR
(position(5)(k) AND sel(5)) OR
(position(6)(k) AND sel(6)) OR
(position(7)(k) AND sel(7)) OR
(position(8)(k) AND sel(8));
END GENERATE;
count(6) <= '0';
END rtl;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
Gray_Processing/ip/Gray_Processing/hcc_rsftpipe36.vhd
|
10
|
4753
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTPIPE36.VHD ***
--*** ***
--*** Function: Pipelined arithmetic right ***
--*** shift for a 36 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END hcc_rsftpipe36;
ARCHITECTURE rtl OF hcc_rsftpipe36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 33 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(34) <= (levzip(34) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(35) AND NOT(shift(2)) AND shift(1)) OR
(levzip(36) AND shift(2));
levone(35) <= (levzip(35) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(36) AND ((shift(2)) OR shift(1)));
levone(36) <= levzip(36);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 24 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 25 TO 28 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(36) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 29 TO 32 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(36) AND shift(4));
END GENERATE;
gbd: FOR k IN 33 TO 35 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(36) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(36) <= levone(36);
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= "00";
FOR k IN 1 TO 36 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(6 DOWNTO 5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 4 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(k+32) AND shiftff(2));
END GENERATE;
gcb: FOR k IN 5 TO 20 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(36) AND shiftff(2));
END GENERATE;
gcc: FOR k IN 21 TO 35 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(36) AND (shiftff(2) OR shiftff(1)));
END GENERATE;
levthr(36) <= levtwoff(36);
outbus <= levthr;
END rtl;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
Gray_Processing/ip/Gray_Processing/fp_ln_double_s5.vhd
|
10
|
543973
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_ln_double_s5
-- VHDL created on Mon Apr 8 15:29:06 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_ln_double_s5 is
port (
a : in std_logic_vector(63 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(63 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_ln_double_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllZWF_uid8_fpLogETest_q : std_logic_vector (51 downto 0);
signal cstBias_uid9_fpLogETest_q : std_logic_vector (10 downto 0);
signal cstBiasMO_uid10_fpLogETest_q : std_logic_vector (10 downto 0);
signal cstAllOWE_uid12_fpLogETest_q : std_logic_vector (10 downto 0);
signal cstAllZWE_uid14_fpLogETest_q : std_logic_vector (10 downto 0);
signal exc_R_uid27_fpLogETest_a : std_logic_vector(0 downto 0);
signal exc_R_uid27_fpLogETest_b : std_logic_vector(0 downto 0);
signal exc_R_uid27_fpLogETest_c : std_logic_vector(0 downto 0);
signal exc_R_uid27_fpLogETest_q_i : std_logic_vector(0 downto 0);
signal exc_R_uid27_fpLogETest_q : std_logic_vector(0 downto 0);
signal oMz_uid38_fpLogETest_a : std_logic_vector(53 downto 0);
signal oMz_uid38_fpLogETest_b : std_logic_vector(53 downto 0);
signal oMz_uid38_fpLogETest_o : std_logic_vector (53 downto 0);
signal oMz_uid38_fpLogETest_q : std_logic_vector (53 downto 0);
signal z2_uid40_fpLogETest_q : std_logic_vector (1 downto 0);
signal wideZero_uid44_fpLogETest_q : std_logic_vector (66 downto 0);
signal addTermOne_uid45_fpLogETest_s : std_logic_vector (0 downto 0);
signal addTermOne_uid45_fpLogETest_q : std_logic_vector (66 downto 0);
signal finalSumOneComp_uid52_fpLogETest_a : std_logic_vector(117 downto 0);
signal finalSumOneComp_uid52_fpLogETest_b : std_logic_vector(117 downto 0);
signal finalSumOneComp_uid52_fpLogETest_q_i : std_logic_vector(117 downto 0);
signal finalSumOneComp_uid52_fpLogETest_q : std_logic_vector(117 downto 0);
signal cstMSBFinalSumPBias_uid56_fpLogETest_q : std_logic_vector (11 downto 0);
signal expRExt_uid57_fpLogETest_a : std_logic_vector(12 downto 0);
signal expRExt_uid57_fpLogETest_b : std_logic_vector(12 downto 0);
signal expRExt_uid57_fpLogETest_o : std_logic_vector (12 downto 0);
signal expRExt_uid57_fpLogETest_q : std_logic_vector (12 downto 0);
signal signRC1_uid73_fpLogETest_a : std_logic_vector(0 downto 0);
signal signRC1_uid73_fpLogETest_b : std_logic_vector(0 downto 0);
signal signRC1_uid73_fpLogETest_q_i : std_logic_vector(0 downto 0);
signal signRC1_uid73_fpLogETest_q : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid76_fpLogETest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid76_fpLogETest_q_i : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid76_fpLogETest_q : std_logic_vector(0 downto 0);
signal signRFull_uid77_fpLogETest_a : std_logic_vector(0 downto 0);
signal signRFull_uid77_fpLogETest_b : std_logic_vector(0 downto 0);
signal signRFull_uid77_fpLogETest_q_i : std_logic_vector(0 downto 0);
signal signRFull_uid77_fpLogETest_q : std_logic_vector(0 downto 0);
signal excREnc_uid79_fpLogETest_q : std_logic_vector(1 downto 0);
signal oneFracRPostExc2_uid80_fpLogETest_q : std_logic_vector (51 downto 0);
signal p1_uid92_constMult_q : std_logic_vector(68 downto 0);
signal rndBit_uid130_natLogPolyEval_q : std_logic_vector (1 downto 0);
signal rndBit_uid142_natLogPolyEval_q : std_logic_vector (2 downto 0);
signal zs_uid147_countZ_uid54_fpLogETest_q : std_logic_vector (63 downto 0);
signal mO_uid150_countZ_uid54_fpLogETest_q : std_logic_vector (8 downto 0);
signal zs_uid155_countZ_uid54_fpLogETest_q : std_logic_vector (31 downto 0);
signal zs_uid161_countZ_uid54_fpLogETest_q : std_logic_vector (15 downto 0);
signal zs_uid167_countZ_uid54_fpLogETest_q : std_logic_vector (7 downto 0);
signal vCount_uid169_countZ_uid54_fpLogETest_a : std_logic_vector(7 downto 0);
signal vCount_uid169_countZ_uid54_fpLogETest_b : std_logic_vector(7 downto 0);
signal vCount_uid169_countZ_uid54_fpLogETest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid169_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0);
signal zs_uid173_countZ_uid54_fpLogETest_q : std_logic_vector (3 downto 0);
signal vCount_uid181_countZ_uid54_fpLogETest_a : std_logic_vector(1 downto 0);
signal vCount_uid181_countZ_uid54_fpLogETest_b : std_logic_vector(1 downto 0);
signal vCount_uid181_countZ_uid54_fpLogETest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid181_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad96_uid197_normVal_uid55_fpLogETest_q : std_logic_vector (95 downto 0);
signal leftShiftStage1Idx3Pad24_uid208_normVal_uid55_fpLogETest_q : std_logic_vector (23 downto 0);
signal leftShiftStage2Idx3Pad6_uid219_normVal_uid55_fpLogETest_q : std_logic_vector (5 downto 0);
signal prodXY_uid230_pT1_uid123_natLogPolyEval_a : std_logic_vector (16 downto 0);
signal prodXY_uid230_pT1_uid123_natLogPolyEval_b : std_logic_vector (16 downto 0);
signal prodXY_uid230_pT1_uid123_natLogPolyEval_s1 : std_logic_vector (33 downto 0);
signal prodXY_uid230_pT1_uid123_natLogPolyEval_pr : SIGNED (34 downto 0);
signal prodXY_uid230_pT1_uid123_natLogPolyEval_q : std_logic_vector (33 downto 0);
signal topProd_uid235_pT2_uid129_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid235_pT2_uid129_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid235_pT2_uid129_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid235_pT2_uid129_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid235_pT2_uid129_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal sm0_uid238_pT2_uid129_natLogPolyEval_a : std_logic_vector (2 downto 0);
signal sm0_uid238_pT2_uid129_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal sm0_uid238_pT2_uid129_natLogPolyEval_s1 : std_logic_vector (6 downto 0);
signal sm0_uid238_pT2_uid129_natLogPolyEval_pr : UNSIGNED (6 downto 0);
attribute multstyle : string;
attribute multstyle of sm0_uid238_pT2_uid129_natLogPolyEval_pr: signal is "logic";
signal sm0_uid238_pT2_uid129_natLogPolyEval_q : std_logic_vector (6 downto 0);
signal sm1_uid241_pT2_uid129_natLogPolyEval_a : std_logic_vector (5 downto 0);
signal sm1_uid241_pT2_uid129_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal sm1_uid241_pT2_uid129_natLogPolyEval_s1 : std_logic_vector (6 downto 0);
signal sm1_uid241_pT2_uid129_natLogPolyEval_pr : SIGNED (7 downto 0);
attribute multstyle of sm1_uid241_pT2_uid129_natLogPolyEval_pr: signal is "logic";
signal sm1_uid241_pT2_uid129_natLogPolyEval_q : std_logic_vector (6 downto 0);
signal topProd_uid248_pT3_uid135_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid248_pT3_uid135_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid248_pT3_uid135_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid248_pT3_uid135_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid248_pT3_uid135_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid265_pT4_uid141_natLogPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid265_pT4_uid141_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid265_pT4_uid141_natLogPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid265_pT4_uid141_natLogPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid265_pT4_uid141_natLogPolyEval_q : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b0_a : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b0_pr : UNSIGNED (53 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b0_q : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b0_a : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b0_pr : SIGNED (54 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b0_q : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b1_a : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b1_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b1_pr : UNSIGNED (53 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b1_q : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b1_a : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b1_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b1_pr : SIGNED (54 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b1_q : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b2_a : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b2_b : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b2_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b2_pr : SIGNED (54 downto 0);
signal postPEMul_uid43_fpLogETest_a0_b2_q : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b2_a : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b2_b : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b2_s1 : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b2_pr : SIGNED (53 downto 0);
signal postPEMul_uid43_fpLogETest_a1_b2_q : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_0_0_a : std_logic_vector(84 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_0_0_b : std_logic_vector(84 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_0_0_o : std_logic_vector (84 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_0_0_q : std_logic_vector (83 downto 0);
signal memoryC0_uid97_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid97_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid97_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid97_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid97_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid97_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid98_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid98_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid98_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid98_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid98_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid98_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid99_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid99_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid99_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid99_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid99_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid99_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid100_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid100_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid100_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid100_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid100_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid100_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid101_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid101_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid101_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid101_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid101_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid101_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC0_uid102_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid102_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC0_uid102_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC0_uid102_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC0_uid102_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC0_uid102_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid104_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid104_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid104_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid104_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid104_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid104_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid105_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid105_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid105_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid105_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid105_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid105_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid106_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid106_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid106_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid106_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid106_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid106_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid107_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid107_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC1_uid107_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid107_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid107_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC1_uid107_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC1_uid108_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid108_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC1_uid108_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC1_uid108_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC1_uid108_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC1_uid108_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC2_uid110_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid110_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid110_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid110_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid110_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid110_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid111_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid111_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid111_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid111_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid111_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid111_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid112_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid112_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC2_uid112_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid112_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid112_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC2_uid112_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC2_uid113_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid113_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC2_uid113_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC2_uid113_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC2_uid113_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC2_uid113_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC3_uid115_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid115_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC3_uid115_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid115_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid115_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC3_uid115_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC3_uid116_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid116_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC3_uid116_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid116_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid116_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC3_uid116_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC3_uid117_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC3_uid117_natLogTabGen_lutmem_ia : std_logic_vector (7 downto 0);
signal memoryC3_uid117_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC3_uid117_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC3_uid117_natLogTabGen_lutmem_iq : std_logic_vector (7 downto 0);
signal memoryC3_uid117_natLogTabGen_lutmem_q : std_logic_vector (7 downto 0);
signal memoryC4_uid119_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC4_uid119_natLogTabGen_lutmem_ia : std_logic_vector (9 downto 0);
signal memoryC4_uid119_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC4_uid119_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC4_uid119_natLogTabGen_lutmem_iq : std_logic_vector (9 downto 0);
signal memoryC4_uid119_natLogTabGen_lutmem_q : std_logic_vector (9 downto 0);
signal memoryC4_uid120_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC4_uid120_natLogTabGen_lutmem_ia : std_logic_vector (6 downto 0);
signal memoryC4_uid120_natLogTabGen_lutmem_aa : std_logic_vector (10 downto 0);
signal memoryC4_uid120_natLogTabGen_lutmem_ab : std_logic_vector (10 downto 0);
signal memoryC4_uid120_natLogTabGen_lutmem_iq : std_logic_vector (6 downto 0);
signal memoryC4_uid120_natLogTabGen_lutmem_q : std_logic_vector (6 downto 0);
type multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_a_type is array(0 to 1) of UNSIGNED(17 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_a : multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_a_type;
attribute preserve : boolean;
attribute preserve of multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_a : signal is true;
type multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_c : multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_c_type;
attribute preserve of multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_c : signal is true;
type multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_l_type is array(0 to 1) of SIGNED(18 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_l : multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_l_type;
type multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_p : multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_p_type;
type multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_w : multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_w_type;
type multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_x : multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_x_type;
type multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_y : multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_y_type;
type multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_s : multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_s_type;
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_s0 : std_logic_vector(36 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_q : std_logic_vector (36 downto 0);
type multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_a_type is array(0 to 1) of UNSIGNED(26 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_a : multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_a_type;
attribute preserve of multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_a : signal is true;
type multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_c : multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_c_type;
attribute preserve of multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_c : signal is true;
type multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_l_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_l : multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_l_type;
type multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_p : multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_p_type;
type multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_w : multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_w_type;
type multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_x : multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_x_type;
type multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_y : multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_y_type;
type multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_s : multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_s_type;
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_q : std_logic_vector (54 downto 0);
signal reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q : std_logic_vector (2 downto 0);
signal reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q : std_logic_vector (0 downto 0);
signal reg_sEz_uid41_fpLogETest_0_to_multTermOne_uid42_fpLogETest_2_q : std_logic_vector (53 downto 0);
signal reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q : std_logic_vector (10 downto 0);
signal reg_memoryC0_uid97_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid98_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid99_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid100_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_3_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid101_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_4_q : std_logic_vector (9 downto 0);
signal reg_memoryC0_uid102_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_5_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid104_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid105_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid106_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid107_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_3_q : std_logic_vector (9 downto 0);
signal reg_memoryC1_uid108_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_4_q : std_logic_vector (7 downto 0);
signal reg_memoryC2_uid110_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid111_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid112_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_2_q : std_logic_vector (9 downto 0);
signal reg_memoryC2_uid113_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_3_q : std_logic_vector (7 downto 0);
signal reg_memoryC4_uid119_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC4_uid120_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_1_q : std_logic_vector (6 downto 0);
signal reg_yT1_uid122_natLogPolyEval_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_0_q : std_logic_vector (16 downto 0);
signal reg_os_uid121_natLogTabGen_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_1_q : std_logic_vector (16 downto 0);
signal reg_memoryC3_uid115_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_0_q : std_logic_vector (9 downto 0);
signal reg_memoryC3_uid116_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_1_q : std_logic_vector (9 downto 0);
signal reg_memoryC3_uid117_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_2_q : std_logic_vector (7 downto 0);
signal reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid234_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_sSM0H_uid236_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_0_q : std_logic_vector (2 downto 0);
signal reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1_q : std_logic_vector (3 downto 0);
signal reg_sSM1H_uid239_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_0_q : std_logic_vector (5 downto 0);
signal reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1_q : std_logic_vector (0 downto 0);
signal reg_cIncludingRoundingBit_uid131_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_0_q : std_logic_vector (39 downto 0);
signal reg_R_uid245_pT2_uid129_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_1_q : std_logic_vector (29 downto 0);
signal reg_xTop18Bits_uid249_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_4_q : std_logic_vector (17 downto 0);
signal reg_pad_yBottomBits_uid250_uid255_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_6_q : std_logic_vector (17 downto 0);
signal reg_pad_xBottomBits_uid251_uid254_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_7_q : std_logic_vector (16 downto 0);
signal reg_yTop18Bits_uid252_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_9_q : std_logic_vector (17 downto 0);
signal reg_xTop27Bits_uid246_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_0_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid247_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid137_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_0_q : std_logic_vector (49 downto 0);
signal reg_R_uid262_pT3_uid135_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_1_q : std_logic_vector (40 downto 0);
signal reg_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_4_q : std_logic_vector (26 downto 0);
signal reg_pad_yBottomBits_uid266_uid270_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_7_q : std_logic_vector (25 downto 0);
signal reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_cIncludingRoundingBit_uid143_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_0_q : std_logic_vector (62 downto 0);
signal reg_R_uid277_pT4_uid141_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_1_q : std_logic_vector (51 downto 0);
signal reg_postPEMul_uid43_fpLogETest_a_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid43_fpLogETest_b_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid43_fpLogETest_a_1_0_to_postPEMul_uid43_fpLogETest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid43_fpLogETest_b_1_0_to_postPEMul_uid43_fpLogETest_a0_b1_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid43_fpLogETest_align_0_0_to_postPEMul_uid43_fpLogETest_result_add_0_0_0_q : std_logic_vector (53 downto 0);
signal reg_postPEMul_uid43_fpLogETest_b_2_0_to_postPEMul_uid43_fpLogETest_a0_b2_1_q : std_logic_vector (26 downto 0);
signal reg_postPEMul_uid43_fpLogETest_align_2_0_to_postPEMul_uid43_fpLogETest_result_add_0_1_0_q : std_logic_vector (108 downto 0);
signal reg_xv1_uid91_constMult_0_to_p1_uid92_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_sR_uid95_constMult_0_to_addTermOne_uid45_fpLogETest_2_q : std_logic_vector (66 downto 0);
signal reg_highBBits_uid47_fpLogETest_0_to_sumAHighB_uid48_fpLogETest_1_q : std_logic_vector (58 downto 0);
signal reg_lowRangeB_uid46_fpLogETest_0_to_finalSum_uid46_uid49_fpLogETest_0_q : std_logic_vector (49 downto 0);
signal reg_rVStage_uid148_countZ_uid54_fpLogETest_0_to_vCount_uid149_countZ_uid54_fpLogETest_1_q : std_logic_vector (63 downto 0);
signal reg_rVStage_uid156_countZ_uid54_fpLogETest_0_to_vCount_uid157_countZ_uid54_fpLogETest_1_q : std_logic_vector (31 downto 0);
signal reg_vStage_uid158_countZ_uid54_fpLogETest_0_to_vStagei_uid160_countZ_uid54_fpLogETest_3_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid162_countZ_uid54_fpLogETest_0_to_vCount_uid163_countZ_uid54_fpLogETest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid164_countZ_uid54_fpLogETest_0_to_vStagei_uid166_countZ_uid54_fpLogETest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid168_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid170_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid180_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid182_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid175_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6_q : std_logic_vector (0 downto 0);
signal reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_q : std_logic_vector (118 downto 0);
signal reg_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_3_q : std_logic_vector (118 downto 0);
signal reg_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_4_q : std_logic_vector (118 downto 0);
signal reg_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_5_q : std_logic_vector (118 downto 0);
signal reg_leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid201_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_2_q : std_logic_vector (118 downto 0);
signal reg_leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_3_q : std_logic_vector (118 downto 0);
signal reg_leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_4_q : std_logic_vector (118 downto 0);
signal reg_leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_5_q : std_logic_vector (118 downto 0);
signal reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid212_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_2_q : std_logic_vector (118 downto 0);
signal reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0_q : std_logic_vector (65 downto 0);
signal reg_fracR_uid61_fpLogETest_0_to_fracRPostExc_uid83_fpLogETest_3_q : std_logic_vector (51 downto 0);
signal reg_expR_uid62_fpLogETest_0_to_expRPostExc_uid87_fpLogETest_3_q : std_logic_vector (10 downto 0);
signal reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q : std_logic_vector (0 downto 0);
signal ld_FullSumAB117_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b_q : std_logic_vector (0 downto 0);
signal ld_r_uid188_countZ_uid54_fpLogETest_q_to_expRExt_uid57_fpLogETest_b_q : std_logic_vector (6 downto 0);
signal ld_signRFull_uid77_fpLogETest_q_to_RLn_uid88_fpLogETest_c_q : std_logic_vector (0 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_cStage_uid152_countZ_uid54_fpLogETest_b_q : std_logic_vector (54 downto 0);
signal ld_rVStage_uid148_countZ_uid54_fpLogETest_b_to_vStagei_uid154_countZ_uid54_fpLogETest_c_q : std_logic_vector (63 downto 0);
signal ld_vCount_uid169_countZ_uid54_fpLogETest_q_to_r_uid188_countZ_uid54_fpLogETest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6_q_to_r_uid188_countZ_uid54_fpLogETest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx1_uid215_normVal_uid55_fpLogETest_b_q : std_logic_vector (116 downto 0);
signal ld_LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx2_uid218_normVal_uid55_fpLogETest_b_q : std_logic_vector (114 downto 0);
signal ld_LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx3_uid221_normVal_uid55_fpLogETest_b_q : std_logic_vector (112 downto 0);
signal ld_reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1_q_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_b_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_b_to_leftShiftStage3_uid228_normVal_uid55_fpLogETest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1_q_to_sm1_uid241_pT2_uid129_natLogPolyEval_b_q : std_logic_vector (0 downto 0);
signal ld_reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_topProd_uid265_pT4_uid141_natLogPolyEval_1_q_to_topProd_uid265_pT4_uid141_natLogPolyEval_b_q : std_logic_vector (26 downto 0);
signal ld_yBottomBits_uid266_pT4_uid141_natLogPolyEval_b_to_spad_yBottomBits_uid266_uid268_pT4_uid141_natLogPolyEval_a_q : std_logic_vector (22 downto 0);
signal ld_postPEMul_uid43_fpLogETest_addcol_1_add_0_0_q_to_postPEMul_uid43_fpLogETest_align_1_a_q : std_logic_vector (55 downto 0);
signal ld_postPEMul_uid43_fpLogETest_addcol_2_add_0_0_q_to_postPEMul_uid43_fpLogETest_align_2_a_q : std_logic_vector (54 downto 0);
signal ld_postPEMul_uid43_fpLogETest_a1_b2_q_to_postPEMul_uid43_fpLogETest_align_3_a_q : std_logic_vector (53 downto 0);
signal ld_sSM0W_uid237_pT2_uid129_natLogPolyEval_b_to_reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1_a_q : std_logic_vector (3 downto 0);
signal ld_xv0_uid90_constMult_b_to_reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0_a_q : std_logic_vector (5 downto 0);
signal ld_vCount_uid163_countZ_uid54_fpLogETest_q_to_reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4_a_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid157_countZ_uid54_fpLogETest_q_to_reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5_a_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_inputreg_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_eq : std_logic;
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q : signal is true;
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_inputreg_q : std_logic_vector (51 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_reset0 : std_logic;
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_sticky_ena_q : signal is true;
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_reset0 : std_logic;
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_ia : std_logic_vector (51 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_iq : std_logic_vector (51 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_q : std_logic_vector (51 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_eq : std_logic;
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_sticky_ena_q : signal is true;
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_reset0 : std_logic;
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_sticky_ena_q : signal is true;
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_reset0 : std_logic;
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_sticky_ena_q : signal is true;
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_reset0 : std_logic;
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_eq : std_logic;
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_sticky_ena_q : signal is true;
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_reset0 : std_logic;
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_sticky_ena_q : signal is true;
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_reset0 : std_logic;
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_sticky_ena_q : signal is true;
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_reset0 : std_logic;
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_sticky_ena_q : signal is true;
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_reset0 : std_logic;
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_mem_top_q : std_logic_vector (6 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_sticky_ena_q : signal is true;
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_inputreg_q : std_logic_vector (27 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_ia : std_logic_vector (27 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_iq : std_logic_vector (27 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_q : std_logic_vector (27 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_inputreg_q : std_logic_vector (37 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_ia : std_logic_vector (37 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_iq : std_logic_vector (37 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_q : std_logic_vector (37 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_inputreg_q : std_logic_vector (41 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_ia : std_logic_vector (41 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_iq : std_logic_vector (41 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_q : std_logic_vector (41 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_inputreg_q : std_logic_vector (47 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_ia : std_logic_vector (47 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_iq : std_logic_vector (47 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_q : std_logic_vector (47 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_inputreg_q : std_logic_vector (59 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_ia : std_logic_vector (59 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_iq : std_logic_vector (59 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_q : std_logic_vector (59 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_inputreg_q : std_logic_vector (86 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_reset0 : std_logic;
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_ia : std_logic_vector (86 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_iq : std_logic_vector (86 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_q : std_logic_vector (86 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_sticky_ena_q : signal is true;
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_reset0 : std_logic;
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_ia : std_logic_vector (54 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_iq : std_logic_vector (54 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_q : std_logic_vector (54 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_sticky_ena_q : signal is true;
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_inputreg_q : std_logic_vector (22 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_reset0 : std_logic;
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_ia : std_logic_vector (41 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_iq : std_logic_vector (41 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_q : std_logic_vector (41 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_sticky_ena_q : signal is true;
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_inputreg_q : std_logic_vector (14 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_sticky_ena_q : signal is true;
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_inputreg_q : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_ia : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_iq : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_q : std_logic_vector (26 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_inputreg_q : std_logic_vector (118 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_reset0 : std_logic;
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_ia : std_logic_vector (118 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_iq : std_logic_vector (118 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_q : std_logic_vector (118 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_sticky_ena_q : signal is true;
signal pad_o_uid11_uid38_fpLogETest_q : std_logic_vector (52 downto 0);
signal FPOne_uid63_fpLogETest_q : std_logic_vector (63 downto 0);
signal pad_sm0_uid238_uid242_pT2_uid129_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal pad_sm1_uid241_uid243_pT2_uid129_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal spad_yBottomBits_uid266_uid268_pT4_uid141_natLogPolyEval_q : std_logic_vector (23 downto 0);
signal pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_q : std_logic_vector (25 downto 0);
signal pad_yBottomBits_uid266_uid270_pT4_uid141_natLogPolyEval_q : std_logic_vector (26 downto 0);
signal expFracPostRnd_uid60_fpLogETest_a : std_logic_vector(66 downto 0);
signal expFracPostRnd_uid60_fpLogETest_b : std_logic_vector(66 downto 0);
signal expFracPostRnd_uid60_fpLogETest_o : std_logic_vector (66 downto 0);
signal expFracPostRnd_uid60_fpLogETest_q : std_logic_vector (66 downto 0);
signal notC_uid71_fpLogETest_a : std_logic_vector(0 downto 0);
signal notC_uid71_fpLogETest_q : std_logic_vector(0 downto 0);
signal postPEMul_uid43_fpLogETest_addcol_1_add_0_0_a : std_logic_vector(56 downto 0);
signal postPEMul_uid43_fpLogETest_addcol_1_add_0_0_b : std_logic_vector(56 downto 0);
signal postPEMul_uid43_fpLogETest_addcol_1_add_0_0_o : std_logic_vector (56 downto 0);
signal postPEMul_uid43_fpLogETest_addcol_1_add_0_0_q : std_logic_vector (55 downto 0);
signal postPEMul_uid43_fpLogETest_addcol_2_add_0_0_a : std_logic_vector(54 downto 0);
signal postPEMul_uid43_fpLogETest_addcol_2_add_0_0_b : std_logic_vector(54 downto 0);
signal postPEMul_uid43_fpLogETest_addcol_2_add_0_0_o : std_logic_vector (54 downto 0);
signal postPEMul_uid43_fpLogETest_addcol_2_add_0_0_q : std_logic_vector (54 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal expX_uid6_fpLogETest_in : std_logic_vector (62 downto 0);
signal expX_uid6_fpLogETest_b : std_logic_vector (10 downto 0);
signal signX_uid7_fpLogETest_in : std_logic_vector (63 downto 0);
signal signX_uid7_fpLogETest_b : std_logic_vector (0 downto 0);
signal frac_uid19_fpLogETest_in : std_logic_vector (51 downto 0);
signal frac_uid19_fpLogETest_b : std_logic_vector (51 downto 0);
signal excRZero_uid64_fpLogETest_a : std_logic_vector(63 downto 0);
signal excRZero_uid64_fpLogETest_b : std_logic_vector(63 downto 0);
signal excRZero_uid64_fpLogETest_q : std_logic_vector(0 downto 0);
signal expXIsZero_uid16_fpLogETest_a : std_logic_vector(10 downto 0);
signal expXIsZero_uid16_fpLogETest_b : std_logic_vector(10 downto 0);
signal expXIsZero_uid16_fpLogETest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid18_fpLogETest_a : std_logic_vector(10 downto 0);
signal expXIsMax_uid18_fpLogETest_b : std_logic_vector(10 downto 0);
signal expXIsMax_uid18_fpLogETest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid20_fpLogETest_a : std_logic_vector(51 downto 0);
signal fracXIsZero_uid20_fpLogETest_b : std_logic_vector(51 downto 0);
signal fracXIsZero_uid20_fpLogETest_q : std_logic_vector(0 downto 0);
signal exc_I_uid21_fpLogETest_a : std_logic_vector(0 downto 0);
signal exc_I_uid21_fpLogETest_b : std_logic_vector(0 downto 0);
signal exc_I_uid21_fpLogETest_q : std_logic_vector(0 downto 0);
signal e_uid29_fpLogETest_a : std_logic_vector(11 downto 0);
signal e_uid29_fpLogETest_b : std_logic_vector(11 downto 0);
signal e_uid29_fpLogETest_o : std_logic_vector (11 downto 0);
signal e_uid29_fpLogETest_q : std_logic_vector (11 downto 0);
signal c_uid31_fpLogETest_a : std_logic_vector(10 downto 0);
signal c_uid31_fpLogETest_b : std_logic_vector(10 downto 0);
signal c_uid31_fpLogETest_q : std_logic_vector(0 downto 0);
signal multTermOne_uid42_fpLogETest_s : std_logic_vector (0 downto 0);
signal multTermOne_uid42_fpLogETest_q : std_logic_vector (53 downto 0);
signal sumAHighB_uid48_fpLogETest_a : std_logic_vector(67 downto 0);
signal sumAHighB_uid48_fpLogETest_b : std_logic_vector(67 downto 0);
signal sumAHighB_uid48_fpLogETest_o : std_logic_vector (67 downto 0);
signal sumAHighB_uid48_fpLogETest_q : std_logic_vector (67 downto 0);
signal finalSumAbs_uid53_fpLogETest_a : std_logic_vector(118 downto 0);
signal finalSumAbs_uid53_fpLogETest_b : std_logic_vector(118 downto 0);
signal finalSumAbs_uid53_fpLogETest_o : std_logic_vector (118 downto 0);
signal finalSumAbs_uid53_fpLogETest_q : std_logic_vector (118 downto 0);
signal signRC11_uid74_fpLogETest_a : std_logic_vector(0 downto 0);
signal signRC11_uid74_fpLogETest_b : std_logic_vector(0 downto 0);
signal signRC11_uid74_fpLogETest_q : std_logic_vector(0 downto 0);
signal signR_uid75_fpLogETest_a : std_logic_vector(0 downto 0);
signal signR_uid75_fpLogETest_b : std_logic_vector(0 downto 0);
signal signR_uid75_fpLogETest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid83_fpLogETest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid83_fpLogETest_q : std_logic_vector (51 downto 0);
signal expRPostExc_uid87_fpLogETest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid87_fpLogETest_q : std_logic_vector (10 downto 0);
signal p0_uid93_constMult_q : std_logic_vector(62 downto 0);
signal lev1_a0_uid94_constMult_a : std_logic_vector(70 downto 0);
signal lev1_a0_uid94_constMult_b : std_logic_vector(70 downto 0);
signal lev1_a0_uid94_constMult_o : std_logic_vector (70 downto 0);
signal lev1_a0_uid94_constMult_q : std_logic_vector (69 downto 0);
signal ts2_uid132_natLogPolyEval_a : std_logic_vector(40 downto 0);
signal ts2_uid132_natLogPolyEval_b : std_logic_vector(40 downto 0);
signal ts2_uid132_natLogPolyEval_o : std_logic_vector (40 downto 0);
signal ts2_uid132_natLogPolyEval_q : std_logic_vector (40 downto 0);
signal ts3_uid138_natLogPolyEval_a : std_logic_vector(50 downto 0);
signal ts3_uid138_natLogPolyEval_b : std_logic_vector(50 downto 0);
signal ts3_uid138_natLogPolyEval_o : std_logic_vector (50 downto 0);
signal ts3_uid138_natLogPolyEval_q : std_logic_vector (50 downto 0);
signal ts4_uid144_natLogPolyEval_a : std_logic_vector(63 downto 0);
signal ts4_uid144_natLogPolyEval_b : std_logic_vector(63 downto 0);
signal ts4_uid144_natLogPolyEval_o : std_logic_vector (63 downto 0);
signal ts4_uid144_natLogPolyEval_q : std_logic_vector (63 downto 0);
signal vCount_uid149_countZ_uid54_fpLogETest_a : std_logic_vector(63 downto 0);
signal vCount_uid149_countZ_uid54_fpLogETest_b : std_logic_vector(63 downto 0);
signal vCount_uid149_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0);
signal vCount_uid157_countZ_uid54_fpLogETest_a : std_logic_vector(31 downto 0);
signal vCount_uid157_countZ_uid54_fpLogETest_b : std_logic_vector(31 downto 0);
signal vCount_uid157_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0);
signal vStagei_uid160_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0);
signal vStagei_uid160_countZ_uid54_fpLogETest_q : std_logic_vector (31 downto 0);
signal vCount_uid163_countZ_uid54_fpLogETest_a : std_logic_vector(15 downto 0);
signal vCount_uid163_countZ_uid54_fpLogETest_b : std_logic_vector(15 downto 0);
signal vCount_uid163_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0);
signal vStagei_uid166_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0);
signal vStagei_uid166_countZ_uid54_fpLogETest_q : std_logic_vector (15 downto 0);
signal vStagei_uid172_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0);
signal vStagei_uid172_countZ_uid54_fpLogETest_q : std_logic_vector (7 downto 0);
signal vStagei_uid184_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0);
signal vStagei_uid184_countZ_uid54_fpLogETest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid212_normVal_uid55_fpLogETest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid212_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal add0_uid242_pT2_uid129_natLogPolyEval_a : std_logic_vector (54 downto 0);
signal add0_uid242_pT2_uid129_natLogPolyEval_b : std_logic_vector (54 downto 0);
signal add0_uid242_pT2_uid129_natLogPolyEval_c : std_logic_vector (54 downto 0);
signal add0_uid242_pT2_uid129_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal add0_uid242_pT2_uid129_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_enaAnd_q : std_logic_vector(0 downto 0);
signal sEz_uid41_fpLogETest_q : std_logic_vector (53 downto 0);
signal leftShiftStage2Idx1_uid215_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal cIncludingRoundingBit_uid131_natLogPolyEval_q : std_logic_vector (39 downto 0);
signal cIncludingRoundingBit_uid137_natLogPolyEval_q : std_logic_vector (49 downto 0);
signal cIncludingRoundingBit_uid143_natLogPolyEval_q : std_logic_vector (62 downto 0);
signal leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal cStage_uid152_countZ_uid54_fpLogETest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal leftShiftStage2Idx2_uid218_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal leftShiftStage2Idx3_uid221_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal prodXYTruncFR_uid231_pT1_uid123_natLogPolyEval_in : std_logic_vector (33 downto 0);
signal prodXYTruncFR_uid231_pT1_uid123_natLogPolyEval_b : std_logic_vector (18 downto 0);
signal postPEMul_uid43_fpLogETest_align_0_q_int : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_align_0_q : std_logic_vector (53 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_in : std_logic_vector (36 downto 0);
signal multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_b : std_logic_vector (32 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_b : std_logic_vector (51 downto 0);
signal os_uid103_natLogTabGen_q : std_logic_vector (59 downto 0);
signal os_uid109_natLogTabGen_q : std_logic_vector (47 downto 0);
signal os_uid114_natLogTabGen_q : std_logic_vector (37 downto 0);
signal os_uid121_natLogTabGen_q : std_logic_vector (16 downto 0);
signal os_uid118_natLogTabGen_q : std_logic_vector (27 downto 0);
signal finalSum_uid46_uid49_fpLogETest_q : std_logic_vector (117 downto 0);
signal leftShiftStage2_uid223_normVal_uid55_fpLogETest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid223_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal RLn_uid88_fpLogETest_q : std_logic_vector (63 downto 0);
signal vStagei_uid154_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0);
signal vStagei_uid154_countZ_uid54_fpLogETest_q : std_logic_vector (63 downto 0);
signal postPEMul_uid43_fpLogETest_align_1_q_int : std_logic_vector (82 downto 0);
signal postPEMul_uid43_fpLogETest_align_1_q : std_logic_vector (82 downto 0);
signal postPEMul_uid43_fpLogETest_align_2_q_int : std_logic_vector (108 downto 0);
signal postPEMul_uid43_fpLogETest_align_2_q : std_logic_vector (108 downto 0);
signal postPEMul_uid43_fpLogETest_align_3_q_int : std_logic_vector (134 downto 0);
signal postPEMul_uid43_fpLogETest_align_3_q : std_logic_vector (134 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_q : std_logic_vector(0 downto 0);
signal zPPolyEval_uid35_fpLogETest_in : std_logic_vector (41 downto 0);
signal zPPolyEval_uid35_fpLogETest_b : std_logic_vector (41 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmp_a : std_logic_vector(6 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmp_b : std_logic_vector(6 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal yT3_uid134_natLogPolyEval_in : std_logic_vector (41 downto 0);
signal yT3_uid134_natLogPolyEval_b : std_logic_vector (37 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_nor_q : std_logic_vector(0 downto 0);
signal xTop27Bits_uid263_pT4_uid141_natLogPolyEval_in : std_logic_vector (41 downto 0);
signal xTop27Bits_uid263_pT4_uid141_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_nor_a : std_logic_vector(0 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_nor_b : std_logic_vector(0 downto 0);
signal ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_nor_q : std_logic_vector(0 downto 0);
signal fracR_uid61_fpLogETest_in : std_logic_vector (52 downto 0);
signal fracR_uid61_fpLogETest_b : std_logic_vector (51 downto 0);
signal expR_uid62_fpLogETest_in : std_logic_vector (63 downto 0);
signal expR_uid62_fpLogETest_b : std_logic_vector (10 downto 0);
signal InvSignX_uid65_fpLogETest_a : std_logic_vector(0 downto 0);
signal InvSignX_uid65_fpLogETest_q : std_logic_vector(0 downto 0);
signal zAddrLow_uid33_fpLogETest_in : std_logic_vector (51 downto 0);
signal zAddrLow_uid33_fpLogETest_b : std_logic_vector (9 downto 0);
signal InvExpXIsZero_uid26_fpLogETest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid26_fpLogETest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid22_fpLogETest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid22_fpLogETest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid25_fpLogETest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid25_fpLogETest_q : std_logic_vector(0 downto 0);
signal excRInfC1_uid66_fpLogETest_a : std_logic_vector(0 downto 0);
signal excRInfC1_uid66_fpLogETest_b : std_logic_vector(0 downto 0);
signal excRInfC1_uid66_fpLogETest_q : std_logic_vector(0 downto 0);
signal xv0_uid90_constMult_in : std_logic_vector (5 downto 0);
signal xv0_uid90_constMult_b : std_logic_vector (5 downto 0);
signal xv1_uid91_constMult_in : std_logic_vector (11 downto 0);
signal xv1_uid91_constMult_b : std_logic_vector (5 downto 0);
signal addr_uid34_fpLogETest_q : std_logic_vector (10 downto 0);
signal postPEMul_uid43_fpLogETest_a_0_in : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a_0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_a_1_in : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_a_1_b : std_logic_vector (26 downto 0);
signal rVStage_uid148_countZ_uid54_fpLogETest_in : std_logic_vector (118 downto 0);
signal rVStage_uid148_countZ_uid54_fpLogETest_b : std_logic_vector (63 downto 0);
signal vStage_uid151_countZ_uid54_fpLogETest_in : std_logic_vector (54 downto 0);
signal vStage_uid151_countZ_uid54_fpLogETest_b : std_logic_vector (54 downto 0);
signal X86dto0_uid192_normVal_uid55_fpLogETest_in : std_logic_vector (86 downto 0);
signal X86dto0_uid192_normVal_uid55_fpLogETest_b : std_logic_vector (86 downto 0);
signal X22dto0_uid198_normVal_uid55_fpLogETest_in : std_logic_vector (22 downto 0);
signal X22dto0_uid198_normVal_uid55_fpLogETest_b : std_logic_vector (22 downto 0);
signal sR_uid95_constMult_in : std_logic_vector (68 downto 0);
signal sR_uid95_constMult_b : std_logic_vector (66 downto 0);
signal s2_uid133_natLogPolyEval_in : std_logic_vector (40 downto 0);
signal s2_uid133_natLogPolyEval_b : std_logic_vector (39 downto 0);
signal s3_uid139_natLogPolyEval_in : std_logic_vector (50 downto 0);
signal s3_uid139_natLogPolyEval_b : std_logic_vector (49 downto 0);
signal s4_uid145_natLogPolyEval_in : std_logic_vector (63 downto 0);
signal s4_uid145_natLogPolyEval_b : std_logic_vector (62 downto 0);
signal rVStage_uid162_countZ_uid54_fpLogETest_in : std_logic_vector (31 downto 0);
signal rVStage_uid162_countZ_uid54_fpLogETest_b : std_logic_vector (15 downto 0);
signal vStage_uid164_countZ_uid54_fpLogETest_in : std_logic_vector (15 downto 0);
signal vStage_uid164_countZ_uid54_fpLogETest_b : std_logic_vector (15 downto 0);
signal rVStage_uid168_countZ_uid54_fpLogETest_in : std_logic_vector (15 downto 0);
signal rVStage_uid168_countZ_uid54_fpLogETest_b : std_logic_vector (7 downto 0);
signal vStage_uid170_countZ_uid54_fpLogETest_in : std_logic_vector (7 downto 0);
signal vStage_uid170_countZ_uid54_fpLogETest_b : std_logic_vector (7 downto 0);
signal rVStage_uid174_countZ_uid54_fpLogETest_in : std_logic_vector (7 downto 0);
signal rVStage_uid174_countZ_uid54_fpLogETest_b : std_logic_vector (3 downto 0);
signal vStage_uid176_countZ_uid54_fpLogETest_in : std_logic_vector (3 downto 0);
signal vStage_uid176_countZ_uid54_fpLogETest_b : std_logic_vector (3 downto 0);
signal rVStage_uid186_countZ_uid54_fpLogETest_in : std_logic_vector (1 downto 0);
signal rVStage_uid186_countZ_uid54_fpLogETest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_in : std_logic_vector (116 downto 0);
signal LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_b : std_logic_vector (116 downto 0);
signal LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_in : std_logic_vector (114 downto 0);
signal LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_b : std_logic_vector (114 downto 0);
signal LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_in : std_logic_vector (112 downto 0);
signal LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_b : std_logic_vector (112 downto 0);
signal R_uid245_pT2_uid129_natLogPolyEval_in : std_logic_vector (53 downto 0);
signal R_uid245_pT2_uid129_natLogPolyEval_b : std_logic_vector (29 downto 0);
signal lowRangeB_uid124_natLogPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid124_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid125_natLogPolyEval_in : std_logic_vector (18 downto 0);
signal highBBits_uid125_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal lowRangeB_uid258_pT3_uid135_natLogPolyEval_in : std_logic_vector (3 downto 0);
signal lowRangeB_uid258_pT3_uid135_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal highBBits_uid259_pT3_uid135_natLogPolyEval_in : std_logic_vector (32 downto 0);
signal highBBits_uid259_pT3_uid135_natLogPolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid273_pT4_uid141_natLogPolyEval_in : std_logic_vector (22 downto 0);
signal lowRangeB_uid273_pT4_uid141_natLogPolyEval_b : std_logic_vector (22 downto 0);
signal highBBits_uid274_pT4_uid141_natLogPolyEval_in : std_logic_vector (51 downto 0);
signal highBBits_uid274_pT4_uid141_natLogPolyEval_b : std_logic_vector (28 downto 0);
signal FullSumAB117_uid50_fpLogETest_in : std_logic_vector (117 downto 0);
signal FullSumAB117_uid50_fpLogETest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage2117dto0_uid225_normVal_uid55_fpLogETest_in : std_logic_vector (117 downto 0);
signal LeftShiftStage2117dto0_uid225_normVal_uid55_fpLogETest_b : std_logic_vector (117 downto 0);
signal rVStage_uid156_countZ_uid54_fpLogETest_in : std_logic_vector (63 downto 0);
signal rVStage_uid156_countZ_uid54_fpLogETest_b : std_logic_vector (31 downto 0);
signal vStage_uid158_countZ_uid54_fpLogETest_in : std_logic_vector (31 downto 0);
signal vStage_uid158_countZ_uid54_fpLogETest_b : std_logic_vector (31 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_0_1_a : std_logic_vector(135 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_0_1_b : std_logic_vector(135 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_0_1_o : std_logic_vector (135 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_0_1_q : std_logic_vector (135 downto 0);
signal yT1_uid122_natLogPolyEval_in : std_logic_vector (41 downto 0);
signal yT1_uid122_natLogPolyEval_b : std_logic_vector (16 downto 0);
signal yT2_uid128_natLogPolyEval_in : std_logic_vector (41 downto 0);
signal yT2_uid128_natLogPolyEval_b : std_logic_vector (27 downto 0);
signal xBottomBits_uid267_pT4_uid141_natLogPolyEval_in : std_logic_vector (14 downto 0);
signal xBottomBits_uid267_pT4_uid141_natLogPolyEval_b : std_logic_vector (14 downto 0);
signal xTop27Bits_uid246_pT3_uid135_natLogPolyEval_in : std_logic_vector (37 downto 0);
signal xTop27Bits_uid246_pT3_uid135_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal xTop18Bits_uid249_pT3_uid135_natLogPolyEval_in : std_logic_vector (37 downto 0);
signal xTop18Bits_uid249_pT3_uid135_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid251_pT3_uid135_natLogPolyEval_in : std_logic_vector (10 downto 0);
signal xBottomBits_uid251_pT3_uid135_natLogPolyEval_b : std_logic_vector (10 downto 0);
signal negNonZero_uid69_fpLogETest_a : std_logic_vector(0 downto 0);
signal negNonZero_uid69_fpLogETest_b : std_logic_vector(0 downto 0);
signal negNonZero_uid69_fpLogETest_q : std_logic_vector(0 downto 0);
signal exc_N_uid23_fpLogETest_a : std_logic_vector(0 downto 0);
signal exc_N_uid23_fpLogETest_b : std_logic_vector(0 downto 0);
signal exc_N_uid23_fpLogETest_q : std_logic_vector(0 downto 0);
signal excRInf_uid67_fpLogETest_a : std_logic_vector(0 downto 0);
signal excRInf_uid67_fpLogETest_b : std_logic_vector(0 downto 0);
signal excRInf_uid67_fpLogETest_q : std_logic_vector(0 downto 0);
signal yTop27Bits_uid247_pT3_uid135_natLogPolyEval_in : std_logic_vector (39 downto 0);
signal yTop27Bits_uid247_pT3_uid135_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid250_pT3_uid135_natLogPolyEval_in : std_logic_vector (12 downto 0);
signal yBottomBits_uid250_pT3_uid135_natLogPolyEval_b : std_logic_vector (12 downto 0);
signal yTop18Bits_uid252_pT3_uid135_natLogPolyEval_in : std_logic_vector (39 downto 0);
signal yTop18Bits_uid252_pT3_uid135_natLogPolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid264_pT4_uid141_natLogPolyEval_in : std_logic_vector (49 downto 0);
signal yTop27Bits_uid264_pT4_uid141_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid266_pT4_uid141_natLogPolyEval_in : std_logic_vector (22 downto 0);
signal yBottomBits_uid266_pT4_uid141_natLogPolyEval_b : std_logic_vector (22 downto 0);
signal peOR_uid37_fpLogETest_in : std_logic_vector (61 downto 0);
signal peOR_uid37_fpLogETest_b : std_logic_vector (54 downto 0);
signal vCount_uid175_countZ_uid54_fpLogETest_a : std_logic_vector(3 downto 0);
signal vCount_uid175_countZ_uid54_fpLogETest_b : std_logic_vector(3 downto 0);
signal vCount_uid175_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0);
signal vStagei_uid178_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0);
signal vStagei_uid178_countZ_uid54_fpLogETest_q : std_logic_vector (3 downto 0);
signal vCount_uid187_countZ_uid54_fpLogETest_a : std_logic_vector(0 downto 0);
signal vCount_uid187_countZ_uid54_fpLogETest_b : std_logic_vector(0 downto 0);
signal vCount_uid187_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid126_natLogPolyEval_a : std_logic_vector(28 downto 0);
signal sumAHighB_uid126_natLogPolyEval_b : std_logic_vector(28 downto 0);
signal sumAHighB_uid126_natLogPolyEval_o : std_logic_vector (28 downto 0);
signal sumAHighB_uid126_natLogPolyEval_q : std_logic_vector (28 downto 0);
signal sumAHighB_uid260_pT3_uid135_natLogPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid260_pT3_uid135_natLogPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid260_pT3_uid135_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid260_pT3_uid135_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid275_pT4_uid141_natLogPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid275_pT4_uid141_natLogPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid275_pT4_uid141_natLogPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid275_pT4_uid141_natLogPolyEval_q : std_logic_vector (54 downto 0);
signal signTerm2_uid72_fpLogETest_a : std_logic_vector(0 downto 0);
signal signTerm2_uid72_fpLogETest_b : std_logic_vector(0 downto 0);
signal signTerm2_uid72_fpLogETest_q : std_logic_vector(0 downto 0);
signal leftShiftStage3Idx1_uid226_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_1_0_a : std_logic_vector(136 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_1_0_b : std_logic_vector(136 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_1_0_o : std_logic_vector (136 downto 0);
signal postPEMul_uid43_fpLogETest_result_add_1_0_q : std_logic_vector (136 downto 0);
signal xTop27Bits_uid233_pT2_uid129_natLogPolyEval_in : std_logic_vector (27 downto 0);
signal xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal sSM0W_uid237_pT2_uid129_natLogPolyEval_in : std_logic_vector (27 downto 0);
signal sSM0W_uid237_pT2_uid129_natLogPolyEval_b : std_logic_vector (3 downto 0);
signal sSM1W_uid240_pT2_uid129_natLogPolyEval_in : std_logic_vector (0 downto 0);
signal sSM1W_uid240_pT2_uid129_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal pad_xBottomBits_uid251_uid254_pT3_uid135_natLogPolyEval_q : std_logic_vector (16 downto 0);
signal excRNaN_uid70_fpLogETest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid70_fpLogETest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid70_fpLogETest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid24_fpLogETest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid24_fpLogETest_q : std_logic_vector(0 downto 0);
signal concExc_uid78_fpLogETest_q : std_logic_vector (2 downto 0);
signal spad_yBottomBits_uid250_uid253_pT3_uid135_natLogPolyEval_q : std_logic_vector (13 downto 0);
signal postPEMul_uid43_fpLogETest_b_0_in : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_b_0_b : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_b_1_in : std_logic_vector (53 downto 0);
signal postPEMul_uid43_fpLogETest_b_1_b : std_logic_vector (26 downto 0);
signal postPEMul_uid43_fpLogETest_b_2_in : std_logic_vector (80 downto 0);
signal postPEMul_uid43_fpLogETest_b_2_b : std_logic_vector (26 downto 0);
signal rVStage_uid180_countZ_uid54_fpLogETest_in : std_logic_vector (3 downto 0);
signal rVStage_uid180_countZ_uid54_fpLogETest_b : std_logic_vector (1 downto 0);
signal vStage_uid182_countZ_uid54_fpLogETest_in : std_logic_vector (1 downto 0);
signal vStage_uid182_countZ_uid54_fpLogETest_b : std_logic_vector (1 downto 0);
signal r_uid188_countZ_uid54_fpLogETest_q : std_logic_vector (6 downto 0);
signal s1_uid124_uid127_natLogPolyEval_q : std_logic_vector (29 downto 0);
signal add0_uid258_uid261_pT3_uid135_natLogPolyEval_q : std_logic_vector (58 downto 0);
signal add0_uid273_uid276_pT4_uid141_natLogPolyEval_q : std_logic_vector (77 downto 0);
signal leftShiftStage3_uid228_normVal_uid55_fpLogETest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid228_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal lowRangeB_uid46_fpLogETest_in : std_logic_vector (49 downto 0);
signal lowRangeB_uid46_fpLogETest_b : std_logic_vector (49 downto 0);
signal highBBits_uid47_fpLogETest_in : std_logic_vector (108 downto 0);
signal highBBits_uid47_fpLogETest_b : std_logic_vector (58 downto 0);
signal pad_yBottomBits_uid250_uid255_pT3_uid135_natLogPolyEval_q : std_logic_vector (17 downto 0);
signal leftShiftStageSel6Dto5_uid200_normVal_uid55_fpLogETest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid200_normVal_uid55_fpLogETest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_b : std_logic_vector (0 downto 0);
signal yTop27Bits_uid234_pT2_uid129_natLogPolyEval_in : std_logic_vector (29 downto 0);
signal yTop27Bits_uid234_pT2_uid129_natLogPolyEval_b : std_logic_vector (26 downto 0);
signal sSM0H_uid236_pT2_uid129_natLogPolyEval_in : std_logic_vector (2 downto 0);
signal sSM0H_uid236_pT2_uid129_natLogPolyEval_b : std_logic_vector (2 downto 0);
signal sSM1H_uid239_pT2_uid129_natLogPolyEval_in : std_logic_vector (29 downto 0);
signal sSM1H_uid239_pT2_uid129_natLogPolyEval_b : std_logic_vector (5 downto 0);
signal R_uid262_pT3_uid135_natLogPolyEval_in : std_logic_vector (57 downto 0);
signal R_uid262_pT3_uid135_natLogPolyEval_b : std_logic_vector (40 downto 0);
signal R_uid277_pT4_uid141_natLogPolyEval_in : std_logic_vector (76 downto 0);
signal R_uid277_pT4_uid141_natLogPolyEval_b : std_logic_vector (51 downto 0);
signal fracR_uid58_fpLogETest_in : std_logic_vector (117 downto 0);
signal fracR_uid58_fpLogETest_b : std_logic_vector (52 downto 0);
signal leftShiftStage0_uid201_normVal_uid55_fpLogETest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid201_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal expFracConc_uid59_fpLogETest_q : std_logic_vector (65 downto 0);
signal LeftShiftStage0110dto0_uid203_normVal_uid55_fpLogETest_in : std_logic_vector (110 downto 0);
signal LeftShiftStage0110dto0_uid203_normVal_uid55_fpLogETest_b : std_logic_vector (110 downto 0);
signal LeftShiftStage0102dto0_uid206_normVal_uid55_fpLogETest_in : std_logic_vector (102 downto 0);
signal LeftShiftStage0102dto0_uid206_normVal_uid55_fpLogETest_b : std_logic_vector (102 downto 0);
signal LeftShiftStage094dto0_uid209_normVal_uid55_fpLogETest_in : std_logic_vector (94 downto 0);
signal LeftShiftStage094dto0_uid209_normVal_uid55_fpLogETest_b : std_logic_vector (94 downto 0);
signal leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
signal leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest_q : std_logic_vector (118 downto 0);
begin
--xIn(GPIN,3)@0
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable(LOGICAL,902)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_a <= en;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q <= not ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_a;
--ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_nor(LOGICAL,914)
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_nor_b <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_sticky_ena_q;
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_nor_q <= not (ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_nor_a or ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_nor_b);
--ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg(REG,912)
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_sticky_ena(REG,915)
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_nor_q = "1") THEN
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_sticky_ena_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_enaAnd(LOGICAL,916)
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_enaAnd_a <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_sticky_ena_q;
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_enaAnd_b <= en;
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_enaAnd_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_enaAnd_a and ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_enaAnd_b;
--frac_uid19_fpLogETest(BITSELECT,18)@0
frac_uid19_fpLogETest_in <= a(51 downto 0);
frac_uid19_fpLogETest_b <= frac_uid19_fpLogETest_in(51 downto 0);
--ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_inputreg(DELAY,906)
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => frac_uid19_fpLogETest_b, xout => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt(COUNTER,908)
-- every=1, low=0, high=1, step=1, init=1
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt_i <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt_i,1));
--ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg(REG,909)
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux(MUX,910)
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_s <= en;
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux: PROCESS (ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_s, ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q, ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt_q)
BEGIN
CASE ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_s IS
WHEN "0" => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q;
WHEN "1" => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdcnt_q;
WHEN OTHERS => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem(DUALMEM,907)
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_ia <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_inputreg_q;
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_aa <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q;
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_ab <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q;
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 1,
numwords_a => 2,
width_b => 52,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_iq,
address_a => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_aa,
data_a => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_ia
);
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_reset0 <= areset;
ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_iq(51 downto 0);
--zPPolyEval_uid35_fpLogETest(BITSELECT,34)@4
zPPolyEval_uid35_fpLogETest_in <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_mem_q(41 downto 0);
zPPolyEval_uid35_fpLogETest_b <= zPPolyEval_uid35_fpLogETest_in(41 downto 0);
--yT2_uid128_natLogPolyEval(BITSELECT,127)@4
yT2_uid128_natLogPolyEval_in <= zPPolyEval_uid35_fpLogETest_b;
yT2_uid128_natLogPolyEval_b <= yT2_uid128_natLogPolyEval_in(41 downto 14);
--sSM1W_uid240_pT2_uid129_natLogPolyEval(BITSELECT,239)@4
sSM1W_uid240_pT2_uid129_natLogPolyEval_in <= yT2_uid128_natLogPolyEval_b(0 downto 0);
sSM1W_uid240_pT2_uid129_natLogPolyEval_b <= sSM1W_uid240_pT2_uid129_natLogPolyEval_in(0 downto 0);
--reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1(REG,369)@4
reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1_q <= sSM1W_uid240_pT2_uid129_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1_q_to_sm1_uid241_pT2_uid129_natLogPolyEval_b(DELAY,672)@5
ld_reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1_q_to_sm1_uid241_pT2_uid129_natLogPolyEval_b : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1_q, xout => ld_reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1_q_to_sm1_uid241_pT2_uid129_natLogPolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--cstBiasMO_uid10_fpLogETest(CONSTANT,9)
cstBiasMO_uid10_fpLogETest_q <= "01111111110";
--expX_uid6_fpLogETest(BITSELECT,5)@0
expX_uid6_fpLogETest_in <= a(62 downto 0);
expX_uid6_fpLogETest_b <= expX_uid6_fpLogETest_in(62 downto 52);
--c_uid31_fpLogETest(LOGICAL,30)@0
c_uid31_fpLogETest_a <= expX_uid6_fpLogETest_b;
c_uid31_fpLogETest_b <= cstBiasMO_uid10_fpLogETest_q;
c_uid31_fpLogETest_q <= "1" when c_uid31_fpLogETest_a = c_uid31_fpLogETest_b else "0";
--zAddrLow_uid33_fpLogETest(BITSELECT,32)@0
zAddrLow_uid33_fpLogETest_in <= frac_uid19_fpLogETest_b;
zAddrLow_uid33_fpLogETest_b <= zAddrLow_uid33_fpLogETest_in(51 downto 42);
--addr_uid34_fpLogETest(BITJOIN,33)@0
addr_uid34_fpLogETest_q <= c_uid31_fpLogETest_q & zAddrLow_uid33_fpLogETest_b;
--reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0(REG,322)@0
reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q <= addr_uid34_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid120_natLogTabGen_lutmem(DUALMEM,316)@1
memoryC4_uid120_natLogTabGen_lutmem_ia <= (others => '0');
memoryC4_uid120_natLogTabGen_lutmem_aa <= (others => '0');
memoryC4_uid120_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC4_uid120_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 11,
numwords_a => 2048,
width_b => 7,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC4_uid120_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC4_uid120_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC4_uid120_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC4_uid120_natLogTabGen_lutmem_iq,
address_a => memoryC4_uid120_natLogTabGen_lutmem_aa,
data_a => memoryC4_uid120_natLogTabGen_lutmem_ia
);
memoryC4_uid120_natLogTabGen_lutmem_reset0 <= areset;
memoryC4_uid120_natLogTabGen_lutmem_q <= memoryC4_uid120_natLogTabGen_lutmem_iq(6 downto 0);
--reg_memoryC4_uid120_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_1(REG,355)@3
reg_memoryC4_uid120_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC4_uid120_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC4_uid120_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_1_q <= memoryC4_uid120_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC4_uid119_natLogTabGen_lutmem(DUALMEM,315)@1
memoryC4_uid119_natLogTabGen_lutmem_ia <= (others => '0');
memoryC4_uid119_natLogTabGen_lutmem_aa <= (others => '0');
memoryC4_uid119_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC4_uid119_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC4_uid119_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC4_uid119_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC4_uid119_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC4_uid119_natLogTabGen_lutmem_iq,
address_a => memoryC4_uid119_natLogTabGen_lutmem_aa,
data_a => memoryC4_uid119_natLogTabGen_lutmem_ia
);
memoryC4_uid119_natLogTabGen_lutmem_reset0 <= areset;
memoryC4_uid119_natLogTabGen_lutmem_q <= memoryC4_uid119_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC4_uid119_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_0(REG,354)@3
reg_memoryC4_uid119_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC4_uid119_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC4_uid119_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_0_q <= memoryC4_uid119_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid121_natLogTabGen(BITJOIN,120)@4
os_uid121_natLogTabGen_q <= reg_memoryC4_uid120_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_1_q & reg_memoryC4_uid119_natLogTabGen_lutmem_0_to_os_uid121_natLogTabGen_0_q;
--reg_os_uid121_natLogTabGen_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_1(REG,357)@4
reg_os_uid121_natLogTabGen_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_os_uid121_natLogTabGen_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_1_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_os_uid121_natLogTabGen_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_1_q <= os_uid121_natLogTabGen_q;
END IF;
END IF;
END PROCESS;
--yT1_uid122_natLogPolyEval(BITSELECT,121)@4
yT1_uid122_natLogPolyEval_in <= zPPolyEval_uid35_fpLogETest_b;
yT1_uid122_natLogPolyEval_b <= yT1_uid122_natLogPolyEval_in(41 downto 25);
--reg_yT1_uid122_natLogPolyEval_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_0(REG,356)@4
reg_yT1_uid122_natLogPolyEval_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid122_natLogPolyEval_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_0_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid122_natLogPolyEval_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_0_q <= yT1_uid122_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid230_pT1_uid123_natLogPolyEval(MULT,229)@5
prodXY_uid230_pT1_uid123_natLogPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid230_pT1_uid123_natLogPolyEval_a),18)) * SIGNED(prodXY_uid230_pT1_uid123_natLogPolyEval_b);
prodXY_uid230_pT1_uid123_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid230_pT1_uid123_natLogPolyEval_a <= (others => '0');
prodXY_uid230_pT1_uid123_natLogPolyEval_b <= (others => '0');
prodXY_uid230_pT1_uid123_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid230_pT1_uid123_natLogPolyEval_a <= reg_yT1_uid122_natLogPolyEval_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_0_q;
prodXY_uid230_pT1_uid123_natLogPolyEval_b <= reg_os_uid121_natLogTabGen_0_to_prodXY_uid230_pT1_uid123_natLogPolyEval_1_q;
prodXY_uid230_pT1_uid123_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid230_pT1_uid123_natLogPolyEval_pr,34));
END IF;
END IF;
END PROCESS;
prodXY_uid230_pT1_uid123_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid230_pT1_uid123_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid230_pT1_uid123_natLogPolyEval_q <= prodXY_uid230_pT1_uid123_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid231_pT1_uid123_natLogPolyEval(BITSELECT,230)@8
prodXYTruncFR_uid231_pT1_uid123_natLogPolyEval_in <= prodXY_uid230_pT1_uid123_natLogPolyEval_q;
prodXYTruncFR_uid231_pT1_uid123_natLogPolyEval_b <= prodXYTruncFR_uid231_pT1_uid123_natLogPolyEval_in(33 downto 15);
--highBBits_uid125_natLogPolyEval(BITSELECT,124)@8
highBBits_uid125_natLogPolyEval_in <= prodXYTruncFR_uid231_pT1_uid123_natLogPolyEval_b;
highBBits_uid125_natLogPolyEval_b <= highBBits_uid125_natLogPolyEval_in(18 downto 1);
--ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_nor(LOGICAL,1029)
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_nor_b <= ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_sticky_ena_q;
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_nor_q <= not (ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_nor_a or ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_nor_b);
--ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_sticky_ena(REG,1030)
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_nor_q = "1") THEN
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_sticky_ena_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_enaAnd(LOGICAL,1031)
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_enaAnd_a <= ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_sticky_ena_q;
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_enaAnd_b <= en;
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_enaAnd_q <= ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_enaAnd_a and ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_enaAnd_b;
--memoryC3_uid117_natLogTabGen_lutmem(DUALMEM,314)@1
memoryC3_uid117_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid117_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid117_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC3_uid117_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC3_uid117_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid117_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid117_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid117_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid117_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid117_natLogTabGen_lutmem_ia
);
memoryC3_uid117_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid117_natLogTabGen_lutmem_q <= memoryC3_uid117_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC3_uid117_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_2(REG,363)@3
reg_memoryC3_uid117_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid117_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid117_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_2_q <= memoryC3_uid117_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid116_natLogTabGen_lutmem(DUALMEM,313)@1
memoryC3_uid116_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid116_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid116_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC3_uid116_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC3_uid116_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid116_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid116_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid116_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid116_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid116_natLogTabGen_lutmem_ia
);
memoryC3_uid116_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid116_natLogTabGen_lutmem_q <= memoryC3_uid116_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC3_uid116_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_1(REG,362)@3
reg_memoryC3_uid116_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid116_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid116_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_1_q <= memoryC3_uid116_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC3_uid115_natLogTabGen_lutmem(DUALMEM,312)@1
memoryC3_uid115_natLogTabGen_lutmem_ia <= (others => '0');
memoryC3_uid115_natLogTabGen_lutmem_aa <= (others => '0');
memoryC3_uid115_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC3_uid115_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC3_uid115_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC3_uid115_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC3_uid115_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC3_uid115_natLogTabGen_lutmem_iq,
address_a => memoryC3_uid115_natLogTabGen_lutmem_aa,
data_a => memoryC3_uid115_natLogTabGen_lutmem_ia
);
memoryC3_uid115_natLogTabGen_lutmem_reset0 <= areset;
memoryC3_uid115_natLogTabGen_lutmem_q <= memoryC3_uid115_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC3_uid115_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_0(REG,361)@3
reg_memoryC3_uid115_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC3_uid115_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC3_uid115_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_0_q <= memoryC3_uid115_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid118_natLogTabGen(BITJOIN,117)@4
os_uid118_natLogTabGen_q <= reg_memoryC3_uid117_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_2_q & reg_memoryC3_uid116_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_1_q & reg_memoryC3_uid115_natLogTabGen_lutmem_0_to_os_uid118_natLogTabGen_0_q;
--ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_inputreg(DELAY,1021)
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 28, depth => 1 )
PORT MAP ( xin => os_uid118_natLogTabGen_q, xout => ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem(DUALMEM,1022)
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_ia <= ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_inputreg_q;
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_aa <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q;
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_ab <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q;
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 28,
widthad_a => 1,
numwords_a => 2,
width_b => 28,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_iq,
address_a => ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_aa,
data_a => ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_ia
);
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_q <= ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_iq(27 downto 0);
--sumAHighB_uid126_natLogPolyEval(ADD,125)@8
sumAHighB_uid126_natLogPolyEval_a <= STD_LOGIC_VECTOR((28 downto 28 => ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_q(27)) & ld_os_uid118_natLogTabGen_q_to_sumAHighB_uid126_natLogPolyEval_a_replace_mem_q);
sumAHighB_uid126_natLogPolyEval_b <= STD_LOGIC_VECTOR((28 downto 18 => highBBits_uid125_natLogPolyEval_b(17)) & highBBits_uid125_natLogPolyEval_b);
sumAHighB_uid126_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid126_natLogPolyEval_a) + SIGNED(sumAHighB_uid126_natLogPolyEval_b));
sumAHighB_uid126_natLogPolyEval_q <= sumAHighB_uid126_natLogPolyEval_o(28 downto 0);
--lowRangeB_uid124_natLogPolyEval(BITSELECT,123)@8
lowRangeB_uid124_natLogPolyEval_in <= prodXYTruncFR_uid231_pT1_uid123_natLogPolyEval_b(0 downto 0);
lowRangeB_uid124_natLogPolyEval_b <= lowRangeB_uid124_natLogPolyEval_in(0 downto 0);
--s1_uid124_uid127_natLogPolyEval(BITJOIN,126)@8
s1_uid124_uid127_natLogPolyEval_q <= sumAHighB_uid126_natLogPolyEval_q & lowRangeB_uid124_natLogPolyEval_b;
--sSM1H_uid239_pT2_uid129_natLogPolyEval(BITSELECT,238)@8
sSM1H_uid239_pT2_uid129_natLogPolyEval_in <= s1_uid124_uid127_natLogPolyEval_q;
sSM1H_uid239_pT2_uid129_natLogPolyEval_b <= sSM1H_uid239_pT2_uid129_natLogPolyEval_in(29 downto 24);
--reg_sSM1H_uid239_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_0(REG,368)@8
reg_sSM1H_uid239_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM1H_uid239_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM1H_uid239_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_0_q <= sSM1H_uid239_pT2_uid129_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--sm1_uid241_pT2_uid129_natLogPolyEval(MULT,240)@9
sm1_uid241_pT2_uid129_natLogPolyEval_pr <= SIGNED(sm1_uid241_pT2_uid129_natLogPolyEval_a) * signed(resize(UNSIGNED(sm1_uid241_pT2_uid129_natLogPolyEval_b),2));
sm1_uid241_pT2_uid129_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm1_uid241_pT2_uid129_natLogPolyEval_a <= (others => '0');
sm1_uid241_pT2_uid129_natLogPolyEval_b <= (others => '0');
sm1_uid241_pT2_uid129_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm1_uid241_pT2_uid129_natLogPolyEval_a <= reg_sSM1H_uid239_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_0_q;
sm1_uid241_pT2_uid129_natLogPolyEval_b <= ld_reg_sSM1W_uid240_pT2_uid129_natLogPolyEval_0_to_sm1_uid241_pT2_uid129_natLogPolyEval_1_q_to_sm1_uid241_pT2_uid129_natLogPolyEval_b_q;
sm1_uid241_pT2_uid129_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(sm1_uid241_pT2_uid129_natLogPolyEval_pr,7));
END IF;
END IF;
END PROCESS;
sm1_uid241_pT2_uid129_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm1_uid241_pT2_uid129_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm1_uid241_pT2_uid129_natLogPolyEval_q <= sm1_uid241_pT2_uid129_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--GND(CONSTANT,0)
GND_q <= "0";
--pad_sm1_uid241_uid243_pT2_uid129_natLogPolyEval(BITJOIN,242)@12
pad_sm1_uid241_uid243_pT2_uid129_natLogPolyEval_q <= sm1_uid241_pT2_uid129_natLogPolyEval_q & STD_LOGIC_VECTOR((19 downto 1 => GND_q(0)) & GND_q);
--sSM0W_uid237_pT2_uid129_natLogPolyEval(BITSELECT,236)@4
sSM0W_uid237_pT2_uid129_natLogPolyEval_in <= yT2_uid128_natLogPolyEval_b;
sSM0W_uid237_pT2_uid129_natLogPolyEval_b <= sSM0W_uid237_pT2_uid129_natLogPolyEval_in(27 downto 24);
--ld_sSM0W_uid237_pT2_uid129_natLogPolyEval_b_to_reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1_a(DELAY,822)@4
ld_sSM0W_uid237_pT2_uid129_natLogPolyEval_b_to_reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1_a : dspba_delay
GENERIC MAP ( width => 4, depth => 4 )
PORT MAP ( xin => sSM0W_uid237_pT2_uid129_natLogPolyEval_b, xout => ld_sSM0W_uid237_pT2_uid129_natLogPolyEval_b_to_reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1(REG,367)@8
reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1_q <= ld_sSM0W_uid237_pT2_uid129_natLogPolyEval_b_to_reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1_a_q;
END IF;
END IF;
END PROCESS;
--sSM0H_uid236_pT2_uid129_natLogPolyEval(BITSELECT,235)@8
sSM0H_uid236_pT2_uid129_natLogPolyEval_in <= s1_uid124_uid127_natLogPolyEval_q(2 downto 0);
sSM0H_uid236_pT2_uid129_natLogPolyEval_b <= sSM0H_uid236_pT2_uid129_natLogPolyEval_in(2 downto 0);
--reg_sSM0H_uid236_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_0(REG,366)@8
reg_sSM0H_uid236_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sSM0H_uid236_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sSM0H_uid236_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_0_q <= sSM0H_uid236_pT2_uid129_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--sm0_uid238_pT2_uid129_natLogPolyEval(MULT,237)@9
sm0_uid238_pT2_uid129_natLogPolyEval_pr <= UNSIGNED(sm0_uid238_pT2_uid129_natLogPolyEval_a) * UNSIGNED(sm0_uid238_pT2_uid129_natLogPolyEval_b);
sm0_uid238_pT2_uid129_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid238_pT2_uid129_natLogPolyEval_a <= (others => '0');
sm0_uid238_pT2_uid129_natLogPolyEval_b <= (others => '0');
sm0_uid238_pT2_uid129_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid238_pT2_uid129_natLogPolyEval_a <= reg_sSM0H_uid236_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_0_q;
sm0_uid238_pT2_uid129_natLogPolyEval_b <= reg_sSM0W_uid237_pT2_uid129_natLogPolyEval_0_to_sm0_uid238_pT2_uid129_natLogPolyEval_1_q;
sm0_uid238_pT2_uid129_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(sm0_uid238_pT2_uid129_natLogPolyEval_pr);
END IF;
END IF;
END PROCESS;
sm0_uid238_pT2_uid129_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sm0_uid238_pT2_uid129_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
sm0_uid238_pT2_uid129_natLogPolyEval_q <= sm0_uid238_pT2_uid129_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--pad_sm0_uid238_uid242_pT2_uid129_natLogPolyEval(BITJOIN,241)@12
pad_sm0_uid238_uid242_pT2_uid129_natLogPolyEval_q <= sm0_uid238_pT2_uid129_natLogPolyEval_q & STD_LOGIC_VECTOR((19 downto 1 => GND_q(0)) & GND_q);
--yTop27Bits_uid234_pT2_uid129_natLogPolyEval(BITSELECT,233)@8
yTop27Bits_uid234_pT2_uid129_natLogPolyEval_in <= s1_uid124_uid127_natLogPolyEval_q;
yTop27Bits_uid234_pT2_uid129_natLogPolyEval_b <= yTop27Bits_uid234_pT2_uid129_natLogPolyEval_in(29 downto 3);
--reg_yTop27Bits_uid234_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_1(REG,365)@8
reg_yTop27Bits_uid234_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid234_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid234_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_1_q <= yTop27Bits_uid234_pT2_uid129_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_nor(LOGICAL,1151)
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_nor_b <= ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_sticky_ena_q;
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_nor_q <= not (ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_nor_a or ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_nor_b);
--ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_sticky_ena(REG,1152)
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_nor_q = "1") THEN
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_sticky_ena_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_enaAnd(LOGICAL,1153)
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_enaAnd_a <= ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_sticky_ena_q;
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_enaAnd_b <= en;
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_enaAnd_q <= ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_enaAnd_a and ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_enaAnd_b;
--xTop27Bits_uid233_pT2_uid129_natLogPolyEval(BITSELECT,232)@4
xTop27Bits_uid233_pT2_uid129_natLogPolyEval_in <= yT2_uid128_natLogPolyEval_b;
xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b <= xTop27Bits_uid233_pT2_uid129_natLogPolyEval_in(27 downto 1);
--ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_inputreg(DELAY,1143)
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b, xout => ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem(DUALMEM,1144)
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_ia <= ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_inputreg_q;
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_aa <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q;
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_ab <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q;
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 27,
widthad_a => 1,
numwords_a => 2,
width_b => 27,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_iq,
address_a => ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_aa,
data_a => ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_ia
);
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_reset0 <= areset;
ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_q <= ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_iq(26 downto 0);
--reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0(REG,364)@8
reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_q <= ld_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_b_to_reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--topProd_uid235_pT2_uid129_natLogPolyEval(MULT,234)@9
topProd_uid235_pT2_uid129_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid235_pT2_uid129_natLogPolyEval_a),28)) * SIGNED(topProd_uid235_pT2_uid129_natLogPolyEval_b);
topProd_uid235_pT2_uid129_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid235_pT2_uid129_natLogPolyEval_a <= (others => '0');
topProd_uid235_pT2_uid129_natLogPolyEval_b <= (others => '0');
topProd_uid235_pT2_uid129_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid235_pT2_uid129_natLogPolyEval_a <= reg_xTop27Bits_uid233_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_0_q;
topProd_uid235_pT2_uid129_natLogPolyEval_b <= reg_yTop27Bits_uid234_pT2_uid129_natLogPolyEval_0_to_topProd_uid235_pT2_uid129_natLogPolyEval_1_q;
topProd_uid235_pT2_uid129_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid235_pT2_uid129_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid235_pT2_uid129_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid235_pT2_uid129_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid235_pT2_uid129_natLogPolyEval_q <= topProd_uid235_pT2_uid129_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--add0_uid242_pT2_uid129_natLogPolyEval(ADDSUB3,243)@12
add0_uid242_pT2_uid129_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid235_pT2_uid129_natLogPolyEval_q(53)) & topProd_uid235_pT2_uid129_natLogPolyEval_q);
add0_uid242_pT2_uid129_natLogPolyEval_b <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000" & pad_sm0_uid238_uid242_pT2_uid129_natLogPolyEval_q);
add0_uid242_pT2_uid129_natLogPolyEval_c <= STD_LOGIC_VECTOR((54 downto 27 => pad_sm1_uid241_uid243_pT2_uid129_natLogPolyEval_q(26)) & pad_sm1_uid241_uid243_pT2_uid129_natLogPolyEval_q);
add0_uid242_pT2_uid129_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(add0_uid242_pT2_uid129_natLogPolyEval_a) + SIGNED(add0_uid242_pT2_uid129_natLogPolyEval_b) + SIGNED(add0_uid242_pT2_uid129_natLogPolyEval_c));
add0_uid242_pT2_uid129_natLogPolyEval_q <= add0_uid242_pT2_uid129_natLogPolyEval_o(54 downto 0);
--R_uid245_pT2_uid129_natLogPolyEval(BITSELECT,244)@12
R_uid245_pT2_uid129_natLogPolyEval_in <= add0_uid242_pT2_uid129_natLogPolyEval_q(53 downto 0);
R_uid245_pT2_uid129_natLogPolyEval_b <= R_uid245_pT2_uid129_natLogPolyEval_in(53 downto 24);
--reg_R_uid245_pT2_uid129_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_1(REG,371)@12
reg_R_uid245_pT2_uid129_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid245_pT2_uid129_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_1_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid245_pT2_uid129_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_1_q <= R_uid245_pT2_uid129_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_nor(LOGICAL,1042)
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_nor_b <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_sticky_ena_q;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_nor_q <= not (ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_nor_a or ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_nor_b);
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_mem_top(CONSTANT,1038)
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_mem_top_q <= "0101";
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmp(LOGICAL,1039)
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmp_a <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_mem_top_q;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmp_a = ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmpReg(REG,1040)
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmpReg_q <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_sticky_ena(REG,1043)
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_sticky_ena_q <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_enaAnd(LOGICAL,1044)
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_enaAnd_a <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_sticky_ena_q;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_enaAnd_q <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_enaAnd_a and ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_enaAnd_b;
--memoryC2_uid113_natLogTabGen_lutmem(DUALMEM,311)@1
memoryC2_uid113_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid113_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid113_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC2_uid113_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC2_uid113_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid113_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid113_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid113_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid113_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid113_natLogTabGen_lutmem_ia
);
memoryC2_uid113_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid113_natLogTabGen_lutmem_q <= memoryC2_uid113_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC2_uid113_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_3(REG,351)@3
reg_memoryC2_uid113_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid113_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid113_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_3_q <= memoryC2_uid113_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid112_natLogTabGen_lutmem(DUALMEM,310)@1
memoryC2_uid112_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid112_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid112_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC2_uid112_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC2_uid112_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid112_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid112_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid112_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid112_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid112_natLogTabGen_lutmem_ia
);
memoryC2_uid112_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid112_natLogTabGen_lutmem_q <= memoryC2_uid112_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid112_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_2(REG,350)@3
reg_memoryC2_uid112_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid112_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid112_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_2_q <= memoryC2_uid112_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid111_natLogTabGen_lutmem(DUALMEM,309)@1
memoryC2_uid111_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid111_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid111_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC2_uid111_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC2_uid111_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid111_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid111_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid111_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid111_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid111_natLogTabGen_lutmem_ia
);
memoryC2_uid111_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid111_natLogTabGen_lutmem_q <= memoryC2_uid111_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid111_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_1(REG,349)@3
reg_memoryC2_uid111_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid111_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid111_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_1_q <= memoryC2_uid111_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid110_natLogTabGen_lutmem(DUALMEM,308)@1
memoryC2_uid110_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid110_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid110_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC2_uid110_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC2_uid110_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid110_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid110_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid110_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid110_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid110_natLogTabGen_lutmem_ia
);
memoryC2_uid110_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid110_natLogTabGen_lutmem_q <= memoryC2_uid110_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC2_uid110_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_0(REG,348)@3
reg_memoryC2_uid110_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid110_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid110_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_0_q <= memoryC2_uid110_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid114_natLogTabGen(BITJOIN,113)@4
os_uid114_natLogTabGen_q <= reg_memoryC2_uid113_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_3_q & reg_memoryC2_uid112_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_2_q & reg_memoryC2_uid111_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_1_q & reg_memoryC2_uid110_natLogTabGen_lutmem_0_to_os_uid114_natLogTabGen_0_q;
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_inputreg(DELAY,1032)
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 38, depth => 1 )
PORT MAP ( xin => os_uid114_natLogTabGen_q, xout => ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt(COUNTER,1034)
-- every=1, low=0, high=5, step=1, init=1
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_i = 4 THEN
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_i - 5;
ELSE
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_i,3));
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdreg(REG,1035)
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux(MUX,1036)
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux_s, ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdreg_q, ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem(DUALMEM,1033)
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_ia <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_inputreg_q;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_aa <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_ab <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 38,
widthad_a => 3,
numwords_a => 6,
width_b => 38,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_q <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_iq(37 downto 0);
--rndBit_uid130_natLogPolyEval(CONSTANT,129)
rndBit_uid130_natLogPolyEval_q <= "01";
--cIncludingRoundingBit_uid131_natLogPolyEval(BITJOIN,130)@12
cIncludingRoundingBit_uid131_natLogPolyEval_q <= ld_os_uid114_natLogTabGen_q_to_cIncludingRoundingBit_uid131_natLogPolyEval_b_replace_mem_q & rndBit_uid130_natLogPolyEval_q;
--reg_cIncludingRoundingBit_uid131_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_0(REG,370)@12
reg_cIncludingRoundingBit_uid131_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid131_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid131_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_0_q <= cIncludingRoundingBit_uid131_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts2_uid132_natLogPolyEval(ADD,131)@13
ts2_uid132_natLogPolyEval_a <= STD_LOGIC_VECTOR((40 downto 40 => reg_cIncludingRoundingBit_uid131_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_0_q(39)) & reg_cIncludingRoundingBit_uid131_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_0_q);
ts2_uid132_natLogPolyEval_b <= STD_LOGIC_VECTOR((40 downto 30 => reg_R_uid245_pT2_uid129_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_1_q(29)) & reg_R_uid245_pT2_uid129_natLogPolyEval_0_to_ts2_uid132_natLogPolyEval_1_q);
ts2_uid132_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts2_uid132_natLogPolyEval_a) + SIGNED(ts2_uid132_natLogPolyEval_b));
ts2_uid132_natLogPolyEval_q <= ts2_uid132_natLogPolyEval_o(40 downto 0);
--s2_uid133_natLogPolyEval(BITSELECT,132)@13
s2_uid133_natLogPolyEval_in <= ts2_uid132_natLogPolyEval_q;
s2_uid133_natLogPolyEval_b <= s2_uid133_natLogPolyEval_in(40 downto 1);
--yTop18Bits_uid252_pT3_uid135_natLogPolyEval(BITSELECT,251)@13
yTop18Bits_uid252_pT3_uid135_natLogPolyEval_in <= s2_uid133_natLogPolyEval_b;
yTop18Bits_uid252_pT3_uid135_natLogPolyEval_b <= yTop18Bits_uid252_pT3_uid135_natLogPolyEval_in(39 downto 22);
--reg_yTop18Bits_uid252_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_9(REG,375)@13
reg_yTop18Bits_uid252_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop18Bits_uid252_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_9_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop18Bits_uid252_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_9_q <= yTop18Bits_uid252_pT3_uid135_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_nor(LOGICAL,1055)
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_nor_b <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_nor_q <= not (ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_nor_a or ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_nor_b);
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_mem_top(CONSTANT,1051)
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_mem_top_q <= "0110";
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmp(LOGICAL,1052)
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmp_a <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_mem_top_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux_q);
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmp_a = ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmp_b else "0";
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmpReg(REG,1053)
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_sticky_ena(REG,1056)
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_enaAnd(LOGICAL,1057)
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_enaAnd_b <= en;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_enaAnd_a and ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_inputreg(DELAY,1045)
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 42, depth => 1 )
PORT MAP ( xin => zPPolyEval_uid35_fpLogETest_b, xout => ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt(COUNTER,1047)
-- every=1, low=0, high=6, step=1, init=1
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_i = 5 THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_i - 6;
ELSE
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_i,3));
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdreg(REG,1048)
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux(MUX,1049)
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux_s <= en;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem(DUALMEM,1046)
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_ia <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_inputreg_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdreg_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_rdmux_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 42,
widthad_a => 3,
numwords_a => 7,
width_b => 42,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_iq(41 downto 0);
--yT3_uid134_natLogPolyEval(BITSELECT,133)@13
yT3_uid134_natLogPolyEval_in <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_replace_mem_q;
yT3_uid134_natLogPolyEval_b <= yT3_uid134_natLogPolyEval_in(41 downto 4);
--xBottomBits_uid251_pT3_uid135_natLogPolyEval(BITSELECT,250)@13
xBottomBits_uid251_pT3_uid135_natLogPolyEval_in <= yT3_uid134_natLogPolyEval_b(10 downto 0);
xBottomBits_uid251_pT3_uid135_natLogPolyEval_b <= xBottomBits_uid251_pT3_uid135_natLogPolyEval_in(10 downto 0);
--pad_xBottomBits_uid251_uid254_pT3_uid135_natLogPolyEval(BITJOIN,253)@13
pad_xBottomBits_uid251_uid254_pT3_uid135_natLogPolyEval_q <= xBottomBits_uid251_pT3_uid135_natLogPolyEval_b & STD_LOGIC_VECTOR((5 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid251_uid254_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_7(REG,374)@13
reg_pad_xBottomBits_uid251_uid254_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid251_uid254_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_7_q <= "00000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid251_uid254_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_7_q <= pad_xBottomBits_uid251_uid254_pT3_uid135_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid250_pT3_uid135_natLogPolyEval(BITSELECT,249)@13
yBottomBits_uid250_pT3_uid135_natLogPolyEval_in <= s2_uid133_natLogPolyEval_b(12 downto 0);
yBottomBits_uid250_pT3_uid135_natLogPolyEval_b <= yBottomBits_uid250_pT3_uid135_natLogPolyEval_in(12 downto 0);
--spad_yBottomBits_uid250_uid253_pT3_uid135_natLogPolyEval(BITJOIN,252)@13
spad_yBottomBits_uid250_uid253_pT3_uid135_natLogPolyEval_q <= GND_q & yBottomBits_uid250_pT3_uid135_natLogPolyEval_b;
--pad_yBottomBits_uid250_uid255_pT3_uid135_natLogPolyEval(BITJOIN,254)@13
pad_yBottomBits_uid250_uid255_pT3_uid135_natLogPolyEval_q <= spad_yBottomBits_uid250_uid253_pT3_uid135_natLogPolyEval_q & STD_LOGIC_VECTOR((3 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid250_uid255_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_6(REG,373)@13
reg_pad_yBottomBits_uid250_uid255_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid250_uid255_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_6_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid250_uid255_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_6_q <= pad_yBottomBits_uid250_uid255_pT3_uid135_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--xTop18Bits_uid249_pT3_uid135_natLogPolyEval(BITSELECT,248)@13
xTop18Bits_uid249_pT3_uid135_natLogPolyEval_in <= yT3_uid134_natLogPolyEval_b;
xTop18Bits_uid249_pT3_uid135_natLogPolyEval_b <= xTop18Bits_uid249_pT3_uid135_natLogPolyEval_in(37 downto 20);
--reg_xTop18Bits_uid249_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_4(REG,372)@13
reg_xTop18Bits_uid249_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop18Bits_uid249_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_4_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop18Bits_uid249_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_4_q <= xTop18Bits_uid249_pT3_uid135_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma(CHAINMULTADD,317)@14
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_a(0),19));
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_a(1),19));
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_p(0) <= multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_l(0) * multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_c(0);
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_p(1) <= multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_l(1) * multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_c(1);
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_p(1),38);
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_x(0) <= multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_w(0);
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_y(0) <= multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_x(0);
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop18Bits_uid249_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_4_q),18);
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid251_uid254_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_7_q),18);
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid250_uid255_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_6_q),18);
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop18Bits_uid252_pT3_uid135_natLogPolyEval_0_to_multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_9_q),18);
IF (en = "1") THEN
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_s(0) <= multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_y(0);
END IF;
END IF;
END PROCESS;
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 37, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_s(0)(36 downto 0)), xout => multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval(BITSELECT,256)@17
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_in <= multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_cma_q;
multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_b <= multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_in(36 downto 4);
--highBBits_uid259_pT3_uid135_natLogPolyEval(BITSELECT,258)@17
highBBits_uid259_pT3_uid135_natLogPolyEval_in <= multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_b;
highBBits_uid259_pT3_uid135_natLogPolyEval_b <= highBBits_uid259_pT3_uid135_natLogPolyEval_in(32 downto 4);
--yTop27Bits_uid247_pT3_uid135_natLogPolyEval(BITSELECT,246)@13
yTop27Bits_uid247_pT3_uid135_natLogPolyEval_in <= s2_uid133_natLogPolyEval_b;
yTop27Bits_uid247_pT3_uid135_natLogPolyEval_b <= yTop27Bits_uid247_pT3_uid135_natLogPolyEval_in(39 downto 13);
--reg_yTop27Bits_uid247_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_1(REG,377)@13
reg_yTop27Bits_uid247_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid247_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid247_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_1_q <= yTop27Bits_uid247_pT3_uid135_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--xTop27Bits_uid246_pT3_uid135_natLogPolyEval(BITSELECT,245)@13
xTop27Bits_uid246_pT3_uid135_natLogPolyEval_in <= yT3_uid134_natLogPolyEval_b;
xTop27Bits_uid246_pT3_uid135_natLogPolyEval_b <= xTop27Bits_uid246_pT3_uid135_natLogPolyEval_in(37 downto 11);
--reg_xTop27Bits_uid246_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_0(REG,376)@13
reg_xTop27Bits_uid246_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid246_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid246_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_0_q <= xTop27Bits_uid246_pT3_uid135_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--topProd_uid248_pT3_uid135_natLogPolyEval(MULT,247)@14
topProd_uid248_pT3_uid135_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid248_pT3_uid135_natLogPolyEval_a),28)) * SIGNED(topProd_uid248_pT3_uid135_natLogPolyEval_b);
topProd_uid248_pT3_uid135_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid248_pT3_uid135_natLogPolyEval_a <= (others => '0');
topProd_uid248_pT3_uid135_natLogPolyEval_b <= (others => '0');
topProd_uid248_pT3_uid135_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid248_pT3_uid135_natLogPolyEval_a <= reg_xTop27Bits_uid246_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_0_q;
topProd_uid248_pT3_uid135_natLogPolyEval_b <= reg_yTop27Bits_uid247_pT3_uid135_natLogPolyEval_0_to_topProd_uid248_pT3_uid135_natLogPolyEval_1_q;
topProd_uid248_pT3_uid135_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid248_pT3_uid135_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid248_pT3_uid135_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid248_pT3_uid135_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid248_pT3_uid135_natLogPolyEval_q <= topProd_uid248_pT3_uid135_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid260_pT3_uid135_natLogPolyEval(ADD,259)@17
sumAHighB_uid260_pT3_uid135_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid248_pT3_uid135_natLogPolyEval_q(53)) & topProd_uid248_pT3_uid135_natLogPolyEval_q);
sumAHighB_uid260_pT3_uid135_natLogPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid259_pT3_uid135_natLogPolyEval_b(28)) & highBBits_uid259_pT3_uid135_natLogPolyEval_b);
sumAHighB_uid260_pT3_uid135_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid260_pT3_uid135_natLogPolyEval_a) + SIGNED(sumAHighB_uid260_pT3_uid135_natLogPolyEval_b));
sumAHighB_uid260_pT3_uid135_natLogPolyEval_q <= sumAHighB_uid260_pT3_uid135_natLogPolyEval_o(54 downto 0);
--lowRangeB_uid258_pT3_uid135_natLogPolyEval(BITSELECT,257)@17
lowRangeB_uid258_pT3_uid135_natLogPolyEval_in <= multSumOfTwo18_uid253_pT3_uid135_natLogPolyEval_b(3 downto 0);
lowRangeB_uid258_pT3_uid135_natLogPolyEval_b <= lowRangeB_uid258_pT3_uid135_natLogPolyEval_in(3 downto 0);
--add0_uid258_uid261_pT3_uid135_natLogPolyEval(BITJOIN,260)@17
add0_uid258_uid261_pT3_uid135_natLogPolyEval_q <= sumAHighB_uid260_pT3_uid135_natLogPolyEval_q & lowRangeB_uid258_pT3_uid135_natLogPolyEval_b;
--R_uid262_pT3_uid135_natLogPolyEval(BITSELECT,261)@17
R_uid262_pT3_uid135_natLogPolyEval_in <= add0_uid258_uid261_pT3_uid135_natLogPolyEval_q(57 downto 0);
R_uid262_pT3_uid135_natLogPolyEval_b <= R_uid262_pT3_uid135_natLogPolyEval_in(57 downto 17);
--reg_R_uid262_pT3_uid135_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_1(REG,379)@17
reg_R_uid262_pT3_uid135_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid262_pT3_uid135_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_1_q <= "00000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid262_pT3_uid135_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_1_q <= R_uid262_pT3_uid135_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_nor(LOGICAL,1068)
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_nor_b <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_sticky_ena_q;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_nor_q <= not (ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_nor_a or ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_nor_b);
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_mem_top(CONSTANT,1064)
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_mem_top_q <= "01010";
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmp(LOGICAL,1065)
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmp_a <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_mem_top_q;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmp_a = ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmpReg(REG,1066)
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmpReg_q <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_sticky_ena(REG,1069)
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_sticky_ena_q <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_enaAnd(LOGICAL,1070)
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_enaAnd_a <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_sticky_ena_q;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_enaAnd_q <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_enaAnd_a and ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_enaAnd_b;
--memoryC1_uid108_natLogTabGen_lutmem(DUALMEM,307)@1
memoryC1_uid108_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid108_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid108_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC1_uid108_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 11,
numwords_a => 2048,
width_b => 8,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC1_uid108_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid108_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid108_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid108_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid108_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid108_natLogTabGen_lutmem_ia
);
memoryC1_uid108_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid108_natLogTabGen_lutmem_q <= memoryC1_uid108_natLogTabGen_lutmem_iq(7 downto 0);
--reg_memoryC1_uid108_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_4(REG,343)@3
reg_memoryC1_uid108_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid108_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_4_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid108_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_4_q <= memoryC1_uid108_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid107_natLogTabGen_lutmem(DUALMEM,306)@1
memoryC1_uid107_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid107_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid107_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC1_uid107_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC1_uid107_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid107_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid107_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid107_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid107_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid107_natLogTabGen_lutmem_ia
);
memoryC1_uid107_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid107_natLogTabGen_lutmem_q <= memoryC1_uid107_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid107_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_3(REG,342)@3
reg_memoryC1_uid107_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid107_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_3_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid107_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_3_q <= memoryC1_uid107_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid106_natLogTabGen_lutmem(DUALMEM,305)@1
memoryC1_uid106_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid106_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid106_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC1_uid106_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC1_uid106_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid106_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid106_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid106_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid106_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid106_natLogTabGen_lutmem_ia
);
memoryC1_uid106_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid106_natLogTabGen_lutmem_q <= memoryC1_uid106_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid106_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_2(REG,341)@3
reg_memoryC1_uid106_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid106_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid106_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_2_q <= memoryC1_uid106_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid105_natLogTabGen_lutmem(DUALMEM,304)@1
memoryC1_uid105_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid105_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid105_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC1_uid105_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC1_uid105_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid105_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid105_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid105_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid105_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid105_natLogTabGen_lutmem_ia
);
memoryC1_uid105_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid105_natLogTabGen_lutmem_q <= memoryC1_uid105_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid105_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_1(REG,340)@3
reg_memoryC1_uid105_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid105_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid105_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_1_q <= memoryC1_uid105_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid104_natLogTabGen_lutmem(DUALMEM,303)@1
memoryC1_uid104_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid104_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid104_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC1_uid104_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC1_uid104_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid104_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid104_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid104_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid104_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid104_natLogTabGen_lutmem_ia
);
memoryC1_uid104_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid104_natLogTabGen_lutmem_q <= memoryC1_uid104_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC1_uid104_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_0(REG,339)@3
reg_memoryC1_uid104_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid104_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid104_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_0_q <= memoryC1_uid104_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid109_natLogTabGen(BITJOIN,108)@4
os_uid109_natLogTabGen_q <= reg_memoryC1_uid108_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_4_q & reg_memoryC1_uid107_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_3_q & reg_memoryC1_uid106_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_2_q & reg_memoryC1_uid105_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_1_q & reg_memoryC1_uid104_natLogTabGen_lutmem_0_to_os_uid109_natLogTabGen_0_q;
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_inputreg(DELAY,1058)
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 48, depth => 1 )
PORT MAP ( xin => os_uid109_natLogTabGen_q, xout => ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt(COUNTER,1060)
-- every=1, low=0, high=10, step=1, init=1
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_i = 9 THEN
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_i - 10;
ELSE
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_i,4));
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdreg(REG,1061)
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux(MUX,1062)
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux_s, ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdreg_q, ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem(DUALMEM,1059)
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_ia <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_inputreg_q;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_aa <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_ab <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 48,
widthad_a => 4,
numwords_a => 11,
width_b => 48,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_q <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_iq(47 downto 0);
--cIncludingRoundingBit_uid137_natLogPolyEval(BITJOIN,136)@17
cIncludingRoundingBit_uid137_natLogPolyEval_q <= ld_os_uid109_natLogTabGen_q_to_cIncludingRoundingBit_uid137_natLogPolyEval_b_replace_mem_q & rndBit_uid130_natLogPolyEval_q;
--reg_cIncludingRoundingBit_uid137_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_0(REG,378)@17
reg_cIncludingRoundingBit_uid137_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid137_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_0_q <= "00000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid137_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_0_q <= cIncludingRoundingBit_uid137_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts3_uid138_natLogPolyEval(ADD,137)@18
ts3_uid138_natLogPolyEval_a <= STD_LOGIC_VECTOR((50 downto 50 => reg_cIncludingRoundingBit_uid137_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_0_q(49)) & reg_cIncludingRoundingBit_uid137_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_0_q);
ts3_uid138_natLogPolyEval_b <= STD_LOGIC_VECTOR((50 downto 41 => reg_R_uid262_pT3_uid135_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_1_q(40)) & reg_R_uid262_pT3_uid135_natLogPolyEval_0_to_ts3_uid138_natLogPolyEval_1_q);
ts3_uid138_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid138_natLogPolyEval_a) + SIGNED(ts3_uid138_natLogPolyEval_b));
ts3_uid138_natLogPolyEval_q <= ts3_uid138_natLogPolyEval_o(50 downto 0);
--s3_uid139_natLogPolyEval(BITSELECT,138)@18
s3_uid139_natLogPolyEval_in <= ts3_uid138_natLogPolyEval_q;
s3_uid139_natLogPolyEval_b <= s3_uid139_natLogPolyEval_in(50 downto 1);
--yTop27Bits_uid264_pT4_uid141_natLogPolyEval(BITSELECT,263)@18
yTop27Bits_uid264_pT4_uid141_natLogPolyEval_in <= s3_uid139_natLogPolyEval_b;
yTop27Bits_uid264_pT4_uid141_natLogPolyEval_b <= yTop27Bits_uid264_pT4_uid141_natLogPolyEval_in(49 downto 23);
--reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_9(REG,383)@18
reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_9_q <= yTop27Bits_uid264_pT4_uid141_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_nor(LOGICAL,1140)
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_nor_b <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_sticky_ena_q;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_nor_q <= not (ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_nor_a or ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_nor_b);
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_mem_top(CONSTANT,1136)
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_mem_top_q <= "01011";
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmp(LOGICAL,1137)
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmp_a <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_mem_top_q;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux_q);
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmp_a = ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmp_b else "0";
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmpReg(REG,1138)
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmpReg_q <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_sticky_ena(REG,1141)
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_nor_q = "1") THEN
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_sticky_ena_q <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_enaAnd(LOGICAL,1142)
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_enaAnd_a <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_sticky_ena_q;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_enaAnd_b <= en;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_enaAnd_q <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_enaAnd_a and ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_enaAnd_b;
--xBottomBits_uid267_pT4_uid141_natLogPolyEval(BITSELECT,266)@4
xBottomBits_uid267_pT4_uid141_natLogPolyEval_in <= zPPolyEval_uid35_fpLogETest_b(14 downto 0);
xBottomBits_uid267_pT4_uid141_natLogPolyEval_b <= xBottomBits_uid267_pT4_uid141_natLogPolyEval_in(14 downto 0);
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_inputreg(DELAY,1130)
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => xBottomBits_uid267_pT4_uid141_natLogPolyEval_b, xout => ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt(COUNTER,1132)
-- every=1, low=0, high=11, step=1, init=1
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_i = 10 THEN
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_i - 11;
ELSE
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_i,4));
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdreg(REG,1133)
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux(MUX,1134)
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux_s <= en;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux_s, ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdreg_q, ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem(DUALMEM,1131)
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_ia <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_inputreg_q;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_aa <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdreg_q;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_ab <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_rdmux_q;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 4,
numwords_a => 12,
width_b => 15,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_iq,
address_a => ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_aa,
data_a => ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_ia
);
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_q <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_iq(14 downto 0);
--pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval(BITJOIN,268)@18
pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_q <= ld_xBottomBits_uid267_pT4_uid141_natLogPolyEval_b_to_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_b_replace_mem_q & STD_LOGIC_VECTOR((10 downto 1 => GND_q(0)) & GND_q);
--reg_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_7(REG,382)@18
reg_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_7: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_7_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_7_q <= pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--yBottomBits_uid266_pT4_uid141_natLogPolyEval(BITSELECT,265)@18
yBottomBits_uid266_pT4_uid141_natLogPolyEval_in <= s3_uid139_natLogPolyEval_b(22 downto 0);
yBottomBits_uid266_pT4_uid141_natLogPolyEval_b <= yBottomBits_uid266_pT4_uid141_natLogPolyEval_in(22 downto 0);
--ld_yBottomBits_uid266_pT4_uid141_natLogPolyEval_b_to_spad_yBottomBits_uid266_uid268_pT4_uid141_natLogPolyEval_a(DELAY,704)@18
ld_yBottomBits_uid266_pT4_uid141_natLogPolyEval_b_to_spad_yBottomBits_uid266_uid268_pT4_uid141_natLogPolyEval_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => yBottomBits_uid266_pT4_uid141_natLogPolyEval_b, xout => ld_yBottomBits_uid266_pT4_uid141_natLogPolyEval_b_to_spad_yBottomBits_uid266_uid268_pT4_uid141_natLogPolyEval_a_q, ena => en(0), clk => clk, aclr => areset );
--spad_yBottomBits_uid266_uid268_pT4_uid141_natLogPolyEval(BITJOIN,267)@19
spad_yBottomBits_uid266_uid268_pT4_uid141_natLogPolyEval_q <= GND_q & ld_yBottomBits_uid266_pT4_uid141_natLogPolyEval_b_to_spad_yBottomBits_uid266_uid268_pT4_uid141_natLogPolyEval_a_q;
--pad_yBottomBits_uid266_uid270_pT4_uid141_natLogPolyEval(BITJOIN,269)@19
pad_yBottomBits_uid266_uid270_pT4_uid141_natLogPolyEval_q <= spad_yBottomBits_uid266_uid268_pT4_uid141_natLogPolyEval_q & STD_LOGIC_VECTOR((2 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid266_uid270_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_6(REG,381)@19
reg_pad_yBottomBits_uid266_uid270_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid266_uid270_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_yBottomBits_uid266_uid270_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_6_q <= pad_yBottomBits_uid266_uid270_pT4_uid141_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_nor(LOGICAL,1127)
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_nor_b <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_nor_q <= not (ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_nor_a or ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_nor_b);
--ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_mem_top(CONSTANT,1123)
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_mem_top_q <= "01100";
--ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmp(LOGICAL,1124)
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmp_a <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_mem_top_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux_q);
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmp_a = ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmp_b else "0";
--ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmpReg(REG,1125)
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_sticky_ena(REG,1128)
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_enaAnd(LOGICAL,1129)
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_enaAnd_b <= en;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_enaAnd_a and ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt(COUNTER,1119)
-- every=1, low=0, high=12, step=1, init=1
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_i = 11 THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_i - 12;
ELSE
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_i,4));
--ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdreg(REG,1120)
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux(MUX,1121)
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux_s <= en;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem(DUALMEM,1118)
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_ia <= ld_zPPolyEval_uid35_fpLogETest_b_to_yT3_uid134_natLogPolyEval_a_inputreg_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdreg_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_rdmux_q;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 42,
widthad_a => 4,
numwords_a => 13,
width_b => 42,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_iq(41 downto 0);
--xTop27Bits_uid263_pT4_uid141_natLogPolyEval(BITSELECT,262)@19
xTop27Bits_uid263_pT4_uid141_natLogPolyEval_in <= ld_zPPolyEval_uid35_fpLogETest_b_to_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_a_replace_mem_q;
xTop27Bits_uid263_pT4_uid141_natLogPolyEval_b <= xTop27Bits_uid263_pT4_uid141_natLogPolyEval_in(41 downto 15);
--reg_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_4(REG,380)@19
reg_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_4_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_4_q <= xTop27Bits_uid263_pT4_uid141_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma(CHAINMULTADD,318)@20
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_l(0) <= SIGNED(RESIZE(multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_a(0),28));
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_l(1) <= SIGNED(RESIZE(multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_a(1),28));
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_p(0) <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_l(0) * multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_c(0);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_p(1) <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_l(1) * multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_c(1);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_p(0),56);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_p(1),56);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_x(0) <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_w(0);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_x(1) <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_w(1);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_y(0) <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_s(1) + multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_x(0);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_y(1) <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_x(1);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_a(0) <= RESIZE(UNSIGNED(reg_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_4_q),27);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_a(1) <= RESIZE(UNSIGNED(reg_pad_xBottomBits_uid267_uid269_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_7_q),27);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_c(0) <= RESIZE(SIGNED(reg_pad_yBottomBits_uid266_uid270_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_6_q),27);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_c(1) <= RESIZE(SIGNED(reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_9_q),27);
IF (en = "1") THEN
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_s(0) <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_y(0);
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_s(1) <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_y(1);
END IF;
END IF;
END PROCESS;
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_delay : dspba_delay
GENERIC MAP (width => 55, depth => 1)
PORT MAP (xin => STD_LOGIC_VECTOR(multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_s(0)(54 downto 0)), xout => multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_q, clk => clk, aclr => areset);
--multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval(BITSELECT,271)@23
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_in <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_q;
multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_b <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_in(54 downto 3);
--highBBits_uid274_pT4_uid141_natLogPolyEval(BITSELECT,273)@23
highBBits_uid274_pT4_uid141_natLogPolyEval_in <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_b;
highBBits_uid274_pT4_uid141_natLogPolyEval_b <= highBBits_uid274_pT4_uid141_natLogPolyEval_in(51 downto 23);
--ld_reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_topProd_uid265_pT4_uid141_natLogPolyEval_1_q_to_topProd_uid265_pT4_uid141_natLogPolyEval_b(DELAY,701)@19
ld_reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_topProd_uid265_pT4_uid141_natLogPolyEval_1_q_to_topProd_uid265_pT4_uid141_natLogPolyEval_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_9_q, xout => ld_reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_topProd_uid265_pT4_uid141_natLogPolyEval_1_q_to_topProd_uid265_pT4_uid141_natLogPolyEval_b_q, ena => en(0), clk => clk, aclr => areset );
--topProd_uid265_pT4_uid141_natLogPolyEval(MULT,264)@20
topProd_uid265_pT4_uid141_natLogPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid265_pT4_uid141_natLogPolyEval_a),28)) * SIGNED(topProd_uid265_pT4_uid141_natLogPolyEval_b);
topProd_uid265_pT4_uid141_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid265_pT4_uid141_natLogPolyEval_a <= (others => '0');
topProd_uid265_pT4_uid141_natLogPolyEval_b <= (others => '0');
topProd_uid265_pT4_uid141_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid265_pT4_uid141_natLogPolyEval_a <= reg_xTop27Bits_uid263_pT4_uid141_natLogPolyEval_0_to_multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_cma_4_q;
topProd_uid265_pT4_uid141_natLogPolyEval_b <= ld_reg_yTop27Bits_uid264_pT4_uid141_natLogPolyEval_0_to_topProd_uid265_pT4_uid141_natLogPolyEval_1_q_to_topProd_uid265_pT4_uid141_natLogPolyEval_b_q;
topProd_uid265_pT4_uid141_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid265_pT4_uid141_natLogPolyEval_pr,54));
END IF;
END IF;
END PROCESS;
topProd_uid265_pT4_uid141_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid265_pT4_uid141_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
topProd_uid265_pT4_uid141_natLogPolyEval_q <= topProd_uid265_pT4_uid141_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid275_pT4_uid141_natLogPolyEval(ADD,274)@23
sumAHighB_uid275_pT4_uid141_natLogPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => topProd_uid265_pT4_uid141_natLogPolyEval_q(53)) & topProd_uid265_pT4_uid141_natLogPolyEval_q);
sumAHighB_uid275_pT4_uid141_natLogPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => highBBits_uid274_pT4_uid141_natLogPolyEval_b(28)) & highBBits_uid274_pT4_uid141_natLogPolyEval_b);
sumAHighB_uid275_pT4_uid141_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid275_pT4_uid141_natLogPolyEval_a) + SIGNED(sumAHighB_uid275_pT4_uid141_natLogPolyEval_b));
sumAHighB_uid275_pT4_uid141_natLogPolyEval_q <= sumAHighB_uid275_pT4_uid141_natLogPolyEval_o(54 downto 0);
--lowRangeB_uid273_pT4_uid141_natLogPolyEval(BITSELECT,272)@23
lowRangeB_uid273_pT4_uid141_natLogPolyEval_in <= multSumOfTwo27_uid268_pT4_uid141_natLogPolyEval_b(22 downto 0);
lowRangeB_uid273_pT4_uid141_natLogPolyEval_b <= lowRangeB_uid273_pT4_uid141_natLogPolyEval_in(22 downto 0);
--add0_uid273_uid276_pT4_uid141_natLogPolyEval(BITJOIN,275)@23
add0_uid273_uid276_pT4_uid141_natLogPolyEval_q <= sumAHighB_uid275_pT4_uid141_natLogPolyEval_q & lowRangeB_uid273_pT4_uid141_natLogPolyEval_b;
--R_uid277_pT4_uid141_natLogPolyEval(BITSELECT,276)@23
R_uid277_pT4_uid141_natLogPolyEval_in <= add0_uid273_uid276_pT4_uid141_natLogPolyEval_q(76 downto 0);
R_uid277_pT4_uid141_natLogPolyEval_b <= R_uid277_pT4_uid141_natLogPolyEval_in(76 downto 25);
--reg_R_uid277_pT4_uid141_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_1(REG,387)@23
reg_R_uid277_pT4_uid141_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid277_pT4_uid141_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_1_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_R_uid277_pT4_uid141_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_1_q <= R_uid277_pT4_uid141_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_nor(LOGICAL,1081)
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_nor_b <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_sticky_ena_q;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_nor_q <= not (ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_nor_a or ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_nor_b);
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_mem_top(CONSTANT,1077)
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_mem_top_q <= "010000";
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmp(LOGICAL,1078)
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmp_a <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_mem_top_q;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux_q);
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmp_q <= "1" when ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmp_a = ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmp_b else "0";
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmpReg(REG,1079)
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmpReg_q <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_sticky_ena(REG,1082)
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_nor_q = "1") THEN
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_sticky_ena_q <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_enaAnd(LOGICAL,1083)
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_enaAnd_a <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_sticky_ena_q;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_enaAnd_b <= en;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_enaAnd_q <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_enaAnd_a and ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_enaAnd_b;
--memoryC0_uid102_natLogTabGen_lutmem(DUALMEM,302)@1
memoryC0_uid102_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid102_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid102_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC0_uid102_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC0_uid102_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid102_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid102_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid102_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid102_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid102_natLogTabGen_lutmem_ia
);
memoryC0_uid102_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid102_natLogTabGen_lutmem_q <= memoryC0_uid102_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid102_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_5(REG,333)@3
reg_memoryC0_uid102_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid102_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_5_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid102_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_5_q <= memoryC0_uid102_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid101_natLogTabGen_lutmem(DUALMEM,301)@1
memoryC0_uid101_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid101_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid101_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC0_uid101_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC0_uid101_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid101_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid101_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid101_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid101_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid101_natLogTabGen_lutmem_ia
);
memoryC0_uid101_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid101_natLogTabGen_lutmem_q <= memoryC0_uid101_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid101_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_4(REG,332)@3
reg_memoryC0_uid101_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid101_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_4_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid101_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_4_q <= memoryC0_uid101_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid100_natLogTabGen_lutmem(DUALMEM,300)@1
memoryC0_uid100_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid100_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid100_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC0_uid100_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC0_uid100_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid100_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid100_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid100_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid100_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid100_natLogTabGen_lutmem_ia
);
memoryC0_uid100_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid100_natLogTabGen_lutmem_q <= memoryC0_uid100_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid100_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_3(REG,331)@3
reg_memoryC0_uid100_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid100_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_3_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid100_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_3_q <= memoryC0_uid100_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid99_natLogTabGen_lutmem(DUALMEM,299)@1
memoryC0_uid99_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid99_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid99_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC0_uid99_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC0_uid99_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid99_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid99_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid99_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid99_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid99_natLogTabGen_lutmem_ia
);
memoryC0_uid99_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid99_natLogTabGen_lutmem_q <= memoryC0_uid99_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid99_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_2(REG,330)@3
reg_memoryC0_uid99_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid99_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_2_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid99_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_2_q <= memoryC0_uid99_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid98_natLogTabGen_lutmem(DUALMEM,298)@1
memoryC0_uid98_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid98_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid98_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC0_uid98_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC0_uid98_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid98_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid98_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid98_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid98_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid98_natLogTabGen_lutmem_ia
);
memoryC0_uid98_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid98_natLogTabGen_lutmem_q <= memoryC0_uid98_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid98_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_1(REG,329)@3
reg_memoryC0_uid98_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid98_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_1_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid98_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_1_q <= memoryC0_uid98_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid97_natLogTabGen_lutmem(DUALMEM,297)@1
memoryC0_uid97_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid97_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid97_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q;
memoryC0_uid97_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 10,
widthad_a => 11,
numwords_a => 2048,
width_b => 10,
widthad_b => 11,
numwords_b => 2048,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln_double_s5_memoryC0_uid97_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid97_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid97_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid97_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid97_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid97_natLogTabGen_lutmem_ia
);
memoryC0_uid97_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid97_natLogTabGen_lutmem_q <= memoryC0_uid97_natLogTabGen_lutmem_iq(9 downto 0);
--reg_memoryC0_uid97_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_0(REG,328)@3
reg_memoryC0_uid97_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid97_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid97_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_0_q <= memoryC0_uid97_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid103_natLogTabGen(BITJOIN,102)@4
os_uid103_natLogTabGen_q <= reg_memoryC0_uid102_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_5_q & reg_memoryC0_uid101_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_4_q & reg_memoryC0_uid100_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_3_q & reg_memoryC0_uid99_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_2_q & reg_memoryC0_uid98_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_1_q & reg_memoryC0_uid97_natLogTabGen_lutmem_0_to_os_uid103_natLogTabGen_0_q;
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_inputreg(DELAY,1071)
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_inputreg : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => os_uid103_natLogTabGen_q, xout => ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt(COUNTER,1073)
-- every=1, low=0, high=16, step=1, init=1
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_i = 15 THEN
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_i - 16;
ELSE
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_i <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_i,5));
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdreg(REG,1074)
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdreg_q <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux(MUX,1075)
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux_s <= en;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux: PROCESS (ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux_s, ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdreg_q, ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux_q <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem(DUALMEM,1072)
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_ia <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_inputreg_q;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_aa <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdreg_q;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_ab <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_rdmux_q;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 60,
widthad_a => 5,
numwords_a => 17,
width_b => 60,
widthad_b => 5,
numwords_b => 17,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_iq,
address_a => ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_aa,
data_a => ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_ia
);
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_reset0 <= areset;
ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_q <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_iq(59 downto 0);
--rndBit_uid142_natLogPolyEval(CONSTANT,141)
rndBit_uid142_natLogPolyEval_q <= "001";
--cIncludingRoundingBit_uid143_natLogPolyEval(BITJOIN,142)@23
cIncludingRoundingBit_uid143_natLogPolyEval_q <= ld_os_uid103_natLogTabGen_q_to_cIncludingRoundingBit_uid143_natLogPolyEval_b_replace_mem_q & rndBit_uid142_natLogPolyEval_q;
--reg_cIncludingRoundingBit_uid143_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_0(REG,386)@23
reg_cIncludingRoundingBit_uid143_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid143_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cIncludingRoundingBit_uid143_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_0_q <= cIncludingRoundingBit_uid143_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ts4_uid144_natLogPolyEval(ADD,143)@24
ts4_uid144_natLogPolyEval_a <= STD_LOGIC_VECTOR((63 downto 63 => reg_cIncludingRoundingBit_uid143_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_0_q(62)) & reg_cIncludingRoundingBit_uid143_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_0_q);
ts4_uid144_natLogPolyEval_b <= STD_LOGIC_VECTOR((63 downto 52 => reg_R_uid277_pT4_uid141_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_1_q(51)) & reg_R_uid277_pT4_uid141_natLogPolyEval_0_to_ts4_uid144_natLogPolyEval_1_q);
ts4_uid144_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid144_natLogPolyEval_a) + SIGNED(ts4_uid144_natLogPolyEval_b));
ts4_uid144_natLogPolyEval_q <= ts4_uid144_natLogPolyEval_o(63 downto 0);
--s4_uid145_natLogPolyEval(BITSELECT,144)@24
s4_uid145_natLogPolyEval_in <= ts4_uid144_natLogPolyEval_q;
s4_uid145_natLogPolyEval_b <= s4_uid145_natLogPolyEval_in(63 downto 1);
--peOR_uid37_fpLogETest(BITSELECT,36)@24
peOR_uid37_fpLogETest_in <= s4_uid145_natLogPolyEval_b(61 downto 0);
peOR_uid37_fpLogETest_b <= peOR_uid37_fpLogETest_in(61 downto 7);
--postPEMul_uid43_fpLogETest_b_2(BITSELECT,281)@24
postPEMul_uid43_fpLogETest_b_2_in <= STD_LOGIC_VECTOR((80 downto 55 => peOR_uid37_fpLogETest_b(54)) & peOR_uid37_fpLogETest_b);
postPEMul_uid43_fpLogETest_b_2_b <= postPEMul_uid43_fpLogETest_b_2_in(80 downto 54);
--reg_postPEMul_uid43_fpLogETest_b_2_0_to_postPEMul_uid43_fpLogETest_a0_b2_1(REG,398)@24
reg_postPEMul_uid43_fpLogETest_b_2_0_to_postPEMul_uid43_fpLogETest_a0_b2_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid43_fpLogETest_b_2_0_to_postPEMul_uid43_fpLogETest_a0_b2_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid43_fpLogETest_b_2_0_to_postPEMul_uid43_fpLogETest_a0_b2_1_q <= postPEMul_uid43_fpLogETest_b_2_b;
END IF;
END IF;
END PROCESS;
--ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_nor(LOGICAL,927)
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_nor_b <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_sticky_ena_q;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_nor_q <= not (ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_nor_a or ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_nor_b);
--ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_mem_top(CONSTANT,923)
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_mem_top_q <= "010100";
--ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmp(LOGICAL,924)
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmp_a <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_mem_top_q;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_q);
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmp_q <= "1" when ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmp_a = ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmp_b else "0";
--ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmpReg(REG,925)
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmpReg_q <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_sticky_ena(REG,928)
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_nor_q = "1") THEN
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_sticky_ena_q <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_enaAnd(LOGICAL,929)
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_enaAnd_a <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_sticky_ena_q;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_enaAnd_b <= en;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_enaAnd_q <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_enaAnd_a and ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_enaAnd_b;
--ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt(COUNTER,919)
-- every=1, low=0, high=20, step=1, init=1
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_i = 19 THEN
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_eq <= '1';
ELSE
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_eq = '1') THEN
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_i <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_i - 20;
ELSE
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_i <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_i,5));
--ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdreg(REG,920)
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdreg_q <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux(MUX,921)
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_s <= en;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux: PROCESS (ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_s, ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdreg_q, ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_q)
BEGIN
CASE ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_s IS
WHEN "0" => ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_q <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdreg_q;
WHEN "1" => ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_q <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdcnt_q;
WHEN OTHERS => ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem(DUALMEM,918)
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_ia <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_inputreg_q;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_aa <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdreg_q;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_ab <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_q;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 52,
widthad_a => 5,
numwords_a => 21,
width_b => 52,
widthad_b => 5,
numwords_b => 21,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_iq,
address_a => ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_aa,
data_a => ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_ia
);
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_reset0 <= areset;
ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_q <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_iq(51 downto 0);
--pad_o_uid11_uid38_fpLogETest(BITJOIN,37)@23
pad_o_uid11_uid38_fpLogETest_q <= VCC_q & STD_LOGIC_VECTOR((51 downto 1 => GND_q(0)) & GND_q);
--oMz_uid38_fpLogETest(SUB,38)@23
oMz_uid38_fpLogETest_a <= STD_LOGIC_VECTOR("0" & pad_o_uid11_uid38_fpLogETest_q);
oMz_uid38_fpLogETest_b <= STD_LOGIC_VECTOR("00" & ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_q);
oMz_uid38_fpLogETest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
oMz_uid38_fpLogETest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
oMz_uid38_fpLogETest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMz_uid38_fpLogETest_a) - UNSIGNED(oMz_uid38_fpLogETest_b));
END IF;
END IF;
END PROCESS;
oMz_uid38_fpLogETest_q <= oMz_uid38_fpLogETest_o(53 downto 0);
--z2_uid40_fpLogETest(CONSTANT,39)
z2_uid40_fpLogETest_q <= "00";
--sEz_uid41_fpLogETest(BITJOIN,40)@23
sEz_uid41_fpLogETest_q <= z2_uid40_fpLogETest_q & ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_mem_q;
--reg_sEz_uid41_fpLogETest_0_to_multTermOne_uid42_fpLogETest_2(REG,321)@23
reg_sEz_uid41_fpLogETest_0_to_multTermOne_uid42_fpLogETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sEz_uid41_fpLogETest_0_to_multTermOne_uid42_fpLogETest_2_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sEz_uid41_fpLogETest_0_to_multTermOne_uid42_fpLogETest_2_q <= sEz_uid41_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_nor(LOGICAL,940)
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_nor_b <= ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_sticky_ena_q;
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_nor_q <= not (ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_nor_a or ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_nor_b);
--ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_sticky_ena(REG,941)
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_nor_q = "1") THEN
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_sticky_ena_q <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_enaAnd(LOGICAL,942)
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_enaAnd_a <= ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_sticky_ena_q;
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_enaAnd_b <= en;
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_enaAnd_q <= ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_enaAnd_a and ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_enaAnd_b;
--reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1(REG,320)@0
reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q <= c_uid31_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_inputreg(DELAY,930)
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q, xout => ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem(DUALMEM,931)
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_ia <= ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_inputreg_q;
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_aa <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdreg_q;
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_ab <= ld_frac_uid19_fpLogETest_b_to_oMz_uid38_fpLogETest_b_replace_rdmux_q;
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 21,
width_b => 1,
widthad_b => 5,
numwords_b => 21,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_iq,
address_a => ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_aa,
data_a => ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_ia
);
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_reset0 <= areset;
ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_q <= ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_iq(0 downto 0);
--multTermOne_uid42_fpLogETest(MUX,41)@24
multTermOne_uid42_fpLogETest_s <= ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_replace_mem_q;
multTermOne_uid42_fpLogETest: PROCESS (multTermOne_uid42_fpLogETest_s, en, reg_sEz_uid41_fpLogETest_0_to_multTermOne_uid42_fpLogETest_2_q, oMz_uid38_fpLogETest_q)
BEGIN
CASE multTermOne_uid42_fpLogETest_s IS
WHEN "0" => multTermOne_uid42_fpLogETest_q <= reg_sEz_uid41_fpLogETest_0_to_multTermOne_uid42_fpLogETest_2_q;
WHEN "1" => multTermOne_uid42_fpLogETest_q <= oMz_uid38_fpLogETest_q;
WHEN OTHERS => multTermOne_uid42_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--postPEMul_uid43_fpLogETest_a_1(BITSELECT,278)@24
postPEMul_uid43_fpLogETest_a_1_in <= multTermOne_uid42_fpLogETest_q;
postPEMul_uid43_fpLogETest_a_1_b <= postPEMul_uid43_fpLogETest_a_1_in(53 downto 27);
--reg_postPEMul_uid43_fpLogETest_a_1_0_to_postPEMul_uid43_fpLogETest_a1_b0_0(REG,390)@24
reg_postPEMul_uid43_fpLogETest_a_1_0_to_postPEMul_uid43_fpLogETest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid43_fpLogETest_a_1_0_to_postPEMul_uid43_fpLogETest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid43_fpLogETest_a_1_0_to_postPEMul_uid43_fpLogETest_a1_b0_0_q <= postPEMul_uid43_fpLogETest_a_1_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_a1_b2(MULT,287)@25
postPEMul_uid43_fpLogETest_a1_b2_pr <= SIGNED(postPEMul_uid43_fpLogETest_a1_b2_a) * SIGNED(postPEMul_uid43_fpLogETest_a1_b2_b);
postPEMul_uid43_fpLogETest_a1_b2_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a1_b2_a <= (others => '0');
postPEMul_uid43_fpLogETest_a1_b2_b <= (others => '0');
postPEMul_uid43_fpLogETest_a1_b2_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a1_b2_a <= reg_postPEMul_uid43_fpLogETest_a_1_0_to_postPEMul_uid43_fpLogETest_a1_b0_0_q;
postPEMul_uid43_fpLogETest_a1_b2_b <= reg_postPEMul_uid43_fpLogETest_b_2_0_to_postPEMul_uid43_fpLogETest_a0_b2_1_q;
postPEMul_uid43_fpLogETest_a1_b2_s1 <= STD_LOGIC_VECTOR(postPEMul_uid43_fpLogETest_a1_b2_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid43_fpLogETest_a1_b2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a1_b2_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a1_b2_q <= postPEMul_uid43_fpLogETest_a1_b2_s1;
END IF;
END IF;
END PROCESS;
--ld_postPEMul_uid43_fpLogETest_a1_b2_q_to_postPEMul_uid43_fpLogETest_align_3_a(DELAY,739)@28
ld_postPEMul_uid43_fpLogETest_a1_b2_q_to_postPEMul_uid43_fpLogETest_align_3_a : dspba_delay
GENERIC MAP ( width => 54, depth => 2 )
PORT MAP ( xin => postPEMul_uid43_fpLogETest_a1_b2_q, xout => ld_postPEMul_uid43_fpLogETest_a1_b2_q_to_postPEMul_uid43_fpLogETest_align_3_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid43_fpLogETest_align_3(BITSHIFT,293)@30
postPEMul_uid43_fpLogETest_align_3_q_int <= ld_postPEMul_uid43_fpLogETest_a1_b2_q_to_postPEMul_uid43_fpLogETest_align_3_a_q & "000000000000000000000000000000000000000000000000000000000000000000000000000000000";
postPEMul_uid43_fpLogETest_align_3_q <= postPEMul_uid43_fpLogETest_align_3_q_int(134 downto 0);
--postPEMul_uid43_fpLogETest_a_0(BITSELECT,277)@24
postPEMul_uid43_fpLogETest_a_0_in <= multTermOne_uid42_fpLogETest_q(26 downto 0);
postPEMul_uid43_fpLogETest_a_0_b <= postPEMul_uid43_fpLogETest_a_0_in(26 downto 0);
--reg_postPEMul_uid43_fpLogETest_a_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_0(REG,388)@24
reg_postPEMul_uid43_fpLogETest_a_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid43_fpLogETest_a_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid43_fpLogETest_a_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_0_q <= postPEMul_uid43_fpLogETest_a_0_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_a0_b2(MULT,286)@25
postPEMul_uid43_fpLogETest_a0_b2_pr <= signed(resize(UNSIGNED(postPEMul_uid43_fpLogETest_a0_b2_a),28)) * SIGNED(postPEMul_uid43_fpLogETest_a0_b2_b);
postPEMul_uid43_fpLogETest_a0_b2_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a0_b2_a <= (others => '0');
postPEMul_uid43_fpLogETest_a0_b2_b <= (others => '0');
postPEMul_uid43_fpLogETest_a0_b2_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a0_b2_a <= reg_postPEMul_uid43_fpLogETest_a_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_0_q;
postPEMul_uid43_fpLogETest_a0_b2_b <= reg_postPEMul_uid43_fpLogETest_b_2_0_to_postPEMul_uid43_fpLogETest_a0_b2_1_q;
postPEMul_uid43_fpLogETest_a0_b2_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid43_fpLogETest_a0_b2_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid43_fpLogETest_a0_b2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a0_b2_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a0_b2_q <= postPEMul_uid43_fpLogETest_a0_b2_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_b_1(BITSELECT,280)@24
postPEMul_uid43_fpLogETest_b_1_in <= peOR_uid37_fpLogETest_b(53 downto 0);
postPEMul_uid43_fpLogETest_b_1_b <= postPEMul_uid43_fpLogETest_b_1_in(53 downto 27);
--reg_postPEMul_uid43_fpLogETest_b_1_0_to_postPEMul_uid43_fpLogETest_a0_b1_1(REG,393)@24
reg_postPEMul_uid43_fpLogETest_b_1_0_to_postPEMul_uid43_fpLogETest_a0_b1_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid43_fpLogETest_b_1_0_to_postPEMul_uid43_fpLogETest_a0_b1_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid43_fpLogETest_b_1_0_to_postPEMul_uid43_fpLogETest_a0_b1_1_q <= postPEMul_uid43_fpLogETest_b_1_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_a1_b1(MULT,285)@25
postPEMul_uid43_fpLogETest_a1_b1_pr <= SIGNED(postPEMul_uid43_fpLogETest_a1_b1_a) * signed(resize(UNSIGNED(postPEMul_uid43_fpLogETest_a1_b1_b),28));
postPEMul_uid43_fpLogETest_a1_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a1_b1_a <= (others => '0');
postPEMul_uid43_fpLogETest_a1_b1_b <= (others => '0');
postPEMul_uid43_fpLogETest_a1_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a1_b1_a <= reg_postPEMul_uid43_fpLogETest_a_1_0_to_postPEMul_uid43_fpLogETest_a1_b0_0_q;
postPEMul_uid43_fpLogETest_a1_b1_b <= reg_postPEMul_uid43_fpLogETest_b_1_0_to_postPEMul_uid43_fpLogETest_a0_b1_1_q;
postPEMul_uid43_fpLogETest_a1_b1_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid43_fpLogETest_a1_b1_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid43_fpLogETest_a1_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a1_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a1_b1_q <= postPEMul_uid43_fpLogETest_a1_b1_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_addcol_2_add_0_0(ADD,289)@28
postPEMul_uid43_fpLogETest_addcol_2_add_0_0_a <= STD_LOGIC_VECTOR((54 downto 54 => postPEMul_uid43_fpLogETest_a1_b1_q(53)) & postPEMul_uid43_fpLogETest_a1_b1_q);
postPEMul_uid43_fpLogETest_addcol_2_add_0_0_b <= STD_LOGIC_VECTOR((54 downto 54 => postPEMul_uid43_fpLogETest_a0_b2_q(53)) & postPEMul_uid43_fpLogETest_a0_b2_q);
postPEMul_uid43_fpLogETest_addcol_2_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid43_fpLogETest_addcol_2_add_0_0_a) + SIGNED(postPEMul_uid43_fpLogETest_addcol_2_add_0_0_b));
postPEMul_uid43_fpLogETest_addcol_2_add_0_0_q <= postPEMul_uid43_fpLogETest_addcol_2_add_0_0_o(54 downto 0);
--ld_postPEMul_uid43_fpLogETest_addcol_2_add_0_0_q_to_postPEMul_uid43_fpLogETest_align_2_a(DELAY,738)@28
ld_postPEMul_uid43_fpLogETest_addcol_2_add_0_0_q_to_postPEMul_uid43_fpLogETest_align_2_a : dspba_delay
GENERIC MAP ( width => 55, depth => 1 )
PORT MAP ( xin => postPEMul_uid43_fpLogETest_addcol_2_add_0_0_q, xout => ld_postPEMul_uid43_fpLogETest_addcol_2_add_0_0_q_to_postPEMul_uid43_fpLogETest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid43_fpLogETest_align_2(BITSHIFT,292)@29
postPEMul_uid43_fpLogETest_align_2_q_int <= ld_postPEMul_uid43_fpLogETest_addcol_2_add_0_0_q_to_postPEMul_uid43_fpLogETest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
postPEMul_uid43_fpLogETest_align_2_q <= postPEMul_uid43_fpLogETest_align_2_q_int(108 downto 0);
--reg_postPEMul_uid43_fpLogETest_align_2_0_to_postPEMul_uid43_fpLogETest_result_add_0_1_0(REG,401)@29
reg_postPEMul_uid43_fpLogETest_align_2_0_to_postPEMul_uid43_fpLogETest_result_add_0_1_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid43_fpLogETest_align_2_0_to_postPEMul_uid43_fpLogETest_result_add_0_1_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid43_fpLogETest_align_2_0_to_postPEMul_uid43_fpLogETest_result_add_0_1_0_q <= postPEMul_uid43_fpLogETest_align_2_q;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_result_add_0_1(ADD,295)@30
postPEMul_uid43_fpLogETest_result_add_0_1_a <= STD_LOGIC_VECTOR((135 downto 109 => reg_postPEMul_uid43_fpLogETest_align_2_0_to_postPEMul_uid43_fpLogETest_result_add_0_1_0_q(108)) & reg_postPEMul_uid43_fpLogETest_align_2_0_to_postPEMul_uid43_fpLogETest_result_add_0_1_0_q);
postPEMul_uid43_fpLogETest_result_add_0_1_b <= STD_LOGIC_VECTOR((135 downto 135 => postPEMul_uid43_fpLogETest_align_3_q(134)) & postPEMul_uid43_fpLogETest_align_3_q);
postPEMul_uid43_fpLogETest_result_add_0_1_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid43_fpLogETest_result_add_0_1_a) + SIGNED(postPEMul_uid43_fpLogETest_result_add_0_1_b));
postPEMul_uid43_fpLogETest_result_add_0_1_q <= postPEMul_uid43_fpLogETest_result_add_0_1_o(135 downto 0);
--postPEMul_uid43_fpLogETest_a0_b1(MULT,284)@25
postPEMul_uid43_fpLogETest_a0_b1_pr <= UNSIGNED(postPEMul_uid43_fpLogETest_a0_b1_a) * UNSIGNED(postPEMul_uid43_fpLogETest_a0_b1_b);
postPEMul_uid43_fpLogETest_a0_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a0_b1_a <= (others => '0');
postPEMul_uid43_fpLogETest_a0_b1_b <= (others => '0');
postPEMul_uid43_fpLogETest_a0_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a0_b1_a <= reg_postPEMul_uid43_fpLogETest_a_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_0_q;
postPEMul_uid43_fpLogETest_a0_b1_b <= reg_postPEMul_uid43_fpLogETest_b_1_0_to_postPEMul_uid43_fpLogETest_a0_b1_1_q;
postPEMul_uid43_fpLogETest_a0_b1_s1 <= STD_LOGIC_VECTOR(postPEMul_uid43_fpLogETest_a0_b1_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid43_fpLogETest_a0_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a0_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a0_b1_q <= postPEMul_uid43_fpLogETest_a0_b1_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_b_0(BITSELECT,279)@24
postPEMul_uid43_fpLogETest_b_0_in <= peOR_uid37_fpLogETest_b(26 downto 0);
postPEMul_uid43_fpLogETest_b_0_b <= postPEMul_uid43_fpLogETest_b_0_in(26 downto 0);
--reg_postPEMul_uid43_fpLogETest_b_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_1(REG,389)@24
reg_postPEMul_uid43_fpLogETest_b_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid43_fpLogETest_b_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid43_fpLogETest_b_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_1_q <= postPEMul_uid43_fpLogETest_b_0_b;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_a1_b0(MULT,283)@25
postPEMul_uid43_fpLogETest_a1_b0_pr <= SIGNED(postPEMul_uid43_fpLogETest_a1_b0_a) * signed(resize(UNSIGNED(postPEMul_uid43_fpLogETest_a1_b0_b),28));
postPEMul_uid43_fpLogETest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a1_b0_a <= (others => '0');
postPEMul_uid43_fpLogETest_a1_b0_b <= (others => '0');
postPEMul_uid43_fpLogETest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a1_b0_a <= reg_postPEMul_uid43_fpLogETest_a_1_0_to_postPEMul_uid43_fpLogETest_a1_b0_0_q;
postPEMul_uid43_fpLogETest_a1_b0_b <= reg_postPEMul_uid43_fpLogETest_b_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_1_q;
postPEMul_uid43_fpLogETest_a1_b0_s1 <= STD_LOGIC_VECTOR(resize(postPEMul_uid43_fpLogETest_a1_b0_pr,54));
END IF;
END IF;
END PROCESS;
postPEMul_uid43_fpLogETest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a1_b0_q <= postPEMul_uid43_fpLogETest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_addcol_1_add_0_0(ADD,288)@28
postPEMul_uid43_fpLogETest_addcol_1_add_0_0_a <= STD_LOGIC_VECTOR((56 downto 54 => postPEMul_uid43_fpLogETest_a1_b0_q(53)) & postPEMul_uid43_fpLogETest_a1_b0_q);
postPEMul_uid43_fpLogETest_addcol_1_add_0_0_b <= STD_LOGIC_VECTOR('0' & "00" & postPEMul_uid43_fpLogETest_a0_b1_q);
postPEMul_uid43_fpLogETest_addcol_1_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid43_fpLogETest_addcol_1_add_0_0_a) + SIGNED(postPEMul_uid43_fpLogETest_addcol_1_add_0_0_b));
postPEMul_uid43_fpLogETest_addcol_1_add_0_0_q <= postPEMul_uid43_fpLogETest_addcol_1_add_0_0_o(55 downto 0);
--ld_postPEMul_uid43_fpLogETest_addcol_1_add_0_0_q_to_postPEMul_uid43_fpLogETest_align_1_a(DELAY,737)@28
ld_postPEMul_uid43_fpLogETest_addcol_1_add_0_0_q_to_postPEMul_uid43_fpLogETest_align_1_a : dspba_delay
GENERIC MAP ( width => 56, depth => 1 )
PORT MAP ( xin => postPEMul_uid43_fpLogETest_addcol_1_add_0_0_q, xout => ld_postPEMul_uid43_fpLogETest_addcol_1_add_0_0_q_to_postPEMul_uid43_fpLogETest_align_1_a_q, ena => en(0), clk => clk, aclr => areset );
--postPEMul_uid43_fpLogETest_align_1(BITSHIFT,291)@29
postPEMul_uid43_fpLogETest_align_1_q_int <= ld_postPEMul_uid43_fpLogETest_addcol_1_add_0_0_q_to_postPEMul_uid43_fpLogETest_align_1_a_q & "000000000000000000000000000";
postPEMul_uid43_fpLogETest_align_1_q <= postPEMul_uid43_fpLogETest_align_1_q_int(82 downto 0);
--postPEMul_uid43_fpLogETest_a0_b0(MULT,282)@25
postPEMul_uid43_fpLogETest_a0_b0_pr <= UNSIGNED(postPEMul_uid43_fpLogETest_a0_b0_a) * UNSIGNED(postPEMul_uid43_fpLogETest_a0_b0_b);
postPEMul_uid43_fpLogETest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a0_b0_a <= (others => '0');
postPEMul_uid43_fpLogETest_a0_b0_b <= (others => '0');
postPEMul_uid43_fpLogETest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a0_b0_a <= reg_postPEMul_uid43_fpLogETest_a_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_0_q;
postPEMul_uid43_fpLogETest_a0_b0_b <= reg_postPEMul_uid43_fpLogETest_b_0_0_to_postPEMul_uid43_fpLogETest_a0_b0_1_q;
postPEMul_uid43_fpLogETest_a0_b0_s1 <= STD_LOGIC_VECTOR(postPEMul_uid43_fpLogETest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid43_fpLogETest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid43_fpLogETest_a0_b0_q <= postPEMul_uid43_fpLogETest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_align_0(BITSHIFT,290)@28
postPEMul_uid43_fpLogETest_align_0_q_int <= postPEMul_uid43_fpLogETest_a0_b0_q;
postPEMul_uid43_fpLogETest_align_0_q <= postPEMul_uid43_fpLogETest_align_0_q_int(53 downto 0);
--reg_postPEMul_uid43_fpLogETest_align_0_0_to_postPEMul_uid43_fpLogETest_result_add_0_0_0(REG,394)@28
reg_postPEMul_uid43_fpLogETest_align_0_0_to_postPEMul_uid43_fpLogETest_result_add_0_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_postPEMul_uid43_fpLogETest_align_0_0_to_postPEMul_uid43_fpLogETest_result_add_0_0_0_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_postPEMul_uid43_fpLogETest_align_0_0_to_postPEMul_uid43_fpLogETest_result_add_0_0_0_q <= postPEMul_uid43_fpLogETest_align_0_q;
END IF;
END IF;
END PROCESS;
--postPEMul_uid43_fpLogETest_result_add_0_0(ADD,294)@29
postPEMul_uid43_fpLogETest_result_add_0_0_a <= STD_LOGIC_VECTOR('0' & "000000000000000000000000000000" & reg_postPEMul_uid43_fpLogETest_align_0_0_to_postPEMul_uid43_fpLogETest_result_add_0_0_0_q);
postPEMul_uid43_fpLogETest_result_add_0_0_b <= STD_LOGIC_VECTOR((84 downto 83 => postPEMul_uid43_fpLogETest_align_1_q(82)) & postPEMul_uid43_fpLogETest_align_1_q);
postPEMul_uid43_fpLogETest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid43_fpLogETest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
postPEMul_uid43_fpLogETest_result_add_0_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid43_fpLogETest_result_add_0_0_a) + SIGNED(postPEMul_uid43_fpLogETest_result_add_0_0_b));
END IF;
END PROCESS;
postPEMul_uid43_fpLogETest_result_add_0_0_q <= postPEMul_uid43_fpLogETest_result_add_0_0_o(83 downto 0);
--postPEMul_uid43_fpLogETest_result_add_1_0(ADD,296)@30
postPEMul_uid43_fpLogETest_result_add_1_0_a <= STD_LOGIC_VECTOR((136 downto 84 => postPEMul_uid43_fpLogETest_result_add_0_0_q(83)) & postPEMul_uid43_fpLogETest_result_add_0_0_q);
postPEMul_uid43_fpLogETest_result_add_1_0_b <= STD_LOGIC_VECTOR((136 downto 136 => postPEMul_uid43_fpLogETest_result_add_0_1_q(135)) & postPEMul_uid43_fpLogETest_result_add_0_1_q);
postPEMul_uid43_fpLogETest_result_add_1_0_o <= STD_LOGIC_VECTOR(SIGNED(postPEMul_uid43_fpLogETest_result_add_1_0_a) + SIGNED(postPEMul_uid43_fpLogETest_result_add_1_0_b));
postPEMul_uid43_fpLogETest_result_add_1_0_q <= postPEMul_uid43_fpLogETest_result_add_1_0_o(136 downto 0);
--highBBits_uid47_fpLogETest(BITSELECT,46)@30
highBBits_uid47_fpLogETest_in <= postPEMul_uid43_fpLogETest_result_add_1_0_q(108 downto 0);
highBBits_uid47_fpLogETest_b <= highBBits_uid47_fpLogETest_in(108 downto 50);
--reg_highBBits_uid47_fpLogETest_0_to_sumAHighB_uid48_fpLogETest_1(REG,406)@30
reg_highBBits_uid47_fpLogETest_0_to_sumAHighB_uid48_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid47_fpLogETest_0_to_sumAHighB_uid48_fpLogETest_1_q <= "00000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_highBBits_uid47_fpLogETest_0_to_sumAHighB_uid48_fpLogETest_1_q <= highBBits_uid47_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--wideZero_uid44_fpLogETest(CONSTANT,43)
wideZero_uid44_fpLogETest_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
--cstBias_uid9_fpLogETest(CONSTANT,8)
cstBias_uid9_fpLogETest_q <= "01111111111";
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor(LOGICAL,903)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_b <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_q <= not (ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_a or ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_b);
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_mem_top(CONSTANT,899)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_mem_top_q <= "011000";
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp(LOGICAL,900)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_mem_top_q;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q);
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_q <= "1" when ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_a = ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_b else "0";
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg(REG,901)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena(REG,904)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_q = "1") THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd(LOGICAL,905)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_b <= en;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_a and ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_b;
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_inputreg(DELAY,893)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_inputreg : dspba_delay
GENERIC MAP ( width => 11, depth => 1 )
PORT MAP ( xin => expX_uid6_fpLogETest_b, xout => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt(COUNTER,895)
-- every=1, low=0, high=24, step=1, init=1
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i = 23 THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_eq = '1') THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i - 24;
ELSE
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i,5));
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg(REG,896)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux(MUX,897)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_s <= en;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux: PROCESS (ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_s, ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q, ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_s IS
WHEN "0" => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q;
WHEN "1" => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem(DUALMEM,894)
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ia <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_inputreg_q;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_aa <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ab <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 5,
numwords_a => 25,
width_b => 11,
widthad_b => 5,
numwords_b => 25,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_iq,
address_a => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_aa,
data_a => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ia
);
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_reset0 <= areset;
ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_iq(10 downto 0);
--e_uid29_fpLogETest(SUB,28)@27
e_uid29_fpLogETest_a <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_q);
e_uid29_fpLogETest_b <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogETest_q);
e_uid29_fpLogETest_o <= STD_LOGIC_VECTOR(UNSIGNED(e_uid29_fpLogETest_a) - UNSIGNED(e_uid29_fpLogETest_b));
e_uid29_fpLogETest_q <= e_uid29_fpLogETest_o(11 downto 0);
--xv0_uid90_constMult(BITSELECT,89)@27
xv0_uid90_constMult_in <= e_uid29_fpLogETest_q(5 downto 0);
xv0_uid90_constMult_b <= xv0_uid90_constMult_in(5 downto 0);
--ld_xv0_uid90_constMult_b_to_reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0_a(DELAY,858)@27
ld_xv0_uid90_constMult_b_to_reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0_a : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => xv0_uid90_constMult_b, xout => ld_xv0_uid90_constMult_b_to_reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0(REG,403)@28
reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0_q <= ld_xv0_uid90_constMult_b_to_reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0_a_q;
END IF;
END IF;
END PROCESS;
--p0_uid93_constMult(LOOKUP,92)@29
p0_uid93_constMult: PROCESS (reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_xv0_uid90_constMult_0_to_p0_uid93_constMult_0_q) IS
WHEN "000000" => p0_uid93_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p0_uid93_constMult_q <= "000000101100010111001000010111111101111101000111001111011110000";
WHEN "000010" => p0_uid93_constMult_q <= "000001011000101110010000101111111011111010001110011110111100000";
WHEN "000011" => p0_uid93_constMult_q <= "000010000101000101011001000111111001110111010101101110011010000";
WHEN "000100" => p0_uid93_constMult_q <= "000010110001011100100001011111110111110100011100111101111000000";
WHEN "000101" => p0_uid93_constMult_q <= "000011011101110011101001110111110101110001100100001101010110000";
WHEN "000110" => p0_uid93_constMult_q <= "000100001010001010110010001111110011101110101011011100110100000";
WHEN "000111" => p0_uid93_constMult_q <= "000100110110100001111010100111110001101011110010101100010010000";
WHEN "001000" => p0_uid93_constMult_q <= "000101100010111001000010111111101111101000111001111011110000000";
WHEN "001001" => p0_uid93_constMult_q <= "000110001111010000001011010111101101100110000001001011001110000";
WHEN "001010" => p0_uid93_constMult_q <= "000110111011100111010011101111101011100011001000011010101100000";
WHEN "001011" => p0_uid93_constMult_q <= "000111100111111110011100000111101001100000001111101010001010000";
WHEN "001100" => p0_uid93_constMult_q <= "001000010100010101100100011111100111011101010110111001101000000";
WHEN "001101" => p0_uid93_constMult_q <= "001001000000101100101100110111100101011010011110001001000110000";
WHEN "001110" => p0_uid93_constMult_q <= "001001101101000011110101001111100011010111100101011000100100000";
WHEN "001111" => p0_uid93_constMult_q <= "001010011001011010111101100111100001010100101100101000000010000";
WHEN "010000" => p0_uid93_constMult_q <= "001011000101110010000101111111011111010001110011110111100000000";
WHEN "010001" => p0_uid93_constMult_q <= "001011110010001001001110010111011101001110111011000110111110000";
WHEN "010010" => p0_uid93_constMult_q <= "001100011110100000010110101111011011001100000010010110011100000";
WHEN "010011" => p0_uid93_constMult_q <= "001101001010110111011111000111011001001001001001100101111010000";
WHEN "010100" => p0_uid93_constMult_q <= "001101110111001110100111011111010111000110010000110101011000000";
WHEN "010101" => p0_uid93_constMult_q <= "001110100011100101101111110111010101000011011000000100110110000";
WHEN "010110" => p0_uid93_constMult_q <= "001111001111111100111000001111010011000000011111010100010100000";
WHEN "010111" => p0_uid93_constMult_q <= "001111111100010100000000100111010000111101100110100011110010000";
WHEN "011000" => p0_uid93_constMult_q <= "010000101000101011001000111111001110111010101101110011010000000";
WHEN "011001" => p0_uid93_constMult_q <= "010001010101000010010001010111001100110111110101000010101110000";
WHEN "011010" => p0_uid93_constMult_q <= "010010000001011001011001101111001010110100111100010010001100000";
WHEN "011011" => p0_uid93_constMult_q <= "010010101101110000100010000111001000110010000011100001101010000";
WHEN "011100" => p0_uid93_constMult_q <= "010011011010000111101010011111000110101111001010110001001000000";
WHEN "011101" => p0_uid93_constMult_q <= "010100000110011110110010110111000100101100010010000000100110000";
WHEN "011110" => p0_uid93_constMult_q <= "010100110010110101111011001111000010101001011001010000000100000";
WHEN "011111" => p0_uid93_constMult_q <= "010101011111001101000011100111000000100110100000011111100010000";
WHEN "100000" => p0_uid93_constMult_q <= "010110001011100100001011111110111110100011100111101111000000000";
WHEN "100001" => p0_uid93_constMult_q <= "010110110111111011010100010110111100100000101110111110011110000";
WHEN "100010" => p0_uid93_constMult_q <= "010111100100010010011100101110111010011101110110001101111100000";
WHEN "100011" => p0_uid93_constMult_q <= "011000010000101001100101000110111000011010111101011101011010000";
WHEN "100100" => p0_uid93_constMult_q <= "011000111101000000101101011110110110011000000100101100111000000";
WHEN "100101" => p0_uid93_constMult_q <= "011001101001010111110101110110110100010101001011111100010110000";
WHEN "100110" => p0_uid93_constMult_q <= "011010010101101110111110001110110010010010010011001011110100000";
WHEN "100111" => p0_uid93_constMult_q <= "011011000010000110000110100110110000001111011010011011010010000";
WHEN "101000" => p0_uid93_constMult_q <= "011011101110011101001110111110101110001100100001101010110000000";
WHEN "101001" => p0_uid93_constMult_q <= "011100011010110100010111010110101100001001101000111010001110000";
WHEN "101010" => p0_uid93_constMult_q <= "011101000111001011011111101110101010000110110000001001101100000";
WHEN "101011" => p0_uid93_constMult_q <= "011101110011100010101000000110101000000011110111011001001010000";
WHEN "101100" => p0_uid93_constMult_q <= "011110011111111001110000011110100110000000111110101000101000000";
WHEN "101101" => p0_uid93_constMult_q <= "011111001100010000111000110110100011111110000101111000000110000";
WHEN "101110" => p0_uid93_constMult_q <= "011111111000101000000001001110100001111011001101000111100100000";
WHEN "101111" => p0_uid93_constMult_q <= "100000100100111111001001100110011111111000010100010111000010000";
WHEN "110000" => p0_uid93_constMult_q <= "100001010001010110010001111110011101110101011011100110100000000";
WHEN "110001" => p0_uid93_constMult_q <= "100001111101101101011010010110011011110010100010110101111110000";
WHEN "110010" => p0_uid93_constMult_q <= "100010101010000100100010101110011001101111101010000101011100000";
WHEN "110011" => p0_uid93_constMult_q <= "100011010110011011101011000110010111101100110001010100111010000";
WHEN "110100" => p0_uid93_constMult_q <= "100100000010110010110011011110010101101001111000100100011000000";
WHEN "110101" => p0_uid93_constMult_q <= "100100101111001001111011110110010011100110111111110011110110000";
WHEN "110110" => p0_uid93_constMult_q <= "100101011011100001000100001110010001100100000111000011010100000";
WHEN "110111" => p0_uid93_constMult_q <= "100110000111111000001100100110001111100001001110010010110010000";
WHEN "111000" => p0_uid93_constMult_q <= "100110110100001111010100111110001101011110010101100010010000000";
WHEN "111001" => p0_uid93_constMult_q <= "100111100000100110011101010110001011011011011100110001101110000";
WHEN "111010" => p0_uid93_constMult_q <= "101000001100111101100101101110001001011000100100000001001100000";
WHEN "111011" => p0_uid93_constMult_q <= "101000111001010100101110000110000111010101101011010000101010000";
WHEN "111100" => p0_uid93_constMult_q <= "101001100101101011110110011110000101010010110010100000001000000";
WHEN "111101" => p0_uid93_constMult_q <= "101010010010000010111110110110000011001111111001101111100110000";
WHEN "111110" => p0_uid93_constMult_q <= "101010111110011010000111001110000001001101000000111111000100000";
WHEN "111111" => p0_uid93_constMult_q <= "101011101010110001001111100101111111001010001000001110100010000";
WHEN OTHERS =>
p0_uid93_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv1_uid91_constMult(BITSELECT,90)@27
xv1_uid91_constMult_in <= e_uid29_fpLogETest_q;
xv1_uid91_constMult_b <= xv1_uid91_constMult_in(11 downto 6);
--reg_xv1_uid91_constMult_0_to_p1_uid92_constMult_0(REG,402)@27
reg_xv1_uid91_constMult_0_to_p1_uid92_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv1_uid91_constMult_0_to_p1_uid92_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv1_uid91_constMult_0_to_p1_uid92_constMult_0_q <= xv1_uid91_constMult_b;
END IF;
END IF;
END PROCESS;
--p1_uid92_constMult(LOOKUP,91)@28
p1_uid92_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p1_uid92_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_xv1_uid91_constMult_0_to_p1_uid92_constMult_0_q) IS
WHEN "000000" => p1_uid92_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
WHEN "000001" => p1_uid92_constMult_q <= "000000101100010111001000010111111101111101000111001111011110000000000";
WHEN "000010" => p1_uid92_constMult_q <= "000001011000101110010000101111111011111010001110011110111100000000000";
WHEN "000011" => p1_uid92_constMult_q <= "000010000101000101011001000111111001110111010101101110011010000000000";
WHEN "000100" => p1_uid92_constMult_q <= "000010110001011100100001011111110111110100011100111101111000000000000";
WHEN "000101" => p1_uid92_constMult_q <= "000011011101110011101001110111110101110001100100001101010110000000000";
WHEN "000110" => p1_uid92_constMult_q <= "000100001010001010110010001111110011101110101011011100110100000000000";
WHEN "000111" => p1_uid92_constMult_q <= "000100110110100001111010100111110001101011110010101100010010000000000";
WHEN "001000" => p1_uid92_constMult_q <= "000101100010111001000010111111101111101000111001111011110000000000000";
WHEN "001001" => p1_uid92_constMult_q <= "000110001111010000001011010111101101100110000001001011001110000000000";
WHEN "001010" => p1_uid92_constMult_q <= "000110111011100111010011101111101011100011001000011010101100000000000";
WHEN "001011" => p1_uid92_constMult_q <= "000111100111111110011100000111101001100000001111101010001010000000000";
WHEN "001100" => p1_uid92_constMult_q <= "001000010100010101100100011111100111011101010110111001101000000000000";
WHEN "001101" => p1_uid92_constMult_q <= "001001000000101100101100110111100101011010011110001001000110000000000";
WHEN "001110" => p1_uid92_constMult_q <= "001001101101000011110101001111100011010111100101011000100100000000000";
WHEN "001111" => p1_uid92_constMult_q <= "001010011001011010111101100111100001010100101100101000000010000000000";
WHEN "010000" => p1_uid92_constMult_q <= "001011000101110010000101111111011111010001110011110111100000000000000";
WHEN "010001" => p1_uid92_constMult_q <= "001011110010001001001110010111011101001110111011000110111110000000000";
WHEN "010010" => p1_uid92_constMult_q <= "001100011110100000010110101111011011001100000010010110011100000000000";
WHEN "010011" => p1_uid92_constMult_q <= "001101001010110111011111000111011001001001001001100101111010000000000";
WHEN "010100" => p1_uid92_constMult_q <= "001101110111001110100111011111010111000110010000110101011000000000000";
WHEN "010101" => p1_uid92_constMult_q <= "001110100011100101101111110111010101000011011000000100110110000000000";
WHEN "010110" => p1_uid92_constMult_q <= "001111001111111100111000001111010011000000011111010100010100000000000";
WHEN "010111" => p1_uid92_constMult_q <= "001111111100010100000000100111010000111101100110100011110010000000000";
WHEN "011000" => p1_uid92_constMult_q <= "010000101000101011001000111111001110111010101101110011010000000000000";
WHEN "011001" => p1_uid92_constMult_q <= "010001010101000010010001010111001100110111110101000010101110000000000";
WHEN "011010" => p1_uid92_constMult_q <= "010010000001011001011001101111001010110100111100010010001100000000000";
WHEN "011011" => p1_uid92_constMult_q <= "010010101101110000100010000111001000110010000011100001101010000000000";
WHEN "011100" => p1_uid92_constMult_q <= "010011011010000111101010011111000110101111001010110001001000000000000";
WHEN "011101" => p1_uid92_constMult_q <= "010100000110011110110010110111000100101100010010000000100110000000000";
WHEN "011110" => p1_uid92_constMult_q <= "010100110010110101111011001111000010101001011001010000000100000000000";
WHEN "011111" => p1_uid92_constMult_q <= "010101011111001101000011100111000000100110100000011111100010000000000";
WHEN "100000" => p1_uid92_constMult_q <= "101001110100011011110100000001000001011100011000010001000000000000000";
WHEN "100001" => p1_uid92_constMult_q <= "101010100000110010111100011000111111011001011111100000011110000000000";
WHEN "100010" => p1_uid92_constMult_q <= "101011001101001010000100110000111101010110100110101111111100000000000";
WHEN "100011" => p1_uid92_constMult_q <= "101011111001100001001101001000111011010011101101111111011010000000000";
WHEN "100100" => p1_uid92_constMult_q <= "101100100101111000010101100000111001010000110101001110111000000000000";
WHEN "100101" => p1_uid92_constMult_q <= "101101010010001111011101111000110111001101111100011110010110000000000";
WHEN "100110" => p1_uid92_constMult_q <= "101101111110100110100110010000110101001011000011101101110100000000000";
WHEN "100111" => p1_uid92_constMult_q <= "101110101010111101101110101000110011001000001010111101010010000000000";
WHEN "101000" => p1_uid92_constMult_q <= "101111010111010100110111000000110001000101010010001100110000000000000";
WHEN "101001" => p1_uid92_constMult_q <= "110000000011101011111111011000101111000010011001011100001110000000000";
WHEN "101010" => p1_uid92_constMult_q <= "110000110000000011000111110000101100111111100000101011101100000000000";
WHEN "101011" => p1_uid92_constMult_q <= "110001011100011010010000001000101010111100100111111011001010000000000";
WHEN "101100" => p1_uid92_constMult_q <= "110010001000110001011000100000101000111001101111001010101000000000000";
WHEN "101101" => p1_uid92_constMult_q <= "110010110101001000100000111000100110110110110110011010000110000000000";
WHEN "101110" => p1_uid92_constMult_q <= "110011100001011111101001010000100100110011111101101001100100000000000";
WHEN "101111" => p1_uid92_constMult_q <= "110100001101110110110001101000100010110001000100111001000010000000000";
WHEN "110000" => p1_uid92_constMult_q <= "110100111010001101111010000000100000101110001100001000100000000000000";
WHEN "110001" => p1_uid92_constMult_q <= "110101100110100101000010011000011110101011010011010111111110000000000";
WHEN "110010" => p1_uid92_constMult_q <= "110110010010111100001010110000011100101000011010100111011100000000000";
WHEN "110011" => p1_uid92_constMult_q <= "110110111111010011010011001000011010100101100001110110111010000000000";
WHEN "110100" => p1_uid92_constMult_q <= "110111101011101010011011100000011000100010101001000110011000000000000";
WHEN "110101" => p1_uid92_constMult_q <= "111000011000000001100011111000010110011111110000010101110110000000000";
WHEN "110110" => p1_uid92_constMult_q <= "111001000100011000101100010000010100011100110111100101010100000000000";
WHEN "110111" => p1_uid92_constMult_q <= "111001110000101111110100101000010010011001111110110100110010000000000";
WHEN "111000" => p1_uid92_constMult_q <= "111010011101000110111101000000010000010111000110000100010000000000000";
WHEN "111001" => p1_uid92_constMult_q <= "111011001001011110000101011000001110010100001101010011101110000000000";
WHEN "111010" => p1_uid92_constMult_q <= "111011110101110101001101110000001100010001010100100011001100000000000";
WHEN "111011" => p1_uid92_constMult_q <= "111100100010001100010110001000001010001110011011110010101010000000000";
WHEN "111100" => p1_uid92_constMult_q <= "111101001110100011011110100000001000001011100011000010001000000000000";
WHEN "111101" => p1_uid92_constMult_q <= "111101111010111010100110111000000110001000101010010001100110000000000";
WHEN "111110" => p1_uid92_constMult_q <= "111110100111010001101111010000000100000101110001100001000100000000000";
WHEN "111111" => p1_uid92_constMult_q <= "111111010011101000110111101000000010000010111000110000100010000000000";
WHEN OTHERS =>
p1_uid92_constMult_q <= "000000000000000000000000000000000000000000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
--lev1_a0_uid94_constMult(ADD,93)@29
lev1_a0_uid94_constMult_a <= STD_LOGIC_VECTOR((70 downto 69 => p1_uid92_constMult_q(68)) & p1_uid92_constMult_q);
lev1_a0_uid94_constMult_b <= STD_LOGIC_VECTOR('0' & "0000000" & p0_uid93_constMult_q);
lev1_a0_uid94_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev1_a0_uid94_constMult_a) + SIGNED(lev1_a0_uid94_constMult_b));
lev1_a0_uid94_constMult_q <= lev1_a0_uid94_constMult_o(69 downto 0);
--sR_uid95_constMult(BITSELECT,94)@29
sR_uid95_constMult_in <= lev1_a0_uid94_constMult_q(68 downto 0);
sR_uid95_constMult_b <= sR_uid95_constMult_in(68 downto 2);
--reg_sR_uid95_constMult_0_to_addTermOne_uid45_fpLogETest_2(REG,405)@29
reg_sR_uid95_constMult_0_to_addTermOne_uid45_fpLogETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sR_uid95_constMult_0_to_addTermOne_uid45_fpLogETest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sR_uid95_constMult_0_to_addTermOne_uid45_fpLogETest_2_q <= sR_uid95_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_nor(LOGICAL,953)
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_nor_b <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_sticky_ena_q;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_nor_q <= not (ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_nor_a or ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_nor_b);
--ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_mem_top(CONSTANT,949)
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_mem_top_q <= "011010";
--ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmp(LOGICAL,950)
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmp_a <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_mem_top_q;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux_q);
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmp_q <= "1" when ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmp_a = ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmp_b else "0";
--ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmpReg(REG,951)
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmpReg_q <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_sticky_ena(REG,954)
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_nor_q = "1") THEN
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_sticky_ena_q <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_enaAnd(LOGICAL,955)
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_enaAnd_a <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_sticky_ena_q;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_enaAnd_b <= en;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_enaAnd_q <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_enaAnd_a and ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_enaAnd_b;
--ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt(COUNTER,945)
-- every=1, low=0, high=26, step=1, init=1
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_i = 25 THEN
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_eq = '1') THEN
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_i <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_i - 26;
ELSE
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_i <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_i,5));
--ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdreg(REG,946)
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdreg_q <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux(MUX,947)
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux_s <= en;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux: PROCESS (ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux_s, ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdreg_q, ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux_q <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdreg_q;
WHEN "1" => ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux_q <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem(DUALMEM,944)
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_ia <= ld_reg_c_uid31_fpLogETest_0_to_multTermOne_uid42_fpLogETest_1_q_to_multTermOne_uid42_fpLogETest_b_inputreg_q;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_aa <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdreg_q;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_ab <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_rdmux_q;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 27,
width_b => 1,
widthad_b => 5,
numwords_b => 27,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_iq,
address_a => ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_aa,
data_a => ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_ia
);
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_reset0 <= areset;
ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_q <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_iq(0 downto 0);
--addTermOne_uid45_fpLogETest(MUX,44)@30
addTermOne_uid45_fpLogETest_s <= ld_reg_c_uid31_fpLogETest_0_to_addTermOne_uid45_fpLogETest_1_q_to_addTermOne_uid45_fpLogETest_b_replace_mem_q;
addTermOne_uid45_fpLogETest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
addTermOne_uid45_fpLogETest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE addTermOne_uid45_fpLogETest_s IS
WHEN "0" => addTermOne_uid45_fpLogETest_q <= reg_sR_uid95_constMult_0_to_addTermOne_uid45_fpLogETest_2_q;
WHEN "1" => addTermOne_uid45_fpLogETest_q <= wideZero_uid44_fpLogETest_q;
WHEN OTHERS => addTermOne_uid45_fpLogETest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid48_fpLogETest(ADD,47)@31
sumAHighB_uid48_fpLogETest_a <= STD_LOGIC_VECTOR((67 downto 67 => addTermOne_uid45_fpLogETest_q(66)) & addTermOne_uid45_fpLogETest_q);
sumAHighB_uid48_fpLogETest_b <= STD_LOGIC_VECTOR((67 downto 59 => reg_highBBits_uid47_fpLogETest_0_to_sumAHighB_uid48_fpLogETest_1_q(58)) & reg_highBBits_uid47_fpLogETest_0_to_sumAHighB_uid48_fpLogETest_1_q);
sumAHighB_uid48_fpLogETest_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid48_fpLogETest_a) + SIGNED(sumAHighB_uid48_fpLogETest_b));
sumAHighB_uid48_fpLogETest_q <= sumAHighB_uid48_fpLogETest_o(67 downto 0);
--lowRangeB_uid46_fpLogETest(BITSELECT,45)@30
lowRangeB_uid46_fpLogETest_in <= postPEMul_uid43_fpLogETest_result_add_1_0_q(49 downto 0);
lowRangeB_uid46_fpLogETest_b <= lowRangeB_uid46_fpLogETest_in(49 downto 0);
--reg_lowRangeB_uid46_fpLogETest_0_to_finalSum_uid46_uid49_fpLogETest_0(REG,407)@30
reg_lowRangeB_uid46_fpLogETest_0_to_finalSum_uid46_uid49_fpLogETest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_lowRangeB_uid46_fpLogETest_0_to_finalSum_uid46_uid49_fpLogETest_0_q <= "00000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_lowRangeB_uid46_fpLogETest_0_to_finalSum_uid46_uid49_fpLogETest_0_q <= lowRangeB_uid46_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--finalSum_uid46_uid49_fpLogETest(BITJOIN,48)@31
finalSum_uid46_uid49_fpLogETest_q <= sumAHighB_uid48_fpLogETest_q & reg_lowRangeB_uid46_fpLogETest_0_to_finalSum_uid46_uid49_fpLogETest_0_q;
--FullSumAB117_uid50_fpLogETest(BITSELECT,49)@31
FullSumAB117_uid50_fpLogETest_in <= finalSum_uid46_uid49_fpLogETest_q;
FullSumAB117_uid50_fpLogETest_b <= FullSumAB117_uid50_fpLogETest_in(117 downto 117);
--notC_uid71_fpLogETest(LOGICAL,70)@31
notC_uid71_fpLogETest_a <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_q;
notC_uid71_fpLogETest_q <= not notC_uid71_fpLogETest_a;
--signTerm2_uid72_fpLogETest(LOGICAL,71)@31
signTerm2_uid72_fpLogETest_a <= notC_uid71_fpLogETest_q;
signTerm2_uid72_fpLogETest_b <= FullSumAB117_uid50_fpLogETest_b;
signTerm2_uid72_fpLogETest_q <= signTerm2_uid72_fpLogETest_a and signTerm2_uid72_fpLogETest_b;
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_nor(LOGICAL,966)
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_nor_b <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_sticky_ena_q;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_nor_q <= not (ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_nor_a or ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_nor_b);
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_mem_top(CONSTANT,962)
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_mem_top_q <= "011100";
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmp(LOGICAL,963)
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmp_a <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_mem_top_q;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_q);
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmp_q <= "1" when ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmp_a = ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmp_b else "0";
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmpReg(REG,964)
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmpReg_q <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_sticky_ena(REG,967)
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_nor_q = "1") THEN
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_sticky_ena_q <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_enaAnd(LOGICAL,968)
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_enaAnd_a <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_sticky_ena_q;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_enaAnd_b <= en;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_enaAnd_q <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_enaAnd_a and ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_enaAnd_b;
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_inputreg(DELAY,956)
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => c_uid31_fpLogETest_q, xout => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt(COUNTER,958)
-- every=1, low=0, high=28, step=1, init=1
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_i = 27 THEN
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_eq <= '1';
ELSE
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_eq = '1') THEN
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_i <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_i - 28;
ELSE
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_i <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_i,5));
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg(REG,959)
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg_q <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux(MUX,960)
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_s <= en;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux: PROCESS (ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_s, ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg_q, ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_q)
BEGIN
CASE ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_s IS
WHEN "0" => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_q <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg_q;
WHEN "1" => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_q <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdcnt_q;
WHEN OTHERS => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem(DUALMEM,957)
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_ia <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_inputreg_q;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_aa <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg_q;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_ab <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_q;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 29,
width_b => 1,
widthad_b => 5,
numwords_b => 29,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_iq,
address_a => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_aa,
data_a => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_ia
);
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_reset0 <= areset;
ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_q <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_iq(0 downto 0);
--signRC1_uid73_fpLogETest(LOGICAL,72)@31
signRC1_uid73_fpLogETest_a <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_mem_q;
signRC1_uid73_fpLogETest_b <= signTerm2_uid72_fpLogETest_q;
signRC1_uid73_fpLogETest_q_i <= signRC1_uid73_fpLogETest_a or signRC1_uid73_fpLogETest_b;
signRC1_uid73_fpLogETest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRC1_uid73_fpLogETest_q, xin => signRC1_uid73_fpLogETest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_nor(LOGICAL,979)
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_nor_b <= ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_sticky_ena_q;
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_nor_q <= not (ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_nor_a or ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_nor_b);
--ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_sticky_ena(REG,980)
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_nor_q = "1") THEN
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_sticky_ena_q <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_enaAnd(LOGICAL,981)
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_enaAnd_a <= ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_sticky_ena_q;
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_enaAnd_b <= en;
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_enaAnd_q <= ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_enaAnd_a and ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_enaAnd_b;
--cstAllZWF_uid8_fpLogETest(CONSTANT,7)
cstAllZWF_uid8_fpLogETest_q <= "0000000000000000000000000000000000000000000000000000";
--fracXIsZero_uid20_fpLogETest(LOGICAL,19)@0
fracXIsZero_uid20_fpLogETest_a <= frac_uid19_fpLogETest_b;
fracXIsZero_uid20_fpLogETest_b <= cstAllZWF_uid8_fpLogETest_q;
fracXIsZero_uid20_fpLogETest_q <= "1" when fracXIsZero_uid20_fpLogETest_a = fracXIsZero_uid20_fpLogETest_b else "0";
--InvFracXIsZero_uid22_fpLogETest(LOGICAL,21)@0
InvFracXIsZero_uid22_fpLogETest_a <= fracXIsZero_uid20_fpLogETest_q;
InvFracXIsZero_uid22_fpLogETest_q <= not InvFracXIsZero_uid22_fpLogETest_a;
--cstAllOWE_uid12_fpLogETest(CONSTANT,11)
cstAllOWE_uid12_fpLogETest_q <= "11111111111";
--expXIsMax_uid18_fpLogETest(LOGICAL,17)@0
expXIsMax_uid18_fpLogETest_a <= expX_uid6_fpLogETest_b;
expXIsMax_uid18_fpLogETest_b <= cstAllOWE_uid12_fpLogETest_q;
expXIsMax_uid18_fpLogETest_q <= "1" when expXIsMax_uid18_fpLogETest_a = expXIsMax_uid18_fpLogETest_b else "0";
--exc_N_uid23_fpLogETest(LOGICAL,22)@0
exc_N_uid23_fpLogETest_a <= expXIsMax_uid18_fpLogETest_q;
exc_N_uid23_fpLogETest_b <= InvFracXIsZero_uid22_fpLogETest_q;
exc_N_uid23_fpLogETest_q <= exc_N_uid23_fpLogETest_a and exc_N_uid23_fpLogETest_b;
--InvExc_N_uid24_fpLogETest(LOGICAL,23)@0
InvExc_N_uid24_fpLogETest_a <= exc_N_uid23_fpLogETest_q;
InvExc_N_uid24_fpLogETest_q <= not InvExc_N_uid24_fpLogETest_a;
--exc_I_uid21_fpLogETest(LOGICAL,20)@0
exc_I_uid21_fpLogETest_a <= expXIsMax_uid18_fpLogETest_q;
exc_I_uid21_fpLogETest_b <= fracXIsZero_uid20_fpLogETest_q;
exc_I_uid21_fpLogETest_q <= exc_I_uid21_fpLogETest_a and exc_I_uid21_fpLogETest_b;
--InvExc_I_uid25_fpLogETest(LOGICAL,24)@0
InvExc_I_uid25_fpLogETest_a <= exc_I_uid21_fpLogETest_q;
InvExc_I_uid25_fpLogETest_q <= not InvExc_I_uid25_fpLogETest_a;
--cstAllZWE_uid14_fpLogETest(CONSTANT,13)
cstAllZWE_uid14_fpLogETest_q <= "00000000000";
--expXIsZero_uid16_fpLogETest(LOGICAL,15)@0
expXIsZero_uid16_fpLogETest_a <= expX_uid6_fpLogETest_b;
expXIsZero_uid16_fpLogETest_b <= cstAllZWE_uid14_fpLogETest_q;
expXIsZero_uid16_fpLogETest_q <= "1" when expXIsZero_uid16_fpLogETest_a = expXIsZero_uid16_fpLogETest_b else "0";
--InvExpXIsZero_uid26_fpLogETest(LOGICAL,25)@0
InvExpXIsZero_uid26_fpLogETest_a <= expXIsZero_uid16_fpLogETest_q;
InvExpXIsZero_uid26_fpLogETest_q <= not InvExpXIsZero_uid26_fpLogETest_a;
--exc_R_uid27_fpLogETest(LOGICAL,26)@0
exc_R_uid27_fpLogETest_a <= InvExpXIsZero_uid26_fpLogETest_q;
exc_R_uid27_fpLogETest_b <= InvExc_I_uid25_fpLogETest_q;
exc_R_uid27_fpLogETest_c <= InvExc_N_uid24_fpLogETest_q;
exc_R_uid27_fpLogETest_q_i <= exc_R_uid27_fpLogETest_a and exc_R_uid27_fpLogETest_b and exc_R_uid27_fpLogETest_c;
exc_R_uid27_fpLogETest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => exc_R_uid27_fpLogETest_q, xin => exc_R_uid27_fpLogETest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_inputreg(DELAY,969)
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_R_uid27_fpLogETest_q, xout => ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem(DUALMEM,970)
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_ia <= ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_inputreg_q;
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_aa <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg_q;
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_ab <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_q;
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 29,
width_b => 1,
widthad_b => 5,
numwords_b => 29,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_iq,
address_a => ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_aa,
data_a => ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_ia
);
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_reset0 <= areset;
ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_q <= ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_iq(0 downto 0);
--signRC11_uid74_fpLogETest(LOGICAL,73)@32
signRC11_uid74_fpLogETest_a <= ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_replace_mem_q;
signRC11_uid74_fpLogETest_b <= signRC1_uid73_fpLogETest_q;
signRC11_uid74_fpLogETest_q <= signRC11_uid74_fpLogETest_a and signRC11_uid74_fpLogETest_b;
--ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_nor(LOGICAL,992)
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_nor_b <= ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_sticky_ena_q;
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_nor_q <= not (ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_nor_a or ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_nor_b);
--ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_sticky_ena(REG,993)
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_nor_q = "1") THEN
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_sticky_ena_q <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_enaAnd(LOGICAL,994)
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_enaAnd_a <= ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_sticky_ena_q;
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_enaAnd_b <= en;
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_enaAnd_q <= ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_enaAnd_a and ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_enaAnd_b;
--reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1(REG,437)@0
reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q <= expXIsZero_uid16_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_inputreg(DELAY,982)
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q, xout => ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem(DUALMEM,983)
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_ia <= ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_inputreg_q;
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_aa <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg_q;
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_ab <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_q;
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 29,
width_b => 1,
widthad_b => 5,
numwords_b => 29,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_iq,
address_a => ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_aa,
data_a => ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_ia
);
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_reset0 <= areset;
ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_q <= ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_iq(0 downto 0);
--signR_uid75_fpLogETest(LOGICAL,74)@32
signR_uid75_fpLogETest_a <= ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_replace_mem_q;
signR_uid75_fpLogETest_b <= signRC11_uid74_fpLogETest_q;
signR_uid75_fpLogETest_q <= signR_uid75_fpLogETest_a or signR_uid75_fpLogETest_b;
--ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_nor(LOGICAL,1005)
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_nor_b <= ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_sticky_ena_q;
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_nor_q <= not (ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_nor_a or ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_nor_b);
--ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_sticky_ena(REG,1006)
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_nor_q = "1") THEN
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_sticky_ena_q <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_enaAnd(LOGICAL,1007)
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_enaAnd_a <= ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_sticky_ena_q;
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_enaAnd_b <= en;
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_enaAnd_q <= ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_enaAnd_a and ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_enaAnd_b;
--signX_uid7_fpLogETest(BITSELECT,6)@0
signX_uid7_fpLogETest_in <= a;
signX_uid7_fpLogETest_b <= signX_uid7_fpLogETest_in(63 downto 63);
--negNonZero_uid69_fpLogETest(LOGICAL,68)@0
negNonZero_uid69_fpLogETest_a <= InvExpXIsZero_uid26_fpLogETest_q;
negNonZero_uid69_fpLogETest_b <= signX_uid7_fpLogETest_b;
negNonZero_uid69_fpLogETest_q <= negNonZero_uid69_fpLogETest_a and negNonZero_uid69_fpLogETest_b;
--excRNaN_uid70_fpLogETest(LOGICAL,69)@0
excRNaN_uid70_fpLogETest_a <= negNonZero_uid69_fpLogETest_q;
excRNaN_uid70_fpLogETest_b <= exc_N_uid23_fpLogETest_q;
excRNaN_uid70_fpLogETest_q <= excRNaN_uid70_fpLogETest_a or excRNaN_uid70_fpLogETest_b;
--ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_inputreg(DELAY,995)
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => excRNaN_uid70_fpLogETest_q, xout => ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem(DUALMEM,996)
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_ia <= ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_inputreg_q;
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_aa <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdreg_q;
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_ab <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_replace_rdmux_q;
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 29,
width_b => 1,
widthad_b => 5,
numwords_b => 29,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_iq,
address_a => ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_aa,
data_a => ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_ia
);
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_reset0 <= areset;
ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_q <= ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_iq(0 downto 0);
--InvExcRNaN_uid76_fpLogETest(LOGICAL,75)@31
InvExcRNaN_uid76_fpLogETest_a <= ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_replace_mem_q;
InvExcRNaN_uid76_fpLogETest_q_i <= not InvExcRNaN_uid76_fpLogETest_a;
InvExcRNaN_uid76_fpLogETest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => InvExcRNaN_uid76_fpLogETest_q, xin => InvExcRNaN_uid76_fpLogETest_q_i, clk => clk, aclr => areset);
--signRFull_uid77_fpLogETest(LOGICAL,76)@32
signRFull_uid77_fpLogETest_a <= InvExcRNaN_uid76_fpLogETest_q;
signRFull_uid77_fpLogETest_b <= signR_uid75_fpLogETest_q;
signRFull_uid77_fpLogETest_q_i <= signRFull_uid77_fpLogETest_a and signRFull_uid77_fpLogETest_b;
signRFull_uid77_fpLogETest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRFull_uid77_fpLogETest_q, xin => signRFull_uid77_fpLogETest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_signRFull_uid77_fpLogETest_q_to_RLn_uid88_fpLogETest_c(DELAY,522)@33
ld_signRFull_uid77_fpLogETest_q_to_RLn_uid88_fpLogETest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 8 )
PORT MAP ( xin => signRFull_uid77_fpLogETest_q, xout => ld_signRFull_uid77_fpLogETest_q_to_RLn_uid88_fpLogETest_c_q, ena => en(0), clk => clk, aclr => areset );
--zs_uid147_countZ_uid54_fpLogETest(CONSTANT,146)
zs_uid147_countZ_uid54_fpLogETest_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--ld_FullSumAB117_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b(DELAY,481)@31
ld_FullSumAB117_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => FullSumAB117_uid50_fpLogETest_b, xout => ld_FullSumAB117_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalSumOneComp_uid52_fpLogETest(LOGICAL,51)@31
finalSumOneComp_uid52_fpLogETest_a <= finalSum_uid46_uid49_fpLogETest_q;
finalSumOneComp_uid52_fpLogETest_b <= STD_LOGIC_VECTOR((117 downto 1 => FullSumAB117_uid50_fpLogETest_b(0)) & FullSumAB117_uid50_fpLogETest_b);
finalSumOneComp_uid52_fpLogETest_q_i <= finalSumOneComp_uid52_fpLogETest_a xor finalSumOneComp_uid52_fpLogETest_b;
finalSumOneComp_uid52_fpLogETest_delay : dspba_delay
GENERIC MAP (width => 118, depth => 1)
PORT MAP (xout => finalSumOneComp_uid52_fpLogETest_q, xin => finalSumOneComp_uid52_fpLogETest_q_i, clk => clk, ena => en(0), aclr => areset);
--finalSumAbs_uid53_fpLogETest(ADD,52)@32
finalSumAbs_uid53_fpLogETest_a <= STD_LOGIC_VECTOR((118 downto 118 => finalSumOneComp_uid52_fpLogETest_q(117)) & finalSumOneComp_uid52_fpLogETest_q);
finalSumAbs_uid53_fpLogETest_b <= STD_LOGIC_VECTOR((118 downto 1 => ld_FullSumAB117_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b_q(0)) & ld_FullSumAB117_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b_q);
finalSumAbs_uid53_fpLogETest_o <= STD_LOGIC_VECTOR(SIGNED(finalSumAbs_uid53_fpLogETest_a) + SIGNED(finalSumAbs_uid53_fpLogETest_b));
finalSumAbs_uid53_fpLogETest_q <= finalSumAbs_uid53_fpLogETest_o(118 downto 0);
--rVStage_uid148_countZ_uid54_fpLogETest(BITSELECT,147)@32
rVStage_uid148_countZ_uid54_fpLogETest_in <= finalSumAbs_uid53_fpLogETest_q;
rVStage_uid148_countZ_uid54_fpLogETest_b <= rVStage_uid148_countZ_uid54_fpLogETest_in(118 downto 55);
--reg_rVStage_uid148_countZ_uid54_fpLogETest_0_to_vCount_uid149_countZ_uid54_fpLogETest_1(REG,408)@32
reg_rVStage_uid148_countZ_uid54_fpLogETest_0_to_vCount_uid149_countZ_uid54_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid148_countZ_uid54_fpLogETest_0_to_vCount_uid149_countZ_uid54_fpLogETest_1_q <= "0000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid148_countZ_uid54_fpLogETest_0_to_vCount_uid149_countZ_uid54_fpLogETest_1_q <= rVStage_uid148_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid149_countZ_uid54_fpLogETest(LOGICAL,148)@33
vCount_uid149_countZ_uid54_fpLogETest_a <= reg_rVStage_uid148_countZ_uid54_fpLogETest_0_to_vCount_uid149_countZ_uid54_fpLogETest_1_q;
vCount_uid149_countZ_uid54_fpLogETest_b <= zs_uid147_countZ_uid54_fpLogETest_q;
vCount_uid149_countZ_uid54_fpLogETest_q <= "1" when vCount_uid149_countZ_uid54_fpLogETest_a = vCount_uid149_countZ_uid54_fpLogETest_b else "0";
--reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6(REG,422)@33
reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6_q <= vCount_uid149_countZ_uid54_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6_q_to_r_uid188_countZ_uid54_fpLogETest_g(DELAY,616)@34
ld_reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6_q_to_r_uid188_countZ_uid54_fpLogETest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6_q, xout => ld_reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6_q_to_r_uid188_countZ_uid54_fpLogETest_g_q, ena => en(0), clk => clk, aclr => areset );
--zs_uid155_countZ_uid54_fpLogETest(CONSTANT,154)
zs_uid155_countZ_uid54_fpLogETest_q <= "00000000000000000000000000000000";
--vStage_uid151_countZ_uid54_fpLogETest(BITSELECT,150)@32
vStage_uid151_countZ_uid54_fpLogETest_in <= finalSumAbs_uid53_fpLogETest_q(54 downto 0);
vStage_uid151_countZ_uid54_fpLogETest_b <= vStage_uid151_countZ_uid54_fpLogETest_in(54 downto 0);
--ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_cStage_uid152_countZ_uid54_fpLogETest_b(DELAY,574)@32
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_cStage_uid152_countZ_uid54_fpLogETest_b : dspba_delay
GENERIC MAP ( width => 55, depth => 1 )
PORT MAP ( xin => vStage_uid151_countZ_uid54_fpLogETest_b, xout => ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_cStage_uid152_countZ_uid54_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid150_countZ_uid54_fpLogETest(CONSTANT,149)
mO_uid150_countZ_uid54_fpLogETest_q <= "111111111";
--cStage_uid152_countZ_uid54_fpLogETest(BITJOIN,151)@33
cStage_uid152_countZ_uid54_fpLogETest_q <= ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_cStage_uid152_countZ_uid54_fpLogETest_b_q & mO_uid150_countZ_uid54_fpLogETest_q;
--ld_rVStage_uid148_countZ_uid54_fpLogETest_b_to_vStagei_uid154_countZ_uid54_fpLogETest_c(DELAY,576)@32
ld_rVStage_uid148_countZ_uid54_fpLogETest_b_to_vStagei_uid154_countZ_uid54_fpLogETest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid148_countZ_uid54_fpLogETest_b, xout => ld_rVStage_uid148_countZ_uid54_fpLogETest_b_to_vStagei_uid154_countZ_uid54_fpLogETest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid154_countZ_uid54_fpLogETest(MUX,153)@33
vStagei_uid154_countZ_uid54_fpLogETest_s <= vCount_uid149_countZ_uid54_fpLogETest_q;
vStagei_uid154_countZ_uid54_fpLogETest: PROCESS (vStagei_uid154_countZ_uid54_fpLogETest_s, en, ld_rVStage_uid148_countZ_uid54_fpLogETest_b_to_vStagei_uid154_countZ_uid54_fpLogETest_c_q, cStage_uid152_countZ_uid54_fpLogETest_q)
BEGIN
CASE vStagei_uid154_countZ_uid54_fpLogETest_s IS
WHEN "0" => vStagei_uid154_countZ_uid54_fpLogETest_q <= ld_rVStage_uid148_countZ_uid54_fpLogETest_b_to_vStagei_uid154_countZ_uid54_fpLogETest_c_q;
WHEN "1" => vStagei_uid154_countZ_uid54_fpLogETest_q <= cStage_uid152_countZ_uid54_fpLogETest_q;
WHEN OTHERS => vStagei_uid154_countZ_uid54_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid156_countZ_uid54_fpLogETest(BITSELECT,155)@33
rVStage_uid156_countZ_uid54_fpLogETest_in <= vStagei_uid154_countZ_uid54_fpLogETest_q;
rVStage_uid156_countZ_uid54_fpLogETest_b <= rVStage_uid156_countZ_uid54_fpLogETest_in(63 downto 32);
--reg_rVStage_uid156_countZ_uid54_fpLogETest_0_to_vCount_uid157_countZ_uid54_fpLogETest_1(REG,409)@33
reg_rVStage_uid156_countZ_uid54_fpLogETest_0_to_vCount_uid157_countZ_uid54_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid156_countZ_uid54_fpLogETest_0_to_vCount_uid157_countZ_uid54_fpLogETest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid156_countZ_uid54_fpLogETest_0_to_vCount_uid157_countZ_uid54_fpLogETest_1_q <= rVStage_uid156_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid157_countZ_uid54_fpLogETest(LOGICAL,156)@34
vCount_uid157_countZ_uid54_fpLogETest_a <= reg_rVStage_uid156_countZ_uid54_fpLogETest_0_to_vCount_uid157_countZ_uid54_fpLogETest_1_q;
vCount_uid157_countZ_uid54_fpLogETest_b <= zs_uid155_countZ_uid54_fpLogETest_q;
vCount_uid157_countZ_uid54_fpLogETest_q <= "1" when vCount_uid157_countZ_uid54_fpLogETest_a = vCount_uid157_countZ_uid54_fpLogETest_b else "0";
--ld_vCount_uid157_countZ_uid54_fpLogETest_q_to_reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5_a(DELAY,876)@34
ld_vCount_uid157_countZ_uid54_fpLogETest_q_to_reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid157_countZ_uid54_fpLogETest_q, xout => ld_vCount_uid157_countZ_uid54_fpLogETest_q_to_reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5(REG,421)@36
reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5_q <= ld_vCount_uid157_countZ_uid54_fpLogETest_q_to_reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5_a_q;
END IF;
END IF;
END PROCESS;
--zs_uid161_countZ_uid54_fpLogETest(CONSTANT,160)
zs_uid161_countZ_uid54_fpLogETest_q <= "0000000000000000";
--vStage_uid158_countZ_uid54_fpLogETest(BITSELECT,157)@33
vStage_uid158_countZ_uid54_fpLogETest_in <= vStagei_uid154_countZ_uid54_fpLogETest_q(31 downto 0);
vStage_uid158_countZ_uid54_fpLogETest_b <= vStage_uid158_countZ_uid54_fpLogETest_in(31 downto 0);
--reg_vStage_uid158_countZ_uid54_fpLogETest_0_to_vStagei_uid160_countZ_uid54_fpLogETest_3(REG,411)@33
reg_vStage_uid158_countZ_uid54_fpLogETest_0_to_vStagei_uid160_countZ_uid54_fpLogETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid158_countZ_uid54_fpLogETest_0_to_vStagei_uid160_countZ_uid54_fpLogETest_3_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid158_countZ_uid54_fpLogETest_0_to_vStagei_uid160_countZ_uid54_fpLogETest_3_q <= vStage_uid158_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid160_countZ_uid54_fpLogETest(MUX,159)@34
vStagei_uid160_countZ_uid54_fpLogETest_s <= vCount_uid157_countZ_uid54_fpLogETest_q;
vStagei_uid160_countZ_uid54_fpLogETest: PROCESS (vStagei_uid160_countZ_uid54_fpLogETest_s, en, reg_rVStage_uid156_countZ_uid54_fpLogETest_0_to_vCount_uid157_countZ_uid54_fpLogETest_1_q, reg_vStage_uid158_countZ_uid54_fpLogETest_0_to_vStagei_uid160_countZ_uid54_fpLogETest_3_q)
BEGIN
CASE vStagei_uid160_countZ_uid54_fpLogETest_s IS
WHEN "0" => vStagei_uid160_countZ_uid54_fpLogETest_q <= reg_rVStage_uid156_countZ_uid54_fpLogETest_0_to_vCount_uid157_countZ_uid54_fpLogETest_1_q;
WHEN "1" => vStagei_uid160_countZ_uid54_fpLogETest_q <= reg_vStage_uid158_countZ_uid54_fpLogETest_0_to_vStagei_uid160_countZ_uid54_fpLogETest_3_q;
WHEN OTHERS => vStagei_uid160_countZ_uid54_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid162_countZ_uid54_fpLogETest(BITSELECT,161)@34
rVStage_uid162_countZ_uid54_fpLogETest_in <= vStagei_uid160_countZ_uid54_fpLogETest_q;
rVStage_uid162_countZ_uid54_fpLogETest_b <= rVStage_uid162_countZ_uid54_fpLogETest_in(31 downto 16);
--reg_rVStage_uid162_countZ_uid54_fpLogETest_0_to_vCount_uid163_countZ_uid54_fpLogETest_1(REG,412)@34
reg_rVStage_uid162_countZ_uid54_fpLogETest_0_to_vCount_uid163_countZ_uid54_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid162_countZ_uid54_fpLogETest_0_to_vCount_uid163_countZ_uid54_fpLogETest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid162_countZ_uid54_fpLogETest_0_to_vCount_uid163_countZ_uid54_fpLogETest_1_q <= rVStage_uid162_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid163_countZ_uid54_fpLogETest(LOGICAL,162)@35
vCount_uid163_countZ_uid54_fpLogETest_a <= reg_rVStage_uid162_countZ_uid54_fpLogETest_0_to_vCount_uid163_countZ_uid54_fpLogETest_1_q;
vCount_uid163_countZ_uid54_fpLogETest_b <= zs_uid161_countZ_uid54_fpLogETest_q;
vCount_uid163_countZ_uid54_fpLogETest_q <= "1" when vCount_uid163_countZ_uid54_fpLogETest_a = vCount_uid163_countZ_uid54_fpLogETest_b else "0";
--ld_vCount_uid163_countZ_uid54_fpLogETest_q_to_reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4_a(DELAY,875)@35
ld_vCount_uid163_countZ_uid54_fpLogETest_q_to_reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid163_countZ_uid54_fpLogETest_q, xout => ld_vCount_uid163_countZ_uid54_fpLogETest_q_to_reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4(REG,420)@36
reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4_q <= ld_vCount_uid163_countZ_uid54_fpLogETest_q_to_reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4_a_q;
END IF;
END IF;
END PROCESS;
--zs_uid167_countZ_uid54_fpLogETest(CONSTANT,166)
zs_uid167_countZ_uid54_fpLogETest_q <= "00000000";
--vStage_uid164_countZ_uid54_fpLogETest(BITSELECT,163)@34
vStage_uid164_countZ_uid54_fpLogETest_in <= vStagei_uid160_countZ_uid54_fpLogETest_q(15 downto 0);
vStage_uid164_countZ_uid54_fpLogETest_b <= vStage_uid164_countZ_uid54_fpLogETest_in(15 downto 0);
--reg_vStage_uid164_countZ_uid54_fpLogETest_0_to_vStagei_uid166_countZ_uid54_fpLogETest_3(REG,414)@34
reg_vStage_uid164_countZ_uid54_fpLogETest_0_to_vStagei_uid166_countZ_uid54_fpLogETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid164_countZ_uid54_fpLogETest_0_to_vStagei_uid166_countZ_uid54_fpLogETest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid164_countZ_uid54_fpLogETest_0_to_vStagei_uid166_countZ_uid54_fpLogETest_3_q <= vStage_uid164_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid166_countZ_uid54_fpLogETest(MUX,165)@35
vStagei_uid166_countZ_uid54_fpLogETest_s <= vCount_uid163_countZ_uid54_fpLogETest_q;
vStagei_uid166_countZ_uid54_fpLogETest: PROCESS (vStagei_uid166_countZ_uid54_fpLogETest_s, en, reg_rVStage_uid162_countZ_uid54_fpLogETest_0_to_vCount_uid163_countZ_uid54_fpLogETest_1_q, reg_vStage_uid164_countZ_uid54_fpLogETest_0_to_vStagei_uid166_countZ_uid54_fpLogETest_3_q)
BEGIN
CASE vStagei_uid166_countZ_uid54_fpLogETest_s IS
WHEN "0" => vStagei_uid166_countZ_uid54_fpLogETest_q <= reg_rVStage_uid162_countZ_uid54_fpLogETest_0_to_vCount_uid163_countZ_uid54_fpLogETest_1_q;
WHEN "1" => vStagei_uid166_countZ_uid54_fpLogETest_q <= reg_vStage_uid164_countZ_uid54_fpLogETest_0_to_vStagei_uid166_countZ_uid54_fpLogETest_3_q;
WHEN OTHERS => vStagei_uid166_countZ_uid54_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid168_countZ_uid54_fpLogETest(BITSELECT,167)@35
rVStage_uid168_countZ_uid54_fpLogETest_in <= vStagei_uid166_countZ_uid54_fpLogETest_q;
rVStage_uid168_countZ_uid54_fpLogETest_b <= rVStage_uid168_countZ_uid54_fpLogETest_in(15 downto 8);
--vCount_uid169_countZ_uid54_fpLogETest(LOGICAL,168)@35
vCount_uid169_countZ_uid54_fpLogETest_a <= rVStage_uid168_countZ_uid54_fpLogETest_b;
vCount_uid169_countZ_uid54_fpLogETest_b <= zs_uid167_countZ_uid54_fpLogETest_q;
vCount_uid169_countZ_uid54_fpLogETest_q_i <= "1" when vCount_uid169_countZ_uid54_fpLogETest_a = vCount_uid169_countZ_uid54_fpLogETest_b else "0";
vCount_uid169_countZ_uid54_fpLogETest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid169_countZ_uid54_fpLogETest_q, xin => vCount_uid169_countZ_uid54_fpLogETest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid169_countZ_uid54_fpLogETest_q_to_r_uid188_countZ_uid54_fpLogETest_d(DELAY,613)@36
ld_vCount_uid169_countZ_uid54_fpLogETest_q_to_r_uid188_countZ_uid54_fpLogETest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid169_countZ_uid54_fpLogETest_q, xout => ld_vCount_uid169_countZ_uid54_fpLogETest_q_to_r_uid188_countZ_uid54_fpLogETest_d_q, ena => en(0), clk => clk, aclr => areset );
--zs_uid173_countZ_uid54_fpLogETest(CONSTANT,172)
zs_uid173_countZ_uid54_fpLogETest_q <= "0000";
--vStage_uid170_countZ_uid54_fpLogETest(BITSELECT,169)@35
vStage_uid170_countZ_uid54_fpLogETest_in <= vStagei_uid166_countZ_uid54_fpLogETest_q(7 downto 0);
vStage_uid170_countZ_uid54_fpLogETest_b <= vStage_uid170_countZ_uid54_fpLogETest_in(7 downto 0);
--reg_vStage_uid170_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_3(REG,416)@35
reg_vStage_uid170_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid170_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid170_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_3_q <= vStage_uid170_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid168_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_2(REG,415)@35
reg_rVStage_uid168_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid168_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid168_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_2_q <= rVStage_uid168_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid172_countZ_uid54_fpLogETest(MUX,171)@36
vStagei_uid172_countZ_uid54_fpLogETest_s <= vCount_uid169_countZ_uid54_fpLogETest_q;
vStagei_uid172_countZ_uid54_fpLogETest: PROCESS (vStagei_uid172_countZ_uid54_fpLogETest_s, en, reg_rVStage_uid168_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_2_q, reg_vStage_uid170_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_3_q)
BEGIN
CASE vStagei_uid172_countZ_uid54_fpLogETest_s IS
WHEN "0" => vStagei_uid172_countZ_uid54_fpLogETest_q <= reg_rVStage_uid168_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_2_q;
WHEN "1" => vStagei_uid172_countZ_uid54_fpLogETest_q <= reg_vStage_uid170_countZ_uid54_fpLogETest_0_to_vStagei_uid172_countZ_uid54_fpLogETest_3_q;
WHEN OTHERS => vStagei_uid172_countZ_uid54_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid174_countZ_uid54_fpLogETest(BITSELECT,173)@36
rVStage_uid174_countZ_uid54_fpLogETest_in <= vStagei_uid172_countZ_uid54_fpLogETest_q;
rVStage_uid174_countZ_uid54_fpLogETest_b <= rVStage_uid174_countZ_uid54_fpLogETest_in(7 downto 4);
--vCount_uid175_countZ_uid54_fpLogETest(LOGICAL,174)@36
vCount_uid175_countZ_uid54_fpLogETest_a <= rVStage_uid174_countZ_uid54_fpLogETest_b;
vCount_uid175_countZ_uid54_fpLogETest_b <= zs_uid173_countZ_uid54_fpLogETest_q;
vCount_uid175_countZ_uid54_fpLogETest_q <= "1" when vCount_uid175_countZ_uid54_fpLogETest_a = vCount_uid175_countZ_uid54_fpLogETest_b else "0";
--reg_vCount_uid175_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_2(REG,419)@36
reg_vCount_uid175_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid175_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid175_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_2_q <= vCount_uid175_countZ_uid54_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid176_countZ_uid54_fpLogETest(BITSELECT,175)@36
vStage_uid176_countZ_uid54_fpLogETest_in <= vStagei_uid172_countZ_uid54_fpLogETest_q(3 downto 0);
vStage_uid176_countZ_uid54_fpLogETest_b <= vStage_uid176_countZ_uid54_fpLogETest_in(3 downto 0);
--vStagei_uid178_countZ_uid54_fpLogETest(MUX,177)@36
vStagei_uid178_countZ_uid54_fpLogETest_s <= vCount_uid175_countZ_uid54_fpLogETest_q;
vStagei_uid178_countZ_uid54_fpLogETest: PROCESS (vStagei_uid178_countZ_uid54_fpLogETest_s, en, rVStage_uid174_countZ_uid54_fpLogETest_b, vStage_uid176_countZ_uid54_fpLogETest_b)
BEGIN
CASE vStagei_uid178_countZ_uid54_fpLogETest_s IS
WHEN "0" => vStagei_uid178_countZ_uid54_fpLogETest_q <= rVStage_uid174_countZ_uid54_fpLogETest_b;
WHEN "1" => vStagei_uid178_countZ_uid54_fpLogETest_q <= vStage_uid176_countZ_uid54_fpLogETest_b;
WHEN OTHERS => vStagei_uid178_countZ_uid54_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid180_countZ_uid54_fpLogETest(BITSELECT,179)@36
rVStage_uid180_countZ_uid54_fpLogETest_in <= vStagei_uid178_countZ_uid54_fpLogETest_q;
rVStage_uid180_countZ_uid54_fpLogETest_b <= rVStage_uid180_countZ_uid54_fpLogETest_in(3 downto 2);
--vCount_uid181_countZ_uid54_fpLogETest(LOGICAL,180)@36
vCount_uid181_countZ_uid54_fpLogETest_a <= rVStage_uid180_countZ_uid54_fpLogETest_b;
vCount_uid181_countZ_uid54_fpLogETest_b <= z2_uid40_fpLogETest_q;
vCount_uid181_countZ_uid54_fpLogETest_q_i <= "1" when vCount_uid181_countZ_uid54_fpLogETest_a = vCount_uid181_countZ_uid54_fpLogETest_b else "0";
vCount_uid181_countZ_uid54_fpLogETest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid181_countZ_uid54_fpLogETest_q, xin => vCount_uid181_countZ_uid54_fpLogETest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid182_countZ_uid54_fpLogETest(BITSELECT,181)@36
vStage_uid182_countZ_uid54_fpLogETest_in <= vStagei_uid178_countZ_uid54_fpLogETest_q(1 downto 0);
vStage_uid182_countZ_uid54_fpLogETest_b <= vStage_uid182_countZ_uid54_fpLogETest_in(1 downto 0);
--reg_vStage_uid182_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_3(REG,418)@36
reg_vStage_uid182_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid182_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid182_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_3_q <= vStage_uid182_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid180_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_2(REG,417)@36
reg_rVStage_uid180_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid180_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid180_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_2_q <= rVStage_uid180_countZ_uid54_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid184_countZ_uid54_fpLogETest(MUX,183)@37
vStagei_uid184_countZ_uid54_fpLogETest_s <= vCount_uid181_countZ_uid54_fpLogETest_q;
vStagei_uid184_countZ_uid54_fpLogETest: PROCESS (vStagei_uid184_countZ_uid54_fpLogETest_s, en, reg_rVStage_uid180_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_2_q, reg_vStage_uid182_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_3_q)
BEGIN
CASE vStagei_uid184_countZ_uid54_fpLogETest_s IS
WHEN "0" => vStagei_uid184_countZ_uid54_fpLogETest_q <= reg_rVStage_uid180_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_2_q;
WHEN "1" => vStagei_uid184_countZ_uid54_fpLogETest_q <= reg_vStage_uid182_countZ_uid54_fpLogETest_0_to_vStagei_uid184_countZ_uid54_fpLogETest_3_q;
WHEN OTHERS => vStagei_uid184_countZ_uid54_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid186_countZ_uid54_fpLogETest(BITSELECT,185)@37
rVStage_uid186_countZ_uid54_fpLogETest_in <= vStagei_uid184_countZ_uid54_fpLogETest_q;
rVStage_uid186_countZ_uid54_fpLogETest_b <= rVStage_uid186_countZ_uid54_fpLogETest_in(1 downto 1);
--vCount_uid187_countZ_uid54_fpLogETest(LOGICAL,186)@37
vCount_uid187_countZ_uid54_fpLogETest_a <= rVStage_uid186_countZ_uid54_fpLogETest_b;
vCount_uid187_countZ_uid54_fpLogETest_b <= GND_q;
vCount_uid187_countZ_uid54_fpLogETest_q <= "1" when vCount_uid187_countZ_uid54_fpLogETest_a = vCount_uid187_countZ_uid54_fpLogETest_b else "0";
--r_uid188_countZ_uid54_fpLogETest(BITJOIN,187)@37
r_uid188_countZ_uid54_fpLogETest_q <= ld_reg_vCount_uid149_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_6_q_to_r_uid188_countZ_uid54_fpLogETest_g_q & reg_vCount_uid157_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_5_q & reg_vCount_uid163_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_4_q & ld_vCount_uid169_countZ_uid54_fpLogETest_q_to_r_uid188_countZ_uid54_fpLogETest_d_q & reg_vCount_uid175_countZ_uid54_fpLogETest_0_to_r_uid188_countZ_uid54_fpLogETest_2_q & vCount_uid181_countZ_uid54_fpLogETest_q & vCount_uid187_countZ_uid54_fpLogETest_q;
--ld_r_uid188_countZ_uid54_fpLogETest_q_to_expRExt_uid57_fpLogETest_b(DELAY,482)@37
ld_r_uid188_countZ_uid54_fpLogETest_q_to_expRExt_uid57_fpLogETest_b : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => r_uid188_countZ_uid54_fpLogETest_q, xout => ld_r_uid188_countZ_uid54_fpLogETest_q_to_expRExt_uid57_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstMSBFinalSumPBias_uid56_fpLogETest(CONSTANT,55)
cstMSBFinalSumPBias_uid56_fpLogETest_q <= "010000001100";
--expRExt_uid57_fpLogETest(SUB,56)@38
expRExt_uid57_fpLogETest_a <= STD_LOGIC_VECTOR("0" & cstMSBFinalSumPBias_uid56_fpLogETest_q);
expRExt_uid57_fpLogETest_b <= STD_LOGIC_VECTOR("000000" & ld_r_uid188_countZ_uid54_fpLogETest_q_to_expRExt_uid57_fpLogETest_b_q);
expRExt_uid57_fpLogETest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRExt_uid57_fpLogETest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expRExt_uid57_fpLogETest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRExt_uid57_fpLogETest_a) - UNSIGNED(expRExt_uid57_fpLogETest_b));
END IF;
END IF;
END PROCESS;
expRExt_uid57_fpLogETest_q <= expRExt_uid57_fpLogETest_o(12 downto 0);
--LeftShiftStage2117dto0_uid225_normVal_uid55_fpLogETest(BITSELECT,224)@39
LeftShiftStage2117dto0_uid225_normVal_uid55_fpLogETest_in <= leftShiftStage2_uid223_normVal_uid55_fpLogETest_q(117 downto 0);
LeftShiftStage2117dto0_uid225_normVal_uid55_fpLogETest_b <= LeftShiftStage2117dto0_uid225_normVal_uid55_fpLogETest_in(117 downto 0);
--leftShiftStage3Idx1_uid226_normVal_uid55_fpLogETest(BITJOIN,225)@39
leftShiftStage3Idx1_uid226_normVal_uid55_fpLogETest_q <= LeftShiftStage2117dto0_uid225_normVal_uid55_fpLogETest_b & GND_q;
--ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_nor(LOGICAL,1114)
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_nor_b <= ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_sticky_ena_q;
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_nor_q <= not (ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_nor_a or ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_nor_b);
--ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_sticky_ena(REG,1115)
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_nor_q = "1") THEN
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_sticky_ena_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_enaAnd(LOGICAL,1116)
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_enaAnd_a <= ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_sticky_ena_q;
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_enaAnd_b <= en;
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_enaAnd_q <= ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_enaAnd_a and ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_enaAnd_b;
--X22dto0_uid198_normVal_uid55_fpLogETest(BITSELECT,197)@32
X22dto0_uid198_normVal_uid55_fpLogETest_in <= finalSumAbs_uid53_fpLogETest_q(22 downto 0);
X22dto0_uid198_normVal_uid55_fpLogETest_b <= X22dto0_uid198_normVal_uid55_fpLogETest_in(22 downto 0);
--ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_inputreg(DELAY,1106)
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => X22dto0_uid198_normVal_uid55_fpLogETest_b, xout => ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem(DUALMEM,1107)
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_ia <= ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_inputreg_q;
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_aa <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q;
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_ab <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q;
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 1,
numwords_a => 2,
width_b => 23,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_iq,
address_a => ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_aa,
data_a => ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_ia
);
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_reset0 <= areset;
ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_q <= ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_iq(22 downto 0);
--leftShiftStage0Idx3Pad96_uid197_normVal_uid55_fpLogETest(CONSTANT,196)
leftShiftStage0Idx3Pad96_uid197_normVal_uid55_fpLogETest_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest(BITJOIN,198)@36
leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_q <= ld_X22dto0_uid198_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_b_replace_mem_q & leftShiftStage0Idx3Pad96_uid197_normVal_uid55_fpLogETest_q;
--reg_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_5(REG,426)@36
reg_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_5_q <= leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_nor(LOGICAL,1103)
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_nor_b <= ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_sticky_ena_q;
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_nor_q <= not (ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_nor_a or ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_nor_b);
--ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_sticky_ena(REG,1104)
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_nor_q = "1") THEN
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_sticky_ena_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_enaAnd(LOGICAL,1105)
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_enaAnd_a <= ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_sticky_ena_q;
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_enaAnd_b <= en;
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_enaAnd_q <= ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_enaAnd_a and ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_enaAnd_b;
--ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem(DUALMEM,1096)
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_ia <= ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_cStage_uid152_countZ_uid54_fpLogETest_b_q;
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_aa <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q;
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_ab <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q;
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 55,
widthad_a => 1,
numwords_a => 2,
width_b => 55,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_iq,
address_a => ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_aa,
data_a => ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_ia
);
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_reset0 <= areset;
ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_q <= ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_iq(54 downto 0);
--leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest(BITJOIN,195)@36
leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_q <= ld_vStage_uid151_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_b_replace_mem_q & zs_uid147_countZ_uid54_fpLogETest_q;
--reg_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_4(REG,425)@36
reg_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_4_q <= leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_nor(LOGICAL,1092)
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_nor_b <= ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_sticky_ena_q;
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_nor_q <= not (ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_nor_a or ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_nor_b);
--ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_sticky_ena(REG,1093)
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_nor_q = "1") THEN
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_sticky_ena_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_enaAnd(LOGICAL,1094)
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_enaAnd_a <= ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_sticky_ena_q;
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_enaAnd_b <= en;
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_enaAnd_q <= ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_enaAnd_a and ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_enaAnd_b;
--X86dto0_uid192_normVal_uid55_fpLogETest(BITSELECT,191)@32
X86dto0_uid192_normVal_uid55_fpLogETest_in <= finalSumAbs_uid53_fpLogETest_q(86 downto 0);
X86dto0_uid192_normVal_uid55_fpLogETest_b <= X86dto0_uid192_normVal_uid55_fpLogETest_in(86 downto 0);
--ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_inputreg(DELAY,1084)
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_inputreg : dspba_delay
GENERIC MAP ( width => 87, depth => 1 )
PORT MAP ( xin => X86dto0_uid192_normVal_uid55_fpLogETest_b, xout => ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem(DUALMEM,1085)
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_ia <= ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_inputreg_q;
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_aa <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q;
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_ab <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q;
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 87,
widthad_a => 1,
numwords_a => 2,
width_b => 87,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_iq,
address_a => ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_aa,
data_a => ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_ia
);
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_reset0 <= areset;
ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_q <= ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_iq(86 downto 0);
--leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest(BITJOIN,192)@36
leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_q <= ld_X86dto0_uid192_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_b_replace_mem_q & zs_uid155_countZ_uid54_fpLogETest_q;
--reg_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_3(REG,424)@36
reg_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_3_q <= leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_nor(LOGICAL,1162)
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_nor_b <= ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_sticky_ena_q;
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_nor_q <= not (ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_nor_a or ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_nor_b);
--ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_sticky_ena(REG,1163)
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_nor_q = "1") THEN
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_sticky_ena_q <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_enaAnd(LOGICAL,1164)
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_enaAnd_a <= ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_sticky_ena_q;
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_enaAnd_b <= en;
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_enaAnd_q <= ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_enaAnd_a and ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_enaAnd_b;
--ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_inputreg(DELAY,1154)
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_inputreg : dspba_delay
GENERIC MAP ( width => 119, depth => 1 )
PORT MAP ( xin => finalSumAbs_uid53_fpLogETest_q, xout => ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem(DUALMEM,1155)
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_ia <= ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_inputreg_q;
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_aa <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdreg_q;
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_ab <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_replace_rdmux_q;
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 119,
widthad_a => 1,
numwords_a => 2,
width_b => 119,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_iq,
address_a => ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_aa,
data_a => ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_ia
);
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_reset0 <= areset;
ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_q <= ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_iq(118 downto 0);
--reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2(REG,423)@36
reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_q <= ld_finalSumAbs_uid53_fpLogETest_q_to_reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel6Dto5_uid200_normVal_uid55_fpLogETest(BITSELECT,199)@37
leftShiftStageSel6Dto5_uid200_normVal_uid55_fpLogETest_in <= r_uid188_countZ_uid54_fpLogETest_q;
leftShiftStageSel6Dto5_uid200_normVal_uid55_fpLogETest_b <= leftShiftStageSel6Dto5_uid200_normVal_uid55_fpLogETest_in(6 downto 5);
--leftShiftStage0_uid201_normVal_uid55_fpLogETest(MUX,200)@37
leftShiftStage0_uid201_normVal_uid55_fpLogETest_s <= leftShiftStageSel6Dto5_uid200_normVal_uid55_fpLogETest_b;
leftShiftStage0_uid201_normVal_uid55_fpLogETest: PROCESS (leftShiftStage0_uid201_normVal_uid55_fpLogETest_s, en, reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_q, reg_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_3_q, reg_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_4_q, reg_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_5_q)
BEGIN
CASE leftShiftStage0_uid201_normVal_uid55_fpLogETest_s IS
WHEN "00" => leftShiftStage0_uid201_normVal_uid55_fpLogETest_q <= reg_finalSumAbs_uid53_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_2_q;
WHEN "01" => leftShiftStage0_uid201_normVal_uid55_fpLogETest_q <= reg_leftShiftStage0Idx1_uid193_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_3_q;
WHEN "10" => leftShiftStage0_uid201_normVal_uid55_fpLogETest_q <= reg_leftShiftStage0Idx2_uid196_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_4_q;
WHEN "11" => leftShiftStage0_uid201_normVal_uid55_fpLogETest_q <= reg_leftShiftStage0Idx3_uid199_normVal_uid55_fpLogETest_0_to_leftShiftStage0_uid201_normVal_uid55_fpLogETest_5_q;
WHEN OTHERS => leftShiftStage0_uid201_normVal_uid55_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage094dto0_uid209_normVal_uid55_fpLogETest(BITSELECT,208)@37
LeftShiftStage094dto0_uid209_normVal_uid55_fpLogETest_in <= leftShiftStage0_uid201_normVal_uid55_fpLogETest_q(94 downto 0);
LeftShiftStage094dto0_uid209_normVal_uid55_fpLogETest_b <= LeftShiftStage094dto0_uid209_normVal_uid55_fpLogETest_in(94 downto 0);
--leftShiftStage1Idx3Pad24_uid208_normVal_uid55_fpLogETest(CONSTANT,207)
leftShiftStage1Idx3Pad24_uid208_normVal_uid55_fpLogETest_q <= "000000000000000000000000";
--leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest(BITJOIN,209)@37
leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest_q <= LeftShiftStage094dto0_uid209_normVal_uid55_fpLogETest_b & leftShiftStage1Idx3Pad24_uid208_normVal_uid55_fpLogETest_q;
--reg_leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_5(REG,431)@37
reg_leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_5_q <= leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0102dto0_uid206_normVal_uid55_fpLogETest(BITSELECT,205)@37
LeftShiftStage0102dto0_uid206_normVal_uid55_fpLogETest_in <= leftShiftStage0_uid201_normVal_uid55_fpLogETest_q(102 downto 0);
LeftShiftStage0102dto0_uid206_normVal_uid55_fpLogETest_b <= LeftShiftStage0102dto0_uid206_normVal_uid55_fpLogETest_in(102 downto 0);
--leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest(BITJOIN,206)@37
leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest_q <= LeftShiftStage0102dto0_uid206_normVal_uid55_fpLogETest_b & zs_uid161_countZ_uid54_fpLogETest_q;
--reg_leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_4(REG,430)@37
reg_leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_4_q <= leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage0110dto0_uid203_normVal_uid55_fpLogETest(BITSELECT,202)@37
LeftShiftStage0110dto0_uid203_normVal_uid55_fpLogETest_in <= leftShiftStage0_uid201_normVal_uid55_fpLogETest_q(110 downto 0);
LeftShiftStage0110dto0_uid203_normVal_uid55_fpLogETest_b <= LeftShiftStage0110dto0_uid203_normVal_uid55_fpLogETest_in(110 downto 0);
--leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest(BITJOIN,203)@37
leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest_q <= LeftShiftStage0110dto0_uid203_normVal_uid55_fpLogETest_b & zs_uid167_countZ_uid54_fpLogETest_q;
--reg_leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_3(REG,429)@37
reg_leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_3_q <= leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid201_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_2(REG,428)@37
reg_leftShiftStage0_uid201_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid201_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid201_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_2_q <= leftShiftStage0_uid201_normVal_uid55_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest(BITSELECT,210)@37
leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_in <= r_uid188_countZ_uid54_fpLogETest_q(4 downto 0);
leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_b <= leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_1(REG,427)@37
reg_leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_1_q <= leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid212_normVal_uid55_fpLogETest(MUX,211)@38
leftShiftStage1_uid212_normVal_uid55_fpLogETest_s <= reg_leftShiftStageSel4Dto3_uid211_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_1_q;
leftShiftStage1_uid212_normVal_uid55_fpLogETest: PROCESS (leftShiftStage1_uid212_normVal_uid55_fpLogETest_s, en, reg_leftShiftStage0_uid201_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_2_q, reg_leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_3_q, reg_leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_4_q, reg_leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_5_q)
BEGIN
CASE leftShiftStage1_uid212_normVal_uid55_fpLogETest_s IS
WHEN "00" => leftShiftStage1_uid212_normVal_uid55_fpLogETest_q <= reg_leftShiftStage0_uid201_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_2_q;
WHEN "01" => leftShiftStage1_uid212_normVal_uid55_fpLogETest_q <= reg_leftShiftStage1Idx1_uid204_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_3_q;
WHEN "10" => leftShiftStage1_uid212_normVal_uid55_fpLogETest_q <= reg_leftShiftStage1Idx2_uid207_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_4_q;
WHEN "11" => leftShiftStage1_uid212_normVal_uid55_fpLogETest_q <= reg_leftShiftStage1Idx3_uid210_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid212_normVal_uid55_fpLogETest_5_q;
WHEN OTHERS => leftShiftStage1_uid212_normVal_uid55_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest(BITSELECT,219)@38
LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_in <= leftShiftStage1_uid212_normVal_uid55_fpLogETest_q(112 downto 0);
LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_b <= LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_in(112 downto 0);
--ld_LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx3_uid221_normVal_uid55_fpLogETest_b(DELAY,645)@38
ld_LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx3_uid221_normVal_uid55_fpLogETest_b : dspba_delay
GENERIC MAP ( width => 113, depth => 1 )
PORT MAP ( xin => LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_b, xout => ld_LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx3_uid221_normVal_uid55_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad6_uid219_normVal_uid55_fpLogETest(CONSTANT,218)
leftShiftStage2Idx3Pad6_uid219_normVal_uid55_fpLogETest_q <= "000000";
--leftShiftStage2Idx3_uid221_normVal_uid55_fpLogETest(BITJOIN,220)@39
leftShiftStage2Idx3_uid221_normVal_uid55_fpLogETest_q <= ld_LeftShiftStage1112dto0_uid220_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx3_uid221_normVal_uid55_fpLogETest_b_q & leftShiftStage2Idx3Pad6_uid219_normVal_uid55_fpLogETest_q;
--LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest(BITSELECT,216)@38
LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_in <= leftShiftStage1_uid212_normVal_uid55_fpLogETest_q(114 downto 0);
LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_b <= LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_in(114 downto 0);
--ld_LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx2_uid218_normVal_uid55_fpLogETest_b(DELAY,643)@38
ld_LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx2_uid218_normVal_uid55_fpLogETest_b : dspba_delay
GENERIC MAP ( width => 115, depth => 1 )
PORT MAP ( xin => LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_b, xout => ld_LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx2_uid218_normVal_uid55_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid218_normVal_uid55_fpLogETest(BITJOIN,217)@39
leftShiftStage2Idx2_uid218_normVal_uid55_fpLogETest_q <= ld_LeftShiftStage1114dto0_uid217_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx2_uid218_normVal_uid55_fpLogETest_b_q & zs_uid173_countZ_uid54_fpLogETest_q;
--LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest(BITSELECT,213)@38
LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_in <= leftShiftStage1_uid212_normVal_uid55_fpLogETest_q(116 downto 0);
LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_b <= LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_in(116 downto 0);
--ld_LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx1_uid215_normVal_uid55_fpLogETest_b(DELAY,641)@38
ld_LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx1_uid215_normVal_uid55_fpLogETest_b : dspba_delay
GENERIC MAP ( width => 117, depth => 1 )
PORT MAP ( xin => LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_b, xout => ld_LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx1_uid215_normVal_uid55_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid215_normVal_uid55_fpLogETest(BITJOIN,214)@39
leftShiftStage2Idx1_uid215_normVal_uid55_fpLogETest_q <= ld_LeftShiftStage1116dto0_uid214_normVal_uid55_fpLogETest_b_to_leftShiftStage2Idx1_uid215_normVal_uid55_fpLogETest_b_q & z2_uid40_fpLogETest_q;
--reg_leftShiftStage1_uid212_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_2(REG,433)@38
reg_leftShiftStage1_uid212_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid212_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid212_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_2_q <= leftShiftStage1_uid212_normVal_uid55_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest(BITSELECT,221)@37
leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_in <= r_uid188_countZ_uid54_fpLogETest_q(2 downto 0);
leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_b <= leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1(REG,432)@37
reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1_q <= leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1_q_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_b(DELAY,647)@38
ld_reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1_q_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1_q, xout => ld_reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1_q_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid223_normVal_uid55_fpLogETest(MUX,222)@39
leftShiftStage2_uid223_normVal_uid55_fpLogETest_s <= ld_reg_leftShiftStageSel2Dto1_uid222_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_1_q_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_b_q;
leftShiftStage2_uid223_normVal_uid55_fpLogETest: PROCESS (leftShiftStage2_uid223_normVal_uid55_fpLogETest_s, en, reg_leftShiftStage1_uid212_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_2_q, leftShiftStage2Idx1_uid215_normVal_uid55_fpLogETest_q, leftShiftStage2Idx2_uid218_normVal_uid55_fpLogETest_q, leftShiftStage2Idx3_uid221_normVal_uid55_fpLogETest_q)
BEGIN
CASE leftShiftStage2_uid223_normVal_uid55_fpLogETest_s IS
WHEN "00" => leftShiftStage2_uid223_normVal_uid55_fpLogETest_q <= reg_leftShiftStage1_uid212_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid223_normVal_uid55_fpLogETest_2_q;
WHEN "01" => leftShiftStage2_uid223_normVal_uid55_fpLogETest_q <= leftShiftStage2Idx1_uid215_normVal_uid55_fpLogETest_q;
WHEN "10" => leftShiftStage2_uid223_normVal_uid55_fpLogETest_q <= leftShiftStage2Idx2_uid218_normVal_uid55_fpLogETest_q;
WHEN "11" => leftShiftStage2_uid223_normVal_uid55_fpLogETest_q <= leftShiftStage2Idx3_uid221_normVal_uid55_fpLogETest_q;
WHEN OTHERS => leftShiftStage2_uid223_normVal_uid55_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest(BITSELECT,226)@37
leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_in <= r_uid188_countZ_uid54_fpLogETest_q(0 downto 0);
leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_b <= leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_b_to_leftShiftStage3_uid228_normVal_uid55_fpLogETest_b(DELAY,655)@37
ld_leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_b_to_leftShiftStage3_uid228_normVal_uid55_fpLogETest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_b, xout => ld_leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_b_to_leftShiftStage3_uid228_normVal_uid55_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid228_normVal_uid55_fpLogETest(MUX,227)@39
leftShiftStage3_uid228_normVal_uid55_fpLogETest_s <= ld_leftShiftStageSel0Dto0_uid227_normVal_uid55_fpLogETest_b_to_leftShiftStage3_uid228_normVal_uid55_fpLogETest_b_q;
leftShiftStage3_uid228_normVal_uid55_fpLogETest: PROCESS (leftShiftStage3_uid228_normVal_uid55_fpLogETest_s, en, leftShiftStage2_uid223_normVal_uid55_fpLogETest_q, leftShiftStage3Idx1_uid226_normVal_uid55_fpLogETest_q)
BEGIN
CASE leftShiftStage3_uid228_normVal_uid55_fpLogETest_s IS
WHEN "0" => leftShiftStage3_uid228_normVal_uid55_fpLogETest_q <= leftShiftStage2_uid223_normVal_uid55_fpLogETest_q;
WHEN "1" => leftShiftStage3_uid228_normVal_uid55_fpLogETest_q <= leftShiftStage3Idx1_uid226_normVal_uid55_fpLogETest_q;
WHEN OTHERS => leftShiftStage3_uid228_normVal_uid55_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--fracR_uid58_fpLogETest(BITSELECT,57)@39
fracR_uid58_fpLogETest_in <= leftShiftStage3_uid228_normVal_uid55_fpLogETest_q(117 downto 0);
fracR_uid58_fpLogETest_b <= fracR_uid58_fpLogETest_in(117 downto 65);
--expFracConc_uid59_fpLogETest(BITJOIN,58)@39
expFracConc_uid59_fpLogETest_q <= expRExt_uid57_fpLogETest_q & fracR_uid58_fpLogETest_b;
--reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0(REG,434)@39
reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0_q <= expFracConc_uid59_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--expFracPostRnd_uid60_fpLogETest(ADD,59)@40
expFracPostRnd_uid60_fpLogETest_a <= STD_LOGIC_VECTOR("0" & reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0_q);
expFracPostRnd_uid60_fpLogETest_b <= STD_LOGIC_VECTOR("000000000000000000000000000000000000000000000000000000000000000000" & VCC_q);
expFracPostRnd_uid60_fpLogETest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracPostRnd_uid60_fpLogETest_a) + UNSIGNED(expFracPostRnd_uid60_fpLogETest_b));
expFracPostRnd_uid60_fpLogETest_q <= expFracPostRnd_uid60_fpLogETest_o(66 downto 0);
--expR_uid62_fpLogETest(BITSELECT,61)@40
expR_uid62_fpLogETest_in <= expFracPostRnd_uid60_fpLogETest_q(63 downto 0);
expR_uid62_fpLogETest_b <= expR_uid62_fpLogETest_in(63 downto 53);
--reg_expR_uid62_fpLogETest_0_to_expRPostExc_uid87_fpLogETest_3(REG,436)@40
reg_expR_uid62_fpLogETest_0_to_expRPostExc_uid87_fpLogETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expR_uid62_fpLogETest_0_to_expRPostExc_uid87_fpLogETest_3_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expR_uid62_fpLogETest_0_to_expRPostExc_uid87_fpLogETest_3_q <= expR_uid62_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_nor(LOGICAL,1018)
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_nor_b <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_sticky_ena_q;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_nor_q <= not (ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_nor_a or ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_nor_b);
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_mem_top(CONSTANT,1014)
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_mem_top_q <= "0100100";
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmp(LOGICAL,1015)
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmp_a <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_mem_top_q;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux_q);
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmp_q <= "1" when ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmp_a = ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmp_b else "0";
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmpReg(REG,1016)
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmpReg_q <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_sticky_ena(REG,1019)
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_nor_q = "1") THEN
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_sticky_ena_q <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_enaAnd(LOGICAL,1020)
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_enaAnd_a <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_sticky_ena_q;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_enaAnd_b <= en;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_enaAnd_q <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_enaAnd_a and ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_enaAnd_b;
--InvSignX_uid65_fpLogETest(LOGICAL,64)@0
InvSignX_uid65_fpLogETest_a <= signX_uid7_fpLogETest_b;
InvSignX_uid65_fpLogETest_q <= not InvSignX_uid65_fpLogETest_a;
--excRInfC1_uid66_fpLogETest(LOGICAL,65)@0
excRInfC1_uid66_fpLogETest_a <= exc_I_uid21_fpLogETest_q;
excRInfC1_uid66_fpLogETest_b <= InvSignX_uid65_fpLogETest_q;
excRInfC1_uid66_fpLogETest_q <= excRInfC1_uid66_fpLogETest_a and excRInfC1_uid66_fpLogETest_b;
--excRInf_uid67_fpLogETest(LOGICAL,66)@0
excRInf_uid67_fpLogETest_a <= excRInfC1_uid66_fpLogETest_q;
excRInf_uid67_fpLogETest_b <= expXIsZero_uid16_fpLogETest_q;
excRInf_uid67_fpLogETest_q <= excRInf_uid67_fpLogETest_a or excRInf_uid67_fpLogETest_b;
--FPOne_uid63_fpLogETest(BITJOIN,62)@0
FPOne_uid63_fpLogETest_q <= GND_q & cstBias_uid9_fpLogETest_q & cstAllZWF_uid8_fpLogETest_q;
--excRZero_uid64_fpLogETest(LOGICAL,63)@0
excRZero_uid64_fpLogETest_a <= a;
excRZero_uid64_fpLogETest_b <= FPOne_uid63_fpLogETest_q;
excRZero_uid64_fpLogETest_q <= "1" when excRZero_uid64_fpLogETest_a = excRZero_uid64_fpLogETest_b else "0";
--concExc_uid78_fpLogETest(BITJOIN,77)@0
concExc_uid78_fpLogETest_q <= excRNaN_uid70_fpLogETest_q & excRInf_uid67_fpLogETest_q & excRZero_uid64_fpLogETest_q;
--reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0(REG,319)@0
reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q <= concExc_uid78_fpLogETest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_inputreg(DELAY,1008)
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q, xout => ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt(COUNTER,1010)
-- every=1, low=0, high=36, step=1, init=1
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_i = 35 THEN
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_eq = '1') THEN
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_i <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_i - 36;
ELSE
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_i <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_i,6));
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdreg(REG,1011)
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdreg_q <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux(MUX,1012)
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux_s <= en;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux: PROCESS (ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux_s, ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdreg_q, ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux_q <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdreg_q;
WHEN "1" => ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux_q <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem(DUALMEM,1009)
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_ia <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_inputreg_q;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_aa <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdreg_q;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_ab <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_rdmux_q;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 6,
numwords_a => 37,
width_b => 3,
widthad_b => 6,
numwords_b => 37,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_iq,
address_a => ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_aa,
data_a => ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_ia
);
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_reset0 <= areset;
ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_q <= ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_iq(2 downto 0);
--excREnc_uid79_fpLogETest(LOOKUP,78)@40
excREnc_uid79_fpLogETest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
excREnc_uid79_fpLogETest_q <= "01";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q_to_excREnc_uid79_fpLogETest_a_replace_mem_q) IS
WHEN "000" => excREnc_uid79_fpLogETest_q <= "01";
WHEN "001" => excREnc_uid79_fpLogETest_q <= "00";
WHEN "010" => excREnc_uid79_fpLogETest_q <= "10";
WHEN "011" => excREnc_uid79_fpLogETest_q <= "00";
WHEN "100" => excREnc_uid79_fpLogETest_q <= "11";
WHEN "101" => excREnc_uid79_fpLogETest_q <= "00";
WHEN "110" => excREnc_uid79_fpLogETest_q <= "00";
WHEN "111" => excREnc_uid79_fpLogETest_q <= "00";
WHEN OTHERS =>
excREnc_uid79_fpLogETest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRPostExc_uid87_fpLogETest(MUX,86)@41
expRPostExc_uid87_fpLogETest_s <= excREnc_uid79_fpLogETest_q;
expRPostExc_uid87_fpLogETest: PROCESS (expRPostExc_uid87_fpLogETest_s, en, cstAllZWE_uid14_fpLogETest_q, reg_expR_uid62_fpLogETest_0_to_expRPostExc_uid87_fpLogETest_3_q, cstAllOWE_uid12_fpLogETest_q, cstAllOWE_uid12_fpLogETest_q)
BEGIN
CASE expRPostExc_uid87_fpLogETest_s IS
WHEN "00" => expRPostExc_uid87_fpLogETest_q <= cstAllZWE_uid14_fpLogETest_q;
WHEN "01" => expRPostExc_uid87_fpLogETest_q <= reg_expR_uid62_fpLogETest_0_to_expRPostExc_uid87_fpLogETest_3_q;
WHEN "10" => expRPostExc_uid87_fpLogETest_q <= cstAllOWE_uid12_fpLogETest_q;
WHEN "11" => expRPostExc_uid87_fpLogETest_q <= cstAllOWE_uid12_fpLogETest_q;
WHEN OTHERS => expRPostExc_uid87_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid80_fpLogETest(CONSTANT,79)
oneFracRPostExc2_uid80_fpLogETest_q <= "0000000000000000000000000000000000000000000000000001";
--fracR_uid61_fpLogETest(BITSELECT,60)@40
fracR_uid61_fpLogETest_in <= expFracPostRnd_uid60_fpLogETest_q(52 downto 0);
fracR_uid61_fpLogETest_b <= fracR_uid61_fpLogETest_in(52 downto 1);
--reg_fracR_uid61_fpLogETest_0_to_fracRPostExc_uid83_fpLogETest_3(REG,435)@40
reg_fracR_uid61_fpLogETest_0_to_fracRPostExc_uid83_fpLogETest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracR_uid61_fpLogETest_0_to_fracRPostExc_uid83_fpLogETest_3_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracR_uid61_fpLogETest_0_to_fracRPostExc_uid83_fpLogETest_3_q <= fracR_uid61_fpLogETest_b;
END IF;
END IF;
END PROCESS;
--fracRPostExc_uid83_fpLogETest(MUX,82)@41
fracRPostExc_uid83_fpLogETest_s <= excREnc_uid79_fpLogETest_q;
fracRPostExc_uid83_fpLogETest: PROCESS (fracRPostExc_uid83_fpLogETest_s, en, cstAllZWF_uid8_fpLogETest_q, reg_fracR_uid61_fpLogETest_0_to_fracRPostExc_uid83_fpLogETest_3_q, cstAllZWF_uid8_fpLogETest_q, oneFracRPostExc2_uid80_fpLogETest_q)
BEGIN
CASE fracRPostExc_uid83_fpLogETest_s IS
WHEN "00" => fracRPostExc_uid83_fpLogETest_q <= cstAllZWF_uid8_fpLogETest_q;
WHEN "01" => fracRPostExc_uid83_fpLogETest_q <= reg_fracR_uid61_fpLogETest_0_to_fracRPostExc_uid83_fpLogETest_3_q;
WHEN "10" => fracRPostExc_uid83_fpLogETest_q <= cstAllZWF_uid8_fpLogETest_q;
WHEN "11" => fracRPostExc_uid83_fpLogETest_q <= oneFracRPostExc2_uid80_fpLogETest_q;
WHEN OTHERS => fracRPostExc_uid83_fpLogETest_q <= (others => '0');
END CASE;
END PROCESS;
--RLn_uid88_fpLogETest(BITJOIN,87)@41
RLn_uid88_fpLogETest_q <= ld_signRFull_uid77_fpLogETest_q_to_RLn_uid88_fpLogETest_c_q & expRPostExc_uid87_fpLogETest_q & fracRPostExc_uid83_fpLogETest_q;
--xOut(GPOUT,4)@41
q <= RLn_uid88_fpLogETest_q;
end normal;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
bin_Gray_Processing/ip/Gray_Processing/hcc_cntusgn32.vhd
|
20
|
4321
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CNTUSGN32.VHD ***
--*** ***
--*** Function: Count leading bits in an ***
--*** unsigned 32 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_cntusgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_cntusgn32;
ARCHITECTURE rtl OF hcc_cntusgn32 IS
type positiontype IS ARRAY (6 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal sec, sel : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal lastfrac : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position : positiontype;
component hcc_usgnpos IS
GENERIC (start : integer := 10);
PORT (
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
-- for single 32 bit mantissa
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- for double 64 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [64][63..60][59][58..7][6..4][321] - NB underflow less than overflow
-- find first leading '1' in inexact portion for 32 bit positive number
sec(1) <= frac(31) OR frac(30) OR frac(29) OR frac(28) OR frac(27) OR frac(26);
sec(2) <= frac(25) OR frac(24) OR frac(23) OR frac(22) OR frac(21) OR frac(20);
sec(3) <= frac(19) OR frac(18) OR frac(17) OR frac(16) OR frac(15) OR frac(14);
sec(4) <= frac(13) OR frac(12) OR frac(11) OR frac(10) OR frac(9) OR frac(8);
sec(5) <= frac(7) OR frac(6) OR frac(5) OR frac(4) OR frac(3) OR frac(2);
sec(6) <= frac(1);
sel(1) <= sec(1);
sel(2) <= sec(2) AND NOT(sec(1));
sel(3) <= sec(3) AND NOT(sec(2)) AND NOT(sec(1));
sel(4) <= sec(4) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(5) <= sec(5) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(6) <= sec(6) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
pone: hcc_usgnpos
GENERIC MAP (start=>0)
PORT MAP (ingroup=>frac(31 DOWNTO 26),
position=>position(1)(6 DOWNTO 1));
ptwo: hcc_usgnpos
GENERIC MAP (start=>6)
PORT MAP (ingroup=>frac(25 DOWNTO 20),
position=>position(2)(6 DOWNTO 1));
pthr: hcc_usgnpos
GENERIC MAP (start=>12)
PORT MAP (ingroup=>frac(19 DOWNTO 14),
position=>position(3)(6 DOWNTO 1));
pfor: hcc_usgnpos
GENERIC MAP (start=>18)
PORT MAP (ingroup=>frac(13 DOWNTO 8),
position=>position(4)(6 DOWNTO 1));
pfiv: hcc_usgnpos
GENERIC MAP (start=>24)
PORT MAP (ingroup=>frac(7 DOWNTO 2),
position=>position(5)(6 DOWNTO 1));
psix: hcc_usgnpos
GENERIC MAP (start=>30)
PORT MAP (ingroup=>lastfrac,
position=>position(6)(6 DOWNTO 1));
lastfrac <= frac(1) & "00000";
gmc: FOR k IN 1 TO 6 GENERATE
count(k) <= (position(1)(k) AND sel(1)) OR
(position(2)(k) AND sel(2)) OR
(position(3)(k) AND sel(3)) OR
(position(4)(k) AND sel(4)) OR
(position(5)(k) AND sel(5)) OR
(position(6)(k) AND sel(6));
END GENERATE;
END rtl;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
bin_Gray_Processing/ip/Gray_Processing/SinDPStratixVf400_safe_path.vhd
|
10
|
427
|
-- safe_path for SinDPStratixVf400 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE SinDPStratixVf400_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END SinDPStratixVf400_safe_path;
PACKAGE body SinDPStratixVf400_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./") & path;
END FUNCTION safe_path;
END SinDPStratixVf400_safe_path;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
Gray_Processing/ip/Gray_Processing/dp_lnclzpipe.vhd
|
10
|
7272
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_LNCLZPIPE.VHD ***
--*** ***
--*** Function: Double Precision CLZ pipelined ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lnclzpipe IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mantissa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END dp_lnclzpipe;
ARCHITECTURE rtl of dp_lnclzpipe IS
type positiontype IS ARRAY (11 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position, positionff, positionmux : positiontype;
signal zerogroup, zerogroupff, firstzero : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal lastman : STD_LOGIC_VECTOR (6 DOWNTO 1);
component dp_pos
GENERIC (start: integer := 0);
PORT
(
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
zerogroup(1) <= mantissa(64) OR mantissa(63) OR mantissa(62) OR mantissa(61) OR mantissa(60) OR mantissa(59);
zerogroup(2) <= mantissa(58) OR mantissa(57) OR mantissa(56) OR mantissa(55) OR mantissa(54) OR mantissa(53);
zerogroup(3) <= mantissa(52) OR mantissa(51) OR mantissa(50) OR mantissa(49) OR mantissa(48) OR mantissa(47);
zerogroup(4) <= mantissa(46) OR mantissa(45) OR mantissa(44) OR mantissa(43) OR mantissa(42) OR mantissa(41);
zerogroup(5) <= mantissa(40) OR mantissa(39) OR mantissa(38) OR mantissa(37) OR mantissa(36) OR mantissa(35);
zerogroup(6) <= mantissa(34) OR mantissa(33) OR mantissa(32) OR mantissa(31) OR mantissa(30) OR mantissa(29);
zerogroup(7) <= mantissa(28) OR mantissa(27) OR mantissa(26) OR mantissa(25) OR mantissa(24) OR mantissa(23);
zerogroup(8) <= mantissa(22) OR mantissa(21) OR mantissa(20) OR mantissa(19) OR mantissa(18) OR mantissa(17);
zerogroup(9) <= mantissa(16) OR mantissa(15) OR mantissa(14) OR mantissa(13) OR mantissa(12) OR mantissa(11);
zerogroup(10) <= mantissa(10) OR mantissa(9) OR mantissa(8) OR mantissa(7) OR mantissa(6) OR mantissa(5);
zerogroup(11) <= mantissa(4) OR mantissa(3) OR mantissa(2) OR mantissa(1);
pa: dp_pos
GENERIC MAP (start=>0)
PORT MAP (ingroup=>mantissa(64 DOWNTO 59),position=>position(1)(6 DOWNTO 1));
pb: dp_pos
GENERIC MAP (start=>6)
PORT MAP (ingroup=>mantissa(58 DOWNTO 53),position=>position(2)(6 DOWNTO 1));
pc: dp_pos
GENERIC MAP (start=>12)
PORT MAP (ingroup=>mantissa(52 DOWNTO 47),position=>position(3)(6 DOWNTO 1));
pd: dp_pos
GENERIC MAP (start=>18)
PORT MAP (ingroup=>mantissa(46 DOWNTO 41),position=>position(4)(6 DOWNTO 1));
pe: dp_pos
GENERIC MAP (start=>24)
PORT MAP (ingroup=>mantissa(40 DOWNTO 35),position=>position(5)(6 DOWNTO 1));
pf: dp_pos
GENERIC MAP (start=>30)
PORT MAP (ingroup=>mantissa(34 DOWNTO 29),position=>position(6)(6 DOWNTO 1));
pg: dp_pos
GENERIC MAP (start=>36)
PORT MAP (ingroup=>mantissa(28 DOWNTO 23),position=>position(7)(6 DOWNTO 1));
ph: dp_pos
GENERIC MAP (start=>42)
PORT MAP (ingroup=>mantissa(22 DOWNTO 17),position=>position(8)(6 DOWNTO 1));
pi: dp_pos
GENERIC MAP (start=>48)
PORT MAP (ingroup=>mantissa(16 DOWNTO 11),position=>position(9)(6 DOWNTO 1));
pj: dp_pos
GENERIC MAP (start=>54)
PORT MAP (ingroup=>mantissa(10 DOWNTO 5),position=>position(10)(6 DOWNTO 1));
pk: dp_pos
GENERIC MAP (start=>60)
PORT MAP (ingroup=>lastman,position=>position(11)(6 DOWNTO 1));
lastman <= mantissa(4 DOWNTO 1) & "00";
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 11 LOOP
zerogroupff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
FOR j IN 1 TO 6 LOOP
positionff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
zerogroupff <= zerogroup;
FOR k IN 1 TO 11 LOOP
positionff(k)(6 DOWNTO 1) <= position(k)(6 DOWNTO 1);
END LOOP;
END IF;
END PROCESS;
firstzero(1) <= zerogroupff(1);
firstzero(2) <= NOT(zerogroupff(1)) AND zerogroupff(2);
firstzero(3) <= NOT(zerogroupff(1)) AND NOT(zerogroupff(2)) AND zerogroupff(3);
firstzero(4) <= NOT(zerogroupff(1)) AND NOT(zerogroupff(2)) AND NOT(zerogroupff(3)) AND zerogroupff(4);
firstzero(5) <= NOT(zerogroupff(1)) AND NOT(zerogroupff(2)) AND NOT(zerogroupff(3)) AND
NOT(zerogroupff(4)) AND zerogroupff(5);
firstzero(6) <= NOT(zerogroupff(1)) AND NOT(zerogroupff(2)) AND NOT(zerogroupff(3)) AND
NOT(zerogroupff(4)) AND NOT(zerogroupff(5)) AND zerogroupff(6);
firstzero(7) <= NOT(zerogroupff(1)) AND NOT(zerogroupff(2)) AND NOT(zerogroupff(3)) AND
NOT(zerogroupff(4)) AND NOT(zerogroupff(5)) AND NOT(zerogroupff(6)) AND zerogroupff(7);
firstzero(8) <= NOT(zerogroupff(1)) AND NOT(zerogroupff(2)) AND NOT(zerogroupff(3)) AND
NOT(zerogroupff(4)) AND NOT(zerogroupff(5)) AND NOT(zerogroupff(6)) AND
NOT(zerogroupff(7)) AND zerogroupff(8);
firstzero(9) <= NOT(zerogroupff(1)) AND NOT(zerogroupff(2)) AND NOT(zerogroupff(3)) AND
NOT(zerogroupff(4)) AND NOT(zerogroupff(5)) AND NOT(zerogroupff(6)) AND
NOT(zerogroupff(7)) AND NOT(zerogroupff(8)) AND zerogroupff(9);
firstzero(10) <= NOT(zerogroupff(1)) AND NOT(zerogroupff(2)) AND NOT(zerogroupff(3)) AND
NOT(zerogroupff(4)) AND NOT(zerogroupff(5)) AND NOT(zerogroupff(6)) AND
NOT(zerogroupff(7)) AND NOT(zerogroupff(8)) AND NOT(zerogroupff(9)) AND zerogroupff(10);
firstzero(11) <= NOT(zerogroupff(1)) AND NOT(zerogroupff(2)) AND NOT(zerogroupff(3)) AND
NOT(zerogroupff(4)) AND NOT(zerogroupff(5)) AND NOT(zerogroupff(6)) AND
NOT(zerogroupff(7)) AND NOT(zerogroupff(8)) AND NOT(zerogroupff(9)) AND
NOT(zerogroupff(10)) AND zerogroupff(11);
gma: FOR k IN 1 TO 6 GENERATE
positionmux(1)(k) <= positionff(1)(k) AND firstzero(1);
gmb: FOR j IN 2 TO 11 GENERATE
positionmux(j)(k) <= positionmux(j-1)(k) OR (positionff(j)(k) AND firstzero(j));
END GENERATE;
END GENERATE;
leading <= positionmux(11)(6 DOWNTO 1);
END rtl;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
Gray_Processing/ip/Gray_Processing/hcc_rsftcomb64.vhd
|
10
|
4574
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTCOMB64.VHD ***
--*** ***
--*** Function: Combinatorial arithmetic right ***
--*** shift for a 64 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftcomb64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_rsftcomb64;
ARCHITECTURE rtl OF hcc_rsftcomb64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 61 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(62) <= (levzip(62) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(63) AND NOT(shift(2)) AND shift(1)) OR
(levzip(64) AND shift(2));
levone(63) <= (levzip(63) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(64) AND ((shift(2)) OR shift(1)));
levone(64) <= levzip(64);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 52 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 53 TO 56 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(64) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 57 TO 60 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(64) AND shift(4));
END GENERATE;
gbd: FOR k IN 61 TO 63 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(64) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(64) <= levone(64);
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(k+48) AND shift(6) AND shift(5));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(64) AND shift(6) AND shift(5));
END GENERATE;
gcc: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(64) AND shift(6) );
END GENERATE;
gcd: FOR k IN 49 TO 63 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(64) AND (shift(6) OR shift(5)));
END GENERATE;
levthr(64) <= levtwo(64);
outbus <= levthr;
END rtl;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
Gray_Processing/ip/Gray_Processing/fp_range_table1.vhd
|
10
|
66434
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_RANGE_TABLE1.VHD ***
--*** ***
--*** Function: Single Precision Range Reduction***
--*** Component ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_range_table1 IS
PORT (
address : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
basefraction : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
incmantissa : OUT STD_LOGIC_VECTOR (56 DOWNTO 1);
incexponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_range_table1;
ARCHITECTURE rtl OF fp_range_table1 IS
BEGIN
pca: PROCESS (address)
BEGIN
CASE address IS
WHEN "01101110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(83443,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(42,8);
WHEN "01101111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(166886,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(41,8);
WHEN "01110000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(333772,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(40,8);
WHEN "01110001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(667544,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(39,8);
WHEN "01110010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(1335088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(38,8);
WHEN "01110011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(2670177,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(37,8);
WHEN "01110100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(5340354,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(36,8);
WHEN "01110101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(10680707,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(35,8);
WHEN "01110110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(21361415,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(34,8);
WHEN "01110111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(42722830,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(33,8);
WHEN "01111000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(85445659,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(32,8);
WHEN "01111001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(170891319,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(31,8);
WHEN "01111010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(1,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(73347182,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(30,8);
WHEN "01111011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(2,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(146694364,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(29,8);
WHEN "01111100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(5,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(24953271,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(28,8);
WHEN "01111101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(10,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(49906542,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(27,8);
WHEN "01111110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(20,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(99813085,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(26,8);
WHEN "01111111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(40,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(199626169,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(25,8);
WHEN "10000000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(81,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(130816882,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891319,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(14297640,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(24,8);
WHEN "10000001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(162,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(261633765,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(23,8);
WHEN "10000010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(69,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(254832074,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(22,8);
WHEN "10000011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(139,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(241228692,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(21,8);
WHEN "10000100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(23,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(214021927,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(20,8);
WHEN "10000101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(47,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(159608398,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(241345352,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(19,8);
WHEN "10000110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(95,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(50781341,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(18,8);
WHEN "10000111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(190,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(101562681,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(237340088,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(17,8);
WHEN "10001000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(124,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(203125362,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(16,8);
WHEN "10001001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(249,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(137815268,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(15,8);
WHEN "10001010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(243,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(7195081,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(14,8);
WHEN "10001011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(230,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(14390161,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(13,8);
WHEN "10001100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(204,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(28780322,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(12,8);
WHEN "10001101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(152,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(57560644,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(11,8);
WHEN "10001110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(48,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(115121288,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(10,8);
WHEN "10001111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(96,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(230242576,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(9,8);
WHEN "10010000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(193,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(192049697,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240015480,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(8,8);
WHEN "10010001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(131,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(115663937,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(7,8);
WHEN "10010010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(6,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(231327875,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(6,8);
WHEN "10010011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(13,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(194220293,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(5,8);
WHEN "10010100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(27,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(120005131,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "10010101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(54,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(240010261,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "10010110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(109,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(211585066,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10010111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(219,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(154734677,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10011000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(183,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(41033897,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(170891318,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(240010256,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10011001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(110,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(82067795,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(146694363,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(154734672,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10011010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(220,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(164135589,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(146694363,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(154734680,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10011011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(185,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(59835722,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835760,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "10011100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(114,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(119671445,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835712,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10011101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(228,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(239342890,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835736,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10011110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(201,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(210250324,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199626169,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(59835728,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10011111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(147,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(152065192,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(261633764,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(239342888,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10100000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(39,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(35694928,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(261633764,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(239342888,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(78,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(71389856,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(254832073,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(210250312,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(156,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(142779712,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(241228691,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(152065192,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(57,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(17123967,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(214021927,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(35694928,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(114,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(34247934,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(159608398,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(71389856,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10100101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(228,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(68495868,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203125362,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(34247944,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10100110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(200,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(136991736,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203125362,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(34247920,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10100111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(145,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(5548017,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203125362,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(34247944,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10101000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(34,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(11096033,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(137815268,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(68495872,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10101001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(68,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(22192066,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768104,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(5,8);
WHEN "10101010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(136,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(44384133,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768184,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "10101011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(16,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(88768266,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768288,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "10101100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(32,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(177536532,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10101101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(65,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(86637607,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768248,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10101110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(130,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(173275215,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(230242576,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88768264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10101111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(5,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(78114973,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(192049696,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(177536536,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(10,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(156229947,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(231327874,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(173275224,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10110001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(21,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(44024437,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(231327874,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(173275224,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(42,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(88048875,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(194220293,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(78114968,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(84,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(176097750,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(240010261,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(44024424,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10110100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(169,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(83760044,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(240010261,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(44024440,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(82,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(167520088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(211585066,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(88048872,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(165,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(66604720,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(154734676,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(176097752,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10110111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(74,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(133209439,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(164135589,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(66604720,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10111000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(148,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(266418879,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(164135589,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(66604728,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10111001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(41,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(264402301,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(164135589,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(66604728,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(83,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(260369146,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(239342889,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(264402312,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "10111011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(167,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(252302836,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(239342889,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(264402288,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "10111100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(79,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(236170217,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(239342889,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(264402296,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(159,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(203904978,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(210250323,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(260369144,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(63,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(139374500,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(152065191,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(252302864,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "10111111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(127,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(10313544,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(142779711,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(139374496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11000000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(254,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(20627088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(142779711,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(139374496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11000001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(252,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(41254175,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(142779711,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(139374496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11000010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(248,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(82508351,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508384,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11000011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(240,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(165016701,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508344,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11000100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(225,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(61597947,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508368,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11000101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(194,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(123195893,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(136991736,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(82508360,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11000110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(132,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(246391786,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260912,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(5,8);
WHEN "11000111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(9,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(224348117,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "11001000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(19,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(180260778,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11001001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(39,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(92086099,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11001010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(78,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(184172199,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11001011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(157,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(99908941,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177536531,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(180260776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11001100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(58,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(199817882,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(173275214,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(184172200,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11001101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(117,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(131200309,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(173275214,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(184172200,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11001110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(234,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(262400618,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(156229946,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(199817896,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11001111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(213,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(256365779,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(156229946,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(199817880,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11010000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(171,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(244296103,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(176097749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(256365776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11010001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(87,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(220156750,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(176097749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(256365792,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11010010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(175,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(171878044,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(176097749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(256365776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11010011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(95,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(75320631,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(167520087,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(220156768,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11010100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(190,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(150641263,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(167520087,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(220156760,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11010101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(125,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(32847070,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(266418878,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(150641264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11010110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(250,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(65694140,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(266418878,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(150641280,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11010111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(244,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(131388279,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(266418878,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(150641264,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(232,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(262776558,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(264402301,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(32847064,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(209,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(257117660,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(260369146,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(65694136,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(163,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(245799864,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(252302836,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(131388288,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(71,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(223164272,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(236170216,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(262776560,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(143,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(177893088,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(203904977,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(257117656,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(31,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(87350721,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(139374499,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(245799872,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11011110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(62,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(174701442,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967568,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(4,8);
WHEN "11011111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(125,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(80967427,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967448,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11100000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(250,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(161934855,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967448,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11100001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(245,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(55434254,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967448,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11100010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(234,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(110868507,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(165016701,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(80967424,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11100011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(212,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(221737015,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(246391786,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(110868472,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11100100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(169,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(175038574,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(246391786,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(110868512,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11100101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(83,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(81641691,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(246391786,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(110868528,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11100110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(166,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(163283383,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(224348116,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(221737016,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11100111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(77,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(58131310,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(180260777,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(175038576,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(154,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(116262619,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(184172198,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(163283376,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11101001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(52,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(232525238,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(184172198,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(163283384,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(105,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(196615020,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199817882,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(116262632,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11101011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(211,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(124794585,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(199817882,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(116262624,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(166,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(249589169,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262400617,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(196615040,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11101101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(77,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(230742883,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262400617,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(196615016,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(155,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(193050309,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(256365779,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(124794584,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11101111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(55,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(117665162,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(244296102,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(249589176,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(110,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(235330325,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(220156749,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(230742864,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(221,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(202225193,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(171878043,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(193050312,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(187,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(136014931,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(150641262,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(235330336,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11110011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(119,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(3594405,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(150641262,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(235330328,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11110100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(238,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(7188811,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188776,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(3,8);
WHEN "11110101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(220,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(14377622,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188816,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(2,8);
WHEN "11110110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(184,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(28755243,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188816,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11110111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(112,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(57510486,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(262776558,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(7188816,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111000" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(224,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(115020973,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(257117660,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(14377624,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111001" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(192,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(230041946,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(245799864,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(28755224,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111010" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(129,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(191648435,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(223164272,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(57510496,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111011" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(3,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(114861414,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(177893088,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(115020976,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111100" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(6,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(229722829,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(174701441,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(191648432,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11111101" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(13,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(191010201,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(174701441,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(191648440,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN "11111110" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(27,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(113584946,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(161934854,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(229722832,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(1,8);
WHEN "11111111" => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(54,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(227169893,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(161934854,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(229722824,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
WHEN others => basefraction(36 DOWNTO 29) <= conv_std_logic_vector(0,8);
basefraction(28 DOWNTO 1) <= conv_std_logic_vector(0,28);
incmantissa(56 DOWNTO 29) <= conv_std_logic_vector(0,28);
incmantissa(28 DOWNTO 1) <= conv_std_logic_vector(0,28);
incexponent(8 DOWNTO 1) <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
bin_Gray_Processing/ip/Gray_Processing/hcc_castdtol.vhd
|
10
|
3430
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTDTOL.VHD ***
--*** ***
--*** Function: Cast IEEE754 Double Format to ***
--*** Long ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castdtol IS
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
normspeed : positive := 2
); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castdtol;
ARCHITECTURE rtl OF hcc_castdtol IS
signal yvector : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal yvectorsat, yvectorzip : STD_LOGIC;
component hcc_castdtoy
GENERIC (
target : integer := 0; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castytol
GENERIC (normspeed : positive := 2); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aazip, aasat : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
BEGIN
corein: hcc_castdtoy
GENERIC MAP (target=>1,roundconvert=>roundconvert,outputpipe=>1,
doublespeed=>doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>yvector,ccsat=>yvectorsat,cczip=>yvectorzip);
coreout: hcc_castytol
GENERIC MAP (normspeed=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>yvector,aasat=>yvectorsat,aazip=>yvectorzip,
cc=>cc);
END rtl;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
bin_Gray_Processing/ip/Gray_Processing/fp_sincos_s5.vhd
|
10
|
671358
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_sincos_s5
-- VHDL created on Wed Mar 27 09:55:14 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_sincos_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
s : out std_logic_vector(31 downto 0);
c : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_sincos_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid6_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid7_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid8_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBias_uid22_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid23_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShift_uid24_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid25_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid26_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstZwShiftP1_uid27_fpSinCosXTest_q : std_logic_vector (13 downto 0);
signal cstNaNwF_uid32_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal cstZmwFRRPwSM1_uid52_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal cPi_uid71_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal p_uid73_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal p_uid73_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal expPSin_uid76_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal expPSin_uid76_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal multSinOp2_uid91_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal multSinOp2_uid91_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal mulSin_uid92_fpSinCosXTest_a : std_logic_vector (25 downto 0);
signal mulSin_uid92_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal mulSin_uid92_fpSinCosXTest_s1 : std_logic_vector (51 downto 0);
signal mulSin_uid92_fpSinCosXTest_pr : UNSIGNED (51 downto 0);
signal mulSin_uid92_fpSinCosXTest_q : std_logic_vector (51 downto 0);
signal mulCos_uid105_fpSinCosXTest_a : std_logic_vector (25 downto 0);
signal mulCos_uid105_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal mulCos_uid105_fpSinCosXTest_s1 : std_logic_vector (51 downto 0);
signal mulCos_uid105_fpSinCosXTest_pr : UNSIGNED (51 downto 0);
signal mulCos_uid105_fpSinCosXTest_q : std_logic_vector (51 downto 0);
signal excSelSin_uid119_fpSinCosXTest_q : std_logic_vector(1 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal expSelectorCos_uid145_fpSinCosXTest_q : std_logic_vector(1 downto 0);
signal signRCond2_uid152_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_d : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_d : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal ZerosGB_uid206_rrx_uid34_fpSinCosXTest_q : std_logic_vector (29 downto 0);
signal leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (2 downto 0);
signal zs_uid236_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(63 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(63 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal mO_uid239_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (62 downto 0);
signal zs_uid244_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal zs_uid250_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (5 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(63 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(63 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (47 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a : std_logic_vector (12 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b : std_logic_vector (12 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_pr : SIGNED (26 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q : std_logic_vector (25 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a : std_logic_vector (14 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b : std_logic_vector (22 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1 : std_logic_vector (37 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_pr : SIGNED (38 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q : std_logic_vector (37 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a : std_logic_vector (12 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b : std_logic_vector (12 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_pr : SIGNED (26 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q : std_logic_vector (25 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a : std_logic_vector (14 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b : std_logic_vector (22 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1 : std_logic_vector (37 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_pr : SIGNED (38 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q : std_logic_vector (37 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_reset0 : std_logic;
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ia : std_logic_vector (39 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_iq : std_logic_vector (39 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_q : std_logic_vector (39 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_reset0 : std_logic;
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ia : std_logic_vector (39 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_iq : std_logic_vector (39 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_q : std_logic_vector (39 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_a : std_logic_vector(81 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_b : std_logic_vector(81 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o : std_logic_vector (81 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_q : std_logic_vector (81 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_reset0 : std_logic;
signal memoryC0_uid394_tableGensinPiZ_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_reset0 : std_logic;
signal memoryC1_uid396_tableGensinPiZ_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_reset0 : std_logic;
signal memoryC2_uid398_tableGensinPiZ_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_q : std_logic_vector (12 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_reset0 : std_logic;
signal memoryC0_uid400_tableGencosPiZ_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_reset0 : std_logic;
signal memoryC1_uid402_tableGencosPiZ_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_reset0 : std_logic;
signal memoryC2_uid404_tableGencosPiZ_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_q : std_logic_vector (12 downto 0);
signal reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q : std_logic_vector (2 downto 0);
signal reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q : std_logic_vector (39 downto 0);
signal reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (39 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q : std_logic_vector (26 downto 0);
signal reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (77 downto 0);
signal reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q : std_logic_vector (67 downto 0);
signal reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q : std_logic_vector (66 downto 0);
signal reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q : std_logic_vector (65 downto 0);
signal reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q : std_logic_vector (67 downto 0);
signal reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q : std_logic_vector (64 downto 0);
signal reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q : std_logic_vector (25 downto 0);
signal reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q : std_logic_vector (12 downto 0);
signal reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q : std_logic_vector (20 downto 0);
signal reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q : std_logic_vector (22 downto 0);
signal reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q : std_logic_vector (29 downto 0);
signal reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q : std_logic_vector (6 downto 0);
signal reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q : std_logic_vector (22 downto 0);
signal reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q : std_logic_vector (0 downto 0);
signal reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q : std_logic_vector (12 downto 0);
signal reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q : std_logic_vector (20 downto 0);
signal reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q : std_logic_vector (22 downto 0);
signal reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q : std_logic_vector (29 downto 0);
signal reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q : std_logic_vector (25 downto 0);
signal reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q : std_logic_vector (25 downto 0);
signal reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q : std_logic_vector (6 downto 0);
signal reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q : std_logic_vector (22 downto 0);
signal reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q : std_logic_vector (3 downto 0);
signal reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q : std_logic_vector (0 downto 0);
signal ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a_q : std_logic_vector (52 downto 0);
signal ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q : std_logic_vector (65 downto 0);
signal ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a_q : std_logic_vector (67 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (7 downto 0);
signal ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b_q : std_logic_vector (66 downto 0);
signal ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b_q : std_logic_vector (65 downto 0);
signal ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b_q : std_logic_vector (64 downto 0);
signal ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q : std_logic_vector (63 downto 0);
signal ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q : std_logic_vector (31 downto 0);
signal ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (62 downto 0);
signal ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (60 downto 0);
signal ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (58 downto 0);
signal ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q : std_logic_vector (63 downto 0);
signal ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q : std_logic_vector (31 downto 0);
signal ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (62 downto 0);
signal ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (60 downto 0);
signal ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (58 downto 0);
signal ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (76 downto 0);
signal ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (75 downto 0);
signal ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (74 downto 0);
signal ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_q : std_logic_vector (12 downto 0);
signal ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a_q : std_logic_vector (53 downto 0);
signal ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_q : std_logic_vector (12 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg_q : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg_q : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_reset0 : std_logic;
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q : signal is true;
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg_q : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top_q : std_logic_vector (6 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg_q : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_reset0 : std_logic;
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q : signal is true;
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg_q : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_reset0 : std_logic;
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ia : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_iq : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q : signal is true;
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg_q : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_reset0 : std_logic;
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ia : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_iq : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q : signal is true;
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg_q : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_reset0 : std_logic;
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ia : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_iq : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q : signal is true;
signal ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q : signal is true;
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_reset0 : std_logic;
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q : signal is true;
signal ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_reset0 : std_logic;
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_reset0 : std_logic;
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq : std_logic;
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q : signal is true;
signal sinXIsXRR_uid41_fpSinCosXTest_a : std_logic_vector(11 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_b : std_logic_vector(11 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_o : std_logic_vector (11 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_a : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_b : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_o : std_logic_vector (11 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal yIsZero_uid51_fpSinCosXTest_a : std_logic_vector(65 downto 0);
signal yIsZero_uid51_fpSinCosXTest_b : std_logic_vector(65 downto 0);
signal yIsZero_uid51_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal pad_one_uid55_fpSinCosXTest_q : std_logic_vector (66 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_a : std_logic_vector(70 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_b : std_logic_vector(70 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_o : std_logic_vector (70 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_c : std_logic_vector (0 downto 0);
signal leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal InvCmpYToOneMinusY_uid61_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvCmpYToOneMinusY_uid61_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid127_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid127_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvSinXIsXRR_uid128_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsXRR_uid128_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid131_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid131_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid132_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid132_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvCosXIsOneXRR_uid136_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOneXRR_uid136_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvCosXONe_uid149_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvCosXONe_uid149_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvYIsZero_uid151_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvYIsZero_uid151_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvIntXParity_uid155_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvIntXParity_uid155_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal oFracXRR_uid43_uid43_fpSinCosXTest_q : std_logic_vector (53 downto 0);
signal half_uid53_fpSinCosXTest_q : std_logic_vector (65 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal exp_uid9_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal exp_uid9_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal frac_uid13_fpSinCosXTest_in : std_logic_vector (22 downto 0);
signal frac_uid13_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal signX_uid37_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal signX_uid37_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal expFracX_uid166_px_uid33_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal expFracX_uid166_px_uid33_fpSinCosXTest_b : std_logic_vector (30 downto 0);
signal expXIsZero_uid10_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid10_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid10_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid12_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid14_fpSinCosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpSinCosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_a : std_logic_vector(10 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_b : std_logic_vector(10 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_o : std_logic_vector (10 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_a : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_b : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_o : std_logic_vector (10 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_q : std_logic_vector (9 downto 0);
signal yIsHalf_uid54_fpSinCosXTest_a : std_logic_vector(65 downto 0);
signal yIsHalf_uid54_fpSinCosXTest_b : std_logic_vector(65 downto 0);
signal yIsHalf_uid54_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_a : std_logic_vector(67 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_b : std_logic_vector(67 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_o : std_logic_vector (67 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal zSin_uid60_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal zSin_uid60_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal zCos_uid64_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal zCos_uid64_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal expSinHC_uid74_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expSinHC_uid74_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expSinHC_uid74_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expSinHC_uid74_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal excRNaN_uid117_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid117_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid117_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fracRPostExcSin_uid122_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExcSin_uid122_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal expRPostExcSin_uid126_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExcSin_uid126_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fracRPostExcCos_uid142_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExcCos_uid142_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal expRPostExcCos_uid147_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExcCos_uid147_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cosXONe_uid148_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal cosXONe_uid148_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal cosXONe_uid148_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal signRCos_uid158_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCos_uid158_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCos_uid158_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal finalExp_uid209_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal finalExp_uid209_rrx_uid34_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid258_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid258_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid337_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid337_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal extendedFracX_uid47_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal normBitSin_uid93_fpSinCosXTest_in : std_logic_vector (51 downto 0);
signal normBitSin_uid93_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal fracRSinPreRndHigh_uid95_fpSinCosXTest_in : std_logic_vector (50 downto 0);
signal fracRSinPreRndHigh_uid95_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal fracRSinPreRndLow_uid96_fpSinCosXTest_in : std_logic_vector (49 downto 0);
signal fracRSinPreRndLow_uid96_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal normBitCos_uid106_fpSinCosXTest_in : std_logic_vector (51 downto 0);
signal normBitCos_uid106_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal fracRCosPreRndHigh_uid108_fpSinCosXTest_in : std_logic_vector (50 downto 0);
signal fracRCosPreRndHigh_uid108_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal fracRCosPreRndLow_uid109_fpSinCosXTest_in : std_logic_vector (49 downto 0);
signal fracRCosPreRndLow_uid109_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q : std_logic_vector (52 downto 0);
signal leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_in : std_logic_vector (37 downto 0);
signal prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_in : std_logic_vector (37 downto 0);
signal prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b : std_logic_vector (23 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q_int : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q_int : std_logic_vector (80 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q : std_logic_vector (80 downto 0);
signal os_uid196_rrx_uid34_fpSinCosXTest_q : std_logic_vector (79 downto 0);
signal leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal join_uid99_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal join_uid141_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal zSinYBottom_uid59_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal zSinYBottom_uid59_fpSinCosXTest_b : std_logic_vector (64 downto 0);
signal zSinOMyBottom_uid58_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal zSinOMyBottom_uid58_fpSinCosXTest_b : std_logic_vector (64 downto 0);
signal excSelBitsSin_uid118_fpSinCosXTest_q : std_logic_vector (2 downto 0);
signal fpSin_uid134_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal join_uid143_fpSinCosXTest_q : std_logic_vector (2 downto 0);
signal fpCos_uid162_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q_int : std_logic_vector (107 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q : std_logic_vector (107 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_a : std_logic_vector(6 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_b : std_logic_vector(6 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal fracX_uid187_rrx_uid34_fpSinCosXTest_in : std_logic_vector (22 downto 0);
signal fracX_uid187_rrx_uid34_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_q : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal oFracXRRSmallXRR_uid90_fpSinCosXTest_in : std_logic_vector (53 downto 0);
signal oFracXRRSmallXRR_uid90_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal R_uid167_px_uid33_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal InvFracXIsZero_uid16_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid16_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fxpXShiftVal_uid46_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal fxpXShiftVal_uid46_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal addr_uid81_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal addr_uid81_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal zPsinPiZ_uid84_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal zPsinPiZ_uid84_fpSinCosXTest_b : std_logic_vector (14 downto 0);
signal rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal vStage_uid240_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (32 downto 0);
signal addr_uid83_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal addr_uid83_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal zPcosPiZ_uid87_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal zPcosPiZ_uid87_fpSinCosXTest_b : std_logic_vector (14 downto 0);
signal rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal vStage_uid319_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (32 downto 0);
signal expSinHCR_uid75_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expSinHCR_uid75_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal expPCos_uid79_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expPCos_uid79_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (66 downto 0);
signal LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (66 downto 0);
signal LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (65 downto 0);
signal LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (65 downto 0);
signal LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (64 downto 0);
signal rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid253_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid265_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal vStage_uid265_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid271_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (60 downto 0);
signal LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (60 downto 0);
signal LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (58 downto 0);
signal LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (58 downto 0);
signal rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid332_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid344_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal vStage_uid344_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid350_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (60 downto 0);
signal LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (60 downto 0);
signal LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (58 downto 0);
signal LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (58 downto 0);
signal rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (76 downto 0);
signal LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (76 downto 0);
signal LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (75 downto 0);
signal LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (75 downto 0);
signal LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (74 downto 0);
signal LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (74 downto 0);
signal X63dto0_uid214_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal X63dto0_uid214_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal X59dto0_uid217_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (59 downto 0);
signal X59dto0_uid217_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (59 downto 0);
signal X55dto0_uid220_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (55 downto 0);
signal X55dto0_uid220_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (55 downto 0);
signal fracRSinPreRnd_uid97_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal fracRSinPreRnd_uid97_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal fracRCosPreRnd_uid110_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal fracRCosPreRnd_uid110_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal cosRndOp_uid112_uid113_fpSinCosXTest_q : std_logic_vector (24 downto 0);
signal rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal vStage_uid326_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal lowRangeB_uid408_polyEvalsinPiZ_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid408_polyEvalsinPiZ_b : std_logic_vector (0 downto 0);
signal highBBits_uid409_polyEvalsinPiZ_in : std_logic_vector (13 downto 0);
signal highBBits_uid409_polyEvalsinPiZ_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid414_polyEvalsinPiZ_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid414_polyEvalsinPiZ_b : std_logic_vector (1 downto 0);
signal highBBits_uid415_polyEvalsinPiZ_in : std_logic_vector (23 downto 0);
signal highBBits_uid415_polyEvalsinPiZ_b : std_logic_vector (21 downto 0);
signal lowRangeB_uid421_polyEvalcosPiZ_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid421_polyEvalcosPiZ_b : std_logic_vector (0 downto 0);
signal highBBits_uid422_polyEvalcosPiZ_in : std_logic_vector (13 downto 0);
signal highBBits_uid422_polyEvalcosPiZ_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid427_polyEvalcosPiZ_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid427_polyEvalcosPiZ_b : std_logic_vector (1 downto 0);
signal highBBits_uid428_polyEvalcosPiZ_in : std_logic_vector (23 downto 0);
signal highBBits_uid428_polyEvalcosPiZ_b : std_logic_vector (21 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_0_in : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_1_in : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_1_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_2_in : std_logic_vector (80 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_2_b : std_logic_vector (26 downto 0);
signal fracCompOut_uid203_rrx_uid34_fpSinCosXTest_in : std_logic_vector (76 downto 0);
signal fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b : std_logic_vector (52 downto 0);
signal intXParity_uid49_fpSinCosXTest_in : std_logic_vector (67 downto 0);
signal intXParity_uid49_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal y_uid50_fpSinCosXTest_in : std_logic_vector (66 downto 0);
signal y_uid50_fpSinCosXTest_b : std_logic_vector (65 downto 0);
signal LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal sinRndOp_uid100_uid101_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal expSelBitsCos_uid144_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal vStage_uid247_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_a : std_logic_vector(108 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_b : std_logic_vector(108 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_o : std_logic_vector (108 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_q : std_logic_vector (108 downto 0);
signal oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal expX_uid186_rrx_uid34_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal expX_uid186_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal exc_N_uid17_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal yT1_uid406_polyEvalsinPiZ_in : std_logic_vector (14 downto 0);
signal yT1_uid406_polyEvalsinPiZ_b : std_logic_vector (12 downto 0);
signal yT1_uid419_polyEvalcosPiZ_in : std_logic_vector (14 downto 0);
signal yT1_uid419_polyEvalcosPiZ_b : std_logic_vector (12 downto 0);
signal vCount_uid252_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid252_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vCount_uid270_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid270_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal vCount_uid331_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid331_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vCount_uid349_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid349_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_a : std_logic_vector(32 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_b : std_logic_vector(32 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_o : std_logic_vector (32 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_q : std_logic_vector (32 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_q : std_logic_vector (30 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_q : std_logic_vector (30 downto 0);
signal finalFrac_uid208_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal finalFrac_uid208_rrx_uid34_fpSinCosXTest_q : std_logic_vector (52 downto 0);
signal signComp_uid129_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signComp_uid129_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signComp_uid129_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signComp_uid129_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_a : std_logic_vector(32 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_b : std_logic_vector(32 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_o : std_logic_vector (32 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_q : std_logic_vector (32 downto 0);
signal leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal multFracBits_uid199_rrx_uid34_fpSinCosXTest_in : std_logic_vector (77 downto 0);
signal multFracBits_uid199_rrx_uid34_fpSinCosXTest_b : std_logic_vector (77 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_b_0_in : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_b_0_b : std_logic_vector (26 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_a : std_logic_vector(10 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_b : std_logic_vector(10 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_o : std_logic_vector (10 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid259_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal vStage_uid259_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid338_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal vStage_uid338_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (5 downto 0);
signal fracRCompCos_uid115_fpSinCosXTest_in : std_logic_vector (23 downto 0);
signal fracRCompCos_uid115_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal expRCompSin_uid116_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal expRCompSin_uid116_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal s1_uid408_uid411_polyEvalsinPiZ_q : std_logic_vector (22 downto 0);
signal s2_uid414_uid417_polyEvalsinPiZ_q : std_logic_vector (32 downto 0);
signal s1_uid421_uid424_polyEvalcosPiZ_q : std_logic_vector (22 downto 0);
signal s2_uid427_uid430_polyEvalcosPiZ_q : std_logic_vector (32 downto 0);
signal RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q : std_logic_vector (61 downto 0);
signal signR_uid130_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signR_uid130_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signR_uid130_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal fracRCompSin_uid103_fpSinCosXTest_in : std_logic_vector (23 downto 0);
signal fracRCompSin_uid103_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal expRCompSin_uid104_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal expRCompSin_uid104_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_in : std_logic_vector (77 downto 0);
signal multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (61 downto 0);
signal X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (61 downto 0);
signal X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (45 downto 0);
signal X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (45 downto 0);
signal X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (29 downto 0);
signal X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (29 downto 0);
signal expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vCount_uid276_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid276_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid276_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid355_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid355_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid355_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal polyEvalSigsinPiZ_uid86_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal polyEvalSigsinPiZ_uid86_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal polyEvalSigcosPiZ_uid89_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal polyEvalSigcosPiZ_uid89_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal expXRR_uid38_fpSinCosXTest_in : std_logic_vector (60 downto 0);
signal expXRR_uid38_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal fracXRR_uid39_fpSinCosXTest_in : std_logic_vector (52 downto 0);
signal fracXRR_uid39_fpSinCosXTest_b : std_logic_vector (52 downto 0);
signal pHigh_uid72_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal pHigh_uid72_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal pCos_uid77_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal pCos_uid77_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal r_uid277_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (6 downto 0);
signal r_uid356_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (6 downto 0);
signal expCompOut_uid205_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expCompOut_uid205_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (73 downto 0);
signal LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (73 downto 0);
signal LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (69 downto 0);
signal LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (69 downto 0);
signal LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (65 downto 0);
signal LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (65 downto 0);
signal leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (56 downto 0);
signal LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (48 downto 0);
signal LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (48 downto 0);
signal LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (40 downto 0);
signal LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (40 downto 0);
signal LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (56 downto 0);
signal LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (48 downto 0);
signal LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (48 downto 0);
signal LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (40 downto 0);
signal LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (40 downto 0);
signal leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
begin
--xIn(GPIN,3)@0
--GND(CONSTANT,0)
GND_q <= "0";
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable(LOGICAL,1282)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_a <= en;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q <= not ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_a;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor(LOGICAL,1422)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_b <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_q <= not (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_a or ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_b);
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top(CONSTANT,1418)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top_q <= "01011";
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp(LOGICAL,1419)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_a <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q);
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_q <= "1" when ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_a = ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_b else "0";
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg(REG,1420)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena(REG,1423)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_q = "1") THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd(LOGICAL,1424)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_a <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_b <= en;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_a and ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_b;
--expFracX_uid166_px_uid33_fpSinCosXTest(BITSELECT,165)@0
expFracX_uid166_px_uid33_fpSinCosXTest_in <= a(30 downto 0);
expFracX_uid166_px_uid33_fpSinCosXTest_b <= expFracX_uid166_px_uid33_fpSinCosXTest_in(30 downto 0);
--R_uid167_px_uid33_fpSinCosXTest(BITJOIN,166)@0
R_uid167_px_uid33_fpSinCosXTest_q <= GND_q & expFracX_uid166_px_uid33_fpSinCosXTest_b;
--expX_uid186_rrx_uid34_fpSinCosXTest(BITSELECT,185)@0
expX_uid186_rrx_uid34_fpSinCosXTest_in <= R_uid167_px_uid33_fpSinCosXTest_q(30 downto 0);
expX_uid186_rrx_uid34_fpSinCosXTest_b <= expX_uid186_rrx_uid34_fpSinCosXTest_in(30 downto 23);
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg(DELAY,1412)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid186_rrx_uid34_fpSinCosXTest_b, xout => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt(COUNTER,1414)
-- every=1, low=0, high=11, step=1, init=1
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i = 10 THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i - 11;
ELSE
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i,4));
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg(REG,1415)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux(MUX,1416)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s, ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q, ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem(DUALMEM,1413)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ia <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_aa <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ab <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 12,
width_b => 8,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ia
);
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_iq(7 downto 0);
--zs_uid244_lzcZSin_uid66_fpSinCosXTest(CONSTANT,243)
zs_uid244_lzcZSin_uid66_fpSinCosXTest_q <= "00000000000000000000000000000000";
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor(LOGICAL,1396)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_b <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_q <= not (ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_a or ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_b);
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg(REG,1318)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena(REG,1397)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_q = "1") THEN
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd(LOGICAL,1398)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_a <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_b <= en;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_q <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_a and ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_b;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg(DELAY,1388)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => R_uid167_px_uid33_fpSinCosXTest_q, xout => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt(COUNTER,1314)
-- every=1, low=0, high=1, step=1, init=1
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i,1));
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg(REG,1315)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux(MUX,1316)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s <= en;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux: PROCESS (ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s, ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q, ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q)
BEGIN
CASE ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s IS
WHEN "0" => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
WHEN "1" => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem(DUALMEM,1389)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ia <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 1,
numwords_a => 2,
width_b => 32,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_iq,
address_a => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_aa,
data_a => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ia
);
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_reset0 <= areset;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_q <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_iq(31 downto 0);
--fracX_uid187_rrx_uid34_fpSinCosXTest(BITSELECT,186)@4
fracX_uid187_rrx_uid34_fpSinCosXTest_in <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_q(22 downto 0);
fracX_uid187_rrx_uid34_fpSinCosXTest_b <= fracX_uid187_rrx_uid34_fpSinCosXTest_in(22 downto 0);
--oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest(BITJOIN,196)@4
oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest_q <= VCC_q & fracX_uid187_rrx_uid34_fpSinCosXTest_b;
--prod_uid198_rrx_uid34_fpSinCosXTest_b_0(BITSELECT,518)@4
prod_uid198_rrx_uid34_fpSinCosXTest_b_0_in <= STD_LOGIC_VECTOR("000" & oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest_q);
prod_uid198_rrx_uid34_fpSinCosXTest_b_0_b <= prod_uid198_rrx_uid34_fpSinCosXTest_b_0_in(26 downto 0);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1(REG,539)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q <= prod_uid198_rrx_uid34_fpSinCosXTest_b_0_b;
END IF;
END IF;
END PROCESS;
--cstBiasMwShift_uid24_fpSinCosXTest(CONSTANT,23)
cstBiasMwShift_uid24_fpSinCosXTest_q <= "01110011";
--expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest(SUB,191)@0
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & expX_uid186_rrx_uid34_fpSinCosXTest_b);
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_b <= STD_LOGIC_VECTOR("0" & cstBiasMwShift_uid24_fpSinCosXTest_q);
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_a) - UNSIGNED(expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_b));
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_q <= expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_o(8 downto 0);
--expXTableAddr_uid193_rrx_uid34_fpSinCosXTest(BITSELECT,192)@0
expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_in <= expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_q(7 downto 0);
expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_b <= expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_in(7 downto 0);
--reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0(REG,534)@0
reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q <= expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem(DUALMEM,514)@1
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ia <= (others => '0');
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_aa <= (others => '0');
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ab <= reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q;
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 140,
width_b => 40,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_iq,
address_a => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_aa,
data_a => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ia
);
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_reset0 <= areset;
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_q <= rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_iq(39 downto 0);
--reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1(REG,537)@3
reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q <= rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem(DUALMEM,513)@1
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ia <= (others => '0');
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_aa <= (others => '0');
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ab <= reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q;
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 140,
width_b => 40,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_iq,
address_a => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_aa,
data_a => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ia
);
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_reset0 <= areset;
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_q <= rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_iq(39 downto 0);
--reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0(REG,536)@3
reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q <= rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid196_rrx_uid34_fpSinCosXTest(BITJOIN,195)@4
os_uid196_rrx_uid34_fpSinCosXTest_q <= reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q & reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q;
--prod_uid198_rrx_uid34_fpSinCosXTest_a_2(BITSELECT,517)@4
prod_uid198_rrx_uid34_fpSinCosXTest_a_2_in <= STD_LOGIC_VECTOR("0" & os_uid196_rrx_uid34_fpSinCosXTest_q);
prod_uid198_rrx_uid34_fpSinCosXTest_a_2_b <= prod_uid198_rrx_uid34_fpSinCosXTest_a_2_in(80 downto 54);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0(REG,542)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a_2_b;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0(MULT,521)@5
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_pr <= UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a) * UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b);
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1 <= STD_LOGIC_VECTOR(prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1;
END IF;
END IF;
END PROCESS;
--ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a(DELAY,1145)@8
ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a : dspba_delay
GENERIC MAP ( width => 54, depth => 1 )
PORT MAP ( xin => prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q, xout => ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--prod_uid198_rrx_uid34_fpSinCosXTest_align_2(BITSHIFT,524)@9
prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q_int <= ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q <= prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q_int(107 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_a_1(BITSELECT,516)@4
prod_uid198_rrx_uid34_fpSinCosXTest_a_1_in <= os_uid196_rrx_uid34_fpSinCosXTest_q(53 downto 0);
prod_uid198_rrx_uid34_fpSinCosXTest_a_1_b <= prod_uid198_rrx_uid34_fpSinCosXTest_a_1_in(53 downto 27);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0(REG,540)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a_1_b;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0(MULT,520)@5
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_pr <= UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a) * UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b);
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1 <= STD_LOGIC_VECTOR(prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_align_1(BITSHIFT,523)@8
prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q_int <= prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q & "000000000000000000000000000";
prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q <= prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q_int(80 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_a_0(BITSELECT,515)@4
prod_uid198_rrx_uid34_fpSinCosXTest_a_0_in <= os_uid196_rrx_uid34_fpSinCosXTest_q(26 downto 0);
prod_uid198_rrx_uid34_fpSinCosXTest_a_0_b <= prod_uid198_rrx_uid34_fpSinCosXTest_a_0_in(26 downto 0);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0(REG,538)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a_0_b;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0(MULT,519)@5
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_pr <= UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a) * UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b);
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1 <= STD_LOGIC_VECTOR(prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_align_0(BITSHIFT,522)@8
prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q_int <= prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q_int(53 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0(ADD,525)@8
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_a <= STD_LOGIC_VECTOR("0000000000000000000000000000" & prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_b <= STD_LOGIC_VECTOR("0" & prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_a) + UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_b));
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o(81 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0(ADD,526)@9
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_a <= STD_LOGIC_VECTOR("000000000000000000000000000" & prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_b <= STD_LOGIC_VECTOR("0" & prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_a) + UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_b));
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_o(108 downto 0);
--multFracBits_uid199_rrx_uid34_fpSinCosXTest(BITSELECT,198)@9
multFracBits_uid199_rrx_uid34_fpSinCosXTest_in <= prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_q(77 downto 0);
multFracBits_uid199_rrx_uid34_fpSinCosXTest_b <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_in(77 downto 0);
--multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest(BITSELECT,199)@9
multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b;
multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_b <= multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_in(77 downto 46);
--reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1(REG,544)@9
reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,433)@10
vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a(DELAY,1178)@10
ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xout => ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5(REG,555)@12
reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q <= ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a_q;
END IF;
END IF;
END PROCESS;
--zs_uid250_lzcZSin_uid66_fpSinCosXTest(CONSTANT,249)
zs_uid250_lzcZSin_uid66_fpSinCosXTest_q <= "0000000000000000";
--mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest(CONSTANT,434)
mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "11111111111111111111111111111111";
--vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,436)@10
vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q, mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,438)@10
rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_in(31 downto 16);
--reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1(REG,546)@10
reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,439)@11
vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4(REG,554)@11
reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q <= vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e(DELAY,1081)@12
ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q, xout => ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWE_uid8_fpSinCosXTest(CONSTANT,7)
cstAllZWE_uid8_fpSinCosXTest_q <= "00000000";
--vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,440)@10
vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q(15 downto 0);
vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_in(15 downto 0);
--reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3(REG,548)@10
reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,442)@11
vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q, reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,444)@11
rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_in(15 downto 8);
--vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,445)@11
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i <= "1" when vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xin => vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d(DELAY,1080)@12
ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xout => ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest(CONSTANT,212)
leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q <= "0000";
--vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,446)@11
vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q(7 downto 0);
vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_in(7 downto 0);
--reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3(REG,550)@11
reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2(REG,549)@11
reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,448)@12
vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q, reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,450)@12
rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_in(7 downto 4);
--vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,451)@12
vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2(REG,553)@12
reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest(CONSTANT,226)
leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q <= "00";
--vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,452)@12
vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q(3 downto 0);
vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_in(3 downto 0);
--vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,454)@12
vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b, vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
WHEN "1" => vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,456)@12
rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_in(3 downto 2);
--vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,457)@12
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i <= "1" when vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xin => vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,458)@12
vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q(1 downto 0);
vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_in(1 downto 0);
--reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3(REG,552)@12
reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2(REG,551)@12
reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,460)@13
vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q, reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,462)@13
rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_in(1 downto 1);
--vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,463)@13
vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= GND_q;
vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest(BITJOIN,464)@13
r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q & ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e_q & ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d_q & reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q & vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q & vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
--cstBiasM1_uid23_fpSinCosXTest(CONSTANT,22)
cstBiasM1_uid23_fpSinCosXTest_q <= "01111110";
--expCompOutExt_uid204_rrx_uid34_fpSinCosXTest(SUB,203)@13
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_fpSinCosXTest_q);
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_b <= STD_LOGIC_VECTOR("000" & r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q);
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_a) - UNSIGNED(expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_b));
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_q <= expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_o(8 downto 0);
--expCompOut_uid205_rrx_uid34_fpSinCosXTest(BITSELECT,204)@13
expCompOut_uid205_rrx_uid34_fpSinCosXTest_in <= expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_q(7 downto 0);
expCompOut_uid205_rrx_uid34_fpSinCosXTest_b <= expCompOut_uid205_rrx_uid34_fpSinCosXTest_in(7 downto 0);
--reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2(REG,564)@13
reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q <= expCompOut_uid205_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--xBranch_uid191_rrx_uid34_fpSinCosXTest(COMPARE,190)@0
xBranch_uid191_rrx_uid34_fpSinCosXTest_cin <= GND_q;
xBranch_uid191_rrx_uid34_fpSinCosXTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid24_fpSinCosXTest_q) & '0';
xBranch_uid191_rrx_uid34_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & expX_uid186_rrx_uid34_fpSinCosXTest_b) & xBranch_uid191_rrx_uid34_fpSinCosXTest_cin(0);
xBranch_uid191_rrx_uid34_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xBranch_uid191_rrx_uid34_fpSinCosXTest_a) - UNSIGNED(xBranch_uid191_rrx_uid34_fpSinCosXTest_b));
xBranch_uid191_rrx_uid34_fpSinCosXTest_n(0) <= not xBranch_uid191_rrx_uid34_fpSinCosXTest_o(10);
--reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1(REG,563)@0
reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q <= xBranch_uid191_rrx_uid34_fpSinCosXTest_n;
END IF;
END IF;
END PROCESS;
--ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b(DELAY,829)@1
ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q, xout => ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalExp_uid209_rrx_uid34_fpSinCosXTest(MUX,208)@14
finalExp_uid209_rrx_uid34_fpSinCosXTest_s <= ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b_q;
finalExp_uid209_rrx_uid34_fpSinCosXTest: PROCESS (finalExp_uid209_rrx_uid34_fpSinCosXTest_s, en, reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q, ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q)
BEGIN
CASE finalExp_uid209_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => finalExp_uid209_rrx_uid34_fpSinCosXTest_q <= reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q;
WHEN "1" => finalExp_uid209_rrx_uid34_fpSinCosXTest_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q;
WHEN OTHERS => finalExp_uid209_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b(DELAY,833)@14
ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => finalExp_uid209_rrx_uid34_fpSinCosXTest_q, xout => ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1409)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_a or ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top(CONSTANT,1279)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top_q <= "01000";
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp(LOGICAL,1280)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q);
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_q <= "1" when ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_a = ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_b else "0";
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg(REG,1281)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1410)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1411)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1399)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid187_rrx_uid34_fpSinCosXTest_b, xout => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt(COUNTER,1275)
-- every=1, low=0, high=8, step=1, init=1
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i = 7 THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i - 8;
ELSE
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i,4));
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg(REG,1276)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux(MUX,1277)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s, ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q, ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1400)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 4,
numwords_a => 9,
width_b => 23,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(22 downto 0);
--ZerosGB_uid206_rrx_uid34_fpSinCosXTest(CONSTANT,205)
ZerosGB_uid206_rrx_uid34_fpSinCosXTest_q <= "000000000000000000000000000000";
--fracXRExt_uid207_rrx_uid34_fpSinCosXTest(BITJOIN,206)@15
fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_q & ZerosGB_uid206_rrx_uid34_fpSinCosXTest_q;
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1499)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a or ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1500)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1501)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,474)@9
X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b(29 downto 0);
X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_in(29 downto 0);
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1491)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 30, depth => 1 )
PORT MAP ( xin => X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1492)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 1,
numwords_a => 2,
width_b => 30,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(29 downto 0);
--leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest(CONSTANT,473)
leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= "000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,475)@13
leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q & leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1488)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a or ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1489)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1490)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,471)@9
X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b(45 downto 0);
X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_in(45 downto 0);
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1480)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 46, depth => 1 )
PORT MAP ( xin => X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1481)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 1,
numwords_a => 2,
width_b => 46,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(45 downto 0);
--leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,472)@13
leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q & zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1477)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a or ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1478)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1479)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,468)@9
X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b(61 downto 0);
X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_in(61 downto 0);
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1469)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1470)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 62,
widthad_a => 1,
numwords_a => 2,
width_b => 62,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(61 downto 0);
--leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,469)@13
leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q & zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor(LOGICAL,1510)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_b <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_q <= not (ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_a or ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_b);
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena(REG,1511)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_q = "1") THEN
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd(LOGICAL,1512)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_a <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_b <= en;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_q <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_a and ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_b;
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg(DELAY,1502)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 78, depth => 1 )
PORT MAP ( xin => multFracBits_uid199_rrx_uid34_fpSinCosXTest_b, xout => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem(DUALMEM,1503)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ia <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 78,
widthad_a => 1,
numwords_a => 2,
width_b => 78,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_iq,
address_a => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_aa,
data_a => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ia
);
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_reset0 <= areset;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_iq(77 downto 0);
--leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,476)@13
leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_in(5 downto 4);
--leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest(MUX,477)@13
leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s <= leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_b;
leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest: PROCESS (leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s, en, ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q, leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "10" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "11" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,485)@13
LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q(65 downto 0);
LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_in(65 downto 0);
--leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest(CONSTANT,218)
leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q <= "000000000000";
--leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,486)@13
leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_b & leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5(REG,560)@13
reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q <= leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,482)@13
LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q(69 downto 0);
LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_in(69 downto 0);
--leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,483)@13
leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4(REG,559)@13
reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q <= leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,479)@13
LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q(73 downto 0);
LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_in(73 downto 0);
--leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,480)@13
leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_b & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3(REG,558)@13
reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q <= leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2(REG,557)@13
reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,487)@13
leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1(REG,556)@13
reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest(MUX,488)@14
leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s <= reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q;
leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest: PROCESS (leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s, en, reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q, reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q, reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q, reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,496)@14
LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q(74 downto 0);
LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_in(74 downto 0);
--ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b(DELAY,1112)@14
ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 75, depth => 1 )
PORT MAP ( xin => LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest(CONSTANT,229)
leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q <= "000";
--leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,497)@15
leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q & leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,493)@14
LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q(75 downto 0);
LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_in(75 downto 0);
--ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b(DELAY,1110)@14
ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 76, depth => 1 )
PORT MAP ( xin => LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,494)@15
leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,490)@14
LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q(76 downto 0);
LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_in(76 downto 0);
--ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b(DELAY,1108)@14
ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 77, depth => 1 )
PORT MAP ( xin => LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,491)@15
leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q & GND_q;
--reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2(REG,562)@14
reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,498)@13
leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a(DELAY,1184)@13
ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1(REG,561)@14
reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest(MUX,499)@15
leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s <= reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q;
leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest: PROCESS (leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s, en, reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q, leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "10" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "11" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracCompOut_uid203_rrx_uid34_fpSinCosXTest(BITSELECT,202)@15
fracCompOut_uid203_rrx_uid34_fpSinCosXTest_in <= leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q(76 downto 0);
fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b <= fracCompOut_uid203_rrx_uid34_fpSinCosXTest_in(76 downto 24);
--ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b(DELAY,826)@0
ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => xBranch_uid191_rrx_uid34_fpSinCosXTest_n, xout => ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalFrac_uid208_rrx_uid34_fpSinCosXTest(MUX,207)@15
finalFrac_uid208_rrx_uid34_fpSinCosXTest_s <= ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b_q;
finalFrac_uid208_rrx_uid34_fpSinCosXTest: PROCESS (finalFrac_uid208_rrx_uid34_fpSinCosXTest_s, en, fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b, fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE finalFrac_uid208_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => finalFrac_uid208_rrx_uid34_fpSinCosXTest_q <= fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b;
WHEN "1" => finalFrac_uid208_rrx_uid34_fpSinCosXTest_q <= fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => finalFrac_uid208_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RRangeRed_uid210_rrx_uid34_fpSinCosXTest(BITJOIN,209)@15
RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q <= GND_q & ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b_q & finalFrac_uid208_rrx_uid34_fpSinCosXTest_q;
--expXRR_uid38_fpSinCosXTest(BITSELECT,37)@15
expXRR_uid38_fpSinCosXTest_in <= RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q(60 downto 0);
expXRR_uid38_fpSinCosXTest_b <= expXRR_uid38_fpSinCosXTest_in(60 downto 53);
--reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1(REG,565)@15
reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q <= expXRR_uid38_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--cstBiasMwShiftM2_uid26_fpSinCosXTest(CONSTANT,25)
cstBiasMwShiftM2_uid26_fpSinCosXTest_q <= "01110000";
--cosXIsOneXRR_uid42_fpSinCosXTest(COMPARE,41)@16
cosXIsOneXRR_uid42_fpSinCosXTest_cin <= GND_q;
cosXIsOneXRR_uid42_fpSinCosXTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid26_fpSinCosXTest_q) & '0';
cosXIsOneXRR_uid42_fpSinCosXTest_b <= STD_LOGIC_VECTOR((10 downto 8 => reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q(7)) & reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q) & cosXIsOneXRR_uid42_fpSinCosXTest_cin(0);
cosXIsOneXRR_uid42_fpSinCosXTest_o <= STD_LOGIC_VECTOR(SIGNED(cosXIsOneXRR_uid42_fpSinCosXTest_a) - SIGNED(cosXIsOneXRR_uid42_fpSinCosXTest_b));
cosXIsOneXRR_uid42_fpSinCosXTest_n(0) <= not cosXIsOneXRR_uid42_fpSinCosXTest_o(11);
--exp_uid9_fpSinCosXTest(BITSELECT,8)@0
exp_uid9_fpSinCosXTest_in <= a(30 downto 0);
exp_uid9_fpSinCosXTest_b <= exp_uid9_fpSinCosXTest_in(30 downto 23);
--sinXIsX_uid40_fpSinCosXTest(COMPARE,39)@0
sinXIsX_uid40_fpSinCosXTest_cin <= GND_q;
sinXIsX_uid40_fpSinCosXTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid24_fpSinCosXTest_q) & '0';
sinXIsX_uid40_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & exp_uid9_fpSinCosXTest_b) & sinXIsX_uid40_fpSinCosXTest_cin(0);
sinXIsX_uid40_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid40_fpSinCosXTest_a) - UNSIGNED(sinXIsX_uid40_fpSinCosXTest_b));
sinXIsX_uid40_fpSinCosXTest_n(0) <= not sinXIsX_uid40_fpSinCosXTest_o(10);
--ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a(DELAY,789)@0
ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => sinXIsX_uid40_fpSinCosXTest_n, xout => ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--cosXONe_uid148_fpSinCosXTest(LOGICAL,147)@16
cosXONe_uid148_fpSinCosXTest_a <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a_q;
cosXONe_uid148_fpSinCosXTest_b <= cosXIsOneXRR_uid42_fpSinCosXTest_n;
cosXONe_uid148_fpSinCosXTest_q <= cosXONe_uid148_fpSinCosXTest_a or cosXONe_uid148_fpSinCosXTest_b;
--ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a(DELAY,791)@16
ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => cosXONe_uid148_fpSinCosXTest_q, xout => ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--VCC(CONSTANT,1)
VCC_q <= "1";
--InvCosXONe_uid149_fpSinCosXTest(LOGICAL,148)@20
InvCosXONe_uid149_fpSinCosXTest_a <= ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a_q;
InvCosXONe_uid149_fpSinCosXTest_q <= not InvCosXONe_uid149_fpSinCosXTest_a;
--cstZwShiftP1_uid27_fpSinCosXTest(CONSTANT,26)
cstZwShiftP1_uid27_fpSinCosXTest_q <= "00000000000000";
--fracXRR_uid39_fpSinCosXTest(BITSELECT,38)@15
fracXRR_uid39_fpSinCosXTest_in <= RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q(52 downto 0);
fracXRR_uid39_fpSinCosXTest_b <= fracXRR_uid39_fpSinCosXTest_in(52 downto 0);
--ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a(DELAY,668)@15
ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => fracXRR_uid39_fpSinCosXTest_b, xout => ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracXRR_uid43_uid43_fpSinCosXTest(BITJOIN,42)@16
oFracXRR_uid43_uid43_fpSinCosXTest_q <= VCC_q & ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a_q;
--extendedFracX_uid47_fpSinCosXTest(BITJOIN,46)@16
extendedFracX_uid47_fpSinCosXTest_q <= cstZwShiftP1_uid27_fpSinCosXTest_q & oFracXRR_uid43_uid43_fpSinCosXTest_q;
--X55dto0_uid220_fxpX_uid48_fpSinCosXTest(BITSELECT,219)@16
X55dto0_uid220_fxpX_uid48_fpSinCosXTest_in <= extendedFracX_uid47_fpSinCosXTest_q(55 downto 0);
X55dto0_uid220_fxpX_uid48_fpSinCosXTest_b <= X55dto0_uid220_fxpX_uid48_fpSinCosXTest_in(55 downto 0);
--leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest(BITJOIN,220)@16
leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_q <= X55dto0_uid220_fxpX_uid48_fpSinCosXTest_b & leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5(REG,571)@16
reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q <= leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--X59dto0_uid217_fxpX_uid48_fpSinCosXTest(BITSELECT,216)@16
X59dto0_uid217_fxpX_uid48_fpSinCosXTest_in <= extendedFracX_uid47_fpSinCosXTest_q(59 downto 0);
X59dto0_uid217_fxpX_uid48_fpSinCosXTest_b <= X59dto0_uid217_fxpX_uid48_fpSinCosXTest_in(59 downto 0);
--leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest(BITJOIN,217)@16
leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_q <= X59dto0_uid217_fxpX_uid48_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4(REG,570)@16
reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q <= leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--X63dto0_uid214_fxpX_uid48_fpSinCosXTest(BITSELECT,213)@16
X63dto0_uid214_fxpX_uid48_fpSinCosXTest_in <= extendedFracX_uid47_fpSinCosXTest_q(63 downto 0);
X63dto0_uid214_fxpX_uid48_fpSinCosXTest_b <= X63dto0_uid214_fxpX_uid48_fpSinCosXTest_in(63 downto 0);
--leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest(BITJOIN,214)@16
leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_q <= X63dto0_uid214_fxpX_uid48_fpSinCosXTest_b & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3(REG,569)@16
reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q <= leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2(REG,568)@16
reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q <= extendedFracX_uid47_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--fxpXShiftValExt_uid45_fpSinCosXTest(SUB,44)@16
fxpXShiftValExt_uid45_fpSinCosXTest_a <= STD_LOGIC_VECTOR((10 downto 8 => reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q(7)) & reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q);
fxpXShiftValExt_uid45_fpSinCosXTest_b <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid26_fpSinCosXTest_q);
fxpXShiftValExt_uid45_fpSinCosXTest_o <= STD_LOGIC_VECTOR(SIGNED(fxpXShiftValExt_uid45_fpSinCosXTest_a) - SIGNED(fxpXShiftValExt_uid45_fpSinCosXTest_b));
fxpXShiftValExt_uid45_fpSinCosXTest_q <= fxpXShiftValExt_uid45_fpSinCosXTest_o(9 downto 0);
--fxpXShiftVal_uid46_fpSinCosXTest(BITSELECT,45)@16
fxpXShiftVal_uid46_fpSinCosXTest_in <= fxpXShiftValExt_uid45_fpSinCosXTest_q(3 downto 0);
fxpXShiftVal_uid46_fpSinCosXTest_b <= fxpXShiftVal_uid46_fpSinCosXTest_in(3 downto 0);
--leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest(BITSELECT,221)@16
leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_in <= fxpXShiftVal_uid46_fpSinCosXTest_b;
leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_b <= leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1(REG,567)@16
reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q <= leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest(MUX,222)@17
leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s <= reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q;
leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest: PROCESS (leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s, en, reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q, reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q, reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q, reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest(BITSELECT,230)@17
LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_in <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q(64 downto 0);
LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b <= LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_in(64 downto 0);
--ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b(DELAY,851)@17
ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b, xout => ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest(BITJOIN,231)@18
leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q <= ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b_q & leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest(BITSELECT,227)@17
LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_in <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q(65 downto 0);
LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b <= LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_in(65 downto 0);
--ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b(DELAY,849)@17
ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 66, depth => 1 )
PORT MAP ( xin => LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b, xout => ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest(BITJOIN,228)@18
leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q <= ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest(BITSELECT,224)@17
LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_in <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q(66 downto 0);
LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b <= LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_in(66 downto 0);
--ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b(DELAY,847)@17
ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 67, depth => 1 )
PORT MAP ( xin => LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b, xout => ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest(BITJOIN,225)@18
leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q <= ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b_q & GND_q;
--reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2(REG,573)@17
reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest(BITSELECT,232)@16
leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_in <= fxpXShiftVal_uid46_fpSinCosXTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b <= leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a(DELAY,1195)@16
ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b, xout => ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1(REG,572)@17
reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q <= ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest(MUX,233)@18
leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s <= reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q;
leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest: PROCESS (leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s, en, reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q, leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q, leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q, leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q;
WHEN "10" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q;
WHEN "11" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid50_fpSinCosXTest(BITSELECT,49)@18
y_uid50_fpSinCosXTest_in <= leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q(66 downto 0);
y_uid50_fpSinCosXTest_b <= y_uid50_fpSinCosXTest_in(66 downto 1);
--ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b(DELAY,680)@18
ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 66, depth => 2 )
PORT MAP ( xin => y_uid50_fpSinCosXTest_b, xout => ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1(REG,575)@18
reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q <= y_uid50_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--pad_one_uid55_fpSinCosXTest(BITJOIN,54)@18
pad_one_uid55_fpSinCosXTest_q <= VCC_q & STD_LOGIC_VECTOR((65 downto 1 => GND_q(0)) & GND_q);
--reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0(REG,574)@18
reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q <= pad_one_uid55_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--oneMinusY_uid55_fpSinCosXTest(SUB,55)@19
oneMinusY_uid55_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q);
oneMinusY_uid55_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q);
oneMinusY_uid55_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid55_fpSinCosXTest_a) - UNSIGNED(oneMinusY_uid55_fpSinCosXTest_b));
oneMinusY_uid55_fpSinCosXTest_q <= oneMinusY_uid55_fpSinCosXTest_o(67 downto 0);
--reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0(REG,576)@19
reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q <= oneMinusY_uid55_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid57_fpSinCosXTest(COMPARE,56)@20
cmpYToOneMinusY_uid57_fpSinCosXTest_cin <= GND_q;
cmpYToOneMinusY_uid57_fpSinCosXTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q) & '0';
cmpYToOneMinusY_uid57_fpSinCosXTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q) & cmpYToOneMinusY_uid57_fpSinCosXTest_cin(0);
cmpYToOneMinusY_uid57_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid57_fpSinCosXTest_a) - UNSIGNED(cmpYToOneMinusY_uid57_fpSinCosXTest_b));
cmpYToOneMinusY_uid57_fpSinCosXTest_c(0) <= cmpYToOneMinusY_uid57_fpSinCosXTest_o(70);
--InvCmpYToOneMinusY_uid61_fpSinCosXTest(LOGICAL,60)@20
InvCmpYToOneMinusY_uid61_fpSinCosXTest_a <= cmpYToOneMinusY_uid57_fpSinCosXTest_c;
InvCmpYToOneMinusY_uid61_fpSinCosXTest_q <= not InvCmpYToOneMinusY_uid61_fpSinCosXTest_a;
--intXParity_uid49_fpSinCosXTest(BITSELECT,48)@18
intXParity_uid49_fpSinCosXTest_in <= leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q;
intXParity_uid49_fpSinCosXTest_b <= intXParity_uid49_fpSinCosXTest_in(67 downto 67);
--ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b(DELAY,794)@18
ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => intXParity_uid49_fpSinCosXTest_b, xout => ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--yIsZero_uid51_fpSinCosXTest(LOGICAL,50)@19
yIsZero_uid51_fpSinCosXTest_a <= reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q;
yIsZero_uid51_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000000000000000000000000000000000" & GND_q);
yIsZero_uid51_fpSinCosXTest_q <= "1" when yIsZero_uid51_fpSinCosXTest_a = yIsZero_uid51_fpSinCosXTest_b else "0";
--ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a(DELAY,792)@19
ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => yIsZero_uid51_fpSinCosXTest_q, xout => ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvYIsZero_uid151_fpSinCosXTest(LOGICAL,150)@20
InvYIsZero_uid151_fpSinCosXTest_a <= ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a_q;
InvYIsZero_uid151_fpSinCosXTest_q <= not InvYIsZero_uid151_fpSinCosXTest_a;
--signRCond2_uid152_fpSinCosXTest(LOGICAL,151)@20
signRCond2_uid152_fpSinCosXTest_a <= InvYIsZero_uid151_fpSinCosXTest_q;
signRCond2_uid152_fpSinCosXTest_b <= ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q;
signRCond2_uid152_fpSinCosXTest_c <= InvCmpYToOneMinusY_uid61_fpSinCosXTest_q;
signRCond2_uid152_fpSinCosXTest_d <= InvCosXONe_uid149_fpSinCosXTest_q;
signRCond2_uid152_fpSinCosXTest_q_i <= signRCond2_uid152_fpSinCosXTest_a and signRCond2_uid152_fpSinCosXTest_b and signRCond2_uid152_fpSinCosXTest_c and signRCond2_uid152_fpSinCosXTest_d;
signRCond2_uid152_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRCond2_uid152_fpSinCosXTest_q, xin => signRCond2_uid152_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--InvIntXParity_uid155_fpSinCosXTest(LOGICAL,154)@20
InvIntXParity_uid155_fpSinCosXTest_a <= ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q;
InvIntXParity_uid155_fpSinCosXTest_q <= not InvIntXParity_uid155_fpSinCosXTest_a;
--signRCond1_uid157_fpSinCosXTest(LOGICAL,156)@20
signRCond1_uid157_fpSinCosXTest_a <= InvYIsZero_uid151_fpSinCosXTest_q;
signRCond1_uid157_fpSinCosXTest_b <= InvIntXParity_uid155_fpSinCosXTest_q;
signRCond1_uid157_fpSinCosXTest_c <= cmpYToOneMinusY_uid57_fpSinCosXTest_c;
signRCond1_uid157_fpSinCosXTest_d <= InvCosXONe_uid149_fpSinCosXTest_q;
signRCond1_uid157_fpSinCosXTest_q_i <= signRCond1_uid157_fpSinCosXTest_a and signRCond1_uid157_fpSinCosXTest_b and signRCond1_uid157_fpSinCosXTest_c and signRCond1_uid157_fpSinCosXTest_d;
signRCond1_uid157_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRCond1_uid157_fpSinCosXTest_q, xin => signRCond1_uid157_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--signRCos_uid158_fpSinCosXTest(LOGICAL,157)@21
signRCos_uid158_fpSinCosXTest_a <= signRCond1_uid157_fpSinCosXTest_q;
signRCos_uid158_fpSinCosXTest_b <= signRCond2_uid152_fpSinCosXTest_q;
signRCos_uid158_fpSinCosXTest_q <= signRCos_uid158_fpSinCosXTest_a or signRCos_uid158_fpSinCosXTest_b;
--cstAllZWF_uid7_fpSinCosXTest(CONSTANT,6)
cstAllZWF_uid7_fpSinCosXTest_q <= "00000000000000000000000";
--frac_uid13_fpSinCosXTest(BITSELECT,12)@0
frac_uid13_fpSinCosXTest_in <= a(22 downto 0);
frac_uid13_fpSinCosXTest_b <= frac_uid13_fpSinCosXTest_in(22 downto 0);
--fracXIsZero_uid14_fpSinCosXTest(LOGICAL,13)@0
fracXIsZero_uid14_fpSinCosXTest_a <= frac_uid13_fpSinCosXTest_b;
fracXIsZero_uid14_fpSinCosXTest_b <= cstAllZWF_uid7_fpSinCosXTest_q;
fracXIsZero_uid14_fpSinCosXTest_q <= "1" when fracXIsZero_uid14_fpSinCosXTest_a = fracXIsZero_uid14_fpSinCosXTest_b else "0";
--cstAllOWE_uid6_fpSinCosXTest(CONSTANT,5)
cstAllOWE_uid6_fpSinCosXTest_q <= "11111111";
--expXIsMax_uid12_fpSinCosXTest(LOGICAL,11)@0
expXIsMax_uid12_fpSinCosXTest_a <= exp_uid9_fpSinCosXTest_b;
expXIsMax_uid12_fpSinCosXTest_b <= cstAllOWE_uid6_fpSinCosXTest_q;
expXIsMax_uid12_fpSinCosXTest_q <= "1" when expXIsMax_uid12_fpSinCosXTest_a = expXIsMax_uid12_fpSinCosXTest_b else "0";
--exc_I_uid15_fpSinCosXTest(LOGICAL,14)@0
exc_I_uid15_fpSinCosXTest_a <= expXIsMax_uid12_fpSinCosXTest_q;
exc_I_uid15_fpSinCosXTest_b <= fracXIsZero_uid14_fpSinCosXTest_q;
exc_I_uid15_fpSinCosXTest_q <= exc_I_uid15_fpSinCosXTest_a and exc_I_uid15_fpSinCosXTest_b;
--ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a(DELAY,762)@0
ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 20 )
PORT MAP ( xin => exc_I_uid15_fpSinCosXTest_q, xout => ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_I_uid131_fpSinCosXTest(LOGICAL,130)@20
InvExc_I_uid131_fpSinCosXTest_a <= ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a_q;
InvExc_I_uid131_fpSinCosXTest_q <= not InvExc_I_uid131_fpSinCosXTest_a;
--reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2(REG,649)@20
reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q <= InvExc_I_uid131_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--InvFracXIsZero_uid16_fpSinCosXTest(LOGICAL,15)@0
InvFracXIsZero_uid16_fpSinCosXTest_a <= fracXIsZero_uid14_fpSinCosXTest_q;
InvFracXIsZero_uid16_fpSinCosXTest_q <= not InvFracXIsZero_uid16_fpSinCosXTest_a;
--exc_N_uid17_fpSinCosXTest(LOGICAL,16)@0
exc_N_uid17_fpSinCosXTest_a <= expXIsMax_uid12_fpSinCosXTest_q;
exc_N_uid17_fpSinCosXTest_b <= InvFracXIsZero_uid16_fpSinCosXTest_q;
exc_N_uid17_fpSinCosXTest_q <= exc_N_uid17_fpSinCosXTest_a and exc_N_uid17_fpSinCosXTest_b;
--ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a(DELAY,763)@0
ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 20 )
PORT MAP ( xin => exc_N_uid17_fpSinCosXTest_q, xout => ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid132_fpSinCosXTest(LOGICAL,131)@20
InvExc_N_uid132_fpSinCosXTest_a <= ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a_q;
InvExc_N_uid132_fpSinCosXTest_q <= not InvExc_N_uid132_fpSinCosXTest_a;
--reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1(REG,648)@20
reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q <= InvExc_N_uid132_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--signRCosFull_uid161_fpSinCosXTest(LOGICAL,160)@21
signRCosFull_uid161_fpSinCosXTest_a <= reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q;
signRCosFull_uid161_fpSinCosXTest_b <= reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q;
signRCosFull_uid161_fpSinCosXTest_c <= signRCos_uid158_fpSinCosXTest_q;
signRCosFull_uid161_fpSinCosXTest_q <= signRCosFull_uid161_fpSinCosXTest_a and signRCosFull_uid161_fpSinCosXTest_b and signRCosFull_uid161_fpSinCosXTest_c;
--ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c(DELAY,809)@21
ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => signRCosFull_uid161_fpSinCosXTest_q, xout => ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid22_fpSinCosXTest(CONSTANT,21)
cstBias_uid22_fpSinCosXTest_q <= "01111111";
--ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a(DELAY,681)@19
ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 68, depth => 1 )
PORT MAP ( xin => oneMinusY_uid55_fpSinCosXTest_q, xout => ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--zSinOMyBottom_uid58_fpSinCosXTest(BITSELECT,57)@20
zSinOMyBottom_uid58_fpSinCosXTest_in <= ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a_q(64 downto 0);
zSinOMyBottom_uid58_fpSinCosXTest_b <= zSinOMyBottom_uid58_fpSinCosXTest_in(64 downto 0);
--reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3(REG,579)@20
reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q <= zSinOMyBottom_uid58_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--zSinYBottom_uid59_fpSinCosXTest(BITSELECT,58)@20
zSinYBottom_uid59_fpSinCosXTest_in <= ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q(64 downto 0);
zSinYBottom_uid59_fpSinCosXTest_b <= zSinYBottom_uid59_fpSinCosXTest_in(64 downto 0);
--reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2(REG,578)@20
reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q <= zSinYBottom_uid59_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1(REG,614)@20
reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q <= InvCmpYToOneMinusY_uid61_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--zCos_uid64_fpSinCosXTest(MUX,63)@21
zCos_uid64_fpSinCosXTest_s <= reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q;
zCos_uid64_fpSinCosXTest: PROCESS (zCos_uid64_fpSinCosXTest_s, en, reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q, reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q)
BEGIN
CASE zCos_uid64_fpSinCosXTest_s IS
WHEN "0" => zCos_uid64_fpSinCosXTest_q <= reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q;
WHEN "1" => zCos_uid64_fpSinCosXTest_q <= reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q;
WHEN OTHERS => zCos_uid64_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--addr_uid83_fpSinCosXTest(BITSELECT,82)@21
addr_uid83_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q;
addr_uid83_fpSinCosXTest_b <= addr_uid83_fpSinCosXTest_in(64 downto 57);
--reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0(REG,630)@21
reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q <= addr_uid83_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid404_tableGencosPiZ_lutmem(DUALMEM,532)@22
memoryC2_uid404_tableGencosPiZ_lutmem_ia <= (others => '0');
memoryC2_uid404_tableGencosPiZ_lutmem_aa <= (others => '0');
memoryC2_uid404_tableGencosPiZ_lutmem_ab <= reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q;
memoryC2_uid404_tableGencosPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC2_uid404_tableGencosPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid404_tableGencosPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid404_tableGencosPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid404_tableGencosPiZ_lutmem_iq,
address_a => memoryC2_uid404_tableGencosPiZ_lutmem_aa,
data_a => memoryC2_uid404_tableGencosPiZ_lutmem_ia
);
memoryC2_uid404_tableGencosPiZ_lutmem_reset0 <= areset;
memoryC2_uid404_tableGencosPiZ_lutmem_q <= memoryC2_uid404_tableGencosPiZ_lutmem_iq(12 downto 0);
--reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1(REG,632)@24
reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q <= memoryC2_uid404_tableGencosPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--zPcosPiZ_uid87_fpSinCosXTest(BITSELECT,86)@21
zPcosPiZ_uid87_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q(56 downto 0);
zPcosPiZ_uid87_fpSinCosXTest_b <= zPcosPiZ_uid87_fpSinCosXTest_in(56 downto 42);
--yT1_uid419_polyEvalcosPiZ(BITSELECT,418)@21
yT1_uid419_polyEvalcosPiZ_in <= zPcosPiZ_uid87_fpSinCosXTest_b;
yT1_uid419_polyEvalcosPiZ_b <= yT1_uid419_polyEvalcosPiZ_in(14 downto 2);
--reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0(REG,631)@21
reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q <= yT1_uid419_polyEvalcosPiZ_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg(DELAY,1513)
ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q, xout => ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a(DELAY,1125)@22
ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg_q, xout => ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid508_pT1_uid420_polyEvalcosPiZ(MULT,507)@25
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a),14)) * SIGNED(prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b);
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a <= (others => '0');
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b <= (others => '0');
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a <= ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_q;
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b <= reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q;
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid508_pT1_uid420_polyEvalcosPiZ_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid508_pT1_uid420_polyEvalcosPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q <= prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ(BITSELECT,508)@28
prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_in <= prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q;
prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b <= prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_in(25 downto 12);
--highBBits_uid422_polyEvalcosPiZ(BITSELECT,421)@28
highBBits_uid422_polyEvalcosPiZ_in <= prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b;
highBBits_uid422_polyEvalcosPiZ_b <= highBBits_uid422_polyEvalcosPiZ_in(13 downto 1);
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a(DELAY,1256)@21
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => addr_uid83_fpSinCosXTest_b, xout => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0(REG,633)@24
reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid402_tableGencosPiZ_lutmem(DUALMEM,531)@25
memoryC1_uid402_tableGencosPiZ_lutmem_ia <= (others => '0');
memoryC1_uid402_tableGencosPiZ_lutmem_aa <= (others => '0');
memoryC1_uid402_tableGencosPiZ_lutmem_ab <= reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q;
memoryC1_uid402_tableGencosPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC1_uid402_tableGencosPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid402_tableGencosPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid402_tableGencosPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid402_tableGencosPiZ_lutmem_iq,
address_a => memoryC1_uid402_tableGencosPiZ_lutmem_aa,
data_a => memoryC1_uid402_tableGencosPiZ_lutmem_ia
);
memoryC1_uid402_tableGencosPiZ_lutmem_reset0 <= areset;
memoryC1_uid402_tableGencosPiZ_lutmem_q <= memoryC1_uid402_tableGencosPiZ_lutmem_iq(20 downto 0);
--reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0(REG,634)@27
reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q <= memoryC1_uid402_tableGencosPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid423_polyEvalcosPiZ(ADD,422)@28
sumAHighB_uid423_polyEvalcosPiZ_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q(20)) & reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q);
sumAHighB_uid423_polyEvalcosPiZ_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid422_polyEvalcosPiZ_b(12)) & highBBits_uid422_polyEvalcosPiZ_b);
sumAHighB_uid423_polyEvalcosPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid423_polyEvalcosPiZ_a) + SIGNED(sumAHighB_uid423_polyEvalcosPiZ_b));
sumAHighB_uid423_polyEvalcosPiZ_q <= sumAHighB_uid423_polyEvalcosPiZ_o(21 downto 0);
--lowRangeB_uid421_polyEvalcosPiZ(BITSELECT,420)@28
lowRangeB_uid421_polyEvalcosPiZ_in <= prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b(0 downto 0);
lowRangeB_uid421_polyEvalcosPiZ_b <= lowRangeB_uid421_polyEvalcosPiZ_in(0 downto 0);
--s1_uid421_uid424_polyEvalcosPiZ(BITJOIN,423)@28
s1_uid421_uid424_polyEvalcosPiZ_q <= sumAHighB_uid423_polyEvalcosPiZ_q & lowRangeB_uid421_polyEvalcosPiZ_b;
--reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1(REG,636)@28
reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q <= s1_uid421_uid424_polyEvalcosPiZ_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor(LOGICAL,1524)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_b <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_q <= not (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_a or ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_b);
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top(CONSTANT,1520)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top_q <= "0100";
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp(LOGICAL,1521)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_a <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q);
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_q <= "1" when ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_a = ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_b else "0";
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg(REG,1522)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena(REG,1525)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_q = "1") THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd(LOGICAL,1526)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_a <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_b <= en;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_a and ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_b;
--reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0(REG,635)@21
reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q <= zPcosPiZ_uid87_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg(DELAY,1514)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q, xout => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt(COUNTER,1516)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i = 3 THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i - 4;
ELSE
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i,3));
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg(REG,1517)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux(MUX,1518)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s <= en;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux: PROCESS (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s, ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q, ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
WHEN "1" => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem(DUALMEM,1515)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ia <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 3,
numwords_a => 5,
width_b => 15,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_iq,
address_a => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_aa,
data_a => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ia
);
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_reset0 <= areset;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_iq(14 downto 0);
--prodXY_uid511_pT2_uid426_polyEvalcosPiZ(MULT,510)@29
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a),16)) * SIGNED(prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b);
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a <= (others => '0');
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b <= (others => '0');
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_q;
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b <= reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q;
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid511_pT2_uid426_polyEvalcosPiZ_pr,38));
END IF;
END IF;
END PROCESS;
prodXY_uid511_pT2_uid426_polyEvalcosPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q <= prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ(BITSELECT,511)@32
prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_in <= prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q;
prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b <= prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_in(37 downto 14);
--highBBits_uid428_polyEvalcosPiZ(BITSELECT,427)@32
highBBits_uid428_polyEvalcosPiZ_in <= prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b;
highBBits_uid428_polyEvalcosPiZ_b <= highBBits_uid428_polyEvalcosPiZ_in(23 downto 2);
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor(LOGICAL,1577)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_b <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_q <= not (ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_a or ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_b);
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena(REG,1578)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_q = "1") THEN
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd(LOGICAL,1579)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_a <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_b <= en;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_a and ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_b;
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg(DELAY,1567)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addr_uid83_fpSinCosXTest_b, xout => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem(DUALMEM,1568)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ia <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_iq,
address_a => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_aa,
data_a => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ia
);
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0(REG,637)@28
reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid400_tableGencosPiZ_lutmem(DUALMEM,530)@29
memoryC0_uid400_tableGencosPiZ_lutmem_ia <= (others => '0');
memoryC0_uid400_tableGencosPiZ_lutmem_aa <= (others => '0');
memoryC0_uid400_tableGencosPiZ_lutmem_ab <= reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q;
memoryC0_uid400_tableGencosPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC0_uid400_tableGencosPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid400_tableGencosPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid400_tableGencosPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid400_tableGencosPiZ_lutmem_iq,
address_a => memoryC0_uid400_tableGencosPiZ_lutmem_aa,
data_a => memoryC0_uid400_tableGencosPiZ_lutmem_ia
);
memoryC0_uid400_tableGencosPiZ_lutmem_reset0 <= areset;
memoryC0_uid400_tableGencosPiZ_lutmem_q <= memoryC0_uid400_tableGencosPiZ_lutmem_iq(29 downto 0);
--reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0(REG,638)@31
reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q <= memoryC0_uid400_tableGencosPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid429_polyEvalcosPiZ(ADD,428)@32
sumAHighB_uid429_polyEvalcosPiZ_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q(29)) & reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q);
sumAHighB_uid429_polyEvalcosPiZ_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid428_polyEvalcosPiZ_b(21)) & highBBits_uid428_polyEvalcosPiZ_b);
sumAHighB_uid429_polyEvalcosPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid429_polyEvalcosPiZ_a) + SIGNED(sumAHighB_uid429_polyEvalcosPiZ_b));
sumAHighB_uid429_polyEvalcosPiZ_q <= sumAHighB_uid429_polyEvalcosPiZ_o(30 downto 0);
--lowRangeB_uid427_polyEvalcosPiZ(BITSELECT,426)@32
lowRangeB_uid427_polyEvalcosPiZ_in <= prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b(1 downto 0);
lowRangeB_uid427_polyEvalcosPiZ_b <= lowRangeB_uid427_polyEvalcosPiZ_in(1 downto 0);
--s2_uid427_uid430_polyEvalcosPiZ(BITJOIN,429)@32
s2_uid427_uid430_polyEvalcosPiZ_q <= sumAHighB_uid429_polyEvalcosPiZ_q & lowRangeB_uid427_polyEvalcosPiZ_b;
--polyEvalSigcosPiZ_uid89_fpSinCosXTest(BITSELECT,88)@32
polyEvalSigcosPiZ_uid89_fpSinCosXTest_in <= s2_uid427_uid430_polyEvalcosPiZ_q(30 downto 0);
polyEvalSigcosPiZ_uid89_fpSinCosXTest_b <= polyEvalSigcosPiZ_uid89_fpSinCosXTest_in(30 downto 5);
--reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1(REG,640)@32
reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q <= polyEvalSigcosPiZ_uid89_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor(LOGICAL,1590)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_b <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_q <= not (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_a or ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_b);
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top(CONSTANT,1586)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top_q <= "010";
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp(LOGICAL,1587)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_a <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q);
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_q <= "1" when ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_a = ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_b else "0";
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg(REG,1588)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena(REG,1591)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_q = "1") THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd(LOGICAL,1592)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_a <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_b <= en;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_a and ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_b;
--LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest(BITSELECT,388)@27
LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q(63 downto 0);
LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_in(63 downto 0);
--leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest(BITJOIN,389)@27
leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_b & GND_q;
--cstZmwFRRPwSM1_uid52_fpSinCosXTest(CONSTANT,51)
cstZmwFRRPwSM1_uid52_fpSinCosXTest_q <= "00000000000000000000000000000000000000000000000000000000000000000";
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor(LOGICAL,1455)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_b <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_q <= not (ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_a or ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_b);
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena(REG,1456)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_q = "1") THEN
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd(LOGICAL,1457)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_a <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_b <= en;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_q <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_a and ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_b;
--X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest(BITSELECT,359)@21
X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q(32 downto 0);
X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b <= X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_in(32 downto 0);
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg(DELAY,1447)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem(DUALMEM,1448)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ia <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 33,
widthad_a => 1,
numwords_a => 2,
width_b => 33,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ia
);
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_q <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_iq(32 downto 0);
--leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest(BITJOIN,360)@25
leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_q & zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor(LOGICAL,1466)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_b <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_q <= not (ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_a or ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_b);
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena(REG,1467)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_q = "1") THEN
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd(LOGICAL,1468)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_a <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_b <= en;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_q <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_a and ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_b;
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg(DELAY,1458)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => zCos_uid64_fpSinCosXTest_q, xout => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem(DUALMEM,1459)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ia <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 65,
widthad_a => 1,
numwords_a => 2,
width_b => 65,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_iq,
address_a => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_aa,
data_a => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ia
);
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_reset0 <= areset;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_iq(64 downto 0);
--zs_uid236_lzcZSin_uid66_fpSinCosXTest(CONSTANT,235)
zs_uid236_lzcZSin_uid66_fpSinCosXTest_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--rVStage_uid316_lzcZCos_uid69_fpSinCosXTest(BITSELECT,315)@21
rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q;
rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_in(64 downto 1);
--vCount_uid317_lzcZCos_uid69_fpSinCosXTest(LOGICAL,316)@21
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_b <= zs_uid236_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_i <= "1" when vCount_uid317_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid317_lzcZCos_uid69_fpSinCosXTest_b else "0";
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q, xin => vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g(DELAY,985)@22
ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q, xout => ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid319_lzcZCos_uid69_fpSinCosXTest(BITSELECT,318)@21
vStage_uid319_lzcZCos_uid69_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q(0 downto 0);
vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid319_lzcZCos_uid69_fpSinCosXTest_in(0 downto 0);
--ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b(DELAY,943)@21
ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid239_lzcZSin_uid66_fpSinCosXTest(CONSTANT,238)
mO_uid239_lzcZSin_uid66_fpSinCosXTest_q <= "111111111111111111111111111111111111111111111111111111111111111";
--cStage_uid320_lzcZCos_uid69_fpSinCosXTest(BITJOIN,319)@22
cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q <= ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b_q & mO_uid239_lzcZSin_uid66_fpSinCosXTest_q;
--ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c(DELAY,945)@21
ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid322_lzcZCos_uid69_fpSinCosXTest(MUX,321)@22
vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid322_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s, en, ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q, cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q)
BEGIN
CASE vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q <= ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q <= cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q;
WHEN OTHERS => vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid324_lzcZCos_uid69_fpSinCosXTest(BITSELECT,323)@22
rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_in(63 downto 32);
--vCount_uid325_lzcZCos_uid69_fpSinCosXTest(LOGICAL,324)@22
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_b <= zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_i <= "1" when vCount_uid325_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid325_lzcZCos_uid69_fpSinCosXTest_b else "0";
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q, xin => vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f(DELAY,984)@23
ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q, xout => ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid326_lzcZCos_uid69_fpSinCosXTest(BITSELECT,325)@22
vStage_uid326_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q(31 downto 0);
vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid326_lzcZCos_uid69_fpSinCosXTest_in(31 downto 0);
--ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d(DELAY,952)@22
ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c(DELAY,951)@22
ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid328_lzcZCos_uid69_fpSinCosXTest(MUX,327)@23
vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid328_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s, en, ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q, ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q)
BEGIN
CASE vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q <= ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q <= ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q;
WHEN OTHERS => vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid330_lzcZCos_uid69_fpSinCosXTest(BITSELECT,329)@23
rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_in(31 downto 16);
--vCount_uid331_lzcZCos_uid69_fpSinCosXTest(LOGICAL,330)@23
vCount_uid331_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid331_lzcZCos_uid69_fpSinCosXTest_b <= zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid331_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid331_lzcZCos_uid69_fpSinCosXTest_b else "0";
--reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4(REG,622)@23
reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q <= vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e(DELAY,983)@24
ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q, xout => ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid332_lzcZCos_uid69_fpSinCosXTest(BITSELECT,331)@23
vStage_uid332_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q(15 downto 0);
vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid332_lzcZCos_uid69_fpSinCosXTest_in(15 downto 0);
--vStagei_uid334_lzcZCos_uid69_fpSinCosXTest(MUX,333)@23
vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid334_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s, en, rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b, vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q <= rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b;
WHEN "1" => vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q <= vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid336_lzcZCos_uid69_fpSinCosXTest(BITSELECT,335)@23
rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_in(15 downto 8);
--reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1(REG,617)@23
reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q <= rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid337_lzcZCos_uid69_fpSinCosXTest(LOGICAL,336)@24
vCount_uid337_lzcZCos_uid69_fpSinCosXTest_a <= reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q;
vCount_uid337_lzcZCos_uid69_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid337_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid337_lzcZCos_uid69_fpSinCosXTest_b else "0";
--ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d(DELAY,982)@24
ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q, xout => ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid338_lzcZCos_uid69_fpSinCosXTest(BITSELECT,337)@23
vStage_uid338_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q(7 downto 0);
vStage_uid338_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid338_lzcZCos_uid69_fpSinCosXTest_in(7 downto 0);
--reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3(REG,619)@23
reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q <= vStage_uid338_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid340_lzcZCos_uid69_fpSinCosXTest(MUX,339)@24
vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid340_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s, en, reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q, reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q <= reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q <= reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid342_lzcZCos_uid69_fpSinCosXTest(BITSELECT,341)@24
rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_in(7 downto 4);
--vCount_uid343_lzcZCos_uid69_fpSinCosXTest(LOGICAL,342)@24
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_b <= leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q_i <= "1" when vCount_uid343_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid343_lzcZCos_uid69_fpSinCosXTest_b else "0";
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q, xin => vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid344_lzcZCos_uid69_fpSinCosXTest(BITSELECT,343)@24
vStage_uid344_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q(3 downto 0);
vStage_uid344_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid344_lzcZCos_uid69_fpSinCosXTest_in(3 downto 0);
--reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3(REG,621)@24
reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q <= vStage_uid344_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2(REG,620)@24
reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q <= rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid346_lzcZCos_uid69_fpSinCosXTest(MUX,345)@25
vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid346_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s, en, reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q, reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q <= reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q <= reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid348_lzcZCos_uid69_fpSinCosXTest(BITSELECT,347)@25
rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_in(3 downto 2);
--vCount_uid349_lzcZCos_uid69_fpSinCosXTest(LOGICAL,348)@25
vCount_uid349_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid349_lzcZCos_uid69_fpSinCosXTest_b <= leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid349_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid349_lzcZCos_uid69_fpSinCosXTest_b else "0";
--vStage_uid350_lzcZCos_uid69_fpSinCosXTest(BITSELECT,349)@25
vStage_uid350_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q(1 downto 0);
vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid350_lzcZCos_uid69_fpSinCosXTest_in(1 downto 0);
--vStagei_uid352_lzcZCos_uid69_fpSinCosXTest(MUX,351)@25
vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid352_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s, en, rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b, vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q <= rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b;
WHEN "1" => vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q <= vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid354_lzcZCos_uid69_fpSinCosXTest(BITSELECT,353)@25
rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_in(1 downto 1);
--vCount_uid355_lzcZCos_uid69_fpSinCosXTest(LOGICAL,354)@25
vCount_uid355_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid355_lzcZCos_uid69_fpSinCosXTest_b <= GND_q;
vCount_uid355_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid355_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid355_lzcZCos_uid69_fpSinCosXTest_b else "0";
--r_uid356_lzcZCos_uid69_fpSinCosXTest(BITJOIN,355)@25
r_uid356_lzcZCos_uid69_fpSinCosXTest_q <= ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g_q & ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f_q & ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e_q & ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d_q & vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q & vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q & vCount_uid355_lzcZCos_uid69_fpSinCosXTest_q;
--leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest(BITSELECT,363)@25
leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q;
leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_in(6 downto 5);
--leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest(MUX,364)@25
leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s <= leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_b;
leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s, en, ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q, leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "10" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN "11" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest(BITSELECT,372)@25
LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q(40 downto 0);
LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_in(40 downto 0);
--leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest(CONSTANT,292)
leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q <= "000000000000000000000000";
--leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest(BITJOIN,373)@25
leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_b & leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q;
--reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5(REG,627)@25
reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q <= leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest(BITSELECT,369)@25
LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q(48 downto 0);
LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_in(48 downto 0);
--leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest(BITJOIN,370)@25
leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_b & zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
--reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4(REG,626)@25
reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q <= leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest(BITSELECT,366)@25
LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q(56 downto 0);
LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_in(56 downto 0);
--leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest(BITJOIN,367)@25
leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3(REG,625)@25
reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q <= leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2(REG,624)@25
reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest(BITSELECT,374)@25
leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1(REG,623)@25
reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q <= leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest(MUX,375)@26
leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s <= reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q;
leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s, en, reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q, reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q, reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q, reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest(BITSELECT,383)@26
LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q(58 downto 0);
LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_in(58 downto 0);
--ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1009)@26
ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest(CONSTANT,303)
leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q <= "000000";
--leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest(BITJOIN,384)@27
leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q <= ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b_q & leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q;
--LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest(BITSELECT,380)@26
LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q(60 downto 0);
LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_in(60 downto 0);
--ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1007)@26
ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest(BITJOIN,381)@27
leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q <= ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b_q & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest(BITSELECT,377)@26
LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q(62 downto 0);
LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_in(62 downto 0);
--ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1005)@26
ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest(BITJOIN,378)@27
leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q <= ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2(REG,629)@26
reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest(BITSELECT,385)@25
leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1(REG,628)@25
reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q <= leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1011)@26
ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q, xout => ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest(MUX,386)@27
leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s <= ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b_q;
leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s, en, reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q, leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q, leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q, leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "10" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "11" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest(BITSELECT,390)@25
leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1019)@25
ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest(MUX,391)@27
leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s <= ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b_q;
leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s, en, leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q, leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "0" => leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "1" => leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--pCos_uid77_fpSinCosXTest(BITSELECT,76)@27
pCos_uid77_fpSinCosXTest_in <= leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q;
pCos_uid77_fpSinCosXTest_b <= pCos_uid77_fpSinCosXTest_in(64 downto 39);
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg(DELAY,1580)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => pCos_uid77_fpSinCosXTest_b, xout => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt(COUNTER,1582)
-- every=1, low=0, high=2, step=1, init=1
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i = 1 THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i - 2;
ELSE
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i,2));
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg(REG,1583)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux(MUX,1584)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s <= en;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux: PROCESS (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s, ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q, ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q)
BEGIN
CASE ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s IS
WHEN "0" => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q;
WHEN "1" => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem(DUALMEM,1581)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ia <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_aa <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ab <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 2,
numwords_a => 3,
width_b => 26,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_iq,
address_a => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_aa,
data_a => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ia
);
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_reset0 <= areset;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_iq(25 downto 0);
--reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0(REG,639)@32
reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--mulCos_uid105_fpSinCosXTest(MULT,104)@33
mulCos_uid105_fpSinCosXTest_pr <= UNSIGNED(mulCos_uid105_fpSinCosXTest_a) * UNSIGNED(mulCos_uid105_fpSinCosXTest_b);
mulCos_uid105_fpSinCosXTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulCos_uid105_fpSinCosXTest_a <= (others => '0');
mulCos_uid105_fpSinCosXTest_b <= (others => '0');
mulCos_uid105_fpSinCosXTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulCos_uid105_fpSinCosXTest_a <= reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q;
mulCos_uid105_fpSinCosXTest_b <= reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q;
mulCos_uid105_fpSinCosXTest_s1 <= STD_LOGIC_VECTOR(mulCos_uid105_fpSinCosXTest_pr);
END IF;
END IF;
END PROCESS;
mulCos_uid105_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulCos_uid105_fpSinCosXTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulCos_uid105_fpSinCosXTest_q <= mulCos_uid105_fpSinCosXTest_s1;
END IF;
END IF;
END PROCESS;
--normBitCos_uid106_fpSinCosXTest(BITSELECT,105)@36
normBitCos_uid106_fpSinCosXTest_in <= mulCos_uid105_fpSinCosXTest_q;
normBitCos_uid106_fpSinCosXTest_b <= normBitCos_uid106_fpSinCosXTest_in(51 downto 51);
--cosRndOp_uid112_uid113_fpSinCosXTest(BITJOIN,112)@36
cosRndOp_uid112_uid113_fpSinCosXTest_q <= normBitCos_uid106_fpSinCosXTest_b & cstAllZWF_uid7_fpSinCosXTest_q & VCC_q;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor(LOGICAL,1296)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_b <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_q <= not (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_a or ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_b);
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top(CONSTANT,1292)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top_q <= "0110";
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp(LOGICAL,1293)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_a <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q);
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_q <= "1" when ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_a = ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_b else "0";
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg(REG,1294)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena(REG,1297)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_q = "1") THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd(LOGICAL,1298)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_a <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_b <= en;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_a and ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_b;
--reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1(REG,641)@25
reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg(DELAY,1286)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q, xout => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt(COUNTER,1288)
-- every=1, low=0, high=6, step=1, init=1
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i = 5 THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i - 6;
ELSE
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i,3));
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg(REG,1289)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux(MUX,1290)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s <= en;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux: PROCESS (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s, ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q, ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem(DUALMEM,1287)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ia <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_aa <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ab <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 7,
width_b => 7,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ia
);
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_iq(6 downto 0);
--expHardCase_uid78_fpSinCosXTest(SUB,77)@35
expHardCase_uid78_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_fpSinCosXTest_q);
expHardCase_uid78_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_q);
expHardCase_uid78_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid78_fpSinCosXTest_a) - UNSIGNED(expHardCase_uid78_fpSinCosXTest_b));
expHardCase_uid78_fpSinCosXTest_q <= expHardCase_uid78_fpSinCosXTest_o(8 downto 0);
--expPCos_uid79_fpSinCosXTest(BITSELECT,78)@35
expPCos_uid79_fpSinCosXTest_in <= expHardCase_uid78_fpSinCosXTest_q(7 downto 0);
expPCos_uid79_fpSinCosXTest_b <= expPCos_uid79_fpSinCosXTest_in(7 downto 0);
--reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1(REG,642)@35
reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q <= expPCos_uid79_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--fracRCosPreRndHigh_uid108_fpSinCosXTest(BITSELECT,107)@36
fracRCosPreRndHigh_uid108_fpSinCosXTest_in <= mulCos_uid105_fpSinCosXTest_q(50 downto 0);
fracRCosPreRndHigh_uid108_fpSinCosXTest_b <= fracRCosPreRndHigh_uid108_fpSinCosXTest_in(50 downto 27);
--fracRCosPreRndLow_uid109_fpSinCosXTest(BITSELECT,108)@36
fracRCosPreRndLow_uid109_fpSinCosXTest_in <= mulCos_uid105_fpSinCosXTest_q(49 downto 0);
fracRCosPreRndLow_uid109_fpSinCosXTest_b <= fracRCosPreRndLow_uid109_fpSinCosXTest_in(49 downto 26);
--fracRCosPreRnd_uid110_fpSinCosXTest(MUX,109)@36
fracRCosPreRnd_uid110_fpSinCosXTest_s <= normBitCos_uid106_fpSinCosXTest_b;
fracRCosPreRnd_uid110_fpSinCosXTest: PROCESS (fracRCosPreRnd_uid110_fpSinCosXTest_s, en, fracRCosPreRndLow_uid109_fpSinCosXTest_b, fracRCosPreRndHigh_uid108_fpSinCosXTest_b)
BEGIN
CASE fracRCosPreRnd_uid110_fpSinCosXTest_s IS
WHEN "0" => fracRCosPreRnd_uid110_fpSinCosXTest_q <= fracRCosPreRndLow_uid109_fpSinCosXTest_b;
WHEN "1" => fracRCosPreRnd_uid110_fpSinCosXTest_q <= fracRCosPreRndHigh_uid108_fpSinCosXTest_b;
WHEN OTHERS => fracRCosPreRnd_uid110_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracRCosPreRnd_uid111_uid111_fpSinCosXTest(BITJOIN,110)@36
expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_q <= reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q & fracRCosPreRnd_uid110_fpSinCosXTest_q;
--expFracRCos_uid114_fpSinCosXTest(ADD,113)@36
expFracRCos_uid114_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_q);
expFracRCos_uid114_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00000000" & cosRndOp_uid112_uid113_fpSinCosXTest_q);
expFracRCos_uid114_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRCos_uid114_fpSinCosXTest_a) + UNSIGNED(expFracRCos_uid114_fpSinCosXTest_b));
expFracRCos_uid114_fpSinCosXTest_q <= expFracRCos_uid114_fpSinCosXTest_o(32 downto 0);
--expRCompSin_uid116_fpSinCosXTest(BITSELECT,115)@36
expRCompSin_uid116_fpSinCosXTest_in <= expFracRCos_uid114_fpSinCosXTest_q(31 downto 0);
expRCompSin_uid116_fpSinCosXTest_b <= expRCompSin_uid116_fpSinCosXTest_in(31 downto 24);
--reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2(REG,646)@36
reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q <= expRCompSin_uid116_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor(LOGICAL,1385)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_b <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_q <= not (ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_a or ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_b);
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top(CONSTANT,1305)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top_q <= "01101";
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp(LOGICAL,1306)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_a <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q);
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_q <= "1" when ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_a = ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_b else "0";
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg(REG,1307)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena(REG,1386)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_q = "1") THEN
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd(LOGICAL,1387)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_a <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_b <= en;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_q <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_a and ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_b;
--ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a(DELAY,745)@0
ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => sinXIsX_uid40_fpSinCosXTest_n, xout => ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c(DELAY,783)@16
ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => cosXIsOneXRR_uid42_fpSinCosXTest_n, xout => ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--InvCosXIsOneXRR_uid136_fpSinCosXTest(LOGICAL,135)@16
InvCosXIsOneXRR_uid136_fpSinCosXTest_a <= cosXIsOneXRR_uid42_fpSinCosXTest_n;
InvCosXIsOneXRR_uid136_fpSinCosXTest_q <= not InvCosXIsOneXRR_uid136_fpSinCosXTest_a;
--ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c(DELAY,773)@16
ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => InvCosXIsOneXRR_uid136_fpSinCosXTest_q, xout => ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a(DELAY,755)@0
ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => sinXIsX_uid40_fpSinCosXTest_n, xout => ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsX_uid127_fpSinCosXTest(LOGICAL,126)@18
InvSinXIsX_uid127_fpSinCosXTest_a <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a_q;
InvSinXIsX_uid127_fpSinCosXTest_q <= not InvSinXIsX_uid127_fpSinCosXTest_a;
--ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b(DELAY,772)@18
ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => InvSinXIsX_uid127_fpSinCosXTest_q, xout => ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--half_uid53_fpSinCosXTest(BITJOIN,52)@19
half_uid53_fpSinCosXTest_q <= VCC_q & cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
--yIsHalf_uid54_fpSinCosXTest(LOGICAL,53)@19
yIsHalf_uid54_fpSinCosXTest_a <= reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q;
yIsHalf_uid54_fpSinCosXTest_b <= half_uid53_fpSinCosXTest_q;
yIsHalf_uid54_fpSinCosXTest_q <= "1" when yIsHalf_uid54_fpSinCosXTest_a = yIsHalf_uid54_fpSinCosXTest_b else "0";
--yHalfCosXNotOne_uid138_fpSinCosXTest(LOGICAL,137)@19
yHalfCosXNotOne_uid138_fpSinCosXTest_a <= yIsHalf_uid54_fpSinCosXTest_q;
yHalfCosXNotOne_uid138_fpSinCosXTest_b <= ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b_q;
yHalfCosXNotOne_uid138_fpSinCosXTest_c <= ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c_q;
yHalfCosXNotOne_uid138_fpSinCosXTest_q <= yHalfCosXNotOne_uid138_fpSinCosXTest_a and yHalfCosXNotOne_uid138_fpSinCosXTest_b and yHalfCosXNotOne_uid138_fpSinCosXTest_c;
--ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b(DELAY,744)@0
ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => exc_I_uid15_fpSinCosXTest_q, xout => ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a(DELAY,743)@0
ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => exc_N_uid17_fpSinCosXTest_q, xout => ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRNaN_uid117_fpSinCosXTest(LOGICAL,116)@19
excRNaN_uid117_fpSinCosXTest_a <= ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a_q;
excRNaN_uid117_fpSinCosXTest_b <= ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b_q;
excRNaN_uid117_fpSinCosXTest_q <= excRNaN_uid117_fpSinCosXTest_a or excRNaN_uid117_fpSinCosXTest_b;
--join_uid143_fpSinCosXTest(BITJOIN,142)@19
join_uid143_fpSinCosXTest_q <= ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q & yHalfCosXNotOne_uid138_fpSinCosXTest_q & excRNaN_uid117_fpSinCosXTest_q;
--expSelBitsCos_uid144_fpSinCosXTest(BITJOIN,143)@19
expSelBitsCos_uid144_fpSinCosXTest_q <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q & join_uid143_fpSinCosXTest_q;
--reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0(REG,645)@19
reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q <= expSelBitsCos_uid144_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--expSelectorCos_uid145_fpSinCosXTest(LOOKUP,144)@20
expSelectorCos_uid145_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSelectorCos_uid145_fpSinCosXTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q) IS
WHEN "0000" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "0001" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "0010" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "0011" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "0100" => expSelectorCos_uid145_fpSinCosXTest_q <= "01";
WHEN "0101" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "0110" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "0111" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "1000" => expSelectorCos_uid145_fpSinCosXTest_q <= "01";
WHEN "1001" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "1010" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "1011" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "1100" => expSelectorCos_uid145_fpSinCosXTest_q <= "01";
WHEN "1101" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "1110" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "1111" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN OTHERS =>
expSelectorCos_uid145_fpSinCosXTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg(DELAY,1375)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => expSelectorCos_uid145_fpSinCosXTest_q, xout => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt(COUNTER,1301)
-- every=1, low=0, high=13, step=1, init=1
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i = 12 THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i - 13;
ELSE
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i,4));
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg(REG,1302)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux(MUX,1303)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s, ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q, ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem(DUALMEM,1376)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ia <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ia
);
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_q <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_iq(1 downto 0);
--expRPostExcCos_uid147_fpSinCosXTest(MUX,146)@37
expRPostExcCos_uid147_fpSinCosXTest_s <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_q;
expRPostExcCos_uid147_fpSinCosXTest: PROCESS (expRPostExcCos_uid147_fpSinCosXTest_s, en, reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q, cstBias_uid22_fpSinCosXTest_q, cstAllZWE_uid8_fpSinCosXTest_q, cstAllOWE_uid6_fpSinCosXTest_q)
BEGIN
CASE expRPostExcCos_uid147_fpSinCosXTest_s IS
WHEN "00" => expRPostExcCos_uid147_fpSinCosXTest_q <= reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q;
WHEN "01" => expRPostExcCos_uid147_fpSinCosXTest_q <= cstBias_uid22_fpSinCosXTest_q;
WHEN "10" => expRPostExcCos_uid147_fpSinCosXTest_q <= cstAllZWE_uid8_fpSinCosXTest_q;
WHEN "11" => expRPostExcCos_uid147_fpSinCosXTest_q <= cstAllOWE_uid6_fpSinCosXTest_q;
WHEN OTHERS => expRPostExcCos_uid147_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstNaNwF_uid32_fpSinCosXTest(CONSTANT,31)
cstNaNwF_uid32_fpSinCosXTest_q <= "00000000000000000000001";
--fracRCompCos_uid115_fpSinCosXTest(BITSELECT,114)@36
fracRCompCos_uid115_fpSinCosXTest_in <= expFracRCos_uid114_fpSinCosXTest_q(23 downto 0);
fracRCompCos_uid115_fpSinCosXTest_b <= fracRCompCos_uid115_fpSinCosXTest_in(23 downto 1);
--reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2(REG,644)@36
reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q <= fracRCompCos_uid115_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor(LOGICAL,1372)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_b <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_q <= not (ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_a or ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_b);
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena(REG,1373)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_q = "1") THEN
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd(LOGICAL,1374)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_a <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_b <= en;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_q <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_a and ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_b;
--reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1(REG,613)@19
reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q <= excRNaN_uid117_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3(REG,612)@19
reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q <= ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q;
END IF;
END IF;
END PROCESS;
--reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2(REG,611)@19
reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q;
END IF;
END IF;
END PROCESS;
--reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1(REG,610)@19
reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q <= yHalfCosXNotOne_uid138_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--rZOrOne_uid140_fpSinCosXTest(LOGICAL,139)@20
rZOrOne_uid140_fpSinCosXTest_a <= reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q;
rZOrOne_uid140_fpSinCosXTest_b <= reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q;
rZOrOne_uid140_fpSinCosXTest_c <= reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q;
rZOrOne_uid140_fpSinCosXTest_q <= rZOrOne_uid140_fpSinCosXTest_a or rZOrOne_uid140_fpSinCosXTest_b or rZOrOne_uid140_fpSinCosXTest_c;
--join_uid141_fpSinCosXTest(BITJOIN,140)@20
join_uid141_fpSinCosXTest_q <= reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q & rZOrOne_uid140_fpSinCosXTest_q;
--reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1(REG,643)@20
reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q <= join_uid141_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg(DELAY,1362)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q, xout => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem(DUALMEM,1363)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ia <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ia
);
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_q <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_iq(1 downto 0);
--fracRPostExcCos_uid142_fpSinCosXTest(MUX,141)@37
fracRPostExcCos_uid142_fpSinCosXTest_s <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_q;
fracRPostExcCos_uid142_fpSinCosXTest: PROCESS (fracRPostExcCos_uid142_fpSinCosXTest_s, en, reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q, cstAllZWF_uid7_fpSinCosXTest_q, cstNaNwF_uid32_fpSinCosXTest_q, cstNaNwF_uid32_fpSinCosXTest_q)
BEGIN
CASE fracRPostExcCos_uid142_fpSinCosXTest_s IS
WHEN "00" => fracRPostExcCos_uid142_fpSinCosXTest_q <= reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q;
WHEN "01" => fracRPostExcCos_uid142_fpSinCosXTest_q <= cstAllZWF_uid7_fpSinCosXTest_q;
WHEN "10" => fracRPostExcCos_uid142_fpSinCosXTest_q <= cstNaNwF_uid32_fpSinCosXTest_q;
WHEN "11" => fracRPostExcCos_uid142_fpSinCosXTest_q <= cstNaNwF_uid32_fpSinCosXTest_q;
WHEN OTHERS => fracRPostExcCos_uid142_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fpCos_uid162_fpSinCosXTest(BITJOIN,161)@37
fpCos_uid162_fpSinCosXTest_q <= ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c_q & expRPostExcCos_uid147_fpSinCosXTest_q & fracRPostExcCos_uid142_fpSinCosXTest_q;
--cstBiasMwShiftM2_uid25_fpSinCosXTest(CONSTANT,24)
cstBiasMwShiftM2_uid25_fpSinCosXTest_q <= "01110001";
--sinXIsXRR_uid41_fpSinCosXTest(COMPARE,40)@16
sinXIsXRR_uid41_fpSinCosXTest_cin <= GND_q;
sinXIsXRR_uid41_fpSinCosXTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid25_fpSinCosXTest_q) & '0';
sinXIsXRR_uid41_fpSinCosXTest_b <= STD_LOGIC_VECTOR((10 downto 8 => reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q(7)) & reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q) & sinXIsXRR_uid41_fpSinCosXTest_cin(0);
sinXIsXRR_uid41_fpSinCosXTest_o <= STD_LOGIC_VECTOR(SIGNED(sinXIsXRR_uid41_fpSinCosXTest_a) - SIGNED(sinXIsXRR_uid41_fpSinCosXTest_b));
sinXIsXRR_uid41_fpSinCosXTest_n(0) <= not sinXIsXRR_uid41_fpSinCosXTest_o(11);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a(DELAY,756)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsXRR_uid128_fpSinCosXTest(LOGICAL,127)@18
InvSinXIsXRR_uid128_fpSinCosXTest_a <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a_q;
InvSinXIsXRR_uid128_fpSinCosXTest_q <= not InvSinXIsXRR_uid128_fpSinCosXTest_a;
--signComp_uid129_fpSinCosXTest(LOGICAL,128)@18
signComp_uid129_fpSinCosXTest_a <= InvSinXIsXRR_uid128_fpSinCosXTest_q;
signComp_uid129_fpSinCosXTest_b <= InvSinXIsX_uid127_fpSinCosXTest_q;
signComp_uid129_fpSinCosXTest_c <= intXParity_uid49_fpSinCosXTest_b;
signComp_uid129_fpSinCosXTest_q <= signComp_uid129_fpSinCosXTest_a and signComp_uid129_fpSinCosXTest_b and signComp_uid129_fpSinCosXTest_c;
--signX_uid37_fpSinCosXTest(BITSELECT,36)@0
signX_uid37_fpSinCosXTest_in <= a;
signX_uid37_fpSinCosXTest_b <= signX_uid37_fpSinCosXTest_in(31 downto 31);
--ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a(DELAY,760)@0
ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => signX_uid37_fpSinCosXTest_b, xout => ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid130_fpSinCosXTest(LOGICAL,129)@18
signR_uid130_fpSinCosXTest_a <= ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a_q;
signR_uid130_fpSinCosXTest_b <= signComp_uid129_fpSinCosXTest_q;
signR_uid130_fpSinCosXTest_q <= signR_uid130_fpSinCosXTest_a xor signR_uid130_fpSinCosXTest_b;
--ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c(DELAY,766)@18
ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => signR_uid130_fpSinCosXTest_q, xout => ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--signRSinFull_uid133_fpSinCosXTest(LOGICAL,132)@20
signRSinFull_uid133_fpSinCosXTest_a <= InvExc_N_uid132_fpSinCosXTest_q;
signRSinFull_uid133_fpSinCosXTest_b <= InvExc_I_uid131_fpSinCosXTest_q;
signRSinFull_uid133_fpSinCosXTest_c <= ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c_q;
signRSinFull_uid133_fpSinCosXTest_q_i <= signRSinFull_uid133_fpSinCosXTest_a and signRSinFull_uid133_fpSinCosXTest_b and signRSinFull_uid133_fpSinCosXTest_c;
signRSinFull_uid133_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRSinFull_uid133_fpSinCosXTest_q, xin => signRSinFull_uid133_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c(DELAY,769)@21
ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => signRSinFull_uid133_fpSinCosXTest_q, xout => ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor(LOGICAL,1359)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_b <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_q <= not (ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_a or ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_b);
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top(CONSTANT,1342)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top_q <= "0100010";
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp(LOGICAL,1343)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_a <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q);
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_q <= "1" when ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_a = ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_b else "0";
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg(REG,1344)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena(REG,1360)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_q = "1") THEN
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd(LOGICAL,1361)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_a <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_b <= en;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_q <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_a and ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_b;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg(DELAY,1349)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => exp_uid9_fpSinCosXTest_b, xout => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt(COUNTER,1338)
-- every=1, low=0, high=34, step=1, init=1
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i = 33 THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i - 34;
ELSE
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i,6));
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg(REG,1339)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux(MUX,1340)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s, ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q, ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem(DUALMEM,1350)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ia <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_aa <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ab <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 6,
numwords_a => 35,
width_b => 8,
widthad_b => 6,
numwords_b => 35,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ia
);
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_iq(7 downto 0);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a(DELAY,1228)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1(REG,605)@35
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor(LOGICAL,1309)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_b <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_q <= not (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_a or ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_b);
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena(REG,1310)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_q = "1") THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd(LOGICAL,1311)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_a <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_b <= en;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_a and ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_b;
--oFracXRRSmallXRR_uid90_fpSinCosXTest(BITSELECT,89)@16
oFracXRRSmallXRR_uid90_fpSinCosXTest_in <= oFracXRR_uid43_uid43_fpSinCosXTest_q;
oFracXRRSmallXRR_uid90_fpSinCosXTest_b <= oFracXRRSmallXRR_uid90_fpSinCosXTest_in(53 downto 28);
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg(DELAY,1299)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => oFracXRRSmallXRR_uid90_fpSinCosXTest_b, xout => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem(DUALMEM,1300)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ia <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 4,
numwords_a => 14,
width_b => 26,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ia
);
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_iq(25 downto 0);
--reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1(REG,577)@20
reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q <= cmpYToOneMinusY_uid57_fpSinCosXTest_c;
END IF;
END IF;
END PROCESS;
--zSin_uid60_fpSinCosXTest(MUX,59)@21
zSin_uid60_fpSinCosXTest_s <= reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q;
zSin_uid60_fpSinCosXTest: PROCESS (zSin_uid60_fpSinCosXTest_s, en, reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q, reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q)
BEGIN
CASE zSin_uid60_fpSinCosXTest_s IS
WHEN "0" => zSin_uid60_fpSinCosXTest_q <= reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q;
WHEN "1" => zSin_uid60_fpSinCosXTest_q <= reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q;
WHEN OTHERS => zSin_uid60_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--addr_uid81_fpSinCosXTest(BITSELECT,80)@21
addr_uid81_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q;
addr_uid81_fpSinCosXTest_b <= addr_uid81_fpSinCosXTest_in(64 downto 57);
--reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0(REG,595)@21
reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q <= addr_uid81_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid398_tableGensinPiZ_lutmem(DUALMEM,529)@22
memoryC2_uid398_tableGensinPiZ_lutmem_ia <= (others => '0');
memoryC2_uid398_tableGensinPiZ_lutmem_aa <= (others => '0');
memoryC2_uid398_tableGensinPiZ_lutmem_ab <= reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q;
memoryC2_uid398_tableGensinPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC2_uid398_tableGensinPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid398_tableGensinPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid398_tableGensinPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid398_tableGensinPiZ_lutmem_iq,
address_a => memoryC2_uid398_tableGensinPiZ_lutmem_aa,
data_a => memoryC2_uid398_tableGensinPiZ_lutmem_ia
);
memoryC2_uid398_tableGensinPiZ_lutmem_reset0 <= areset;
memoryC2_uid398_tableGensinPiZ_lutmem_q <= memoryC2_uid398_tableGensinPiZ_lutmem_iq(12 downto 0);
--reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1(REG,597)@24
reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q <= memoryC2_uid398_tableGensinPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--zPsinPiZ_uid84_fpSinCosXTest(BITSELECT,83)@21
zPsinPiZ_uid84_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q(56 downto 0);
zPsinPiZ_uid84_fpSinCosXTest_b <= zPsinPiZ_uid84_fpSinCosXTest_in(56 downto 42);
--yT1_uid406_polyEvalsinPiZ(BITSELECT,405)@21
yT1_uid406_polyEvalsinPiZ_in <= zPsinPiZ_uid84_fpSinCosXTest_b;
yT1_uid406_polyEvalsinPiZ_b <= yT1_uid406_polyEvalsinPiZ_in(14 downto 2);
--ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg(DELAY,1540)
ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => yT1_uid406_polyEvalsinPiZ_b, xout => ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a(DELAY,1219)@21
ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg_q, xout => ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0(REG,596)@24
reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q <= ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid502_pT1_uid407_polyEvalsinPiZ(MULT,501)@25
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a),14)) * SIGNED(prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b);
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a <= (others => '0');
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b <= (others => '0');
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a <= reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q;
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b <= reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q;
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid502_pT1_uid407_polyEvalsinPiZ_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid502_pT1_uid407_polyEvalsinPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q <= prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ(BITSELECT,502)@28
prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_in <= prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q;
prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b <= prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_in(25 downto 12);
--highBBits_uid409_polyEvalsinPiZ(BITSELECT,408)@28
highBBits_uid409_polyEvalsinPiZ_in <= prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b;
highBBits_uid409_polyEvalsinPiZ_b <= highBBits_uid409_polyEvalsinPiZ_in(13 downto 1);
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a(DELAY,1221)@21
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => addr_uid81_fpSinCosXTest_b, xout => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0(REG,598)@24
reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid396_tableGensinPiZ_lutmem(DUALMEM,528)@25
memoryC1_uid396_tableGensinPiZ_lutmem_ia <= (others => '0');
memoryC1_uid396_tableGensinPiZ_lutmem_aa <= (others => '0');
memoryC1_uid396_tableGensinPiZ_lutmem_ab <= reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q;
memoryC1_uid396_tableGensinPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC1_uid396_tableGensinPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid396_tableGensinPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid396_tableGensinPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid396_tableGensinPiZ_lutmem_iq,
address_a => memoryC1_uid396_tableGensinPiZ_lutmem_aa,
data_a => memoryC1_uid396_tableGensinPiZ_lutmem_ia
);
memoryC1_uid396_tableGensinPiZ_lutmem_reset0 <= areset;
memoryC1_uid396_tableGensinPiZ_lutmem_q <= memoryC1_uid396_tableGensinPiZ_lutmem_iq(20 downto 0);
--reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0(REG,599)@27
reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q <= memoryC1_uid396_tableGensinPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid410_polyEvalsinPiZ(ADD,409)@28
sumAHighB_uid410_polyEvalsinPiZ_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q(20)) & reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q);
sumAHighB_uid410_polyEvalsinPiZ_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid409_polyEvalsinPiZ_b(12)) & highBBits_uid409_polyEvalsinPiZ_b);
sumAHighB_uid410_polyEvalsinPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid410_polyEvalsinPiZ_a) + SIGNED(sumAHighB_uid410_polyEvalsinPiZ_b));
sumAHighB_uid410_polyEvalsinPiZ_q <= sumAHighB_uid410_polyEvalsinPiZ_o(21 downto 0);
--lowRangeB_uid408_polyEvalsinPiZ(BITSELECT,407)@28
lowRangeB_uid408_polyEvalsinPiZ_in <= prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b(0 downto 0);
lowRangeB_uid408_polyEvalsinPiZ_b <= lowRangeB_uid408_polyEvalsinPiZ_in(0 downto 0);
--s1_uid408_uid411_polyEvalsinPiZ(BITJOIN,410)@28
s1_uid408_uid411_polyEvalsinPiZ_q <= sumAHighB_uid410_polyEvalsinPiZ_q & lowRangeB_uid408_polyEvalsinPiZ_b;
--reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1(REG,601)@28
reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q <= s1_uid408_uid411_polyEvalsinPiZ_q;
END IF;
END IF;
END PROCESS;
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor(LOGICAL,1551)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_b <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_q <= not (ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_a or ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_b);
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena(REG,1552)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_q = "1") THEN
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd(LOGICAL,1553)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_a <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_b <= en;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_q <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_a and ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_b;
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg(DELAY,1541)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => zPsinPiZ_uid84_fpSinCosXTest_b, xout => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem(DUALMEM,1542)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ia <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 3,
numwords_a => 5,
width_b => 15,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_iq,
address_a => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_aa,
data_a => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ia
);
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_reset0 <= areset;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_q <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_iq(14 downto 0);
--reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0(REG,600)@28
reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid505_pT2_uid413_polyEvalsinPiZ(MULT,504)@29
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a),16)) * SIGNED(prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b);
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a <= (others => '0');
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b <= (others => '0');
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a <= reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q;
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b <= reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q;
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid505_pT2_uid413_polyEvalsinPiZ_pr,38));
END IF;
END IF;
END PROCESS;
prodXY_uid505_pT2_uid413_polyEvalsinPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q <= prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ(BITSELECT,505)@32
prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_in <= prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q;
prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b <= prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_in(37 downto 14);
--highBBits_uid415_polyEvalsinPiZ(BITSELECT,414)@32
highBBits_uid415_polyEvalsinPiZ_in <= prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b;
highBBits_uid415_polyEvalsinPiZ_b <= highBBits_uid415_polyEvalsinPiZ_in(23 downto 2);
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor(LOGICAL,1564)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_b <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_q <= not (ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_a or ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_b);
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena(REG,1565)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_q = "1") THEN
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd(LOGICAL,1566)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_a <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_b <= en;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_a and ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_b;
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg(DELAY,1554)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addr_uid81_fpSinCosXTest_b, xout => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem(DUALMEM,1555)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ia <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_iq,
address_a => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_aa,
data_a => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ia
);
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0(REG,602)@28
reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid394_tableGensinPiZ_lutmem(DUALMEM,527)@29
memoryC0_uid394_tableGensinPiZ_lutmem_ia <= (others => '0');
memoryC0_uid394_tableGensinPiZ_lutmem_aa <= (others => '0');
memoryC0_uid394_tableGensinPiZ_lutmem_ab <= reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q;
memoryC0_uid394_tableGensinPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC0_uid394_tableGensinPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid394_tableGensinPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid394_tableGensinPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid394_tableGensinPiZ_lutmem_iq,
address_a => memoryC0_uid394_tableGensinPiZ_lutmem_aa,
data_a => memoryC0_uid394_tableGensinPiZ_lutmem_ia
);
memoryC0_uid394_tableGensinPiZ_lutmem_reset0 <= areset;
memoryC0_uid394_tableGensinPiZ_lutmem_q <= memoryC0_uid394_tableGensinPiZ_lutmem_iq(29 downto 0);
--reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0(REG,603)@31
reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q <= memoryC0_uid394_tableGensinPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid416_polyEvalsinPiZ(ADD,415)@32
sumAHighB_uid416_polyEvalsinPiZ_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q(29)) & reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q);
sumAHighB_uid416_polyEvalsinPiZ_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid415_polyEvalsinPiZ_b(21)) & highBBits_uid415_polyEvalsinPiZ_b);
sumAHighB_uid416_polyEvalsinPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid416_polyEvalsinPiZ_a) + SIGNED(sumAHighB_uid416_polyEvalsinPiZ_b));
sumAHighB_uid416_polyEvalsinPiZ_q <= sumAHighB_uid416_polyEvalsinPiZ_o(30 downto 0);
--lowRangeB_uid414_polyEvalsinPiZ(BITSELECT,413)@32
lowRangeB_uid414_polyEvalsinPiZ_in <= prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b(1 downto 0);
lowRangeB_uid414_polyEvalsinPiZ_b <= lowRangeB_uid414_polyEvalsinPiZ_in(1 downto 0);
--s2_uid414_uid417_polyEvalsinPiZ(BITJOIN,416)@32
s2_uid414_uid417_polyEvalsinPiZ_q <= sumAHighB_uid416_polyEvalsinPiZ_q & lowRangeB_uid414_polyEvalsinPiZ_b;
--polyEvalSigsinPiZ_uid86_fpSinCosXTest(BITSELECT,85)@32
polyEvalSigsinPiZ_uid86_fpSinCosXTest_in <= s2_uid414_uid417_polyEvalsinPiZ_q(30 downto 0);
polyEvalSigsinPiZ_uid86_fpSinCosXTest_b <= polyEvalSigsinPiZ_uid86_fpSinCosXTest_in(30 downto 5);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b(DELAY,708)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--multSinOp2_uid91_fpSinCosXTest(MUX,90)@32
multSinOp2_uid91_fpSinCosXTest_s <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b_q;
multSinOp2_uid91_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSinOp2_uid91_fpSinCosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE multSinOp2_uid91_fpSinCosXTest_s IS
WHEN "0" => multSinOp2_uid91_fpSinCosXTest_q <= polyEvalSigsinPiZ_uid86_fpSinCosXTest_b;
WHEN "1" => multSinOp2_uid91_fpSinCosXTest_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_q;
WHEN OTHERS => multSinOp2_uid91_fpSinCosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor(LOGICAL,1320)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_b <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_q <= not (ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_a or ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_b);
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena(REG,1321)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_q = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd(LOGICAL,1322)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_a <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_b <= en;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_a and ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_b;
--cPi_uid71_fpSinCosXTest(CONSTANT,70)
cPi_uid71_fpSinCosXTest_q <= "11001001000011111101101011";
--LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest(BITSELECT,309)@27
LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q(63 downto 0);
LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_in(63 downto 0);
--leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest(BITJOIN,310)@27
leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_b & GND_q;
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor(LOGICAL,1433)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_b <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_q <= not (ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_a or ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_b);
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena(REG,1434)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_q = "1") THEN
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd(LOGICAL,1435)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_a <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_b <= en;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_q <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_a and ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_b;
--X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest(BITSELECT,280)@21
X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q(32 downto 0);
X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b <= X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_in(32 downto 0);
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg(DELAY,1425)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem(DUALMEM,1426)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ia <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 33,
widthad_a => 1,
numwords_a => 2,
width_b => 33,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ia
);
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_q <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_iq(32 downto 0);
--leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest(BITJOIN,281)@25
leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_q & zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor(LOGICAL,1444)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_b <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_q <= not (ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_a or ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_b);
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena(REG,1445)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_q = "1") THEN
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd(LOGICAL,1446)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_a <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_b <= en;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_q <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_a and ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_b;
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg(DELAY,1436)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => zSin_uid60_fpSinCosXTest_q, xout => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem(DUALMEM,1437)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ia <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 65,
widthad_a => 1,
numwords_a => 2,
width_b => 65,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_iq,
address_a => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_aa,
data_a => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ia
);
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_reset0 <= areset;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_iq(64 downto 0);
--rVStage_uid237_lzcZSin_uid66_fpSinCosXTest(BITSELECT,236)@21
rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q;
rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_in(64 downto 1);
--vCount_uid238_lzcZSin_uid66_fpSinCosXTest(LOGICAL,237)@21
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_b <= zs_uid236_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_i <= "1" when vCount_uid238_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid238_lzcZSin_uid66_fpSinCosXTest_b else "0";
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q, xin => vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g(DELAY,903)@22
ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q, xout => ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid240_lzcZSin_uid66_fpSinCosXTest(BITSELECT,239)@21
vStage_uid240_lzcZSin_uid66_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q(0 downto 0);
vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid240_lzcZSin_uid66_fpSinCosXTest_in(0 downto 0);
--ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b(DELAY,861)@21
ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cStage_uid241_lzcZSin_uid66_fpSinCosXTest(BITJOIN,240)@22
cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q <= ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b_q & mO_uid239_lzcZSin_uid66_fpSinCosXTest_q;
--ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c(DELAY,863)@21
ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid243_lzcZSin_uid66_fpSinCosXTest(MUX,242)@22
vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid243_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s, en, ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q, cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q)
BEGIN
CASE vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q <= ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q <= cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q;
WHEN OTHERS => vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid245_lzcZSin_uid66_fpSinCosXTest(BITSELECT,244)@22
rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_in(63 downto 32);
--vCount_uid246_lzcZSin_uid66_fpSinCosXTest(LOGICAL,245)@22
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_b <= zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_i <= "1" when vCount_uid246_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid246_lzcZSin_uid66_fpSinCosXTest_b else "0";
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q, xin => vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f(DELAY,902)@23
ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q, xout => ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid247_lzcZSin_uid66_fpSinCosXTest(BITSELECT,246)@22
vStage_uid247_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q(31 downto 0);
vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid247_lzcZSin_uid66_fpSinCosXTest_in(31 downto 0);
--ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d(DELAY,870)@22
ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c(DELAY,869)@22
ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid249_lzcZSin_uid66_fpSinCosXTest(MUX,248)@23
vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid249_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s, en, ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q, ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q)
BEGIN
CASE vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q <= ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q <= ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q;
WHEN OTHERS => vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid251_lzcZSin_uid66_fpSinCosXTest(BITSELECT,250)@23
rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_in(31 downto 16);
--vCount_uid252_lzcZSin_uid66_fpSinCosXTest(LOGICAL,251)@23
vCount_uid252_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid252_lzcZSin_uid66_fpSinCosXTest_b <= zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid252_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid252_lzcZSin_uid66_fpSinCosXTest_b else "0";
--reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4(REG,585)@23
reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q <= vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e(DELAY,901)@24
ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q, xout => ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid253_lzcZSin_uid66_fpSinCosXTest(BITSELECT,252)@23
vStage_uid253_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q(15 downto 0);
vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid253_lzcZSin_uid66_fpSinCosXTest_in(15 downto 0);
--vStagei_uid255_lzcZSin_uid66_fpSinCosXTest(MUX,254)@23
vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid255_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s, en, rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b, vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q <= rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b;
WHEN "1" => vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q <= vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid257_lzcZSin_uid66_fpSinCosXTest(BITSELECT,256)@23
rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_in(15 downto 8);
--reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1(REG,580)@23
reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q <= rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid258_lzcZSin_uid66_fpSinCosXTest(LOGICAL,257)@24
vCount_uid258_lzcZSin_uid66_fpSinCosXTest_a <= reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q;
vCount_uid258_lzcZSin_uid66_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid258_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid258_lzcZSin_uid66_fpSinCosXTest_b else "0";
--ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d(DELAY,900)@24
ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q, xout => ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid259_lzcZSin_uid66_fpSinCosXTest(BITSELECT,258)@23
vStage_uid259_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q(7 downto 0);
vStage_uid259_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid259_lzcZSin_uid66_fpSinCosXTest_in(7 downto 0);
--reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3(REG,582)@23
reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q <= vStage_uid259_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid261_lzcZSin_uid66_fpSinCosXTest(MUX,260)@24
vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid261_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s, en, reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q, reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q <= reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q <= reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid263_lzcZSin_uid66_fpSinCosXTest(BITSELECT,262)@24
rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_in(7 downto 4);
--vCount_uid264_lzcZSin_uid66_fpSinCosXTest(LOGICAL,263)@24
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_b <= leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q_i <= "1" when vCount_uid264_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid264_lzcZSin_uid66_fpSinCosXTest_b else "0";
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q, xin => vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid265_lzcZSin_uid66_fpSinCosXTest(BITSELECT,264)@24
vStage_uid265_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q(3 downto 0);
vStage_uid265_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid265_lzcZSin_uid66_fpSinCosXTest_in(3 downto 0);
--reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3(REG,584)@24
reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q <= vStage_uid265_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2(REG,583)@24
reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q <= rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid267_lzcZSin_uid66_fpSinCosXTest(MUX,266)@25
vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid267_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s, en, reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q, reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q <= reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q <= reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid269_lzcZSin_uid66_fpSinCosXTest(BITSELECT,268)@25
rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_in(3 downto 2);
--vCount_uid270_lzcZSin_uid66_fpSinCosXTest(LOGICAL,269)@25
vCount_uid270_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid270_lzcZSin_uid66_fpSinCosXTest_b <= leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid270_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid270_lzcZSin_uid66_fpSinCosXTest_b else "0";
--vStage_uid271_lzcZSin_uid66_fpSinCosXTest(BITSELECT,270)@25
vStage_uid271_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q(1 downto 0);
vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid271_lzcZSin_uid66_fpSinCosXTest_in(1 downto 0);
--vStagei_uid273_lzcZSin_uid66_fpSinCosXTest(MUX,272)@25
vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid273_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s, en, rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b, vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q <= rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b;
WHEN "1" => vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q <= vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid275_lzcZSin_uid66_fpSinCosXTest(BITSELECT,274)@25
rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_in(1 downto 1);
--vCount_uid276_lzcZSin_uid66_fpSinCosXTest(LOGICAL,275)@25
vCount_uid276_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid276_lzcZSin_uid66_fpSinCosXTest_b <= GND_q;
vCount_uid276_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid276_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid276_lzcZSin_uid66_fpSinCosXTest_b else "0";
--r_uid277_lzcZSin_uid66_fpSinCosXTest(BITJOIN,276)@25
r_uid277_lzcZSin_uid66_fpSinCosXTest_q <= ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g_q & ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f_q & ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e_q & ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d_q & vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q & vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q & vCount_uid276_lzcZSin_uid66_fpSinCosXTest_q;
--leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest(BITSELECT,284)@25
leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q;
leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_in(6 downto 5);
--leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest(MUX,285)@25
leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s <= leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_b;
leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s, en, ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q, leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "10" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN "11" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest(BITSELECT,293)@25
LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q(40 downto 0);
LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_in(40 downto 0);
--leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest(BITJOIN,294)@25
leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_b & leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q;
--reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5(REG,590)@25
reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q <= leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest(BITSELECT,290)@25
LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q(48 downto 0);
LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_in(48 downto 0);
--leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest(BITJOIN,291)@25
leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_b & zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
--reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4(REG,589)@25
reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q <= leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest(BITSELECT,287)@25
LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q(56 downto 0);
LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_in(56 downto 0);
--leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest(BITJOIN,288)@25
leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3(REG,588)@25
reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q <= leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2(REG,587)@25
reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest(BITSELECT,295)@25
leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1(REG,586)@25
reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q <= leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest(MUX,296)@26
leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s <= reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q;
leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s, en, reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q, reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q, reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q, reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest(BITSELECT,304)@26
LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q(58 downto 0);
LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_in(58 downto 0);
--ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b(DELAY,927)@26
ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest(BITJOIN,305)@27
leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q <= ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b_q & leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q;
--LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest(BITSELECT,301)@26
LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q(60 downto 0);
LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_in(60 downto 0);
--ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b(DELAY,925)@26
ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest(BITJOIN,302)@27
leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q <= ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b_q & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest(BITSELECT,298)@26
LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q(62 downto 0);
LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_in(62 downto 0);
--ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b(DELAY,923)@26
ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest(BITJOIN,299)@27
leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q <= ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2(REG,592)@26
reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest(BITSELECT,306)@25
leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_in(2 downto 1);
--ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a(DELAY,1214)@25
ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1(REG,591)@26
reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q <= ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest(MUX,307)@27
leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s <= reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q;
leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s, en, reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q, leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q, leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q, leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "10" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "11" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest(BITSELECT,311)@25
leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b(DELAY,937)@25
ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest(MUX,312)@27
leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s <= ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b_q;
leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s, en, leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q, leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "0" => leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "1" => leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--pHigh_uid72_fpSinCosXTest(BITSELECT,71)@27
pHigh_uid72_fpSinCosXTest_in <= leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q;
pHigh_uid72_fpSinCosXTest_b <= pHigh_uid72_fpSinCosXTest_in(64 downto 39);
--reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2(REG,594)@27
reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q <= pHigh_uid72_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a(DELAY,1216)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1(REG,593)@27
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--p_uid73_fpSinCosXTest(MUX,72)@28
p_uid73_fpSinCosXTest_s <= reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q;
p_uid73_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p_uid73_fpSinCosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE p_uid73_fpSinCosXTest_s IS
WHEN "0" => p_uid73_fpSinCosXTest_q <= reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q;
WHEN "1" => p_uid73_fpSinCosXTest_q <= cPi_uid71_fpSinCosXTest_q;
WHEN OTHERS => p_uid73_fpSinCosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg(DELAY,1312)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => p_uid73_fpSinCosXTest_q, xout => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem(DUALMEM,1313)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ia <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 1,
numwords_a => 2,
width_b => 26,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_iq,
address_a => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_aa,
data_a => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ia
);
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_reset0 <= areset;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_iq(25 downto 0);
--mulSin_uid92_fpSinCosXTest(MULT,91)@33
mulSin_uid92_fpSinCosXTest_pr <= UNSIGNED(mulSin_uid92_fpSinCosXTest_a) * UNSIGNED(mulSin_uid92_fpSinCosXTest_b);
mulSin_uid92_fpSinCosXTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulSin_uid92_fpSinCosXTest_a <= (others => '0');
mulSin_uid92_fpSinCosXTest_b <= (others => '0');
mulSin_uid92_fpSinCosXTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulSin_uid92_fpSinCosXTest_a <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_q;
mulSin_uid92_fpSinCosXTest_b <= multSinOp2_uid91_fpSinCosXTest_q;
mulSin_uid92_fpSinCosXTest_s1 <= STD_LOGIC_VECTOR(mulSin_uid92_fpSinCosXTest_pr);
END IF;
END IF;
END PROCESS;
mulSin_uid92_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulSin_uid92_fpSinCosXTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulSin_uid92_fpSinCosXTest_q <= mulSin_uid92_fpSinCosXTest_s1;
END IF;
END IF;
END PROCESS;
--normBitSin_uid93_fpSinCosXTest(BITSELECT,92)@36
normBitSin_uid93_fpSinCosXTest_in <= mulSin_uid92_fpSinCosXTest_q;
normBitSin_uid93_fpSinCosXTest_b <= normBitSin_uid93_fpSinCosXTest_in(51 downto 51);
--join_uid99_fpSinCosXTest(BITJOIN,98)@36
join_uid99_fpSinCosXTest_q <= reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q & normBitSin_uid93_fpSinCosXTest_b;
--sinRndOp_uid100_uid101_fpSinCosXTest(BITJOIN,100)@36
sinRndOp_uid100_uid101_fpSinCosXTest_q <= join_uid99_fpSinCosXTest_q & cstAllZWF_uid7_fpSinCosXTest_q & VCC_q;
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor(LOGICAL,1333)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_b <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_q <= not (ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_a or ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_b);
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena(REG,1334)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_q = "1") THEN
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd(LOGICAL,1335)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_a <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_b <= en;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_q <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_a and ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_b;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor(LOGICAL,1283)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_b <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_q <= not (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_a or ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_b);
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena(REG,1284)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_q = "1") THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd(LOGICAL,1285)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_b <= en;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_a and ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_b;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg(DELAY,1273)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expXRR_uid38_fpSinCosXTest_b, xout => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem(DUALMEM,1274)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ia <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_aa <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ab <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 9,
width_b => 8,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ia
);
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_iq(7 downto 0);
--reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1(REG,604)@25
reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--expSinHC_uid74_fpSinCosXTest(SUB,73)@26
expSinHC_uid74_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_fpSinCosXTest_q);
expSinHC_uid74_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q);
expSinHC_uid74_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSinHC_uid74_fpSinCosXTest_a) - UNSIGNED(expSinHC_uid74_fpSinCosXTest_b));
expSinHC_uid74_fpSinCosXTest_q <= expSinHC_uid74_fpSinCosXTest_o(8 downto 0);
--expSinHCR_uid75_fpSinCosXTest(BITSELECT,74)@26
expSinHCR_uid75_fpSinCosXTest_in <= expSinHC_uid74_fpSinCosXTest_q(7 downto 0);
expSinHCR_uid75_fpSinCosXTest_b <= expSinHCR_uid75_fpSinCosXTest_in(7 downto 0);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b(DELAY,695)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expPSin_uid76_fpSinCosXTest(MUX,75)@26
expPSin_uid76_fpSinCosXTest_s <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b_q;
expPSin_uid76_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expPSin_uid76_fpSinCosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expPSin_uid76_fpSinCosXTest_s IS
WHEN "0" => expPSin_uid76_fpSinCosXTest_q <= expSinHCR_uid75_fpSinCosXTest_b;
WHEN "1" => expPSin_uid76_fpSinCosXTest_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_q;
WHEN OTHERS => expPSin_uid76_fpSinCosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg(DELAY,1323)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expPSin_uid76_fpSinCosXTest_q, xout => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem(DUALMEM,1324)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ia <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_aa <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ab <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 7,
width_b => 8,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ia
);
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_q <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_iq(7 downto 0);
--fracRSinPreRndHigh_uid95_fpSinCosXTest(BITSELECT,94)@36
fracRSinPreRndHigh_uid95_fpSinCosXTest_in <= mulSin_uid92_fpSinCosXTest_q(50 downto 0);
fracRSinPreRndHigh_uid95_fpSinCosXTest_b <= fracRSinPreRndHigh_uid95_fpSinCosXTest_in(50 downto 27);
--fracRSinPreRndLow_uid96_fpSinCosXTest(BITSELECT,95)@36
fracRSinPreRndLow_uid96_fpSinCosXTest_in <= mulSin_uid92_fpSinCosXTest_q(49 downto 0);
fracRSinPreRndLow_uid96_fpSinCosXTest_b <= fracRSinPreRndLow_uid96_fpSinCosXTest_in(49 downto 26);
--fracRSinPreRnd_uid97_fpSinCosXTest(MUX,96)@36
fracRSinPreRnd_uid97_fpSinCosXTest_s <= normBitSin_uid93_fpSinCosXTest_b;
fracRSinPreRnd_uid97_fpSinCosXTest: PROCESS (fracRSinPreRnd_uid97_fpSinCosXTest_s, en, fracRSinPreRndLow_uid96_fpSinCosXTest_b, fracRSinPreRndHigh_uid95_fpSinCosXTest_b)
BEGIN
CASE fracRSinPreRnd_uid97_fpSinCosXTest_s IS
WHEN "0" => fracRSinPreRnd_uid97_fpSinCosXTest_q <= fracRSinPreRndLow_uid96_fpSinCosXTest_b;
WHEN "1" => fracRSinPreRnd_uid97_fpSinCosXTest_q <= fracRSinPreRndHigh_uid95_fpSinCosXTest_b;
WHEN OTHERS => fracRSinPreRnd_uid97_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracRSinPreRnd_uid98_uid98_fpSinCosXTest(BITJOIN,97)@36
expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_q <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_q & fracRSinPreRnd_uid97_fpSinCosXTest_q;
--expFracRSin_uid102_fpSinCosXTest(ADD,101)@36
expFracRSin_uid102_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_q);
expFracRSin_uid102_fpSinCosXTest_b <= STD_LOGIC_VECTOR("0000000" & sinRndOp_uid100_uid101_fpSinCosXTest_q);
expFracRSin_uid102_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRSin_uid102_fpSinCosXTest_a) + UNSIGNED(expFracRSin_uid102_fpSinCosXTest_b));
expFracRSin_uid102_fpSinCosXTest_q <= expFracRSin_uid102_fpSinCosXTest_o(32 downto 0);
--expRCompSin_uid104_fpSinCosXTest(BITSELECT,103)@36
expRCompSin_uid104_fpSinCosXTest_in <= expFracRSin_uid102_fpSinCosXTest_q(31 downto 0);
expRCompSin_uid104_fpSinCosXTest_b <= expRCompSin_uid104_fpSinCosXTest_in(31 downto 24);
--reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2(REG,607)@36
reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q <= expRCompSin_uid104_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor(LOGICAL,1537)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_b <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_q <= not (ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_a or ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_b);
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena(REG,1538)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_q = "1") THEN
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd(LOGICAL,1539)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_a <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_b <= en;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_q <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_a and ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_b;
--expXIsZero_uid10_fpSinCosXTest(LOGICAL,9)@0
expXIsZero_uid10_fpSinCosXTest_a <= exp_uid9_fpSinCosXTest_b;
expXIsZero_uid10_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
expXIsZero_uid10_fpSinCosXTest_q <= "1" when expXIsZero_uid10_fpSinCosXTest_a = expXIsZero_uid10_fpSinCosXTest_b else "0";
--ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b(DELAY,746)@0
ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => expXIsZero_uid10_fpSinCosXTest_q, xout => ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excSelBitsSin_uid118_fpSinCosXTest(BITJOIN,117)@19
excSelBitsSin_uid118_fpSinCosXTest_q <= excRNaN_uid117_fpSinCosXTest_q & ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b_q & ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q;
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg(DELAY,1527)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => excSelBitsSin_uid118_fpSinCosXTest_q, xout => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem(DUALMEM,1528)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ia <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 4,
numwords_a => 14,
width_b => 3,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_iq,
address_a => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_aa,
data_a => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ia
);
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_reset0 <= areset;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_q <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_iq(2 downto 0);
--reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0(REG,533)@35
reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--excSelSin_uid119_fpSinCosXTest(LOOKUP,118)@36
excSelSin_uid119_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
excSelSin_uid119_fpSinCosXTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q) IS
WHEN "000" => excSelSin_uid119_fpSinCosXTest_q <= "00";
WHEN "001" => excSelSin_uid119_fpSinCosXTest_q <= "01";
WHEN "010" => excSelSin_uid119_fpSinCosXTest_q <= "10";
WHEN "011" => excSelSin_uid119_fpSinCosXTest_q <= "10";
WHEN "100" => excSelSin_uid119_fpSinCosXTest_q <= "11";
WHEN "101" => excSelSin_uid119_fpSinCosXTest_q <= "11";
WHEN "110" => excSelSin_uid119_fpSinCosXTest_q <= "00";
WHEN "111" => excSelSin_uid119_fpSinCosXTest_q <= "00";
WHEN OTHERS =>
excSelSin_uid119_fpSinCosXTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRPostExcSin_uid126_fpSinCosXTest(MUX,125)@37
expRPostExcSin_uid126_fpSinCosXTest_s <= excSelSin_uid119_fpSinCosXTest_q;
expRPostExcSin_uid126_fpSinCosXTest: PROCESS (expRPostExcSin_uid126_fpSinCosXTest_s, en, reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q, ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q, cstAllZWE_uid8_fpSinCosXTest_q, cstAllOWE_uid6_fpSinCosXTest_q)
BEGIN
CASE expRPostExcSin_uid126_fpSinCosXTest_s IS
WHEN "00" => expRPostExcSin_uid126_fpSinCosXTest_q <= reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q;
WHEN "01" => expRPostExcSin_uid126_fpSinCosXTest_q <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q;
WHEN "10" => expRPostExcSin_uid126_fpSinCosXTest_q <= cstAllZWE_uid8_fpSinCosXTest_q;
WHEN "11" => expRPostExcSin_uid126_fpSinCosXTest_q <= cstAllOWE_uid6_fpSinCosXTest_q;
WHEN OTHERS => expRPostExcSin_uid126_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor(LOGICAL,1346)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_b <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_q <= not (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_a or ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_b);
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena(REG,1347)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_q = "1") THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd(LOGICAL,1348)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_a <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_b <= en;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_a and ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_b;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg(DELAY,1336)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => frac_uid13_fpSinCosXTest_b, xout => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem(DUALMEM,1337)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ia <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_aa <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ab <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 6,
numwords_a => 35,
width_b => 23,
widthad_b => 6,
numwords_b => 35,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ia
);
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_iq(22 downto 0);
--fracRCompSin_uid103_fpSinCosXTest(BITSELECT,102)@36
fracRCompSin_uid103_fpSinCosXTest_in <= expFracRSin_uid102_fpSinCosXTest_q(23 downto 0);
fracRCompSin_uid103_fpSinCosXTest_b <= fracRCompSin_uid103_fpSinCosXTest_in(23 downto 1);
--reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2(REG,606)@36
reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q <= fracRCompSin_uid103_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--fracRPostExcSin_uid122_fpSinCosXTest(MUX,121)@37
fracRPostExcSin_uid122_fpSinCosXTest_s <= excSelSin_uid119_fpSinCosXTest_q;
fracRPostExcSin_uid122_fpSinCosXTest: PROCESS (fracRPostExcSin_uid122_fpSinCosXTest_s, en, reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q, ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q, cstAllZWF_uid7_fpSinCosXTest_q, cstNaNwF_uid32_fpSinCosXTest_q)
BEGIN
CASE fracRPostExcSin_uid122_fpSinCosXTest_s IS
WHEN "00" => fracRPostExcSin_uid122_fpSinCosXTest_q <= reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q;
WHEN "01" => fracRPostExcSin_uid122_fpSinCosXTest_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q;
WHEN "10" => fracRPostExcSin_uid122_fpSinCosXTest_q <= cstAllZWF_uid7_fpSinCosXTest_q;
WHEN "11" => fracRPostExcSin_uid122_fpSinCosXTest_q <= cstNaNwF_uid32_fpSinCosXTest_q;
WHEN OTHERS => fracRPostExcSin_uid122_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fpSin_uid134_fpSinCosXTest(BITJOIN,133)@37
fpSin_uid134_fpSinCosXTest_q <= ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c_q & expRPostExcSin_uid126_fpSinCosXTest_q & fracRPostExcSin_uid122_fpSinCosXTest_q;
--xOut(GPOUT,4)@37
s <= fpSin_uid134_fpSinCosXTest_q;
c <= fpCos_uid162_fpSinCosXTest_q;
end normal;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
bin_Gray_Processing/ip/Gray_Processing/hcc_neg2x.vhd
|
10
|
2843
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NEG2X.VHD ***
--*** ***
--*** Function: Negation (for unary -ve) ***
--*** ***
--*** 13/03/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_neg2x IS
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_neg2x;
ARCHITECTURE rtl OF hcc_neg2x IS
signal aaff : STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
signal aasatff, aazipff : STD_LOGIC;
BEGIN
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64+13*xoutput+3*funcoutput LOOP
aaff(k) <= '0';
END LOOP;
aasatff <= '0';
aazipff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
aasatff <= aasat;
aazipff <= aazip;
END IF;
END IF;
END PROCESS;
goa: IF (ieeeoutput = 1) GENERATE
cc(64) <= NOT(aaff(64));
cc(63 DOWNTO 1) <= aaff(63 DOWNTO 1);
ccsat <= '0';
cczip <= '0';
END GENERATE;
gob: IF (xoutput = 1) GENERATE
gxa: FOR k IN 14 TO 77 GENERATE
cc(k) <= NOT(aaff(k));
END GENERATE;
cc(13 DOWNTO 1) <= aaff(13 DOWNTO 1);
ccsat <= aasatff;
cczip <= aazipff;
END GENERATE;
goc: IF (funcoutput = 1) GENERATE
cc(67) <= NOT(aaff(67));
cc(66 DOWNTO 1) <= aaff(66 DOWNTO 1);
ccsat <= aasatff;
cczip <= aazipff;
END GENERATE;
END rtl;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
Gray_Processing/ip/Gray_Processing/hcc_rsftcomb36.vhd
|
10
|
4152
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTCOMB36.VHD ***
--*** ***
--*** Function: Combinatorial arithmetic right ***
--*** shift for a 36 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END hcc_rsftcomb36;
ARCHITECTURE rtl OF hcc_rsftcomb36 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 33 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(34) <= (levzip(34) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(35) AND NOT(shift(2)) AND shift(1)) OR
(levzip(36) AND shift(2));
levone(35) <= (levzip(35) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(36) AND ((shift(2)) OR shift(1)));
levone(36) <= levzip(36);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 24 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 25 TO 28 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(36) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 29 TO 32 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(36) AND shift(4));
END GENERATE;
gbd: FOR k IN 33 TO 35 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(36) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(36) <= levone(36);
gca: FOR k IN 1 TO 4 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k+32) AND shift(6));
END GENERATE;
gcb: FOR k IN 5 TO 20 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(36) AND shift(6));
END GENERATE;
gcc: FOR k IN 21 TO 35 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(36) AND (shift(6) OR shift(5)));
END GENERATE;
levthr(36) <= levtwo(36);
outbus <= levthr;
END rtl;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
bin_Gray_Processing/ip/Gray_Processing/hcc_castftox.vhd
|
10
|
6574
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTFTOX.VHD ***
--*** ***
--*** Function: Cast IEEE754 Single to Internal ***
--*** Single ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 06/02/08 - divider mantissa aa to aaff ***
--*** 13/07/09 - if zip, then zero '1' in frac ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castftox IS
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_castftox;
ARCHITECTURE rtl OF hcc_castftox IS
signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal ccff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal fracnode, fractional : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal expnode, exponent : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal satnode, zipnode : STD_LOGIC;
signal satff, zipff : STD_LOGIC;
BEGIN
-- ieee754: sign (32), 8 exponent (31:24), 23 mantissa (23:1)
-- x format: (signx5,!sign,mantissa XOR sign, sign(xx.xx)), exponent(10:1)
-- multiplier : (SIGN)('1')(23:1)sign(xx.xx), exponent(10:1)
-- divider : "01"(23:1) (00..00),exponent(10:1) (lower mantissa bits ignored by fpdiv1x)
gza: IF (roundconvert = 1) GENERATE
gza: FOR k IN 1 TO mantissa-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
END GENERATE;
pca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 32 LOOP
aaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
END IF;
END IF;
END PROCESS;
gro: IF ((target = 0 AND outputpipe = 1) OR
(target = 1 AND outputpipe = 1)) GENERATE
pca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
ccff(k) <= '0';
END LOOP;
satff <= '0';
zipff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
ccff <= fractional & exponent;
satff <= satnode;
zipff <= zipnode;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- if exponent = 255 => saturate, if 0 => 0
satnode <= aaff(31) AND aaff(30) AND aaff(29) AND aaff(28) AND
aaff(27) AND aaff(26) AND aaff(25) AND aaff(24);
zipnode <= NOT(aaff(31) OR aaff(30) OR aaff(29) OR aaff(28) OR
aaff(27) OR aaff(26) OR aaff(25) OR aaff(24));
gexpa: FOR k IN 1 TO 8 GENERATE
expnode(k) <= (aaff(k+23) OR satnode) AND NOT(zipnode);
END GENERATE;
expnode(9) <= satnode;
expnode(10) <= '0';
--*** internal format ***
gxa: IF (target = 0) GENERATE
fracnode(mantissa) <= aaff(32);
fracnode(mantissa-1) <= aaff(32);
fracnode(mantissa-2) <= aaff(32);
fracnode(mantissa-3) <= aaff(32);
fracnode(mantissa-4) <= aaff(32);
--fracnode(mantissa-5) <= NOT(aaff(32)); -- '1' XOR sign
-- 13/07/09
fracnode(mantissa-5) <= aaff(32) XOR NOT(zipnode); -- '1' XOR sign
gxb: FOR k IN 1 TO 23 GENERATE
fracnode(mantissa-29+k)<= (aaff(k) XOR aaff(32));
END GENERATE;
gxc: FOR k IN 1 TO mantissa-29 GENERATE
fracnode(k)<= aaff(32); -- '0' XOR sign
END GENERATE;
gxd: IF (roundconvert = 0) GENERATE
fractional <= fracnode;
END GENERATE;
gxe: IF (roundconvert = 1) GENERATE
fractional <= fracnode + (zerovec(mantissa-1) & aaff(32));
END GENERATE;
exponent <= expnode;
END GENERATE;
--*** direct to multiplier ***
gma: IF (target = 1) GENERATE
fracnode(mantissa) <= aaff(32);
--fracnode(mantissa-1) <= NOT(aaff(32)); -- '1' XOR sign
-- 13/07/09
fracnode(mantissa-1) <= aaff(32) XOR NOT(zipnode);
gmb: FOR k IN 1 TO 23 GENERATE
fracnode(mantissa-25+k)<= (aaff(k) XOR aaff(32));
END GENERATE;
gmc: FOR k IN 1 TO mantissa-25 GENERATE
fracnode(k)<= aaff(32); -- '0' XOR sign
END GENERATE;
gmd: IF (roundconvert = 0) GENERATE
fractional <= fracnode;
END GENERATE;
gme: IF (roundconvert = 1) GENERATE
fractional <= fracnode + (zerovec(mantissa-1) & aaff(32));
END GENERATE;
--***??? adjust ???
exponent <= expnode;
END GENERATE;
-- never register output
--*** direct to divider ***
gda: IF (target = 2) GENERATE
fracnode(mantissa) <= aaff(32);
-- 13/07/09
fracnode(mantissa-1) <= '1' AND NOT(zipnode);
fracnode(mantissa-2 DOWNTO mantissa-24)<= aaff(23 DOWNTO 1);
gfb: FOR k IN 1 TO mantissa-25 GENERATE
fracnode(k)<= '0';
END GENERATE;
fractional <= fracnode;
--***??? adjust ???
exponent <= expnode;
END GENERATE;
--*** OUTPUTS ***
goa: IF ((target = 0 AND outputpipe = 1) OR
(target = 1 AND outputpipe = 1)) GENERATE
cc <= ccff;
ccsat <= satff;
cczip <= zipff;
END GENERATE;
gob: IF ((target = 0 AND outputpipe = 0) OR
(target = 1 AND outputpipe = 0) OR
(target = 2)) GENERATE
cc <= fractional & exponent;
ccsat <= satnode;
cczip <= zipnode;
END GENERATE;
END rtl;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
Gray_Processing/ip/Gray_Processing/dp_divnornd.vhd
|
10
|
5286
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION DIVIDER - OUTPUT STAGE ***
--*** ***
--*** DP_DIVNORND.VHD ***
--*** ***
--*** Function: Output Stage, No Rounding ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: Latency = 1 ***
--***************************************************
ENTITY dp_divnornd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentdiv : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
mantissadiv : IN STD_LOGIC_VECTOR (53 DOWNTO 1); -- includes roundbit
nanin : IN STD_LOGIC;
dividebyzeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
END dp_divnornd;
ARCHITECTURE rtl OF dp_divnornd IS
constant expwidth : positive := 11;
constant manwidth : positive := 52;
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth-1 DOWNTO 1);
signal signff : STD_LOGIC;
signal nanff : STD_LOGIC;
signal dividebyzeroff : STD_LOGIC;
signal mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal exponentff : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal infinitygen : STD_LOGIC_VECTOR (expwidth+1 DOWNTO 1);
signal zerogen : STD_LOGIC_VECTOR (expwidth+1 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO manwidth-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signff <= '0';
nanff <= '0';
dividebyzeroff <= '0';
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponentff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
signff <= signin;
nanff <= nanin;
dividebyzeroff <= dividebyzeroin;
-- nan takes precedence (set max)
-- nan takes precedence (set max)
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= (mantissadiv(k+1) AND setmanzero) OR setmanmax;
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponentff(k) <= (exponentdiv(k) AND setexpzero) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- infinity if exponent >= 255
infinitygen(1) <= exponentdiv(1);
gia: FOR k IN 2 TO expwidth GENERATE
infinitygen(k) <= infinitygen(k-1) AND exponentdiv(k);
END GENERATE;
infinitygen(expwidth+1) <= infinitygen(expwidth) OR
(exponentdiv(expwidth+1) AND
NOT(exponentdiv(expwidth+2))); -- ;1' if infinity
-- zero if exponent <= 0
zerogen(1) <= exponentdiv(1);
gza: FOR k IN 2 TO expwidth GENERATE
zerogen(k) <= zerogen(k-1) OR exponentdiv(k);
END GENERATE;
zerogen(expwidth+1) <= zerogen(expwidth) AND
NOT(exponentdiv(expwidth+2)); -- '0' if zero
-- set mantissa to 0 when infinity or zero condition
setmanzero <= NOT(infinitygen(expwidth+1)) AND zerogen(expwidth+1) AND NOT(dividebyzeroin);
-- setmantissa to "11..11" when nan
setmanmax <= nanin;
-- set exponent to 0 when zero condition
setexpzero <= zerogen(expwidth+1);
-- set exponent to "11..11" when nan, infinity, or divide by 0
setexpmax <= nanin OR infinitygen(expwidth+1) OR dividebyzeroin;
--***************
--*** OUTPUTS ***
--***************
signout <= signff;
mantissaout <= mantissaff;
exponentout <= exponentff(expwidth DOWNTO 1);
-----------------------------------------------
nanout <= nanff;
invalidout <= nanff;
dividebyzeroout <= dividebyzeroff;
END rtl;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
Gray_Processing/ip/Gray_Processing/hcc_mul54uss.vhd
|
10
|
11101
|
LIBRARY ieee;
LIBRARY work;
LIBRARY lpm;
USE lpm.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL54USS.VHD ***
--*** ***
--*** Function: 6 pipeline stage unsigned 54 ***
--*** bit multiplier (synthesizable) ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul54uss IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_mul54uss;
ARCHITECTURE syn of hcc_mul54uss IS
signal muloneaa, mulonebb : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multwoaa, multwobb, multhraa, multhrbb : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal mulforaa, mulforbb, mulfivaa, mulfivbb : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal mulsixaa, mulsixbb : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal muloneout : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal multwoout, multhrout, mulforout, mulfivout, mulsixout : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal vecone, vectwo, vecthr, vecfor, vecfiv : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal vecsix, vecsev, vecegt, vecnin, vecten : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumvecone, carvecone : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumvectwo, carvectwo : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumvecthr, carvecthr : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumoneff, caroneff : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumtwoff, cartwoff : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal resultnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
component altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (width_b-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (width_result-1 DOWNTO 0)
);
end component;
-- identical component to that above, but fixed at 18x18, latency 2
-- mul18usus generated by Quartus
component hcc_mul18usus
PORT
(
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
end component;
COMPONENT lpm_add_sub
GENERIC (
lpm_direction : STRING;
lpm_hint : STRING;
lpm_pipeline : NATURAL;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
clken : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
BEGIN
gza: FOR k IN 1 TO 36 GENERATE
zerovec(k) <= '0';
END GENERATE;
muloneaa <= mulaa(36 DOWNTO 1);
mulonebb <= mulbb(36 DOWNTO 1);
multwoaa <= mulaa(54 DOWNTO 37);
multwobb <= mulbb(18 DOWNTO 1);
multhraa <= mulaa(54 DOWNTO 37);
multhrbb <= mulbb(36 DOWNTO 19);
mulforaa <= mulbb(54 DOWNTO 37);
mulforbb <= mulaa(18 DOWNTO 1);
mulfivaa <= mulbb(54 DOWNTO 37);
mulfivbb <= mulaa(36 DOWNTO 19);
mulsixaa <= mulbb(54 DOWNTO 37);
mulsixbb <= mulaa(54 DOWNTO 37);
-- {C,A) * {D,B}
-- CAA
-- DBB
-- AA*BB 36x36=72, latency 3
mulone : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 36,
width_b => 36,
width_result => 72
)
PORT MAP (
dataa => muloneaa,
datab => mulonebb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => muloneout
);
-- Blo*C 18*18 = 36, latency = 2
multwo: hcc_mul18usus
PORT MAP (
dataa_0 => multwoaa,
datab_0 => multwobb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => multwoout
);
-- Bhi*C 18*18 = 36, latency = 2
multhr: hcc_mul18usus
PORT MAP (
dataa_0 => multhraa,
datab_0 => multhrbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => multhrout
);
-- Alo*D 18*18 = 36, latency = 2
mulfor: hcc_mul18usus
PORT MAP (
dataa_0 => mulforaa,
datab_0 => mulforbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulforout
);
-- Ahi*D 18*18 = 36, latency = 2
mulfiv: hcc_mul18usus
PORT MAP (
dataa_0 => mulfivaa,
datab_0 => mulfivbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulfivout
);
-- C*D 18*18 = 36, latency = 3
mulsix : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 18,
width_b => 18,
width_result => 36
)
PORT MAP (
dataa => mulsixaa,
datab => mulsixbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulsixout
);
vecone <= zerovec(36 DOWNTO 1) & multwoout;
vectwo <= zerovec(18 DOWNTO 1) & multhrout & zerovec(18 DOWNTO 1);
vecthr <= zerovec(36 DOWNTO 1) & mulforout;
vecfor <= zerovec(18 DOWNTO 1) & mulfivout & zerovec(18 DOWNTO 1);
gva: FOR k IN 1 TO 72 GENERATE
sumvecone(k) <= vecone(k) XOR vectwo(k) XOR vecthr(k);
carvecone(k) <= (vecone(k) AND vectwo(k)) OR
(vectwo(k) AND vecthr(k)) OR
(vecone(k) AND vecthr(k));
END GENERATE;
vecfiv <= vecfor;
vecsix <= sumvecone;
vecsev <= carvecone(71 DOWNTO 1) & '0';
gvb: FOR k IN 1 TO 72 GENERATE
sumvectwo(k) <= vecfiv(k) XOR vecsix(k) XOR vecsev(k);
carvectwo(k) <= (vecfiv(k) AND vecsix(k)) OR
(vecsix(k) AND vecsev(k)) OR
(vecfiv(k) AND vecsev(k));
END GENERATE;
paa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 72 LOOP
sumoneff(k) <= '0';
caroneff(k) <= '0';
sumtwoff(k) <= '0';
cartwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
sumoneff <= sumvectwo;
caroneff <= carvectwo(71 DOWNTO 1) & '0';
sumtwoff <= sumvecthr;
cartwoff <= carvecthr(71 DOWNTO 1) & '0';
END IF;
END IF;
END PROCESS;
vecegt <= sumoneff;
vecnin <= caroneff;
vecten <= mulsixout & muloneout(72 DOWNTO 37);
gvc: FOR k IN 1 TO 72 GENERATE
sumvecthr(k) <= vecegt(k) XOR vecnin(k) XOR vecten(k);
carvecthr(k) <= (vecegt(k) AND vecnin(k)) OR
(vecnin(k) AND vecten(k)) OR
(vecegt(k) AND vecten(k));
END GENERATE;
-- according to marcel, 2 pipes = 1 pipe in middle, on on output
adder : lpm_add_sub
GENERIC MAP (
lpm_direction => "ADD",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO",
lpm_pipeline => 2,
lpm_type => "LPM_ADD_SUB",
lpm_width => 64
)
PORT MAP (
dataa => sumtwoff(72 DOWNTO 9),
datab => cartwoff(72 DOWNTO 9),
clken => enable,
aclr => reset,
clock => sysclk,
result => resultnode
);
mulcc <= resultnode;
END syn;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
bin_Gray_Processing/ip/Gray_Processing/hcc_mul2727s_sv.vhd
|
10
|
2171
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL2727S.VHD ***
--*** ***
--*** Function: 2 pipeline stage signed 27 bit ***
--*** SV(behavioral/synthesizable) ***
--*** ***
--*** 30/10/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul2727s IS
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
END hcc_mul2727s;
ARCHITECTURE rtl OF hcc_mul2727s IS
signal aaff, bbff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal multiplyff : STD_LOGIC_VECTOR (2*width DOWNTO 1);
BEGIN
pma: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
aaff(k) <= '0';
bbff(k) <= '0';
END LOOP;
FOR k IN 1 TO 2*width LOOP
multiplyff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
bbff <= bb;
multiplyff <= aaff * bbff;
END IF;
END IF;
END PROCESS;
cc <= multiplyff;
END rtl;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
Gray_Processing/ip/Gray_Processing/dotp_core_sv.vhd
|
10
|
13923
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hdatain_b__package.all;
--USE work.hdatain_b__library_package.all;
--**********************************************
--*** ***
--*** Generated by Floating Point Compiler ***
--*** ***
--*** Copyright Altera Corporation 2008 ***
--*** ***
--*** ***
--*** Version 2008.2X - April 24,2008 ***
--*** Testing Version Only - ***
--*** Stratix V DSP Benchmarking ***
--*** ***
--**********************************************
ENTITY dotp_core_sv IS
PORT(
clock : IN STD_LOGIC;
resetn : IN STD_LOGIC;
valid_in : IN STD_LOGIC;
valid_out : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(32 DOWNTO 1);
a0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1)
);
END dotp_core_sv;
ARCHITECTURE gen OF dotp_core_sv IS
COMPONENT dotProduct64_dut is
port (
c_s : in std_logic_vector(7 downto 0);
cout_s : out std_logic_vector(7 downto 0);
datain_a_00 : in std_logic_vector(31 downto 0);
datain_a_01 : in std_logic_vector(31 downto 0);
datain_a_02 : in std_logic_vector(31 downto 0);
datain_a_03 : in std_logic_vector(31 downto 0);
datain_a_04 : in std_logic_vector(31 downto 0);
datain_a_05 : in std_logic_vector(31 downto 0);
datain_a_06 : in std_logic_vector(31 downto 0);
datain_a_07 : in std_logic_vector(31 downto 0);
datain_a_08 : in std_logic_vector(31 downto 0);
datain_a_09 : in std_logic_vector(31 downto 0);
datain_a_10 : in std_logic_vector(31 downto 0);
datain_a_11 : in std_logic_vector(31 downto 0);
datain_a_12 : in std_logic_vector(31 downto 0);
datain_a_13 : in std_logic_vector(31 downto 0);
datain_a_14 : in std_logic_vector(31 downto 0);
datain_a_15 : in std_logic_vector(31 downto 0);
datain_a_16 : in std_logic_vector(31 downto 0);
datain_a_17 : in std_logic_vector(31 downto 0);
datain_a_18 : in std_logic_vector(31 downto 0);
datain_a_19 : in std_logic_vector(31 downto 0);
datain_a_20 : in std_logic_vector(31 downto 0);
datain_a_21 : in std_logic_vector(31 downto 0);
datain_a_22 : in std_logic_vector(31 downto 0);
datain_a_23 : in std_logic_vector(31 downto 0);
datain_a_24 : in std_logic_vector(31 downto 0);
datain_a_25 : in std_logic_vector(31 downto 0);
datain_a_26 : in std_logic_vector(31 downto 0);
datain_a_27 : in std_logic_vector(31 downto 0);
datain_a_28 : in std_logic_vector(31 downto 0);
datain_a_29 : in std_logic_vector(31 downto 0);
datain_a_30 : in std_logic_vector(31 downto 0);
datain_a_31 : in std_logic_vector(31 downto 0);
datain_a_32 : in std_logic_vector(31 downto 0);
datain_a_33 : in std_logic_vector(31 downto 0);
datain_a_34 : in std_logic_vector(31 downto 0);
datain_a_35 : in std_logic_vector(31 downto 0);
datain_a_36 : in std_logic_vector(31 downto 0);
datain_a_37 : in std_logic_vector(31 downto 0);
datain_a_38 : in std_logic_vector(31 downto 0);
datain_a_39 : in std_logic_vector(31 downto 0);
datain_a_40 : in std_logic_vector(31 downto 0);
datain_a_41 : in std_logic_vector(31 downto 0);
datain_a_42 : in std_logic_vector(31 downto 0);
datain_a_43 : in std_logic_vector(31 downto 0);
datain_a_44 : in std_logic_vector(31 downto 0);
datain_a_45 : in std_logic_vector(31 downto 0);
datain_a_46 : in std_logic_vector(31 downto 0);
datain_a_47 : in std_logic_vector(31 downto 0);
datain_a_48 : in std_logic_vector(31 downto 0);
datain_a_49 : in std_logic_vector(31 downto 0);
datain_a_50 : in std_logic_vector(31 downto 0);
datain_a_51 : in std_logic_vector(31 downto 0);
datain_a_52 : in std_logic_vector(31 downto 0);
datain_a_53 : in std_logic_vector(31 downto 0);
datain_a_54 : in std_logic_vector(31 downto 0);
datain_a_55 : in std_logic_vector(31 downto 0);
datain_a_56 : in std_logic_vector(31 downto 0);
datain_a_57 : in std_logic_vector(31 downto 0);
datain_a_58 : in std_logic_vector(31 downto 0);
datain_a_59 : in std_logic_vector(31 downto 0);
datain_a_60 : in std_logic_vector(31 downto 0);
datain_a_61 : in std_logic_vector(31 downto 0);
datain_a_62 : in std_logic_vector(31 downto 0);
datain_a_63 : in std_logic_vector(31 downto 0);
datain_b_00 : in std_logic_vector(31 downto 0);
datain_b_01 : in std_logic_vector(31 downto 0);
datain_b_02 : in std_logic_vector(31 downto 0);
datain_b_03 : in std_logic_vector(31 downto 0);
datain_b_04 : in std_logic_vector(31 downto 0);
datain_b_05 : in std_logic_vector(31 downto 0);
datain_b_06 : in std_logic_vector(31 downto 0);
datain_b_07 : in std_logic_vector(31 downto 0);
datain_b_08 : in std_logic_vector(31 downto 0);
datain_b_09 : in std_logic_vector(31 downto 0);
datain_b_10 : in std_logic_vector(31 downto 0);
datain_b_11 : in std_logic_vector(31 downto 0);
datain_b_12 : in std_logic_vector(31 downto 0);
datain_b_13 : in std_logic_vector(31 downto 0);
datain_b_14 : in std_logic_vector(31 downto 0);
datain_b_15 : in std_logic_vector(31 downto 0);
datain_b_16 : in std_logic_vector(31 downto 0);
datain_b_17 : in std_logic_vector(31 downto 0);
datain_b_18 : in std_logic_vector(31 downto 0);
datain_b_19 : in std_logic_vector(31 downto 0);
datain_b_20 : in std_logic_vector(31 downto 0);
datain_b_21 : in std_logic_vector(31 downto 0);
datain_b_22 : in std_logic_vector(31 downto 0);
datain_b_23 : in std_logic_vector(31 downto 0);
datain_b_24 : in std_logic_vector(31 downto 0);
datain_b_25 : in std_logic_vector(31 downto 0);
datain_b_26 : in std_logic_vector(31 downto 0);
datain_b_27 : in std_logic_vector(31 downto 0);
datain_b_28 : in std_logic_vector(31 downto 0);
datain_b_29 : in std_logic_vector(31 downto 0);
datain_b_30 : in std_logic_vector(31 downto 0);
datain_b_31 : in std_logic_vector(31 downto 0);
datain_b_32 : in std_logic_vector(31 downto 0);
datain_b_33 : in std_logic_vector(31 downto 0);
datain_b_34 : in std_logic_vector(31 downto 0);
datain_b_35 : in std_logic_vector(31 downto 0);
datain_b_36 : in std_logic_vector(31 downto 0);
datain_b_37 : in std_logic_vector(31 downto 0);
datain_b_38 : in std_logic_vector(31 downto 0);
datain_b_39 : in std_logic_vector(31 downto 0);
datain_b_40 : in std_logic_vector(31 downto 0);
datain_b_41 : in std_logic_vector(31 downto 0);
datain_b_42 : in std_logic_vector(31 downto 0);
datain_b_43 : in std_logic_vector(31 downto 0);
datain_b_44 : in std_logic_vector(31 downto 0);
datain_b_45 : in std_logic_vector(31 downto 0);
datain_b_46 : in std_logic_vector(31 downto 0);
datain_b_47 : in std_logic_vector(31 downto 0);
datain_b_48 : in std_logic_vector(31 downto 0);
datain_b_49 : in std_logic_vector(31 downto 0);
datain_b_50 : in std_logic_vector(31 downto 0);
datain_b_51 : in std_logic_vector(31 downto 0);
datain_b_52 : in std_logic_vector(31 downto 0);
datain_b_53 : in std_logic_vector(31 downto 0);
datain_b_54 : in std_logic_vector(31 downto 0);
datain_b_55 : in std_logic_vector(31 downto 0);
datain_b_56 : in std_logic_vector(31 downto 0);
datain_b_57 : in std_logic_vector(31 downto 0);
datain_b_58 : in std_logic_vector(31 downto 0);
datain_b_59 : in std_logic_vector(31 downto 0);
datain_b_60 : in std_logic_vector(31 downto 0);
datain_b_61 : in std_logic_vector(31 downto 0);
datain_b_62 : in std_logic_vector(31 downto 0);
datain_b_63 : in std_logic_vector(31 downto 0);
dout_s : out std_logic_vector(31 downto 0);
v_s : in std_logic_vector(0 downto 0);
vout_s : out std_logic_vector(0 downto 0);
clk : in std_logic;
areset : in std_logic;
h_areset : in std_logic
);
end component;
SIGNAL done : STD_LOGIC;
SIGNAL res : STD_LOGIC_VECTOR(32 DOWNTO 1);
SIGNAL reset : STD_LOGIC;
SIGNAL v_in : std_logic_vector(0 downto 0);
SIGNAL v_out : std_logic_vector(0 downto 0);
BEGIN
reset <= NOT resetn;
v_in <= "1" when (valid_in = '1') else "0";
cmp0: dotProduct64_dut
PORT MAP (clk=>clock, areset=>reset, h_areset => reset, v_s=>v_in,
vout_s=>v_out, dout_s=>res, c_s => "00000000",
datain_a_00 => a0(32 DOWNTO 1),
datain_b_00 => b0(32 DOWNTO 1),
datain_a_01 => a0(64 DOWNTO 33),
datain_b_01 => b0(64 DOWNTO 33),
datain_a_02 => a0(96 DOWNTO 65),
datain_b_02 => b0(96 DOWNTO 65),
datain_a_03 => a0(128 DOWNTO 97),
datain_b_03 => b0(128 DOWNTO 97),
datain_a_04 => a0(160 DOWNTO 129),
datain_b_04 => b0(160 DOWNTO 129),
datain_a_05 => a0(192 DOWNTO 161),
datain_b_05 => b0(192 DOWNTO 161),
datain_a_06 => a0(224 DOWNTO 193),
datain_b_06 => b0(224 DOWNTO 193),
datain_a_07 => a0(256 DOWNTO 225),
datain_b_07 => b0(256 DOWNTO 225),
datain_a_08 => a0(288 DOWNTO 257),
datain_b_08 => b0(288 DOWNTO 257),
datain_a_09 => a0(320 DOWNTO 289),
datain_b_09 => b0(320 DOWNTO 289),
datain_a_10 => a0(352 DOWNTO 321),
datain_b_10 => b0(352 DOWNTO 321),
datain_a_11 => a0(384 DOWNTO 353),
datain_b_11 => b0(384 DOWNTO 353),
datain_a_12 => a0(416 DOWNTO 385),
datain_b_12 => b0(416 DOWNTO 385),
datain_a_13 => a0(448 DOWNTO 417),
datain_b_13 => b0(448 DOWNTO 417),
datain_a_14 => a0(480 DOWNTO 449),
datain_b_14 => b0(480 DOWNTO 449),
datain_a_15 => a0(512 DOWNTO 481),
datain_b_15 => b0(512 DOWNTO 481),
datain_a_16 => a1(32 DOWNTO 1),
datain_b_16 => b1(32 DOWNTO 1),
datain_a_17 => a1(64 DOWNTO 33),
datain_b_17 => b1(64 DOWNTO 33),
datain_a_18 => a1(96 DOWNTO 65),
datain_b_18 => b1(96 DOWNTO 65),
datain_a_19 => a1(128 DOWNTO 97),
datain_b_19 => b1(128 DOWNTO 97),
datain_a_20 => a1(160 DOWNTO 129),
datain_b_20 => b1(160 DOWNTO 129),
datain_a_21 => a1(192 DOWNTO 161),
datain_b_21 => b1(192 DOWNTO 161),
datain_a_22 => a1(224 DOWNTO 193),
datain_b_22 => b1(224 DOWNTO 193),
datain_a_23 => a1(256 DOWNTO 225),
datain_b_23 => b1(256 DOWNTO 225),
datain_a_24 => a1(288 DOWNTO 257),
datain_b_24 => b1(288 DOWNTO 257),
datain_a_25 => a1(320 DOWNTO 289),
datain_b_25 => b1(320 DOWNTO 289),
datain_a_26 => a1(352 DOWNTO 321),
datain_b_26 => b1(352 DOWNTO 321),
datain_a_27 => a1(384 DOWNTO 353),
datain_b_27 => b1(384 DOWNTO 353),
datain_a_28 => a1(416 DOWNTO 385),
datain_b_28 => b1(416 DOWNTO 385),
datain_a_29 => a1(448 DOWNTO 417),
datain_b_29 => b1(448 DOWNTO 417),
datain_a_30 => a1(480 DOWNTO 449),
datain_b_30 => b1(480 DOWNTO 449),
datain_a_31 => a1(512 DOWNTO 481),
datain_b_31 => b1(512 DOWNTO 481),
datain_a_32 => a2(32 DOWNTO 1),
datain_b_32 => b2(32 DOWNTO 1),
datain_a_33 => a2(64 DOWNTO 33),
datain_b_33 => b2(64 DOWNTO 33),
datain_a_34 => a2(96 DOWNTO 65),
datain_b_34 => b2(96 DOWNTO 65),
datain_a_35 => a2(128 DOWNTO 97),
datain_b_35 => b2(128 DOWNTO 97),
datain_a_36 => a2(160 DOWNTO 129),
datain_b_36 => b2(160 DOWNTO 129),
datain_a_37 => a2(192 DOWNTO 161),
datain_b_37 => b2(192 DOWNTO 161),
datain_a_38 => a2(224 DOWNTO 193),
datain_b_38 => b2(224 DOWNTO 193),
datain_a_39 => a2(256 DOWNTO 225),
datain_b_39 => b2(256 DOWNTO 225),
datain_a_40 => a2(288 DOWNTO 257),
datain_b_40 => b2(288 DOWNTO 257),
datain_a_41 => a2(320 DOWNTO 289),
datain_b_41 => b2(320 DOWNTO 289),
datain_a_42 => a2(352 DOWNTO 321),
datain_b_42 => b2(352 DOWNTO 321),
datain_a_43 => a2(384 DOWNTO 353),
datain_b_43 => b2(384 DOWNTO 353),
datain_a_44 => a2(416 DOWNTO 385),
datain_b_44 => b2(416 DOWNTO 385),
datain_a_45 => a2(448 DOWNTO 417),
datain_b_45 => b2(448 DOWNTO 417),
datain_a_46 => a2(480 DOWNTO 449),
datain_b_46 => b2(480 DOWNTO 449),
datain_a_47 => a2(512 DOWNTO 481),
datain_b_47 => b2(512 DOWNTO 481),
datain_a_48 => a3(32 DOWNTO 1),
datain_b_48 => b3(32 DOWNTO 1),
datain_a_49 => a3(64 DOWNTO 33),
datain_b_49 => b3(64 DOWNTO 33),
datain_a_50 => a3(96 DOWNTO 65),
datain_b_50 => b3(96 DOWNTO 65),
datain_a_51 => a3(128 DOWNTO 97),
datain_b_51 => b3(128 DOWNTO 97),
datain_a_52 => a3(160 DOWNTO 129),
datain_b_52 => b3(160 DOWNTO 129),
datain_a_53 => a3(192 DOWNTO 161),
datain_b_53 => b3(192 DOWNTO 161),
datain_a_54 => a3(224 DOWNTO 193),
datain_b_54 => b3(224 DOWNTO 193),
datain_a_55 => a3(256 DOWNTO 225),
datain_b_55 => b3(256 DOWNTO 225),
datain_a_56 => a3(288 DOWNTO 257),
datain_b_56 => b3(288 DOWNTO 257),
datain_a_57 => a3(320 DOWNTO 289),
datain_b_57 => b3(320 DOWNTO 289),
datain_a_58 => a3(352 DOWNTO 321),
datain_b_58 => b3(352 DOWNTO 321),
datain_a_59 => a3(384 DOWNTO 353),
datain_b_59 => b3(384 DOWNTO 353),
datain_a_60 => a3(416 DOWNTO 385),
datain_b_60 => b3(416 DOWNTO 385),
datain_a_61 => a3(448 DOWNTO 417),
datain_b_61 => b3(448 DOWNTO 417),
datain_a_62 => a3(480 DOWNTO 449),
datain_b_62 => b3(480 DOWNTO 449),
datain_a_63 => a3(512 DOWNTO 481),
datain_b_63 => b3(512 DOWNTO 481));
done <= '1' when (v_out = "1") else '0';
result <= res;
valid_out <= done;
END gen;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
Gray_Processing/ip/Gray_Processing/fp_log.vhd
|
10
|
7973
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION LOG(LN) - TOP LEVEL ***
--*** ***
--*** FP_LOG.VHD ***
--*** ***
--*** Function: IEEE754 FP LOG() ***
--*** ***
--*** 21/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** Latency = 21 ***
--***************************************************
ENTITY fp_log IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END fp_log;
ARCHITECTURE rtl OF fp_log IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
constant coredepth : positive := 19;
signal signinff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signnode : STD_LOGIC;
signal mantissanode : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal zeronode : STD_LOGIC;
-- conditions
signal zeroman : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal zeroexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maxexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zeromaninff : STD_LOGIC;
signal zeroexpinff : STD_LOGIC;
signal maxexpinff : STD_LOGIC;
signal naninff : STD_LOGIC;
signal nanff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
signal infinityinff : STD_LOGIC;
signal infinityff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
component fp_ln_core
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aaman : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
aaexp : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
ccman : OUT STD_LOGIC_VECTOR (24 DOWNTO 1);
ccexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
ccsgn : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
component fp_lnrnd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (24 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
end component;
BEGIN
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth LOOP
maninff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
signinff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
maninff <= mantissain;
expinff <= exponentin;
signinff(1) <= signin;
signinff(2) <= signinff(1);
END IF;
END IF;
END PROCESS;
--********************
--*** CHECK INPUTS ***
--********************
zeroman(1) <= maninff(1);
gca: FOR k IN 2 TO manwidth GENERATE
zeroman(k) <= zeroman(k-1) OR maninff(k);
END GENERATE;
zeroexp(1) <= expinff(1);
gcb: FOR k IN 2 TO expwidth GENERATE
zeroexp(k) <= zeroexp(k-1) OR expinff(k);
END GENERATE;
maxexp(1) <= expinff(1);
gcc: FOR k IN 2 TO expwidth GENERATE
maxexp(k) <= maxexp(k-1) AND expinff(k);
END GENERATE;
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
zeromaninff <= '0';
zeroexpinff <= '0';
maxexpinff <= '0';
naninff <= '0';
FOR k IN 1 TO coredepth-3 LOOP
nanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeromaninff <= NOT(zeroman(manwidth));
zeroexpinff <= NOT(zeroexp(expwidth));
maxexpinff <= maxexp(expwidth);
-- infinity when exp = zero
-- nan when man != 0, exp = max
-- all ffs '1' when condition true
naninff <= (zeromaninff AND maxexpinff) OR signinff(2);
infinityinff <= zeroexpinff OR maxexpinff;
-- nan output when nan input
nanff(1) <= naninff;
FOR k IN 2 TO coredepth-3 LOOP
nanff(k) <= nanff(k-1);
END LOOP;
infinityff(1) <= infinityinff;
FOR k IN 2 TO coredepth-3 LOOP
infinityff(k) <= infinityff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--***************
--*** LN CORE ***
--***************
lncore: fp_ln_core
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aaman=>mantissain,aaexp=>exponentin,
ccman=>mantissanode,ccexp=>exponentnode,ccsgn=>signnode,
zeroout=>zeronode);
--************************
--*** ROUND AND OUTPUT ***
--************************
rndout: fp_lnrnd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signln=>signnode,
exponentln=>exponentnode,
mantissaln=>mantissanode,
nanin=>nanff(coredepth-3),
infinityin=>infinityff(coredepth-3),
zeroin=>zeronode,
signout=>signout,
exponentout=>exponentout,
mantissaout=>mantissaout,
nanout=>nanout,overflowout=>overflowout,zeroout=>zeroout);
END rtl;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
bin_Gray_Processing/ip/Gray_Processing/dp_addb.vhd
|
10
|
2971
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION CORE LIBRARY ***
--*** ***
--*** DP_ADDB.VHD ***
--*** ***
--*** Function: Behavioral Fixed Point Adder ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_addb IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END dp_addb;
ARCHITECTURE rtl OF dp_addb IS
type pipefftype IS ARRAY (pipes DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal delff : STD_LOGIC_VECTOR (width DOWNTO 1);
signal pipeff : pipefftype;
signal ccnode : STD_LOGIC_VECTOR (width DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (width-1 DOWNTO 1);
BEGIN
gza: FOR k IN 1 TO width-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
ccnode <= aa + bb + (zerovec & carryin);
gda: IF (pipes = 1) GENERATE
pda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
delff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delff <= ccnode;
END IF;
END IF;
END PROCESS;
cc <= delff;
END GENERATE;
gpa: IF (pipes > 1) GENERATE
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO pipes LOOP
FOR j IN 1 TO width LOOP
pipeff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
pipeff(1)(width DOWNTO 1) <= ccnode;
FOR k IN 2 TO pipes LOOP
pipeff(k)(width DOWNTO 1) <= pipeff(k-1)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= pipeff(pipes)(width DOWNTO 1);
END GENERATE;
END rtl;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
Gray_Processing/ip/Gray_Processing/dp_rsftpipe64x64.vhd
|
10
|
5777
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ***
--*** DP_RSFTPIPE64X64.VHD ***
--*** ***
--*** Function: Pipelined Right Shift ***
--*** (max 64.0 to 1.52) ***
--*** ***
--*** 07/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 29/07/09 - signed number problem fixed ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_rsftpipe64x64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (116 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (116 DOWNTO 1)
);
END dp_rsftpipe64x64;
ARCHITECTURE rtl of dp_rsftpipe64x64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (6 DOWNTO 5);
BEGIN
levzip <= inbus;
-- unsigned input
gla: FOR k IN 1 TO 113 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
-- 29/07/65 always shift 116, else will fill with zeros
-- fixed here and other lines
levone(114) <= (levzip(114) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(115) AND NOT(shift(2)) AND shift(1)) OR
(levzip(116) AND shift(2) AND NOT(shift(1))) OR
(levzip(116) AND shift(2) AND shift(1));
levone(115) <= (levzip(115) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(116) AND NOT(shift(2)) AND shift(1)) OR
(levzip(116) AND shift(2) AND NOT(shift(1))) OR
(levzip(116) AND shift(2) AND shift(1));
levone(116) <= levzip(116);
glba: FOR k IN 1 TO 104 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
glbb: FOR k IN 105 TO 108 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(116) AND shift(4) AND shift(3));
END GENERATE;
glbc: FOR k IN 109 TO 112 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(116) AND shift(4) AND NOT(shift(3))) OR
(levone(116) AND shift(4) AND shift(3));
END GENERATE;
glbd: FOR k IN 113 TO 116 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(116) AND (shift(4) OR shift(3)));
END GENERATE;
pp: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 116 LOOP
levtwoff(k) <= '0';
END LOOP;
shiftff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
levtwoff <= levtwo;
shiftff <= shift(6 DOWNTO 5);
END IF;
END IF;
END PROCESS;
glca: FOR k IN 1 TO 66 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k+16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k+32) AND shiftff(6) AND NOT(shiftff(5))) OR
(levtwoff(k+48) AND shiftff(6) AND shiftff(5));
END GENERATE;
glcb: FOR k IN 67 TO 84 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shift(5))) OR
(levtwoff(k+16) AND NOT(shiftff(6)) AND shift(5)) OR
(levtwoff(k+32) AND shiftff(6) AND NOT(shift(5))) OR
(levtwoff(116) AND shiftff(6) AND shift(5));
END GENERATE;
glcc: FOR k IN 85 TO 100 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k+16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(116) AND shiftff(6) AND NOT(shiftff(5))) OR
(levtwoff(116) AND shiftff(6) AND shiftff(5));
END GENERATE;
glcd: FOR k IN 101 TO 116 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(116) AND (shiftff(6) OR shiftff(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
Gray_Processing/ip/Gray_Processing/fp_sin.vhd
|
10
|
14482
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_SIN.VHD ***
--*** ***
--*** Function: Single Precision SIN Core ***
--*** ***
--*** 10/01/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. Input < 0.5 radians, take cos(pi/2-input)***
--*** 2. latency = depth + range_depth (11) + 7 ***
--*** (1 more than cos) ***
--***************************************************
ENTITY fp_sin IS
GENERIC (
device : integer := 0;
width : positive := 30;
depth : positive := 18;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_sin;
ARCHITECTURE rtl of fp_sin IS
constant cordic_width : positive := width;
constant cordic_depth : positive := depth;
constant range_depth : positive := 11;
signal piovertwo : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal input_number : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal input_number_delay : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal exponentinff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentcheck : STD_LOGIC_VECTOR (9 DOWNTO 1);
-- range reduction
signal circle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal negcircle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quadrantsign, quadrantselect : STD_LOGIC;
signal positive_quadrant, negative_quadrant : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fraction_quadrant : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal one_term : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quadrant : STD_LOGIC_VECTOR (34 DOWNTO 1);
-- circle to radians mult
signal radiansnode : STD_LOGIC_VECTOR (cordic_width DOWNTO 1);
signal indexcheck : STD_LOGIC_VECTOR (16 DOWNTO 1);
signal indexbit : STD_LOGIC;
signal signinff : STD_LOGIC_VECTOR (range_depth DOWNTO 1);
signal selectoutputff : STD_LOGIC_VECTOR (range_depth+cordic_depth+5 DOWNTO 1);
signal signcalcff : STD_LOGIC_VECTOR (cordic_depth+6 DOWNTO 1);
signal quadrant_sumff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal select_sincosff : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal fixed_sincos : STD_LOGIC_VECTOR (cordic_width DOWNTO 1);
signal fixed_sincosnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fixed_sincosff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal countnode : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal mantissanormnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissanormff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentnormnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentnormff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal overflownode : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal mantissaoutff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal signoutff : STD_LOGIC;
component fp_range1
GENERIC (device : integer);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
circle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
negcircle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_cordic_m1
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sincosbit : IN STD_LOGIC;
sincos : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_clz36 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_lsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- pi/2 = 1.57
piovertwo <= x"c90fdaa22";
zerovec <= x"000000000";
--*** SIN(X) = X when exponent < 115 ***
input_number <= signin & exponentin & mantissain;
-- level 1 in, level range_depth+cordic_depth+7 out
cdin: fp_del
GENERIC MAP (width=>32,pipes=>range_depth+cordic_depth+6)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>input_number,
cc=>input_number_delay);
--*** RANGE REDUCTION ***
crr: fp_range1
GENERIC MAP(device=>device)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signin,exponentin=>exponentin,mantissain=>mantissain,
circle=>circle,negcircle=>negcircle);
quadrantsign <= circle(36); -- sin negative in quadrants 3&4
quadrantselect <= circle(35); -- sin (1-x) in quadants 2&4
gra: FOR k IN 1 TO 34 GENERATE
quadrant(k) <= (circle(k) AND NOT(quadrantselect)) OR
(negcircle(k) AND quadrantselect);
END GENERATE;
-- if quadrant >0.5 (when quadrant(34) = 1), use quadrant, else use 1-quadrant, and take cos rather than sin
positive_quadrant <= '0' & quadrant & '0';
gnqa: FOR k IN 1 TO 36 GENERATE
negative_quadrant(k) <= NOT(positive_quadrant(k));
fraction_quadrant(k) <= (positive_quadrant(k) AND quadrant(34)) OR
(negative_quadrant(k) AND NOT(quadrant(34)));
END GENERATE;
one_term <= NOT(quadrant(34)) & zerovec(35 DOWNTO 1); -- 0 if positive quadrant
pfa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO range_depth LOOP
signinff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth+6 LOOP
signcalcff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentinff(k) <= '0';
END LOOP;
FOR k IN 1 TO range_depth+cordic_depth+5 LOOP
selectoutputff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
quadrant_sumff(k) <= '0';
END LOOP;
FOR k IN 1 TO 4 LOOP
select_sincosff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff(1) <= signin;
FOR k IN 2 TO range_depth LOOP
signinff(k) <= signinff(k-1);
END LOOP;
-- level range_depth+1 to range_depth+cordic_depth+6
signcalcff(1) <= quadrantsign XOR signinff(range_depth);
FOR k IN 2 TO cordic_depth+6 LOOP
signcalcff(k) <= signcalcff(k-1);
END LOOP;
exponentinff <= exponentin; -- level 1
selectoutputff(1) <= exponentcheck(9); -- level 2 to range_depth+cordic_depth+6
FOR k IN 2 TO range_depth+cordic_depth+5 LOOP
selectoutputff(k) <= selectoutputff(k-1);
END LOOP;
-- range 0-0.9999
quadrant_sumff <= one_term + fraction_quadrant + NOT(quadrant(34)); -- level range_depth+1
-- level range depth+1 to range_depth+4
select_sincosff(1) <= quadrant(34);
FOR k IN 2 TO 4 LOOP
select_sincosff(k) <= select_sincosff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- if exponent < 115, sin = input
exponentcheck <= ('0' & exponentinff) - ('0' & x"73");
-- levels range_depth+2,3,4
cmul: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>cordic_width,
pipes=>3,synthesize=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>quadrant_sumff,databb=>piovertwo,
result=>radiansnode);
indexcheck(1) <= radiansnode(cordic_width-1);
gica: FOR k IN 2 TO 16 GENERATE
indexcheck(k) <= indexcheck(k-1) OR radiansnode(cordic_width-k);
END GENERATE;
-- for safety, give an extra bit of space
indexbit <= NOT(indexcheck(indexpoint+1));
ccc: fp_cordic_m1
GENERIC MAP (width=>cordic_width,depth=>cordic_depth,indexpoint=>indexpoint)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
radians=>radiansnode,
indexbit=>indexbit,
sincosbit=>select_sincosff(4),
sincos=>fixed_sincos);
gfxa: IF (width < 36) GENERATE
fixed_sincosnode <= fixed_sincos & zerovec(36-width DOWNTO 1);
END GENERATE;
gfxb: IF (width = 36) GENERATE
fixed_sincosnode <= fixed_sincos;
END GENERATE;
clz: fp_clz36
PORT MAP (mantissa=>fixed_sincosnode,leading=>countnode);
sft: fp_lsft36
PORT MAP (inbus=>fixed_sincosff,shift=>countff,
outbus=>mantissanormnode);
-- maximum sin or cos = 1.0 = 1.0e127 single precision
-- 1e128 - 1 (leading one) gives correct number
exponentnormnode <= "10000000" - ("00" & countff);
overflownode(1) <= mantissanormnode(12);
gova: FOR k IN 2 TO 24 GENERATE
overflownode(k) <= mantissanormnode(k+11) AND overflownode(k-1);
END GENERATE;
-- OUTPUT
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
fixed_sincosff(k) <= '0';
END LOOP;
countff <= "000000";
FOR k IN 1 TO 23 LOOP
mantissanormff(k) <= '0';
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentnormff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
signoutff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
fixed_sincosff <= fixed_sincosnode; -- level range_depth+cordic_depth+5
countff <= countnode; -- level range_depth+4+cordic_depth+5
-- level range_depth+cordic_depth+6
mantissanormff <= mantissanormnode(35 DOWNTO 13) + mantissanormnode(12);
exponentnormff <= exponentnormnode(8 DOWNTO 1) + overflownode(24);
-- level range_depth+cordic_depth+7
FOR k IN 1 TO 23 LOOP
mantissaoutff(k) <= (mantissanormff(k) AND NOT(selectoutputff(range_depth+cordic_depth+5))) OR
(input_number_delay(k) AND selectoutputff(range_depth+cordic_depth+5));
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentoutff(k) <= (exponentnormff(k) AND NOT(selectoutputff(range_depth+cordic_depth+5))) OR
(input_number_delay(k+23) AND selectoutputff(range_depth+cordic_depth+5));
END LOOP;
signoutff <= (signcalcff(cordic_depth+6) AND NOT(selectoutputff(range_depth+cordic_depth+5))) OR
(input_number_delay(32) AND selectoutputff(range_depth+cordic_depth+5));
END IF;
END IF;
END PROCESS;
mantissaout <= mantissaoutff;
exponentout <= exponentoutff;
signout <= signoutff;
END rtl;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
Gray_Processing/ip/Gray_Processing/dspba_library_sv.vhd
|
22
|
1907
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_loop: for i in depth-1 downto 0 generate
begin
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
xout <= delay_signals(0);
end delay;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
bin_Gray_Processing/ip/Gray_Processing/dspba_library_sv.vhd
|
22
|
1907
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_loop: for i in depth-1 downto 0 generate
begin
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
xout <= delay_signals(0);
end delay;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
Gray_Processing/ip/Gray_Processing/fp_explutneg.vhd
|
10
|
14862
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_EXPLUTNEG.VHD ***
--*** ***
--*** Function: Look Up Table - EXP() ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_explutneg IS
PORT (
address : IN STD_LOGIC_VECTOR (7 DOWNTO 1);
mantissa : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_explutneg;
ARCHITECTURE rtl OF fp_explutneg IS
BEGIN
pca: PROCESS (address)
BEGIN
CASE address IS
WHEN "0000000" =>
mantissa <= conv_std_logic_vector(0,23);
exponent <= conv_std_logic_vector(127,8);
WHEN "0000001" =>
mantissa <= conv_std_logic_vector(3955378,23);
exponent <= conv_std_logic_vector(125,8);
WHEN "0000010" =>
mantissa <= conv_std_logic_vector(693589,23);
exponent <= conv_std_logic_vector(124,8);
WHEN "0000011" =>
mantissa <= conv_std_logic_vector(4976006,23);
exponent <= conv_std_logic_vector(122,8);
WHEN "0000100" =>
mantissa <= conv_std_logic_vector(1444526,23);
exponent <= conv_std_logic_vector(121,8);
WHEN "0000101" =>
mantissa <= conv_std_logic_vector(6081023,23);
exponent <= conv_std_logic_vector(119,8);
WHEN "0000110" =>
mantissa <= conv_std_logic_vector(2257552,23);
exponent <= conv_std_logic_vector(118,8);
WHEN "0000111" =>
mantissa <= conv_std_logic_vector(7277405,23);
exponent <= conv_std_logic_vector(116,8);
WHEN "0001000" =>
mantissa <= conv_std_logic_vector(3137800,23);
exponent <= conv_std_logic_vector(115,8);
WHEN "0001001" =>
mantissa <= conv_std_logic_vector(92049,23);
exponent <= conv_std_logic_vector(114,8);
WHEN "0001010" =>
mantissa <= conv_std_logic_vector(4090830,23);
exponent <= conv_std_logic_vector(112,8);
WHEN "0001011" =>
mantissa <= conv_std_logic_vector(793249,23);
exponent <= conv_std_logic_vector(111,8);
WHEN "0001100" =>
mantissa <= conv_std_logic_vector(5122658,23);
exponent <= conv_std_logic_vector(109,8);
WHEN "0001101" =>
mantissa <= conv_std_logic_vector(1552426,23);
exponent <= conv_std_logic_vector(108,8);
WHEN "0001110" =>
mantissa <= conv_std_logic_vector(6239800,23);
exponent <= conv_std_logic_vector(106,8);
WHEN "0001111" =>
mantissa <= conv_std_logic_vector(2374373,23);
exponent <= conv_std_logic_vector(105,8);
WHEN "0010000" =>
mantissa <= conv_std_logic_vector(7449310,23);
exponent <= conv_std_logic_vector(103,8);
WHEN "0010001" =>
mantissa <= conv_std_logic_vector(3264281,23);
exponent <= conv_std_logic_vector(102,8);
WHEN "0010010" =>
mantissa <= conv_std_logic_vector(185108,23);
exponent <= conv_std_logic_vector(101,8);
WHEN "0010011" =>
mantissa <= conv_std_logic_vector(4227768,23);
exponent <= conv_std_logic_vector(99,8);
WHEN "0010100" =>
mantissa <= conv_std_logic_vector(894003,23);
exponent <= conv_std_logic_vector(98,8);
WHEN "0010101" =>
mantissa <= conv_std_logic_vector(5270919,23);
exponent <= conv_std_logic_vector(96,8);
WHEN "0010110" =>
mantissa <= conv_std_logic_vector(1661510,23);
exponent <= conv_std_logic_vector(95,8);
WHEN "0010111" =>
mantissa <= conv_std_logic_vector(6400319,23);
exponent <= conv_std_logic_vector(93,8);
WHEN "0011000" =>
mantissa <= conv_std_logic_vector(2492476,23);
exponent <= conv_std_logic_vector(92,8);
WHEN "0011001" =>
mantissa <= conv_std_logic_vector(7623101,23);
exponent <= conv_std_logic_vector(90,8);
WHEN "0011010" =>
mantissa <= conv_std_logic_vector(3392149,23);
exponent <= conv_std_logic_vector(89,8);
WHEN "0011011" =>
mantissa <= conv_std_logic_vector(279189,23);
exponent <= conv_std_logic_vector(88,8);
WHEN "0011100" =>
mantissa <= conv_std_logic_vector(4366209,23);
exponent <= conv_std_logic_vector(86,8);
WHEN "0011101" =>
mantissa <= conv_std_logic_vector(995862,23);
exponent <= conv_std_logic_vector(85,8);
WHEN "0011110" =>
mantissa <= conv_std_logic_vector(5420806,23);
exponent <= conv_std_logic_vector(83,8);
WHEN "0011111" =>
mantissa <= conv_std_logic_vector(1771791,23);
exponent <= conv_std_logic_vector(82,8);
WHEN "0100000" =>
mantissa <= conv_std_logic_vector(6562600,23);
exponent <= conv_std_logic_vector(80,8);
WHEN "0100001" =>
mantissa <= conv_std_logic_vector(2611876,23);
exponent <= conv_std_logic_vector(79,8);
WHEN "0100010" =>
mantissa <= conv_std_logic_vector(7798799,23);
exponent <= conv_std_logic_vector(77,8);
WHEN "0100011" =>
mantissa <= conv_std_logic_vector(3521421,23);
exponent <= conv_std_logic_vector(76,8);
WHEN "0100100" =>
mantissa <= conv_std_logic_vector(374301,23);
exponent <= conv_std_logic_vector(75,8);
WHEN "0100101" =>
mantissa <= conv_std_logic_vector(4506169,23);
exponent <= conv_std_logic_vector(73,8);
WHEN "0100110" =>
mantissa <= conv_std_logic_vector(1098839,23);
exponent <= conv_std_logic_vector(72,8);
WHEN "0100111" =>
mantissa <= conv_std_logic_vector(5572338,23);
exponent <= conv_std_logic_vector(70,8);
WHEN "0101000" =>
mantissa <= conv_std_logic_vector(1883282,23);
exponent <= conv_std_logic_vector(69,8);
WHEN "0101001" =>
mantissa <= conv_std_logic_vector(6726661,23);
exponent <= conv_std_logic_vector(67,8);
WHEN "0101010" =>
mantissa <= conv_std_logic_vector(2732585,23);
exponent <= conv_std_logic_vector(66,8);
WHEN "0101011" =>
mantissa <= conv_std_logic_vector(7976426,23);
exponent <= conv_std_logic_vector(64,8);
WHEN "0101100" =>
mantissa <= conv_std_logic_vector(3652111,23);
exponent <= conv_std_logic_vector(63,8);
WHEN "0101101" =>
mantissa <= conv_std_logic_vector(470458,23);
exponent <= conv_std_logic_vector(62,8);
WHEN "0101110" =>
mantissa <= conv_std_logic_vector(4647665,23);
exponent <= conv_std_logic_vector(60,8);
WHEN "0101111" =>
mantissa <= conv_std_logic_vector(1202946,23);
exponent <= conv_std_logic_vector(59,8);
WHEN "0110000" =>
mantissa <= conv_std_logic_vector(5725533,23);
exponent <= conv_std_logic_vector(57,8);
WHEN "0110001" =>
mantissa <= conv_std_logic_vector(1995997,23);
exponent <= conv_std_logic_vector(56,8);
WHEN "0110010" =>
mantissa <= conv_std_logic_vector(6892523,23);
exponent <= conv_std_logic_vector(54,8);
WHEN "0110011" =>
mantissa <= conv_std_logic_vector(2854620,23);
exponent <= conv_std_logic_vector(53,8);
WHEN "0110100" =>
mantissa <= conv_std_logic_vector(8156001,23);
exponent <= conv_std_logic_vector(51,8);
WHEN "0110101" =>
mantissa <= conv_std_logic_vector(3784235,23);
exponent <= conv_std_logic_vector(50,8);
WHEN "0110110" =>
mantissa <= conv_std_logic_vector(567669,23);
exponent <= conv_std_logic_vector(49,8);
WHEN "0110111" =>
mantissa <= conv_std_logic_vector(4790713,23);
exponent <= conv_std_logic_vector(47,8);
WHEN "0111000" =>
mantissa <= conv_std_logic_vector(1308195,23);
exponent <= conv_std_logic_vector(46,8);
WHEN "0111001" =>
mantissa <= conv_std_logic_vector(5880410,23);
exponent <= conv_std_logic_vector(44,8);
WHEN "0111010" =>
mantissa <= conv_std_logic_vector(2109948,23);
exponent <= conv_std_logic_vector(43,8);
WHEN "0111011" =>
mantissa <= conv_std_logic_vector(7060204,23);
exponent <= conv_std_logic_vector(41,8);
WHEN "0111100" =>
mantissa <= conv_std_logic_vector(2977993,23);
exponent <= conv_std_logic_vector(40,8);
WHEN "0111101" =>
mantissa <= conv_std_logic_vector(8337547,23);
exponent <= conv_std_logic_vector(38,8);
WHEN "0111110" =>
mantissa <= conv_std_logic_vector(3917809,23);
exponent <= conv_std_logic_vector(37,8);
WHEN "0111111" =>
mantissa <= conv_std_logic_vector(665948,23);
exponent <= conv_std_logic_vector(36,8);
WHEN "1000000" =>
mantissa <= conv_std_logic_vector(4935332,23);
exponent <= conv_std_logic_vector(34,8);
WHEN "1000001" =>
mantissa <= conv_std_logic_vector(1414599,23);
exponent <= conv_std_logic_vector(33,8);
WHEN "1000010" =>
mantissa <= conv_std_logic_vector(6036985,23);
exponent <= conv_std_logic_vector(31,8);
WHEN "1000011" =>
mantissa <= conv_std_logic_vector(2225150,23);
exponent <= conv_std_logic_vector(30,8);
WHEN "1000100" =>
mantissa <= conv_std_logic_vector(7229726,23);
exponent <= conv_std_logic_vector(28,8);
WHEN "1000101" =>
mantissa <= conv_std_logic_vector(3102720,23);
exponent <= conv_std_logic_vector(27,8);
WHEN "1000110" =>
mantissa <= conv_std_logic_vector(66239,23);
exponent <= conv_std_logic_vector(26,8);
WHEN "1000111" =>
mantissa <= conv_std_logic_vector(4052849,23);
exponent <= conv_std_logic_vector(24,8);
WHEN "1001000" =>
mantissa <= conv_std_logic_vector(765304,23);
exponent <= conv_std_logic_vector(23,8);
WHEN "1001001" =>
mantissa <= conv_std_logic_vector(5081537,23);
exponent <= conv_std_logic_vector(21,8);
WHEN "1001010" =>
mantissa <= conv_std_logic_vector(1522171,23);
exponent <= conv_std_logic_vector(20,8);
WHEN "1001011" =>
mantissa <= conv_std_logic_vector(6195279,23);
exponent <= conv_std_logic_vector(18,8);
WHEN "1001100" =>
mantissa <= conv_std_logic_vector(2341616,23);
exponent <= conv_std_logic_vector(17,8);
WHEN "1001101" =>
mantissa <= conv_std_logic_vector(7401108,23);
exponent <= conv_std_logic_vector(15,8);
WHEN "1001110" =>
mantissa <= conv_std_logic_vector(3228816,23);
exponent <= conv_std_logic_vector(14,8);
WHEN "1001111" =>
mantissa <= conv_std_logic_vector(159015,23);
exponent <= conv_std_logic_vector(13,8);
WHEN "1010000" =>
mantissa <= conv_std_logic_vector(4189370,23);
exponent <= conv_std_logic_vector(11,8);
WHEN "1010001" =>
mantissa <= conv_std_logic_vector(865751,23);
exponent <= conv_std_logic_vector(10,8);
WHEN "1010010" =>
mantissa <= conv_std_logic_vector(5229346,23);
exponent <= conv_std_logic_vector(8,8);
WHEN "1010011" =>
mantissa <= conv_std_logic_vector(1630923,23);
exponent <= conv_std_logic_vector(7,8);
WHEN "1010100" =>
mantissa <= conv_std_logic_vector(6355309,23);
exponent <= conv_std_logic_vector(5,8);
WHEN "1010101" =>
mantissa <= conv_std_logic_vector(2459360,23);
exponent <= conv_std_logic_vector(4,8);
WHEN "1010110" =>
mantissa <= conv_std_logic_vector(7574370,23);
exponent <= conv_std_logic_vector(2,8);
WHEN "1010111" =>
mantissa <= conv_std_logic_vector(3356295,23);
exponent <= conv_std_logic_vector(1,8);
WHEN "1011000" =>
mantissa <= conv_std_logic_vector(252809,23);
exponent <= conv_std_logic_vector(0,8);
WHEN "1011001" =>
mantissa <= conv_std_logic_vector(4327390,23);
exponent <= conv_std_logic_vector(-2,8);
WHEN others =>
mantissa <= conv_std_logic_vector(0,23);
exponent <= conv_std_logic_vector(0,8);
END CASE;
END PROCESS;
END rtl;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
Gray_Processing/ip/Gray_Processing/fp_mul5418s.vhd
|
10
|
4973
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_MUL5418S.VHD ***
--*** ***
--*** Function: Fixed Point Multiplier ***
--*** 54x18=54, 3 18x18 architecture, ***
--*** Stratix II/III, 3 or 4 pipeline, ***
--*** synthesizable ***
--*** ***
--*** 09/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 15/01/08 - outputs up to 72 bits now ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_mul5418s IS
GENERIC (
widthcc : positive := 36;
pipes : positive := 3 --3/4
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (18 DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
END fp_mul5418s;
ARCHITECTURE rtl OF fp_mul5418s IS
signal zerovec : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal muloneout, multwoout, multhrout : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal aavec, bbvec : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal resultnode : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal lowff, lowdelff : STD_LOGIC_VECTOR (18 DOWNTO 1);
component dp_fxadd IS
GENERIC (
width : positive := 64;
pipes : positive := 1;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_mul2s IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 18 GENERATE
zerovec(k) <= '0';
END GENERATE;
mulone: fp_mul2s
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>36)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa(18 DOWNTO 1),databb=>databb(18 DOWNTO 1),
result=>muloneout);
multwo: fp_mul2s
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>36)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa(36 DOWNTO 19),databb=>databb(18 DOWNTO 1),
result=>multwoout);
multhr: fp_mul2s
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>36)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa(54 DOWNTO 37),databb=>databb(18 DOWNTO 1),
result=>multhrout);
aavec <= multhrout & muloneout(36 DOWNTO 19);
bbvec <= zerovec(18 DOWNTO 1) & multwoout;
adder: dp_fxadd
GENERIC MAP (width=>54,pipes=>pipes-2,synthesize=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aavec,bb=>bbvec,carryin=>'0',
cc=>resultnode(72 DOWNTO 19));
gda: IF (pipes = 3) GENERATE
pda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 18 LOOP
lowff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
lowff <= muloneout(18 DOWNTO 1);
END IF;
END IF;
END PROCESS;
resultnode(18 DOWNTO 1) <= lowff;
END GENERATE;
gdb: IF (pipes = 4) GENERATE
pdb: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 18 LOOP
lowff(k) <= '0';
lowdelff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
lowff <= muloneout(18 DOWNTO 1);
lowdelff <= lowff;
END IF;
END IF;
END PROCESS;
resultnode(18 DOWNTO 1) <= lowdelff;
END GENERATE;
result <= resultnode(72 DOWNTO 73-widthcc);
END rtl;
|
mit
|
Given-Jiang/Gray_Processing_Altera_OpenCL_DE1-SoC
|
Gray_Processing/ip/Gray_Processing/hcc_mul3236s.vhd
|
10
|
4308
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL3236S.VHD ***
--*** ***
--*** Function: 3 pipeline stage unsigned 32 or ***
--*** 36 bit multiplier (synth'able) ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul3236s IS
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
END hcc_mul3236s;
ARCHITECTURE syn OF hcc_mul3236s IS
COMPONENT altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (2*width-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "SIGNED",
representation_b => "SIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => width,
width_b => width,
width_result => 2*width
)
PORT MAP (
dataa => mulaa,
datab => mulbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulcc
);
END syn;
|
mit
|
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