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`protect end_protected
|
mit
|
HighlandersFRC/fpga
|
led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/proc_common_v4_0/hdl/src/vhdl/pf_counter_top.vhd
|
15
|
8369
|
-------------------------------------------------------------------------------
-- $Id: pf_counter_top.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_counter_top - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
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-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter_top.vhd
--
-- Description: Implements parameterized up/down counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter_top.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET 2001-08-30 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--Use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.pf_counter;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter_top is
generic (
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_Enable : in std_logic;
Load_value : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Down : in std_logic;
Count_Up : in std_logic;
--Carry_Out : out std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_counter_top;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter_top is
Signal sig_cnt_enable : std_logic;
Signal sig_cnt_up_n_dwn : std_logic;
Signal sig_carry_out : std_logic;
Signal sig_count_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
begin -- VHDL_RTL
-- Misc signal assignments
Count_Out <= sig_count_out;
--Carry_Out <= sig_carry_Out;
sig_cnt_enable <= Count_Up xor Count_Down;
sig_cnt_up_n_dwn <= not(Count_Up);
I_UP_DWN_COUNTER : entity proc_common_v4_0.pf_counter
generic map (
C_COUNT_WIDTH => C_COUNT_WIDTH
)
port map(
Clk => Clk, -- : in std_logic;
Rst => Rst, -- : in std_logic;
Carry_Out => sig_carry_out, -- : out std_logic;
Load_In => Load_value, -- : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable => sig_cnt_enable, -- : in std_logic;
Count_Load => Load_Enable, -- : in std_logic;
Count_Down => sig_cnt_up_n_dwn,-- : in std_logic;
Count_Out => sig_count_out -- : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end architecture implementation;
|
mit
|
HighlandersFRC/fpga
|
lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/proc_common_v4_0/hdl/src/vhdl/pf_counter_top.vhd
|
15
|
8369
|
-------------------------------------------------------------------------------
-- $Id: pf_counter_top.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_counter_top - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter_top.vhd
--
-- Description: Implements parameterized up/down counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter_top.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET 2001-08-30 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--Use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.pf_counter;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter_top is
generic (
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_Enable : in std_logic;
Load_value : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Down : in std_logic;
Count_Up : in std_logic;
--Carry_Out : out std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_counter_top;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter_top is
Signal sig_cnt_enable : std_logic;
Signal sig_cnt_up_n_dwn : std_logic;
Signal sig_carry_out : std_logic;
Signal sig_count_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
begin -- VHDL_RTL
-- Misc signal assignments
Count_Out <= sig_count_out;
--Carry_Out <= sig_carry_Out;
sig_cnt_enable <= Count_Up xor Count_Down;
sig_cnt_up_n_dwn <= not(Count_Up);
I_UP_DWN_COUNTER : entity proc_common_v4_0.pf_counter
generic map (
C_COUNT_WIDTH => C_COUNT_WIDTH
)
port map(
Clk => Clk, -- : in std_logic;
Rst => Rst, -- : in std_logic;
Carry_Out => sig_carry_out, -- : out std_logic;
Load_In => Load_value, -- : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable => sig_cnt_enable, -- : in std_logic;
Count_Load => Load_Enable, -- : in std_logic;
Count_Down => sig_cnt_up_n_dwn,-- : in std_logic;
Count_Out => sig_count_out -- : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end architecture implementation;
|
mit
|
HighlandersFRC/fpga
|
led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_quad_spi_0_0/proc_common_v4_0/hdl/src/vhdl/pf_counter_top.vhd
|
15
|
8369
|
-------------------------------------------------------------------------------
-- $Id: pf_counter_top.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pf_counter_top - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter_top.vhd
--
-- Description: Implements parameterized up/down counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter_top.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- DET 2001-08-30 First Version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
--Use IEEE.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.pf_counter;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter_top is
generic (
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_Enable : in std_logic;
Load_value : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Down : in std_logic;
Count_Up : in std_logic;
--Carry_Out : out std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_counter_top;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter_top is
Signal sig_cnt_enable : std_logic;
Signal sig_cnt_up_n_dwn : std_logic;
Signal sig_carry_out : std_logic;
Signal sig_count_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
begin -- VHDL_RTL
-- Misc signal assignments
Count_Out <= sig_count_out;
--Carry_Out <= sig_carry_Out;
sig_cnt_enable <= Count_Up xor Count_Down;
sig_cnt_up_n_dwn <= not(Count_Up);
I_UP_DWN_COUNTER : entity proc_common_v4_0.pf_counter
generic map (
C_COUNT_WIDTH => C_COUNT_WIDTH
)
port map(
Clk => Clk, -- : in std_logic;
Rst => Rst, -- : in std_logic;
Carry_Out => sig_carry_out, -- : out std_logic;
Load_In => Load_value, -- : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable => sig_cnt_enable, -- : in std_logic;
Count_Load => Load_Enable, -- : in std_logic;
Count_Down => sig_cnt_up_n_dwn,-- : in std_logic;
Count_Out => sig_count_out -- : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end architecture implementation;
|
mit
|
HighlandersFRC/fpga
|
led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_xbar_0/blk_mem_gen_v8_1/blk_mem_gen_prim_width.vhd
|
27
|
70652
|
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`protect end_protected
|
mit
|
HighlandersFRC/fpga
|
lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_9/blk_mem_gen_v8_1/blk_mem_gen_prim_width.vhd
|
27
|
70652
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 50560)
`protect data_block
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`protect end_protected
|
mit
|
HighlandersFRC/fpga
|
led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_bram_ctrl_0_0/fifo_generator_v11_0/ramfifo/wr_dc_fwft_ext_as.vhd
|
19
|
13630
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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0RIeWd32HQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8352)
`protect data_block
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`protect end_protected
|
mit
|
HighlandersFRC/fpga
|
led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_gpio_0_0/fifo_generator_v11_0/ramfifo/axi_reg_slice.vhd
|
19
|
17522
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11232)
`protect data_block
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`protect end_protected
|
mit
|
HighlandersFRC/fpga
|
oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_gpio_0_0/fifo_generator_v11_0/ramfifo/axi_reg_slice.vhd
|
19
|
17522
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11232)
`protect data_block
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`protect end_protected
|
mit
|
HighlandersFRC/fpga
|
led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_bram_ctrl_0_0/proc_common_v4_0/hdl/src/vhdl/eval_timer.vhd
|
15
|
11230
|
-------------------------------------------------------------------------------
-- $Id: eval_timer.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- eval_timer.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: eval_timer.vhd
-- Version: v1.00a
-- Description: 40-bit counter that enables IP to be used in an evaluation
-- mode. Once the counter expires, the eval_timeout signal
-- asserts and can be used to reset the IP.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- eval_timer.vhd
--
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 09/12/01 -- Created from PCI eval timer
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- No generics
--
-- Definition of Ports:
-- Clk -- clock
-- Rst -- active high reset
-- Eval_timeout -- timer has expired
-------------------------------------------------------------------------------
entity eval_timer is
port (
Clk : in std_logic;
Rst : in std_logic;
Eval_timeout : out std_logic
);
end entity eval_timer;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of eval_timer is
-----------------------------------------------------------------------------
-- Constant Declarations
-----------------------------------------------------------------------------
constant NUM_BITS : integer := 8;
-----------------------------------------------------------------------------
-- Signal Declarations
-----------------------------------------------------------------------------
signal co : std_logic_vector(0 to 4); -- carry out
signal ceo : std_logic_vector(0 to 4); -- count enable out
signal ceo_d1 : std_logic_vector(0 to 4); -- registered count enable out
signal zeros : std_logic_vector(NUM_BITS-1 downto 0);
-----------------------------------------------------------------------------
-- Component Declarations
-----------------------------------------------------------------------------
component Counter is
generic(
C_NUM_BITS : Integer := 9
);
port (
Clk : in std_logic;
Rst : in std_logic;
Load_In : in std_logic_vector(C_NUM_BITS - 1 downto 0);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Count_Out : out std_logic_vector(C_NUM_BITS - 1 downto 0);
Carry_Out : out std_logic
);
end component Counter;
component FDRE
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
component FDR
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
begin -- VHDL_RTL
-- set the load value to zero
zeros <= (others => '0');
-- Generate a 40-bit counter from 5 8-bit counters. Register the carry-out between counters
-- to avoid timing problems.
COUNTER_GEN: for i in 0 to 4 generate
-- first 8-bit counter
FIRST: if i = 0 generate
COUNT_0_I: Counter
generic map (C_NUM_BITS => NUM_BITS)
port map ( Clk => Clk,
Rst => Rst,
Load_in => zeros,
Count_Enable => '1',
Count_Load => '0',
Count_Down => '0',
Count_out => open,
Carry_Out => co(0)
);
-- register the carry out to create the count enable out
ceo(i) <= co(i);
FDR_0_I: FDR
port map (
Q => ceo_d1(i),
C => Clk,
D => ceo(i),
R => Rst
);
end generate FIRST;
-- all other eight bit counters and the carry out register
ALL_OTHERS: if i /= 0 generate
COUNT_I: Counter
generic map (C_NUM_BITS => NUM_BITS)
port map ( Clk => Clk,
Rst => Rst,
Load_in => zeros,
Count_Enable => ceo_d1(i-1),
Count_Load => '0',
Count_Down => '0',
Count_out => open,
Carry_Out => co(i)
);
-- register the carry out AND the count enable to create the count enable out
ceo(i) <= co(i) and ceo_d1(i-1);
FDR_0_I: FDR
port map (
Q => ceo_d1(i),
C => Clk,
D => ceo(i),
R => Rst
);
end generate ALL_OTHERS;
end generate COUNTER_GEN;
-- Using the final carry out as a CE, clock a '1' to assert and hold the eval_timeout signal.
FDRE_I: FDRE
port map (
Q => eval_timeout, --[out]
C => Clk, --[in]
CE => ceo_d1(4), --[in]
D => '1', --[in]
R => Rst --[in]
);
end imp;
|
mit
|
HighlandersFRC/fpga
|
lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/coregen_comp_defs.vhd
|
12
|
52359
|
-------------------------------------------------------------------------------
-- $Id:$
-------------------------------------------------------------------------------
-- coregen_comp_defs - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: coregen_comp_defs.vhd
-- Version: initial
-- Description:
-- Component declarations for all black box netlists generated by
-- running COREGEN and FIFO Generator when XST elaborated the client core
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- -- coregen_comp_defs.vhd
-- |
-- |--- XilinxCoreLib.fifo_generator_v9_2
-- |--- XilinxCoreLib.fifo_generator_v9_3
-- |
-- |--- XilinxCoreLib.blk_mem_gen_v7_1
-- |--- XilinxCoreLib.blk_mem_gen_v7_3
--
-------------------------------------------------------------------------------
-- Author: DET
-- History:
-- DET 02/01/2008 Initial Version
--
-- DET 2/01/2008 for proc_common_v4_0
-- ~~~~~~
-- - Adapted coregen_comp_defs.vhd from proc_common_v2_00_a to create
-- this file.
-- - Changed instance of sync fifo to use new wrapper file that will adapt
-- to FIFO Generator primitive.
-- - Replaced "edk_generatecore" with "generatecore" utility call
-- - Removed the CAM component
-- ^^^^^^
--
-- DET 7/30/2008 for EDK 11.1
-- ~~~~~~
-- - Added component for Fifo Generator version 4.3
-- - Added Block Memory Generator Component Version 2.7
-- ^^^^^^
--
-- MSH 2/26/2009 for EDK 11.1
-- ~~~~~~
-- - Added component for Fifo Generator version 5.1
-- - Added Block Memory Generator Component Version 3.1
-- ^^^^^^
--
-- DET 3/2/2009 for EDK 11.1
-- ~~~~~~
-- - Added new Parameters and ports for Fifo Generatore 5.1.
-- ^^^^^^
--
-- DET 3/30/2009 EDK 11.2
-- ~~~~~~
-- - Had to reorder parameter list of FIFO Generator 4.3 component to match
-- the corresponding Verilog model due to NCSIM positional order
-- dependancy of parameters in vhdl/verilog use case.
-- ^^^^^^
--
-- DET 4/8/2009 EDK 11.2
-- ~~~~~~
-- - Added blk_mem_gen_v3_2
-- ^^^^^^
--
-- DET 4/9/2009 EDK 11.2
-- ~~~~~~
-- - Added fifo_generator_v5_2
-- ^^^^^^
--
-- DET 2/9/2010 For EDK 12.1
-- ~~~~~~
-- - Added fifo_generator_v5_3
-- - Added blk_mem_gen_v3_3
-- ^^^^^^
--
-- DET 3/10/2010 For EDK 12.x
-- ~~~~~~
-- -- Per CR553307
-- - Added fifo_generator_v6_1
-- - Added blk_mem_gen_v4_1
-- ^^^^^^
--
-- DET 3/17/2010 Initial
-- ~~~~~~
-- -- Per CR554253
-- - Incorporated changes to comment out FLOP_DELAY parameter from the
-- blk_mem_gen_v4_1 component. This parameter is on the XilinxCoreLib
-- model for blk_mem_gen_v4_1 but is declared as a TIME type for the
-- vhdl version and an integer for the verilog.
-- ^^^^^^
--
-- DET 10/04/2010 EDK 13.1
-- ~~~~~~
-- - Added fifo_generator_v7_3
-- - Added blk_mem_gen_v5_2
-- ^^^^^^
--
-- DET 12/8/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR586109
-- - Replaced fifo_generator v7.3 with v8.1
-- - Added blk_mem_gen_v6_1
-- ^^^^^^
--
-- DET 12/17/2010 EDK 13.1
-- ~~~~~~
-- -- Per CR587494
-- - Removed blk_mem_gen v6_1
-- ^^^^^^
--
-- DET 3/2/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR595473
-- - Update to use fifo_generator_v8_2
-- - Update to use blk_mem_gen_v6_2
-- - Remove out of date components.
-- ^^^^^^
--
-- DET 3/3/2011 EDK 13.2
-- ~~~~~~
-- - Removed C_ELABORATION_DIR parameter from the component decalarion
-- ^^^^^^
--
-- DET 3/7/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR596052
-- - Added removed fifo generator and Blk Mem Gen components back into
-- coregen_comp_defs.
-- ^^^^^^
--
-- RBODDU 08/18/2011 EDK 13.3
-- ~~~~~~
-- - Update to use fifo_generator_v8_3
-- ^^^^^^
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
library fifo_generator_v11_0;
use fifo_generator_v11_0.all;
library blk_mem_gen_v8_1;
use blk_mem_gen_v8_1.all;
PACKAGE coregen_comp_defs IS
--------------------------------------------------------
-- Declare general attributes used in this file
-- for defining each component being used with
-- the generatecore utility
attribute box_type: string;
attribute GENERATOR_DEFAULT: string;
-------------------------------------------------------
-------------------------------------------------------------------------------------
-- Start FIFO Generator Component for fifo_generator_v11_0
-- The Component declaration for fifo_generator_v11_0 pulled from the
-- Coregen version of
-- file: fifo_generator_v11_0_comp.vhd.
--
-- This component is used for both dual clock (async) and synchronous fifos
-- implemented with BRAM or distributed RAM. Hard FIFO simulation support may not
-- be provided in FIFO Generator V10.0 so not supported here.
--
-- Note: AXI ports and parameters added for this version of FIFO Generator.
--
-------------------------------------------------------------------------------------
COMPONENT fifo_generator_v11_0
GENERIC (
-------------------------------------------------------------------------
-- Generic Declarations
-------------------------------------------------------------------------
C_COMMON_CLOCK : integer := 0;
C_COUNT_TYPE : integer := 0;
C_DATA_COUNT_WIDTH : integer := 2;
C_DEFAULT_VALUE : string := "";
C_DIN_WIDTH : integer := 8;
C_DOUT_RST_VAL : string := "";
C_DOUT_WIDTH : integer := 8;
C_ENABLE_RLOCS : integer := 0;
C_FAMILY : string := "virtex6";
C_FULL_FLAGS_RST_VAL : integer := 1;
C_HAS_ALMOST_EMPTY : integer := 0;
C_HAS_ALMOST_FULL : integer := 0;
C_HAS_BACKUP : integer := 0;
C_HAS_DATA_COUNT : integer := 0;
C_HAS_INT_CLK : integer := 0;
C_HAS_MEMINIT_FILE : integer := 0;
C_HAS_OVERFLOW : integer := 0;
C_HAS_RD_DATA_COUNT : integer := 0;
C_HAS_RD_RST : integer := 0;
C_HAS_RST : integer := 1;
C_HAS_SRST : integer := 0;
C_HAS_UNDERFLOW : integer := 0;
C_HAS_VALID : integer := 0;
C_HAS_WR_ACK : integer := 0;
C_HAS_WR_DATA_COUNT : integer := 0;
C_HAS_WR_RST : integer := 0;
C_IMPLEMENTATION_TYPE : integer := 0;
C_INIT_WR_PNTR_VAL : integer := 0;
C_MEMORY_TYPE : integer := 1;
C_MIF_FILE_NAME : string := "";
C_OPTIMIZATION_MODE : integer := 0;
C_OVERFLOW_LOW : integer := 0;
C_PRELOAD_LATENCY : integer := 1;
C_PRELOAD_REGS : integer := 0;
C_PRIM_FIFO_TYPE : string := "4kx4";
C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0;
C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0;
C_PROG_EMPTY_TYPE : integer := 0;
C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0;
C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0;
C_PROG_FULL_TYPE : integer := 0;
C_RD_DATA_COUNT_WIDTH : integer := 2;
C_RD_DEPTH : integer := 256;
C_RD_FREQ : integer := 1;
C_RD_PNTR_WIDTH : integer := 8;
C_UNDERFLOW_LOW : integer := 0;
C_USE_DOUT_RST : integer := 0;
C_USE_ECC : integer := 0;
C_USE_EMBEDDED_REG : integer := 0;
C_USE_FIFO16_FLAGS : integer := 0;
C_USE_FWFT_DATA_COUNT : integer := 0;
C_VALID_LOW : integer := 0;
C_WR_ACK_LOW : integer := 0;
C_WR_DATA_COUNT_WIDTH : integer := 2;
C_WR_DEPTH : integer := 256;
C_WR_FREQ : integer := 1;
C_WR_PNTR_WIDTH : integer := 8;
C_WR_RESPONSE_LATENCY : integer := 1;
C_MSGON_VAL : integer := 1;
C_ENABLE_RST_SYNC : integer := 1;
C_ERROR_INJECTION_TYPE : integer := 0;
C_SYNCHRONIZER_STAGE : integer := 2;
-- AXI Interface related parameters start here
C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI4 Stream; 2: AXI4/AXI3
C_AXI_TYPE : integer := 0; -- 1: AXI4; 2: AXI4 Lite; 3: AXI3
C_HAS_AXI_WR_CHANNEL : integer := 0;
C_HAS_AXI_RD_CHANNEL : integer := 0;
C_HAS_SLAVE_CE : integer := 0;
C_HAS_MASTER_CE : integer := 0;
C_ADD_NGC_CONSTRAINT : integer := 0;
C_USE_COMMON_OVERFLOW : integer := 0;
C_USE_COMMON_UNDERFLOW : integer := 0;
C_USE_DEFAULT_SETTINGS : integer := 0;
-- AXI Full/Lite
C_AXI_ID_WIDTH : integer := 4;
C_AXI_ADDR_WIDTH : integer := 32;
C_AXI_DATA_WIDTH : integer := 64;
C_AXI_LEN_WIDTH : integer := 8;
C_AXI_LOCK_WIDTH : integer := 2;
C_HAS_AXI_ID : integer := 0;
C_HAS_AXI_AWUSER : integer := 0;
C_HAS_AXI_WUSER : integer := 0;
C_HAS_AXI_BUSER : integer := 0;
C_HAS_AXI_ARUSER : integer := 0;
C_HAS_AXI_RUSER : integer := 0;
C_AXI_ARUSER_WIDTH : integer := 1;
C_AXI_AWUSER_WIDTH : integer := 1;
C_AXI_WUSER_WIDTH : integer := 1;
C_AXI_BUSER_WIDTH : integer := 1;
C_AXI_RUSER_WIDTH : integer := 1;
-- AXI Streaming
C_HAS_AXIS_TDATA : integer := 0;
C_HAS_AXIS_TID : integer := 0;
C_HAS_AXIS_TDEST : integer := 0;
C_HAS_AXIS_TUSER : integer := 0;
C_HAS_AXIS_TREADY : integer := 1;
C_HAS_AXIS_TLAST : integer := 0;
C_HAS_AXIS_TSTRB : integer := 0;
C_HAS_AXIS_TKEEP : integer := 0;
C_AXIS_TDATA_WIDTH : integer := 64;
C_AXIS_TID_WIDTH : integer := 8;
C_AXIS_TDEST_WIDTH : integer := 4;
C_AXIS_TUSER_WIDTH : integer := 4;
C_AXIS_TSTRB_WIDTH : integer := 4;
C_AXIS_TKEEP_WIDTH : integer := 4;
-- AXI Channel Type
-- WACH --> Write Address Channel
-- WDCH --> Write Data Channel
-- WRCH --> Write Response Channel
-- RACH --> Read Address Channel
-- RDCH --> Read Data Channel
-- AXIS --> AXI Streaming
C_WACH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic
C_WDCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_WRCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RACH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_RDCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
C_AXIS_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie
-- AXI Implementation Type
-- 1 = Common Clock Block RAM FIFO
-- 2 = Common Clock Distributed RAM FIFO
-- 5 = Common Clock Built-in FIFO
-- 11 = Independent Clock Block RAM FIFO
-- 12 = Independent Clock Distributed RAM FIFO
C_IMPLEMENTATION_TYPE_WACH : integer := 1;
C_IMPLEMENTATION_TYPE_WDCH : integer := 1;
C_IMPLEMENTATION_TYPE_WRCH : integer := 1;
C_IMPLEMENTATION_TYPE_RACH : integer := 1;
C_IMPLEMENTATION_TYPE_RDCH : integer := 1;
C_IMPLEMENTATION_TYPE_AXIS : integer := 1;
-- AXI FIFO Type
-- 0 = Data FIFO
-- 1 = Packet FIFO
-- 2 = Low Latency Sync FIFO
-- 3 = Low Latency Async FIFO
C_APPLICATION_TYPE_WACH : integer := 0;
C_APPLICATION_TYPE_WDCH : integer := 0;
C_APPLICATION_TYPE_WRCH : integer := 0;
C_APPLICATION_TYPE_RACH : integer := 0;
C_APPLICATION_TYPE_RDCH : integer := 0;
C_APPLICATION_TYPE_AXIS : integer := 0;
-- Enable ECC
-- 0 = ECC disabled
-- 1 = ECC enabled
C_USE_ECC_WACH : integer := 0;
C_USE_ECC_WDCH : integer := 0;
C_USE_ECC_WRCH : integer := 0;
C_USE_ECC_RACH : integer := 0;
C_USE_ECC_RDCH : integer := 0;
C_USE_ECC_AXIS : integer := 0;
-- ECC Error Injection Type
-- 0 = No Error Injection
-- 1 = Single Bit Error Injection
-- 2 = Double Bit Error Injection
-- 3 = Single Bit and Double Bit Error Injection
C_ERROR_INJECTION_TYPE_WACH : integer := 0;
C_ERROR_INJECTION_TYPE_WDCH : integer := 0;
C_ERROR_INJECTION_TYPE_WRCH : integer := 0;
C_ERROR_INJECTION_TYPE_RACH : integer := 0;
C_ERROR_INJECTION_TYPE_RDCH : integer := 0;
C_ERROR_INJECTION_TYPE_AXIS : integer := 0;
-- Input Data Width
-- Accumulation of all AXI input signal's width
C_DIN_WIDTH_WACH : integer := 32;
C_DIN_WIDTH_WDCH : integer := 64;
C_DIN_WIDTH_WRCH : integer := 2;
C_DIN_WIDTH_RACH : integer := 32;
C_DIN_WIDTH_RDCH : integer := 64;
C_DIN_WIDTH_AXIS : integer := 1;
C_WR_DEPTH_WACH : integer := 16;
C_WR_DEPTH_WDCH : integer := 1024;
C_WR_DEPTH_WRCH : integer := 16;
C_WR_DEPTH_RACH : integer := 16;
C_WR_DEPTH_RDCH : integer := 1024;
C_WR_DEPTH_AXIS : integer := 1024;
C_WR_PNTR_WIDTH_WACH : integer := 4;
C_WR_PNTR_WIDTH_WDCH : integer := 10;
C_WR_PNTR_WIDTH_WRCH : integer := 4;
C_WR_PNTR_WIDTH_RACH : integer := 4;
C_WR_PNTR_WIDTH_RDCH : integer := 10;
C_WR_PNTR_WIDTH_AXIS : integer := 10;
C_HAS_DATA_COUNTS_WACH : integer := 0;
C_HAS_DATA_COUNTS_WDCH : integer := 0;
C_HAS_DATA_COUNTS_WRCH : integer := 0;
C_HAS_DATA_COUNTS_RACH : integer := 0;
C_HAS_DATA_COUNTS_RDCH : integer := 0;
C_HAS_DATA_COUNTS_AXIS : integer := 0;
C_HAS_PROG_FLAGS_WACH : integer := 0;
C_HAS_PROG_FLAGS_WDCH : integer := 0;
C_HAS_PROG_FLAGS_WRCH : integer := 0;
C_HAS_PROG_FLAGS_RACH : integer := 0;
C_HAS_PROG_FLAGS_RDCH : integer := 0;
C_HAS_PROG_FLAGS_AXIS : integer := 0;
-- 0: No Programmable FULL
-- 1: Single Programmable FULL Threshold Constant
-- 3: Single Programmable FULL Threshold Input Port
C_PROG_FULL_TYPE_WACH : integer := 5;
C_PROG_FULL_TYPE_WDCH : integer := 5;
C_PROG_FULL_TYPE_WRCH : integer := 5;
C_PROG_FULL_TYPE_RACH : integer := 5;
C_PROG_FULL_TYPE_RDCH : integer := 5;
C_PROG_FULL_TYPE_AXIS : integer := 5;
-- Single Programmable FULL Threshold Constant Assert Value
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer := 1023;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer := 1023;
-- 0: No Programmable EMPTY
-- 1: Single Programmable EMPTY Threshold Constant
-- 3: Single Programmable EMPTY Threshold Input Port
C_PROG_EMPTY_TYPE_WACH : integer := 5;
C_PROG_EMPTY_TYPE_WDCH : integer := 5;
C_PROG_EMPTY_TYPE_WRCH : integer := 5;
C_PROG_EMPTY_TYPE_RACH : integer := 5;
C_PROG_EMPTY_TYPE_RDCH : integer := 5;
C_PROG_EMPTY_TYPE_AXIS : integer := 5;
-- Single Programmable EMPTY Threshold Constant Assert Value
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer := 1022;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer := 1022;
C_REG_SLICE_MODE_WACH : integer := 0;
C_REG_SLICE_MODE_WDCH : integer := 0;
C_REG_SLICE_MODE_WRCH : integer := 0;
C_REG_SLICE_MODE_RACH : integer := 0;
C_REG_SLICE_MODE_RDCH : integer := 0;
C_REG_SLICE_MODE_AXIS : integer := 0
);
PORT(
------------------------------------------------------------------------------
-- Input and Output Declarations
------------------------------------------------------------------------------
-- Conventional FIFO Interface Signals
backup : in std_logic := '0';
backup_marker : in std_logic := '0';
clk : in std_logic := '0';
rst : in std_logic := '0';
srst : in std_logic := '0';
wr_clk : in std_logic := '0';
wr_rst : in std_logic := '0';
rd_clk : in std_logic := '0';
rd_rst : in std_logic := '0';
din : in std_logic_vector(C_DIN_WIDTH-1 downto 0) := (others => '0');
wr_en : in std_logic := '0';
rd_en : in std_logic := '0';
-- optional inputs
prog_empty_thresh : in std_logic_vector(C_RD_PNTR_WIDTH-1 downto 0) := (others => '0');
prog_empty_thresh_assert : in std_logic_vector(C_RD_PNTR_WIDTH-1 downto 0) := (others => '0');
prog_empty_thresh_negate : in std_logic_vector(C_RD_PNTR_WIDTH-1 downto 0) := (others => '0');
prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH-1 downto 0) := (others => '0');
prog_full_thresh_assert : in std_logic_vector(C_WR_PNTR_WIDTH-1 downto 0) := (others => '0');
prog_full_thresh_negate : in std_logic_vector(C_WR_PNTR_WIDTH-1 downto 0) := (others => '0');
int_clk : in std_logic := '0';
injectdbiterr : in std_logic := '0';
injectsbiterr : in std_logic := '0';
dout : out std_logic_vector(C_DOUT_WIDTH-1 downto 0) := (others => '0');
full : out std_logic := '0';
almost_full : out std_logic := '0';
wr_ack : out std_logic := '0';
overflow : out std_logic := '0';
empty : out std_logic := '1';
almost_empty : out std_logic := '1';
valid : out std_logic := '0';
underflow : out std_logic := '0';
data_count : out std_logic_vector(C_DATA_COUNT_WIDTH-1 downto 0) := (others => '0');
rd_data_count : out std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 downto 0) := (others => '0');
wr_data_count : out std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 downto 0) := (others => '0');
prog_full : out std_logic := '0';
prog_empty : out std_logic := '1';
sbiterr : out std_logic := '0';
dbiterr : out std_logic := '0';
-- axi global signal
m_aclk : in std_logic := '0';
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '1'; -- Active low reset, default value set to 1
m_aclk_en : in std_logic := '0';
s_aclk_en : in std_logic := '0';
-- axi full/lite slave write channel (write side)
s_axi_awid : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(C_AXI_LEN_WIDTH-1 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(3-1 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(2-1 downto 0) := (others => '0');
s_axi_awlock : in std_logic_vector(C_AXI_LOCK_WIDTH-1 downto 0) := (others => '0');
s_axi_awcache : in std_logic_vector(4-1 downto 0) := (others => '0');
s_axi_awprot : in std_logic_vector(3-1 downto 0) := (others => '0');
s_axi_awqos : in std_logic_vector(4-1 downto 0) := (others => '0');
s_axi_awregion : in std_logic_vector(4-1 downto 0) := (others => '0');
s_axi_awuser : in std_logic_vector(C_AXI_AWUSER_WIDTH-1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic := '0';
s_axi_wid : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
s_axi_wdata : in std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(C_AXI_DATA_WIDTH/8-1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wuser : in std_logic_vector(C_AXI_WUSER_WIDTH-1 downto 0) := (others => '0');
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic := '0';
s_axi_bid : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
s_axi_bresp : out std_logic_vector(2-1 downto 0) := (others => '0');
s_axi_buser : out std_logic_vector(C_AXI_BUSER_WIDTH-1 downto 0) := (others => '0');
s_axi_bvalid : out std_logic := '0';
s_axi_bready : in std_logic := '0';
-- axi full/lite master write channel (read side)
m_axi_awid : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
m_axi_awaddr : out std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
m_axi_awlen : out std_logic_vector(C_AXI_LEN_WIDTH-1 downto 0) := (others => '0');
m_axi_awsize : out std_logic_vector(3-1 downto 0) := (others => '0');
m_axi_awburst : out std_logic_vector(2-1 downto 0) := (others => '0');
m_axi_awlock : out std_logic_vector(C_AXI_LOCK_WIDTH-1 downto 0) := (others => '0');
m_axi_awcache : out std_logic_vector(4-1 downto 0) := (others => '0');
m_axi_awprot : out std_logic_vector(3-1 downto 0) := (others => '0');
m_axi_awqos : out std_logic_vector(4-1 downto 0) := (others => '0');
m_axi_awregion : out std_logic_vector(4-1 downto 0) := (others => '0');
m_axi_awuser : out std_logic_vector(C_AXI_AWUSER_WIDTH-1 downto 0) := (others => '0');
m_axi_awvalid : out std_logic := '0';
m_axi_awready : in std_logic := '0';
m_axi_wid : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
m_axi_wdata : out std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
m_axi_wstrb : out std_logic_vector(C_AXI_DATA_WIDTH/8-1 downto 0) := (others => '0');
m_axi_wlast : out std_logic := '0';
m_axi_wuser : out std_logic_vector(C_AXI_WUSER_WIDTH-1 downto 0) := (others => '0');
m_axi_wvalid : out std_logic := '0';
m_axi_wready : in std_logic := '0';
m_axi_bid : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
m_axi_bresp : in std_logic_vector(2-1 downto 0) := (others => '0');
m_axi_buser : in std_logic_vector(C_AXI_BUSER_WIDTH-1 downto 0) := (others => '0');
m_axi_bvalid : in std_logic := '0';
m_axi_bready : out std_logic := '0';
-- axi full/lite slave read channel (write side)
s_axi_arid : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(C_AXI_LEN_WIDTH-1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(3-1 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(2-1 downto 0) := (others => '0');
s_axi_arlock : in std_logic_vector(C_AXI_LOCK_WIDTH-1 downto 0) := (others => '0');
s_axi_arcache : in std_logic_vector(4-1 downto 0) := (others => '0');
s_axi_arprot : in std_logic_vector(3-1 downto 0) := (others => '0');
s_axi_arqos : in std_logic_vector(4-1 downto 0) := (others => '0');
s_axi_arregion : in std_logic_vector(4-1 downto 0) := (others => '0');
s_axi_aruser : in std_logic_vector(C_AXI_ARUSER_WIDTH-1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic := '0';
s_axi_rid : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
s_axi_rdata : out std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
s_axi_rresp : out std_logic_vector(2-1 downto 0) := (others => '0');
s_axi_rlast : out std_logic := '0';
s_axi_ruser : out std_logic_vector(C_AXI_RUSER_WIDTH-1 downto 0) := (others => '0');
s_axi_rvalid : out std_logic := '0';
s_axi_rready : in std_logic := '0';
-- axi full/lite master read channel (read side)
m_axi_arid : out std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
m_axi_araddr : out std_logic_vector(C_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
m_axi_arlen : out std_logic_vector(C_AXI_LEN_WIDTH-1 downto 0) := (others => '0');
m_axi_arsize : out std_logic_vector(3-1 downto 0) := (others => '0');
m_axi_arburst : out std_logic_vector(2-1 downto 0) := (others => '0');
m_axi_arlock : out std_logic_vector(C_AXI_LOCK_WIDTH-1 downto 0) := (others => '0');
m_axi_arcache : out std_logic_vector(4-1 downto 0) := (others => '0');
m_axi_arprot : out std_logic_vector(3-1 downto 0) := (others => '0');
m_axi_arqos : out std_logic_vector(4-1 downto 0) := (others => '0');
m_axi_arregion : out std_logic_vector(4-1 downto 0) := (others => '0');
m_axi_aruser : out std_logic_vector(C_AXI_ARUSER_WIDTH-1 downto 0) := (others => '0');
m_axi_arvalid : out std_logic := '0';
m_axi_arready : in std_logic := '0';
m_axi_rid : in std_logic_vector(C_AXI_ID_WIDTH-1 downto 0) := (others => '0');
m_axi_rdata : in std_logic_vector(C_AXI_DATA_WIDTH-1 downto 0) := (others => '0');
m_axi_rresp : in std_logic_vector(2-1 downto 0) := (others => '0');
m_axi_rlast : in std_logic := '0';
m_axi_ruser : in std_logic_vector(C_AXI_RUSER_WIDTH-1 downto 0) := (others => '0');
m_axi_rvalid : in std_logic := '0';
m_axi_rready : out std_logic := '0';
-- axi streaming slave signals (write side)
s_axis_tvalid : in std_logic := '0';
s_axis_tready : out std_logic := '0';
s_axis_tdata : in std_logic_vector(C_AXIS_TDATA_WIDTH-1 downto 0) := (others => '0');
s_axis_tstrb : in std_logic_vector(C_AXIS_TSTRB_WIDTH-1 downto 0) := (others => '0');
s_axis_tkeep : in std_logic_vector(C_AXIS_TKEEP_WIDTH-1 downto 0) := (others => '0');
s_axis_tlast : in std_logic := '0';
s_axis_tid : in std_logic_vector(C_AXIS_TID_WIDTH-1 downto 0) := (others => '0');
s_axis_tdest : in std_logic_vector(C_AXIS_TDEST_WIDTH-1 downto 0) := (others => '0');
s_axis_tuser : in std_logic_vector(C_AXIS_TUSER_WIDTH-1 downto 0) := (others => '0');
-- axi streaming master signals (read side)
m_axis_tvalid : out std_logic := '0';
m_axis_tready : in std_logic := '0';
m_axis_tdata : out std_logic_vector(C_AXIS_TDATA_WIDTH-1 downto 0) := (others => '0');
m_axis_tstrb : out std_logic_vector(C_AXIS_TSTRB_WIDTH-1 downto 0) := (others => '0');
m_axis_tkeep : out std_logic_vector(C_AXIS_TKEEP_WIDTH-1 downto 0) := (others => '0');
m_axis_tlast : out std_logic := '0';
m_axis_tid : out std_logic_vector(C_AXIS_TID_WIDTH-1 downto 0) := (others => '0');
m_axis_tdest : out std_logic_vector(C_AXIS_TDEST_WIDTH-1 downto 0) := (others => '0');
m_axis_tuser : out std_logic_vector(C_AXIS_TUSER_WIDTH-1 downto 0) := (others => '0');
-- axi full/lite write address channel signals
axi_aw_injectsbiterr : in std_logic := '0';
axi_aw_injectdbiterr : in std_logic := '0';
axi_aw_prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 downto 0) := (others => '0');
axi_aw_prog_empty_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 downto 0) := (others => '0');
axi_aw_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WACH downto 0) := (others => '0');
axi_aw_wr_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WACH downto 0) := (others => '0');
axi_aw_rd_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WACH downto 0) := (others => '0');
axi_aw_sbiterr : out std_logic := '0';
axi_aw_dbiterr : out std_logic := '0';
axi_aw_overflow : out std_logic := '0';
axi_aw_underflow : out std_logic := '0';
axi_aw_prog_full : out std_logic := '0';
axi_aw_prog_empty : out std_logic := '1';
-- axi_aw_almost_full : out std_logic := '0';
-- axi_aw_almost_empty : out std_logic := '1';
-- axi full/lite write data channel signals
axi_w_injectsbiterr : in std_logic := '0';
axi_w_injectdbiterr : in std_logic := '0';
axi_w_prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 downto 0) := (others => '0');
axi_w_prog_empty_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 downto 0) := (others => '0');
axi_w_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WDCH downto 0) := (others => '0');
axi_w_wr_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WDCH downto 0) := (others => '0');
axi_w_rd_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WDCH downto 0) := (others => '0');
axi_w_sbiterr : out std_logic := '0';
axi_w_dbiterr : out std_logic := '0';
axi_w_overflow : out std_logic := '0';
axi_w_underflow : out std_logic := '0';
axi_w_prog_full : out std_logic := '0';
axi_w_prog_empty : out std_logic := '1';
-- axi_w_almost_full : out std_logic := '0';
-- axi_w_almost_empty : out std_logic := '1';
-- axi full/lite write response channel signals
axi_b_injectsbiterr : in std_logic := '0';
axi_b_injectdbiterr : in std_logic := '0';
axi_b_prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 downto 0) := (others => '0');
axi_b_prog_empty_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 downto 0) := (others => '0');
axi_b_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WRCH downto 0) := (others => '0');
axi_b_wr_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WRCH downto 0) := (others => '0');
axi_b_rd_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_WRCH downto 0) := (others => '0');
axi_b_sbiterr : out std_logic := '0';
axi_b_dbiterr : out std_logic := '0';
axi_b_overflow : out std_logic := '0';
axi_b_underflow : out std_logic := '0';
axi_b_prog_full : out std_logic := '0';
axi_b_prog_empty : out std_logic := '1';
-- axi_b_almost_full : out std_logic := '0';
-- axi_b_almost_empty : out std_logic := '1';
-- axi full/lite read address channel signals
axi_ar_injectsbiterr : in std_logic := '0';
axi_ar_injectdbiterr : in std_logic := '0';
axi_ar_prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 downto 0) := (others => '0');
axi_ar_prog_empty_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 downto 0) := (others => '0');
axi_ar_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_RACH downto 0) := (others => '0');
axi_ar_wr_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_RACH downto 0) := (others => '0');
axi_ar_rd_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_RACH downto 0) := (others => '0');
axi_ar_sbiterr : out std_logic := '0';
axi_ar_dbiterr : out std_logic := '0';
axi_ar_overflow : out std_logic := '0';
axi_ar_underflow : out std_logic := '0';
axi_ar_prog_full : out std_logic := '0';
axi_ar_prog_empty : out std_logic := '1';
-- axi_ar_almost_full : out std_logic := '0';
-- axi_ar_almost_empty : out std_logic := '1';
-- axi full/lite read data channel signals
axi_r_injectsbiterr : in std_logic := '0';
axi_r_injectdbiterr : in std_logic := '0';
axi_r_prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 downto 0) := (others => '0');
axi_r_prog_empty_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 downto 0) := (others => '0');
axi_r_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_RDCH downto 0) := (others => '0');
axi_r_wr_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_RDCH downto 0) := (others => '0');
axi_r_rd_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_RDCH downto 0) := (others => '0');
axi_r_sbiterr : out std_logic := '0';
axi_r_dbiterr : out std_logic := '0';
axi_r_overflow : out std_logic := '0';
axi_r_underflow : out std_logic := '0';
axi_r_prog_full : out std_logic := '0';
axi_r_prog_empty : out std_logic := '1';
-- axi_r_almost_full : out std_logic := '0';
-- axi_r_almost_empty : out std_logic := '1';
-- axi streaming fifo related signals
axis_injectsbiterr : in std_logic := '0';
axis_injectdbiterr : in std_logic := '0';
axis_prog_full_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 downto 0) := (others => '0');
axis_prog_empty_thresh : in std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 downto 0) := (others => '0');
axis_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_AXIS downto 0) := (others => '0');
axis_wr_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_AXIS downto 0) := (others => '0');
axis_rd_data_count : out std_logic_vector(C_WR_PNTR_WIDTH_AXIS downto 0) := (others => '0');
axis_sbiterr : out std_logic := '0';
axis_dbiterr : out std_logic := '0';
axis_overflow : out std_logic := '0';
axis_underflow : out std_logic := '0';
axis_prog_full : out std_logic := '0';
axis_prog_empty : out std_logic := '1'
-- axis_almost_full : out std_logic := '0';
-- axis_almost_empty : out std_logic := '1'
);
END COMPONENT;
-- End FIFO Generator Component ---------------------------------------
-------------------------------------------------------------------------------------
-- Start Block Memory Generator Component for blk_mem_gen_v8_1
-- Component declaration for blk_mem_gen_v8_1 pulled from the
-- /proj/xbuilds/ids_14.4_P.49d.2.0/lin64/14.4/ISE_DS/ISE/vhdl/src/XilinxCoreLib
-- file: blk_mem_gen_v8_1.v
-- Verilog file used to match paramter order for NCSIM compatibility
-------------------------------------------------------------------------------------
component blk_mem_gen_v8_1 IS
GENERIC (
C_FAMILY : STRING := "virtex6";
C_XDEVICEFAMILY : STRING := "virtex6";
C_ELABORATION_DIR : STRING := "";
C_INTERFACE_TYPE : INTEGER := 0;
C_USE_BRAM_BLOCK : INTEGER := 0;
C_ENABLE_32BIT_ADDRESS : INTEGER := 0;
C_AXI_TYPE : INTEGER := 0;
C_AXI_SLAVE_TYPE : INTEGER := 0;
C_HAS_AXI_ID : INTEGER := 0;
C_AXI_ID_WIDTH : INTEGER := 4;
C_MEM_TYPE : INTEGER := 2;
C_BYTE_SIZE : INTEGER := 8;
C_ALGORITHM : INTEGER := 2;
C_PRIM_TYPE : INTEGER := 3;
C_LOAD_INIT_FILE : INTEGER := 0;
C_INIT_FILE_NAME : STRING := "";
C_INIT_FILE : STRING := "";
C_USE_DEFAULT_DATA : INTEGER := 0;
C_DEFAULT_DATA : STRING := "";
C_RST_TYPE : STRING := "SYNC";
C_HAS_RSTA : INTEGER := 0;
C_RST_PRIORITY_A : STRING := "CE";
C_RSTRAM_A : INTEGER := 0;
C_INITA_VAL : STRING := "";
C_HAS_ENA : INTEGER := 1;
C_HAS_REGCEA : INTEGER := 0;
C_USE_BYTE_WEA : INTEGER := 0;
C_WEA_WIDTH : INTEGER := 1;
C_WRITE_MODE_A : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_A : INTEGER := 32;
C_READ_WIDTH_A : INTEGER := 32;
C_WRITE_DEPTH_A : INTEGER := 64;
C_READ_DEPTH_A : INTEGER := 64;
C_ADDRA_WIDTH : INTEGER := 6;
C_HAS_RSTB : INTEGER := 0;
C_RST_PRIORITY_B : STRING := "CE";
C_RSTRAM_B : INTEGER := 0;
C_INITB_VAL : STRING := "";
C_HAS_ENB : INTEGER := 1;
C_HAS_REGCEB : INTEGER := 0;
C_USE_BYTE_WEB : INTEGER := 0;
C_WEB_WIDTH : INTEGER := 1;
C_WRITE_MODE_B : STRING := "WRITE_FIRST";
C_WRITE_WIDTH_B : INTEGER := 32;
C_READ_WIDTH_B : INTEGER := 32;
C_WRITE_DEPTH_B : INTEGER := 64;
C_READ_DEPTH_B : INTEGER := 64;
C_ADDRB_WIDTH : INTEGER := 6;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER := 0;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER := 0;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER := 0;
C_MUX_PIPELINE_STAGES : INTEGER := 0;
C_USE_SOFTECC : INTEGER := 0;
C_USE_ECC : INTEGER := 0;
C_HAS_INJECTERR : INTEGER := 0;
C_SIM_COLLISION_CHECK : STRING := "NONE";
C_COMMON_CLK : INTEGER := 1;
C_DISABLE_WARN_BHV_COLL : INTEGER := 0;
C_DISABLE_WARN_BHV_RANGE : INTEGER := 0
);
PORT (
CLKA : IN STD_LOGIC := '0';
RSTA : IN STD_LOGIC := '0';
ENA : IN STD_LOGIC := '1';
REGCEA : IN STD_LOGIC := '1';
WEA : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRA : IN STD_LOGIC_VECTOR(C_ADDRA_WIDTH-1 DOWNTO 0):= (OTHERS => '0');
DINA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTA : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_A-1 DOWNTO 0);
CLKB : IN STD_LOGIC := '0';
RSTB : IN STD_LOGIC := '0';
ENB : IN STD_LOGIC := '1';
REGCEB : IN STD_LOGIC := '1';
WEB : IN STD_LOGIC_VECTOR(C_WEB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
ADDRB : IN STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0)
:= (OTHERS => '0');
DINB : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0)
:= (OTHERS => '0');
DOUTB : OUT STD_LOGIC_VECTOR(C_READ_WIDTH_B-1 DOWNTO 0);
INJECTSBITERR : IN STD_LOGIC := '0';
INJECTDBITERR : IN STD_LOGIC := '0';
SBITERR : OUT STD_LOGIC := '0';
DBITERR : OUT STD_LOGIC := '0';
RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0);
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_AClk : IN STD_LOGIC := '0';
S_ARESETN : IN STD_LOGIC := '0';
-- AXI Full/Lite Slave Write (write side)
S_AXI_AWID : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_AWVALID : IN STD_LOGIC := '0';
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(C_WRITE_WIDTH_A-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(C_WEA_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_WLAST : IN STD_LOGIC := '0';
S_AXI_WVALID : IN STD_LOGIC := '0';
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC := '0';
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(8-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
S_AXI_ARVALID : IN STD_LOGIC := '0';
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(C_WRITE_WIDTH_B-1 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(2-1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC := '0';
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC := '0';
S_AXI_INJECTDBITERR : IN STD_LOGIC := '0';
S_AXI_SBITERR : OUT STD_LOGIC := '0';
S_AXI_DBITERR : OUT STD_LOGIC := '0';
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(C_ADDRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT; --blk_mem_gen_v8_1
-- The following tells XST that blk_mem_gen_v8_1 is a black box which
-- should be generated command given by the value of this attribute
-- Note the fully qualified SIM (JAVA class) name that forms the
-- basis of the core
-- ATTRIBUTE box_type OF blk_mem_gen_v8_1 : COMPONENT IS "black_box";
-- ATTRIBUTE generator_default OF blk_mem_gen_v8_1 : COMPONENT IS
-- "generatecore com.xilinx.ip.blk_mem_gen_v8_1.blk_mem_gen_v8_1 -a map_qvirtex_to=virtex map_qrvirtex_to=virtex map_virtexe_to=virtex map_qvirtex2_to=virtex2 map_qrvirtex2_to=virtex2 map_spartan2_to=virtex map_spartan2e_to=virtex map_virtex5_to=virtex4 map_spartan3a_to=spartan3e spartan3an_to=spartan3e spartan3adsp_to=spartan3e ";
-- End Block Memory Generator Component for v7_1 -------------------------------
END coregen_comp_defs;
|
mit
|
HighlandersFRC/fpga
|
led_string_no_gpio/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_15/blk_mem_gen_v8_1/blk_mem_axi_read_wrapper.vhd
|
27
|
57813
|
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`protect end_protected
|
mit
|
HighlandersFRC/fpga
|
led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/blk_mem_gen_v8_1/blk_mem_gen_v8_1_defaults.vhd
|
27
|
32589
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 22384)
`protect data_block
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`protect end_protected
|
mit
|
HighlandersFRC/fpga
|
led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_gpio_0_0/blk_mem_gen_v8_1/blk_mem_gen_v8_1_defaults.vhd
|
27
|
32589
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 22384)
`protect data_block
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`protect end_protected
|
mit
|
HighlandersFRC/fpga
|
oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_9/fifo_generator_v11_0/builtin/fifo_generator_v11_0_builtin.vhd
|
19
|
49663
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 35024)
`protect data_block
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`protect end_protected
|
mit
|
HighlandersFRC/fpga
|
led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_quad_spi_0_0/fifo_generator_v11_0/builtin/fifo_generator_v11_0_builtin.vhd
|
19
|
49663
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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zeZXd9sb8Q==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
|
mit
|
HighlandersFRC/fpga
|
led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_xbar_0/fifo_generator_v11_0/builtin/fifo_generator_v11_0_builtin.vhd
|
19
|
49663
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 35024)
`protect data_block
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`protect end_protected
|
mit
|
HighlandersFRC/fpga
|
lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_9/fifo_generator_v11_0/builtin/fifo_generator_v11_0_builtin.vhd
|
19
|
49663
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 35024)
`protect data_block
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`protect end_protected
|
mit
|
HighlandersFRC/fpga
|
led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_quad_spi_0_0/proc_common_v4_0/hdl/src/vhdl/or_gate_f.vhd
|
15
|
9178
|
-------------------------------------------------------------------------------
-- $Id: or_gate_f.vhd,v 1.1.4.2 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_gate_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_gate_f.vhd
--
-- Description: OR gates. The width of each OR gate (C_OR_WIDTH)
-- and the number of or gates (C_BUS_WIDTH) are
-- parameterizable.
--
-- Y(j) <= A(j) OR A(C_BUS_WIDTH+j)
-- OR A(2*C_BUS_WIDTH+j)
-- ...
-- OR A((C_OR_WIDTH-1)*C_BUS_WIDTH+j),
--
-- for 0 <= j < C_BUS_WIDTH
--
-- If C_FAMILY is set (or left defaulted) to "nofamily"
-- then the implementation will be by synthesis inference.
-- Otherwise, a structural implementation optimized to
-- C_FAMILY may be generated, depending on whether
-- C_FAMILY supports the needed primtives.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- or_gate_f.vhd
--
-------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 2006-12-11
-- ^^^^^^
-- First Version, derived from or_gate by BLT
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library proc_common_v4_0;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_OR_WIDTH -- Which Xilinx FPGA family to target when
-- syntesizing, affect the RLOC string values
-- C_BUS_WIDTH -- Which Y position the RLOC should start from
--
-- Definition of Ports:
-- A -- Input. Input buses are concatenated together to
-- form input A. Example: to OR buses R, S, and T,
-- assign A <= R & S & T;
-- Y -- Output. Same width as input buses.
--
-------------------------------------------------------------------------------
entity or_gate_f is
generic (
C_OR_WIDTH : natural := 17;
C_BUS_WIDTH : natural := 1;
C_FAMILY : string := "nofamily"
);
port (
A : in std_logic_vector(0 to C_OR_WIDTH*C_BUS_WIDTH-1);
Y : out std_logic_vector(0 to C_BUS_WIDTH-1)
);
end entity or_gate_f;
architecture imp of or_gate_f is
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
signal test : std_logic_vector(0 to C_BUS_WIDTH-1);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
BUS_WIDTH_FOR_GEN: for i in 0 to C_BUS_WIDTH-1 generate
signal in_Bus : std_logic_vector(0 to C_OR_WIDTH-1);
begin
ORDER_INPUT_BUS_PROCESS: process( A ) is
begin
for k in 0 to C_OR_WIDTH-1 loop
in_Bus(k) <= A(k*C_BUS_WIDTH+i);
end loop;
end process ORDER_INPUT_BUS_PROCESS;
OR_BITS_I: entity proc_common_v4_0.or_muxcy_f
generic map (
C_NUM_BITS => C_OR_WIDTH,
C_FAMILY => C_FAMILY
)
port map (
In_bus => in_Bus, --[in]
Or_out => Y(i) --[out]
);
end generate BUS_WIDTH_FOR_GEN;
end architecture imp;
|
mit
|
HighlandersFRC/fpga
|
led_string_no_gpio/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_15/blk_mem_gen_v8_1/blk_mem_gen_generic_cstr.vhd
|
27
|
120556
|
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`protect end_protected
|
mit
|
HighlandersFRC/fpga
|
lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/blk_mem_gen_v8_1/blk_mem_gen_generic_cstr.vhd
|
27
|
120556
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 87504)
`protect data_block
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`protect end_protected
|
mit
|
fupolarbear/THU-Class-CO-makecomputer
|
src/VGA/ipcore_dir/blk_mem_gen_v7_3/simulation/blk_mem_gen_v7_3_tb.vhd
|
3
|
4370
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: blk_mem_gen_v7_3_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY blk_mem_gen_v7_3_tb IS
END ENTITY;
ARCHITECTURE blk_mem_gen_v7_3_tb_ARCH OF blk_mem_gen_v7_3_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
blk_mem_gen_v7_3_synth_inst:ENTITY work.blk_mem_gen_v7_3_synth
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
mit
|
HighlandersFRC/fpga
|
oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/proc_common_v4_0/hdl/src/vhdl/ipif_mirror128.vhd
|
15
|
17011
|
--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: ipif_mirror128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- ipif_mirror128 - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_steer128.vhd
-- Version: v1.00b
-- Description: Read and Write Steering logic for IPIF
--
-- For writes, this logic mirrors data from the master with
-- the smaller bus width to the correct byte lanes of the
-- larger IPIF devices. The BE signals are also mirrored.
--
-- For reads, the Decode_size signal determines how read
-- data is steered onto the byte lanes. To simplify the
-- logic, the read data is mirrored onto the entire data
-- bus, insuring that the lanes corrsponding to the BE's
-- have correct data.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ipif_steer128.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 10-10-2008 -- First version
-- ^^^^^^
-- First version of IPIF mirror logic.
-- ~~~~~~
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Port declarations
-- generic definitions:
-- C_DWIDTH : integer := width of IPIF Slave
-- C_SMALLEST : integer := width of smallest Master (not access size)
-- that will access the IPIF Slave
-- C_AWIDTH : integer := width of the host address bus attached to
-- the IPIF
-- port definitions:
-- Wr_Data_In : in Write Data In (from host data bus)
-- Rd_Data_In : in Read Data In (from IPIC data bus)
-- Addr : in Address bus from host address bus
-- BE_In : in Byte Enables In from host side
-- Decode_size : in Size of Master accessing slave
-- Size indication (Decode_size)
-- 00 - 32-Bit Master
-- 01 - 64-Bit Master
-- 10 - 128-Bit Master
-- 11 - 256-Bit Master (Not Support)
--
-- Wr_Data_Out : out Write Data Out (to IPIF data bus)
-- Rd_Data_Out : out Read Data Out (to host data bus)
-- BE_Out : out Byte Enables Out to IPIF side
--
-------------------------------------------------------------------------------
entity ipif_mirror128 is
generic (
C_DWIDTH : integer := 32; -- 64, 128 (Slave Dwidth)
C_SMALLEST : integer := 32; -- 32, 64, 128 (Smallest Master)
C_AWIDTH : integer := 32
);
port (
Wr_Addr : in std_logic_vector(0 to C_AWIDTH-1);
Wr_Size : in std_logic_vector(0 to 1);
Rd_Addr : in std_logic_vector(0 to C_AWIDTH-1);
Rd_Size : in std_logic_vector(0 to 1);
Wr_Data_In : in std_logic_vector(0 to C_DWIDTH-1);
Rd_Data_In : in std_logic_vector(0 to C_DWIDTH-1);
BE_In : in std_logic_vector(0 to C_DWIDTH/8-1);
Wr_Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
Rd_Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
BE_Out : out std_logic_vector(0 to C_DWIDTH/8-1)
);
end entity ipif_mirror128;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of ipif_mirror128 is
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
GEN_SAME: if C_DWIDTH <= C_SMALLEST generate
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
end generate GEN_SAME;
-------------------------------------------------------------------------------
-- Write Data Mirroring
-------------------------------------------------------------------------------
---------------------
-- 64 Bit Support --
---------------------
GEN_WR_64_32: if C_DWIDTH = 64 and C_SMALLEST = 32 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Wr_Addr,Wr_Data_In,BE_In,Wr_Size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
addr_bits <= Wr_Addr(C_AWIDTH-3); --a29
case addr_bits is
when '0' =>
case Wr_Size is
when "00" => -- 32-Bit Master
BE_Out(4 to 7) <= (others => '0');
when others => null;
end case;
when '1' =>
case Wr_Size is
when "00" => -- 32-Bit Master
Wr_Data_Out(32 to 63) <= Wr_Data_In(0 to 31);
BE_Out(4 to 7) <= BE_In(0 to 3);
BE_Out(0 to 3) <= (others => '0');
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_WR_64_32;
---------------------
-- 128 Bit Support --
---------------------
GEN_WR_128_32: if C_DWIDTH = 128 and C_SMALLEST = 32 generate
signal addr_bits : std_logic_vector(0 to 1);
begin
CONNECT_PROC: process (addr_bits,Wr_Addr,Wr_Data_In,BE_In,Wr_Size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
addr_bits <= Wr_Addr(C_AWIDTH-4 to C_AWIDTH-3);
case addr_bits is
when "00" => --0
case Wr_Size is
when "00" => -- 32-Bit Master
BE_Out(4 to 15) <= (others => '0');
when "01" => -- 64-Bit Master
BE_Out(8 to 15) <= (others => '0');
when others => null;
end case;
when "01" => --4
case Wr_Size is
when "00" => -- 32-Bit Master
Wr_Data_Out(32 to 63) <= Wr_Data_In(0 to 31);
BE_Out(4 to 7) <= BE_In(0 to 3);
BE_Out(0 to 3) <= (others => '0');
BE_Out(8 to 15) <= (others => '0');
when others => null;
end case;
when "10" => --8
case Wr_Size is
when "00" => -- 32-Bit Master
Wr_Data_Out(64 to 95) <= Wr_Data_In(0 to 31);
BE_Out(8 to 11) <= BE_In(0 to 3);
BE_Out(0 to 7) <= (others => '0');
BE_Out(12 to 15) <= (others => '0');
when "01" => -- 64-Bit Master
Wr_Data_Out(64 to 127) <= Wr_Data_In(0 to 63);
BE_Out(8 to 15) <= BE_In(0 to 7);
BE_Out(0 to 7) <= (others => '0');
when others => null;
end case;
when "11" => --C
case Wr_Size is
when "00" => --32-Bit Master
Wr_Data_Out(96 to 127) <= Wr_Data_In(0 to 31);
BE_Out(12 to 15) <= BE_In(0 to 3);
BE_Out(0 to 11) <= (others => '0');
when "01" => --64-Bit Master
Wr_Data_Out(64 to 127) <= Wr_Data_In(0 to 63);
BE_Out(8 to 15) <= BE_In(0 to 7);
BE_Out(0 to 7) <= (others => '0');
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_WR_128_32;
GEN_WR_128_64: if C_DWIDTH = 128 and C_SMALLEST = 64 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Wr_Addr,Wr_Data_In,BE_In,Wr_Size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
addr_bits <= Wr_Addr(C_AWIDTH-4);
case addr_bits is
when '0' =>
case Wr_Size is
when "01" => -- 64-Bit Master
BE_Out(8 to 15) <= (others => '0');
when others => null;
end case;
when '1' => --8
case Wr_Size is
when "01" => -- 64-Bit Master
Wr_Data_Out(64 to 127) <= Wr_Data_In(0 to 63);
BE_Out(8 to 15) <= BE_In(0 to 7);
BE_Out(0 to 7) <= (others => '0');
when others => null;
end case;
when others =>
null;
end case;
end process CONNECT_PROC;
end generate GEN_WR_128_64;
-------------------------------------------------------------------------------
-- Read Data Steering
-------------------------------------------------------------------------------
---------------------
-- 64 Bit Support --
---------------------
GEN_RD_64_32: if C_DWIDTH = 64 and C_SMALLEST = 32 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Rd_Addr,Rd_Data_In,Rd_Size)
begin
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Rd_Addr(C_AWIDTH-3); --a29
case addr_bits is
when '1' =>
case Rd_Size is
when "00" => -- 32-Bit Master
Rd_Data_Out(0 to 31) <= Rd_Data_In(32 to 63);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_RD_64_32;
---------------------
-- 128 Bit Support --
---------------------
GEN_RD_128_32: if C_DWIDTH = 128 and C_SMALLEST = 32 generate
signal addr_bits : std_logic_vector(0 to 1);
begin
CONNECT_PROC: process (addr_bits,Rd_Addr,Rd_Data_In,Rd_Size)
begin
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Rd_Addr(C_AWIDTH-4 to C_AWIDTH-3);
case addr_bits is
when "01" => --4
case Rd_Size is
when "00" => -- 32-Bit Master
Rd_Data_Out(0 to 31) <= Rd_Data_In(32 to 63);
when others => null;
end case;
when "10" => --8
case Rd_Size is
when "00" => -- 32-Bit Master
Rd_Data_Out(0 to 31) <= Rd_Data_In(64 to 95);
when "01" => -- 64-Bit Master
Rd_Data_Out(0 to 63) <= Rd_Data_In(64 to 127);
when others => null;
end case;
when "11" => --C
case Rd_Size is
when "00" => --32-Bit Master
Rd_Data_Out(0 to 31) <= Rd_Data_In(96 to 127);
when "01" => --64-Bit Master
Rd_Data_Out(0 to 63) <= Rd_Data_In(64 to 127);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_RD_128_32;
GEN_RD_128_64: if C_DWIDTH = 128 and C_SMALLEST = 64 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Rd_Addr,Rd_Data_In,Rd_Size)
begin
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Rd_Addr(C_AWIDTH-4);
case addr_bits is
when '1' => --8
case Rd_Size is
when "01" => -- 64-Bit Master
Rd_Data_Out(0 to 63) <= Rd_Data_In(64 to 127);
when others => null;
end case;
when others =>
null;
end case;
end process CONNECT_PROC;
end generate GEN_RD_128_64;
end architecture IMP;
|
mit
|
HighlandersFRC/fpga
|
led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/proc_common_v4_0/hdl/src/vhdl/ipif_mirror128.vhd
|
15
|
17011
|
--SINGLE_FILE_TAG
-------------------------------------------------------------------------------
-- $Id: ipif_mirror128.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- ipif_mirror128 - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ipif_steer128.vhd
-- Version: v1.00b
-- Description: Read and Write Steering logic for IPIF
--
-- For writes, this logic mirrors data from the master with
-- the smaller bus width to the correct byte lanes of the
-- larger IPIF devices. The BE signals are also mirrored.
--
-- For reads, the Decode_size signal determines how read
-- data is steered onto the byte lanes. To simplify the
-- logic, the read data is mirrored onto the entire data
-- bus, insuring that the lanes corrsponding to the BE's
-- have correct data.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ipif_steer128.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 10-10-2008 -- First version
-- ^^^^^^
-- First version of IPIF mirror logic.
-- ~~~~~~
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Port declarations
-- generic definitions:
-- C_DWIDTH : integer := width of IPIF Slave
-- C_SMALLEST : integer := width of smallest Master (not access size)
-- that will access the IPIF Slave
-- C_AWIDTH : integer := width of the host address bus attached to
-- the IPIF
-- port definitions:
-- Wr_Data_In : in Write Data In (from host data bus)
-- Rd_Data_In : in Read Data In (from IPIC data bus)
-- Addr : in Address bus from host address bus
-- BE_In : in Byte Enables In from host side
-- Decode_size : in Size of Master accessing slave
-- Size indication (Decode_size)
-- 00 - 32-Bit Master
-- 01 - 64-Bit Master
-- 10 - 128-Bit Master
-- 11 - 256-Bit Master (Not Support)
--
-- Wr_Data_Out : out Write Data Out (to IPIF data bus)
-- Rd_Data_Out : out Read Data Out (to host data bus)
-- BE_Out : out Byte Enables Out to IPIF side
--
-------------------------------------------------------------------------------
entity ipif_mirror128 is
generic (
C_DWIDTH : integer := 32; -- 64, 128 (Slave Dwidth)
C_SMALLEST : integer := 32; -- 32, 64, 128 (Smallest Master)
C_AWIDTH : integer := 32
);
port (
Wr_Addr : in std_logic_vector(0 to C_AWIDTH-1);
Wr_Size : in std_logic_vector(0 to 1);
Rd_Addr : in std_logic_vector(0 to C_AWIDTH-1);
Rd_Size : in std_logic_vector(0 to 1);
Wr_Data_In : in std_logic_vector(0 to C_DWIDTH-1);
Rd_Data_In : in std_logic_vector(0 to C_DWIDTH-1);
BE_In : in std_logic_vector(0 to C_DWIDTH/8-1);
Wr_Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
Rd_Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
BE_Out : out std_logic_vector(0 to C_DWIDTH/8-1)
);
end entity ipif_mirror128;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of ipif_mirror128 is
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
GEN_SAME: if C_DWIDTH <= C_SMALLEST generate
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
Rd_Data_Out <= Rd_Data_In;
end generate GEN_SAME;
-------------------------------------------------------------------------------
-- Write Data Mirroring
-------------------------------------------------------------------------------
---------------------
-- 64 Bit Support --
---------------------
GEN_WR_64_32: if C_DWIDTH = 64 and C_SMALLEST = 32 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Wr_Addr,Wr_Data_In,BE_In,Wr_Size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
addr_bits <= Wr_Addr(C_AWIDTH-3); --a29
case addr_bits is
when '0' =>
case Wr_Size is
when "00" => -- 32-Bit Master
BE_Out(4 to 7) <= (others => '0');
when others => null;
end case;
when '1' =>
case Wr_Size is
when "00" => -- 32-Bit Master
Wr_Data_Out(32 to 63) <= Wr_Data_In(0 to 31);
BE_Out(4 to 7) <= BE_In(0 to 3);
BE_Out(0 to 3) <= (others => '0');
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_WR_64_32;
---------------------
-- 128 Bit Support --
---------------------
GEN_WR_128_32: if C_DWIDTH = 128 and C_SMALLEST = 32 generate
signal addr_bits : std_logic_vector(0 to 1);
begin
CONNECT_PROC: process (addr_bits,Wr_Addr,Wr_Data_In,BE_In,Wr_Size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
addr_bits <= Wr_Addr(C_AWIDTH-4 to C_AWIDTH-3);
case addr_bits is
when "00" => --0
case Wr_Size is
when "00" => -- 32-Bit Master
BE_Out(4 to 15) <= (others => '0');
when "01" => -- 64-Bit Master
BE_Out(8 to 15) <= (others => '0');
when others => null;
end case;
when "01" => --4
case Wr_Size is
when "00" => -- 32-Bit Master
Wr_Data_Out(32 to 63) <= Wr_Data_In(0 to 31);
BE_Out(4 to 7) <= BE_In(0 to 3);
BE_Out(0 to 3) <= (others => '0');
BE_Out(8 to 15) <= (others => '0');
when others => null;
end case;
when "10" => --8
case Wr_Size is
when "00" => -- 32-Bit Master
Wr_Data_Out(64 to 95) <= Wr_Data_In(0 to 31);
BE_Out(8 to 11) <= BE_In(0 to 3);
BE_Out(0 to 7) <= (others => '0');
BE_Out(12 to 15) <= (others => '0');
when "01" => -- 64-Bit Master
Wr_Data_Out(64 to 127) <= Wr_Data_In(0 to 63);
BE_Out(8 to 15) <= BE_In(0 to 7);
BE_Out(0 to 7) <= (others => '0');
when others => null;
end case;
when "11" => --C
case Wr_Size is
when "00" => --32-Bit Master
Wr_Data_Out(96 to 127) <= Wr_Data_In(0 to 31);
BE_Out(12 to 15) <= BE_In(0 to 3);
BE_Out(0 to 11) <= (others => '0');
when "01" => --64-Bit Master
Wr_Data_Out(64 to 127) <= Wr_Data_In(0 to 63);
BE_Out(8 to 15) <= BE_In(0 to 7);
BE_Out(0 to 7) <= (others => '0');
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_WR_128_32;
GEN_WR_128_64: if C_DWIDTH = 128 and C_SMALLEST = 64 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Wr_Addr,Wr_Data_In,BE_In,Wr_Size)
begin
Wr_Data_Out <= Wr_Data_In;
BE_Out <= BE_In;
addr_bits <= Wr_Addr(C_AWIDTH-4);
case addr_bits is
when '0' =>
case Wr_Size is
when "01" => -- 64-Bit Master
BE_Out(8 to 15) <= (others => '0');
when others => null;
end case;
when '1' => --8
case Wr_Size is
when "01" => -- 64-Bit Master
Wr_Data_Out(64 to 127) <= Wr_Data_In(0 to 63);
BE_Out(8 to 15) <= BE_In(0 to 7);
BE_Out(0 to 7) <= (others => '0');
when others => null;
end case;
when others =>
null;
end case;
end process CONNECT_PROC;
end generate GEN_WR_128_64;
-------------------------------------------------------------------------------
-- Read Data Steering
-------------------------------------------------------------------------------
---------------------
-- 64 Bit Support --
---------------------
GEN_RD_64_32: if C_DWIDTH = 64 and C_SMALLEST = 32 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Rd_Addr,Rd_Data_In,Rd_Size)
begin
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Rd_Addr(C_AWIDTH-3); --a29
case addr_bits is
when '1' =>
case Rd_Size is
when "00" => -- 32-Bit Master
Rd_Data_Out(0 to 31) <= Rd_Data_In(32 to 63);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_RD_64_32;
---------------------
-- 128 Bit Support --
---------------------
GEN_RD_128_32: if C_DWIDTH = 128 and C_SMALLEST = 32 generate
signal addr_bits : std_logic_vector(0 to 1);
begin
CONNECT_PROC: process (addr_bits,Rd_Addr,Rd_Data_In,Rd_Size)
begin
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Rd_Addr(C_AWIDTH-4 to C_AWIDTH-3);
case addr_bits is
when "01" => --4
case Rd_Size is
when "00" => -- 32-Bit Master
Rd_Data_Out(0 to 31) <= Rd_Data_In(32 to 63);
when others => null;
end case;
when "10" => --8
case Rd_Size is
when "00" => -- 32-Bit Master
Rd_Data_Out(0 to 31) <= Rd_Data_In(64 to 95);
when "01" => -- 64-Bit Master
Rd_Data_Out(0 to 63) <= Rd_Data_In(64 to 127);
when others => null;
end case;
when "11" => --C
case Rd_Size is
when "00" => --32-Bit Master
Rd_Data_Out(0 to 31) <= Rd_Data_In(96 to 127);
when "01" => --64-Bit Master
Rd_Data_Out(0 to 63) <= Rd_Data_In(64 to 127);
when others => null;
end case;
when others => null;
end case;
end process CONNECT_PROC;
end generate GEN_RD_128_32;
GEN_RD_128_64: if C_DWIDTH = 128 and C_SMALLEST = 64 generate
signal addr_bits : std_logic;
begin
CONNECT_PROC: process (addr_bits,Rd_Addr,Rd_Data_In,Rd_Size)
begin
Rd_Data_Out <= Rd_Data_In;
addr_bits <= Rd_Addr(C_AWIDTH-4);
case addr_bits is
when '1' => --8
case Rd_Size is
when "01" => -- 64-Bit Master
Rd_Data_Out(0 to 63) <= Rd_Data_In(64 to 127);
when others => null;
end case;
when others =>
null;
end case;
end process CONNECT_PROC;
end generate GEN_RD_128_64;
end architecture IMP;
|
mit
|
HighlandersFRC/fpga
|
lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_9/fifo_generator_v11_0/ramfifo/wr_handshaking_flags.vhd
|
19
|
12657
|
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|
mit
|
HighlandersFRC/fpga
|
led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pselect_mask.vhd
|
15
|
13363
|
-------------------------------------------------------------------------------
-- $Id: pselect_mask.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- pselect_mask.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pselect_mask.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pselect_mask.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- goran 2002-02-06 First Version
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library Unisim;
use Unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- PS -- peripheral select
-------------------------------------------------------------------------------
entity pselect_mask is
generic (
C_AW : integer := 32;
C_BAR : std_logic_vector(0 to 31) := "00000000000000100000000000000000";
C_MASK : std_logic_vector(0 to 31) := "00000000000001111100000000000000"
);
port (
A : in std_logic_vector(0 to C_AW-1);
Valid : in std_logic;
CS : out std_logic
);
end entity pselect_mask;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
library unisim;
use unisim.all;
architecture imp of pselect_mask is
-- component LUT4
-- generic(
-- INIT : bit_vector := X"0000"
-- );
-- port (
-- O : out std_logic;
-- I0 : in std_logic := '0';
-- I1 : in std_logic := '0';
-- I2 : in std_logic := '0';
-- I3 : in std_logic := '0');
-- end component;
-- component MUXCY is
-- port (
-- O : out std_logic;
-- CI : in std_logic;
-- DI : in std_logic;
-- S : in std_logic
-- );
-- end component MUXCY;
function Nr_Of_Ones (S : std_logic_vector) return natural is
variable tmp : natural := 0;
begin -- function Nr_Of_Ones
for I in S'range loop
if (S(I) = '1') then
tmp := tmp + 1;
end if;
end loop; -- I
return tmp;
end function Nr_Of_Ones;
function fix_AB (B : boolean; I : integer) return integer is
begin -- function fix_AB
if (not B) then
return I + 1;
else
return I;
end if;
end function fix_AB;
constant Nr : integer := Nr_Of_Ones(C_MASK);
constant Use_CIN : boolean := ((Nr mod 4) = 0);
constant AB : integer := fix_AB(Use_CIN, Nr);
attribute INIT : string;
constant NUM_LUTS : integer := (AB-1)/4+1;
-- signal lut_out : std_logic_vector(0 to NUM_LUTS-1);
-- signal carry_chain : std_logic_vector(0 to NUM_LUTS);
-- function to initialize LUT within pselect
type int4 is array (3 downto 0) of integer;
function pselect_init_lut(i : integer;
AB : integer;
NUM_LUTS : integer;
C_AW : integer;
C_BAR : std_logic_vector(0 to 31))
return bit_vector is
variable init_vector : bit_vector(15 downto 0) := X"0001";
variable j : integer := 0;
variable val_in : int4;
begin
for j in 0 to 3 loop
if i < NUM_LUTS-1 or j <= ((AB-1) mod 4) then
val_in(j) := conv_integer(C_BAR(i*4+j));
else val_in(j) := 0;
end if;
end loop;
init_vector := To_bitvector(conv_std_logic_vector(2**(val_in(3)*8+
val_in(2)*4+val_in(1)*2+val_in(0)*1),16));
return init_vector;
end pselect_init_lut;
signal A_Bus : std_logic_vector(0 to AB);
signal BAR : std_logic_vector(0 to AB);
-------------------------------------------------------------------------------
-- Begin architecture section
-------------------------------------------------------------------------------
begin -- VHDL_RTL
Make_Busses : process (A,Valid) is
variable tmp : natural;
begin -- process Make_Busses
tmp := 0;
A_Bus <= (others => '0');
BAR <= (others => '0');
for I in C_MASK'range loop
if (C_MASK(I) = '1') then
A_Bus(tmp) <= A(I);
BAR(tmp) <= C_BAR(I);
tmp := tmp + 1;
end if;
end loop; -- I
if (not Use_CIN) then
BAR(tmp) <= '1';
A_Bus(tmp) <= Valid;
end if;
end process Make_Busses;
-- More_Than_3_Bits : if (AB > 3) generate
-- Using_CIn: if (Use_CIN) generate
-- carry_chain(0) <= Valid;
-- end generate Using_CIn;
-- No_CIn: if (not Use_CIN) generate
-- carry_chain(0) <= '1';
-- end generate No_CIn;
-- GEN_DECODE : for i in 0 to NUM_LUTS-1 generate
-- signal lut_in : std_logic_vector(3 downto 0);
-- begin
-- GEN_LUT_INPUTS : for j in 0 to 3 generate
-- -- Generate to assign address bits to LUT4 inputs
-- GEN_INPUT : if i < NUM_LUTS-1 or j <= ((AB-1) mod 4) generate
-- lut_in(j) <= A_Bus(i*4+j);
-- end generate;
-- -- Generate to assign zeros to remaining LUT4 inputs
-- GEN_ZEROS : if not(i < NUM_LUTS-1 or j <= ((AB-1) mod 4)) generate
-- lut_in(j) <= '0';
-- end generate;
-- end generate;
---------------------------------------------------------------------------------
---- RTL version without LUT instantiation for XST
---------------------------------------------------------------------------------
-- lut_out(i) <= (lut_in(0) xnor BAR(i*4+0)) and
-- (lut_in(1) xnor BAR(i*4+1)) and
-- (lut_in(2) xnor BAR(i*4+2)) and
-- (lut_in(3) xnor BAR(i*4+3));
---------------------------------------------------------------------------------
---- Structural version with LUT instantiation for Synplicity (when RLOC is
---- desired for placing LUT
---------------------------------------------------------------------------------
---- LUT4_I : LUT4
---- generic map(
---- -- Function init_lut is used to generate INIT value for LUT4
---- INIT => pselect_init_lut(i,C_AB,NUM_LUTS,C_AW,C_BAR)
---- )
---- port map (
---- O => lut_out(i), -- [out]
---- I0 => lut_in(0), -- [in]
---- I1 => lut_in(1), -- [in]
---- I2 => lut_in(2), -- [in]
---- I3 => lut_in(3)); -- [in]
---------------------------------------------------------------------------------
-- MUXCY_I : MUXCY
-- port map (
-- O => carry_chain(i+1), --[out]
-- CI => carry_chain(i), --[in]
-- DI => '0', --[in]
-- S => lut_out(i) --[in]
-- );
-- end generate;
-- CS <= carry_chain(NUM_LUTS); -- assign end of carry chain to output
-- end generate More_Than_3_Bits;
-- Less_than_4_bits: if (AB < 4) generate
CS <= Valid when A_Bus=BAR else '0';
-- end generate Less_than_4_bits;
end imp;
|
mit
|
HighlandersFRC/fpga
|
lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_9/fifo_generator_v11_0/common/input_blk.vhd
|
19
|
28006
|
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cQXfmo+TjiYJBGo=
`protect end_protected
|
mit
|
HighlandersFRC/fpga
|
led_string_no_gpio/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/fifo_generator_v11_0/common/input_blk.vhd
|
19
|
28006
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18992)
`protect data_block
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`protect end_protected
|
mit
|
HighlandersFRC/fpga
|
lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/counter_bit.vhd
|
15
|
8803
|
-------------------------------------------------------------------------------
-- counter_bit_imp.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_bit.vhd
--
-- Description: Implements 1 bit of the counter/timer
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_bit.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:46 $
--
-- History:
-- tise 2001-04-04 First Version
--
-- KC 2002-01-23 Remove used generics and removed unused code
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library Unisim;
use Unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_bit is
port (
Clk : in std_logic;
Rst : in std_logic;
Count_In : in std_logic;
Load_In : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Carry_In : in std_logic;
Clock_Enable : in std_logic;
Result : out std_logic;
Carry_Out : out std_logic);
end entity counter_bit;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_bit is
component LUT4 is
generic(
INIT : bit_vector := X"0000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic);
end component LUT4;
component MUXCY_L is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component MUXCY_L;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
signal count_AddSub : std_logic;
signal count_Result : std_logic;
signal count_Result_Reg : std_logic;
attribute INIT : string;
begin -- VHDL_RTL
I_ALU_LUT : LUT4
generic map(
INIT => X"36C6"
)
port map (
O => count_AddSub, -- [out]
I0 => Count_In, -- [in]
I1 => Count_Down, -- [in]
I2 => Count_Load, -- [in]
I3 => Load_In); -- [in]
MUXCY_I : MUXCY_L
port map (
DI => Count_Down,
CI => Carry_In,
S => count_AddSub,
LO => Carry_Out);
XOR_I : XORCY
port map (
LI => count_AddSub,
CI => Carry_In,
O => count_Result);
FDRE_I: FDRE
port map (
Q => count_Result_Reg, -- [out]
C => Clk, -- [in]
CE => Clock_Enable, -- [in]
D => count_Result, -- [in]
R => Rst -- [in]
);
Result <= count_Result_Reg;
end imp;
|
mit
|
HighlandersFRC/fpga
|
lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/proc_common_v4_0/hdl/src/vhdl/addsub.vhd
|
15
|
10861
|
-------------------------------------------------------------------------------
-- $Id: addsub.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- Either add an ArgA or subtract an ArgS from an ArgD.
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: addsub.vhd
-- Version:
--------------------------------------------------------------------------------
-- Description:
-- Either add an ArgA or subtract an ArgS from an ArgD. The
-- output, Result, can be optionally combinatorial or registered.
--
-- When C_REGISTERED is false, Result will take on one of
-- two values:
--
-- ArgD - ArgS, when Sub is asserted, or
-- ArgD + ArgA, when Sub is not asserted.
--
-- Cry_BrwN will be '1' if ArgD + ArgA produces a carry
-- and it will be '0' if ArgD - ArgS produces a borrow.
--
-- The signals Clk, Rst and CE are meaningful and used only
-- if C_REGISTERED is true. These may be "tied off" to any
-- std_logic value in combinatorial instantiations (e.g.
-- connected to '0').
--
-- This table details the operation in registered mode:
--
-- Clk Rst CE Sub <Cry_BrwN, Result>
-- --- --- -- --- ------------------
-- _
-- _| 1 x x 0
--
-- _
-- _| 0 1 0 ArgD + ArgA
--
-- _
-- _| 0 1 1 ArgD - ArgS
--
-- _
-- _| 0 0 x No change
--
-- _
-- not _| x x x No change
--
-------------------------------------------------------------------------------
-- Structure:
--
-- addsub.vhd
-------------------------------------------------------------------------------
-- Author: FO
--
-- History:
--
-- FO 08/14/2003 -- First version
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity addsub is
generic (
C_WIDTH : natural := 8;
C_REGISTERED : boolean := false
);
port (
Clk : in std_logic;
Rst : in std_logic; -- Reset Result and Cry_BrwN to zero
CE : in std_logic;
ArgD : in std_logic_vector(0 to C_WIDTH-1);
ArgA : in std_logic_vector(0 to C_WIDTH-1);
ArgS : in std_logic_vector(0 to C_WIDTH-1);
Sub : in std_logic;
Cry_BrwN : out std_logic;
Result : out std_logic_vector(0 to C_WIDTH-1)
);
end addsub;
library unisim;
use unisim.VCOMPONENTS.FDRE;
use unisim.VCOMPONENTS.MUXCY;
use unisim.VCOMPONENTS.XORCY;
library ieee;
use ieee.numeric_std.all;
architecture imp of addsub is
signal lutout,
xorcy_out : std_logic_vector(0 to C_WIDTH-1);
signal cry : std_logic_vector(0 to C_WIDTH);
begin
cry(C_WIDTH) <= Sub;
PERBIT_GEN: for j in C_WIDTH-1 downto 0 generate
begin
------------------------------------------------------------------------
-- LUT output generation.
------------------------------------------------------------------------
lutout(j) <= ArgD(j) xor ArgA(j) when Sub = '0' else
ArgD(j) xnor ArgS(j);
------------------------------------------------------------------------
-- Propagate the carry (borrow) out.
------------------------------------------------------------------------
MUXCY_i1: MUXCY
port map (
DI => ArgD(j),
CI => cry(j+1),
S => lutout(j),
O => cry(j)
);
------------------------------------------------------------------------
-- Apply the effect of carry (borrow) in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => lutout(j),
CI => cry(j+1),
O => xorcy_out(j)
);
------------------------------------------------------------------------
-- Result, combinatorial or registered.
------------------------------------------------------------------------
COM_GEN : if not C_REGISTERED generate
Result(j) <= xorcy_out(j);
end generate;
-- else
REG_GEN : if C_REGISTERED generate
FDRE_I1: FDRE
port map (
Q => Result(j),
C => Clk,
CE => CE,
D => xorcy_out(j),
R => Rst
);
end generate;
end generate;
----------------------------------------------------------------------------
-- Cry_BrwN, combinatorial or registered.
----------------------------------------------------------------------------
COM_GEN : if not C_REGISTERED generate
Cry_BrwN <= cry(0);
end generate;
-- else
REG_GEN : if C_REGISTERED generate
FDRE_I1: FDRE
port map (
Q => Cry_BrwN,
C => Clk,
CE => CE,
D => cry(0),
R => Rst
);
end generate;
end imp;
|
mit
|
Given-Jiang/Add_Frame
|
Add_Frame_dspbuilder/db/alt_dspbuilder_sLpmAddSub.vhd
|
8
|
4640
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_signed.all;
library LPM;
use LPM.LPM_COMPONENTS.all;
library altera;
use altera.alt_dspbuilder_package.all;
ENTITY alt_dspbuilder_sLpmAddSub IS
GENERIC
(
width : positive :=8;
isunsigned : natural :=0;
pipeline : natural :=0;
or_aclr_inputs : boolean := true
);
PORT
(
add_sub : in std_logic ;
dataa : in std_logic_vector (width-1 DOWNTO 0);
datab : in std_logic_vector (width-1 DOWNTO 0);
cin : in std_logic ;
clock : in std_logic ;
aclr : in std_logic ;
user_aclr : in std_logic ;
clken : in std_logic ;
result : out std_logic_vector (width-1 DOWNTO 0);
cout : out std_logic
);
END alt_dspbuilder_sLpmAddSub;
ARCHITECTURE SYN OF alt_dspbuilder_sLpmAddSub IS
signal aclr_i : std_logic;
BEGIN
or_aclrs: if (or_aclr_inputs=true) generate
aclr_i <= aclr or user_aclr;
end generate or_aclrs;
only_user_aclr: if(or_aclr_inputs=false) generate
aclr_i <= user_aclr;
end generate only_user_aclr;
gnp:if (0=pipeline) generate
gsn:if (0=isunsigned) generate
U0 : lpm_add_sub
GENERIC MAP (
lpm_width => width,
lpm_direction => "UNUSED",
lpm_type => "LPM_ADD_SUB",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO",
lpm_representation => "SIGNED",
lpm_pipeline => 0
)
PORT MAP (
dataa => dataa,
add_sub => add_sub,
datab => datab,
cin => cin,
overflow => cout,
result => result
);
end generate gsn;
gusn:if (0<isunsigned) generate
U0 : lpm_add_sub
GENERIC MAP (
lpm_width => width,
lpm_direction => "UNUSED",
lpm_type => "LPM_ADD_SUB",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO",
lpm_representation => "UNSIGNED",
lpm_pipeline => 0
)
PORT MAP (
dataa => dataa,
add_sub => add_sub,
datab => datab,
cin => cin,
cout => cout,
result => result
);
end generate gusn;
end generate gnp;
gp:if (pipeline>0) generate
gsn:if (0=isunsigned) generate
U0 : lpm_add_sub
GENERIC MAP (
lpm_width => width,
lpm_direction => "UNUSED",
lpm_type => "LPM_ADD_SUB",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO",
lpm_representation => "SIGNED",
lpm_pipeline => pipeline
)
PORT MAP (
dataa => dataa,
add_sub => add_sub,
datab => datab,
cin => cin,
clken => clken,
aclr => aclr_i,
clock => clock,
overflow => cout,
result => result
);
end generate gsn;
gusn:if (0<isunsigned) generate
U0 : lpm_add_sub
GENERIC MAP (
lpm_width => width,
lpm_direction => "UNUSED",
lpm_type => "LPM_ADD_SUB",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO",
lpm_representation => "UNSIGNED",
lpm_pipeline => pipeline
)
PORT MAP (
dataa => dataa,
add_sub => add_sub,
datab => datab,
cin => cin,
clken => clken,
aclr => aclr_i,
clock => clock,
cout => cout,
result => result
);
end generate gusn;
end generate gp;
END SYN;
|
mit
|
Given-Jiang/Add_Frame
|
Add_Frame_dspbuilder/hdl/alt_dspbuilder_bus_concat_GNXPBV3I7L.vhd
|
4
|
654
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GNXPBV3I7L is
generic ( widthB : natural := 4;
widthA : natural := 12);
port(
a : in std_logic_vector((widthA)-1 downto 0);
aclr : in std_logic;
b : in std_logic_vector((widthB)-1 downto 0);
clock : in std_logic;
output : out std_logic_vector((widthA+widthB)-1 downto 0));
end entity;
architecture rtl of alt_dspbuilder_bus_concat_GNXPBV3I7L is
Begin
output <= a & b;
end architecture;
|
mit
|
Given-Jiang/Add_Frame
|
tb_Add_Frame/hdl/Add_Frame_GN_Add_Frame_Add_Frame_Module_CTRL_DECODER.vhd
|
2
|
35050
|
-- Add_Frame_GN_Add_Frame_Add_Frame_Module_CTRL_DECODER.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.25.10:37:28
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Add_Frame_GN_Add_Frame_Add_Frame_Module_CTRL_DECODER is
port (
decoder_col : out std_logic_vector(15 downto 0); -- decoder_col.wire
decoder_row : out std_logic_vector(15 downto 0); -- decoder_row.wire
height : out std_logic_vector(15 downto 0); -- height.wire
data : in std_logic_vector(23 downto 0) := (others => '0'); -- data.wire
sop : in std_logic := '0'; -- sop.wire
width : out std_logic_vector(15 downto 0); -- width.wire
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0' -- .reset
);
end entity Add_Frame_GN_Add_Frame_Add_Frame_Module_CTRL_DECODER;
architecture rtl of Add_Frame_GN_Add_Frame_Add_Frame_Module_CTRL_DECODER is
component alt_dspbuilder_clock_GNQFU4PUDH is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
component alt_dspbuilder_cast_GNED3D3FSF is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(3 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNED3D3FSF;
component alt_dspbuilder_cast_GNYDD6MCZ4 is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(11 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(3 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNYDD6MCZ4;
component alt_dspbuilder_cast_GNHBD5Z3AF is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(3 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNHBD5Z3AF;
component alt_dspbuilder_cast_GN76IOUHQH is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(11 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(3 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN76IOUHQH;
component alt_dspbuilder_cast_GNMU5M7DX7 is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(3 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNMU5M7DX7;
component alt_dspbuilder_cast_GNI42JW6WW is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(11 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(3 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNI42JW6WW;
component alt_dspbuilder_bus_concat_GNAUBM7IRL is
generic (
widthB : natural := 8;
widthA : natural := 8
);
port (
a : in std_logic_vector(widthA-1 downto 0) := (others => 'X'); -- wire
aclr : in std_logic := 'X'; -- clk
b : in std_logic_vector(widthB-1 downto 0) := (others => 'X'); -- wire
clock : in std_logic := 'X'; -- clk
output : out std_logic_vector(widthA+widthB-1 downto 0) -- wire
);
end component alt_dspbuilder_bus_concat_GNAUBM7IRL;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_bus_concat_GNBH75ZTOD is
generic (
widthB : natural := 8;
widthA : natural := 8
);
port (
a : in std_logic_vector(widthA-1 downto 0) := (others => 'X'); -- wire
aclr : in std_logic := 'X'; -- clk
b : in std_logic_vector(widthB-1 downto 0) := (others => 'X'); -- wire
clock : in std_logic := 'X'; -- clk
output : out std_logic_vector(widthA+widthB-1 downto 0) -- wire
);
end component alt_dspbuilder_bus_concat_GNBH75ZTOD;
component alt_dspbuilder_bus_concat_GNXPBV3I7L is
generic (
widthB : natural := 8;
widthA : natural := 8
);
port (
a : in std_logic_vector(widthA-1 downto 0) := (others => 'X'); -- wire
aclr : in std_logic := 'X'; -- clk
b : in std_logic_vector(widthB-1 downto 0) := (others => 'X'); -- wire
clock : in std_logic := 'X'; -- clk
output : out std_logic_vector(widthA+widthB-1 downto 0) -- wire
);
end component alt_dspbuilder_bus_concat_GNXPBV3I7L;
component alt_dspbuilder_port_GNBO6OMO5Y is
port (
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(15 downto 0) -- wire
);
end component alt_dspbuilder_port_GNBO6OMO5Y;
component alt_dspbuilder_if_statement_GNURIZNNI4 is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(2 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(2 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNURIZNNI4;
component alt_dspbuilder_constant_GNP7P5YZV2 is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(2 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNP7P5YZV2;
component alt_dspbuilder_logical_bit_op_GNKUBZL4TE is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNKUBZL4TE;
component alt_dspbuilder_logical_bit_op_GNUQ2R64DV is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNUQ2R64DV;
component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V;
component alt_dspbuilder_delay_GNVCBR7UZP is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNVCBR7UZP;
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_gnd_GN;
component alt_dspbuilder_counter_GNW5IG44CT is
generic (
use_usr_aclr : string := "false";
use_ena : string := "false";
use_cin : string := "false";
use_sset : string := "false";
ndirection : natural := 1;
svalue : string := "0";
use_sload : string := "false";
use_sclr : string := "false";
use_cout : string := "false";
modulus : integer := 256;
use_cnt_ena : string := "false";
width : natural := 8;
use_aset : string := "false";
use_aload : string := "false";
avalue : string := "0"
);
port (
aclr : in std_logic := 'X'; -- clk
aload : in std_logic := 'X'; -- wire
aset : in std_logic := 'X'; -- wire
cin : in std_logic := 'X'; -- wire
clock : in std_logic := 'X'; -- clk
cnt_ena : in std_logic := 'X'; -- wire
cout : out std_logic; -- wire
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
direction : in std_logic := 'X'; -- wire
ena : in std_logic := 'X'; -- wire
q : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X'; -- wire
sload : in std_logic := 'X'; -- wire
sset : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_counter_GNW5IG44CT;
component alt_dspbuilder_port_GN37ALZBS4 is
port (
input : in std_logic := 'X'; -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_port_GN37ALZBS4;
component alt_dspbuilder_delay_GNGQ56ZS4N is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNGQ56ZS4N;
component alt_dspbuilder_decoder_GNSCEXJCJK is
generic (
decode : string := "00000000";
pipeline : natural := 0;
width : natural := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
dec : out std_logic; -- wire
ena : in std_logic := 'X'; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_decoder_GNSCEXJCJK;
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_vcc_GN;
component alt_dspbuilder_cast_GNSB3OXIQS is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(0 downto 0) := (others => 'X'); -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_cast_GNSB3OXIQS;
component alt_dspbuilder_cast_GN46N4UJ5S is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic := 'X'; -- wire
output : out std_logic_vector(0 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN46N4UJ5S;
signal delay5sclrgnd_output_wire : std_logic; -- Delay5sclrGND:output -> Delay5:sclr
signal delay4sclrgnd_output_wire : std_logic; -- Delay4sclrGND:output -> Delay4:sclr
signal delay3sclrgnd_output_wire : std_logic; -- Delay3sclrGND:output -> Delay3:sclr
signal delay1sclrgnd_output_wire : std_logic; -- Delay1sclrGND:output -> Delay1:sclr
signal decodersclrgnd_output_wire : std_logic; -- DecodersclrGND:output -> Decoder:sclr
signal decoderenavcc_output_wire : std_logic; -- DecoderenaVCC:output -> Decoder:ena
signal bus_concatenation3_output_wire : std_logic_vector(7 downto 0); -- Bus_Concatenation3:output -> Bus_Concatenation4:a
signal bus_concatenation5_output_wire : std_logic_vector(7 downto 0); -- Bus_Concatenation5:output -> Bus_Concatenation1:a
signal bus_concatenation4_output_wire : std_logic_vector(11 downto 0); -- Bus_Concatenation4:output -> Bus_Concatenation6:a
signal bus_concatenation7_output_wire : std_logic_vector(7 downto 0); -- Bus_Concatenation7:output -> Bus_Concatenation8:a
signal bus_concatenation8_output_wire : std_logic_vector(11 downto 0); -- Bus_Concatenation8:output -> Bus_Concatenation9:a
signal data_0_output_wire : std_logic_vector(23 downto 0); -- data_0:output -> [Bus_Conversion1:input, Bus_Conversion2:input, Bus_Conversion3:input, Decoder:data]
signal bus_conversion1_output_wire : std_logic_vector(3 downto 0); -- Bus_Conversion1:output -> Bus_Concatenation5:b
signal bus_conversion10_output_wire : std_logic_vector(3 downto 0); -- Bus_Conversion10:output -> Bus_Concatenation8:b
signal bus_conversion11_output_wire : std_logic_vector(3 downto 0); -- Bus_Conversion11:output -> Bus_Concatenation9:b
signal bus_conversion2_output_wire : std_logic_vector(3 downto 0); -- Bus_Conversion2:output -> Bus_Concatenation5:a
signal bus_conversion3_output_wire : std_logic_vector(3 downto 0); -- Bus_Conversion3:output -> Bus_Concatenation1:b
signal bus_conversion4_output_wire : std_logic_vector(3 downto 0); -- Bus_Conversion4:output -> Bus_Concatenation3:a
signal bus_conversion5_output_wire : std_logic_vector(3 downto 0); -- Bus_Conversion5:output -> Bus_Concatenation3:b
signal bus_conversion6_output_wire : std_logic_vector(3 downto 0); -- Bus_Conversion6:output -> Bus_Concatenation4:b
signal bus_conversion7_output_wire : std_logic_vector(3 downto 0); -- Bus_Conversion7:output -> Bus_Concatenation6:b
signal bus_conversion8_output_wire : std_logic_vector(3 downto 0); -- Bus_Conversion8:output -> Bus_Concatenation7:a
signal bus_conversion9_output_wire : std_logic_vector(3 downto 0); -- Bus_Conversion9:output -> Bus_Concatenation7:b
signal delay3_output_wire : std_logic_vector(11 downto 0); -- Delay3:output -> [Bus_Conversion4:input, Bus_Conversion5:input, Bus_Conversion6:input]
signal delay4_output_wire : std_logic_vector(11 downto 0); -- Delay4:output -> [Bus_Conversion7:input, Bus_Conversion8:input, Bus_Conversion9:input, Delay3:input]
signal bus_concatenation1_output_wire : std_logic_vector(11 downto 0); -- Bus_Concatenation1:output -> Delay5:input
signal delay5_output_wire : std_logic_vector(11 downto 0); -- Delay5:output -> [Bus_Conversion10:input, Bus_Conversion11:input, Bus_Conversion12:input, Delay4:input]
signal constant2_output_wire : std_logic_vector(2 downto 0); -- Constant2:output -> If_Statement:a
signal counter_q_wire : std_logic_vector(2 downto 0); -- Counter:q -> If_Statement:b
signal decoder_dec_wire : std_logic; -- Decoder:dec -> Logical_Bit_Operator:data0
signal sop_0_output_wire : std_logic; -- sop_0:output -> Logical_Bit_Operator:data1
signal logical_bit_operator_result_wire : std_logic; -- Logical_Bit_Operator:result -> [Logical_Bit_Operator1:data0, cast221:input]
signal if_statement_true_wire : std_logic; -- If_Statement:true -> Logical_Bit_Operator1:data1
signal logical_bit_operator1_result_wire : std_logic; -- Logical_Bit_Operator1:result -> Delay1:ena
signal logical_bit_operator3_result_wire : std_logic; -- Logical_Bit_Operator3:result -> Counter:sclr
signal bus_concatenation6_output_wire : std_logic_vector(15 downto 0); -- Bus_Concatenation6:output -> [decoder_col_0:input, width_0:input]
signal bus_concatenation9_output_wire : std_logic_vector(15 downto 0); -- Bus_Concatenation9:output -> [decoder_row_0:input, height_0:input]
signal delay1_output_wire : std_logic_vector(0 downto 0); -- Delay1:output -> [cast217:input, cast218:input, cast219:input, cast220:input, cast222:input]
signal cast217_output_wire : std_logic; -- cast217:output -> Counter:cnt_ena
signal cast218_output_wire : std_logic; -- cast218:output -> Delay3:ena
signal cast219_output_wire : std_logic; -- cast219:output -> Delay4:ena
signal cast220_output_wire : std_logic; -- cast220:output -> Delay5:ena
signal cast221_output_wire : std_logic_vector(0 downto 0); -- cast221:output -> Delay1:input
signal cast222_output_wire : std_logic; -- cast222:output -> Logical_Bit_Operator3:data0
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Bus_Concatenation1:aclr, Bus_Concatenation3:aclr, Bus_Concatenation4:aclr, Bus_Concatenation5:aclr, Bus_Concatenation6:aclr, Bus_Concatenation7:aclr, Bus_Concatenation8:aclr, Bus_Concatenation9:aclr, Counter:aclr, Decoder:aclr, Delay1:aclr, Delay3:aclr, Delay4:aclr, Delay5:aclr]
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Bus_Concatenation1:clock, Bus_Concatenation3:clock, Bus_Concatenation4:clock, Bus_Concatenation5:clock, Bus_Concatenation6:clock, Bus_Concatenation7:clock, Bus_Concatenation8:clock, Bus_Concatenation9:clock, Counter:clock, Decoder:clock, Delay1:clock, Delay3:clock, Delay4:clock, Delay5:clock]
begin
clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr => aclr -- .reset
);
bus_conversion1 : component alt_dspbuilder_cast_GNED3D3FSF
generic map (
round => 0,
saturate => 0
)
port map (
input => data_0_output_wire, -- input.wire
output => bus_conversion1_output_wire -- output.wire
);
bus_conversion12 : component alt_dspbuilder_cast_GNYDD6MCZ4
generic map (
round => 0,
saturate => 0
)
port map (
input => delay5_output_wire, -- input.wire
output => open -- output.wire
);
bus_conversion2 : component alt_dspbuilder_cast_GNHBD5Z3AF
generic map (
round => 0,
saturate => 0
)
port map (
input => data_0_output_wire, -- input.wire
output => bus_conversion2_output_wire -- output.wire
);
bus_conversion10 : component alt_dspbuilder_cast_GN76IOUHQH
generic map (
round => 0,
saturate => 0
)
port map (
input => delay5_output_wire, -- input.wire
output => bus_conversion10_output_wire -- output.wire
);
bus_conversion3 : component alt_dspbuilder_cast_GNMU5M7DX7
generic map (
round => 0,
saturate => 0
)
port map (
input => data_0_output_wire, -- input.wire
output => bus_conversion3_output_wire -- output.wire
);
bus_conversion11 : component alt_dspbuilder_cast_GNI42JW6WW
generic map (
round => 0,
saturate => 0
)
port map (
input => delay5_output_wire, -- input.wire
output => bus_conversion11_output_wire -- output.wire
);
bus_conversion4 : component alt_dspbuilder_cast_GN76IOUHQH
generic map (
round => 0,
saturate => 0
)
port map (
input => delay3_output_wire, -- input.wire
output => bus_conversion4_output_wire -- output.wire
);
bus_concatenation7 : component alt_dspbuilder_bus_concat_GNAUBM7IRL
generic map (
widthB => 4,
widthA => 4
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => bus_conversion8_output_wire, -- a.wire
b => bus_conversion9_output_wire, -- b.wire
output => bus_concatenation7_output_wire -- output.wire
);
data_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => data, -- input.wire
output => data_0_output_wire -- output.wire
);
bus_concatenation8 : component alt_dspbuilder_bus_concat_GNBH75ZTOD
generic map (
widthB => 4,
widthA => 8
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => bus_concatenation7_output_wire, -- a.wire
b => bus_conversion10_output_wire, -- b.wire
output => bus_concatenation8_output_wire -- output.wire
);
bus_concatenation5 : component alt_dspbuilder_bus_concat_GNAUBM7IRL
generic map (
widthB => 4,
widthA => 4
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => bus_conversion2_output_wire, -- a.wire
b => bus_conversion1_output_wire, -- b.wire
output => bus_concatenation5_output_wire -- output.wire
);
bus_concatenation6 : component alt_dspbuilder_bus_concat_GNXPBV3I7L
generic map (
widthB => 4,
widthA => 12
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => bus_concatenation4_output_wire, -- a.wire
b => bus_conversion7_output_wire, -- b.wire
output => bus_concatenation6_output_wire -- output.wire
);
bus_concatenation3 : component alt_dspbuilder_bus_concat_GNAUBM7IRL
generic map (
widthB => 4,
widthA => 4
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => bus_conversion4_output_wire, -- a.wire
b => bus_conversion5_output_wire, -- b.wire
output => bus_concatenation3_output_wire -- output.wire
);
bus_concatenation4 : component alt_dspbuilder_bus_concat_GNBH75ZTOD
generic map (
widthB => 4,
widthA => 8
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => bus_concatenation3_output_wire, -- a.wire
b => bus_conversion6_output_wire, -- b.wire
output => bus_concatenation4_output_wire -- output.wire
);
bus_concatenation1 : component alt_dspbuilder_bus_concat_GNBH75ZTOD
generic map (
widthB => 4,
widthA => 8
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => bus_concatenation5_output_wire, -- a.wire
b => bus_conversion3_output_wire, -- b.wire
output => bus_concatenation1_output_wire -- output.wire
);
height_0 : component alt_dspbuilder_port_GNBO6OMO5Y
port map (
input => bus_concatenation9_output_wire, -- input.wire
output => height -- output.wire
);
if_statement : component alt_dspbuilder_if_statement_GNURIZNNI4
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "(a<b)",
number_inputs => 2,
width => 3
)
port map (
true => if_statement_true_wire, -- true.wire
a => constant2_output_wire, -- a.wire
b => counter_q_wire -- b.wire
);
constant2 : component alt_dspbuilder_constant_GNP7P5YZV2
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "001",
width => 3
)
port map (
output => constant2_output_wire -- output.wire
);
logical_bit_operator3 : component alt_dspbuilder_logical_bit_op_GNKUBZL4TE
generic map (
LogicalOp => "AltNOT",
number_inputs => 1
)
port map (
result => logical_bit_operator3_result_wire, -- result.wire
data0 => cast222_output_wire -- data0.wire
);
logical_bit_operator1 : component alt_dspbuilder_logical_bit_op_GNUQ2R64DV
generic map (
LogicalOp => "AltOR",
number_inputs => 2
)
port map (
result => logical_bit_operator1_result_wire, -- result.wire
data0 => logical_bit_operator_result_wire, -- data0.wire
data1 => if_statement_true_wire -- data1.wire
);
decoder_row_0 : component alt_dspbuilder_port_GNBO6OMO5Y
port map (
input => bus_concatenation9_output_wire, -- input.wire
output => decoder_row -- output.wire
);
logical_bit_operator : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator_result_wire, -- result.wire
data0 => decoder_dec_wire, -- data0.wire
data1 => sop_0_output_wire -- data1.wire
);
width_0 : component alt_dspbuilder_port_GNBO6OMO5Y
port map (
input => bus_concatenation6_output_wire, -- input.wire
output => width -- output.wire
);
decoder_col_0 : component alt_dspbuilder_port_GNBO6OMO5Y
port map (
input => bus_concatenation6_output_wire, -- input.wire
output => decoder_col -- output.wire
);
delay5 : component alt_dspbuilder_delay_GNVCBR7UZP
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "000000000001",
width => 12
)
port map (
input => bus_concatenation1_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay5_output_wire, -- output.wire
sclr => delay5sclrgnd_output_wire, -- sclr.wire
ena => cast220_output_wire -- ena.wire
);
delay5sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay5sclrgnd_output_wire -- output.wire
);
counter : component alt_dspbuilder_counter_GNW5IG44CT
generic map (
use_usr_aclr => "false",
use_ena => "false",
use_cin => "false",
use_sset => "false",
ndirection => 1,
svalue => "1",
use_sload => "false",
use_sclr => "true",
use_cout => "false",
modulus => -1,
use_cnt_ena => "true",
width => 3,
use_aset => "false",
use_aload => "false",
avalue => "0"
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
cnt_ena => cast217_output_wire, -- cnt_ena.wire
sclr => logical_bit_operator3_result_wire, -- sclr.wire
q => counter_q_wire, -- q.wire
cout => open -- cout.wire
);
delay4 : component alt_dspbuilder_delay_GNVCBR7UZP
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "000000000001",
width => 12
)
port map (
input => delay5_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay4_output_wire, -- output.wire
sclr => delay4sclrgnd_output_wire, -- sclr.wire
ena => cast219_output_wire -- ena.wire
);
delay4sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay4sclrgnd_output_wire -- output.wire
);
delay3 : component alt_dspbuilder_delay_GNVCBR7UZP
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "000000000001",
width => 12
)
port map (
input => delay4_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay3_output_wire, -- output.wire
sclr => delay3sclrgnd_output_wire, -- sclr.wire
ena => cast218_output_wire -- ena.wire
);
delay3sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay3sclrgnd_output_wire -- output.wire
);
sop_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => sop, -- input.wire
output => sop_0_output_wire -- output.wire
);
bus_concatenation9 : component alt_dspbuilder_bus_concat_GNXPBV3I7L
generic map (
widthB => 4,
widthA => 12
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => bus_concatenation8_output_wire, -- a.wire
b => bus_conversion11_output_wire, -- b.wire
output => bus_concatenation9_output_wire -- output.wire
);
delay1 : component alt_dspbuilder_delay_GNGQ56ZS4N
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "1",
width => 1
)
port map (
input => cast221_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay1_output_wire, -- output.wire
sclr => delay1sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator1_result_wire -- ena.wire
);
delay1sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay1sclrgnd_output_wire -- output.wire
);
bus_conversion9 : component alt_dspbuilder_cast_GNYDD6MCZ4
generic map (
round => 0,
saturate => 0
)
port map (
input => delay4_output_wire, -- input.wire
output => bus_conversion9_output_wire -- output.wire
);
bus_conversion8 : component alt_dspbuilder_cast_GNI42JW6WW
generic map (
round => 0,
saturate => 0
)
port map (
input => delay4_output_wire, -- input.wire
output => bus_conversion8_output_wire -- output.wire
);
decoder : component alt_dspbuilder_decoder_GNSCEXJCJK
generic map (
decode => "000000000000000000001111",
pipeline => 0,
width => 24
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => data_0_output_wire, -- data.wire
dec => decoder_dec_wire, -- dec.wire
sclr => decodersclrgnd_output_wire, -- sclr.wire
ena => decoderenavcc_output_wire -- ena.wire
);
decodersclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decodersclrgnd_output_wire -- output.wire
);
decoderenavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoderenavcc_output_wire -- output.wire
);
bus_conversion7 : component alt_dspbuilder_cast_GN76IOUHQH
generic map (
round => 0,
saturate => 0
)
port map (
input => delay4_output_wire, -- input.wire
output => bus_conversion7_output_wire -- output.wire
);
bus_conversion6 : component alt_dspbuilder_cast_GNYDD6MCZ4
generic map (
round => 0,
saturate => 0
)
port map (
input => delay3_output_wire, -- input.wire
output => bus_conversion6_output_wire -- output.wire
);
bus_conversion5 : component alt_dspbuilder_cast_GNI42JW6WW
generic map (
round => 0,
saturate => 0
)
port map (
input => delay3_output_wire, -- input.wire
output => bus_conversion5_output_wire -- output.wire
);
cast217 : component alt_dspbuilder_cast_GNSB3OXIQS
generic map (
round => 0,
saturate => 0
)
port map (
input => delay1_output_wire, -- input.wire
output => cast217_output_wire -- output.wire
);
cast218 : component alt_dspbuilder_cast_GNSB3OXIQS
generic map (
round => 0,
saturate => 0
)
port map (
input => delay1_output_wire, -- input.wire
output => cast218_output_wire -- output.wire
);
cast219 : component alt_dspbuilder_cast_GNSB3OXIQS
generic map (
round => 0,
saturate => 0
)
port map (
input => delay1_output_wire, -- input.wire
output => cast219_output_wire -- output.wire
);
cast220 : component alt_dspbuilder_cast_GNSB3OXIQS
generic map (
round => 0,
saturate => 0
)
port map (
input => delay1_output_wire, -- input.wire
output => cast220_output_wire -- output.wire
);
cast221 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => logical_bit_operator_result_wire, -- input.wire
output => cast221_output_wire -- output.wire
);
cast222 : component alt_dspbuilder_cast_GNSB3OXIQS
generic map (
round => 0,
saturate => 0
)
port map (
input => delay1_output_wire, -- input.wire
output => cast222_output_wire -- output.wire
);
end architecture rtl; -- of Add_Frame_GN_Add_Frame_Add_Frame_Module_CTRL_DECODER
|
mit
|
Given-Jiang/Add_Frame
|
tb_Add_Frame/db/alt_dspbuilder_if_statement_GNHRNNRV37.vhd
|
4
|
1883
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNHRNNRV37 is
generic ( use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 0;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "(((a>b) or (a=b)) and ((a<c) or (a=c)) and (d=e)) or ((d>e) and (d<f) and (a=b)) or ((d>e) and (d<f) and (a=c)) or (((a>b) or (a=b)) and ((a<c) or (a=c)) and (d=f))";
number_inputs : integer := 6;
width : natural := 16);
port(
true : out std_logic;
a : in std_logic_vector(15 downto 0);
b : in std_logic_vector(15 downto 0);
c : in std_logic_vector(15 downto 0);
d : in std_logic_vector(15 downto 0);
e : in std_logic_vector(15 downto 0);
f : in std_logic_vector(15 downto 0));
end entity;
architecture rtl of alt_dspbuilder_if_statement_GNHRNNRV37 is
signal result : std_logic;
constant zero : STD_LOGIC_VECTOR(15 DOWNTO 0) := (others=>'0');
constant one : STD_LOGIC_VECTOR(15 DOWNTO 0) := (0 => '1', others => '0');
function myFunc ( Value: boolean )
return std_logic is
variable func_result : std_logic;
begin
if (Value) then
func_result := '1';
else
func_result := '0';
end if;
return func_result;
end;
function myFunc ( Value: std_logic )
return std_logic is
begin
return Value;
end;
Begin
-- DSP Builder Block - Simulink Block "IfStatement"
result <= myFunc((((a>b) or (a=b)) and ((a<c) or (a=c)) and (d=e)) or ((d>e) and (d<f) and (a=b)) or ((d>e) and (d<f) and (a=c)) or (((a>b) or (a=b)) and ((a<c) or (a=c)) and (d=f))) ;
true <= result;
end architecture;
|
mit
|
Given-Jiang/Add_Frame
|
tb_Add_Frame/altera_lnsim/altera_lnsim_functions/_primary.vhd
|
5
|
104
|
library verilog;
use verilog.vl_types.all;
entity altera_lnsim_functions is
end altera_lnsim_functions;
|
mit
|
Given-Jiang/Add_Frame
|
Add_Frame_dspbuilder/hdl/alt_dspbuilder_AROUND.vhd
|
20
|
2588
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_AROUND is
generic (
widthin : natural :=8;
widthout : natural :=4
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
yout : out std_logic_vector(widthout-1 downto 0)
);
end alt_dspbuilder_AROUND;
architecture AROUND_SYNTH of alt_dspbuilder_AROUND is
signal ADDOFIVE : std_logic_vector(widthin downto 0) ;
signal XINEXT : std_logic_vector(widthin downto 0) ;
signal YOUTEXT : std_logic_vector(widthin downto 0);
signal notsigned : std_logic :='0';
begin
ev:if widthin=widthout generate
yout <= xin;
end generate ev;
nev:if (widthin>widthout) generate
ad5:if (widthin-widthout>1) generate
lo:for i in 0 to widthin-widthout-2 generate
ADDOFIVE(i) <= '1';
end generate lo;
hi:for i in widthin-widthout-1 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate ad5;
adn:if (widthin-widthout=1) generate
hi:for i in 0 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate adn;
XINEXT(widthin-1 downto 0) <= xin(widthin-1 downto 0);
XINEXT(widthin) <= xin(widthin-1);
notsigned <= not(XINEXT(widthin-1));
YOUTEXT <= XINEXT + ADDOFIVE + notsigned;
gy:for i in 0 to widthout-1 generate
yout(i) <= YOUTEXT(i+widthin-widthout) ;
end generate gy;
end generate ;
end AROUND_SYNTH;
|
mit
|
Given-Jiang/Add_Frame
|
Add_Frame_dspbuilder/db/alt_dspbuilder_single_pulse.vhd
|
4
|
1650
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_single_pulse is
generic (
DELAY : positive := 1;
SIGNAL_TYPE : string := "Impulse";
IMPULSE_WIDTH : positive := 1
);
port (
result : out std_logic;
clock : in std_logic := '0';
sclr : in std_logic := '0';
aclr : in std_logic := '0';
ena : in std_logic := '0'
);
end entity alt_dspbuilder_single_pulse;
architecture rtl of alt_dspbuilder_single_pulse is
component alt_dspbuilder_single_pulse_GN2XGKTRR3 is
generic (
DELAY : positive := 1;
SIGNAL_TYPE : string := "Step Down";
IMPULSE_WIDTH : positive := 1
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
ena : in std_logic := '0';
result : out std_logic;
sclr : in std_logic := '0'
);
end component alt_dspbuilder_single_pulse_GN2XGKTRR3;
begin
alt_dspbuilder_single_pulse_GN2XGKTRR3_0: if ((DELAY = 1) and (SIGNAL_TYPE = "Step Down") and (IMPULSE_WIDTH = 1)) generate
inst_alt_dspbuilder_single_pulse_GN2XGKTRR3_0: alt_dspbuilder_single_pulse_GN2XGKTRR3
generic map(DELAY => 1, SIGNAL_TYPE => "Step Down", IMPULSE_WIDTH => 1)
port map(aclr => aclr, clock => clock, ena => ena, result => result, sclr => sclr);
end generate;
assert not (((DELAY = 1) and (SIGNAL_TYPE = "Step Down") and (IMPULSE_WIDTH = 1)))
report "Please run generate again" severity error;
end architecture rtl;
|
mit
|
Given-Jiang/Add_Frame
|
Add_Frame_dspbuilder/hdl/alt_dspbuilder_testbench_salt_GNUCY2GBID.vhd
|
4
|
1747
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GNUCY2GBID is
generic ( XFILE : string := "default");
port(
clock : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(2 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_salt_GNUCY2GBID is
function to_std_logic (B: character) return std_logic is
begin
case B is
when '0' => return '0';
when '1' => return '1';
when OTHERS => return 'X';
end case;
end;
function to_std_logic_vector (B: string) return
std_logic_vector is
variable res: std_logic_vector (B'range);
begin
for i in B'range loop
case B(i) is
when '0' => res(i) := '0';
when '1' => res(i) := '1';
when OTHERS => res(i) := 'X';
end case;
end loop;
return res;
end;
procedure skip_type_header(file f:text) is
use STD.textio.all;
variable in_line : line;
begin
readline(f, in_line);
end procedure skip_type_header ;
file InputFile : text open read_mode is XFILE;
Begin
-- salt generator
skip_type_header(InputFile);
-- Reading Simulink Input
Input_pInput:process(clock, aclr)
variable s : string(1 to 3) ;
variable ptr : line ;
begin
if (aclr = '1') then
output <= (others=>'0');
elsif (not endfile(InputFile)) then
if clock'event and clock='0' then
readline(Inputfile, ptr);
read(ptr, s);
output <= to_std_logic_vector(s);
end if ;
end if ;
end process ;
end architecture;
|
mit
|
Given-Jiang/Add_Frame
|
tb_Add_Frame/db/alt_dspbuilder_testbench_capture_GNAXODEVVW.vhd
|
3
|
1775
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_capture_GNAXODEVVW is
generic ( XFILE : string := "default";
DSPBTYPE : string := "");
port(
clock : in std_logic;
aclr : in std_logic;
input : in std_logic_vector(15 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_capture_GNAXODEVVW is
function str(sl: std_logic) return character is
variable c: character;
begin
case sl is
when '0' => c := '0';
when '1' => c := '1';
when others => c := 'X';
end case;
return c;
end str;
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := str(slv(i));
r := r + 1;
end loop;
return result;
end str;
procedure write_type_header(file f:text) is
use STD.textio.all;
variable my_line : line;
begin
write ( my_line, DSPBTYPE);
writeline ( f, my_line );
end procedure write_type_header ;
file oFile : text open write_mode is XFILE;
Begin
-- data capture
-- write type information to output file
write_type_header(oFile);
-- Writing Output Signal into file
Output:process(clock)
variable traceline : line ;
begin
if (aclr ='1') then
-- do not record
elsif clock'event and clock='1' then
write(traceline, str(input),justified=>left);
writeline(oFile,traceline);
end if ;
end process ;
end architecture;
|
mit
|
danschultz/ace_polymer.dart
|
lib/src/ace-js/demo/kitchen-sink/docs/vhdl.vhd
|
472
|
830
|
library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
|
mit
|
Given-Jiang/Add_Frame
|
tb_Add_Frame/db/alt_dspbuilder_SBF.vhd
|
20
|
8869
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_SBF is
generic (
width_inl : natural :=10;
width_inr : natural :=10;
width_outl : natural :=8;
width_outr : natural :=8;
round : natural :=1;
satur : natural :=1;
lpm_signed : BusArithm :=BusIsSigned
);
port (
xin : in std_logic_vector(width_inl+width_inr-1 downto 0);
yout : out std_logic_vector(width_outl+width_outr-1 downto 0)
);
end alt_dspbuilder_SBF;
architecture SBF_SYNTH of alt_dspbuilder_SBF is
signal youtround : std_logic_vector(width_inl+width_outr-1 downto 0);
signal youtroundc : std_logic_vector(width_outl+width_outr-1 downto 0);
signal xinextc : std_logic_vector(width_outl+width_inr-1 downto 0) ;
signal xin_int : std_logic_vector(width_inl+width_inr-1 downto 0);
begin
u0: alt_dspbuilder_sAltrPropagate generic map(QTB=>DSPBuilderQTB, QTB_PRODUCT => DSPBuilderProduct, QTB_VERSION => DSPBuilderVersion , width=> width_inl+width_inr)
port map (d => xin, r => xin_int);
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--(width_inl>=width_outl) and (width_inr>=width_outr)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
sbf_a:if (width_inl>=width_outl) and (width_inr>=width_outr) generate
gnsnr:if (round = 0) generate
gnsat:if (satur=0) generate
gl:for i in 0 to width_outl+width_outr-1 generate
yout(i) <= xin_int(i+width_inr-width_outr);
end generate ;
end generate gnsat;
gsat:if (satur>0) generate
gl:for i in 0 to width_inl+width_outr-1 generate
youtround(i) <= xin_int(i+width_inr-width_outr);
end generate ;
us:alt_dspbuilder_ASAT
generic map ( widthin => width_inl+width_outr,
widthout => width_outl+width_outr,
lpm_signed => lpm_signed)
port map ( xin => youtround,
yout => yout);
end generate gsat;
end generate ;
rnd:if (round>0)generate
ura:alt_dspbuilder_AROUND
generic map ( widthin => width_inl+width_inr,
widthout => width_inl+width_outr)
port map ( xin => xin_int,
yout => youtround);
gns:if satur=0 generate
yout(width_outl+width_outr-1 downto 0) <= youtround(width_outl+width_outr-1 downto 0);
end generate gns;
gs:if (satur>0) generate
us:alt_dspbuilder_ASAT
generic map ( widthin => width_inl+width_outr,
widthout => width_outl+width_outr,
lpm_signed => lpm_signed)
port map ( xin => youtround,
yout => yout
);
end generate gs;
end generate rnd;
end generate sbf_a;
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
-- (width_inl>width_outl) and (width_inr<width_outr)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
sbf_b:if (width_inl>=width_outl) and (width_inr<width_outr) generate
ns:if (satur=0) generate
gc:for i in 0 to width_outr-width_inr-1 generate
yout(i) <= '0';
end generate gc;
gl:for i in width_outr-width_inr to width_outl+width_outr-1 generate
yout(i) <= xin_int(i+width_inr-width_outr);
end generate ;
end generate ns ;
gs:if (satur>0) generate
gc:for i in 0 to width_outr-width_inr-1 generate
youtround(i) <= '0';
end generate gc;
gl:for i in width_outr-width_inr to width_inl+width_outr-1 generate
youtround(i) <= xin_int(i+width_inr-width_outr);
end generate ;
us:alt_dspbuilder_ASAT
generic map ( widthin => width_inl+width_outr,
widthout => width_outl+width_outr,
lpm_signed => lpm_signed)
port map ( xin => youtround,
yout => yout);
end generate gs ;
end generate sbf_b;
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
-- (width_inl<width_outl) and (width_inr>width_outr)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
sbf_c:if (width_inl<width_outl) and (width_inr>=width_outr) generate
gnsnr:if (round = 0) generate
gl:for i in 0 to width_inl+width_outr-1 generate
yout(i) <= xin_int(i+width_inr-width_outr);
end generate ;
gc:for i in width_inl+width_outr to width_outl+width_outr-1 generate
yout(i) <= xin_int( width_inl+width_inr-1);
end generate ;
end generate ;
rnd:if (round > 0) generate
xinextc(width_inl+width_inr-1 downto 0) <= xin_int(width_inl+width_inr-1 downto 0);
gxinextc:for i in width_inl+width_inr to width_outl+width_inr-1 generate
xinextc(i) <= xin_int(width_inl+width_inr-1);
end generate gxinextc;
urb:alt_dspbuilder_AROUND
generic map ( widthin => width_outl+width_inr,
widthout => width_outl+width_outr)
port map ( xin => xinextc,
yout => youtroundc);
yout <= youtroundc;
end generate rnd ;
end generate sbf_c;
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
-- (width_inl<width_outl) and (width_inr<width_outr)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
sbf_d:if (width_inl<width_outl) and (width_inr<width_outr) generate
gl:for i in width_outr-width_inr to width_inl+width_outr-1 generate
yout(i) <= xin_int(i+width_inr-width_outr);
end generate gl;
gc:for i in 0 to width_outr-width_inr-1 generate
yout(i) <= '0';
end generate gc;
gcv:for i in width_inl+width_outr to width_outl+width_outr-1 generate
yout(i) <= xin_int( width_inl+width_inr-1);
end generate gcv;
end generate sbf_d;
end SBF_SYNTH;
|
mit
|
Given-Jiang/Add_Frame
|
tb_Add_Frame/hdl/alt_dspbuilder_logical_bit_op_GNA5ZFEL7V.vhd
|
20
|
806
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_logical_bit_op_GNA5ZFEL7V is
generic ( LogicalOp : string := "AltAND";
number_inputs : positive := 2);
port(
result : out std_logic;
data0 : in std_logic;
data1 : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_logical_bit_op_GNA5ZFEL7V is
Begin
-- Logical Bit Operation - Simulink Block "LogicalBitOperator"
LogicalBitOperatori : alt_dspbuilder_SBitLogical generic map (
LPM_WIDTH => 2,
LOP => AltAND)
port map (
dataa(0) => data0,
dataa(1) => data1,
result => result);
end architecture;
|
mit
|
Given-Jiang/Add_Frame
|
tb_Add_Frame/hdl/alt_dspbuilder_if_statement_GN7VA7SRUP.vhd
|
16
|
1471
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GN7VA7SRUP is
generic ( use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 0;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "(a=b) and (a /= c)";
number_inputs : integer := 3;
width : natural := 24);
port(
true : out std_logic;
a : in std_logic_vector(23 downto 0);
b : in std_logic_vector(23 downto 0);
c : in std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_if_statement_GN7VA7SRUP is
signal result : std_logic;
constant zero : STD_LOGIC_VECTOR(23 DOWNTO 0) := (others=>'0');
constant one : STD_LOGIC_VECTOR(23 DOWNTO 0) := (0 => '1', others => '0');
function myFunc ( Value: boolean )
return std_logic is
variable func_result : std_logic;
begin
if (Value) then
func_result := '1';
else
func_result := '0';
end if;
return func_result;
end;
function myFunc ( Value: std_logic )
return std_logic is
begin
return Value;
end;
Begin
-- DSP Builder Block - Simulink Block "IfStatement"
result <= myFunc((a=b) and (a /= c)) ;
true <= result;
end architecture;
|
mit
|
Given-Jiang/Add_Frame
|
Add_Frame_dspbuilder/hdl/alt_dspbuilder_decoder_GNAGWQMRGS.vhd
|
2
|
947
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_decoder_GNAGWQMRGS is
generic ( decode : string := "000000000000000000000000";
pipeline : natural := 0;
width : natural := 24);
port(
aclr : in std_logic;
clock : in std_logic;
data : in std_logic_vector((width)-1 downto 0);
dec : out std_logic;
ena : in std_logic;
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_decoder_GNAGWQMRGS is
Begin
-- DSP Builder Block - Simulink Block "Decoder"
Decoderi : alt_dspbuilder_sdecoderaltr Generic map (
width => 24,
decode => "000000000000000000000000",
pipeline => 0)
port map (
aclr => aclr,
user_aclr => '0',
sclr => sclr,
clock => clock,
data => data,
dec => dec);
end architecture;
|
mit
|
Given-Jiang/Add_Frame
|
tb_Add_Frame/hdl/alt_dspbuilder_bus_concat_GNAUBM7IRL.vhd
|
8
|
653
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_bus_concat_GNAUBM7IRL is
generic ( widthB : natural := 4;
widthA : natural := 4);
port(
a : in std_logic_vector((widthA)-1 downto 0);
aclr : in std_logic;
b : in std_logic_vector((widthB)-1 downto 0);
clock : in std_logic;
output : out std_logic_vector((widthA+widthB)-1 downto 0));
end entity;
architecture rtl of alt_dspbuilder_bus_concat_GNAUBM7IRL is
Begin
output <= a & b;
end architecture;
|
mit
|
lsangild/DSD
|
Exercise6/Alarm/Alarm.vhd
|
1
|
411
|
----- Libraries------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
----- Entity ------
entity Alarm is
port( bin_min1, bin_min10, bin_hrs1, bin_hrs10 : in std_logic_vector(3 downto 0);
time_alarm : out std_logic_vector(15 downto 0)
);
end Alarm;
-----Architecture-----
architecture Alerter of Alarm is
begin
time_alarm <= bin_hrs10 & bin_hrs1 & bin_min10 & bin_min1;
end Alerter;
|
mit
|
Given-Jiang/Add_Frame
|
tb_Add_Frame/db/Add_Frame_GN_Add_Frame_Add_Frame_Module_Frame_Par.vhd
|
2
|
34955
|
-- Add_Frame_GN_Add_Frame_Add_Frame_Module_Frame_Par.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.25.10:37:28
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Add_Frame_GN_Add_Frame_Add_Frame_Module_Frame_Par is
port (
width : out std_logic_vector(15 downto 0); -- width.wire
write : in std_logic := '0'; -- write.wire
writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- writedata.wire
addr : in std_logic_vector(2 downto 0) := (others => '0'); -- addr.wire
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0'; -- .reset
sop : in std_logic := '0'; -- sop.wire
height : out std_logic_vector(15 downto 0); -- height.wire
vertex_col : out std_logic_vector(15 downto 0); -- vertex_col.wire
vertex_row : out std_logic_vector(15 downto 0); -- vertex_row.wire
data : in std_logic := '0' -- data.wire
);
end entity Add_Frame_GN_Add_Frame_Add_Frame_Module_Frame_Par;
architecture rtl of Add_Frame_GN_Add_Frame_Add_Frame_Module_Frame_Par is
component alt_dspbuilder_clock_GNQFU4PUDH is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
component alt_dspbuilder_cast_GNNZHXLS76 is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(15 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNNZHXLS76;
component alt_dspbuilder_port_GNEPKLLZKY is
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(31 downto 0) -- wire
);
end component alt_dspbuilder_port_GNEPKLLZKY;
component alt_dspbuilder_port_GN37ALZBS4 is
port (
input : in std_logic := 'X'; -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_port_GN37ALZBS4;
component alt_dspbuilder_port_GNS2GDLO5E is
port (
input : in std_logic_vector(2 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(2 downto 0) -- wire
);
end component alt_dspbuilder_port_GNS2GDLO5E;
component alt_dspbuilder_port_GNBO6OMO5Y is
port (
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(15 downto 0) -- wire
);
end component alt_dspbuilder_port_GNBO6OMO5Y;
component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V;
component alt_dspbuilder_decoder_GNBHXAVAPH is
generic (
decode : string := "00000000";
pipeline : natural := 0;
width : natural := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
dec : out std_logic; -- wire
ena : in std_logic := 'X'; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_decoder_GNBHXAVAPH;
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_gnd_GN;
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_vcc_GN;
component alt_dspbuilder_decoder_GNSCEXJCJK is
generic (
decode : string := "00000000";
pipeline : natural := 0;
width : natural := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
dec : out std_logic; -- wire
ena : in std_logic := 'X'; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_decoder_GNSCEXJCJK;
component alt_dspbuilder_delay_GNWON5MXYC is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNWON5MXYC;
component alt_dspbuilder_decoder_GNQPHUITBS is
generic (
decode : string := "00000000";
pipeline : natural := 0;
width : natural := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
dec : out std_logic; -- wire
ena : in std_logic := 'X'; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_decoder_GNQPHUITBS;
component alt_dspbuilder_decoder_GN7W55JURN is
generic (
decode : string := "00000000";
pipeline : natural := 0;
width : natural := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
dec : out std_logic; -- wire
ena : in std_logic := 'X'; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_decoder_GN7W55JURN;
component alt_dspbuilder_decoder_GNBT6YIKS3 is
generic (
decode : string := "00000000";
pipeline : natural := 0;
width : natural := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
dec : out std_logic; -- wire
ena : in std_logic := 'X'; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_decoder_GNBT6YIKS3;
component alt_dspbuilder_cast_GNWMSU6SSZ is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic := 'X'; -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNWMSU6SSZ;
signal decoder2sclrgnd_output_wire : std_logic; -- Decoder2sclrGND:output -> Decoder2:sclr
signal decoder2enavcc_output_wire : std_logic; -- Decoder2enaVCC:output -> Decoder2:ena
signal decoder3sclrgnd_output_wire : std_logic; -- Decoder3sclrGND:output -> Decoder3:sclr
signal decoder3enavcc_output_wire : std_logic; -- Decoder3enaVCC:output -> Decoder3:ena
signal decoder1sclrgnd_output_wire : std_logic; -- Decoder1sclrGND:output -> Decoder1:sclr
signal decoder1enavcc_output_wire : std_logic; -- Decoder1enaVCC:output -> Decoder1:ena
signal delay6sclrgnd_output_wire : std_logic; -- Delay6sclrGND:output -> Delay6:sclr
signal delay5sclrgnd_output_wire : std_logic; -- Delay5sclrGND:output -> Delay5:sclr
signal delay4sclrgnd_output_wire : std_logic; -- Delay4sclrGND:output -> Delay4:sclr
signal delay9sclrgnd_output_wire : std_logic; -- Delay9sclrGND:output -> Delay9:sclr
signal delay8sclrgnd_output_wire : std_logic; -- Delay8sclrGND:output -> Delay8:sclr
signal delay7sclrgnd_output_wire : std_logic; -- Delay7sclrGND:output -> Delay7:sclr
signal decoder7sclrgnd_output_wire : std_logic; -- Decoder7sclrGND:output -> Decoder7:sclr
signal decoder7enavcc_output_wire : std_logic; -- Decoder7enaVCC:output -> Decoder7:ena
signal delay10sclrgnd_output_wire : std_logic; -- Delay10sclrGND:output -> Delay10:sclr
signal decodersclrgnd_output_wire : std_logic; -- DecodersclrGND:output -> Decoder:sclr
signal decoderenavcc_output_wire : std_logic; -- DecoderenaVCC:output -> Decoder:ena
signal decoder6sclrgnd_output_wire : std_logic; -- Decoder6sclrGND:output -> Decoder6:sclr
signal decoder6enavcc_output_wire : std_logic; -- Decoder6enaVCC:output -> Decoder6:ena
signal delay11sclrgnd_output_wire : std_logic; -- Delay11sclrGND:output -> Delay11:sclr
signal decoder5sclrgnd_output_wire : std_logic; -- Decoder5sclrGND:output -> Decoder5:sclr
signal decoder5enavcc_output_wire : std_logic; -- Decoder5enaVCC:output -> Decoder5:ena
signal decoder4sclrgnd_output_wire : std_logic; -- Decoder4sclrGND:output -> Decoder4:sclr
signal decoder4enavcc_output_wire : std_logic; -- Decoder4enaVCC:output -> Decoder4:ena
signal writedata_0_output_wire : std_logic_vector(31 downto 0); -- writedata_0:output -> [Bus_Conversion1:input, Bus_Conversion2:input, Bus_Conversion3:input, Bus_Conversion8:input]
signal addr_0_output_wire : std_logic_vector(2 downto 0); -- addr_0:output -> [Decoder2:data, Decoder4:data, Decoder6:data, Decoder:data]
signal bus_conversion8_output_wire : std_logic_vector(15 downto 0); -- Bus_Conversion8:output -> Delay10:input
signal delay10_output_wire : std_logic_vector(15 downto 0); -- Delay10:output -> Delay11:input
signal bus_conversion1_output_wire : std_logic_vector(15 downto 0); -- Bus_Conversion1:output -> Delay4:input
signal delay4_output_wire : std_logic_vector(15 downto 0); -- Delay4:output -> Delay5:input
signal bus_conversion2_output_wire : std_logic_vector(15 downto 0); -- Bus_Conversion2:output -> Delay6:input
signal delay6_output_wire : std_logic_vector(15 downto 0); -- Delay6:output -> Delay7:input
signal bus_conversion3_output_wire : std_logic_vector(15 downto 0); -- Bus_Conversion3:output -> Delay8:input
signal delay8_output_wire : std_logic_vector(15 downto 0); -- Delay8:output -> Delay9:input
signal decoder_dec_wire : std_logic; -- Decoder:dec -> Logical_Bit_Operator1:data0
signal write_0_output_wire : std_logic; -- write_0:output -> [Logical_Bit_Operator1:data1, Logical_Bit_Operator4:data1, Logical_Bit_Operator6:data1, Logical_Bit_Operator8:data1]
signal logical_bit_operator1_result_wire : std_logic; -- Logical_Bit_Operator1:result -> Delay4:ena
signal sop_0_output_wire : std_logic; -- sop_0:output -> [Logical_Bit_Operator3:data0, Logical_Bit_Operator5:data0, Logical_Bit_Operator7:data0, Logical_Bit_Operator9:data0]
signal decoder1_dec_wire : std_logic; -- Decoder1:dec -> Logical_Bit_Operator3:data1
signal logical_bit_operator3_result_wire : std_logic; -- Logical_Bit_Operator3:result -> Delay5:ena
signal decoder2_dec_wire : std_logic; -- Decoder2:dec -> Logical_Bit_Operator4:data0
signal logical_bit_operator4_result_wire : std_logic; -- Logical_Bit_Operator4:result -> Delay6:ena
signal decoder3_dec_wire : std_logic; -- Decoder3:dec -> Logical_Bit_Operator5:data1
signal logical_bit_operator5_result_wire : std_logic; -- Logical_Bit_Operator5:result -> Delay7:ena
signal decoder4_dec_wire : std_logic; -- Decoder4:dec -> Logical_Bit_Operator6:data0
signal logical_bit_operator6_result_wire : std_logic; -- Logical_Bit_Operator6:result -> Delay8:ena
signal decoder5_dec_wire : std_logic; -- Decoder5:dec -> Logical_Bit_Operator7:data1
signal logical_bit_operator7_result_wire : std_logic; -- Logical_Bit_Operator7:result -> Delay9:ena
signal decoder6_dec_wire : std_logic; -- Decoder6:dec -> Logical_Bit_Operator8:data0
signal logical_bit_operator8_result_wire : std_logic; -- Logical_Bit_Operator8:result -> Delay10:ena
signal decoder7_dec_wire : std_logic; -- Decoder7:dec -> Logical_Bit_Operator9:data1
signal logical_bit_operator9_result_wire : std_logic; -- Logical_Bit_Operator9:result -> Delay11:ena
signal delay5_output_wire : std_logic_vector(15 downto 0); -- Delay5:output -> vertex_col_0:input
signal delay7_output_wire : std_logic_vector(15 downto 0); -- Delay7:output -> vertex_row_0:input
signal delay9_output_wire : std_logic_vector(15 downto 0); -- Delay9:output -> width_0:input
signal delay11_output_wire : std_logic_vector(15 downto 0); -- Delay11:output -> height_0:input
signal data_0_output_wire : std_logic; -- data_0:output -> [cast223:input, cast224:input, cast225:input, cast226:input]
signal cast223_output_wire : std_logic_vector(23 downto 0); -- cast223:output -> Decoder5:data
signal cast224_output_wire : std_logic_vector(23 downto 0); -- cast224:output -> Decoder1:data
signal cast225_output_wire : std_logic_vector(23 downto 0); -- cast225:output -> Decoder7:data
signal cast226_output_wire : std_logic_vector(23 downto 0); -- cast226:output -> Decoder3:data
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Decoder1:aclr, Decoder2:aclr, Decoder3:aclr, Decoder4:aclr, Decoder5:aclr, Decoder6:aclr, Decoder7:aclr, Decoder:aclr, Delay10:aclr, Delay11:aclr, Delay4:aclr, Delay5:aclr, Delay6:aclr, Delay7:aclr, Delay8:aclr, Delay9:aclr]
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Decoder1:clock, Decoder2:clock, Decoder3:clock, Decoder4:clock, Decoder5:clock, Decoder6:clock, Decoder7:clock, Decoder:clock, Delay10:clock, Delay11:clock, Delay4:clock, Delay5:clock, Delay6:clock, Delay7:clock, Delay8:clock, Delay9:clock]
begin
clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr => aclr -- .reset
);
bus_conversion1 : component alt_dspbuilder_cast_GNNZHXLS76
generic map (
round => 0,
saturate => 0
)
port map (
input => writedata_0_output_wire, -- input.wire
output => bus_conversion1_output_wire -- output.wire
);
bus_conversion2 : component alt_dspbuilder_cast_GNNZHXLS76
generic map (
round => 0,
saturate => 0
)
port map (
input => writedata_0_output_wire, -- input.wire
output => bus_conversion2_output_wire -- output.wire
);
bus_conversion3 : component alt_dspbuilder_cast_GNNZHXLS76
generic map (
round => 0,
saturate => 0
)
port map (
input => writedata_0_output_wire, -- input.wire
output => bus_conversion3_output_wire -- output.wire
);
writedata_0 : component alt_dspbuilder_port_GNEPKLLZKY
port map (
input => writedata, -- input.wire
output => writedata_0_output_wire -- output.wire
);
data_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => data, -- input.wire
output => data_0_output_wire -- output.wire
);
addr_0 : component alt_dspbuilder_port_GNS2GDLO5E
port map (
input => addr, -- input.wire
output => addr_0_output_wire -- output.wire
);
vertex_row_0 : component alt_dspbuilder_port_GNBO6OMO5Y
port map (
input => delay7_output_wire, -- input.wire
output => vertex_row -- output.wire
);
logical_bit_operator7 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator7_result_wire, -- result.wire
data0 => sop_0_output_wire, -- data0.wire
data1 => decoder5_dec_wire -- data1.wire
);
logical_bit_operator6 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator6_result_wire, -- result.wire
data0 => decoder4_dec_wire, -- data0.wire
data1 => write_0_output_wire -- data1.wire
);
vertex_col_0 : component alt_dspbuilder_port_GNBO6OMO5Y
port map (
input => delay5_output_wire, -- input.wire
output => vertex_col -- output.wire
);
logical_bit_operator5 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator5_result_wire, -- result.wire
data0 => sop_0_output_wire, -- data0.wire
data1 => decoder3_dec_wire -- data1.wire
);
height_0 : component alt_dspbuilder_port_GNBO6OMO5Y
port map (
input => delay11_output_wire, -- input.wire
output => height -- output.wire
);
logical_bit_operator4 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator4_result_wire, -- result.wire
data0 => decoder2_dec_wire, -- data0.wire
data1 => write_0_output_wire -- data1.wire
);
logical_bit_operator9 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator9_result_wire, -- result.wire
data0 => sop_0_output_wire, -- data0.wire
data1 => decoder7_dec_wire -- data1.wire
);
logical_bit_operator8 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator8_result_wire, -- result.wire
data0 => decoder6_dec_wire, -- data0.wire
data1 => write_0_output_wire -- data1.wire
);
write_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => write, -- input.wire
output => write_0_output_wire -- output.wire
);
logical_bit_operator3 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator3_result_wire, -- result.wire
data0 => sop_0_output_wire, -- data0.wire
data1 => decoder1_dec_wire -- data1.wire
);
logical_bit_operator1 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator1_result_wire, -- result.wire
data0 => decoder_dec_wire, -- data0.wire
data1 => write_0_output_wire -- data1.wire
);
decoder2 : component alt_dspbuilder_decoder_GNBHXAVAPH
generic map (
decode => "010",
pipeline => 1,
width => 3
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => addr_0_output_wire, -- data.wire
dec => decoder2_dec_wire, -- dec.wire
sclr => decoder2sclrgnd_output_wire, -- sclr.wire
ena => decoder2enavcc_output_wire -- ena.wire
);
decoder2sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder2sclrgnd_output_wire -- output.wire
);
decoder2enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder2enavcc_output_wire -- output.wire
);
decoder3 : component alt_dspbuilder_decoder_GNSCEXJCJK
generic map (
decode => "000000000000000000001111",
pipeline => 0,
width => 24
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => cast226_output_wire, -- data.wire
dec => decoder3_dec_wire, -- dec.wire
sclr => decoder3sclrgnd_output_wire, -- sclr.wire
ena => decoder3enavcc_output_wire -- ena.wire
);
decoder3sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder3sclrgnd_output_wire -- output.wire
);
decoder3enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder3enavcc_output_wire -- output.wire
);
decoder1 : component alt_dspbuilder_decoder_GNSCEXJCJK
generic map (
decode => "000000000000000000001111",
pipeline => 0,
width => 24
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => cast224_output_wire, -- data.wire
dec => decoder1_dec_wire, -- dec.wire
sclr => decoder1sclrgnd_output_wire, -- sclr.wire
ena => decoder1enavcc_output_wire -- ena.wire
);
decoder1sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder1sclrgnd_output_wire -- output.wire
);
decoder1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder1enavcc_output_wire -- output.wire
);
width_0 : component alt_dspbuilder_port_GNBO6OMO5Y
port map (
input => delay9_output_wire, -- input.wire
output => width -- output.wire
);
delay6 : component alt_dspbuilder_delay_GNWON5MXYC
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0000000000001010",
width => 16
)
port map (
input => bus_conversion2_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay6_output_wire, -- output.wire
sclr => delay6sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator4_result_wire -- ena.wire
);
delay6sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay6sclrgnd_output_wire -- output.wire
);
delay5 : component alt_dspbuilder_delay_GNWON5MXYC
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0000000000001010",
width => 16
)
port map (
input => delay4_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay5_output_wire, -- output.wire
sclr => delay5sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator3_result_wire -- ena.wire
);
delay5sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay5sclrgnd_output_wire -- output.wire
);
delay4 : component alt_dspbuilder_delay_GNWON5MXYC
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0000000000001010",
width => 16
)
port map (
input => bus_conversion1_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay4_output_wire, -- output.wire
sclr => delay4sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator1_result_wire -- ena.wire
);
delay4sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay4sclrgnd_output_wire -- output.wire
);
sop_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => sop, -- input.wire
output => sop_0_output_wire -- output.wire
);
delay9 : component alt_dspbuilder_delay_GNWON5MXYC
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0000000000001010",
width => 16
)
port map (
input => delay8_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay9_output_wire, -- output.wire
sclr => delay9sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator7_result_wire -- ena.wire
);
delay9sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay9sclrgnd_output_wire -- output.wire
);
delay8 : component alt_dspbuilder_delay_GNWON5MXYC
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0000000000001010",
width => 16
)
port map (
input => bus_conversion3_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay8_output_wire, -- output.wire
sclr => delay8sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator6_result_wire -- ena.wire
);
delay8sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay8sclrgnd_output_wire -- output.wire
);
delay7 : component alt_dspbuilder_delay_GNWON5MXYC
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0000000000001010",
width => 16
)
port map (
input => delay6_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay7_output_wire, -- output.wire
sclr => delay7sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator5_result_wire -- ena.wire
);
delay7sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay7sclrgnd_output_wire -- output.wire
);
bus_conversion8 : component alt_dspbuilder_cast_GNNZHXLS76
generic map (
round => 0,
saturate => 0
)
port map (
input => writedata_0_output_wire, -- input.wire
output => bus_conversion8_output_wire -- output.wire
);
decoder7 : component alt_dspbuilder_decoder_GNSCEXJCJK
generic map (
decode => "000000000000000000001111",
pipeline => 0,
width => 24
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => cast225_output_wire, -- data.wire
dec => decoder7_dec_wire, -- dec.wire
sclr => decoder7sclrgnd_output_wire, -- sclr.wire
ena => decoder7enavcc_output_wire -- ena.wire
);
decoder7sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder7sclrgnd_output_wire -- output.wire
);
decoder7enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder7enavcc_output_wire -- output.wire
);
delay10 : component alt_dspbuilder_delay_GNWON5MXYC
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0000000000001010",
width => 16
)
port map (
input => bus_conversion8_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay10_output_wire, -- output.wire
sclr => delay10sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator8_result_wire -- ena.wire
);
delay10sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay10sclrgnd_output_wire -- output.wire
);
decoder : component alt_dspbuilder_decoder_GNQPHUITBS
generic map (
decode => "001",
pipeline => 1,
width => 3
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => addr_0_output_wire, -- data.wire
dec => decoder_dec_wire, -- dec.wire
sclr => decodersclrgnd_output_wire, -- sclr.wire
ena => decoderenavcc_output_wire -- ena.wire
);
decodersclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decodersclrgnd_output_wire -- output.wire
);
decoderenavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoderenavcc_output_wire -- output.wire
);
decoder6 : component alt_dspbuilder_decoder_GN7W55JURN
generic map (
decode => "100",
pipeline => 1,
width => 3
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => addr_0_output_wire, -- data.wire
dec => decoder6_dec_wire, -- dec.wire
sclr => decoder6sclrgnd_output_wire, -- sclr.wire
ena => decoder6enavcc_output_wire -- ena.wire
);
decoder6sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder6sclrgnd_output_wire -- output.wire
);
decoder6enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder6enavcc_output_wire -- output.wire
);
delay11 : component alt_dspbuilder_delay_GNWON5MXYC
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0000000000001010",
width => 16
)
port map (
input => delay10_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay11_output_wire, -- output.wire
sclr => delay11sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator9_result_wire -- ena.wire
);
delay11sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay11sclrgnd_output_wire -- output.wire
);
decoder5 : component alt_dspbuilder_decoder_GNSCEXJCJK
generic map (
decode => "000000000000000000001111",
pipeline => 0,
width => 24
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => cast223_output_wire, -- data.wire
dec => decoder5_dec_wire, -- dec.wire
sclr => decoder5sclrgnd_output_wire, -- sclr.wire
ena => decoder5enavcc_output_wire -- ena.wire
);
decoder5sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder5sclrgnd_output_wire -- output.wire
);
decoder5enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder5enavcc_output_wire -- output.wire
);
decoder4 : component alt_dspbuilder_decoder_GNBT6YIKS3
generic map (
decode => "011",
pipeline => 1,
width => 3
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => addr_0_output_wire, -- data.wire
dec => decoder4_dec_wire, -- dec.wire
sclr => decoder4sclrgnd_output_wire, -- sclr.wire
ena => decoder4enavcc_output_wire -- ena.wire
);
decoder4sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder4sclrgnd_output_wire -- output.wire
);
decoder4enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder4enavcc_output_wire -- output.wire
);
cast223 : component alt_dspbuilder_cast_GNWMSU6SSZ
generic map (
round => 0,
saturate => 0
)
port map (
input => data_0_output_wire, -- input.wire
output => cast223_output_wire -- output.wire
);
cast224 : component alt_dspbuilder_cast_GNWMSU6SSZ
generic map (
round => 0,
saturate => 0
)
port map (
input => data_0_output_wire, -- input.wire
output => cast224_output_wire -- output.wire
);
cast225 : component alt_dspbuilder_cast_GNWMSU6SSZ
generic map (
round => 0,
saturate => 0
)
port map (
input => data_0_output_wire, -- input.wire
output => cast225_output_wire -- output.wire
);
cast226 : component alt_dspbuilder_cast_GNWMSU6SSZ
generic map (
round => 0,
saturate => 0
)
port map (
input => data_0_output_wire, -- input.wire
output => cast226_output_wire -- output.wire
);
end architecture rtl; -- of Add_Frame_GN_Add_Frame_Add_Frame_Module_Frame_Par
|
mit
|
Given-Jiang/Add_Frame
|
tb_Add_Frame/hdl/alt_dspbuilder_constant_GNTKFCVCZO.vhd
|
1
|
576
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNTKFCVCZO is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000001001000000";
width : natural := 16);
port(
output : out std_logic_vector(15 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNTKFCVCZO is
Begin
-- Constant
output <= "0000001001000000";
end architecture;
|
mit
|
Given-Jiang/Add_Frame
|
tb_Add_Frame/hdl/alt_dspbuilder_constant_GNKFDCPWED.vhd
|
1
|
576
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNKFDCPWED is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000000000111111";
width : natural := 16);
port(
output : out std_logic_vector(15 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNKFDCPWED is
Begin
-- Constant
output <= "0000000000111111";
end architecture;
|
mit
|
Given-Jiang/Add_Frame
|
tb_Add_Frame/hdl/alt_dspbuilder_counter_GNW5IG44CT.vhd
|
4
|
1595
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_counter_GNW5IG44CT is
generic ( use_usr_aclr : string := "false";
use_ena : string := "false";
use_cin : string := "false";
use_sset : string := "false";
ndirection : natural := 1;
svalue : string := "1";
use_sload : string := "false";
use_sclr : string := "true";
use_cout : string := "false";
modulus : integer := -1;
use_cnt_ena : string := "true";
width : natural := 3;
use_aset : string := "false";
use_aload : string := "false";
avalue : string := "0");
port(
aclr : in std_logic;
aload : in std_logic;
aset : in std_logic;
cin : in std_logic;
clock : in std_logic;
cnt_ena : in std_logic;
cout : out std_logic;
data : in std_logic_vector((width)-1 downto 0);
direction : in std_logic;
ena : in std_logic;
q : out std_logic_vector((width)-1 downto 0);
sclr : in std_logic;
sload : in std_logic;
sset : in std_logic;
user_aclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_counter_GNW5IG44CT is
Begin
-- DSP Builder Block - Simulink Block "Counter"
Counteri : lpm_counter Generic map (
LPM_WIDTH => 3,
LPM_DIRECTION => "UP",
LPM_AVALUE => "0",
LPM_SVALUE => "1",
LPM_TYPE => "LPM_COUNTER"
)
port map (
clock => clock,
cnt_en => cnt_ena,
aclr => aclr,
sclr => sclr,
q => q);
end architecture;
|
mit
|
Given-Jiang/Add_Frame
|
Add_Frame_dspbuilder/hdl/alt_dspbuilder_port_GN37ALZBS4.vhd
|
20
|
449
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GN37ALZBS4 is
port(
input : in std_logic;
output : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_port_GN37ALZBS4 is
Begin
-- Straight Bypass block
output <= input;
end architecture;
|
mit
|
Given-Jiang/Add_Frame
|
tb_Add_Frame/db/alt_dspbuilder_port.vhd
|
10
|
637
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_port is
end entity alt_dspbuilder_port;
architecture rtl of alt_dspbuilder_port is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
mit
|
Given-Jiang/Add_Frame
|
tb_Add_Frame/hdl/tb_Add_Frame.vhd
|
2
|
25065
|
-- tb_Add_Frame.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.25.10:37:28
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tb_Add_Frame is
end entity tb_Add_Frame;
architecture rtl of tb_Add_Frame is
component Add_Frame_GN is
port (
Clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
Avalon_MM_Slave_address : in std_logic_vector(2 downto 0) := (others => 'X'); -- wire
Avalon_ST_Source_valid : out std_logic; -- wire
Avalon_MM_Slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
Avalon_ST_Source_endofpacket : out std_logic; -- wire
Avalon_ST_Source_startofpacket : out std_logic; -- wire
Avalon_MM_Slave_write : in std_logic := 'X'; -- wire
Avalon_ST_Sink_data : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
Avalon_ST_Sink_ready : out std_logic; -- wire
Avalon_ST_Sink_startofpacket : in std_logic := 'X'; -- wire
Avalon_ST_Sink_endofpacket : in std_logic := 'X'; -- wire
Avalon_ST_Source_data : out std_logic_vector(23 downto 0); -- wire
Avalon_ST_Sink_valid : in std_logic := 'X'; -- wire
Add_Frame_Add_Frame_Module_row_counter : out std_logic_vector(15 downto 0); -- wire
Add_Frame_Add_Frame_Module_state : out std_logic_vector(2 downto 0); -- wire
Add_Frame_Add_Frame_Module_CTRL_DECODER_decoder_row : out std_logic_vector(15 downto 0); -- wire
Add_Frame_Add_Frame_Module_CTRL_DECODER_decoder_col : out std_logic_vector(15 downto 0); -- wire
Add_Frame_Add_Frame_Module_frame_in : out std_logic_vector(0 downto 0); -- wire
Add_Frame_Add_Frame_Module_col_counter : out std_logic_vector(15 downto 0); -- wire
Avalon_ST_Source_ready : in std_logic := 'X' -- wire
);
end component Add_Frame_GN;
component alt_dspbuilder_testbench_clock_GNCGUFKHRR is
generic (
SIMULATION_START_CYCLE : natural := 4;
RESET_LATENCY : natural := 0;
RESET_REGISTER_CASCADE_DEPTH : natural := 0
);
port (
aclr_out : out std_logic; -- reset
clock_out : out std_logic; -- clk
reg_aclr_out : out std_logic; -- reset
tb_aclr : out std_logic -- reset
);
end component alt_dspbuilder_testbench_clock_GNCGUFKHRR;
component alt_dspbuilder_testbench_salt_GNUCY2GBID is
generic (
XFILE : string := "default"
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
output : out std_logic_vector(2 downto 0) -- wire
);
end component alt_dspbuilder_testbench_salt_GNUCY2GBID;
component alt_dspbuilder_testbench_salt_GN7Z4SHGOK is
generic (
XFILE : string := "default"
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
output : out std_logic_vector(31 downto 0) -- wire
);
end component alt_dspbuilder_testbench_salt_GN7Z4SHGOK;
component alt_dspbuilder_testbench_salt_GNDBMPYDND is
generic (
XFILE : string := "default"
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
output : out std_logic -- wire
);
end component alt_dspbuilder_testbench_salt_GNDBMPYDND;
component alt_dspbuilder_testbench_salt_GNOXVOQUET is
generic (
XFILE : string := "default"
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_testbench_salt_GNOXVOQUET;
component alt_dspbuilder_testbench_capture_GNQX2JTRTZ is
generic (
XFILE : string := "default";
DSPBTYPE : string := ""
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
input : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_testbench_capture_GNQX2JTRTZ;
component alt_dspbuilder_testbench_capture_GNHCRI5YMO is
generic (
XFILE : string := "default";
DSPBTYPE : string := ""
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
input : in std_logic_vector(23 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_testbench_capture_GNHCRI5YMO;
component alt_dspbuilder_testbench_capture_GNAXODEVVW is
generic (
XFILE : string := "default";
DSPBTYPE : string := ""
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
input : in std_logic_vector(15 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_testbench_capture_GNAXODEVVW;
component alt_dspbuilder_testbench_capture_GN32ABLG7V is
generic (
XFILE : string := "default";
DSPBTYPE : string := ""
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
input : in std_logic_vector(2 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_testbench_capture_GN32ABLG7V;
component alt_dspbuilder_testbench_capture_GNZUHKKGTG is
generic (
XFILE : string := "default";
DSPBTYPE : string := ""
);
port (
clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
input : in std_logic_vector(0 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_testbench_capture_GNZUHKKGTG;
signal salt_avalon_mm_slave_address_output_wire : std_logic_vector(2 downto 0); -- salt_Avalon_MM_Slave_address:output -> dut:Avalon_MM_Slave_address
signal clock_clock_tb_reset : std_logic; -- Clock:tb_aclr -> [salt_Avalon_MM_Slave_address:aclr, salt_Avalon_MM_Slave_write:aclr, salt_Avalon_MM_Slave_writedata:aclr, salt_Avalon_ST_Sink_data:aclr, salt_Avalon_ST_Sink_endofpacket:aclr, salt_Avalon_ST_Sink_startofpacket:aclr, salt_Avalon_ST_Sink_valid:aclr, salt_Avalon_ST_Source_ready:aclr]
signal clock_clock_tb_clk : std_logic; -- Clock:clock_out -> [capture_Add_Frame_Add_Frame_Module_CTRL_DECODER_decoder_col:clock, capture_Add_Frame_Add_Frame_Module_CTRL_DECODER_decoder_row:clock, capture_Add_Frame_Add_Frame_Module_col_counter:clock, capture_Add_Frame_Add_Frame_Module_frame_in:clock, capture_Add_Frame_Add_Frame_Module_row_counter:clock, capture_Add_Frame_Add_Frame_Module_state:clock, capture_Avalon_ST_Sink_ready:clock, capture_Avalon_ST_Source_data:clock, capture_Avalon_ST_Source_endofpacket:clock, capture_Avalon_ST_Source_startofpacket:clock, capture_Avalon_ST_Source_valid:clock, dut:Clock, salt_Avalon_MM_Slave_address:clock, salt_Avalon_MM_Slave_write:clock, salt_Avalon_MM_Slave_writedata:clock, salt_Avalon_ST_Sink_data:clock, salt_Avalon_ST_Sink_endofpacket:clock, salt_Avalon_ST_Sink_startofpacket:clock, salt_Avalon_ST_Sink_valid:clock, salt_Avalon_ST_Source_ready:clock]
signal salt_avalon_mm_slave_writedata_output_wire : std_logic_vector(31 downto 0); -- salt_Avalon_MM_Slave_writedata:output -> dut:Avalon_MM_Slave_writedata
signal salt_avalon_mm_slave_write_output_wire : std_logic; -- salt_Avalon_MM_Slave_write:output -> dut:Avalon_MM_Slave_write
signal salt_avalon_st_sink_data_output_wire : std_logic_vector(23 downto 0); -- salt_Avalon_ST_Sink_data:output -> dut:Avalon_ST_Sink_data
signal salt_avalon_st_sink_startofpacket_output_wire : std_logic; -- salt_Avalon_ST_Sink_startofpacket:output -> dut:Avalon_ST_Sink_startofpacket
signal salt_avalon_st_sink_endofpacket_output_wire : std_logic; -- salt_Avalon_ST_Sink_endofpacket:output -> dut:Avalon_ST_Sink_endofpacket
signal salt_avalon_st_sink_valid_output_wire : std_logic; -- salt_Avalon_ST_Sink_valid:output -> dut:Avalon_ST_Sink_valid
signal salt_avalon_st_source_ready_output_wire : std_logic; -- salt_Avalon_ST_Source_ready:output -> dut:Avalon_ST_Source_ready
signal dut_avalon_st_source_valid_wire : std_logic; -- dut:Avalon_ST_Source_valid -> capture_Avalon_ST_Source_valid:input
signal clock_clock_reg_reset_reset : std_logic; -- Clock:reg_aclr_out -> [capture_Add_Frame_Add_Frame_Module_CTRL_DECODER_decoder_col:aclr, capture_Add_Frame_Add_Frame_Module_CTRL_DECODER_decoder_row:aclr, capture_Add_Frame_Add_Frame_Module_col_counter:aclr, capture_Add_Frame_Add_Frame_Module_frame_in:aclr, capture_Add_Frame_Add_Frame_Module_row_counter:aclr, capture_Add_Frame_Add_Frame_Module_state:aclr, capture_Avalon_ST_Sink_ready:aclr, capture_Avalon_ST_Source_data:aclr, capture_Avalon_ST_Source_endofpacket:aclr, capture_Avalon_ST_Source_startofpacket:aclr, capture_Avalon_ST_Source_valid:aclr]
signal dut_avalon_st_source_endofpacket_wire : std_logic; -- dut:Avalon_ST_Source_endofpacket -> capture_Avalon_ST_Source_endofpacket:input
signal dut_avalon_st_source_startofpacket_wire : std_logic; -- dut:Avalon_ST_Source_startofpacket -> capture_Avalon_ST_Source_startofpacket:input
signal dut_avalon_st_sink_ready_wire : std_logic; -- dut:Avalon_ST_Sink_ready -> capture_Avalon_ST_Sink_ready:input
signal dut_avalon_st_source_data_wire : std_logic_vector(23 downto 0); -- dut:Avalon_ST_Source_data -> capture_Avalon_ST_Source_data:input
signal dut_add_frame_add_frame_module_row_counter_wire : std_logic_vector(15 downto 0); -- dut:Add_Frame_Add_Frame_Module_row_counter -> capture_Add_Frame_Add_Frame_Module_row_counter:input
signal dut_add_frame_add_frame_module_state_wire : std_logic_vector(2 downto 0); -- dut:Add_Frame_Add_Frame_Module_state -> capture_Add_Frame_Add_Frame_Module_state:input
signal dut_add_frame_add_frame_module_ctrl_decoder_decoder_row_wire : std_logic_vector(15 downto 0); -- dut:Add_Frame_Add_Frame_Module_CTRL_DECODER_decoder_row -> capture_Add_Frame_Add_Frame_Module_CTRL_DECODER_decoder_row:input
signal dut_add_frame_add_frame_module_ctrl_decoder_decoder_col_wire : std_logic_vector(15 downto 0); -- dut:Add_Frame_Add_Frame_Module_CTRL_DECODER_decoder_col -> capture_Add_Frame_Add_Frame_Module_CTRL_DECODER_decoder_col:input
signal dut_add_frame_add_frame_module_frame_in_wire : std_logic_vector(0 downto 0); -- dut:Add_Frame_Add_Frame_Module_frame_in -> capture_Add_Frame_Add_Frame_Module_frame_in:input
signal dut_add_frame_add_frame_module_col_counter_wire : std_logic_vector(15 downto 0); -- dut:Add_Frame_Add_Frame_Module_col_counter -> capture_Add_Frame_Add_Frame_Module_col_counter:input
signal clock_clock_output_reset : std_logic; -- Clock:aclr_out -> dut:aclr
begin
dut : component Add_Frame_GN
port map (
Clock => clock_clock_tb_clk, -- Clock.clk
aclr => clock_clock_output_reset, -- .reset
Avalon_MM_Slave_address => salt_avalon_mm_slave_address_output_wire, -- Avalon_MM_Slave_address.wire
Avalon_ST_Source_valid => dut_avalon_st_source_valid_wire, -- Avalon_ST_Source_valid.wire
Avalon_MM_Slave_writedata => salt_avalon_mm_slave_writedata_output_wire, -- Avalon_MM_Slave_writedata.wire
Avalon_ST_Source_endofpacket => dut_avalon_st_source_endofpacket_wire, -- Avalon_ST_Source_endofpacket.wire
Avalon_ST_Source_startofpacket => dut_avalon_st_source_startofpacket_wire, -- Avalon_ST_Source_startofpacket.wire
Avalon_MM_Slave_write => salt_avalon_mm_slave_write_output_wire, -- Avalon_MM_Slave_write.wire
Avalon_ST_Sink_data => salt_avalon_st_sink_data_output_wire, -- Avalon_ST_Sink_data.wire
Avalon_ST_Sink_ready => dut_avalon_st_sink_ready_wire, -- Avalon_ST_Sink_ready.wire
Avalon_ST_Sink_startofpacket => salt_avalon_st_sink_startofpacket_output_wire, -- Avalon_ST_Sink_startofpacket.wire
Avalon_ST_Sink_endofpacket => salt_avalon_st_sink_endofpacket_output_wire, -- Avalon_ST_Sink_endofpacket.wire
Avalon_ST_Source_data => dut_avalon_st_source_data_wire, -- Avalon_ST_Source_data.wire
Avalon_ST_Sink_valid => salt_avalon_st_sink_valid_output_wire, -- Avalon_ST_Sink_valid.wire
Add_Frame_Add_Frame_Module_row_counter => dut_add_frame_add_frame_module_row_counter_wire, -- Add_Frame_Add_Frame_Module_row_counter.wire
Add_Frame_Add_Frame_Module_state => dut_add_frame_add_frame_module_state_wire, -- Add_Frame_Add_Frame_Module_state.wire
Add_Frame_Add_Frame_Module_CTRL_DECODER_decoder_row => dut_add_frame_add_frame_module_ctrl_decoder_decoder_row_wire, -- Add_Frame_Add_Frame_Module_CTRL_DECODER_decoder_row.wire
Add_Frame_Add_Frame_Module_CTRL_DECODER_decoder_col => dut_add_frame_add_frame_module_ctrl_decoder_decoder_col_wire, -- Add_Frame_Add_Frame_Module_CTRL_DECODER_decoder_col.wire
Add_Frame_Add_Frame_Module_frame_in => dut_add_frame_add_frame_module_frame_in_wire, -- Add_Frame_Add_Frame_Module_frame_in.wire
Add_Frame_Add_Frame_Module_col_counter => dut_add_frame_add_frame_module_col_counter_wire, -- Add_Frame_Add_Frame_Module_col_counter.wire
Avalon_ST_Source_ready => salt_avalon_st_source_ready_output_wire -- Avalon_ST_Source_ready.wire
);
clock : component alt_dspbuilder_testbench_clock_GNCGUFKHRR
generic map (
SIMULATION_START_CYCLE => 5,
RESET_LATENCY => 0,
RESET_REGISTER_CASCADE_DEPTH => 0
)
port map (
clock_out => clock_clock_tb_clk, -- clock_tb.clk
tb_aclr => clock_clock_tb_reset, -- .reset
aclr_out => clock_clock_output_reset, -- clock_output.reset
reg_aclr_out => clock_clock_reg_reset_reset -- clock_reg_reset.reset
);
salt_avalon_mm_slave_address : component alt_dspbuilder_testbench_salt_GNUCY2GBID
generic map (
XFILE => "Add%5FFrame_Avalon-MM+Slave_address.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_mm_slave_address_output_wire -- output.wire
);
salt_avalon_mm_slave_writedata : component alt_dspbuilder_testbench_salt_GN7Z4SHGOK
generic map (
XFILE => "Add%5FFrame_Avalon-MM+Slave_writedata.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_mm_slave_writedata_output_wire -- output.wire
);
salt_avalon_mm_slave_write : component alt_dspbuilder_testbench_salt_GNDBMPYDND
generic map (
XFILE => "Add%5FFrame_Avalon-MM+Slave_write.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_mm_slave_write_output_wire -- output.wire
);
salt_avalon_st_sink_data : component alt_dspbuilder_testbench_salt_GNOXVOQUET
generic map (
XFILE => "Add%5FFrame_Avalon-ST+Sink_data.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_st_sink_data_output_wire -- output.wire
);
salt_avalon_st_sink_startofpacket : component alt_dspbuilder_testbench_salt_GNDBMPYDND
generic map (
XFILE => "Add%5FFrame_Avalon-ST+Sink_startofpacket.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_st_sink_startofpacket_output_wire -- output.wire
);
salt_avalon_st_sink_endofpacket : component alt_dspbuilder_testbench_salt_GNDBMPYDND
generic map (
XFILE => "Add%5FFrame_Avalon-ST+Sink_endofpacket.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_st_sink_endofpacket_output_wire -- output.wire
);
salt_avalon_st_sink_valid : component alt_dspbuilder_testbench_salt_GNDBMPYDND
generic map (
XFILE => "Add%5FFrame_Avalon-ST+Sink_valid.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_st_sink_valid_output_wire -- output.wire
);
salt_avalon_st_source_ready : component alt_dspbuilder_testbench_salt_GNDBMPYDND
generic map (
XFILE => "Add%5FFrame_Avalon-ST+Source_ready.salt"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_tb_reset, -- .reset
output => salt_avalon_st_source_ready_output_wire -- output.wire
);
capture_avalon_st_source_valid : component alt_dspbuilder_testbench_capture_GNQX2JTRTZ
generic map (
XFILE => "Add%5FFrame_Avalon-ST+Source_valid.capture.msim",
DSPBTYPE => "BIT [1, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_avalon_st_source_valid_wire -- input.wire
);
capture_avalon_st_source_endofpacket : component alt_dspbuilder_testbench_capture_GNQX2JTRTZ
generic map (
XFILE => "Add%5FFrame_Avalon-ST+Source_endofpacket.capture.msim",
DSPBTYPE => "BIT [1, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_avalon_st_source_endofpacket_wire -- input.wire
);
capture_avalon_st_source_startofpacket : component alt_dspbuilder_testbench_capture_GNQX2JTRTZ
generic map (
XFILE => "Add%5FFrame_Avalon-ST+Source_startofpacket.capture.msim",
DSPBTYPE => "BIT [1, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_avalon_st_source_startofpacket_wire -- input.wire
);
capture_avalon_st_sink_ready : component alt_dspbuilder_testbench_capture_GNQX2JTRTZ
generic map (
XFILE => "Add%5FFrame_Avalon-ST+Sink_ready.capture.msim",
DSPBTYPE => "BIT [1, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_avalon_st_sink_ready_wire -- input.wire
);
capture_avalon_st_source_data : component alt_dspbuilder_testbench_capture_GNHCRI5YMO
generic map (
XFILE => "Add%5FFrame_Avalon-ST+Source_data.capture.msim",
DSPBTYPE => "UINT [24, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_avalon_st_source_data_wire -- input.wire
);
capture_add_frame_add_frame_module_row_counter : component alt_dspbuilder_testbench_capture_GNAXODEVVW
generic map (
XFILE => "Add%5FFrame_Add+Frame+Module_row%5Fcounter.capture.msim",
DSPBTYPE => "UINT [16, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_add_frame_add_frame_module_row_counter_wire -- input.wire
);
capture_add_frame_add_frame_module_state : component alt_dspbuilder_testbench_capture_GN32ABLG7V
generic map (
XFILE => "Add%5FFrame_Add+Frame+Module_state.capture.msim",
DSPBTYPE => "INT [3, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_add_frame_add_frame_module_state_wire -- input.wire
);
capture_add_frame_add_frame_module_ctrl_decoder_decoder_row : component alt_dspbuilder_testbench_capture_GNAXODEVVW
generic map (
XFILE => "Add%5FFrame_Add+Frame+Module_CTRL%5FDECODER_decoder%5Frow.capture.msim",
DSPBTYPE => "UINT [16, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_add_frame_add_frame_module_ctrl_decoder_decoder_row_wire -- input.wire
);
capture_add_frame_add_frame_module_ctrl_decoder_decoder_col : component alt_dspbuilder_testbench_capture_GNAXODEVVW
generic map (
XFILE => "Add%5FFrame_Add+Frame+Module_CTRL%5FDECODER_decoder%5Fcol.capture.msim",
DSPBTYPE => "UINT [16, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_add_frame_add_frame_module_ctrl_decoder_decoder_col_wire -- input.wire
);
capture_add_frame_add_frame_module_frame_in : component alt_dspbuilder_testbench_capture_GNZUHKKGTG
generic map (
XFILE => "Add%5FFrame_Add+Frame+Module_frame%5Fin.capture.msim",
DSPBTYPE => "INT [1, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_add_frame_add_frame_module_frame_in_wire -- input.wire
);
capture_add_frame_add_frame_module_col_counter : component alt_dspbuilder_testbench_capture_GNAXODEVVW
generic map (
XFILE => "Add%5FFrame_Add+Frame+Module_col%5Fcounter.capture.msim",
DSPBTYPE => "UINT [16, 0]"
)
port map (
clock => clock_clock_tb_clk, -- clock_aclr.clk
aclr => clock_clock_reg_reset_reset, -- .reset
input => dut_add_frame_add_frame_module_col_counter_wire -- input.wire
);
end architecture rtl; -- of tb_Add_Frame
|
mit
|
Given-Jiang/Add_Frame
|
Add_Frame_dspbuilder/db/alt_dspbuilder_port_GNS2GDLO5E.vhd
|
4
|
487
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNS2GDLO5E is
port(
input : in std_logic_vector(2 downto 0);
output : out std_logic_vector(2 downto 0));
end entity;
architecture rtl of alt_dspbuilder_port_GNS2GDLO5E is
Begin
-- Straight Bypass block
output <= input;
end architecture;
|
mit
|
lsangild/DSD
|
Exercise5/GuessGame/GuessGame2.vhd
|
1
|
1244
|
-----Library statements -----
library ieee;
use ieee.std_logic_1164.all;
-----Entity declaration -----
entity GuessGame2 is
port(
inputs : in std_logic_vector(7 downto 0);
player : in std_logic;
set : in std_logic; -- set predefined value
show : in std_logic; -- Show predefined value
try : in std_logic; -- Evaluate guess
hex1 : out std_logic_vector(6 downto 0); -- 7seg ones
hex10 : out std_logic_vector(6 downto 0) -- 7seg tens
);
end GuessGame2;
architecture guessing of GuessGame2 is
-- declare signals, components here...
signal setValue, dispValue : std_logic_vector(7 downto 0) := "00000000";
begin
ones: entity work.DecimalSeg port map(bin => dispValue(3 downto 0), seg => hex1);
tens: entity work.DecimalSeg port map(bin => dispValue(7 downto 4), seg => hex10);
-- architecture body...
process(show, set, try)
begin
if set = '0' then
setValue <= inputs;
dispValue <= setValue; -- to avoid inferred latch
elsif show = '0' then
dispValue <= setValue;
elsif try = '0' then
if inputs < setValue then
dispValue <= "10101011";
elsif inputs > setValue then
dispValue <= "11001101";
else
dispValue <= "11101110";
end if;
else
dispValue <= inputs;
end if;
end process;
end architecture;
|
mit
|
Given-Jiang/Add_Frame
|
tb_Add_Frame/db/alt_dspbuilder_sImpulsen1Altr.vhd
|
8
|
3102
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sImpulsen1Altr is
generic (
Impulsedelay : positive
);
port (
clock : in std_logic;
ena : in std_logic :='1';
sclr : in std_logic :='0';
aclr : in std_logic :='0';
q : out std_logic
);
end alt_dspbuilder_sImpulsen1Altr ;
architecture syn of alt_dspbuilder_sImpulsen1Altr is
type States_ImpulseAltr is (sclear, slow, shigh,slowend);
signal current_state : States_ImpulseAltr;
signal next_state : States_ImpulseAltr;
signal count : std_logic_vector(ToNatural(nbitnecessary(Impulsedelay)-1) downto 0);
begin
rp:process(clock,aclr)
begin
if aclr='1' then
count <= (others=>'0');
current_state <= sclear;
elsif clock'event and clock='1' then
if (sclr='1') then
count <= (others=>'0');
current_state <= sclear;
elsif (ena='1') then
count <= count+int2ustd(1,nbitnecessary(Impulsedelay));
current_state <= next_state;
end if;
end if;
end process;
cp:process(count, current_state, sclr,ena)
begin
case current_state is
when sclear =>
q <= '0';
if (ena='1') and (sclr='0') then
next_state <= slow;
else
next_state <= sclear;
end if;
when slow =>
q <= '0';
if (sclr='1') then
next_state <= sclear;
elsif (count=int2ustd(Impulsedelay-1,nbitnecessary(Impulsedelay))) and (ena='1') then
next_state <= shigh;
else
next_state <= slow ;
end if;
when shigh =>
q <= '1';
if (sclr='1') then
next_state <= sclear;
elsif (ena='1') then
next_state <= slowend ;
else
next_state <= shigh;
end if;
when slowend =>
q <= '0';
if (sclr='1') then
next_state <= sclear;
else
next_state <= slowend ;
end if;
end case;
end process;
end syn;
|
mit
|
Given-Jiang/Add_Frame
|
tb_Add_Frame/hdl/alt_dspbuilder_cast_GNLWRZWTQF.vhd
|
8
|
852
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNLWRZWTQF is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(2 downto 0);
output : out std_logic_vector(2 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNLWRZWTQF is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 3 ,
width_inr=> 0,
width_outl=> 3,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(2 downto 0) => input,
yout => output
);
end architecture;
|
mit
|
lsangild/DSD
|
Exercise6/Clock6/output_files/reset_logic.vhd
|
2
|
544
|
----- Libraries------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
----- Entity ------
entity reset_logic is
port( reset_in : in std_logic;
reset_out : out std_logic;
hrs_bin1, hrs_bin10 : in std_logic_vector(3 downto 0)
);
end reset_logic;
-----Architecture-----
architecture resetter of reset_logic is
begin
process(reset_in, hrs_bin1, hrs_bin10)
begin
if (reset_in = '0' or ((hrs_bin10 & hrs_bin1) > "00100011")) then
reset_out <= '0';
else
reset_out <= '1';
end if;
end process;
end resetter;
|
mit
|
Given-Jiang/Add_Frame
|
Add_Frame_dspbuilder/hdl/alt_dspbuilder_decoder_GN7UJNSI7B.vhd
|
2
|
903
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_decoder_GN7UJNSI7B is
generic ( decode : string := "101";
pipeline : natural := 1;
width : natural := 3);
port(
aclr : in std_logic;
clock : in std_logic;
data : in std_logic_vector((width)-1 downto 0);
dec : out std_logic;
ena : in std_logic;
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_decoder_GN7UJNSI7B is
Begin
-- DSP Builder Block - Simulink Block "Decoder"
Decoderi : alt_dspbuilder_sdecoderaltr Generic map (
width => 3,
decode => "101",
pipeline => 1)
port map (
aclr => aclr,
user_aclr => '0',
sclr => sclr,
clock => clock,
data => data,
dec => dec);
end architecture;
|
mit
|
Given-Jiang/Add_Frame
|
tb_Add_Frame/hdl/alt_dspbuilder_testbench_capture_GNQX2JTRTZ.vhd
|
20
|
1755
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_capture_GNQX2JTRTZ is
generic ( XFILE : string := "default";
DSPBTYPE : string := "");
port(
clock : in std_logic;
aclr : in std_logic;
input : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_testbench_capture_GNQX2JTRTZ is
function str(sl: std_logic) return character is
variable c: character;
begin
case sl is
when '0' => c := '0';
when '1' => c := '1';
when others => c := 'X';
end case;
return c;
end str;
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := str(slv(i));
r := r + 1;
end loop;
return result;
end str;
procedure write_type_header(file f:text) is
use STD.textio.all;
variable my_line : line;
begin
write ( my_line, DSPBTYPE);
writeline ( f, my_line );
end procedure write_type_header ;
file oFile : text open write_mode is XFILE;
Begin
-- data capture
-- write type information to output file
write_type_header(oFile);
-- Writing Output Signal into file
Output:process(clock)
variable traceline : line ;
begin
if (aclr ='1') then
-- do not record
elsif clock'event and clock='1' then
write(traceline, str(input),justified=>left);
writeline(oFile,traceline);
end if ;
end process ;
end architecture;
|
mit
|
Given-Jiang/Add_Frame
|
Add_Frame_dspbuilder/db/Add_Frame_GN_Add_Frame_Add_Frame_Module_CTRL_DECODER.vhd
|
2
|
37667
|
-- Add_Frame_GN_Add_Frame_Add_Frame_Module_CTRL_DECODER.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.11:15:11
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Add_Frame_GN_Add_Frame_Add_Frame_Module_CTRL_DECODER is
port (
height : out std_logic_vector(15 downto 0); -- height.wire
width : out std_logic_vector(15 downto 0); -- width.wire
sop : in std_logic := '0'; -- sop.wire
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0'; -- .reset
data : in std_logic_vector(23 downto 0) := (others => '0'); -- data.wire
valid : in std_logic := '0' -- valid.wire
);
end entity Add_Frame_GN_Add_Frame_Add_Frame_Module_CTRL_DECODER;
architecture rtl of Add_Frame_GN_Add_Frame_Add_Frame_Module_CTRL_DECODER is
component alt_dspbuilder_clock_GNQFU4PUDH is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNQFU4PUDH;
component alt_dspbuilder_cast_GNHBD5Z3AF is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(3 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNHBD5Z3AF;
component alt_dspbuilder_cast_GNED3D3FSF is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(3 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNED3D3FSF;
component alt_dspbuilder_port_GN37ALZBS4 is
port (
input : in std_logic := 'X'; -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_port_GN37ALZBS4;
component alt_dspbuilder_cast_GNMU5M7DX7 is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(3 downto 0) -- wire
);
end component alt_dspbuilder_cast_GNMU5M7DX7;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_bus_concat_GNBH75ZTOD is
generic (
widthB : natural := 8;
widthA : natural := 8
);
port (
a : in std_logic_vector(widthA-1 downto 0) := (others => 'X'); -- wire
aclr : in std_logic := 'X'; -- clk
b : in std_logic_vector(widthB-1 downto 0) := (others => 'X'); -- wire
clock : in std_logic := 'X'; -- clk
output : out std_logic_vector(widthA+widthB-1 downto 0) -- wire
);
end component alt_dspbuilder_bus_concat_GNBH75ZTOD;
component alt_dspbuilder_bus_concat_GNXPBV3I7L is
generic (
widthB : natural := 8;
widthA : natural := 8
);
port (
a : in std_logic_vector(widthA-1 downto 0) := (others => 'X'); -- wire
aclr : in std_logic := 'X'; -- clk
b : in std_logic_vector(widthB-1 downto 0) := (others => 'X'); -- wire
clock : in std_logic := 'X'; -- clk
output : out std_logic_vector(widthA+widthB-1 downto 0) -- wire
);
end component alt_dspbuilder_bus_concat_GNXPBV3I7L;
component alt_dspbuilder_bus_concat_GNAUBM7IRL is
generic (
widthB : natural := 8;
widthA : natural := 8
);
port (
a : in std_logic_vector(widthA-1 downto 0) := (others => 'X'); -- wire
aclr : in std_logic := 'X'; -- clk
b : in std_logic_vector(widthB-1 downto 0) := (others => 'X'); -- wire
clock : in std_logic := 'X'; -- clk
output : out std_logic_vector(widthA+widthB-1 downto 0) -- wire
);
end component alt_dspbuilder_bus_concat_GNAUBM7IRL;
component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V;
component alt_dspbuilder_port_GNBO6OMO5Y is
port (
input : in std_logic_vector(15 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(15 downto 0) -- wire
);
end component alt_dspbuilder_port_GNBO6OMO5Y;
component alt_dspbuilder_if_statement_GNURIZNNI4 is
generic (
use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 1;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "a";
number_inputs : integer := 1;
width : natural := 8
);
port (
true : out std_logic; -- wire
a : in std_logic_vector(2 downto 0) := (others => 'X'); -- wire
b : in std_logic_vector(2 downto 0) := (others => 'X') -- wire
);
end component alt_dspbuilder_if_statement_GNURIZNNI4;
component alt_dspbuilder_constant_GNDDTJRE6Q is
generic (
HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000";
width : natural := 4
);
port (
output : out std_logic_vector(2 downto 0) -- wire
);
end component alt_dspbuilder_constant_GNDDTJRE6Q;
component alt_dspbuilder_delay_GNZCCH64DU is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNZCCH64DU;
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_gnd_GN;
component alt_dspbuilder_logical_bit_op_GNKUBZL4TE is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNKUBZL4TE;
component alt_dspbuilder_logical_bit_op_GNUQ2R64DV is
generic (
LogicalOp : string := "AltAND";
number_inputs : positive := 2
);
port (
result : out std_logic; -- wire
data0 : in std_logic := 'X'; -- wire
data1 : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_logical_bit_op_GNUQ2R64DV;
component alt_dspbuilder_decoder_GNAGWQMRGS is
generic (
decode : string := "00000000";
pipeline : natural := 0;
width : natural := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
dec : out std_logic; -- wire
ena : in std_logic := 'X'; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_decoder_GNAGWQMRGS;
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic -- wire
);
end component alt_dspbuilder_vcc_GN;
component alt_dspbuilder_delay_GNXEWPAYC5 is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNXEWPAYC5;
component alt_dspbuilder_counter_GNW5IG44CT is
generic (
use_usr_aclr : string := "false";
use_ena : string := "false";
use_cin : string := "false";
use_sset : string := "false";
ndirection : natural := 1;
svalue : string := "0";
use_sload : string := "false";
use_sclr : string := "false";
use_cout : string := "false";
modulus : integer := 256;
use_cnt_ena : string := "false";
width : natural := 8;
use_aset : string := "false";
use_aload : string := "false";
avalue : string := "0"
);
port (
aclr : in std_logic := 'X'; -- clk
aload : in std_logic := 'X'; -- wire
aset : in std_logic := 'X'; -- wire
cin : in std_logic := 'X'; -- wire
clock : in std_logic := 'X'; -- clk
cnt_ena : in std_logic := 'X'; -- wire
cout : out std_logic; -- wire
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
direction : in std_logic := 'X'; -- wire
ena : in std_logic := 'X'; -- wire
q : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X'; -- wire
sload : in std_logic := 'X'; -- wire
sset : in std_logic := 'X'; -- wire
user_aclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_counter_GNW5IG44CT;
component alt_dspbuilder_delay_GNGQ56ZS4N is
generic (
ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "00000001";
width : positive := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
ena : in std_logic := 'X'; -- wire
input : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(width-1 downto 0); -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_delay_GNGQ56ZS4N;
component alt_dspbuilder_decoder_GNSCEXJCJK is
generic (
decode : string := "00000000";
pipeline : natural := 0;
width : natural := 8
);
port (
aclr : in std_logic := 'X'; -- clk
clock : in std_logic := 'X'; -- clk
data : in std_logic_vector(width-1 downto 0) := (others => 'X'); -- wire
dec : out std_logic; -- wire
ena : in std_logic := 'X'; -- wire
sclr : in std_logic := 'X' -- wire
);
end component alt_dspbuilder_decoder_GNSCEXJCJK;
component alt_dspbuilder_cast_GN46N4UJ5S is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic := 'X'; -- wire
output : out std_logic_vector(0 downto 0) -- wire
);
end component alt_dspbuilder_cast_GN46N4UJ5S;
component alt_dspbuilder_cast_GNSB3OXIQS is
generic (
round : natural := 0;
saturate : natural := 0
);
port (
input : in std_logic_vector(0 downto 0) := (others => 'X'); -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_cast_GNSB3OXIQS;
signal delaysclrgnd_output_wire : std_logic; -- DelaysclrGND:output -> Delay:sclr
signal decoder2sclrgnd_output_wire : std_logic; -- Decoder2sclrGND:output -> Decoder2:sclr
signal decoder2enavcc_output_wire : std_logic; -- Decoder2enaVCC:output -> Decoder2:ena
signal decoder1sclrgnd_output_wire : std_logic; -- Decoder1sclrGND:output -> Decoder1:sclr
signal decoder1enavcc_output_wire : std_logic; -- Decoder1enaVCC:output -> Decoder1:ena
signal delay5sclrgnd_output_wire : std_logic; -- Delay5sclrGND:output -> Delay5:sclr
signal delay4sclrgnd_output_wire : std_logic; -- Delay4sclrGND:output -> Delay4:sclr
signal delay3sclrgnd_output_wire : std_logic; -- Delay3sclrGND:output -> Delay3:sclr
signal delay1sclrgnd_output_wire : std_logic; -- Delay1sclrGND:output -> Delay1:sclr
signal delay2sclrgnd_output_wire : std_logic; -- Delay2sclrGND:output -> Delay2:sclr
signal decodersclrgnd_output_wire : std_logic; -- DecodersclrGND:output -> Decoder:sclr
signal decoderenavcc_output_wire : std_logic; -- DecoderenaVCC:output -> Decoder:ena
signal bus_concatenation1_output_wire : std_logic_vector(7 downto 0); -- Bus_Concatenation1:output -> Bus_Concatenation2:a
signal bus_concatenation2_output_wire : std_logic_vector(11 downto 0); -- Bus_Concatenation2:output -> Bus_Concatenation3:a
signal bus_concatenation4_output_wire : std_logic_vector(7 downto 0); -- Bus_Concatenation4:output -> Bus_Concatenation5:a
signal bus_concatenation5_output_wire : std_logic_vector(11 downto 0); -- Bus_Concatenation5:output -> Bus_Concatenation6:a
signal bus_conversion1_output_wire : std_logic_vector(3 downto 0); -- Bus_Conversion1:output -> Bus_Concatenation1:a
signal bus_conversion2_output_wire : std_logic_vector(3 downto 0); -- Bus_Conversion2:output -> Bus_Concatenation1:b
signal bus_conversion3_output_wire : std_logic_vector(3 downto 0); -- Bus_Conversion3:output -> Bus_Concatenation2:b
signal bus_conversion4_output_wire : std_logic_vector(3 downto 0); -- Bus_Conversion4:output -> Bus_Concatenation3:b
signal bus_conversion5_output_wire : std_logic_vector(3 downto 0); -- Bus_Conversion5:output -> Bus_Concatenation4:a
signal bus_conversion6_output_wire : std_logic_vector(3 downto 0); -- Bus_Conversion6:output -> Bus_Concatenation4:b
signal bus_conversion7_output_wire : std_logic_vector(3 downto 0); -- Bus_Conversion7:output -> Bus_Concatenation5:b
signal bus_conversion8_output_wire : std_logic_vector(3 downto 0); -- Bus_Conversion8:output -> Bus_Concatenation6:b
signal data_0_output_wire : std_logic_vector(23 downto 0); -- data_0:output -> [Decoder1:data, Decoder2:data, Decoder:data, Delay5:input]
signal bus_concatenation3_output_wire : std_logic_vector(15 downto 0); -- Bus_Concatenation3:output -> Delay:input
signal bus_concatenation6_output_wire : std_logic_vector(15 downto 0); -- Bus_Concatenation6:output -> Delay2:input
signal delay3_output_wire : std_logic_vector(23 downto 0); -- Delay3:output -> [Bus_Conversion1:input, Bus_Conversion2:input, Bus_Conversion3:input]
signal delay4_output_wire : std_logic_vector(23 downto 0); -- Delay4:output -> [Bus_Conversion4:input, Bus_Conversion5:input, Bus_Conversion6:input, Delay3:input]
signal delay5_output_wire : std_logic_vector(23 downto 0); -- Delay5:output -> [Bus_Conversion7:input, Bus_Conversion8:input, Bus_Conversion9:input, Delay4:input]
signal constant2_output_wire : std_logic_vector(2 downto 0); -- Constant2:output -> If_Statement:a
signal counter_q_wire : std_logic_vector(2 downto 0); -- Counter:q -> If_Statement:b
signal decoder_dec_wire : std_logic; -- Decoder:dec -> Logical_Bit_Operator:data0
signal sop_0_output_wire : std_logic; -- sop_0:output -> [Logical_Bit_Operator2:data0, Logical_Bit_Operator4:data0, Logical_Bit_Operator:data1]
signal logical_bit_operator_result_wire : std_logic; -- Logical_Bit_Operator:result -> [Logical_Bit_Operator1:data0, cast6:input]
signal if_statement_true_wire : std_logic; -- If_Statement:true -> Logical_Bit_Operator1:data1
signal logical_bit_operator1_result_wire : std_logic; -- Logical_Bit_Operator1:result -> Delay1:ena
signal decoder1_dec_wire : std_logic; -- Decoder1:dec -> Logical_Bit_Operator2:data1
signal logical_bit_operator2_result_wire : std_logic; -- Logical_Bit_Operator2:result -> Delay:ena
signal logical_bit_operator3_result_wire : std_logic; -- Logical_Bit_Operator3:result -> Counter:sclr
signal decoder2_dec_wire : std_logic; -- Decoder2:dec -> Logical_Bit_Operator4:data1
signal logical_bit_operator4_result_wire : std_logic; -- Logical_Bit_Operator4:result -> Delay2:ena
signal valid_0_output_wire : std_logic; -- valid_0:output -> Logical_Bit_Operator5:data1
signal logical_bit_operator5_result_wire : std_logic; -- Logical_Bit_Operator5:result -> [Counter:cnt_ena, Delay3:ena, Delay4:ena, Delay5:ena]
signal delay_output_wire : std_logic_vector(15 downto 0); -- Delay:output -> width_0:input
signal delay2_output_wire : std_logic_vector(15 downto 0); -- Delay2:output -> height_0:input
signal cast6_output_wire : std_logic_vector(0 downto 0); -- cast6:output -> Delay1:input
signal delay1_output_wire : std_logic_vector(0 downto 0); -- Delay1:output -> [cast7:input, cast8:input]
signal cast7_output_wire : std_logic; -- cast7:output -> Logical_Bit_Operator3:data0
signal cast8_output_wire : std_logic; -- cast8:output -> Logical_Bit_Operator5:data0
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> [Bus_Concatenation1:aclr, Bus_Concatenation2:aclr, Bus_Concatenation3:aclr, Bus_Concatenation4:aclr, Bus_Concatenation5:aclr, Bus_Concatenation6:aclr, Counter:aclr, Decoder1:aclr, Decoder2:aclr, Decoder:aclr, Delay1:aclr, Delay2:aclr, Delay3:aclr, Delay4:aclr, Delay5:aclr, Delay:aclr]
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> [Bus_Concatenation1:clock, Bus_Concatenation2:clock, Bus_Concatenation3:clock, Bus_Concatenation4:clock, Bus_Concatenation5:clock, Bus_Concatenation6:clock, Counter:clock, Decoder1:clock, Decoder2:clock, Decoder:clock, Delay1:clock, Delay2:clock, Delay3:clock, Delay4:clock, Delay5:clock, Delay:clock]
begin
clock_0 : component alt_dspbuilder_clock_GNQFU4PUDH
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr => aclr -- .reset
);
bus_conversion1 : component alt_dspbuilder_cast_GNHBD5Z3AF
generic map (
round => 0,
saturate => 0
)
port map (
input => delay3_output_wire, -- input.wire
output => bus_conversion1_output_wire -- output.wire
);
bus_conversion2 : component alt_dspbuilder_cast_GNED3D3FSF
generic map (
round => 0,
saturate => 0
)
port map (
input => delay3_output_wire, -- input.wire
output => bus_conversion2_output_wire -- output.wire
);
valid_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => valid, -- input.wire
output => valid_0_output_wire -- output.wire
);
bus_conversion3 : component alt_dspbuilder_cast_GNMU5M7DX7
generic map (
round => 0,
saturate => 0
)
port map (
input => delay3_output_wire, -- input.wire
output => bus_conversion3_output_wire -- output.wire
);
bus_conversion4 : component alt_dspbuilder_cast_GNHBD5Z3AF
generic map (
round => 0,
saturate => 0
)
port map (
input => delay4_output_wire, -- input.wire
output => bus_conversion4_output_wire -- output.wire
);
data_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => data, -- input.wire
output => data_0_output_wire -- output.wire
);
bus_concatenation5 : component alt_dspbuilder_bus_concat_GNBH75ZTOD
generic map (
widthB => 4,
widthA => 8
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => bus_concatenation4_output_wire, -- a.wire
b => bus_conversion7_output_wire, -- b.wire
output => bus_concatenation5_output_wire -- output.wire
);
bus_concatenation6 : component alt_dspbuilder_bus_concat_GNXPBV3I7L
generic map (
widthB => 4,
widthA => 12
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => bus_concatenation5_output_wire, -- a.wire
b => bus_conversion8_output_wire, -- b.wire
output => bus_concatenation6_output_wire -- output.wire
);
bus_concatenation3 : component alt_dspbuilder_bus_concat_GNXPBV3I7L
generic map (
widthB => 4,
widthA => 12
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => bus_concatenation2_output_wire, -- a.wire
b => bus_conversion4_output_wire, -- b.wire
output => bus_concatenation3_output_wire -- output.wire
);
bus_concatenation4 : component alt_dspbuilder_bus_concat_GNAUBM7IRL
generic map (
widthB => 4,
widthA => 4
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => bus_conversion5_output_wire, -- a.wire
b => bus_conversion6_output_wire, -- b.wire
output => bus_concatenation4_output_wire -- output.wire
);
bus_concatenation1 : component alt_dspbuilder_bus_concat_GNAUBM7IRL
generic map (
widthB => 4,
widthA => 4
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => bus_conversion1_output_wire, -- a.wire
b => bus_conversion2_output_wire, -- b.wire
output => bus_concatenation1_output_wire -- output.wire
);
bus_concatenation2 : component alt_dspbuilder_bus_concat_GNBH75ZTOD
generic map (
widthB => 4,
widthA => 8
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
a => bus_concatenation1_output_wire, -- a.wire
b => bus_conversion3_output_wire, -- b.wire
output => bus_concatenation2_output_wire -- output.wire
);
logical_bit_operator5 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator5_result_wire, -- result.wire
data0 => cast8_output_wire, -- data0.wire
data1 => valid_0_output_wire -- data1.wire
);
height_0 : component alt_dspbuilder_port_GNBO6OMO5Y
port map (
input => delay2_output_wire, -- input.wire
output => height -- output.wire
);
logical_bit_operator4 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator4_result_wire, -- result.wire
data0 => sop_0_output_wire, -- data0.wire
data1 => decoder2_dec_wire -- data1.wire
);
if_statement : component alt_dspbuilder_if_statement_GNURIZNNI4
generic map (
use_else_output => 0,
bwr => 0,
use_else_input => 0,
signed => 0,
HDLTYPE => "STD_LOGIC_VECTOR",
if_expression => "(a<b)",
number_inputs => 2,
width => 3
)
port map (
true => if_statement_true_wire, -- true.wire
a => constant2_output_wire, -- a.wire
b => counter_q_wire -- b.wire
);
constant2 : component alt_dspbuilder_constant_GNDDTJRE6Q
generic map (
HDLTYPE => "STD_LOGIC_VECTOR",
BitPattern => "010",
width => 3
)
port map (
output => constant2_output_wire -- output.wire
);
delay : component alt_dspbuilder_delay_GNZCCH64DU
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0000000000000000",
width => 16
)
port map (
input => bus_concatenation3_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay_output_wire, -- output.wire
sclr => delaysclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator2_result_wire -- ena.wire
);
delaysclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delaysclrgnd_output_wire -- output.wire
);
logical_bit_operator3 : component alt_dspbuilder_logical_bit_op_GNKUBZL4TE
generic map (
LogicalOp => "AltNOT",
number_inputs => 1
)
port map (
result => logical_bit_operator3_result_wire, -- result.wire
data0 => cast7_output_wire -- data0.wire
);
logical_bit_operator2 : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator2_result_wire, -- result.wire
data0 => sop_0_output_wire, -- data0.wire
data1 => decoder1_dec_wire -- data1.wire
);
logical_bit_operator1 : component alt_dspbuilder_logical_bit_op_GNUQ2R64DV
generic map (
LogicalOp => "AltOR",
number_inputs => 2
)
port map (
result => logical_bit_operator1_result_wire, -- result.wire
data0 => logical_bit_operator_result_wire, -- data0.wire
data1 => if_statement_true_wire -- data1.wire
);
decoder2 : component alt_dspbuilder_decoder_GNAGWQMRGS
generic map (
decode => "000000000000000000000000",
pipeline => 0,
width => 24
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => data_0_output_wire, -- data.wire
dec => decoder2_dec_wire, -- dec.wire
sclr => decoder2sclrgnd_output_wire, -- sclr.wire
ena => decoder2enavcc_output_wire -- ena.wire
);
decoder2sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder2sclrgnd_output_wire -- output.wire
);
decoder2enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder2enavcc_output_wire -- output.wire
);
decoder1 : component alt_dspbuilder_decoder_GNAGWQMRGS
generic map (
decode => "000000000000000000000000",
pipeline => 0,
width => 24
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => data_0_output_wire, -- data.wire
dec => decoder1_dec_wire, -- dec.wire
sclr => decoder1sclrgnd_output_wire, -- sclr.wire
ena => decoder1enavcc_output_wire -- ena.wire
);
decoder1sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decoder1sclrgnd_output_wire -- output.wire
);
decoder1enavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoder1enavcc_output_wire -- output.wire
);
logical_bit_operator : component alt_dspbuilder_logical_bit_op_GNA5ZFEL7V
generic map (
LogicalOp => "AltAND",
number_inputs => 2
)
port map (
result => logical_bit_operator_result_wire, -- result.wire
data0 => decoder_dec_wire, -- data0.wire
data1 => sop_0_output_wire -- data1.wire
);
width_0 : component alt_dspbuilder_port_GNBO6OMO5Y
port map (
input => delay_output_wire, -- input.wire
output => width -- output.wire
);
delay5 : component alt_dspbuilder_delay_GNXEWPAYC5
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "000000000000000000000001",
width => 24
)
port map (
input => data_0_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay5_output_wire, -- output.wire
sclr => delay5sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator5_result_wire -- ena.wire
);
delay5sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay5sclrgnd_output_wire -- output.wire
);
counter : component alt_dspbuilder_counter_GNW5IG44CT
generic map (
use_usr_aclr => "false",
use_ena => "false",
use_cin => "false",
use_sset => "false",
ndirection => 1,
svalue => "1",
use_sload => "false",
use_sclr => "true",
use_cout => "false",
modulus => -1,
use_cnt_ena => "true",
width => 3,
use_aset => "false",
use_aload => "false",
avalue => "0"
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
cnt_ena => logical_bit_operator5_result_wire, -- cnt_ena.wire
sclr => logical_bit_operator3_result_wire, -- sclr.wire
q => counter_q_wire, -- q.wire
cout => open -- cout.wire
);
delay4 : component alt_dspbuilder_delay_GNXEWPAYC5
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "000000000000000000000001",
width => 24
)
port map (
input => delay5_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay4_output_wire, -- output.wire
sclr => delay4sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator5_result_wire -- ena.wire
);
delay4sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay4sclrgnd_output_wire -- output.wire
);
delay3 : component alt_dspbuilder_delay_GNXEWPAYC5
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "000000000000000000000001",
width => 24
)
port map (
input => delay4_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay3_output_wire, -- output.wire
sclr => delay3sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator5_result_wire -- ena.wire
);
delay3sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay3sclrgnd_output_wire -- output.wire
);
sop_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => sop, -- input.wire
output => sop_0_output_wire -- output.wire
);
delay1 : component alt_dspbuilder_delay_GNGQ56ZS4N
generic map (
ClockPhase => "1",
delay => 1,
use_init => 0,
BitPattern => "1",
width => 1
)
port map (
input => cast6_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay1_output_wire, -- output.wire
sclr => delay1sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator1_result_wire -- ena.wire
);
delay1sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay1sclrgnd_output_wire -- output.wire
);
delay2 : component alt_dspbuilder_delay_GNZCCH64DU
generic map (
ClockPhase => "1",
delay => 1,
use_init => 1,
BitPattern => "0000000000000000",
width => 16
)
port map (
input => bus_concatenation6_output_wire, -- input.wire
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
output => delay2_output_wire, -- output.wire
sclr => delay2sclrgnd_output_wire, -- sclr.wire
ena => logical_bit_operator4_result_wire -- ena.wire
);
delay2sclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => delay2sclrgnd_output_wire -- output.wire
);
bus_conversion9 : component alt_dspbuilder_cast_GNMU5M7DX7
generic map (
round => 0,
saturate => 0
)
port map (
input => delay5_output_wire, -- input.wire
output => open -- output.wire
);
bus_conversion8 : component alt_dspbuilder_cast_GNED3D3FSF
generic map (
round => 0,
saturate => 0
)
port map (
input => delay5_output_wire, -- input.wire
output => bus_conversion8_output_wire -- output.wire
);
bus_conversion7 : component alt_dspbuilder_cast_GNHBD5Z3AF
generic map (
round => 0,
saturate => 0
)
port map (
input => delay5_output_wire, -- input.wire
output => bus_conversion7_output_wire -- output.wire
);
decoder : component alt_dspbuilder_decoder_GNSCEXJCJK
generic map (
decode => "000000000000000000001111",
pipeline => 0,
width => 24
)
port map (
clock => clock_0_clock_output_clk, -- clock_aclr.clk
aclr => clock_0_clock_output_reset, -- .reset
data => data_0_output_wire, -- data.wire
dec => decoder_dec_wire, -- dec.wire
sclr => decodersclrgnd_output_wire, -- sclr.wire
ena => decoderenavcc_output_wire -- ena.wire
);
decodersclrgnd : component alt_dspbuilder_gnd_GN
port map (
output => decodersclrgnd_output_wire -- output.wire
);
decoderenavcc : component alt_dspbuilder_vcc_GN
port map (
output => decoderenavcc_output_wire -- output.wire
);
bus_conversion6 : component alt_dspbuilder_cast_GNMU5M7DX7
generic map (
round => 0,
saturate => 0
)
port map (
input => delay4_output_wire, -- input.wire
output => bus_conversion6_output_wire -- output.wire
);
bus_conversion5 : component alt_dspbuilder_cast_GNED3D3FSF
generic map (
round => 0,
saturate => 0
)
port map (
input => delay4_output_wire, -- input.wire
output => bus_conversion5_output_wire -- output.wire
);
cast6 : component alt_dspbuilder_cast_GN46N4UJ5S
generic map (
round => 0,
saturate => 0
)
port map (
input => logical_bit_operator_result_wire, -- input.wire
output => cast6_output_wire -- output.wire
);
cast7 : component alt_dspbuilder_cast_GNSB3OXIQS
generic map (
round => 0,
saturate => 0
)
port map (
input => delay1_output_wire, -- input.wire
output => cast7_output_wire -- output.wire
);
cast8 : component alt_dspbuilder_cast_GNSB3OXIQS
generic map (
round => 0,
saturate => 0
)
port map (
input => delay1_output_wire, -- input.wire
output => cast8_output_wire -- output.wire
);
end architecture rtl; -- of Add_Frame_GN_Add_Frame_Add_Frame_Module_CTRL_DECODER
|
mit
|
Given-Jiang/Add_Frame
|
Add_Frame_dspbuilder/db/alt_dspbuilder_port_GNXAOKDYKC.vhd
|
4
|
487
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNXAOKDYKC is
port(
input : in std_logic_vector(0 downto 0);
output : out std_logic_vector(0 downto 0));
end entity;
architecture rtl of alt_dspbuilder_port_GNXAOKDYKC is
Begin
-- Straight Bypass block
output <= input;
end architecture;
|
mit
|
Given-Jiang/Add_Frame
|
tb_Add_Frame/hdl/alt_dspbuilder_counter_GNCXNZXIE5.vhd
|
1
|
1618
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_counter_GNCXNZXIE5 is
generic ( use_usr_aclr : string := "false";
use_ena : string := "false";
use_cin : string := "false";
use_sset : string := "false";
ndirection : natural := 1;
svalue : string := "1";
use_sload : string := "false";
use_sclr : string := "true";
use_cout : string := "false";
modulus : integer := 7;
use_cnt_ena : string := "true";
width : natural := 3;
use_aset : string := "false";
use_aload : string := "false";
avalue : string := "0");
port(
aclr : in std_logic;
aload : in std_logic;
aset : in std_logic;
cin : in std_logic;
clock : in std_logic;
cnt_ena : in std_logic;
cout : out std_logic;
data : in std_logic_vector((width)-1 downto 0);
direction : in std_logic;
ena : in std_logic;
q : out std_logic_vector((width)-1 downto 0);
sclr : in std_logic;
sload : in std_logic;
sset : in std_logic;
user_aclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_counter_GNCXNZXIE5 is
Begin
-- DSP Builder Block - Simulink Block "Counter"
Counteri : lpm_counter Generic map (
LPM_WIDTH => 3,
LPM_DIRECTION => "UP",
LPM_MODULUS => 7,
LPM_AVALUE => "0",
LPM_SVALUE => "1",
LPM_TYPE => "LPM_COUNTER"
)
port map (
clock => clock,
cnt_en => cnt_ena,
aclr => aclr,
sclr => sclr,
q => q);
end architecture;
|
mit
|
Given-Jiang/Add_Frame
|
tb_Add_Frame/altera_lnsim/common_porta_latches/_primary.vhd
|
5
|
935
|
library verilog;
use verilog.vl_types.all;
entity common_porta_latches is
generic(
addr_register_width: integer := 1;
datain_register_width: integer := 1;
byteena_register_width: integer := 1
);
port(
addr_d : in vl_logic_vector;
datain_d : in vl_logic_vector;
byteena_d : in vl_logic_vector;
clk : in vl_logic;
ena : in vl_logic;
addr_q : out vl_logic_vector;
datain_q : out vl_logic_vector;
byteena_q : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of addr_register_width : constant is 1;
attribute mti_svvh_generic_type of datain_register_width : constant is 1;
attribute mti_svvh_generic_type of byteena_register_width : constant is 1;
end common_porta_latches;
|
mit
|
Given-Jiang/Add_Frame
|
tb_Add_Frame/hdl/alt_dspbuilder_sImpulse1nAltr.vhd
|
8
|
2837
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sImpulse1nAltr is
generic (
Impulsewidth : positive
);
port (
clock : in std_logic;
ena : in std_logic :='1';
sclr : in std_logic :='0';
aclr : in std_logic :='0';
q : out std_logic
);
end alt_dspbuilder_sImpulse1nAltr ;
architecture syn of alt_dspbuilder_sImpulse1nAltr is
type States_ImpulseAltr is (sclear, shigh,slowend);
signal current_state : States_ImpulseAltr;
signal next_state : States_ImpulseAltr;
signal count : std_logic_vector(ToNatural(nbitnecessary(Impulsewidth)-1) downto 0);
begin
rp:process(clock,aclr)
begin
if aclr='1' then
current_state <= sclear;
count <= (others=>'0');
elsif clock'event and clock='1' then
if (sclr='1') then
current_state <= sclear;
count <= (others=>'0');
elsif (ena='1') then
current_state <= next_state;
count <= count+int2ustd(1,nbitnecessary(Impulsewidth));
end if;
end if;
end process;
cp:process(count,current_state, sclr,ena)
begin
case current_state is
when sclear =>
q <= '0';
if (ena='1') and (sclr='0') then
next_state <= shigh;
else
next_state <= sclear;
end if;
when shigh =>
q <= '1';
if (sclr='1') then
next_state <= sclear;
elsif (count=int2ustd(Impulsewidth,nbitnecessary(Impulsewidth))) and (ena='1') then
next_state <= slowend ;
else
next_state <= shigh;
end if;
when slowend =>
q <= '0';
if (sclr='1') then
next_state <= sclear;
else
next_state <= slowend ;
end if;
end case;
end process;
end syn;
|
mit
|
Given-Jiang/Add_Frame
|
tb_Add_Frame/db/alt_dspbuilder_sMuxAltr.vhd
|
20
|
3446
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library altera;
use altera.alt_dspbuilder_package.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity alt_dspbuilder_sMuxAltr is
generic ( lpm_pipeline : natural:=0;
lpm_size : positive:=5;
lpm_widths : positive:=3;
lpm_width : positive:=8;
SelOneHot : natural:=0);
PORT ( clock : in std_logic ;
aclr : in std_logic := '0';
user_aclr : in std_logic := '0';
ena : in std_logic := '1';
data : in std_logic_vector (lpm_width*lpm_size-1 downto 0);
sel : in std_logic_vector (lpm_widths-1 downto 0);
result : out std_logic_vector (lpm_width-1 downto 0));
end alt_dspbuilder_sMuxAltr;
architecture synth of alt_dspbuilder_sMuxAltr is
function salive( ipp : integer; w : natural ) return std_logic_vector is
variable sxbus : std_logic_vector(w-1 downto 0);
begin
for i in 0 to w-1 loop
if ipp=i then
sxbus(i) :='1';
else
sxbus(i) :='0';
end if;
end loop;
return sxbus;
end;
signal selint : std_logic_vector(nbitnecessary(lpm_size)-1 downto 0);
signal dataa : std_logic_2d (lpm_size-1 downto 0, lpm_width-1 downto 0);
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
gnoh:if SelOneHot=0 generate
selint <= sel;
end generate gnoh;
g_one_hot:if SelOneHot>0 generate
gi:for i in 0 to lpm_size-1 generate
selint <= int2ustd(i,nbitnecessary(lpm_size)) when sel = salive(i, lpm_size) else (others=>'Z');
end generate gi;
end generate g_one_hot;
g2d:for i in 1 to lpm_size generate
gw:for j in 0 to lpm_width-1 generate
dataa(i-1,j) <= data(j+(i-1)*lpm_width);
end generate gw;
end generate g2d;
gp:if lpm_pipeline>0 generate
U0 : lpm_mux generic map ( lpm_pipeline => lpm_pipeline,
lpm_size => lpm_size,
lpm_widths => nbitnecessary(lpm_size),
lpm_width => lpm_width,
lpm_type => "LPM_MUX")
port map ( sel => selint,
clken => ena,
aclr => aclr_i,
clock => clock,
data => dataa,
result => result);
end generate gp;
gc:if lpm_pipeline=0 generate
U0 : lpm_mux generic map ( lpm_size => lpm_size,
lpm_widths => nbitnecessary(lpm_size),
lpm_width => lpm_width,
lpm_type => "LPM_MUX")
port map ( sel => selint,
data => dataa,
result => result);
end generate gc;
end synth;
|
mit
|
lsangild/DSD
|
Exercise5/8inputNAND/oInputNAND.vhd
|
1
|
433
|
-----Libraries-----
library ieee;
use ieee.std_logic_1164.all;
-----Entities-----
entity OinputNAND is
port( a : in std_logic_vector(7 downto 0);
y : out std_logic
);
end oinputNAND;
-----Architectures-----
architecture oNAND of OinputNAND is
begin
po: process(a)
variable equal : std_logic;
begin
equal:= '1';
for index in 7 downto 0 loop
equal := equal and a(index);
end loop;
y <= NOT equal;
end process;
end oNAND;
|
mit
|
Given-Jiang/Add_Frame
|
tb_Add_Frame/hdl/alt_dspbuilder_port_GNEPKLLZKY.vhd
|
17
|
489
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNEPKLLZKY is
port(
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of alt_dspbuilder_port_GNEPKLLZKY is
Begin
-- Straight Bypass block
output <= input;
end architecture;
|
mit
|
Given-Jiang/Add_Frame
|
Add_Frame_dspbuilder/hdl/alt_dspbuilder_delay_GNHYCSAEGT.vhd
|
16
|
1037
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNHYCSAEGT is
generic ( ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 0;
BitPattern : string := "0";
width : positive := 1);
port(
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
input : in std_logic_vector((width)-1 downto 0);
output : out std_logic_vector((width)-1 downto 0);
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_delay_GNHYCSAEGT is
Begin
-- Delay Element
Delay1i : alt_dspbuilder_SDelay generic map (
LPM_WIDTH => 1,
LPM_DELAY => 1,
SequenceLength => 1,
SequenceValue => "1")
port map (
dataa => input,
clock => clock,
ena => ena,
sclr => sclr,
aclr => aclr,
user_aclr => '0',
result => output);
end architecture;
|
mit
|
Given-Jiang/Add_Frame
|
tb_Add_Frame/hdl/alt_dspbuilder_decoder_GNSCEXJCJK.vhd
|
13
|
947
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_decoder_GNSCEXJCJK is
generic ( decode : string := "000000000000000000001111";
pipeline : natural := 0;
width : natural := 24);
port(
aclr : in std_logic;
clock : in std_logic;
data : in std_logic_vector((width)-1 downto 0);
dec : out std_logic;
ena : in std_logic;
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_decoder_GNSCEXJCJK is
Begin
-- DSP Builder Block - Simulink Block "Decoder"
Decoderi : alt_dspbuilder_sdecoderaltr Generic map (
width => 24,
decode => "000000000000000000001111",
pipeline => 0)
port map (
aclr => aclr,
user_aclr => '0',
sclr => sclr,
clock => clock,
data => data,
dec => dec);
end architecture;
|
mit
|
Given-Jiang/Add_Frame
|
Add_Frame_dspbuilder/hdl/alt_dspbuilder_decoder_GNSCEXJCJK.vhd
|
13
|
947
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_decoder_GNSCEXJCJK is
generic ( decode : string := "000000000000000000001111";
pipeline : natural := 0;
width : natural := 24);
port(
aclr : in std_logic;
clock : in std_logic;
data : in std_logic_vector((width)-1 downto 0);
dec : out std_logic;
ena : in std_logic;
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_decoder_GNSCEXJCJK is
Begin
-- DSP Builder Block - Simulink Block "Decoder"
Decoderi : alt_dspbuilder_sdecoderaltr Generic map (
width => 24,
decode => "000000000000000000001111",
pipeline => 0)
port map (
aclr => aclr,
user_aclr => '0',
sclr => sclr,
clock => clock,
data => data,
dec => dec);
end architecture;
|
mit
|
Given-Jiang/Add_Frame
|
Add_Frame_dspbuilder/reports/Add_Frame/tb_Add_Frame_example.vhd
|
2
|
296
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity tb_Add_Frame_example is
end entity;
architecture rtl of tb_Add_Frame_example is
component tb_Add_Frame
end component;
begin
tb_Add_Frame_instance :
component tb_Add_Frame
port map();
end architecture rtl;
|
mit
|
Given-Jiang/Add_Frame
|
tb_Add_Frame/hdl/alt_dspbuilder_vecseq.vhd
|
20
|
2951
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_vecseq is
generic (
SequenceLength : positive :=15;
SequenceValue : std_logic_vector := "100001110001001"
);
port (
clock : in std_logic ;
ena : in std_logic :='1';
sclr : in std_logic :='0';
aclr : in std_logic :='0';
yout : out std_logic
);
end alt_dspbuilder_vecseq;
architecture seq_SYNTH of alt_dspbuilder_vecseq is
signal clr_signal : STD_LOGIC;
signal lclr_signal : STD_LOGIC;
signal counter : std_logic_vector(ToNatural(nbitnecessary(SequenceLength)-1) downto 0);
signal yout_int : STD_LOGIC;
signal yout_comb : STD_LOGIC;
begin
u0: alt_dspbuilder_sAltrBitPropagate generic map(QTB=>DSPBuilderQTB, QTB_PRODUCT => DSPBuilderProduct, QTB_VERSION => DSPBuilderVersion)
port map (d => yout_int, r => yout);
fixed_constant:if SequenceLength=1 generate
yout_int <=SequenceValue(0);
end generate fixed_constant;
resetable_sequence:if SequenceLength>1 generate
process(clock, aclr)
begin
if aclr='1' then
yout_int <= '0';
counter <= (OTHERS => '0');
elsif clock'event and clock='1' then
if sclr='1' then
yout_int <= '0';
counter <= (OTHERS => '0');
elsif ena='1' then
if counter < int2ustd(SequenceLength-1 ,nbitnecessary(SequenceLength)+1) then
counter <= counter + '1';
else
counter <= (OTHERS => '0');
end if;
yout_int <= yout_comb;
end if;
end if;
end process;
gen:for i in 0 to SequenceLength-1 generate
yout_comb <= SequenceValue(i) when (counter=int2ustd(i,nbitnecessary(SequenceLength)+1)) else 'Z';
end generate;
end generate resetable_sequence;
end seq_SYNTH;
|
mit
|
Given-Jiang/Add_Frame
|
tb_Add_Frame/hdl/alt_dspbuilder_constant_GNWFCSDEFM.vhd
|
4
|
576
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNWFCSDEFM is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000000000000001";
width : natural := 16);
port(
output : out std_logic_vector(15 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNWFCSDEFM is
Begin
-- Constant
output <= "0000000000000001";
end architecture;
|
mit
|
Given-Jiang/Add_Frame
|
Add_Frame_dspbuilder/hdl/alt_dspbuilder_constant_GNWFCSDEFM.vhd
|
4
|
576
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNWFCSDEFM is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000000000000001";
width : natural := 16);
port(
output : out std_logic_vector(15 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNWFCSDEFM is
Begin
-- Constant
output <= "0000000000000001";
end architecture;
|
mit
|
lsangild/DSD
|
Exercise5/GuessGame/testerGuessGame.vhd
|
1
|
645
|
-----Libraries-----
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-----Entity-----
entity testerGuessGame is
port( SW : in std_logic_vector(7 downto 0);
HEX0, HEX1, HEX2, HEX3 : out std_logic_vector(6 downto 0);
KEY : in std_logic_vector(2 downto 0)
);
end testerGuessGame;
-----Architecture-----
architecture TEST of testerGuessGame is
constant turnOff : std_logic_vector(6 downto 0) := "1111111";
begin
HEX2 <= turnOff;
HEX3 <= turnOff;
B2S : entity work.GuessGame port map ( inputs => SW, set => KEY(0),
show => KEY(1), try => KEY(2),
hex1 => HEX0, hex10 => HEX1);
end TEST;
|
mit
|
Given-Jiang/Add_Frame
|
tb_Add_Frame/db/alt_dspbuilder_testbench_salt_GNDBMPYDND.vhd
|
20
|
1717
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GNDBMPYDND is
generic ( XFILE : string := "default");
port(
clock : in std_logic;
aclr : in std_logic;
output : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_testbench_salt_GNDBMPYDND is
function to_std_logic (B: character) return std_logic is
begin
case B is
when '0' => return '0';
when '1' => return '1';
when OTHERS => return 'X';
end case;
end;
function to_std_logic_vector (B: string) return
std_logic_vector is
variable res: std_logic_vector (B'range);
begin
for i in B'range loop
case B(i) is
when '0' => res(i) := '0';
when '1' => res(i) := '1';
when OTHERS => res(i) := 'X';
end case;
end loop;
return res;
end;
procedure skip_type_header(file f:text) is
use STD.textio.all;
variable in_line : line;
begin
readline(f, in_line);
end procedure skip_type_header ;
file InputFile : text open read_mode is XFILE;
Begin
-- salt generator
skip_type_header(InputFile);
-- Reading Simulink Input
Input_pInput:process(clock, aclr)
variable s : string(1 to 1) ;
variable ptr : line ;
begin
if (aclr = '1') then
output <= '0';
elsif (not endfile(InputFile)) then
if clock'event and clock='0' then
readline(Inputfile, ptr);
read(ptr, s);
output <= to_std_logic(s(1));
end if ;
end if ;
end process ;
end architecture;
|
mit
|
Given-Jiang/Add_Frame
|
tb_Add_Frame/hdl/alt_dspbuilder_testbench_salt_GNDBMPYDND.vhd
|
20
|
1717
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GNDBMPYDND is
generic ( XFILE : string := "default");
port(
clock : in std_logic;
aclr : in std_logic;
output : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_testbench_salt_GNDBMPYDND is
function to_std_logic (B: character) return std_logic is
begin
case B is
when '0' => return '0';
when '1' => return '1';
when OTHERS => return 'X';
end case;
end;
function to_std_logic_vector (B: string) return
std_logic_vector is
variable res: std_logic_vector (B'range);
begin
for i in B'range loop
case B(i) is
when '0' => res(i) := '0';
when '1' => res(i) := '1';
when OTHERS => res(i) := 'X';
end case;
end loop;
return res;
end;
procedure skip_type_header(file f:text) is
use STD.textio.all;
variable in_line : line;
begin
readline(f, in_line);
end procedure skip_type_header ;
file InputFile : text open read_mode is XFILE;
Begin
-- salt generator
skip_type_header(InputFile);
-- Reading Simulink Input
Input_pInput:process(clock, aclr)
variable s : string(1 to 1) ;
variable ptr : line ;
begin
if (aclr = '1') then
output <= '0';
elsif (not endfile(InputFile)) then
if clock'event and clock='0' then
readline(Inputfile, ptr);
read(ptr, s);
output <= to_std_logic(s(1));
end if ;
end if ;
end process ;
end architecture;
|
mit
|
Given-Jiang/Add_Frame
|
Add_Frame_dspbuilder/db/alt_dspbuilder_sImpulseAltr.vhd
|
8
|
2714
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sImpulseAltr is
generic (
Impulsedelay : positive ;
Impulsewidth : positive
);
port (
clock : in std_logic;
ena : in std_logic :='1';
sclr : in std_logic :='0';
aclr : in std_logic :='0';
user_aclr : in std_logic :='0';
q : out std_logic
);
end alt_dspbuilder_sImpulseAltr ;
architecture syn of alt_dspbuilder_sImpulseAltr is
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
g1:if Impulsewidth=1 generate
gr:if Impulsedelay=1 generate
u0: alt_dspbuilder_sImpulse11Altr port map (clock=> clock, ena => ena ,aclr => aclr_i, sclr => sclr, q =>q );
end generate gr;
grr:if Impulsedelay>1 generate
u0: alt_dspbuilder_sImpulsen1Altr generic map (Impulsedelay=>Impulsedelay)
port map (clock=> clock, ena => ena ,aclr => aclr_i, sclr => sclr, q =>q );
end generate grr;
end generate g1;
gn:if Impulsewidth>1 generate
gr:if Impulsedelay=1 generate
u0: alt_dspbuilder_sImpulse1nAltr generic map (Impulsewidth=>Impulsewidth)
port map (clock=> clock, ena => ena ,aclr => aclr_i, sclr => sclr, q =>q );
end generate gr;
grr:if Impulsedelay>1 generate
u0: alt_dspbuilder_sImpulsennAltr generic map (Impulsedelay=>Impulsedelay, Impulsewidth=>Impulsewidth)
port map (clock=> clock, ena => ena ,aclr => aclr_i, sclr => sclr, q =>q );
end generate grr;
end generate gn;
end syn;
|
mit
|
Given-Jiang/Add_Frame
|
Add_Frame_dspbuilder/db/alt_dspbuilder_cast_GNNZHXLS76.vhd
|
8
|
879
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNNZHXLS76 is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(15 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNNZHXLS76 is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 32 + 1 ,
width_inr=> 0,
width_outl=> 16,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(31 downto 0) => input,
xin(32) => '0', yout => output
);
end architecture;
|
mit
|
Given-Jiang/Add_Frame
|
tb_Add_Frame/db/alt_dspbuilder_cast_GNNZHXLS76.vhd
|
8
|
879
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNNZHXLS76 is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(31 downto 0);
output : out std_logic_vector(15 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNNZHXLS76 is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 32 + 1 ,
width_inr=> 0,
width_outl=> 16,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(31 downto 0) => input,
xin(32) => '0', yout => output
);
end architecture;
|
mit
|
Given-Jiang/Add_Frame
|
tb_Add_Frame/hdl/alt_dspbuilder_if_statement_GNUCFELPE2.vhd
|
4
|
1405
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_if_statement_GNUCFELPE2 is
generic ( use_else_output : natural := 0;
bwr : natural := 0;
use_else_input : natural := 0;
signed : natural := 0;
HDLTYPE : string := "STD_LOGIC_VECTOR";
if_expression : string := "(a=b)";
number_inputs : integer := 2;
width : natural := 16);
port(
true : out std_logic;
a : in std_logic_vector(15 downto 0);
b : in std_logic_vector(15 downto 0));
end entity;
architecture rtl of alt_dspbuilder_if_statement_GNUCFELPE2 is
signal result : std_logic;
constant zero : STD_LOGIC_VECTOR(15 DOWNTO 0) := (others=>'0');
constant one : STD_LOGIC_VECTOR(15 DOWNTO 0) := (0 => '1', others => '0');
function myFunc ( Value: boolean )
return std_logic is
variable func_result : std_logic;
begin
if (Value) then
func_result := '1';
else
func_result := '0';
end if;
return func_result;
end;
function myFunc ( Value: std_logic )
return std_logic is
begin
return Value;
end;
Begin
-- DSP Builder Block - Simulink Block "IfStatement"
result <= myFunc((a=b)) ;
true <= result;
end architecture;
|
mit
|
Given-Jiang/Add_Frame
|
tb_Add_Frame/altera_lnsim/generic_m10k/_primary.vhd
|
5
|
9371
|
library verilog;
use verilog.vl_types.all;
entity generic_m10k is
generic(
operation_mode : string := "single_port";
mixed_port_feed_through_mode: string := "dont_care";
ram_block_type : string := "auto";
logical_ram_name: string := "ram_name";
init_file : string := "init_file.hex";
init_file_layout: string := "none";
ecc_pipeline_stage_enabled: string := "false";
enable_ecc : string := "false";
width_eccstatus : integer := 2;
data_interleave_width_in_bits: integer := 1;
data_interleave_offset_in_bits: integer := 1;
port_a_logical_ram_depth: integer := 0;
port_a_logical_ram_width: integer := 0;
port_a_first_address: integer := 0;
port_a_last_address: integer := 0;
port_a_first_bit_number: integer := 0;
port_a_data_out_clear: string := "none";
port_a_data_out_clock: string := "none";
port_a_data_width: integer := 1;
port_a_address_width: integer := 1;
port_a_byte_enable_mask_width: integer := 1;
port_b_logical_ram_depth: integer := 0;
port_b_logical_ram_width: integer := 0;
port_b_first_address: integer := 0;
port_b_last_address: integer := 0;
port_b_first_bit_number: integer := 0;
port_b_address_clear: string := "none";
port_b_data_out_clear: string := "none";
port_b_data_in_clock: string := "clock1";
port_b_address_clock: string := "clock1";
port_b_write_enable_clock: string := "clock1";
port_b_read_enable_clock: string := "clock1";
port_b_byte_enable_clock: string := "clock1";
port_b_data_out_clock: string := "none";
port_b_data_width: integer := 1;
port_b_address_width: integer := 1;
port_b_byte_enable_mask_width: integer := 1;
port_a_read_during_write_mode: string := "new_data_no_nbe_read";
port_b_read_during_write_mode: string := "new_data_no_nbe_read";
power_up_uninitialized: string := "false";
lpm_type : string := "arriav_ram_block";
lpm_hint : string := "true";
connectivity_checking: string := "off";
mem_init0 : string := "";
mem_init1 : string := "";
mem_init2 : string := "";
mem_init3 : string := "";
mem_init4 : string := "";
port_a_byte_size: integer := 0;
port_b_byte_size: integer := 0;
clk0_input_clock_enable: string := "none";
clk0_core_clock_enable: string := "none";
clk0_output_clock_enable: string := "none";
clk1_input_clock_enable: string := "none";
clk1_core_clock_enable: string := "none";
clk1_output_clock_enable: string := "none";
bist_ena : string := "false";
port_a_address_clear: string := "none";
port_a_data_in_clock: string := "clock0";
port_a_address_clock: string := "clock0";
port_a_write_enable_clock: string := "clock0";
port_a_byte_enable_clock: string := "clock0";
port_a_read_enable_clock: string := "clock0"
);
port(
portadatain : in vl_logic_vector;
portaaddr : in vl_logic_vector;
portawe : in vl_logic;
portare : in vl_logic;
portbdatain : in vl_logic_vector;
portbaddr : in vl_logic_vector;
portbwe : in vl_logic;
portbre : in vl_logic;
clk0 : in vl_logic;
clk1 : in vl_logic;
ena0 : in vl_logic;
ena1 : in vl_logic;
ena2 : in vl_logic;
ena3 : in vl_logic;
clr0 : in vl_logic;
clr1 : in vl_logic;
nerror : in vl_logic;
portabyteenamasks: in vl_logic_vector;
portbbyteenamasks: in vl_logic_vector;
portaaddrstall : in vl_logic;
portbaddrstall : in vl_logic;
devclrn : in vl_logic;
devpor : in vl_logic;
eccstatus : out vl_logic_vector;
portadataout : out vl_logic_vector;
portbdataout : out vl_logic_vector;
dftout : out vl_logic_vector(8 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of operation_mode : constant is 1;
attribute mti_svvh_generic_type of mixed_port_feed_through_mode : constant is 1;
attribute mti_svvh_generic_type of ram_block_type : constant is 1;
attribute mti_svvh_generic_type of logical_ram_name : constant is 1;
attribute mti_svvh_generic_type of init_file : constant is 1;
attribute mti_svvh_generic_type of init_file_layout : constant is 1;
attribute mti_svvh_generic_type of ecc_pipeline_stage_enabled : constant is 1;
attribute mti_svvh_generic_type of enable_ecc : constant is 1;
attribute mti_svvh_generic_type of width_eccstatus : constant is 1;
attribute mti_svvh_generic_type of data_interleave_width_in_bits : constant is 1;
attribute mti_svvh_generic_type of data_interleave_offset_in_bits : constant is 1;
attribute mti_svvh_generic_type of port_a_logical_ram_depth : constant is 1;
attribute mti_svvh_generic_type of port_a_logical_ram_width : constant is 1;
attribute mti_svvh_generic_type of port_a_first_address : constant is 1;
attribute mti_svvh_generic_type of port_a_last_address : constant is 1;
attribute mti_svvh_generic_type of port_a_first_bit_number : constant is 1;
attribute mti_svvh_generic_type of port_a_data_out_clear : constant is 1;
attribute mti_svvh_generic_type of port_a_data_out_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_data_width : constant is 1;
attribute mti_svvh_generic_type of port_a_address_width : constant is 1;
attribute mti_svvh_generic_type of port_a_byte_enable_mask_width : constant is 1;
attribute mti_svvh_generic_type of port_b_logical_ram_depth : constant is 1;
attribute mti_svvh_generic_type of port_b_logical_ram_width : constant is 1;
attribute mti_svvh_generic_type of port_b_first_address : constant is 1;
attribute mti_svvh_generic_type of port_b_last_address : constant is 1;
attribute mti_svvh_generic_type of port_b_first_bit_number : constant is 1;
attribute mti_svvh_generic_type of port_b_address_clear : constant is 1;
attribute mti_svvh_generic_type of port_b_data_out_clear : constant is 1;
attribute mti_svvh_generic_type of port_b_data_in_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_address_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_write_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_read_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_byte_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_data_out_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_data_width : constant is 1;
attribute mti_svvh_generic_type of port_b_address_width : constant is 1;
attribute mti_svvh_generic_type of port_b_byte_enable_mask_width : constant is 1;
attribute mti_svvh_generic_type of port_a_read_during_write_mode : constant is 1;
attribute mti_svvh_generic_type of port_b_read_during_write_mode : constant is 1;
attribute mti_svvh_generic_type of power_up_uninitialized : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of connectivity_checking : constant is 1;
attribute mti_svvh_generic_type of mem_init0 : constant is 1;
attribute mti_svvh_generic_type of mem_init1 : constant is 1;
attribute mti_svvh_generic_type of mem_init2 : constant is 1;
attribute mti_svvh_generic_type of mem_init3 : constant is 1;
attribute mti_svvh_generic_type of mem_init4 : constant is 1;
attribute mti_svvh_generic_type of port_a_byte_size : constant is 1;
attribute mti_svvh_generic_type of port_b_byte_size : constant is 1;
attribute mti_svvh_generic_type of clk0_input_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk0_core_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk0_output_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk1_input_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk1_core_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk1_output_clock_enable : constant is 1;
attribute mti_svvh_generic_type of bist_ena : constant is 1;
attribute mti_svvh_generic_type of port_a_address_clear : constant is 1;
attribute mti_svvh_generic_type of port_a_data_in_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_address_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_write_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_byte_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_read_enable_clock : constant is 1;
end generic_m10k;
|
mit
|
Given-Jiang/Add_Frame
|
Add_Frame_dspbuilder/db/alt_dspbuilder_sAltrBitPropagate.vhd
|
20
|
1572
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sAltrBitPropagate is
generic (
QTB : string :="on";
QTB_PRODUCT : string :="DSP Builder";
QTB_VERSION : string :="6.0"
);
port (
d : in std_logic;
r : out std_logic
);
end alt_dspbuilder_sAltrBitPropagate ;
architecture sAltrBitPropagate_Synth of alt_dspbuilder_sAltrBitPropagate is
begin
r<=d;
end sAltrBitPropagate_Synth;
|
mit
|
UCR-CS179-SUMMER2014/NES_FPGA
|
source/NES_FPGA/nios_system/synthesis/submodules/Altera_UP_SD_Card_Clock.vhd
|
2
|
2224
|
-------------------------------------------------------------------------------------
-- This module is a clock generator for the SD card interface. It takes a 50 MHz
-- clock as input and produces a clock signal that depends on the mode in which the
-- SD card interface is in. For a card identification mode a clock with a frequency of
-- 390.625 kHz is generated. For the data transfer mode, a clock with a frequency of
-- 12.5MHz is generated.
--
-- In addition, the generator produces a clock_mode value that identifies the frequency
-- of the o_SD_clock that is currently being generated.
--
-- NOTES/REVISIONS:
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Altera_UP_SD_Card_Clock is
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
i_enable : in std_logic;
i_mode : in std_logic; -- 0 for card identification mode, 1 for data transfer mode.
o_SD_clock : out std_logic;
o_clock_mode : out std_logic;
o_trigger_receive : out std_logic;
o_trigger_send : out std_logic
);
end entity;
architecture rtl of Altera_UP_SD_Card_Clock is
-- Local wires
-- REGISTERED
signal counter : std_logic_vector(6 downto 0);
signal local_mode : std_logic;
-- UNREGISTERED
begin
process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
counter <= (OTHERS => '0');
local_mode <= '0';
else
if (rising_edge(i_clock)) then
if (i_enable = '1') then
counter <= counter + '1';
end if;
-- Change the clock pulse only when at the positive edge of the clock
if (counter = "1000000") then
local_mode <= i_mode;
end if;
end if;
end if;
end process;
o_clock_mode <= local_mode;
o_SD_clock <= counter(6) when (local_mode = '0') else counter(1);
o_trigger_receive <= '1' when ((local_mode = '0') and (counter = "0111111")) else
((not counter(1)) and (counter(0))) when (local_mode = '1') else '0';
o_trigger_send <= '1' when ((local_mode = '0') and (counter = "0011111")) else
((counter(1)) and (counter(0))) when (local_mode = '1') else '0';
end rtl;
|
mit
|
monotone-RK/FACE
|
IEICE-Trans/data_compression/4-way_2-tree/src/ip_pcie/PCIeGen2x8If128_stub.vhdl
|
1
|
7253
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
-- Date : Sun Aug 28 01:02:31 2016
-- Host : fpgaserv running 64-bit Ubuntu 14.04.4 LTS
-- Command : write_vhdl -force -mode synth_stub
-- /home/kobayashi/PCIe_test/branches/IEICE/data_compression/4-way_2-tree/src/ip_pcie/PCIeGen2x8If128_stub.vhdl
-- Design : PCIeGen2x8If128
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7vx485tffg1761-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PCIeGen2x8If128 is
Port (
pci_exp_txp : out STD_LOGIC_VECTOR ( 7 downto 0 );
pci_exp_txn : out STD_LOGIC_VECTOR ( 7 downto 0 );
pci_exp_rxp : in STD_LOGIC_VECTOR ( 7 downto 0 );
pci_exp_rxn : in STD_LOGIC_VECTOR ( 7 downto 0 );
user_clk_out : out STD_LOGIC;
user_reset_out : out STD_LOGIC;
user_lnk_up : out STD_LOGIC;
user_app_rdy : out STD_LOGIC;
tx_buf_av : out STD_LOGIC_VECTOR ( 5 downto 0 );
tx_cfg_req : out STD_LOGIC;
tx_err_drop : out STD_LOGIC;
s_axis_tx_tready : out STD_LOGIC;
s_axis_tx_tdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
s_axis_tx_tkeep : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axis_tx_tlast : in STD_LOGIC;
s_axis_tx_tvalid : in STD_LOGIC;
s_axis_tx_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
tx_cfg_gnt : in STD_LOGIC;
m_axis_rx_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axis_rx_tkeep : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axis_rx_tlast : out STD_LOGIC;
m_axis_rx_tvalid : out STD_LOGIC;
m_axis_rx_tready : in STD_LOGIC;
m_axis_rx_tuser : out STD_LOGIC_VECTOR ( 21 downto 0 );
rx_np_ok : in STD_LOGIC;
rx_np_req : in STD_LOGIC;
fc_cpld : out STD_LOGIC_VECTOR ( 11 downto 0 );
fc_cplh : out STD_LOGIC_VECTOR ( 7 downto 0 );
fc_npd : out STD_LOGIC_VECTOR ( 11 downto 0 );
fc_nph : out STD_LOGIC_VECTOR ( 7 downto 0 );
fc_pd : out STD_LOGIC_VECTOR ( 11 downto 0 );
fc_ph : out STD_LOGIC_VECTOR ( 7 downto 0 );
fc_sel : in STD_LOGIC_VECTOR ( 2 downto 0 );
cfg_status : out STD_LOGIC_VECTOR ( 15 downto 0 );
cfg_command : out STD_LOGIC_VECTOR ( 15 downto 0 );
cfg_dstatus : out STD_LOGIC_VECTOR ( 15 downto 0 );
cfg_dcommand : out STD_LOGIC_VECTOR ( 15 downto 0 );
cfg_lstatus : out STD_LOGIC_VECTOR ( 15 downto 0 );
cfg_lcommand : out STD_LOGIC_VECTOR ( 15 downto 0 );
cfg_dcommand2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
cfg_pcie_link_state : out STD_LOGIC_VECTOR ( 2 downto 0 );
cfg_pmcsr_pme_en : out STD_LOGIC;
cfg_pmcsr_powerstate : out STD_LOGIC_VECTOR ( 1 downto 0 );
cfg_pmcsr_pme_status : out STD_LOGIC;
cfg_received_func_lvl_rst : out STD_LOGIC;
cfg_trn_pending : in STD_LOGIC;
cfg_pm_halt_aspm_l0s : in STD_LOGIC;
cfg_pm_halt_aspm_l1 : in STD_LOGIC;
cfg_pm_force_state_en : in STD_LOGIC;
cfg_pm_force_state : in STD_LOGIC_VECTOR ( 1 downto 0 );
cfg_dsn : in STD_LOGIC_VECTOR ( 63 downto 0 );
cfg_interrupt : in STD_LOGIC;
cfg_interrupt_rdy : out STD_LOGIC;
cfg_interrupt_assert : in STD_LOGIC;
cfg_interrupt_di : in STD_LOGIC_VECTOR ( 7 downto 0 );
cfg_interrupt_do : out STD_LOGIC_VECTOR ( 7 downto 0 );
cfg_interrupt_mmenable : out STD_LOGIC_VECTOR ( 2 downto 0 );
cfg_interrupt_msienable : out STD_LOGIC;
cfg_interrupt_msixenable : out STD_LOGIC;
cfg_interrupt_msixfm : out STD_LOGIC;
cfg_interrupt_stat : in STD_LOGIC;
cfg_pciecap_interrupt_msgnum : in STD_LOGIC_VECTOR ( 4 downto 0 );
cfg_to_turnoff : out STD_LOGIC;
cfg_turnoff_ok : in STD_LOGIC;
cfg_bus_number : out STD_LOGIC_VECTOR ( 7 downto 0 );
cfg_device_number : out STD_LOGIC_VECTOR ( 4 downto 0 );
cfg_function_number : out STD_LOGIC_VECTOR ( 2 downto 0 );
cfg_pm_wake : in STD_LOGIC;
cfg_pm_send_pme_to : in STD_LOGIC;
cfg_ds_bus_number : in STD_LOGIC_VECTOR ( 7 downto 0 );
cfg_ds_device_number : in STD_LOGIC_VECTOR ( 4 downto 0 );
cfg_ds_function_number : in STD_LOGIC_VECTOR ( 2 downto 0 );
cfg_bridge_serr_en : out STD_LOGIC;
cfg_slot_control_electromech_il_ctl_pulse : out STD_LOGIC;
cfg_root_control_syserr_corr_err_en : out STD_LOGIC;
cfg_root_control_syserr_non_fatal_err_en : out STD_LOGIC;
cfg_root_control_syserr_fatal_err_en : out STD_LOGIC;
cfg_root_control_pme_int_en : out STD_LOGIC;
cfg_aer_rooterr_corr_err_reporting_en : out STD_LOGIC;
cfg_aer_rooterr_non_fatal_err_reporting_en : out STD_LOGIC;
cfg_aer_rooterr_fatal_err_reporting_en : out STD_LOGIC;
cfg_aer_rooterr_corr_err_received : out STD_LOGIC;
cfg_aer_rooterr_non_fatal_err_received : out STD_LOGIC;
cfg_aer_rooterr_fatal_err_received : out STD_LOGIC;
cfg_vc_tcvc_map : out STD_LOGIC_VECTOR ( 6 downto 0 );
sys_clk : in STD_LOGIC;
sys_rst_n : in STD_LOGIC
);
end PCIeGen2x8If128;
architecture stub of PCIeGen2x8If128 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "pci_exp_txp[7:0],pci_exp_txn[7:0],pci_exp_rxp[7:0],pci_exp_rxn[7:0],user_clk_out,user_reset_out,user_lnk_up,user_app_rdy,tx_buf_av[5:0],tx_cfg_req,tx_err_drop,s_axis_tx_tready,s_axis_tx_tdata[127:0],s_axis_tx_tkeep[15:0],s_axis_tx_tlast,s_axis_tx_tvalid,s_axis_tx_tuser[3:0],tx_cfg_gnt,m_axis_rx_tdata[127:0],m_axis_rx_tkeep[15:0],m_axis_rx_tlast,m_axis_rx_tvalid,m_axis_rx_tready,m_axis_rx_tuser[21:0],rx_np_ok,rx_np_req,fc_cpld[11:0],fc_cplh[7:0],fc_npd[11:0],fc_nph[7:0],fc_pd[11:0],fc_ph[7:0],fc_sel[2:0],cfg_status[15:0],cfg_command[15:0],cfg_dstatus[15:0],cfg_dcommand[15:0],cfg_lstatus[15:0],cfg_lcommand[15:0],cfg_dcommand2[15:0],cfg_pcie_link_state[2:0],cfg_pmcsr_pme_en,cfg_pmcsr_powerstate[1:0],cfg_pmcsr_pme_status,cfg_received_func_lvl_rst,cfg_trn_pending,cfg_pm_halt_aspm_l0s,cfg_pm_halt_aspm_l1,cfg_pm_force_state_en,cfg_pm_force_state[1:0],cfg_dsn[63:0],cfg_interrupt,cfg_interrupt_rdy,cfg_interrupt_assert,cfg_interrupt_di[7:0],cfg_interrupt_do[7:0],cfg_interrupt_mmenable[2:0],cfg_interrupt_msienable,cfg_interrupt_msixenable,cfg_interrupt_msixfm,cfg_interrupt_stat,cfg_pciecap_interrupt_msgnum[4:0],cfg_to_turnoff,cfg_turnoff_ok,cfg_bus_number[7:0],cfg_device_number[4:0],cfg_function_number[2:0],cfg_pm_wake,cfg_pm_send_pme_to,cfg_ds_bus_number[7:0],cfg_ds_device_number[4:0],cfg_ds_function_number[2:0],cfg_bridge_serr_en,cfg_slot_control_electromech_il_ctl_pulse,cfg_root_control_syserr_corr_err_en,cfg_root_control_syserr_non_fatal_err_en,cfg_root_control_syserr_fatal_err_en,cfg_root_control_pme_int_en,cfg_aer_rooterr_corr_err_reporting_en,cfg_aer_rooterr_non_fatal_err_reporting_en,cfg_aer_rooterr_fatal_err_reporting_en,cfg_aer_rooterr_corr_err_received,cfg_aer_rooterr_non_fatal_err_received,cfg_aer_rooterr_fatal_err_received,cfg_vc_tcvc_map[6:0],sys_clk,sys_rst_n";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "PCIeGen2x8If128_pcie2_top,Vivado 2015.4";
begin
end;
|
mit
|
monotone-RK/FACE
|
IEICE-Trans/4-way/src/ip_pcie/PCIeGen2x8If128_stub.vhdl
|
1
|
7229
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
-- Date : Thu Aug 25 17:35:26 2016
-- Host : fpgaserv running 64-bit Ubuntu 14.04.4 LTS
-- Command : write_vhdl -force -mode synth_stub
-- /home/kobayashi/PCIe_test/branches/IEICE/4-way/src/ip_pcie/PCIeGen2x8If128_stub.vhdl
-- Design : PCIeGen2x8If128
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7vx485tffg1761-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PCIeGen2x8If128 is
Port (
pci_exp_txp : out STD_LOGIC_VECTOR ( 7 downto 0 );
pci_exp_txn : out STD_LOGIC_VECTOR ( 7 downto 0 );
pci_exp_rxp : in STD_LOGIC_VECTOR ( 7 downto 0 );
pci_exp_rxn : in STD_LOGIC_VECTOR ( 7 downto 0 );
user_clk_out : out STD_LOGIC;
user_reset_out : out STD_LOGIC;
user_lnk_up : out STD_LOGIC;
user_app_rdy : out STD_LOGIC;
tx_buf_av : out STD_LOGIC_VECTOR ( 5 downto 0 );
tx_cfg_req : out STD_LOGIC;
tx_err_drop : out STD_LOGIC;
s_axis_tx_tready : out STD_LOGIC;
s_axis_tx_tdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
s_axis_tx_tkeep : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axis_tx_tlast : in STD_LOGIC;
s_axis_tx_tvalid : in STD_LOGIC;
s_axis_tx_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
tx_cfg_gnt : in STD_LOGIC;
m_axis_rx_tdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axis_rx_tkeep : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axis_rx_tlast : out STD_LOGIC;
m_axis_rx_tvalid : out STD_LOGIC;
m_axis_rx_tready : in STD_LOGIC;
m_axis_rx_tuser : out STD_LOGIC_VECTOR ( 21 downto 0 );
rx_np_ok : in STD_LOGIC;
rx_np_req : in STD_LOGIC;
fc_cpld : out STD_LOGIC_VECTOR ( 11 downto 0 );
fc_cplh : out STD_LOGIC_VECTOR ( 7 downto 0 );
fc_npd : out STD_LOGIC_VECTOR ( 11 downto 0 );
fc_nph : out STD_LOGIC_VECTOR ( 7 downto 0 );
fc_pd : out STD_LOGIC_VECTOR ( 11 downto 0 );
fc_ph : out STD_LOGIC_VECTOR ( 7 downto 0 );
fc_sel : in STD_LOGIC_VECTOR ( 2 downto 0 );
cfg_status : out STD_LOGIC_VECTOR ( 15 downto 0 );
cfg_command : out STD_LOGIC_VECTOR ( 15 downto 0 );
cfg_dstatus : out STD_LOGIC_VECTOR ( 15 downto 0 );
cfg_dcommand : out STD_LOGIC_VECTOR ( 15 downto 0 );
cfg_lstatus : out STD_LOGIC_VECTOR ( 15 downto 0 );
cfg_lcommand : out STD_LOGIC_VECTOR ( 15 downto 0 );
cfg_dcommand2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
cfg_pcie_link_state : out STD_LOGIC_VECTOR ( 2 downto 0 );
cfg_pmcsr_pme_en : out STD_LOGIC;
cfg_pmcsr_powerstate : out STD_LOGIC_VECTOR ( 1 downto 0 );
cfg_pmcsr_pme_status : out STD_LOGIC;
cfg_received_func_lvl_rst : out STD_LOGIC;
cfg_trn_pending : in STD_LOGIC;
cfg_pm_halt_aspm_l0s : in STD_LOGIC;
cfg_pm_halt_aspm_l1 : in STD_LOGIC;
cfg_pm_force_state_en : in STD_LOGIC;
cfg_pm_force_state : in STD_LOGIC_VECTOR ( 1 downto 0 );
cfg_dsn : in STD_LOGIC_VECTOR ( 63 downto 0 );
cfg_interrupt : in STD_LOGIC;
cfg_interrupt_rdy : out STD_LOGIC;
cfg_interrupt_assert : in STD_LOGIC;
cfg_interrupt_di : in STD_LOGIC_VECTOR ( 7 downto 0 );
cfg_interrupt_do : out STD_LOGIC_VECTOR ( 7 downto 0 );
cfg_interrupt_mmenable : out STD_LOGIC_VECTOR ( 2 downto 0 );
cfg_interrupt_msienable : out STD_LOGIC;
cfg_interrupt_msixenable : out STD_LOGIC;
cfg_interrupt_msixfm : out STD_LOGIC;
cfg_interrupt_stat : in STD_LOGIC;
cfg_pciecap_interrupt_msgnum : in STD_LOGIC_VECTOR ( 4 downto 0 );
cfg_to_turnoff : out STD_LOGIC;
cfg_turnoff_ok : in STD_LOGIC;
cfg_bus_number : out STD_LOGIC_VECTOR ( 7 downto 0 );
cfg_device_number : out STD_LOGIC_VECTOR ( 4 downto 0 );
cfg_function_number : out STD_LOGIC_VECTOR ( 2 downto 0 );
cfg_pm_wake : in STD_LOGIC;
cfg_pm_send_pme_to : in STD_LOGIC;
cfg_ds_bus_number : in STD_LOGIC_VECTOR ( 7 downto 0 );
cfg_ds_device_number : in STD_LOGIC_VECTOR ( 4 downto 0 );
cfg_ds_function_number : in STD_LOGIC_VECTOR ( 2 downto 0 );
cfg_bridge_serr_en : out STD_LOGIC;
cfg_slot_control_electromech_il_ctl_pulse : out STD_LOGIC;
cfg_root_control_syserr_corr_err_en : out STD_LOGIC;
cfg_root_control_syserr_non_fatal_err_en : out STD_LOGIC;
cfg_root_control_syserr_fatal_err_en : out STD_LOGIC;
cfg_root_control_pme_int_en : out STD_LOGIC;
cfg_aer_rooterr_corr_err_reporting_en : out STD_LOGIC;
cfg_aer_rooterr_non_fatal_err_reporting_en : out STD_LOGIC;
cfg_aer_rooterr_fatal_err_reporting_en : out STD_LOGIC;
cfg_aer_rooterr_corr_err_received : out STD_LOGIC;
cfg_aer_rooterr_non_fatal_err_received : out STD_LOGIC;
cfg_aer_rooterr_fatal_err_received : out STD_LOGIC;
cfg_vc_tcvc_map : out STD_LOGIC_VECTOR ( 6 downto 0 );
sys_clk : in STD_LOGIC;
sys_rst_n : in STD_LOGIC
);
end PCIeGen2x8If128;
architecture stub of PCIeGen2x8If128 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "pci_exp_txp[7:0],pci_exp_txn[7:0],pci_exp_rxp[7:0],pci_exp_rxn[7:0],user_clk_out,user_reset_out,user_lnk_up,user_app_rdy,tx_buf_av[5:0],tx_cfg_req,tx_err_drop,s_axis_tx_tready,s_axis_tx_tdata[127:0],s_axis_tx_tkeep[15:0],s_axis_tx_tlast,s_axis_tx_tvalid,s_axis_tx_tuser[3:0],tx_cfg_gnt,m_axis_rx_tdata[127:0],m_axis_rx_tkeep[15:0],m_axis_rx_tlast,m_axis_rx_tvalid,m_axis_rx_tready,m_axis_rx_tuser[21:0],rx_np_ok,rx_np_req,fc_cpld[11:0],fc_cplh[7:0],fc_npd[11:0],fc_nph[7:0],fc_pd[11:0],fc_ph[7:0],fc_sel[2:0],cfg_status[15:0],cfg_command[15:0],cfg_dstatus[15:0],cfg_dcommand[15:0],cfg_lstatus[15:0],cfg_lcommand[15:0],cfg_dcommand2[15:0],cfg_pcie_link_state[2:0],cfg_pmcsr_pme_en,cfg_pmcsr_powerstate[1:0],cfg_pmcsr_pme_status,cfg_received_func_lvl_rst,cfg_trn_pending,cfg_pm_halt_aspm_l0s,cfg_pm_halt_aspm_l1,cfg_pm_force_state_en,cfg_pm_force_state[1:0],cfg_dsn[63:0],cfg_interrupt,cfg_interrupt_rdy,cfg_interrupt_assert,cfg_interrupt_di[7:0],cfg_interrupt_do[7:0],cfg_interrupt_mmenable[2:0],cfg_interrupt_msienable,cfg_interrupt_msixenable,cfg_interrupt_msixfm,cfg_interrupt_stat,cfg_pciecap_interrupt_msgnum[4:0],cfg_to_turnoff,cfg_turnoff_ok,cfg_bus_number[7:0],cfg_device_number[4:0],cfg_function_number[2:0],cfg_pm_wake,cfg_pm_send_pme_to,cfg_ds_bus_number[7:0],cfg_ds_device_number[4:0],cfg_ds_function_number[2:0],cfg_bridge_serr_en,cfg_slot_control_electromech_il_ctl_pulse,cfg_root_control_syserr_corr_err_en,cfg_root_control_syserr_non_fatal_err_en,cfg_root_control_syserr_fatal_err_en,cfg_root_control_pme_int_en,cfg_aer_rooterr_corr_err_reporting_en,cfg_aer_rooterr_non_fatal_err_reporting_en,cfg_aer_rooterr_fatal_err_reporting_en,cfg_aer_rooterr_corr_err_received,cfg_aer_rooterr_non_fatal_err_received,cfg_aer_rooterr_fatal_err_received,cfg_vc_tcvc_map[6:0],sys_clk,sys_rst_n";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "PCIeGen2x8If128_pcie2_top,Vivado 2015.4";
begin
end;
|
mit
|
Xion345/fpga-projects
|
library/uart/uart_tx.vhd
|
1
|
3776
|
-- UART Transmitter
-- 20/07/2015
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart_tx is
port(
clk, reset: in std_logic; -- Clock and reset
baud16_tick: in std_logic; -- 16x oversampled baud tick
data_in: in std_logic_vector(7 downto 0); -- Data byte to send
tx_start: in std_logic; -- Start transmission tick
tx: out std_logic; -- UART TX (Send) pin
tx_done_tick: out std_logic
);
end uart_tx;
architecture uart_tx_arch of uart_tx is
type state_type is (idle, start, data, stop);
signal state_reg, state_next: state_type; -- State register
signal data_reg, data_next: std_logic_vector(7 downto 0); -- Data (shift) register
signal sent_reg, sent_next: unsigned(2 downto 0); -- Count sent bits
signal ticks_reg, ticks_next: unsigned(3 downto 0); -- Ticks count (oversampling)
signal tx_reg, tx_next: std_logic; -- TX pin register
begin
-- State and data registers
process(clk, reset)
begin
if reset = '1' then
state_reg <= idle;
ticks_reg <= (others => '0');
sent_reg <= (others => '0');
data_reg <= (others => '0');
tx_reg <= '1'; -- Keep TX high for idle state (it is held low to start transmission)
elsif rising_edge(clk) then
state_reg <= state_next;
data_reg <= data_next;
sent_reg <= sent_next;
ticks_reg <= ticks_next;
tx_reg <= tx_next;
end if;
end process;
-- Next state logic and data path
process(state_reg, data_reg, sent_reg, ticks_reg, tx_reg, baud16_tick, tx_start, data_in)
begin
state_next <= state_reg;
data_next <= data_reg;
sent_next <= sent_reg;
ticks_next <= ticks_reg;
tx_next <= tx_reg;
tx_done_tick <= '0';
case state_reg is
--
when idle =>
if tx_start = '1' then
state_next <= start;
ticks_next <= (others => '0');
data_next <= data_in;
end if;
--
when start =>
if baud16_tick = '1' then
if ticks_reg = 15 then -- Move to data state
state_next <= data;
ticks_next <= (others => '0');
sent_next <= (others => '0');
else
tx_next <= '0';
ticks_next <= ticks_reg + 1;
end if;
end if;
--
when data =>
if baud16_tick = '1' then
if ticks_reg = 15 then -- Move to next bit
ticks_next <= (others => '0');
data_next <= '0' & data_reg(7 downto 1);
if sent_reg = 7 then -- Last byte ?
state_next <= stop;
else
sent_next <= sent_reg + 1;
end if;
else
tx_next <= data_reg(0);
ticks_next <= ticks_reg + 1;
end if;
end if;
--
when stop =>
if baud16_tick = '1' then
if ticks_reg = 15 then
state_next <= idle;
tx_done_tick <= '1';
else
tx_next <= '1'; -- I FOUND YOU BASTARD BUG !
ticks_next <= ticks_reg + 1;
end if;
end if;
end case;
end process;
-- Output logic
tx <= tx_reg;
end uart_tx_arch;
|
mit
|
shio-phys/SPI-FLASH-Programmer
|
fpga/SPI_CommandSender.vhd
|
1
|
5139
|
--------------------------------------------------------------------------------
--! @file SPI_CommandSender.vhd
--! @brief Send command to SPI FLASH and receive data from SPI FLASH
--! @author Takehiro Shiozaki
--! @date 2014-06-24
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity SPI_CommandSender is
port(
CLK : in std_logic;
RESET : in std_logic;
START : in std_logic;
BUSY : out std_logic;
LENGTH : in std_logic_vector(12 downto 0);
WE : out std_logic;
DOUT : out std_logic_vector(7 downto 0);
WADDR : out std_logic_vector(12 downto 0);
DIN : in std_logic_vector(7 downto 0);
RADDR : out std_logic_vector(8 downto 0);
SPI_SCLK : out std_logic;
SPI_SS_N : out std_logic;
SPI_MOSI : out std_logic;
SPI_MISO : in std_logic
);
end SPI_CommandSender;
architecture RTL of SPI_CommandSender is
component SPI_IF is
port(
CLK : in std_logic;
RESET : in std_logic;
DIN : in std_logic_vector(7 downto 0);
DOUT : out std_logic_vector(7 downto 0);
START : in std_logic;
BUSY : out std_logic;
SPI_SCLK : out std_logic;
SPI_MISO : in std_logic;
SPI_MOSI : out std_logic
);
end component;
signal int_WADDR : std_logic_vector(12 downto 0);
signal WaddrCountUp : std_logic;
signal WaddrCountClear : std_logic;
signal int_RADDR : std_logic_vector(8 downto 0);
signal RaddrCountUp : std_logic;
signal RaddrCountClear : std_logic;
signal LengthReg : std_logic_vector(12 downto 0);
signal LengthRegCountDown : std_logic;
signal StartIf : std_logic;
signal BusyIf : std_logic;
signal SpiSSNPre : std_logic;
type State is (IDLE, START_IF, WAIT_BUSY, WRITE_DATA);
signal CurrentState, NextState : State;
begin
SPI_IF_0: SPI_IF
port map(
CLK => CLK,
RESET => RESET,
DIN => DIN,
DOUT => DOUT,
START => StartIf,
BUSY => BusyIf,
SPI_SCLK => SPI_SCLK,
SPI_MISO => SPI_MISO,
SPI_MOSI => SPI_MOSI
);
process(CLK)
begin
if(CLK'event and CLK = '1') then
if(WaddrCountClear = '1') then
int_WADDR <= (others => '0');
elsif(WaddrCountUp = '1') then
int_WADDR <= int_WADDR + 1;
end if;
end if;
end process;
WADDR <= int_WADDR;
process(CLK)
begin
if(CLK'event and CLK = '1') then
if(RaddrCountClear = '1') then
int_RADDR <= (others => '0');
elsif(RaddrCountUp = '1') then
int_RADDR <= int_RADDR + 1;
end if;
end if;
end process;
RADDR <= int_RADDR;
process(CLK)
begin
if(CLK'event and CLK = '1') then
if(START = '1') then
LengthReg <= LENGTH;
elsif(LengthRegCountDown = '1') then
LengthReg <= LengthReg - 1;
end if;
end if;
end process;
process(CLK)
begin
if(CLK'event and CLK = '1') then
if(RESET = '1') then
CurrentState <= IDLE;
else
CurrentState <= NextState;
end if;
end if;
end process;
process(CurrentState, START, BusyIf, LengthReg)
begin
case CurrentState is
when IDLE =>
if(START = '1') then
NextState <= START_IF;
else
NextState <= CurrentState;
end if;
when START_IF =>
NextState <= WAIT_BUSY;
when WAIT_BUSY =>
if(BusyIf = '1') then
NextState <= CurrentState;
else
NextState <= WRITE_DATA;
end if;
when WRITE_DATA =>
if(LengthReg = 0) then
NextState <= IDLE;
else
NextState <= START_IF;
end if;
end case;
end process;
WaddrCountUp <= '1' when(CurrentState = WRITE_DATA) else
'0';
WaddrCountClear <= '1' when(CurrentState = IDLE) else
'0';
RaddrCountUp <= '1' when(CurrentState = START_IF) else
'0';
RaddrCountClear <= '1' when(CurrentState = IDLE) else
'0';
LengthRegCountDown <= '1' when(CurrentState = WRITE_DATA) else
'0';
StartIf <= '1' when(CurrentState = START_IF) else
'0';
SpiSSNPre <= '1' when(CurrentState = IDLE) else
'0';
WE <= '1' when(CurrentState = WRITE_DATA) else
'0';
BUSY <= '0' when(CurrentState = IDLE) else
'1';
process(CLK)
begin
if(CLK'event and CLK = '1') then
SPI_SS_N <= SpiSSNPre;
end if;
end process;
end RTL;
|
mit
|
Given-Jiang/Gray_Processing
|
tb_Gray_Processing/db/alt_dspbuilder_cast_GN46N4UJ5S.vhd
|
20
|
844
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GN46N4UJ5S is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic;
output : out std_logic_vector(0 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GN46N4UJ5S is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 1 + 1 ,
width_inr=> 0,
width_outl=> 1,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(0) => input,
xin(1) => '0', yout => output
);
end architecture;
|
mit
|
Given-Jiang/Gray_Processing
|
Gray_Processing_dspbuilder/db/alt_dspbuilder_SBF.vhd
|
20
|
8869
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_SBF is
generic (
width_inl : natural :=10;
width_inr : natural :=10;
width_outl : natural :=8;
width_outr : natural :=8;
round : natural :=1;
satur : natural :=1;
lpm_signed : BusArithm :=BusIsSigned
);
port (
xin : in std_logic_vector(width_inl+width_inr-1 downto 0);
yout : out std_logic_vector(width_outl+width_outr-1 downto 0)
);
end alt_dspbuilder_SBF;
architecture SBF_SYNTH of alt_dspbuilder_SBF is
signal youtround : std_logic_vector(width_inl+width_outr-1 downto 0);
signal youtroundc : std_logic_vector(width_outl+width_outr-1 downto 0);
signal xinextc : std_logic_vector(width_outl+width_inr-1 downto 0) ;
signal xin_int : std_logic_vector(width_inl+width_inr-1 downto 0);
begin
u0: alt_dspbuilder_sAltrPropagate generic map(QTB=>DSPBuilderQTB, QTB_PRODUCT => DSPBuilderProduct, QTB_VERSION => DSPBuilderVersion , width=> width_inl+width_inr)
port map (d => xin, r => xin_int);
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--(width_inl>=width_outl) and (width_inr>=width_outr)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
sbf_a:if (width_inl>=width_outl) and (width_inr>=width_outr) generate
gnsnr:if (round = 0) generate
gnsat:if (satur=0) generate
gl:for i in 0 to width_outl+width_outr-1 generate
yout(i) <= xin_int(i+width_inr-width_outr);
end generate ;
end generate gnsat;
gsat:if (satur>0) generate
gl:for i in 0 to width_inl+width_outr-1 generate
youtround(i) <= xin_int(i+width_inr-width_outr);
end generate ;
us:alt_dspbuilder_ASAT
generic map ( widthin => width_inl+width_outr,
widthout => width_outl+width_outr,
lpm_signed => lpm_signed)
port map ( xin => youtround,
yout => yout);
end generate gsat;
end generate ;
rnd:if (round>0)generate
ura:alt_dspbuilder_AROUND
generic map ( widthin => width_inl+width_inr,
widthout => width_inl+width_outr)
port map ( xin => xin_int,
yout => youtround);
gns:if satur=0 generate
yout(width_outl+width_outr-1 downto 0) <= youtround(width_outl+width_outr-1 downto 0);
end generate gns;
gs:if (satur>0) generate
us:alt_dspbuilder_ASAT
generic map ( widthin => width_inl+width_outr,
widthout => width_outl+width_outr,
lpm_signed => lpm_signed)
port map ( xin => youtround,
yout => yout
);
end generate gs;
end generate rnd;
end generate sbf_a;
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
-- (width_inl>width_outl) and (width_inr<width_outr)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
sbf_b:if (width_inl>=width_outl) and (width_inr<width_outr) generate
ns:if (satur=0) generate
gc:for i in 0 to width_outr-width_inr-1 generate
yout(i) <= '0';
end generate gc;
gl:for i in width_outr-width_inr to width_outl+width_outr-1 generate
yout(i) <= xin_int(i+width_inr-width_outr);
end generate ;
end generate ns ;
gs:if (satur>0) generate
gc:for i in 0 to width_outr-width_inr-1 generate
youtround(i) <= '0';
end generate gc;
gl:for i in width_outr-width_inr to width_inl+width_outr-1 generate
youtround(i) <= xin_int(i+width_inr-width_outr);
end generate ;
us:alt_dspbuilder_ASAT
generic map ( widthin => width_inl+width_outr,
widthout => width_outl+width_outr,
lpm_signed => lpm_signed)
port map ( xin => youtround,
yout => yout);
end generate gs ;
end generate sbf_b;
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
-- (width_inl<width_outl) and (width_inr>width_outr)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
sbf_c:if (width_inl<width_outl) and (width_inr>=width_outr) generate
gnsnr:if (round = 0) generate
gl:for i in 0 to width_inl+width_outr-1 generate
yout(i) <= xin_int(i+width_inr-width_outr);
end generate ;
gc:for i in width_inl+width_outr to width_outl+width_outr-1 generate
yout(i) <= xin_int( width_inl+width_inr-1);
end generate ;
end generate ;
rnd:if (round > 0) generate
xinextc(width_inl+width_inr-1 downto 0) <= xin_int(width_inl+width_inr-1 downto 0);
gxinextc:for i in width_inl+width_inr to width_outl+width_inr-1 generate
xinextc(i) <= xin_int(width_inl+width_inr-1);
end generate gxinextc;
urb:alt_dspbuilder_AROUND
generic map ( widthin => width_outl+width_inr,
widthout => width_outl+width_outr)
port map ( xin => xinextc,
yout => youtroundc);
yout <= youtroundc;
end generate rnd ;
end generate sbf_c;
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
-- (width_inl<width_outl) and (width_inr<width_outr)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
sbf_d:if (width_inl<width_outl) and (width_inr<width_outr) generate
gl:for i in width_outr-width_inr to width_inl+width_outr-1 generate
yout(i) <= xin_int(i+width_inr-width_outr);
end generate gl;
gc:for i in 0 to width_outr-width_inr-1 generate
yout(i) <= '0';
end generate gc;
gcv:for i in width_inl+width_outr to width_outl+width_outr-1 generate
yout(i) <= xin_int( width_inl+width_inr-1);
end generate gcv;
end generate sbf_d;
end SBF_SYNTH;
|
mit
|
Given-Jiang/Gray_Processing
|
tb_Gray_Processing/reports/Gray_Processing/tb_Gray_Processing_example.vhd
|
2
|
326
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity tb_Gray_Processing_example is
end entity;
architecture rtl of tb_Gray_Processing_example is
component tb_Gray_Processing
end component;
begin
tb_Gray_Processing_instance :
component tb_Gray_Processing
port map();
end architecture rtl;
|
mit
|
Given-Jiang/Gray_Processing
|
tb_Gray_Processing/altera_lnsim/dprio_init/_primary.vhd
|
5
|
627
|
library verilog;
use verilog.vl_types.all;
entity dprio_init is
port(
clk : in vl_logic;
reset_n : in vl_logic;
dprio_address : out vl_logic_vector(5 downto 0);
dprio_byteen : out vl_logic_vector(1 downto 0);
dprio_write : out vl_logic;
dprio_writedata : out vl_logic_vector(15 downto 0);
atpgmode : out vl_logic;
mdio_dis : out vl_logic;
scanen : out vl_logic;
ser_shift_load : out vl_logic;
dprio_init_done : out vl_logic
);
end dprio_init;
|
mit
|
Given-Jiang/Gray_Processing
|
tb_Gray_Processing/hdl/alt_dspbuilder_barrelshifter_GNV5DVAGHT.vhd
|
8
|
1654
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_barrelshifter_GNV5DVAGHT is
generic ( DISTANCE_WIDTH : natural := 4;
NDIRECTION : natural := 1;
SIGNED : integer := 0;
use_dedicated_circuitry : string := "false";
PIPELINE : natural := 0;
WIDTH : natural := 18);
port(
a : in std_logic_vector((WIDTH)-1 downto 0);
aclr : in std_logic;
clock : in std_logic;
direction : in std_logic;
distance : in std_logic_vector((DISTANCE_WIDTH)-1 downto 0);
ena : in std_logic;
r : out std_logic_vector((WIDTH)-1 downto 0);
user_aclr : in std_logic);
end entity;
--- The DSPBuilder BarrelShifter
architecture rtl of alt_dspbuilder_barrelshifter_GNV5DVAGHT is
signal clear : std_logic;
signal a_ext : std_logic_vector(18 downto 0);
signal d_ext : std_logic_vector(5 - 1 downto 0);
signal r_ext : std_logic_vector(18 downto 0);
Begin
clear <= aclr or user_aclr;
a_ext(18 - 1 downto 0) <= a;
a_ext(18) <= '0';
d_ext(4 - 1 downto 0) <= distance;
d_ext(5 - 1 downto 4) <= (others => '0');
BarrelShifteri : alt_dspbuilder_BarrelShiftAltr Generic map (
widthin => WIDTH + 1 ,
pipeline => PIPELINE,
use_dedicated_circuitry => 0 ,
widthd => 5 ,
ndirection => NDIRECTION )
port map (
clock => clock,
aclr => clear,
sclr => '0',
ena => ena,
direction => '0',
xin => a_ext ,
distance => d_ext ,
yout => r_ext );
r <= r_ext(18 - 1 downto 0);
end architecture;
|
mit
|
Given-Jiang/Gray_Processing
|
Gray_Processing_dspbuilder/hdl/alt_dspbuilder_cast_GNKXX25S2S.vhd
|
12
|
877
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNKXX25S2S is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(23 downto 0);
output : out std_logic_vector(7 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GNKXX25S2S is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 24 + 1 ,
width_inr=> 0,
width_outl=> 8,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(23 downto 0) => input,
xin(24) => '0', yout => output
);
end architecture;
|
mit
|
Given-Jiang/Gray_Processing
|
Gray_Processing_dspbuilder/hdl/alt_dspbuilder_port_GNOC3SGKQJ.vhd
|
20
|
489
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNOC3SGKQJ is
port(
input : in std_logic_vector(23 downto 0);
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_port_GNOC3SGKQJ is
Begin
-- Straight Bypass block
output <= input;
end architecture;
|
mit
|
Given-Jiang/Gray_Processing
|
Gray_Processing_dspbuilder/db/alt_dspbuilder_port_GNOC3SGKQJ.vhd
|
20
|
489
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNOC3SGKQJ is
port(
input : in std_logic_vector(23 downto 0);
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_port_GNOC3SGKQJ is
Begin
-- Straight Bypass block
output <= input;
end architecture;
|
mit
|
Given-Jiang/Gray_Processing
|
tb_Gray_Processing/db/alt_dspbuilder_clock_GNF343OQUJ.vhd
|
16
|
576
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_clock_GNF343OQUJ is
port(
aclr : in std_logic;
aclr_n : in std_logic;
aclr_out : out std_logic;
clock : in std_logic;
clock_out : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_clock_GNF343OQUJ is
Begin
-- Straight Bypass Clock
clock_out <= clock;
-- reset logic
aclr_out <= not(aclr_n);
end architecture;
|
mit
|
Given-Jiang/Gray_Processing
|
tb_Gray_Processing/hdl/alt_dspbuilder_port_GN37ALZBS4.vhd
|
20
|
449
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GN37ALZBS4 is
port(
input : in std_logic;
output : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_port_GN37ALZBS4 is
Begin
-- Straight Bypass block
output <= input;
end architecture;
|
mit
|
Given-Jiang/Gray_Processing
|
Gray_Processing_dspbuilder/db/alt_dspbuilder_port_GN37ALZBS4.vhd
|
20
|
449
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GN37ALZBS4 is
port(
input : in std_logic;
output : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_port_GN37ALZBS4 is
Begin
-- Straight Bypass block
output <= input;
end architecture;
|
mit
|
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