repo_name
stringlengths 6
79
| path
stringlengths 5
236
| copies
stringclasses 54
values | size
stringlengths 1
8
| content
stringlengths 0
1.04M
⌀ | license
stringclasses 15
values |
|---|---|---|---|---|---|
arthurTemporim/SD_SS
|
pre/4/projetos/projeto1/projeto1.vhd
|
1
|
619
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity projeto1 is
port (
e : in std_logic_vector (3 downto 0):= "0100";
s: out std_logic_vector (6 downto 0)
);
end projeto1;
architecture Behavioral of projeto1 is
begin
-- Alteração feita para relatório.
s <= "1111110" when e = "0000" else
"0110000" when e = "0001" else
"1101101" when e = "0010" else
"1111001" when e = "0011" else
"0110010" when e = "0100" else
"1011010" when e = "0101" else
"1011111" when e = "0110" else
"1110000" when e = "0111" else
"1111111" when e = "1000" else
"1111011" when e = "1001";
end Behavioral;
|
mit
|
arthurTemporim/SD_SS
|
pre/3/projetos/complemento1/overflowTest.vhd
|
1
|
1551
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY overflowTest IS
END overflowTest;
ARCHITECTURE behavior OF overflowTest IS
COMPONENT overflow
PORT(
entrada1 : IN std_logic_vector(2 downto 0);
entrada2 : IN std_logic_vector(2 downto 0);
cin : IN std_logic;
saida1 : IN std_logic_vector(2 downto 0);
cout : OUT std_logic
);
END COMPONENT;
--Inputs
signal entrada1 : std_logic_vector(2 downto 0) := (others => '0');
signal entrada2 : std_logic_vector(2 downto 0) := (others => '0');
signal cin : std_logic := '0';
signal saida1 : std_logic_vector(2 downto 0) := (others => '0');
--Outputs
signal cout : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant <clock>_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: overflow PORT MAP (
entrada1 => entrada1,
entrada2 => entrada2,
cin => cin,
saida1 => saida1,
cout => cout
);
-- Clock process definitions
<clock>_process :process
begin
<clock> <= '0';
wait for <clock>_period/2;
<clock> <= '1';
wait for <clock>_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 10 ns;
saida1 <= entrada1;
wait for <clock>_period*10;
entada2 <= "111";
saida1 <= entrada2;
-- insert stimulus here
wait;
end process;
END;
|
mit
|
documment/ng-cordova
|
demo/www/lib/ace-builds/demo/kitchen-sink/docs/vhdl.vhd
|
472
|
830
|
library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
|
mit
|
arthurTemporim/SD_SS
|
pre/5/projetos/projeto1/projeto1.vhd
|
1
|
774
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity projeto1 is
port (
d : in std_logic := '0'; -- Entrada 'D'
sel : in std_logic_vector (2 downto 0) := "000"; -- Entradas "ABC"
s_m : out std_logic
);
end projeto1;
architecture Behavioral of projeto1 is
signal saida_mux : std_logic;
begin
-- Multiplexador 8 para 1.
process (sel, d)
begin
if(sel = "000") then
saida_mux <= (not d);
elsif(sel = "001") then
saida_mux <= (not d);
elsif(sel = "010") then
saida_mux <= sel(0);
elsif(sel = "011") then
saida_mux <= d;
elsif(sel = "100") then
saida_mux <= d;
elsif(sel = "101") then
saida_mux <= '0';
elsif(sel = "110") then
saida_mux <= '0';
else
saida_mux <= '0';
end if;
end process;
s_m <= saida_mux;
end Behavioral;
|
mit
|
arthurTemporim/SD_SS
|
rel/final/Projeto/Main.vhd
|
1
|
3493
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Main is
port(
modo : in std_logic := '0'; -- Gera / Valida. [sel 1]
k : in std_logic_vector (3 downto 0) := "1000"; -- Seleciona um grupo de até 16 bits. [sel 2~5]
s : in std_logic_vector (3 downto 0) := "0000"; -- Seleciona um valor. [sel 6~9]
hab_clk : in std_logic := '1'; -- Habilitador de clock. [sel 10]
but_clk : in std_logic := '0'; -- Botão pra trabalhar como clock. [sel 11]
clk : in std_logic := '0'; -- Clock do circuito.
display : out std_logic_vector (6 to 0); -- Display usado para mostrar estatisticas.
leds : out std_logic_vector (15 downto 0) -- LEDs de saída do circuito.
);
end Main;
architecture Behavioral of Main is
-- Vetor usado para deslocamento de bits.
signal vetor : std_logic_vector (15 downto 0) := "0000000000000010";
-- Guarda quantas vezes o valor de 'S' aparece.
signal estatistica : std_logic_vector (3 downto 0) := "0000";
-- Sinal para conectar estatística com display.
signal bcd : std_logic_vector (6 to 0);
-- Conta quantas vezes o valor de 'S' aparece no vetor.
signal conta_s : integer range 0 to 15;
begin
process (vetor, clk, modo)
-- Transforma o valor binário do grupo 'k' em inteiro.
variable grupo : integer range 0 to 15;
begin
-- Função GERA e VALIDA implementadas juntas.
if (modo = '0') then
-- Variável que contém tamanho do grupo.
grupo := to_integer(unsigned(k));
-- Aplica a geração aleatória.
vetor(grupo) <= vetor(0) xor vetor(1);
-- Da o shift nos bits em borda de subida.
if (clk'event and clk = '1' and hab_clk = '1') then
vetor <= std_logic_vector(unsigned(vetor) srl 1);
elsif (but_clk'event and but_clk = '1') then
vetor <= std_logic_vector(unsigned(vetor) srl 1);
end if;
-- VALIDA
-- Se os 4 últimos digitos do vetor foram iguais ao valor de 'S' então conta.
if (vetor(0) = s(0) and vetor(1) = s(1) and vetor(2) = s(2) and vetor(3) = s(3)) then
conta_s <= conta_s + 1;
end if;
end if;
end process;
-- Atribui valor inteiro da contagem para sinal.
estatistica <= std_logic_vector(to_unsigned(conta_s, 4));
-- BCD.
process (estatistica, clk)
begin
if (estatistica = "0000") then -- 0
bcd <= "1111110";
elsif (estatistica = "0001") then -- 1
bcd <= "0110000";
elsif (estatistica = "0010") then -- 2
bcd <= "1101101";
elsif (estatistica = "0011") then -- 3
bcd <= "1111001";
elsif (estatistica = "0100") then -- 4
bcd <= "0110010";
elsif (estatistica = "0101") then -- 5
bcd <= "1011010";
elsif (estatistica = "0110") then -- 6
bcd <= "1011111";
elsif (estatistica = "0111") then -- 7
bcd <= "1110000";
elsif (estatistica = "1000") then -- 8
bcd <= "1111111";
elsif (estatistica = "1001") then -- 9
bcd <= "1111011";
elsif (estatistica = "1010") then -- A
bcd <= "1110111";
elsif (estatistica = "1011") then -- B
bcd <= "0011111";
elsif (estatistica = "1100") then -- C
bcd <= "1001110";
elsif (estatistica = "1101") then -- D
bcd <= "0111101";
elsif (estatistica = "1110") then -- E
bcd <= "1001111";
else
bcd <= "1000111"; -- Caso defaul -> 'F'
end if;
end process;
-- Inverte os valores do display pois é anodo.
display <= not bcd;
-- Atribui o valor do vetor deslocado aos LEDs de saida.
leds <= vetor;
end Behavioral;
|
mit
|
antlr/grammars-v4
|
vhdl/examples/numeric_std.vhd
|
6
|
34284
|
-- --------------------------------------------------------------------
--
-- Copyright 1995 by IEEE. All rights reserved.
--
-- This source file is considered by the IEEE to be an essential part of the use
-- of the standard 1076.3 and as such may be distributed without change, except
-- as permitted by the standard. This source file may not be sold or distributed
-- for profit. This package may be modified to include additional data required
-- by tools, but must in no way change the external interfaces or simulation
-- behaviour of the description. It is permissible to add comments and/or
-- attributes to the package declarations, but not to change or delete any
-- original lines of the approved package declaration. The package body may be
-- changed only in accordance with the terms of clauses 7.1 and 7.2 of the
-- standard.
--
-- Title : Standard VHDL Synthesis Package (1076.3, NUMERIC_STD)
--
-- Library : This package shall be compiled into a library symbolically
-- : named IEEE.
--
-- Developers : IEEE DASC Synthesis Working Group, PAR 1076.3
--
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Two numeric types are defined:
-- : -- > UNSIGNED: represents UNSIGNED number in vector form
-- : -- > SIGNED: represents a SIGNED number in vector form
-- : The base element type is type STD_LOGIC.
-- : The leftmost bit is treated as the most significant bit.
-- : Signed vectors are represented in two's complement form.
-- : This package contains overloaded arithmetic operators on
-- : the SIGNED and UNSIGNED types. The package also contains
-- : useful type conversions functions.
-- :
-- : If any argument to a function is a null array, a null array is
-- : returned (exceptions, if any, are noted individually).
--
-- Limitation :
--
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the types, subtypes and declarations of
-- : NUMERIC_STD. The NUMERIC_STD package body shall be
-- : considered the formal definition of the semantics of
-- : this package. Tool developers may choose to implement
-- : the package body in the most efficient manner available
-- : to them.
--
-- --------------------------------------------------------------------
-- modification history :
-- --------------------------------------------------------------------
-- Version: 2.4
-- Date : 12 April 1995
-- -----------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package NUMERIC_STD is
constant CopyRightNotice: STRING
:= "Copyright 1995 IEEE. All rights reserved.";
--============================================================================
-- Numeric array type definitions
--============================================================================
type UNSIGNED is array (NATURAL range <>) of STD_LOGIC;
type SIGNED is array (NATURAL range <>) of STD_LOGIC;
--============================================================================
-- Arithmetic Operators:
--===========================================================================
-- Id: A.1
function "abs" (ARG: SIGNED) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0).
-- Result: Returns the absolute value of a SIGNED vector ARG.
-- Id: A.2
function "-" (ARG: SIGNED) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0).
-- Result: Returns the value of the unary minus operation on a
-- SIGNED vector ARG.
--============================================================================
-- Id: A.3
function "+" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two UNSIGNED vectors that may be of different lengths.
-- Id: A.4
function "+" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two SIGNED vectors that may be of different lengths.
-- Id: A.5
function "+" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0).
-- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.
-- Id: A.6
function "+" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0).
-- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.
-- Id: A.7
function "+" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0).
-- Result: Adds an INTEGER, L(may be positive or negative), to a SIGNED
-- vector, R.
-- Id: A.8
function "+" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0).
-- Result: Adds a SIGNED vector, L, to an INTEGER, R.
--============================================================================
-- Id: A.9
function "-" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts two UNSIGNED vectors that may be of different lengths.
-- Id: A.10
function "-" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts a SIGNED vector, R, from another SIGNED vector, L,
-- that may possibly be of different lengths.
-- Id: A.11
function "-" (L: UNSIGNED;R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0).
-- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L.
-- Id: A.12
function "-" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0).
-- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L.
-- Id: A.13
function "-" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0).
-- Result: Subtracts an INTEGER, R, from a SIGNED vector, L.
-- Id: A.14
function "-" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0).
-- Result: Subtracts a SIGNED vector, R, from an INTEGER, L.
--============================================================================
-- Id: A.15
function "*" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED((L'LENGTH+R'LENGTH-1) downto 0).
-- Result: Performs the multiplication operation on two UNSIGNED vectors
-- that may possibly be of different lengths.
-- Id: A.16
function "*" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED((L'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies two SIGNED vectors that may possibly be of
-- different lengths.
-- Id: A.17
function "*" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED((L'LENGTH+L'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, L, with a non-negative
-- INTEGER, R. R is converted to an UNSIGNED vector of
-- SIZE L'LENGTH before multiplication.
-- Id: A.18
function "*" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED((R'LENGTH+R'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, R, with a non-negative
-- INTEGER, L. L is converted to an UNSIGNED vector of
-- SIZE R'LENGTH before multiplication.
-- Id: A.19
function "*" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED((L'LENGTH+L'LENGTH-1) downto 0)
-- Result: Multiplies a SIGNED vector, L, with an INTEGER, R. R is
-- converted to a SIGNED vector of SIZE L'LENGTH before
-- multiplication.
-- Id: A.20
function "*" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED((R'LENGTH+R'LENGTH-1) downto 0)
-- Result: Multiplies a SIGNED vector, R, with an INTEGER, L. L is
-- converted to a SIGNED vector of SIZE R'LENGTH before
-- multiplication.
--============================================================================
--
-- NOTE: If second argument is zero for "/" operator, a severity level
-- of ERROR is issued.
-- Id: A.21
function "/" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R.
-- Id: A.22
function "/" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an SIGNED vector, L, by another SIGNED vector, R.
-- Id: A.23
function "/" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.24
function "/" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.25
function "/" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Divides a SIGNED vector, L, by an INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.26
function "/" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Divides an INTEGER, L, by a SIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "rem" operator, a severity level
-- of ERROR is issued.
-- Id: A.27
function "rem" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNSIGNED vectors.
-- Id: A.28
function "rem" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are SIGNED vectors.
-- Id: A.29
function "rem" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a
-- non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.30
function "rem" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a
-- non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.31
function "rem" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is SIGNED vector and R is an INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.32
function "rem" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is SIGNED vector and L is an INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "mod" operator, a severity level
-- of ERROR is issued.
-- Id: A.33
function "mod" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNSIGNED vectors.
-- Id: A.34
function "mod" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are SIGNED vectors.
-- Id: A.35
function "mod" (L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNSIGNED vector and R
-- is a non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.36
function "mod" (L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where R is an UNSIGNED vector and L
-- is a non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
-- Id: A.37
function "mod" (L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is a SIGNED vector and
-- R is an INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.38
function "mod" (L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an INTEGER and
-- R is a SIGNED vector.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
-- Comparison Operators
--============================================================================
-- Id: C.1
function ">" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.2
function ">" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.3
function ">" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.4
function ">" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a INTEGER and
-- R is a SIGNED vector.
-- Id: C.5
function ">" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.6
function ">" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a SIGNED vector and
-- R is a INTEGER.
--============================================================================
-- Id: C.7
function "<" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.8
function "<" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.9
function "<" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.10
function "<" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.11
function "<" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.12
function "<" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.13
function "<=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.14
function "<=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.15
function "<=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.16
function "<=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.17
function "<=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.18
function "<=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.19
function ">=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.20
function ">=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.21
function ">=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.22
function ">=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.23
function ">=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.24
function ">=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.25
function "=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.26
function "=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.27
function "=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.28
function "=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.29
function "=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.30
function "=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.31
function "/=" (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.32
function "/=" (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.33
function "/=" (L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.34
function "/=" (L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.35
function "/=" (L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.36
function "/=" (L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Shift and Rotate Functions
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT leftmost elements are lost.
-- Id: S.2
function SHIFT_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT rightmost elements are lost.
-- Id: S.3
function SHIFT_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on a SIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT leftmost elements are lost.
-- Id: S.4
function SHIFT_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on a SIGNED vector COUNT times.
-- The vacated positions are filled with the leftmost
-- element, ARG'LEFT. The COUNT rightmost elements are lost.
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-left of an UNSIGNED vector COUNT times.
-- Id: S.6
function ROTATE_RIGHT (ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-right of an UNSIGNED vector COUNT times.
-- Id: S.7
function ROTATE_LEFT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a logical rotate-left of a SIGNED
-- vector COUNT times.
-- Id: S.8
function ROTATE_RIGHT (ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a logical rotate-right of a SIGNED
-- vector COUNT times.
--============================================================================
--============================================================================
------------------------------------------------------------------------------
-- Note : Function S.9 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.10 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.10
function "sll" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.11 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.12 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.12
function "srl" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: SIGNED(SHIFT_RIGHT(UNSIGNED(ARG), COUNT))
------------------------------------------------------------------------------
-- Note : Function S.13 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.14
function "rol" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.15 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG: UNSIGNED; COUNT: INTEGER) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note : Function S.16 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.16
function "ror" (ARG: SIGNED; COUNT: INTEGER) return SIGNED; --V93
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
--============================================================================
-- RESIZE Functions
--============================================================================
-- Id: R.1
function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED;
-- Result subtype: SIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the SIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with the sign bit (ARG'LEFT). When truncating,
-- the sign bit is retained along with the rightmost part.
-- Id: R.2
function RESIZE (ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(NEW_SIZE-1 downto 0)
-- Result: Resizes the SIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
--============================================================================
-- Conversion Functions
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG: UNSIGNED) return NATURAL;
-- Result subtype: NATURAL. Value cannot be negative since parameter is an
-- UNSIGNED vector.
-- Result: Converts the UNSIGNED vector to an INTEGER.
-- Id: D.2
function TO_INTEGER (ARG: SIGNED) return INTEGER;
-- Result subtype: INTEGER
-- Result: Converts a SIGNED vector to an INTEGER.
-- Id: D.3
function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(SIZE-1 downto 0)
-- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
-- the specified SIZE.
-- Id: D.4
function TO_SIGNED (ARG: INTEGER; SIZE: NATURAL) return SIGNED;
-- Result subtype: SIGNED(SIZE-1 downto 0)
-- Result: Converts an INTEGER to a SIGNED vector of the specified SIZE.
--============================================================================
-- Logical Operators
--============================================================================
-- Id: L.1
function "not" (L: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Termwise inversion
-- Id: L.2
function "and" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector AND operation
-- Id: L.3
function "or" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector OR operation
-- Id: L.4
function "nand" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NAND operation
-- Id: L.5
function "nor" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NOR operation
-- Id: L.6
function "xor" (L, R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XOR operation
-- ---------------------------------------------------------------------------
-- Note : Function L.7 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
-- ---------------------------------------------------------------------------
-- Id: L.7
function "xnor" (L, R: UNSIGNED) return UNSIGNED; --V93
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XNOR operation
-- Id: L.8
function "not" (L: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Termwise inversion
-- Id: L.9
function "and" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector AND operation
-- Id: L.10
function "or" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector OR operation
-- Id: L.11
function "nand" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NAND operation
-- Id: L.12
function "nor" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector NOR operation
-- Id: L.13
function "xor" (L, R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XOR operation
-- ---------------------------------------------------------------------------
-- Note : Function L.14 is not compatible with VHDL 1076-1987. Comment
-- out the function (declaration and body) for VHDL 1076-1987 compatibility.
-- ---------------------------------------------------------------------------
-- Id: L.14
function "xnor" (L, R: SIGNED) return SIGNED; --V93
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Vector XNOR operation
--============================================================================
-- Match Functions
--============================================================================
-- Id: M.1
function STD_MATCH (L, R: STD_ULOGIC) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: terms compared per STD_LOGIC_1164 intent
-- Id: M.2
function STD_MATCH (L, R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: terms compared per STD_LOGIC_1164 intent
-- Id: M.3
function STD_MATCH (L, R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: terms compared per STD_LOGIC_1164 intent
-- Id: M.4
function STD_MATCH (L, R: STD_LOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: terms compared per STD_LOGIC_1164 intent
-- Id: M.5
function STD_MATCH (L, R: STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: terms compared per STD_LOGIC_1164 intent
--============================================================================
-- Translation Functions
--============================================================================
-- Id: T.1
function TO_01 (S: UNSIGNED; XMAP: STD_LOGIC := '0') return UNSIGNED;
-- Result subtype: UNSIGNED(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', and 'L' is translated
-- to '0'. If a value other than '0'|'1'|'H'|'L' is found,
-- the array is set to (others => XMAP), and a warning is
-- issued.
-- Id: T.2
function TO_01 (S: SIGNED; XMAP: STD_LOGIC := '0') return SIGNED;
-- Result subtype: SIGNED(S'RANGE)
-- Result: Termwise, 'H' is translated to '1', and 'L' is translated
-- to '0'. If a value other than '0'|'1'|'H'|'L' is found,
-- the array is set to (others => XMAP), and a warning is
-- issued.
end NUMERIC_STD;
|
mit
|
andrewandrepowell/kernel-on-chip
|
hdl/projects/Nexys4/jump_pack.vhd
|
1
|
792
|
library ieee;
use ieee.std_logic_1164.all;
package jump_pack is
constant cpu_width : integer := 32;
constant ram_size : integer := 10;
subtype word_type is std_logic_vector(cpu_width-1 downto 0);
type ram_type is array(0 to ram_size-1) of word_type;
function load_hex return ram_type;
end package;
package body jump_pack is
function load_hex return ram_type is
variable ram_buffer : ram_type := (others=>(others=>'0'));
begin
ram_buffer(0) := X"3C081000";
ram_buffer(1) := X"35080000";
ram_buffer(2) := X"01000008";
ram_buffer(3) := X"00000000";
ram_buffer(4) := X"00000100";
ram_buffer(5) := X"01010001";
ram_buffer(6) := X"00000000";
ram_buffer(7) := X"00000000";
ram_buffer(8) := X"00000000";
ram_buffer(9) := X"00000000";
return ram_buffer;
end;
end;
|
mit
|
antlr/grammars-v4
|
vhdl/examples/arith.vhd
|
6
|
72193
|
--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990,1991,1992 by Synopsys, Inc. All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_ARITH --
-- --
-- Purpose: --
-- A set of arithemtic, conversion, and comparison functions --
-- for SIGNED, UNSIGNED, SMALL_INT, INTEGER, --
-- STD_ULOGIC, STD_LOGIC, and STD_LOGIC_VECTOR. --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package std_logic_arith is
type UNSIGNED is array (NATURAL range <>) of STD_LOGIC;
type SIGNED is array (NATURAL range <>) of STD_LOGIC;
subtype SMALL_INT is INTEGER range 0 to 1;
----------------
-- add operators
----------------
function "+"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED; R: SIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: SIGNED) return SIGNED;
function "+"(L: SIGNED; R: UNSIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: INTEGER) return UNSIGNED;
function "+"(L: INTEGER; R: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED; R: INTEGER) return SIGNED;
function "+"(L: INTEGER; R: SIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED; R: STD_ULOGIC) return SIGNED;
function "+"(L: STD_ULOGIC; R: SIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR;
---------------------
-- subtract operators
---------------------
function "-"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED;
function "-"(L: SIGNED; R: SIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: SIGNED) return SIGNED;
function "-"(L: SIGNED; R: UNSIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: INTEGER) return UNSIGNED;
function "-"(L: INTEGER; R: UNSIGNED) return UNSIGNED;
function "-"(L: SIGNED; R: INTEGER) return SIGNED;
function "-"(L: INTEGER; R: SIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED;
function "-"(L: SIGNED; R: STD_ULOGIC) return SIGNED;
function "-"(L: STD_ULOGIC; R: SIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR;
------------------
-- unary operators
------------------
function "+"(L: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED) return SIGNED;
function "-"(L: SIGNED) return SIGNED;
function "ABS"(L: SIGNED) return SIGNED;
function "+"(L: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED) return STD_LOGIC_VECTOR;
function "ABS"(L: SIGNED) return STD_LOGIC_VECTOR;
---------------------------
-- multiplication operators
---------------------------
function "*"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED;
function "*"(L: SIGNED; R: SIGNED) return SIGNED;
function "*"(L: SIGNED; R: UNSIGNED) return SIGNED;
function "*"(L: UNSIGNED; R: SIGNED) return SIGNED;
function "*"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "*"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "*"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "*"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
-----------------------
-- less_than comparison
-----------------------
function "<"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "<"(L: SIGNED; R: SIGNED) return BOOLEAN;
function "<"(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "<"(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "<"(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "<"(L: SIGNED; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: SIGNED) return BOOLEAN;
--------------------------------
-- less_than_or_equal comparison
--------------------------------
function "<="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "<="(L: SIGNED; R: SIGNED) return BOOLEAN;
function "<="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "<="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "<="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "<="(L: SIGNED; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: SIGNED) return BOOLEAN;
--------------------------
-- greater_than comparison
--------------------------
function ">"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function ">"(L: SIGNED; R: SIGNED) return BOOLEAN;
function ">"(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function ">"(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function ">"(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function ">"(L: SIGNED; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: SIGNED) return BOOLEAN;
-----------------------------------
-- greater_than_or_equal comparison
-----------------------------------
function ">="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function ">="(L: SIGNED; R: SIGNED) return BOOLEAN;
function ">="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function ">="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function ">="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function ">="(L: SIGNED; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: SIGNED) return BOOLEAN;
-------------------
-- equal comparison
-------------------
function "="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "="(L: SIGNED; R: SIGNED) return BOOLEAN;
function "="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "="(L: SIGNED; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: SIGNED) return BOOLEAN;
-----------------------
-- not equal comparison
-----------------------
function "/="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "/="(L: SIGNED; R: SIGNED) return BOOLEAN;
function "/="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "/="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "/="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "/="(L: SIGNED; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: SIGNED) return BOOLEAN;
------------------
-- shift operators
------------------
function SHL(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED;
function SHL(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED;
function SHR(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED;
function SHR(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED;
-----------------------
-- conversion operators
-----------------------
function CONV_INTEGER(ARG: INTEGER) return INTEGER;
function CONV_INTEGER(ARG: UNSIGNED) return INTEGER;
function CONV_INTEGER(ARG: SIGNED) return INTEGER;
function CONV_INTEGER(ARG: STD_ULOGIC) return SMALL_INT;
function CONV_UNSIGNED(ARG: INTEGER; SIZE: INTEGER) return UNSIGNED;
function CONV_UNSIGNED(ARG: UNSIGNED; SIZE: INTEGER) return UNSIGNED;
function CONV_UNSIGNED(ARG: SIGNED; SIZE: INTEGER) return UNSIGNED;
function CONV_UNSIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return UNSIGNED;
function CONV_SIGNED(ARG: INTEGER; SIZE: INTEGER) return SIGNED;
function CONV_SIGNED(ARG: UNSIGNED; SIZE: INTEGER) return SIGNED;
function CONV_SIGNED(ARG: SIGNED; SIZE: INTEGER) return SIGNED;
function CONV_SIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return SIGNED;
function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: UNSIGNED; SIZE: INTEGER) return STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: SIGNED; SIZE: INTEGER) return STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: STD_ULOGIC; SIZE: INTEGER) return STD_LOGIC_VECTOR;
----------------------------------------------
-- zero extend STD_LOGIC_VECTOR (ARG) to SIZE,
-- SIZE < 0 is same as SIZE = 0
-- returns STD_LOGIC_VECTOR(SIZE-1 downto 0)
----------------------------------------------
function EXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR;
----------------------------------------------
-- sign extend STD_LOGIC_VECTOR (ARG) to SIZE,
-- SIZE < 0 is same as SIZE = 0
-- return STD_LOGIC_VECTOR(SIZE-1 downto 0)
----------------------------------------------
function SXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR;
end Std_logic_arith;
library IEEE;
use IEEE.std_logic_1164.all;
package body std_logic_arith is
function max(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
-- synopsys synthesis_off
type tbl_type is array (STD_ULOGIC) of STD_ULOGIC;
constant tbl_BINARY : tbl_type :=
('X', 'X', '0', '1', 'X', 'X', '0', '1', 'X');
-- synopsys synthesis_on
-- synopsys synthesis_off
type tbl_mvl9_boolean is array (STD_ULOGIC) of boolean;
constant IS_X : tbl_mvl9_boolean :=
(true, true, false, false, true, true, false, false, true);
-- synopsys synthesis_on
function MAKE_BINARY(A : STD_ULOGIC) return STD_ULOGIC is
-- synopsys built_in SYN_FEED_THRU
begin
-- synopsys synthesis_off
if (IS_X(A)) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
return ('X');
end if;
return tbl_BINARY(A);
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : UNSIGNED) return UNSIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : UNSIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : UNSIGNED) return SIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : SIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : SIGNED) return UNSIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : UNSIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : SIGNED) return SIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : SIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : STD_LOGIC_VECTOR (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : UNSIGNED) return STD_LOGIC_VECTOR is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : STD_LOGIC_VECTOR (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : SIGNED) return STD_LOGIC_VECTOR is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : STD_LOGIC_VECTOR (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
-- Type propagation function which returns a signed type with the
-- size of the left arg.
function LEFT_SIGNED_ARG(A,B: SIGNED) return SIGNED is
variable Z: SIGNED (A'left downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns an unsigned type with the
-- size of the left arg.
function LEFT_UNSIGNED_ARG(A,B: UNSIGNED) return UNSIGNED is
variable Z: UNSIGNED (A'left downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns a signed type with the
-- size of the result of a signed multiplication
function MULT_SIGNED_ARG(A,B: SIGNED) return SIGNED is
variable Z: SIGNED ((A'length+B'length-1) downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns an unsigned type with the
-- size of the result of a unsigned multiplication
function MULT_UNSIGNED_ARG(A,B: UNSIGNED) return UNSIGNED is
variable Z: UNSIGNED ((A'length+B'length-1) downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
function mult(A,B: SIGNED) return SIGNED is
variable BA: SIGNED((A'length+B'length-1) downto 0);
variable PA: SIGNED((A'length+B'length-1) downto 0);
variable AA: SIGNED(A'length downto 0);
variable neg: STD_ULOGIC;
constant one : UNSIGNED(1 downto 0) := "01";
-- pragma map_to_operator MULT_TC_OP
-- pragma type_function MULT_SIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
PA := (others => 'X');
return(PA);
end if;
PA := (others => '0');
neg := B(B'left) xor A(A'left);
BA := CONV_SIGNED(('0' & ABS(B)),(A'length+B'length));
AA := '0' & ABS(A);
for i in 0 to A'length-1 loop
if AA(i) = '1' then
PA := PA+BA;
end if;
BA := SHL(BA,one);
end loop;
if (neg= '1') then
return(-PA);
else
return(PA);
end if;
end;
function mult(A,B: UNSIGNED) return UNSIGNED is
variable BA: UNSIGNED((A'length+B'length-1) downto 0);
variable PA: UNSIGNED((A'length+B'length-1) downto 0);
constant one : UNSIGNED(1 downto 0) := "01";
-- pragma map_to_operator MULT_UNS_OP
-- pragma type_function MULT_UNSIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
PA := (others => 'X');
return(PA);
end if;
PA := (others => '0');
BA := CONV_UNSIGNED(B,(A'length+B'length));
for i in 0 to A'length-1 loop
if A(i) = '1' then
PA := PA+BA;
end if;
BA := SHL(BA,one);
end loop;
return(PA);
end;
-- subtract two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function minus(A, B: SIGNED) return SIGNED is
variable carry: STD_ULOGIC;
variable BV: STD_ULOGIC_VECTOR (A'left downto 0);
variable sum: SIGNED (A'left downto 0);
-- pragma map_to_operator SUB_TC_OP
-- pragma type_function LEFT_SIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '1';
BV := not STD_ULOGIC_VECTOR(B);
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
-- add two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function plus(A, B: SIGNED) return SIGNED is
variable carry: STD_ULOGIC;
variable BV, sum: SIGNED (A'left downto 0);
-- pragma map_to_operator ADD_TC_OP
-- pragma type_function LEFT_SIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '0';
BV := B;
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
-- subtract two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_minus(A, B: UNSIGNED) return UNSIGNED is
variable carry: STD_ULOGIC;
variable BV: STD_ULOGIC_VECTOR (A'left downto 0);
variable sum: UNSIGNED (A'left downto 0);
-- pragma map_to_operator SUB_UNS_OP
-- pragma type_function LEFT_UNSIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '1';
BV := not STD_ULOGIC_VECTOR(B);
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
-- add two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_plus(A, B: UNSIGNED) return UNSIGNED is
variable carry: STD_ULOGIC;
variable BV, sum: UNSIGNED (A'left downto 0);
-- pragma map_to_operator ADD_UNS_OP
-- pragma type_function LEFT_UNSIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '0';
BV := B;
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
function "*"(L: SIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to mult
begin
return mult(CONV_SIGNED(L, L'length),
CONV_SIGNED(R, R'length)); -- pragma label mult
end;
function "*"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to mult
begin
return mult(CONV_UNSIGNED(L, L'length),
CONV_UNSIGNED(R, R'length)); -- pragma label mult
end;
function "*"(L: UNSIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
begin
return mult(CONV_SIGNED(L, L'length+1),
CONV_SIGNED(R, R'length)); -- pragma label mult
end;
function "*"(L: SIGNED; R: UNSIGNED) return SIGNED is
-- pragma label_applies_to plus
begin
return mult(CONV_SIGNED(L, L'length),
CONV_SIGNED(R, R'length+1)); -- pragma label mult
end;
function "*"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
begin
return STD_LOGIC_VECTOR (mult(CONV_SIGNED(L, L'length),
CONV_SIGNED(R, R'length))); -- pragma label mult
end;
function "*"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
begin
return STD_LOGIC_VECTOR (mult(CONV_UNSIGNED(L, L'length),
CONV_UNSIGNED(R, R'length))); -- pragma label mult
end;
function "*"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
begin
return STD_LOGIC_VECTOR (mult(CONV_SIGNED(L, L'length+1),
CONV_SIGNED(R, R'length))); -- pragma label mult
end;
function "*"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
begin
return STD_LOGIC_VECTOR (mult(CONV_SIGNED(L, L'length),
CONV_SIGNED(R, R'length+1))); -- pragma label mult
end;
function "+"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to plus
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_plus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label plus
end;
function "+"(L: SIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
constant length: INTEGER := max(L'length, R'length);
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
constant length: INTEGER := max(L'length + 1, R'length);
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: SIGNED; R: UNSIGNED) return SIGNED is
-- pragma label_applies_to plus
constant length: INTEGER := max(L'length, R'length + 1);
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: INTEGER) return UNSIGNED is
-- pragma label_applies_to plus
constant length: INTEGER := L'length + 1;
begin
return CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length),
CONV_SIGNED(R, length)),
length-1);
end;
function "+"(L: INTEGER; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to plus
constant length: INTEGER := R'length + 1;
begin
return CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length),
CONV_SIGNED(R, length)),
length-1);
end;
function "+"(L: SIGNED; R: INTEGER) return SIGNED is
-- pragma label_applies_to plus
constant length: INTEGER := L'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: INTEGER; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
constant length: INTEGER := R'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
-- pragma label_applies_to plus
constant length: INTEGER := L'length;
begin
return unsigned_plus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)) ; -- pragma label plus
end;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to plus
constant length: INTEGER := R'length;
begin
return unsigned_plus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label plus
end;
function "+"(L: SIGNED; R: STD_ULOGIC) return SIGNED is
-- pragma label_applies_to plus
constant length: INTEGER := L'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: STD_ULOGIC; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
constant length: INTEGER := R'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (unsigned_plus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length))); -- pragma label plus
end;
function "+"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length))); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := max(L'length + 1, R'length);
begin
return STD_LOGIC_VECTOR (plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length))); -- pragma label plus
end;
function "+"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := max(L'length, R'length + 1);
begin
return STD_LOGIC_VECTOR (plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length))); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := L'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length),
CONV_SIGNED(R, length)),
length-1));
end;
function "+"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := R'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length),
CONV_SIGNED(R, length)),
length-1));
end;
function "+"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length))); -- pragma label plus
end;
function "+"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length))); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (unsigned_plus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length))) ; -- pragma label plus
end;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (unsigned_plus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length))); -- pragma label plus
end;
function "+"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length))); -- pragma label plus
end;
function "+"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length))); -- pragma label plus
end;
function "-"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to minus
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_minus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label minus
end;
function "-"(L: SIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
constant length: INTEGER := max(L'length, R'length);
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
constant length: INTEGER := max(L'length + 1, R'length);
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: SIGNED; R: UNSIGNED) return SIGNED is
-- pragma label_applies_to minus
constant length: INTEGER := max(L'length, R'length + 1);
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: INTEGER) return UNSIGNED is
-- pragma label_applies_to minus
constant length: INTEGER := L'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length),
CONV_SIGNED(R, length)),
length-1);
end;
function "-"(L: INTEGER; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to minus
constant length: INTEGER := R'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length),
CONV_SIGNED(R, length)),
length-1);
end;
function "-"(L: SIGNED; R: INTEGER) return SIGNED is
-- pragma label_applies_to minus
constant length: INTEGER := L'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: INTEGER; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
constant length: INTEGER := R'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
-- pragma label_applies_to minus
constant length: INTEGER := L'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length),
CONV_SIGNED(R, length)),
length-1);
end;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to minus
constant length: INTEGER := R'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length),
CONV_SIGNED(R, length)),
length-1);
end;
function "-"(L: SIGNED; R: STD_ULOGIC) return SIGNED is
-- pragma label_applies_to minus
constant length: INTEGER := L'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: STD_ULOGIC; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
constant length: INTEGER := R'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (unsigned_minus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length))); -- pragma label minus
end;
function "-"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length))); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := max(L'length + 1, R'length);
begin
return STD_LOGIC_VECTOR (minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length))); -- pragma label minus
end;
function "-"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := max(L'length, R'length + 1);
begin
return STD_LOGIC_VECTOR (minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length))); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := L'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length),
CONV_SIGNED(R, length)),
length-1));
end;
function "-"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := R'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length),
CONV_SIGNED(R, length)),
length-1));
end;
function "-"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length))); -- pragma label minus
end;
function "-"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length))); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := L'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length),
CONV_SIGNED(R, length)),
length-1));
end;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := R'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length),
CONV_SIGNED(R, length)),
length-1));
end;
function "-"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length))); -- pragma label minus
end;
function "-"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length))); -- pragma label minus
end;
function "+"(L: UNSIGNED) return UNSIGNED is
begin
return L;
end;
function "+"(L: SIGNED) return SIGNED is
begin
return L;
end;
function "-"(L: SIGNED) return SIGNED is
-- pragma label_applies_to minus
begin
return 0 - L; -- pragma label minus
end;
function "ABS"(L: SIGNED) return SIGNED is
begin
if (L(L'left) = '0' or L(L'left) = 'L') then
return L;
else
return 0 - L;
end if;
end;
function "+"(L: UNSIGNED) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L);
end;
function "+"(L: SIGNED) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (L);
end;
function "-"(L: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable tmp: SIGNED(L'length-1 downto 0);
begin
tmp := 0 - L; -- pragma label minus
return STD_LOGIC_VECTOR (tmp);
end;
function "ABS"(L: SIGNED) return STD_LOGIC_VECTOR is
variable tmp: SIGNED(L'length-1 downto 0);
begin
if (L(L'left) = '0' or L(L'left) = 'L') then
return STD_LOGIC_VECTOR (L);
else
tmp := 0 - L;
return STD_LOGIC_VECTOR (tmp);
end if;
end;
-- Type propagation function which returns the type BOOLEAN
function UNSIGNED_RETURN_BOOLEAN(A,B: UNSIGNED) return BOOLEAN is
variable Z: BOOLEAN;
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns the type BOOLEAN
function SIGNED_RETURN_BOOLEAN(A,B: SIGNED) return BOOLEAN is
variable Z: BOOLEAN;
-- pragma return_port_name Z
begin
return(Z);
end;
-- compare two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function is_less(A, B: SIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LT_TC_OP
-- pragma type_function SIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
if A(sign) /= B(sign) then
result := A(sign) = '1';
else
result := FALSE;
for i in 0 to sign-1 loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
end if;
return result;
end;
-- compare two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function is_less_or_equal(A, B: SIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LEQ_TC_OP
-- pragma type_function SIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
if A(sign) /= B(sign) then
result := A(sign) = '1';
else
result := TRUE;
for i in 0 to sign-1 loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
end if;
return result;
end;
-- compare two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_is_less(A, B: UNSIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LT_UNS_OP
-- pragma type_function UNSIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
result := FALSE;
for i in 0 to sign loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
return result;
end;
-- compare two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_is_less_or_equal(A, B: UNSIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LEQ_UNS_OP
-- pragma type_function UNSIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
result := TRUE;
for i in 0 to sign loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
return result;
end;
function "<"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label lt
end;
function "<"(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := max(L'length, R'length);
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := L'length + 1;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := R'length + 1;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := L'length;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := R'length;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to leq
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less_or_equal(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label leq
end;
function "<="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to leq
constant length: INTEGER := max(L'length, R'length);
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to leq
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to leq
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
constant length: INTEGER := L'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to leq
constant length: INTEGER := R'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
constant length: INTEGER := L'length;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to leq
constant length: INTEGER := R'length;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function ">"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to gt
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less(CONV_UNSIGNED(R, length),
CONV_UNSIGNED(L, length)); -- pragma label gt
end;
function ">"(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to gt
constant length: INTEGER := max(L'length, R'length);
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to gt
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to gt
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
constant length: INTEGER := L'length + 1;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to gt
constant length: INTEGER := R'length + 1;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
constant length: INTEGER := L'length;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to gt
constant length: INTEGER := R'length;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to geq
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less_or_equal(CONV_UNSIGNED(R, length),
CONV_UNSIGNED(L, length)); -- pragma label geq
end;
function ">="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to geq
constant length: INTEGER := max(L'length, R'length);
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to geq
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to geq
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
constant length: INTEGER := L'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to geq
constant length: INTEGER := R'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
constant length: INTEGER := L'length;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to geq
constant length: INTEGER := R'length;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
-- for internal use only. Assumes SIGNED arguments of equal length.
function bitwise_eql(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR)
return BOOLEAN is
-- pragma built_in SYN_EQL
begin
for i in L'range loop
if L(i) /= R(i) then
return FALSE;
end if;
end loop;
return TRUE;
end;
-- for internal use only. Assumes SIGNED arguments of equal length.
function bitwise_neq(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR)
return BOOLEAN is
-- pragma built_in SYN_NEQ
begin
for i in L'range loop
if L(i) /= R(i) then
return TRUE;
end if;
end loop;
return FALSE;
end;
function "="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_UNSIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_UNSIGNED(R, length) ) );
end;
function "="(L: SIGNED; R: SIGNED) return BOOLEAN is
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
constant length: INTEGER := max(L'length + 1, R'length);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
constant length: INTEGER := max(L'length, R'length + 1);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
constant length: INTEGER := L'length + 1;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
constant length: INTEGER := R'length + 1;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: SIGNED; R: INTEGER) return BOOLEAN is
constant length: INTEGER := L'length;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: INTEGER; R: SIGNED) return BOOLEAN is
constant length: INTEGER := R'length;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_UNSIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_UNSIGNED(R, length) ) );
end;
function "/="(L: SIGNED; R: SIGNED) return BOOLEAN is
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
constant length: INTEGER := max(L'length + 1, R'length);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
constant length: INTEGER := max(L'length, R'length + 1);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
constant length: INTEGER := L'length + 1;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
constant length: INTEGER := R'length + 1;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: SIGNED; R: INTEGER) return BOOLEAN is
constant length: INTEGER := L'length;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: INTEGER; R: SIGNED) return BOOLEAN is
constant length: INTEGER := R'length;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function SHL(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED is
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is UNSIGNED (result_msb downto 0);
variable result, temp: rtype;
begin
control := MAKE_BINARY(COUNT);
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := ARG;
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => '0');
if 2**i <= result_msb then
temp(result_msb downto 2**i) :=
result(result_msb - 2**i downto 0);
end if;
result := temp;
end if;
end loop;
return result;
end;
function SHL(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED is
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is SIGNED (result_msb downto 0);
variable result, temp: rtype;
begin
control := MAKE_BINARY(COUNT);
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := ARG;
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => '0');
if 2**i <= result_msb then
temp(result_msb downto 2**i) :=
result(result_msb - 2**i downto 0);
end if;
result := temp;
end if;
end loop;
return result;
end;
function SHR(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED is
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is UNSIGNED (result_msb downto 0);
variable result, temp: rtype;
begin
control := MAKE_BINARY(COUNT);
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := ARG;
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => '0');
if 2**i <= result_msb then
temp(result_msb - 2**i downto 0) :=
result(result_msb downto 2**i);
end if;
result := temp;
end if;
end loop;
return result;
end;
function SHR(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED is
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is SIGNED (result_msb downto 0);
variable result, temp: rtype;
variable sign_bit: STD_ULOGIC;
begin
control := MAKE_BINARY(COUNT);
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := ARG;
sign_bit := ARG(ARG'left);
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => sign_bit);
if 2**i <= result_msb then
temp(result_msb - 2**i downto 0) :=
result(result_msb downto 2**i);
end if;
result := temp;
end if;
end loop;
return result;
end;
function CONV_INTEGER(ARG: INTEGER) return INTEGER is
begin
return ARG;
end;
function CONV_INTEGER(ARG: UNSIGNED) return INTEGER is
variable result: INTEGER;
variable tmp: STD_ULOGIC;
-- synopsys built_in SYN_UNSIGNED_TO_INTEGER
begin
-- synopsys synthesis_off
assert ARG'length <= 31
report "ARG is too large in CONV_INTEGER"
severity FAILURE;
result := 0;
for i in ARG'range loop
result := result * 2;
tmp := tbl_BINARY(ARG(i));
if tmp = '1' then
result := result + 1;
elsif tmp = 'X' then
assert false
report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0."
severity WARNING;
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_INTEGER(ARG: SIGNED) return INTEGER is
variable result: INTEGER;
variable tmp: STD_ULOGIC;
-- synopsys built_in SYN_SIGNED_TO_INTEGER
begin
-- synopsys synthesis_off
assert ARG'length <= 32
report "ARG is too large in CONV_INTEGER"
severity FAILURE;
result := 0;
for i in ARG'range loop
if i /= ARG'left then
result := result * 2;
tmp := tbl_BINARY(ARG(i));
if tmp = '1' then
result := result + 1;
elsif tmp = 'X' then
assert false
report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0."
severity WARNING;
end if;
end if;
end loop;
tmp := MAKE_BINARY(ARG(ARG'left));
if tmp = '1' then
if ARG'length = 32 then
result := (result - 2**30) - 2**30;
else
result := result - (2 ** (ARG'length-1));
end if;
end if;
return result;
-- synopsys synthesis_on
end;
function CONV_INTEGER(ARG: STD_ULOGIC) return SMALL_INT is
variable tmp: STD_ULOGIC;
-- synopsys built_in SYN_FEED_THRU
begin
-- synopsys synthesis_off
tmp := tbl_BINARY(ARG);
if tmp = '1' then
return 1;
elsif tmp = 'X' then
assert false
report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0."
severity WARNING;
return 0;
else
return 0;
end if;
-- synopsys synthesis_on
end;
-- convert an integer to a unsigned STD_ULOGIC_VECTOR
function CONV_UNSIGNED(ARG: INTEGER; SIZE: INTEGER) return UNSIGNED is
variable result: UNSIGNED(SIZE-1 downto 0);
variable temp: integer;
-- synopsys built_in SYN_INTEGER_TO_UNSIGNED
begin
-- synopsys synthesis_off
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
else
temp := (temp - 1) / 2; -- simulate ASR
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_UNSIGNED(ARG: UNSIGNED; SIZE: INTEGER) return UNSIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is UNSIGNED (SIZE-1 downto 0);
variable new_bounds: UNSIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_UNSIGNED(ARG: SIGNED; SIZE: INTEGER) return UNSIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is UNSIGNED (SIZE-1 downto 0);
variable new_bounds: UNSIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_UNSIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return UNSIGNED is
subtype rtype is UNSIGNED (SIZE-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
begin
-- synopsys synthesis_off
result := rtype'(others => '0');
result(0) := MAKE_BINARY(ARG);
if (result(0) = 'X') then
result := rtype'(others => 'X');
end if;
return result;
-- synopsys synthesis_on
end;
-- convert an integer to a 2's complement STD_ULOGIC_VECTOR
function CONV_SIGNED(ARG: INTEGER; SIZE: INTEGER) return SIGNED is
variable result: SIGNED (SIZE-1 downto 0);
variable temp: integer;
-- synopsys built_in SYN_INTEGER_TO_SIGNED
begin
-- synopsys synthesis_off
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
else
temp := (temp - 1) / 2; -- simulate ASR
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_SIGNED(ARG: UNSIGNED; SIZE: INTEGER) return SIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is SIGNED (SIZE-1 downto 0);
variable new_bounds : SIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_SIGNED(ARG: SIGNED; SIZE: INTEGER) return SIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is SIGNED (SIZE-1 downto 0);
variable new_bounds : SIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_SIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return SIGNED is
subtype rtype is SIGNED (SIZE-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
begin
-- synopsys synthesis_off
result := rtype'(others => '0');
result(0) := MAKE_BINARY(ARG);
if (result(0) = 'X') then
result := rtype'(others => 'X');
end if;
return result;
-- synopsys synthesis_on
end;
-- convert an integer to an STD_LOGIC_VECTOR
function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR is
variable result: STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable temp: integer;
-- synopsys built_in SYN_INTEGER_TO_SIGNED
begin
-- synopsys synthesis_off
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
else
temp := (temp - 1) / 2; -- simulate ASR
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_STD_LOGIC_VECTOR(ARG: UNSIGNED; SIZE: INTEGER) return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds : STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_STD_LOGIC_VECTOR(ARG: SIGNED; SIZE: INTEGER) return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds : STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_STD_LOGIC_VECTOR(ARG: STD_ULOGIC; SIZE: INTEGER) return STD_LOGIC_VECTOR is
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
begin
-- synopsys synthesis_off
result := rtype'(others => '0');
result(0) := MAKE_BINARY(ARG);
if (result(0) = 'X') then
result := rtype'(others => 'X');
end if;
return result;
-- synopsys synthesis_on
end;
function EXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER)
return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds: STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function SXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds : STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
end std_logic_arith;
|
mit
|
chcbaram/Altera_DE0_nano_Exam
|
prj_niosii_test/niosii/synthesis/niosii_rst_controller_001.vhd
|
6
|
9084
|
-- niosii_rst_controller_001.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_rst_controller_001 is
generic (
NUM_RESET_INPUTS : integer := 1;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 1;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := '0'; -- reset_in0.reset
clk : in std_logic := '0'; -- clk.clk
reset_out : out std_logic; -- reset_out.reset
reset_req : out std_logic; -- .reset_req
reset_in1 : in std_logic := '0';
reset_in10 : in std_logic := '0';
reset_in11 : in std_logic := '0';
reset_in12 : in std_logic := '0';
reset_in13 : in std_logic := '0';
reset_in14 : in std_logic := '0';
reset_in15 : in std_logic := '0';
reset_in2 : in std_logic := '0';
reset_in3 : in std_logic := '0';
reset_in4 : in std_logic := '0';
reset_in5 : in std_logic := '0';
reset_in6 : in std_logic := '0';
reset_in7 : in std_logic := '0';
reset_in8 : in std_logic := '0';
reset_in9 : in std_logic := '0';
reset_req_in0 : in std_logic := '0';
reset_req_in1 : in std_logic := '0';
reset_req_in10 : in std_logic := '0';
reset_req_in11 : in std_logic := '0';
reset_req_in12 : in std_logic := '0';
reset_req_in13 : in std_logic := '0';
reset_req_in14 : in std_logic := '0';
reset_req_in15 : in std_logic := '0';
reset_req_in2 : in std_logic := '0';
reset_req_in3 : in std_logic := '0';
reset_req_in4 : in std_logic := '0';
reset_req_in5 : in std_logic := '0';
reset_req_in6 : in std_logic := '0';
reset_req_in7 : in std_logic := '0';
reset_req_in8 : in std_logic := '0';
reset_req_in9 : in std_logic := '0'
);
end entity niosii_rst_controller_001;
architecture rtl of niosii_rst_controller_001 is
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component altera_reset_controller;
begin
rst_controller_001 : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => NUM_RESET_INPUTS,
OUTPUT_RESET_SYNC_EDGES => OUTPUT_RESET_SYNC_EDGES,
SYNC_DEPTH => SYNC_DEPTH,
RESET_REQUEST_PRESENT => RESET_REQUEST_PRESENT,
RESET_REQ_WAIT_TIME => RESET_REQ_WAIT_TIME,
MIN_RST_ASSERTION_TIME => MIN_RST_ASSERTION_TIME,
RESET_REQ_EARLY_DSRT_TIME => RESET_REQ_EARLY_DSRT_TIME,
USE_RESET_REQUEST_IN0 => USE_RESET_REQUEST_IN0,
USE_RESET_REQUEST_IN1 => USE_RESET_REQUEST_IN1,
USE_RESET_REQUEST_IN2 => USE_RESET_REQUEST_IN2,
USE_RESET_REQUEST_IN3 => USE_RESET_REQUEST_IN3,
USE_RESET_REQUEST_IN4 => USE_RESET_REQUEST_IN4,
USE_RESET_REQUEST_IN5 => USE_RESET_REQUEST_IN5,
USE_RESET_REQUEST_IN6 => USE_RESET_REQUEST_IN6,
USE_RESET_REQUEST_IN7 => USE_RESET_REQUEST_IN7,
USE_RESET_REQUEST_IN8 => USE_RESET_REQUEST_IN8,
USE_RESET_REQUEST_IN9 => USE_RESET_REQUEST_IN9,
USE_RESET_REQUEST_IN10 => USE_RESET_REQUEST_IN10,
USE_RESET_REQUEST_IN11 => USE_RESET_REQUEST_IN11,
USE_RESET_REQUEST_IN12 => USE_RESET_REQUEST_IN12,
USE_RESET_REQUEST_IN13 => USE_RESET_REQUEST_IN13,
USE_RESET_REQUEST_IN14 => USE_RESET_REQUEST_IN14,
USE_RESET_REQUEST_IN15 => USE_RESET_REQUEST_IN15,
ADAPT_RESET_REQUEST => ADAPT_RESET_REQUEST
)
port map (
reset_in0 => reset_in0, -- reset_in0.reset
clk => clk, -- clk.clk
reset_out => reset_out, -- reset_out.reset
reset_req => reset_req, -- .reset_req
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
end architecture rtl; -- of niosii_rst_controller_001
|
mit
|
chcbaram/Altera_DE0_nano_Exam
|
prj_niosii_uart/niosii_top.vhd
|
2
|
3050
|
----------------------------------------------------------------------------------
-- Design Name : led_top
-- Create Date : 2015/12/31
-- Module Name :
-- Project Name :
-- Target Devices:
-- Tool Versions :
-- Description :
-- Revision :
-- Additional Comments:
--
----------------------------------------------------------------------------------
--The MIT License (MIT)
--
--Copyright (c) 2015
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
----------------------------------------------------------------------------------
-- Library Define
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
entity niosii_top is
Port (
p_clk_50Mhz : in std_logic;
p_button : in std_logic_vector( 1 downto 0 );
p_led_out : out std_logic_vector( 7 downto 0 );
p_uart_0_rxd : in std_logic;
p_uart_0_txd : out std_logic
);
end niosii_top;
architecture Behavioral of niosii_top is
component niosii is
port (
clk_clk : in std_logic := 'X'; -- clk
pio_0_external_connection_export : out std_logic_vector(7 downto 0); -- export
reset_reset_n : in std_logic := 'X'; -- reset_n
uart_0_rxd : in std_logic := 'X'; -- rxd
uart_0_txd : out std_logic -- txd
);
end component niosii;
signal s_reset_n : std_logic;
begin
s_reset_n <= p_button(0);
u0 : component niosii
port map (
clk_clk => p_clk_50Mhz,
pio_0_external_connection_export => p_led_out,
reset_reset_n => s_reset_n,
uart_0_rxd => p_uart_0_rxd,
uart_0_txd => p_uart_0_txd
);
end Behavioral;
|
mit
|
FrankBuss/YaGraphCon
|
spartan3e/src/rs232_sender.vhd
|
1
|
1739
|
-- Copyright (c) 2009 Frank Buss ([email protected])
-- See license.txt for license
--
-- Simple RS232 sender with generic baudrate and 8N1 mode.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
USE work.all;
entity rs232_sender is
generic(
-- clock frequency, in hz
SYSTEM_SPEED,
-- baudrate, in bps
BAUDRATE: integer
);
port(
clock: in std_logic;
-- RS232 for sending
data: in unsigned(7 downto 0);
-- RS232 TX pin
tx: out std_logic;
-- set this for one clock pulse to 1 for sending the data
sendTrigger: in std_logic;
-- this is set for one clock pulse to 1, when the data was sent
dataSent: out std_logic
);
end entity rs232_sender;
architecture rtl of rs232_sender is
constant MAX_COUNTER: natural := SYSTEM_SPEED / BAUDRATE;
signal baudrateCounter: natural range 0 to MAX_COUNTER := 0;
signal bitCounter: natural range 0 to 9 := 0;
signal shiftRegister: unsigned(9 downto 0) := (others => '0');
signal dataSendingStarted: std_logic := '0';
begin
process(clock)
begin
if rising_edge(clock) then
dataSent <= '0';
if dataSendingStarted = '1' then
if baudrateCounter = 0 then
tx <= shiftRegister(0);
shiftRegister <= shift_right(shiftRegister, 1);
if bitCounter > 0 then
bitCounter <= bitCounter - 1;
else
dataSendingStarted <= '0';
dataSent <= '1';
end if;
baudrateCounter <= MAX_COUNTER;
else
baudrateCounter <= baudrateCounter - 1;
end if;
else
tx <= '1';
if sendTrigger = '1' then
shiftRegister <= '1' & data & '0';
bitCounter <= 9;
baudrateCounter <= 0;
dataSendingStarted <= '1';
end if;
end if;
end if;
end process;
end architecture rtl;
|
mit
|
chcbaram/Altera_DE0_nano_Exam
|
prj_niosii_pll/niosii/niosii_inst.vhd
|
2
|
730
|
component niosii is
port (
clk_clk : in std_logic := 'X'; -- clk
pio_0_external_connection_export : out std_logic_vector(7 downto 0); -- export
reset_reset_n : in std_logic := 'X' -- reset_n
);
end component niosii;
u0 : component niosii
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
pio_0_external_connection_export => CONNECTED_TO_pio_0_external_connection_export, -- pio_0_external_connection.export
reset_reset_n => CONNECTED_TO_reset_reset_n -- reset.reset_n
);
|
mit
|
chcbaram/Altera_DE0_nano_Exam
|
prj_niosii_abot/ip_pwm/ip_pwm_out.vhd
|
6
|
3223
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 2015/01/14 00:19:02
-- Design Name:
-- Module Name: pwm_top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ip_pwm_out is
Port (
reset_n : in STD_LOGIC;
clk : in STD_LOGIC;
pwm_hz : in STD_LOGIC_VECTOR (7 downto 0);
pwm_dir : in STD_LOGIC;
pwm_duty : in STD_LOGIC_VECTOR (7 downto 0);
pwm_pin_duty : out STD_LOGIC;
pwm_pin_dir : out STD_LOGIC
);
end ip_pwm_out;
architecture Behavioral of ip_pwm_out is
signal pwm_cnt_div : std_logic_vector( 7 downto 0 );
signal pwm_cnt_div_p : std_logic;
signal pwm_cnt_div_pp : std_logic;
signal pwm_cnt : std_logic_vector( 7 downto 0 );
signal pwm_cnt_p : std_logic;
signal pwm_pin_duty_p : std_logic;
begin
pwm_pin_duty <= pwm_pin_duty_p;
pwm_pin_dir <= pwm_dir;
-- PWM 분주 타이머
--
process( clk ) is
begin
if rising_edge( clk ) then
if reset_n = '0' then
pwm_cnt_div <= ( others => '0' );
else
pwm_cnt_div <= pwm_cnt_div + 1;
end if;
end if;
end process;
process( clk ) is
begin
if rising_edge( clk ) then
case pwm_hz is
when x"00" => pwm_cnt_div_p <= pwm_cnt_div(0);
when x"01" => pwm_cnt_div_p <= pwm_cnt_div(1);
when x"02" => pwm_cnt_div_p <= pwm_cnt_div(2);
when x"03" => pwm_cnt_div_p <= pwm_cnt_div(3);
when x"04" => pwm_cnt_div_p <= pwm_cnt_div(4);
when x"05" => pwm_cnt_div_p <= pwm_cnt_div(5);
when x"06" => pwm_cnt_div_p <= pwm_cnt_div(6);
when x"07" => pwm_cnt_div_p <= pwm_cnt_div(7);
when others => pwm_cnt_div_p <= pwm_cnt_div(0);
end case;
pwm_cnt_div_pp <= pwm_cnt_div_p;
if pwm_cnt_div_pp = '0' and pwm_cnt_div_p = '1' then
pwm_cnt_p <= '1';
else
pwm_cnt_p <= '0';
end if;
end if;
end process;
-- PWM 기본 타이머
--
process( clk ) is
begin
if rising_edge( clk ) then
if reset_n = '0' then
pwm_cnt <= ( others => '0' );
else
if pwm_cnt_p = '1' then
pwm_cnt <= pwm_cnt + 1;
end if;
end if;
end if;
end process;
-- PWM 출력
--
process( clk ) is
begin
if rising_edge( clk ) then
if reset_n = '0' then
pwm_pin_duty_p <= '0';
else
if pwm_cnt < pwm_duty then
if pwm_duty = x"00" then
pwm_pin_duty_p <= '0';
else
pwm_pin_duty_p <= '1';
end if;
else
if pwm_duty = x"FF" then
pwm_pin_duty_p <= '1';
else
pwm_pin_duty_p <= '0';
end if;
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
chcbaram/Altera_DE0_nano_Exam
|
prj_niosii_abot/db/ip/niosii/submodules/ip_pwm_out.vhd
|
6
|
3223
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 2015/01/14 00:19:02
-- Design Name:
-- Module Name: pwm_top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ip_pwm_out is
Port (
reset_n : in STD_LOGIC;
clk : in STD_LOGIC;
pwm_hz : in STD_LOGIC_VECTOR (7 downto 0);
pwm_dir : in STD_LOGIC;
pwm_duty : in STD_LOGIC_VECTOR (7 downto 0);
pwm_pin_duty : out STD_LOGIC;
pwm_pin_dir : out STD_LOGIC
);
end ip_pwm_out;
architecture Behavioral of ip_pwm_out is
signal pwm_cnt_div : std_logic_vector( 7 downto 0 );
signal pwm_cnt_div_p : std_logic;
signal pwm_cnt_div_pp : std_logic;
signal pwm_cnt : std_logic_vector( 7 downto 0 );
signal pwm_cnt_p : std_logic;
signal pwm_pin_duty_p : std_logic;
begin
pwm_pin_duty <= pwm_pin_duty_p;
pwm_pin_dir <= pwm_dir;
-- PWM 분주 타이머
--
process( clk ) is
begin
if rising_edge( clk ) then
if reset_n = '0' then
pwm_cnt_div <= ( others => '0' );
else
pwm_cnt_div <= pwm_cnt_div + 1;
end if;
end if;
end process;
process( clk ) is
begin
if rising_edge( clk ) then
case pwm_hz is
when x"00" => pwm_cnt_div_p <= pwm_cnt_div(0);
when x"01" => pwm_cnt_div_p <= pwm_cnt_div(1);
when x"02" => pwm_cnt_div_p <= pwm_cnt_div(2);
when x"03" => pwm_cnt_div_p <= pwm_cnt_div(3);
when x"04" => pwm_cnt_div_p <= pwm_cnt_div(4);
when x"05" => pwm_cnt_div_p <= pwm_cnt_div(5);
when x"06" => pwm_cnt_div_p <= pwm_cnt_div(6);
when x"07" => pwm_cnt_div_p <= pwm_cnt_div(7);
when others => pwm_cnt_div_p <= pwm_cnt_div(0);
end case;
pwm_cnt_div_pp <= pwm_cnt_div_p;
if pwm_cnt_div_pp = '0' and pwm_cnt_div_p = '1' then
pwm_cnt_p <= '1';
else
pwm_cnt_p <= '0';
end if;
end if;
end process;
-- PWM 기본 타이머
--
process( clk ) is
begin
if rising_edge( clk ) then
if reset_n = '0' then
pwm_cnt <= ( others => '0' );
else
if pwm_cnt_p = '1' then
pwm_cnt <= pwm_cnt + 1;
end if;
end if;
end if;
end process;
-- PWM 출력
--
process( clk ) is
begin
if rising_edge( clk ) then
if reset_n = '0' then
pwm_pin_duty_p <= '0';
else
if pwm_cnt < pwm_duty then
if pwm_duty = x"00" then
pwm_pin_duty_p <= '0';
else
pwm_pin_duty_p <= '1';
end if;
else
if pwm_duty = x"FF" then
pwm_pin_duty_p <= '1';
else
pwm_pin_duty_p <= '0';
end if;
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
chcbaram/Altera_DE0_nano_Exam
|
prj_niosii_test/niosii/synthesis/niosii.vhd
|
1
|
62188
|
-- niosii.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii is
port (
clk_clk : in std_logic := '0'; -- clk.clk
pio_0_external_connection_export : out std_logic_vector(7 downto 0); -- pio_0_external_connection.export
reset_reset_n : in std_logic := '0'; -- reset.reset_n
sdram_addr : out std_logic_vector(12 downto 0); -- sdram.addr
sdram_ba : out std_logic_vector(1 downto 0); -- .ba
sdram_cas_n : out std_logic; -- .cas_n
sdram_cke : out std_logic; -- .cke
sdram_cs_n : out std_logic; -- .cs_n
sdram_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq
sdram_dqm : out std_logic_vector(1 downto 0); -- .dqm
sdram_ras_n : out std_logic; -- .ras_n
sdram_we_n : out std_logic; -- .we_n
sdram_clk_clk : out std_logic -- sdram_clk.clk
);
end entity niosii;
architecture rtl of niosii is
component niosii_jtag_uart_0 is
port (
clk : in std_logic := 'X'; -- clk
rst_n : in std_logic := 'X'; -- reset_n
av_chipselect : in std_logic := 'X'; -- chipselect
av_address : in std_logic := 'X'; -- address
av_read_n : in std_logic := 'X'; -- read_n
av_readdata : out std_logic_vector(31 downto 0); -- readdata
av_write_n : in std_logic := 'X'; -- write_n
av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
av_waitrequest : out std_logic; -- waitrequest
av_irq : out std_logic -- irq
);
end component niosii_jtag_uart_0;
component niosii_nios2_gen2_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
reset_req : in std_logic := 'X'; -- reset_req
d_address : out std_logic_vector(26 downto 0); -- address
d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
d_read : out std_logic; -- read
d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
d_waitrequest : in std_logic := 'X'; -- waitrequest
d_write : out std_logic; -- write
d_writedata : out std_logic_vector(31 downto 0); -- writedata
debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess
i_address : out std_logic_vector(26 downto 0); -- address
i_read : out std_logic; -- read
i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
i_waitrequest : in std_logic := 'X'; -- waitrequest
irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
debug_reset_request : out std_logic; -- reset
debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess
debug_mem_slave_read : in std_logic := 'X'; -- read
debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata
debug_mem_slave_waitrequest : out std_logic; -- waitrequest
debug_mem_slave_write : in std_logic := 'X'; -- write
debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
dummy_ci_port : out std_logic -- readra
);
end component niosii_nios2_gen2_0;
component niosii_onchip_memory2_0 is
port (
clk : in std_logic := 'X'; -- clk
address : in std_logic_vector(13 downto 0) := (others => 'X'); -- address
clken : in std_logic := 'X'; -- clken
chipselect : in std_logic := 'X'; -- chipselect
write : in std_logic := 'X'; -- write
readdata : out std_logic_vector(31 downto 0); -- readdata
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
reset : in std_logic := 'X'; -- reset
reset_req : in std_logic := 'X' -- reset_req
);
end component niosii_onchip_memory2_0;
component niosii_pio_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
write_n : in std_logic := 'X'; -- write_n
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
chipselect : in std_logic := 'X'; -- chipselect
readdata : out std_logic_vector(31 downto 0); -- readdata
out_port : out std_logic_vector(7 downto 0) -- export
);
end component niosii_pio_0;
component niosii_sdram_controller_0 is
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
az_addr : in std_logic_vector(23 downto 0) := (others => 'X'); -- address
az_be_n : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable_n
az_cs : in std_logic := 'X'; -- chipselect
az_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
az_rd_n : in std_logic := 'X'; -- read_n
az_wr_n : in std_logic := 'X'; -- write_n
za_data : out std_logic_vector(15 downto 0); -- readdata
za_valid : out std_logic; -- readdatavalid
za_waitrequest : out std_logic; -- waitrequest
zs_addr : out std_logic_vector(12 downto 0); -- export
zs_ba : out std_logic_vector(1 downto 0); -- export
zs_cas_n : out std_logic; -- export
zs_cke : out std_logic; -- export
zs_cs_n : out std_logic; -- export
zs_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- export
zs_dqm : out std_logic_vector(1 downto 0); -- export
zs_ras_n : out std_logic; -- export
zs_we_n : out std_logic -- export
);
end component niosii_sdram_controller_0;
component niosii_sys_sdram_pll_0 is
port (
ref_clk_clk : in std_logic := 'X'; -- clk
ref_reset_reset : in std_logic := 'X'; -- reset
sys_clk_clk : out std_logic; -- clk
sdram_clk_clk : out std_logic; -- clk
reset_source_reset : out std_logic -- reset
);
end component niosii_sys_sdram_pll_0;
component niosii_mm_interconnect_0 is
port (
clk_0_clk_clk : in std_logic := 'X'; -- clk
sys_sdram_pll_0_sys_clk_clk : in std_logic := 'X'; -- clk
jtag_uart_0_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
nios2_gen2_0_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset
nios2_gen2_0_data_master_address : in std_logic_vector(26 downto 0) := (others => 'X'); -- address
nios2_gen2_0_data_master_waitrequest : out std_logic; -- waitrequest
nios2_gen2_0_data_master_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
nios2_gen2_0_data_master_read : in std_logic := 'X'; -- read
nios2_gen2_0_data_master_readdata : out std_logic_vector(31 downto 0); -- readdata
nios2_gen2_0_data_master_write : in std_logic := 'X'; -- write
nios2_gen2_0_data_master_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
nios2_gen2_0_data_master_debugaccess : in std_logic := 'X'; -- debugaccess
nios2_gen2_0_instruction_master_address : in std_logic_vector(26 downto 0) := (others => 'X'); -- address
nios2_gen2_0_instruction_master_waitrequest : out std_logic; -- waitrequest
nios2_gen2_0_instruction_master_read : in std_logic := 'X'; -- read
nios2_gen2_0_instruction_master_readdata : out std_logic_vector(31 downto 0); -- readdata
jtag_uart_0_avalon_jtag_slave_address : out std_logic_vector(0 downto 0); -- address
jtag_uart_0_avalon_jtag_slave_write : out std_logic; -- write
jtag_uart_0_avalon_jtag_slave_read : out std_logic; -- read
jtag_uart_0_avalon_jtag_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
jtag_uart_0_avalon_jtag_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
jtag_uart_0_avalon_jtag_slave_waitrequest : in std_logic := 'X'; -- waitrequest
jtag_uart_0_avalon_jtag_slave_chipselect : out std_logic; -- chipselect
nios2_gen2_0_debug_mem_slave_address : out std_logic_vector(8 downto 0); -- address
nios2_gen2_0_debug_mem_slave_write : out std_logic; -- write
nios2_gen2_0_debug_mem_slave_read : out std_logic; -- read
nios2_gen2_0_debug_mem_slave_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
nios2_gen2_0_debug_mem_slave_writedata : out std_logic_vector(31 downto 0); -- writedata
nios2_gen2_0_debug_mem_slave_byteenable : out std_logic_vector(3 downto 0); -- byteenable
nios2_gen2_0_debug_mem_slave_waitrequest : in std_logic := 'X'; -- waitrequest
nios2_gen2_0_debug_mem_slave_debugaccess : out std_logic; -- debugaccess
onchip_memory2_0_s1_address : out std_logic_vector(13 downto 0); -- address
onchip_memory2_0_s1_write : out std_logic; -- write
onchip_memory2_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
onchip_memory2_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
onchip_memory2_0_s1_byteenable : out std_logic_vector(3 downto 0); -- byteenable
onchip_memory2_0_s1_chipselect : out std_logic; -- chipselect
onchip_memory2_0_s1_clken : out std_logic; -- clken
pio_0_s1_address : out std_logic_vector(1 downto 0); -- address
pio_0_s1_write : out std_logic; -- write
pio_0_s1_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
pio_0_s1_writedata : out std_logic_vector(31 downto 0); -- writedata
pio_0_s1_chipselect : out std_logic; -- chipselect
sdram_controller_0_s1_address : out std_logic_vector(23 downto 0); -- address
sdram_controller_0_s1_write : out std_logic; -- write
sdram_controller_0_s1_read : out std_logic; -- read
sdram_controller_0_s1_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata
sdram_controller_0_s1_writedata : out std_logic_vector(15 downto 0); -- writedata
sdram_controller_0_s1_byteenable : out std_logic_vector(1 downto 0); -- byteenable
sdram_controller_0_s1_readdatavalid : in std_logic := 'X'; -- readdatavalid
sdram_controller_0_s1_waitrequest : in std_logic := 'X'; -- waitrequest
sdram_controller_0_s1_chipselect : out std_logic -- chipselect
);
end component niosii_mm_interconnect_0;
component niosii_irq_mapper is
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
receiver0_irq : in std_logic := 'X'; -- irq
sender_irq : out std_logic_vector(31 downto 0) -- irq
);
end component niosii_irq_mapper;
component altera_irq_clock_crosser is
generic (
IRQ_WIDTH : integer := 1
);
port (
receiver_clk : in std_logic := 'X'; -- clk
sender_clk : in std_logic := 'X'; -- clk
receiver_reset : in std_logic := 'X'; -- reset
sender_reset : in std_logic := 'X'; -- reset
receiver_irq : in std_logic_vector(0 downto 0) := (others => 'X'); -- irq
sender_irq : out std_logic_vector(0 downto 0) -- irq
);
end component altera_irq_clock_crosser;
component niosii_rst_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component niosii_rst_controller;
component niosii_rst_controller_001 is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component niosii_rst_controller_001;
signal sys_sdram_pll_0_sys_clk_clk : std_logic; -- sys_sdram_pll_0:sys_clk_clk -> [irq_mapper:clk, irq_synchronizer:sender_clk, mm_interconnect_0:sys_sdram_pll_0_sys_clk_clk, nios2_gen2_0:clk, onchip_memory2_0:clk, pio_0:clk, rst_controller_001:clk, sdram_controller_0:clk]
signal nios2_gen2_0_data_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_data_master_readdata -> nios2_gen2_0:d_readdata
signal nios2_gen2_0_data_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_data_master_waitrequest -> nios2_gen2_0:d_waitrequest
signal nios2_gen2_0_data_master_debugaccess : std_logic; -- nios2_gen2_0:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_gen2_0_data_master_debugaccess
signal nios2_gen2_0_data_master_address : std_logic_vector(26 downto 0); -- nios2_gen2_0:d_address -> mm_interconnect_0:nios2_gen2_0_data_master_address
signal nios2_gen2_0_data_master_byteenable : std_logic_vector(3 downto 0); -- nios2_gen2_0:d_byteenable -> mm_interconnect_0:nios2_gen2_0_data_master_byteenable
signal nios2_gen2_0_data_master_read : std_logic; -- nios2_gen2_0:d_read -> mm_interconnect_0:nios2_gen2_0_data_master_read
signal nios2_gen2_0_data_master_write : std_logic; -- nios2_gen2_0:d_write -> mm_interconnect_0:nios2_gen2_0_data_master_write
signal nios2_gen2_0_data_master_writedata : std_logic_vector(31 downto 0); -- nios2_gen2_0:d_writedata -> mm_interconnect_0:nios2_gen2_0_data_master_writedata
signal nios2_gen2_0_instruction_master_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_instruction_master_readdata -> nios2_gen2_0:i_readdata
signal nios2_gen2_0_instruction_master_waitrequest : std_logic; -- mm_interconnect_0:nios2_gen2_0_instruction_master_waitrequest -> nios2_gen2_0:i_waitrequest
signal nios2_gen2_0_instruction_master_address : std_logic_vector(26 downto 0); -- nios2_gen2_0:i_address -> mm_interconnect_0:nios2_gen2_0_instruction_master_address
signal nios2_gen2_0_instruction_master_read : std_logic; -- nios2_gen2_0:i_read -> mm_interconnect_0:nios2_gen2_0_instruction_master_read
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect : std_logic; -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_chipselect -> jtag_uart_0:av_chipselect
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata : std_logic_vector(31 downto 0); -- jtag_uart_0:av_readdata -> mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_readdata
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest : std_logic; -- jtag_uart_0:av_waitrequest -> mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_waitrequest
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address : std_logic_vector(0 downto 0); -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_address -> jtag_uart_0:av_address
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read : std_logic; -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_read -> mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read:in
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write : std_logic; -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_write -> mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write:in
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_writedata -> jtag_uart_0:av_writedata
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata : std_logic_vector(31 downto 0); -- nios2_gen2_0:debug_mem_slave_readdata -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_readdata
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest : std_logic; -- nios2_gen2_0:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_waitrequest
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_debugaccess -> nios2_gen2_0:debug_mem_slave_debugaccess
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address : std_logic_vector(8 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_address -> nios2_gen2_0:debug_mem_slave_address
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_read -> nios2_gen2_0:debug_mem_slave_read
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_byteenable -> nios2_gen2_0:debug_mem_slave_byteenable
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write : std_logic; -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_write -> nios2_gen2_0:debug_mem_slave_write
signal mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:nios2_gen2_0_debug_mem_slave_writedata -> nios2_gen2_0:debug_mem_slave_writedata
signal mm_interconnect_0_onchip_memory2_0_s1_chipselect : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect
signal mm_interconnect_0_onchip_memory2_0_s1_readdata : std_logic_vector(31 downto 0); -- onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata
signal mm_interconnect_0_onchip_memory2_0_s1_address : std_logic_vector(13 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address
signal mm_interconnect_0_onchip_memory2_0_s1_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable
signal mm_interconnect_0_onchip_memory2_0_s1_write : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write
signal mm_interconnect_0_onchip_memory2_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata
signal mm_interconnect_0_onchip_memory2_0_s1_clken : std_logic; -- mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken
signal mm_interconnect_0_pio_0_s1_chipselect : std_logic; -- mm_interconnect_0:pio_0_s1_chipselect -> pio_0:chipselect
signal mm_interconnect_0_pio_0_s1_readdata : std_logic_vector(31 downto 0); -- pio_0:readdata -> mm_interconnect_0:pio_0_s1_readdata
signal mm_interconnect_0_pio_0_s1_address : std_logic_vector(1 downto 0); -- mm_interconnect_0:pio_0_s1_address -> pio_0:address
signal mm_interconnect_0_pio_0_s1_write : std_logic; -- mm_interconnect_0:pio_0_s1_write -> mm_interconnect_0_pio_0_s1_write:in
signal mm_interconnect_0_pio_0_s1_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:pio_0_s1_writedata -> pio_0:writedata
signal mm_interconnect_0_sdram_controller_0_s1_chipselect : std_logic; -- mm_interconnect_0:sdram_controller_0_s1_chipselect -> sdram_controller_0:az_cs
signal mm_interconnect_0_sdram_controller_0_s1_readdata : std_logic_vector(15 downto 0); -- sdram_controller_0:za_data -> mm_interconnect_0:sdram_controller_0_s1_readdata
signal mm_interconnect_0_sdram_controller_0_s1_waitrequest : std_logic; -- sdram_controller_0:za_waitrequest -> mm_interconnect_0:sdram_controller_0_s1_waitrequest
signal mm_interconnect_0_sdram_controller_0_s1_address : std_logic_vector(23 downto 0); -- mm_interconnect_0:sdram_controller_0_s1_address -> sdram_controller_0:az_addr
signal mm_interconnect_0_sdram_controller_0_s1_read : std_logic; -- mm_interconnect_0:sdram_controller_0_s1_read -> mm_interconnect_0_sdram_controller_0_s1_read:in
signal mm_interconnect_0_sdram_controller_0_s1_byteenable : std_logic_vector(1 downto 0); -- mm_interconnect_0:sdram_controller_0_s1_byteenable -> mm_interconnect_0_sdram_controller_0_s1_byteenable:in
signal mm_interconnect_0_sdram_controller_0_s1_readdatavalid : std_logic; -- sdram_controller_0:za_valid -> mm_interconnect_0:sdram_controller_0_s1_readdatavalid
signal mm_interconnect_0_sdram_controller_0_s1_write : std_logic; -- mm_interconnect_0:sdram_controller_0_s1_write -> mm_interconnect_0_sdram_controller_0_s1_write:in
signal mm_interconnect_0_sdram_controller_0_s1_writedata : std_logic_vector(15 downto 0); -- mm_interconnect_0:sdram_controller_0_s1_writedata -> sdram_controller_0:az_data
signal nios2_gen2_0_irq_irq : std_logic_vector(31 downto 0); -- irq_mapper:sender_irq -> nios2_gen2_0:irq
signal irq_mapper_receiver0_irq : std_logic; -- irq_synchronizer:sender_irq -> irq_mapper:receiver0_irq
signal irq_synchronizer_receiver_irq : std_logic_vector(0 downto 0); -- jtag_uart_0:av_irq -> irq_synchronizer:receiver_irq
signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> [irq_synchronizer:receiver_reset, mm_interconnect_0:jtag_uart_0_reset_reset_bridge_in_reset_reset, rst_controller_reset_out_reset:in, sys_sdram_pll_0:ref_reset_reset]
signal rst_controller_001_reset_out_reset : std_logic; -- rst_controller_001:reset_out -> [irq_mapper:reset, irq_synchronizer:sender_reset, mm_interconnect_0:nios2_gen2_0_reset_reset_bridge_in_reset_reset, onchip_memory2_0:reset, rst_controller_001_reset_out_reset:in, rst_translator:in_reset]
signal rst_controller_001_reset_out_reset_req : std_logic; -- rst_controller_001:reset_req -> [nios2_gen2_0:reset_req, onchip_memory2_0:reset_req, rst_translator:reset_req_in]
signal reset_reset_n_ports_inv : std_logic; -- reset_reset_n:inv -> [rst_controller:reset_in0, rst_controller_001:reset_in0]
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read_ports_inv : std_logic; -- mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read:inv -> jtag_uart_0:av_read_n
signal mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write_ports_inv : std_logic; -- mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write:inv -> jtag_uart_0:av_write_n
signal mm_interconnect_0_pio_0_s1_write_ports_inv : std_logic; -- mm_interconnect_0_pio_0_s1_write:inv -> pio_0:write_n
signal mm_interconnect_0_sdram_controller_0_s1_read_ports_inv : std_logic; -- mm_interconnect_0_sdram_controller_0_s1_read:inv -> sdram_controller_0:az_rd_n
signal mm_interconnect_0_sdram_controller_0_s1_byteenable_ports_inv : std_logic_vector(1 downto 0); -- mm_interconnect_0_sdram_controller_0_s1_byteenable:inv -> sdram_controller_0:az_be_n
signal mm_interconnect_0_sdram_controller_0_s1_write_ports_inv : std_logic; -- mm_interconnect_0_sdram_controller_0_s1_write:inv -> sdram_controller_0:az_wr_n
signal rst_controller_reset_out_reset_ports_inv : std_logic; -- rst_controller_reset_out_reset:inv -> jtag_uart_0:rst_n
signal rst_controller_001_reset_out_reset_ports_inv : std_logic; -- rst_controller_001_reset_out_reset:inv -> [nios2_gen2_0:reset_n, pio_0:reset_n, sdram_controller_0:reset_n]
begin
jtag_uart_0 : component niosii_jtag_uart_0
port map (
clk => clk_clk, -- clk.clk
rst_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n
av_chipselect => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect, -- avalon_jtag_slave.chipselect
av_address => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address(0), -- .address
av_read_n => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read_ports_inv, -- .read_n
av_readdata => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata, -- .readdata
av_write_n => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write_ports_inv, -- .write_n
av_writedata => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata, -- .writedata
av_waitrequest => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest, -- .waitrequest
av_irq => irq_synchronizer_receiver_irq(0) -- irq.irq
);
nios2_gen2_0 : component niosii_nios2_gen2_0
port map (
clk => sys_sdram_pll_0_sys_clk_clk, -- clk.clk
reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n
reset_req => rst_controller_001_reset_out_reset_req, -- .reset_req
d_address => nios2_gen2_0_data_master_address, -- data_master.address
d_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable
d_read => nios2_gen2_0_data_master_read, -- .read
d_readdata => nios2_gen2_0_data_master_readdata, -- .readdata
d_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest
d_write => nios2_gen2_0_data_master_write, -- .write
d_writedata => nios2_gen2_0_data_master_writedata, -- .writedata
debug_mem_slave_debugaccess_to_roms => nios2_gen2_0_data_master_debugaccess, -- .debugaccess
i_address => nios2_gen2_0_instruction_master_address, -- instruction_master.address
i_read => nios2_gen2_0_instruction_master_read, -- .read
i_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata
i_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest
irq => nios2_gen2_0_irq_irq, -- irq.irq
debug_reset_request => open, -- debug_reset_request.reset
debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- debug_mem_slave.address
debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable
debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess
debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read
debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata
debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest
debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write
debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata
dummy_ci_port => open -- custom_instruction_master.readra
);
onchip_memory2_0 : component niosii_onchip_memory2_0
port map (
clk => sys_sdram_pll_0_sys_clk_clk, -- clk1.clk
address => mm_interconnect_0_onchip_memory2_0_s1_address, -- s1.address
clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken
chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect
write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write
readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata
writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata
byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable
reset => rst_controller_001_reset_out_reset, -- reset1.reset
reset_req => rst_controller_001_reset_out_reset_req -- .reset_req
);
pio_0 : component niosii_pio_0
port map (
clk => sys_sdram_pll_0_sys_clk_clk, -- clk.clk
reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n
address => mm_interconnect_0_pio_0_s1_address, -- s1.address
write_n => mm_interconnect_0_pio_0_s1_write_ports_inv, -- .write_n
writedata => mm_interconnect_0_pio_0_s1_writedata, -- .writedata
chipselect => mm_interconnect_0_pio_0_s1_chipselect, -- .chipselect
readdata => mm_interconnect_0_pio_0_s1_readdata, -- .readdata
out_port => pio_0_external_connection_export -- external_connection.export
);
sdram_controller_0 : component niosii_sdram_controller_0
port map (
clk => sys_sdram_pll_0_sys_clk_clk, -- clk.clk
reset_n => rst_controller_001_reset_out_reset_ports_inv, -- reset.reset_n
az_addr => mm_interconnect_0_sdram_controller_0_s1_address, -- s1.address
az_be_n => mm_interconnect_0_sdram_controller_0_s1_byteenable_ports_inv, -- .byteenable_n
az_cs => mm_interconnect_0_sdram_controller_0_s1_chipselect, -- .chipselect
az_data => mm_interconnect_0_sdram_controller_0_s1_writedata, -- .writedata
az_rd_n => mm_interconnect_0_sdram_controller_0_s1_read_ports_inv, -- .read_n
az_wr_n => mm_interconnect_0_sdram_controller_0_s1_write_ports_inv, -- .write_n
za_data => mm_interconnect_0_sdram_controller_0_s1_readdata, -- .readdata
za_valid => mm_interconnect_0_sdram_controller_0_s1_readdatavalid, -- .readdatavalid
za_waitrequest => mm_interconnect_0_sdram_controller_0_s1_waitrequest, -- .waitrequest
zs_addr => sdram_addr, -- wire.export
zs_ba => sdram_ba, -- .export
zs_cas_n => sdram_cas_n, -- .export
zs_cke => sdram_cke, -- .export
zs_cs_n => sdram_cs_n, -- .export
zs_dq => sdram_dq, -- .export
zs_dqm => sdram_dqm, -- .export
zs_ras_n => sdram_ras_n, -- .export
zs_we_n => sdram_we_n -- .export
);
sys_sdram_pll_0 : component niosii_sys_sdram_pll_0
port map (
ref_clk_clk => clk_clk, -- ref_clk.clk
ref_reset_reset => rst_controller_reset_out_reset, -- ref_reset.reset
sys_clk_clk => sys_sdram_pll_0_sys_clk_clk, -- sys_clk.clk
sdram_clk_clk => sdram_clk_clk, -- sdram_clk.clk
reset_source_reset => open -- reset_source.reset
);
mm_interconnect_0 : component niosii_mm_interconnect_0
port map (
clk_0_clk_clk => clk_clk, -- clk_0_clk.clk
sys_sdram_pll_0_sys_clk_clk => sys_sdram_pll_0_sys_clk_clk, -- sys_sdram_pll_0_sys_clk.clk
jtag_uart_0_reset_reset_bridge_in_reset_reset => rst_controller_reset_out_reset, -- jtag_uart_0_reset_reset_bridge_in_reset.reset
nios2_gen2_0_reset_reset_bridge_in_reset_reset => rst_controller_001_reset_out_reset, -- nios2_gen2_0_reset_reset_bridge_in_reset.reset
nios2_gen2_0_data_master_address => nios2_gen2_0_data_master_address, -- nios2_gen2_0_data_master.address
nios2_gen2_0_data_master_waitrequest => nios2_gen2_0_data_master_waitrequest, -- .waitrequest
nios2_gen2_0_data_master_byteenable => nios2_gen2_0_data_master_byteenable, -- .byteenable
nios2_gen2_0_data_master_read => nios2_gen2_0_data_master_read, -- .read
nios2_gen2_0_data_master_readdata => nios2_gen2_0_data_master_readdata, -- .readdata
nios2_gen2_0_data_master_write => nios2_gen2_0_data_master_write, -- .write
nios2_gen2_0_data_master_writedata => nios2_gen2_0_data_master_writedata, -- .writedata
nios2_gen2_0_data_master_debugaccess => nios2_gen2_0_data_master_debugaccess, -- .debugaccess
nios2_gen2_0_instruction_master_address => nios2_gen2_0_instruction_master_address, -- nios2_gen2_0_instruction_master.address
nios2_gen2_0_instruction_master_waitrequest => nios2_gen2_0_instruction_master_waitrequest, -- .waitrequest
nios2_gen2_0_instruction_master_read => nios2_gen2_0_instruction_master_read, -- .read
nios2_gen2_0_instruction_master_readdata => nios2_gen2_0_instruction_master_readdata, -- .readdata
jtag_uart_0_avalon_jtag_slave_address => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address, -- jtag_uart_0_avalon_jtag_slave.address
jtag_uart_0_avalon_jtag_slave_write => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write, -- .write
jtag_uart_0_avalon_jtag_slave_read => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read, -- .read
jtag_uart_0_avalon_jtag_slave_readdata => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata, -- .readdata
jtag_uart_0_avalon_jtag_slave_writedata => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata, -- .writedata
jtag_uart_0_avalon_jtag_slave_waitrequest => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest, -- .waitrequest
jtag_uart_0_avalon_jtag_slave_chipselect => mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect, -- .chipselect
nios2_gen2_0_debug_mem_slave_address => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address, -- nios2_gen2_0_debug_mem_slave.address
nios2_gen2_0_debug_mem_slave_write => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write, -- .write
nios2_gen2_0_debug_mem_slave_read => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read, -- .read
nios2_gen2_0_debug_mem_slave_readdata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata, -- .readdata
nios2_gen2_0_debug_mem_slave_writedata => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata, -- .writedata
nios2_gen2_0_debug_mem_slave_byteenable => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable, -- .byteenable
nios2_gen2_0_debug_mem_slave_waitrequest => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest, -- .waitrequest
nios2_gen2_0_debug_mem_slave_debugaccess => mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess, -- .debugaccess
onchip_memory2_0_s1_address => mm_interconnect_0_onchip_memory2_0_s1_address, -- onchip_memory2_0_s1.address
onchip_memory2_0_s1_write => mm_interconnect_0_onchip_memory2_0_s1_write, -- .write
onchip_memory2_0_s1_readdata => mm_interconnect_0_onchip_memory2_0_s1_readdata, -- .readdata
onchip_memory2_0_s1_writedata => mm_interconnect_0_onchip_memory2_0_s1_writedata, -- .writedata
onchip_memory2_0_s1_byteenable => mm_interconnect_0_onchip_memory2_0_s1_byteenable, -- .byteenable
onchip_memory2_0_s1_chipselect => mm_interconnect_0_onchip_memory2_0_s1_chipselect, -- .chipselect
onchip_memory2_0_s1_clken => mm_interconnect_0_onchip_memory2_0_s1_clken, -- .clken
pio_0_s1_address => mm_interconnect_0_pio_0_s1_address, -- pio_0_s1.address
pio_0_s1_write => mm_interconnect_0_pio_0_s1_write, -- .write
pio_0_s1_readdata => mm_interconnect_0_pio_0_s1_readdata, -- .readdata
pio_0_s1_writedata => mm_interconnect_0_pio_0_s1_writedata, -- .writedata
pio_0_s1_chipselect => mm_interconnect_0_pio_0_s1_chipselect, -- .chipselect
sdram_controller_0_s1_address => mm_interconnect_0_sdram_controller_0_s1_address, -- sdram_controller_0_s1.address
sdram_controller_0_s1_write => mm_interconnect_0_sdram_controller_0_s1_write, -- .write
sdram_controller_0_s1_read => mm_interconnect_0_sdram_controller_0_s1_read, -- .read
sdram_controller_0_s1_readdata => mm_interconnect_0_sdram_controller_0_s1_readdata, -- .readdata
sdram_controller_0_s1_writedata => mm_interconnect_0_sdram_controller_0_s1_writedata, -- .writedata
sdram_controller_0_s1_byteenable => mm_interconnect_0_sdram_controller_0_s1_byteenable, -- .byteenable
sdram_controller_0_s1_readdatavalid => mm_interconnect_0_sdram_controller_0_s1_readdatavalid, -- .readdatavalid
sdram_controller_0_s1_waitrequest => mm_interconnect_0_sdram_controller_0_s1_waitrequest, -- .waitrequest
sdram_controller_0_s1_chipselect => mm_interconnect_0_sdram_controller_0_s1_chipselect -- .chipselect
);
irq_mapper : component niosii_irq_mapper
port map (
clk => sys_sdram_pll_0_sys_clk_clk, -- clk.clk
reset => rst_controller_001_reset_out_reset, -- clk_reset.reset
receiver0_irq => irq_mapper_receiver0_irq, -- receiver0.irq
sender_irq => nios2_gen2_0_irq_irq -- sender.irq
);
irq_synchronizer : component altera_irq_clock_crosser
generic map (
IRQ_WIDTH => 1
)
port map (
receiver_clk => clk_clk, -- receiver_clk.clk
sender_clk => sys_sdram_pll_0_sys_clk_clk, -- sender_clk.clk
receiver_reset => rst_controller_reset_out_reset, -- receiver_clk_reset.reset
sender_reset => rst_controller_001_reset_out_reset, -- sender_clk_reset.reset
receiver_irq => irq_synchronizer_receiver_irq, -- receiver.irq
sender_irq(0) => irq_mapper_receiver0_irq -- sender.irq
);
rst_controller : component niosii_rst_controller
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 0,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
clk => clk_clk, -- clk.clk
reset_out => rst_controller_reset_out_reset, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
rst_controller_001 : component niosii_rst_controller_001
generic map (
NUM_RESET_INPUTS => 1,
OUTPUT_RESET_SYNC_EDGES => "deassert",
SYNC_DEPTH => 2,
RESET_REQUEST_PRESENT => 1,
RESET_REQ_WAIT_TIME => 1,
MIN_RST_ASSERTION_TIME => 3,
RESET_REQ_EARLY_DSRT_TIME => 1,
USE_RESET_REQUEST_IN0 => 0,
USE_RESET_REQUEST_IN1 => 0,
USE_RESET_REQUEST_IN2 => 0,
USE_RESET_REQUEST_IN3 => 0,
USE_RESET_REQUEST_IN4 => 0,
USE_RESET_REQUEST_IN5 => 0,
USE_RESET_REQUEST_IN6 => 0,
USE_RESET_REQUEST_IN7 => 0,
USE_RESET_REQUEST_IN8 => 0,
USE_RESET_REQUEST_IN9 => 0,
USE_RESET_REQUEST_IN10 => 0,
USE_RESET_REQUEST_IN11 => 0,
USE_RESET_REQUEST_IN12 => 0,
USE_RESET_REQUEST_IN13 => 0,
USE_RESET_REQUEST_IN14 => 0,
USE_RESET_REQUEST_IN15 => 0,
ADAPT_RESET_REQUEST => 0
)
port map (
reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset
clk => sys_sdram_pll_0_sys_clk_clk, -- clk.clk
reset_out => rst_controller_001_reset_out_reset, -- reset_out.reset
reset_req => rst_controller_001_reset_out_reset_req, -- .reset_req
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
reset_reset_n_ports_inv <= not reset_reset_n;
mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read_ports_inv <= not mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read;
mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write_ports_inv <= not mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write;
mm_interconnect_0_pio_0_s1_write_ports_inv <= not mm_interconnect_0_pio_0_s1_write;
mm_interconnect_0_sdram_controller_0_s1_read_ports_inv <= not mm_interconnect_0_sdram_controller_0_s1_read;
mm_interconnect_0_sdram_controller_0_s1_byteenable_ports_inv <= not mm_interconnect_0_sdram_controller_0_s1_byteenable;
mm_interconnect_0_sdram_controller_0_s1_write_ports_inv <= not mm_interconnect_0_sdram_controller_0_s1_write;
rst_controller_reset_out_reset_ports_inv <= not rst_controller_reset_out_reset;
rst_controller_001_reset_out_reset_ports_inv <= not rst_controller_001_reset_out_reset;
end architecture rtl; -- of niosii
|
mit
|
chcbaram/Altera_DE0_nano_Exam
|
prj_niosii_pll/niosii/synthesis/niosii_rst_controller.vhd
|
6
|
9023
|
-- niosii_rst_controller.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity niosii_rst_controller is
generic (
NUM_RESET_INPUTS : integer := 1;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := '0'; -- reset_in0.reset
clk : in std_logic := '0'; -- clk.clk
reset_out : out std_logic; -- reset_out.reset
reset_in1 : in std_logic := '0';
reset_in10 : in std_logic := '0';
reset_in11 : in std_logic := '0';
reset_in12 : in std_logic := '0';
reset_in13 : in std_logic := '0';
reset_in14 : in std_logic := '0';
reset_in15 : in std_logic := '0';
reset_in2 : in std_logic := '0';
reset_in3 : in std_logic := '0';
reset_in4 : in std_logic := '0';
reset_in5 : in std_logic := '0';
reset_in6 : in std_logic := '0';
reset_in7 : in std_logic := '0';
reset_in8 : in std_logic := '0';
reset_in9 : in std_logic := '0';
reset_req : out std_logic;
reset_req_in0 : in std_logic := '0';
reset_req_in1 : in std_logic := '0';
reset_req_in10 : in std_logic := '0';
reset_req_in11 : in std_logic := '0';
reset_req_in12 : in std_logic := '0';
reset_req_in13 : in std_logic := '0';
reset_req_in14 : in std_logic := '0';
reset_req_in15 : in std_logic := '0';
reset_req_in2 : in std_logic := '0';
reset_req_in3 : in std_logic := '0';
reset_req_in4 : in std_logic := '0';
reset_req_in5 : in std_logic := '0';
reset_req_in6 : in std_logic := '0';
reset_req_in7 : in std_logic := '0';
reset_req_in8 : in std_logic := '0';
reset_req_in9 : in std_logic := '0'
);
end entity niosii_rst_controller;
architecture rtl of niosii_rst_controller is
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component altera_reset_controller;
begin
rst_controller : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => NUM_RESET_INPUTS,
OUTPUT_RESET_SYNC_EDGES => OUTPUT_RESET_SYNC_EDGES,
SYNC_DEPTH => SYNC_DEPTH,
RESET_REQUEST_PRESENT => RESET_REQUEST_PRESENT,
RESET_REQ_WAIT_TIME => RESET_REQ_WAIT_TIME,
MIN_RST_ASSERTION_TIME => MIN_RST_ASSERTION_TIME,
RESET_REQ_EARLY_DSRT_TIME => RESET_REQ_EARLY_DSRT_TIME,
USE_RESET_REQUEST_IN0 => USE_RESET_REQUEST_IN0,
USE_RESET_REQUEST_IN1 => USE_RESET_REQUEST_IN1,
USE_RESET_REQUEST_IN2 => USE_RESET_REQUEST_IN2,
USE_RESET_REQUEST_IN3 => USE_RESET_REQUEST_IN3,
USE_RESET_REQUEST_IN4 => USE_RESET_REQUEST_IN4,
USE_RESET_REQUEST_IN5 => USE_RESET_REQUEST_IN5,
USE_RESET_REQUEST_IN6 => USE_RESET_REQUEST_IN6,
USE_RESET_REQUEST_IN7 => USE_RESET_REQUEST_IN7,
USE_RESET_REQUEST_IN8 => USE_RESET_REQUEST_IN8,
USE_RESET_REQUEST_IN9 => USE_RESET_REQUEST_IN9,
USE_RESET_REQUEST_IN10 => USE_RESET_REQUEST_IN10,
USE_RESET_REQUEST_IN11 => USE_RESET_REQUEST_IN11,
USE_RESET_REQUEST_IN12 => USE_RESET_REQUEST_IN12,
USE_RESET_REQUEST_IN13 => USE_RESET_REQUEST_IN13,
USE_RESET_REQUEST_IN14 => USE_RESET_REQUEST_IN14,
USE_RESET_REQUEST_IN15 => USE_RESET_REQUEST_IN15,
ADAPT_RESET_REQUEST => ADAPT_RESET_REQUEST
)
port map (
reset_in0 => reset_in0, -- reset_in0.reset
clk => clk, -- clk.clk
reset_out => reset_out, -- reset_out.reset
reset_req => open, -- (terminated)
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
end architecture rtl; -- of niosii_rst_controller
|
mit
|
chcbaram/Altera_DE0_nano_Exam
|
prj_niosii_abot/niosii_top.vhd
|
1
|
4372
|
----------------------------------------------------------------------------------
-- Design Name : led_top
-- Create Date : 2015/12/31
-- Module Name :
-- Project Name :
-- Target Devices:
-- Tool Versions :
-- Description :
-- Revision :
-- Additional Comments:
--
----------------------------------------------------------------------------------
--The MIT License (MIT)
--
--Copyright (c) 2015
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
----------------------------------------------------------------------------------
-- Library Define
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
entity niosii_top is
Port (
p_clk_50Mhz : in std_logic;
p_button : in std_logic_vector( 1 downto 0 );
p_led_out : out std_logic_vector( 7 downto 0 );
p_pwm_dir : out std_logic_vector(1 downto 0);
p_pwm_out : out std_logic_vector(1 downto 0);
p_uart_0_rxd : in std_logic;
p_uart_0_txd : out std_logic;
p_epcs_flash_dclk : out std_logic;
p_epcs_flash_sce : out std_logic;
p_epcs_flash_sdo : out std_logic;
p_epcs_flash_data0 : in std_logic
);
end niosii_top;
architecture Behavioral of niosii_top is
component niosii is
port (
clk_clk : in std_logic := 'X'; -- clk
pio_0_external_connection_export : out std_logic_vector(7 downto 0); -- export
reset_reset_n : in std_logic := 'X'; -- reset_n
uart_0_rxd : in std_logic := 'X'; -- rxd
uart_0_txd : out std_logic; -- txd
ip_pwm_dir : out std_logic_vector(1 downto 0); -- dir
ip_pwm_out : out std_logic_vector(1 downto 0); -- out
epcs_flash_dclk : out std_logic; -- dclk
epcs_flash_sce : out std_logic; -- sce
epcs_flash_sdo : out std_logic; -- sdo
epcs_flash_data0 : in std_logic := 'X' -- data0
);
end component niosii;
signal s_reset_n : std_logic;
begin
s_reset_n <= p_button(0);
u0 : component niosii
port map (
clk_clk => p_clk_50Mhz,
pio_0_external_connection_export => p_led_out,
reset_reset_n => s_reset_n,
uart_0_rxd => p_uart_0_rxd,
uart_0_txd => p_uart_0_txd,
ip_pwm_dir => p_pwm_dir,
ip_pwm_out => p_pwm_out,
epcs_flash_dclk => p_epcs_flash_dclk,
epcs_flash_sce => p_epcs_flash_sce,
epcs_flash_sdo => p_epcs_flash_sdo,
epcs_flash_data0 => p_epcs_flash_data0
);
end Behavioral;
|
mit
|
chcbaram/Altera_DE0_nano_Exam
|
prj_niosii_abot/niosii/synthesis/submodules/altera_epcq_controller_core.vhd
|
1
|
18709
|
-- altera_epcq_controller_core.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity altera_epcq_controller_core is
generic (
DEVICE_FAMILY : string := "Cyclone IV E";
ADDR_WIDTH : integer := 19;
ASMI_ADDR_WIDTH : integer := 24;
ASI_WIDTH : integer := 1;
CS_WIDTH : integer := 1;
CHIP_SELS : integer := 1;
ENABLE_4BYTE_ADDR : integer := 0
);
port (
clk : in std_logic := '0'; -- clock_sink.clk
reset_n : in std_logic := '0'; -- reset.reset_n
avl_csr_read : in std_logic := '0'; -- avl_csr.read
avl_csr_waitrequest : out std_logic; -- .waitrequest
avl_csr_write : in std_logic := '0'; -- .write
avl_csr_addr : in std_logic_vector(2 downto 0) := (others => '0'); -- .address
avl_csr_wrdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
avl_csr_rddata : out std_logic_vector(31 downto 0); -- .readdata
avl_csr_rddata_valid : out std_logic; -- .readdatavalid
avl_mem_write : in std_logic := '0'; -- avl_mem.write
avl_mem_burstcount : in std_logic_vector(6 downto 0) := (others => '0'); -- .burstcount
avl_mem_waitrequest : out std_logic; -- .waitrequest
avl_mem_read : in std_logic := '0'; -- .read
avl_mem_addr : in std_logic_vector(18 downto 0) := (others => '0'); -- .address
avl_mem_wrdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
avl_mem_rddata : out std_logic_vector(31 downto 0); -- .readdata
avl_mem_rddata_valid : out std_logic; -- .readdatavalid
avl_mem_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
asmi_status_out : in std_logic_vector(7 downto 0) := (others => '0'); -- asmi_status_out.conduit_status_out
asmi_epcs_id : in std_logic_vector(7 downto 0) := (others => '0'); -- asmi_epcs_id.conduit_epcs_id
asmi_illegal_erase : in std_logic := '0'; -- asmi_illegal_erase.conduit_illegal_erase
asmi_illegal_write : in std_logic := '0'; -- asmi_illegal_write.conduit_illegal_write
ddasi_dataoe : in std_logic_vector(0 downto 0) := (others => '0'); -- ddasi_dataoe.conduit_ddasi_dataoe
ddasi_dclk : in std_logic := '0'; -- ddasi_dclk.conduit_ddasi_dclk
ddasi_scein : in std_logic_vector(0 downto 0) := (others => '0'); -- ddasi_scein.conduit_ddasi_scein
ddasi_sdoin : in std_logic_vector(0 downto 0) := (others => '0'); -- ddasi_sdoin.conduit_ddasi_sdoin
asmi_busy : in std_logic := '0'; -- asmi_busy.conduit_busy
asmi_data_valid : in std_logic := '0'; -- asmi_data_valid.conduit_data_valid
asmi_dataout : in std_logic_vector(7 downto 0) := (others => '0'); -- asmi_dataout.conduit_dataout
epcq_dataout : in std_logic_vector(0 downto 0) := (others => '0'); -- epcq_dataout.conduit_epcq_dataout
ddasi_dataout : out std_logic_vector(0 downto 0); -- ddasi_dataout.conduit_ddasi_dataout
asmi_read_rdid : out std_logic; -- asmi_read_rdid.conduit_read_rdid
asmi_read_status : out std_logic; -- asmi_read_status.conduit_read_status
asmi_read_sid : out std_logic; -- asmi_read_sid.conduit_read_sid
asmi_bulk_erase : out std_logic; -- asmi_bulk_erase.conduit_bulk_erase
asmi_sector_erase : out std_logic; -- asmi_sector_erase.conduit_sector_erase
asmi_sector_protect : out std_logic; -- asmi_sector_protect.conduit_sector_protect
epcq_dclk : out std_logic; -- epcq_dclk.conduit_epcq_dclk
epcq_scein : out std_logic_vector(0 downto 0); -- epcq_scein.conduit_epcq_scein
epcq_sdoin : out std_logic_vector(0 downto 0); -- epcq_sdoin.conduit_epcq_sdoin
epcq_dataoe : out std_logic_vector(0 downto 0); -- epcq_dataoe.conduit_epcq_dataoe
asmi_clkin : out std_logic; -- asmi_clkin.conduit_clkin
asmi_reset : out std_logic; -- asmi_reset.conduit_reset
asmi_sce : out std_logic_vector(0 downto 0); -- asmi_sce.conduit_asmi_sce
asmi_addr : out std_logic_vector(23 downto 0); -- asmi_addr.conduit_addr
asmi_datain : out std_logic_vector(7 downto 0); -- asmi_datain.conduit_datain
asmi_fast_read : out std_logic; -- asmi_fast_read.conduit_fast_read
asmi_rden : out std_logic; -- asmi_rden.conduit_rden
asmi_shift_bytes : out std_logic; -- asmi_shift_bytes.conduit_shift_bytes
asmi_wren : out std_logic; -- asmi_wren.conduit_wren
asmi_write : out std_logic; -- asmi_write.conduit_write
asmi_rdid_out : in std_logic_vector(7 downto 0) := (others => '0'); -- asmi_rdid_out.conduit_rdid_out
asmi_en4b_addr : out std_logic; -- asmi_en4b_addr.conduit_en4b_addr
irq : out std_logic -- interrupt_sender.irq
);
end entity altera_epcq_controller_core;
architecture rtl of altera_epcq_controller_core is
component altera_epcq_controller_arb is
generic (
DEVICE_FAMILY : string := "";
ADDR_WIDTH : integer := 19;
ASMI_ADDR_WIDTH : integer := 24;
ASI_WIDTH : integer := 1;
CS_WIDTH : integer := 1;
CHIP_SELS : integer := 1;
ENABLE_4BYTE_ADDR : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
avl_csr_read : in std_logic := 'X'; -- read
avl_csr_waitrequest : out std_logic; -- waitrequest
avl_csr_write : in std_logic := 'X'; -- write
avl_csr_addr : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
avl_csr_wrdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
avl_csr_rddata : out std_logic_vector(31 downto 0); -- readdata
avl_csr_rddata_valid : out std_logic; -- readdatavalid
avl_mem_write : in std_logic := 'X'; -- write
avl_mem_burstcount : in std_logic_vector(6 downto 0) := (others => 'X'); -- burstcount
avl_mem_waitrequest : out std_logic; -- waitrequest
avl_mem_read : in std_logic := 'X'; -- read
avl_mem_addr : in std_logic_vector(18 downto 0) := (others => 'X'); -- address
avl_mem_wrdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
avl_mem_rddata : out std_logic_vector(31 downto 0); -- readdata
avl_mem_rddata_valid : out std_logic; -- readdatavalid
avl_mem_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
asmi_status_out : in std_logic_vector(7 downto 0) := (others => 'X'); -- conduit_status_out
asmi_epcs_id : in std_logic_vector(7 downto 0) := (others => 'X'); -- conduit_epcs_id
asmi_illegal_erase : in std_logic := 'X'; -- conduit_illegal_erase
asmi_illegal_write : in std_logic := 'X'; -- conduit_illegal_write
ddasi_dataoe : in std_logic_vector(0 downto 0) := (others => 'X'); -- conduit_ddasi_dataoe
ddasi_dclk : in std_logic := 'X'; -- conduit_ddasi_dclk
ddasi_scein : in std_logic_vector(0 downto 0) := (others => 'X'); -- conduit_ddasi_scein
ddasi_sdoin : in std_logic_vector(0 downto 0) := (others => 'X'); -- conduit_ddasi_sdoin
asmi_busy : in std_logic := 'X'; -- conduit_busy
asmi_data_valid : in std_logic := 'X'; -- conduit_data_valid
asmi_dataout : in std_logic_vector(7 downto 0) := (others => 'X'); -- conduit_dataout
epcq_dataout : in std_logic_vector(0 downto 0) := (others => 'X'); -- conduit_epcq_dataout
ddasi_dataout : out std_logic_vector(0 downto 0); -- conduit_ddasi_dataout
asmi_read_rdid : out std_logic; -- conduit_read_rdid
asmi_read_status : out std_logic; -- conduit_read_status
asmi_read_sid : out std_logic; -- conduit_read_sid
asmi_bulk_erase : out std_logic; -- conduit_bulk_erase
asmi_sector_erase : out std_logic; -- conduit_sector_erase
asmi_sector_protect : out std_logic; -- conduit_sector_protect
epcq_dclk : out std_logic; -- conduit_epcq_dclk
epcq_scein : out std_logic_vector(0 downto 0); -- conduit_epcq_scein
epcq_sdoin : out std_logic_vector(0 downto 0); -- conduit_epcq_sdoin
epcq_dataoe : out std_logic_vector(0 downto 0); -- conduit_epcq_dataoe
asmi_clkin : out std_logic; -- conduit_clkin
asmi_reset : out std_logic; -- conduit_reset
asmi_sce : out std_logic_vector(0 downto 0); -- conduit_asmi_sce
asmi_addr : out std_logic_vector(23 downto 0); -- conduit_addr
asmi_datain : out std_logic_vector(7 downto 0); -- conduit_datain
asmi_fast_read : out std_logic; -- conduit_fast_read
asmi_rden : out std_logic; -- conduit_rden
asmi_shift_bytes : out std_logic; -- conduit_shift_bytes
asmi_wren : out std_logic; -- conduit_wren
asmi_write : out std_logic; -- conduit_write
asmi_rdid_out : in std_logic_vector(7 downto 0) := (others => 'X'); -- conduit_rdid_out
asmi_en4b_addr : out std_logic; -- conduit_en4b_addr
irq : out std_logic -- irq
);
end component altera_epcq_controller_arb;
begin
device_family_check : if DEVICE_FAMILY /= "Cyclone IV E" generate
assert false report "Supplied generics do not match expected generics" severity Failure;
end generate;
addr_width_check : if ADDR_WIDTH /= 19 generate
assert false report "Supplied generics do not match expected generics" severity Failure;
end generate;
asmi_addr_width_check : if ASMI_ADDR_WIDTH /= 24 generate
assert false report "Supplied generics do not match expected generics" severity Failure;
end generate;
asi_width_check : if ASI_WIDTH /= 1 generate
assert false report "Supplied generics do not match expected generics" severity Failure;
end generate;
cs_width_check : if CS_WIDTH /= 1 generate
assert false report "Supplied generics do not match expected generics" severity Failure;
end generate;
chip_sels_check : if CHIP_SELS /= 1 generate
assert false report "Supplied generics do not match expected generics" severity Failure;
end generate;
enable_4byte_addr_check : if ENABLE_4BYTE_ADDR /= 0 generate
assert false report "Supplied generics do not match expected generics" severity Failure;
end generate;
altera_epcq_controller_core : component altera_epcq_controller_arb
generic map (
DEVICE_FAMILY => "Cyclone IV E",
ADDR_WIDTH => 19,
ASMI_ADDR_WIDTH => 24,
ASI_WIDTH => 1,
CS_WIDTH => 1,
CHIP_SELS => 1,
ENABLE_4BYTE_ADDR => 0
)
port map (
clk => clk, -- clock_sink.clk
reset_n => reset_n, -- reset.reset_n
avl_csr_read => avl_csr_read, -- avl_csr.read
avl_csr_waitrequest => avl_csr_waitrequest, -- .waitrequest
avl_csr_write => avl_csr_write, -- .write
avl_csr_addr => avl_csr_addr, -- .address
avl_csr_wrdata => avl_csr_wrdata, -- .writedata
avl_csr_rddata => avl_csr_rddata, -- .readdata
avl_csr_rddata_valid => avl_csr_rddata_valid, -- .readdatavalid
avl_mem_write => avl_mem_write, -- avl_mem.write
avl_mem_burstcount => avl_mem_burstcount, -- .burstcount
avl_mem_waitrequest => avl_mem_waitrequest, -- .waitrequest
avl_mem_read => avl_mem_read, -- .read
avl_mem_addr => avl_mem_addr, -- .address
avl_mem_wrdata => avl_mem_wrdata, -- .writedata
avl_mem_rddata => avl_mem_rddata, -- .readdata
avl_mem_rddata_valid => avl_mem_rddata_valid, -- .readdatavalid
avl_mem_byteenable => avl_mem_byteenable, -- .byteenable
asmi_status_out => asmi_status_out, -- asmi_status_out.conduit_status_out
asmi_epcs_id => asmi_epcs_id, -- asmi_epcs_id.conduit_epcs_id
asmi_illegal_erase => asmi_illegal_erase, -- asmi_illegal_erase.conduit_illegal_erase
asmi_illegal_write => asmi_illegal_write, -- asmi_illegal_write.conduit_illegal_write
ddasi_dataoe => ddasi_dataoe, -- ddasi_dataoe.conduit_ddasi_dataoe
ddasi_dclk => ddasi_dclk, -- ddasi_dclk.conduit_ddasi_dclk
ddasi_scein => ddasi_scein, -- ddasi_scein.conduit_ddasi_scein
ddasi_sdoin => ddasi_sdoin, -- ddasi_sdoin.conduit_ddasi_sdoin
asmi_busy => asmi_busy, -- asmi_busy.conduit_busy
asmi_data_valid => asmi_data_valid, -- asmi_data_valid.conduit_data_valid
asmi_dataout => asmi_dataout, -- asmi_dataout.conduit_dataout
epcq_dataout => epcq_dataout, -- epcq_dataout.conduit_epcq_dataout
ddasi_dataout => ddasi_dataout, -- ddasi_dataout.conduit_ddasi_dataout
asmi_read_rdid => asmi_read_rdid, -- asmi_read_rdid.conduit_read_rdid
asmi_read_status => asmi_read_status, -- asmi_read_status.conduit_read_status
asmi_read_sid => asmi_read_sid, -- asmi_read_sid.conduit_read_sid
asmi_bulk_erase => asmi_bulk_erase, -- asmi_bulk_erase.conduit_bulk_erase
asmi_sector_erase => asmi_sector_erase, -- asmi_sector_erase.conduit_sector_erase
asmi_sector_protect => asmi_sector_protect, -- asmi_sector_protect.conduit_sector_protect
epcq_dclk => epcq_dclk, -- epcq_dclk.conduit_epcq_dclk
epcq_scein => epcq_scein, -- epcq_scein.conduit_epcq_scein
epcq_sdoin => epcq_sdoin, -- epcq_sdoin.conduit_epcq_sdoin
epcq_dataoe => epcq_dataoe, -- epcq_dataoe.conduit_epcq_dataoe
asmi_clkin => asmi_clkin, -- asmi_clkin.conduit_clkin
asmi_reset => asmi_reset, -- asmi_reset.conduit_reset
asmi_sce => asmi_sce, -- asmi_sce.conduit_asmi_sce
asmi_addr => asmi_addr, -- asmi_addr.conduit_addr
asmi_datain => asmi_datain, -- asmi_datain.conduit_datain
asmi_fast_read => asmi_fast_read, -- asmi_fast_read.conduit_fast_read
asmi_rden => asmi_rden, -- asmi_rden.conduit_rden
asmi_shift_bytes => asmi_shift_bytes, -- asmi_shift_bytes.conduit_shift_bytes
asmi_wren => asmi_wren, -- asmi_wren.conduit_wren
asmi_write => asmi_write, -- asmi_write.conduit_write
asmi_rdid_out => asmi_rdid_out, -- asmi_rdid_out.conduit_rdid_out
asmi_en4b_addr => asmi_en4b_addr, -- asmi_en4b_addr.conduit_en4b_addr
irq => irq -- interrupt_sender.irq
);
end architecture rtl; -- of altera_epcq_controller_core
|
mit
|
andrewandrepowell/axiplasma
|
hdl/plasoc/plasoc_gpio_axi4_write_cntrl.vhd
|
1
|
6873
|
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 16, 2017
--! @brief Contains the entity and architecture of the
--! GPIO Core's Write Controller.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.plasoc_gpio_pack.all;
entity plasoc_gpio_axi4_write_cntrl is
generic (
-- AXI4-Lite parameters.
axi_address_width : integer := 16; --! Defines the AXI4-Lite Address Width.
axi_data_width : integer := 32; --! Defines the AXI4-Lite Data Width.
-- Register interface.
reg_control_offset : std_logic_vector := X"0000"; --! Defines the offset for the Control register.
reg_control_enable_bit_loc : integer := 0;
reg_control_ack_bit_loc : integer := 1;
reg_data_out_offset : std_logic_vector := X"0008"
);
port (
-- Global interface.
aclk : in std_logic; --! Clock. Tested with 50 MHz.
aresetn : in std_logic; --! Reset on low.
-- Slave AXI4-Lite Write interface.
axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Write signal.
axi_awprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Write signal.
axi_awvalid : in std_logic; --! AXI4-Lite Address Write signal.
axi_awready : out std_logic; --! AXI4-Lite Address Write signal.
axi_wvalid : in std_logic; --! AXI4-Lite Write Data signal.
axi_wready : out std_logic; --! AXI4-Lite Write Data signal.
axi_wdata : in std_logic_vector(axi_data_width-1 downto 0); --! AXI4-Lite Write Data signal.
axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0); --! AXI4-Lite Write Data signal.
axi_bvalid : out std_logic; --! AXI4-Lite Write Response signal.
axi_bready : in std_logic; --! AXI4-Lite Write Response signal.
axi_bresp : out std_logic_vector(1 downto 0); --! AXI4-Lite Write Response signal.
-- Register interface.
reg_control_enable : out std_logic := '0'; --! Control register.
reg_control_ack : out std_logic := '0';
reg_data_out : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0')
);
end plasoc_gpio_axi4_write_cntrl;
architecture Behavioral of plasoc_gpio_axi4_write_cntrl is
type state_type is (state_wait,state_write,state_response);
signal state : state_type := state_wait;
signal axi_awready_buff : std_logic := '0';
signal axi_awaddr_buff : std_logic_vector(axi_address_width-1 downto 0);
signal axi_wready_buff : std_logic := '0';
signal axi_bvalid_buff : std_logic := '0';
begin
axi_awready <= axi_awready_buff;
axi_wready <= axi_wready_buff;
axi_bvalid <= axi_bvalid_buff;
axi_bresp <= axi_resp_okay;
-- Drive the axi write interface.
process (aclk)
begin
-- Perform operations on the clock's positive edge.
if rising_edge(aclk) then
if aresetn='0' then
axi_awready_buff <= '0';
axi_wready_buff <= '0';
axi_bvalid_buff <= '0';
reg_control_enable <= '0';
reg_control_ack <= '0';
reg_data_out <= (others=>'0');
state <= state_wait;
else
-- Drive state machine.
case state is
-- WAIT mode.
when state_wait=>
-- Sample address interface on handshake and go start
-- performing the write operation.
if axi_awvalid='1' and axi_awready_buff='1' then
-- Prevent the master from sending any more control information.
axi_awready_buff <= '0';
-- Sample the address sent from the master.
axi_awaddr_buff <= axi_awaddr;
-- Begin to read data to write.
axi_wready_buff <= '1';
state <= state_write;
-- Let the master interface know the slave is ready
-- to receive address information.
else
axi_awready_buff <= '1';
end if;
-- WRITE mode.
when state_write=>
-- Wait for handshake.
if axi_wvalid='1' and axi_wready_buff='1' then
-- Prevent the master from sending any more data.
axi_wready_buff <= '0';
-- Only sample the specified bytes.
for each_byte in 0 to axi_data_width/8-1 loop
if axi_wstrb(each_byte)='1' then
-- Samples the bits of the control register.
if axi_awaddr_buff=reg_control_offset then
reg_control_enable <= axi_wdata(reg_control_enable_bit_loc);
reg_control_ack <= axi_wdata(reg_control_ack_bit_loc);
-- Sample the data for the data out register.
elsif axi_awaddr_buff=reg_data_out_offset then
reg_data_out(7+each_byte*8 downto each_byte*8) <=
axi_wdata(7+each_byte*8 downto each_byte*8);
end if;
end if;
end loop;
-- Begin to transmit the response.
state <= state_response;
axi_bvalid_buff <= '1';
end if;
-- RESPONSE mode.
when state_response=>
-- The acknlowedge should only be high for a single cycle.
reg_control_ack <= '0';
-- Wait for handshake.
if axi_bvalid_buff='1' and axi_bready='1' then
-- Starting waiting for more address information on
-- successful handshake.
axi_bvalid_buff <= '0';
state <= state_wait;
end if;
end case;
end if;
end if;
end process;
end Behavioral;
|
mit
|
andrewandrepowell/axiplasma
|
hdl/projects/VC707/vc707_pack.vhd
|
1
|
141
|
library ieee;
use ieee.std_logic_1164.all;
package vc707_pack is
constant vc707_default_gpio_width : integer := 8;
end package;
|
mit
|
andrewandrepowell/axiplasma
|
hdl/projects/Nexys4/bram.vhd
|
3
|
6275
|
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 14, 2017
--! @brief Contains the entity and architecture of the
--! Single Port Block RAM needed to load either the boot
--! loader, jumper loader, or the main application.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.main_pack.all;
use work.jump_pack.all;
use work.boot_pack.all;
--! The Single Port BRAM is effectively defined as an array the
--! compiler can infer as Block RAM. This methodology is useful for verification
--! purposes since the contents of the array can be observed while in simulation.
--! Moreover, binary can be loaded into the BRAM during static elaboration prior
--! to synthesis, allowing the BRAM to be initialized with a bootloader application
--! for hardware deployment.
--!
--! One out of three types of binary can be statically loaded into the BRAM. The first
--! of which is the Jump binary, whose purpose is to make the Plasma-SoC's CPU jump
--! to a particular place in memory. The Jump binary was made so that the Bootloader
--! binary can be bypassed in simulation, allowing the Main binary to begin its execution
--! faster. The second binary is the Bootloader. The purpose of the Bootloader is to load
--! the Main application into memory and then cause the CPU to jump to the starting address
--! of the Main application. Finally, the Main binary is the application under test. Unlike
--! the Jump and Boot binaries, the Main binary can be located at an address other than 0 if
--! compiled and linked correctly. The Jump and Bootloader binaries need to be built such that
--! they are aware where the Main binary is located and needs to go, respectively.
--!
--! Alternatively, the BRAM can be initialized to zero; in other words, without any binary.
--!
--! It is recommended to read over the documentation presented in the corresponding C sources
--! to learn more about these applications.
entity bram is
generic (
select_app : string := "none"; --! Selects the binary to statically load. "none" refers to no binary. "jump" refers to the Jump binary. "boot" refers to the Bootloader binary. "main" refers to the Main application.
address_width : integer := 18; --! Defines the address width.
data_width : integer := 32; --! Defines the data width.
bram_depth : integer := 65536 --! Defines the size of the BRAM in the number of words.
);
port(
bram_rst_a : in std_logic; --! High reset. Since the binary is loaded statically, this reset effectively behaves like another bram_en_a.
bram_clk_a : in std_logic; --! Clock that synchronizes the BRAM's operation.
bram_en_a : in std_logic; --! Enables the BRAM when high.
bram_we_a : in std_logic_vector(data_width/8-1 downto 0); --! Each high bit allows the respective byte in bram_wrdata_a to be written into the BRAM.
bram_addr_a : in std_logic_vector(address_width-1 downto 0); --! Specifies the BRAM's location where the memory access operation will occur on the next positive edge clock cycle. Should be a multiple of (2**address_width)/(data_width/8) and less than bram_depth*(data_width/8).
bram_wrdata_a : in std_logic_vector(data_width-1 downto 0); --! The data that will be written on the next positive edge clock cycle provided that bram_rst_a is low, bram_en_a is high, and at least one bit in bram_we_a is high.
bram_rddata_a : out std_logic_vector(data_width-1 downto 0) := (others=>'0') --! The data that will be read on the next positive edge clock cycle provided that bram_rst_a is low and bram_en_a is high.
);
end bram;
architecture Behavioral of bram is
constant bytes_per_word : integer := data_width/8;
type bram_buff_type is array (0 to bram_depth-1) of std_logic_vector(data_width-1 downto 0);
function load_selected_app return bram_buff_type is
variable bram_buff : bram_buff_type := (others=>(others=>'0'));
variable boot_buff : work.boot_pack.ram_type;
variable jump_buff : work.jump_pack.ram_type;
variable main_buff : work.main_pack.ram_type;
begin
case select_app is
when "none"=>
when "main"=>
main_buff := work.main_pack.load_hex;
for each_word in 0 to work.main_pack.ram_size-1 loop
bram_buff(each_word) := main_buff(each_word);
end loop;
when "jump"=>
jump_buff := work.jump_pack.load_hex;
for each_word in 0 to work.jump_pack.ram_size-1 loop
bram_buff(each_word) := jump_buff(each_word);
end loop;
when "boot"=>
boot_buff := work.boot_pack.load_hex;
for each_word in 0 to work.boot_pack.ram_size-1 loop
bram_buff(each_word) := boot_buff(each_word);
end loop;
when others=>
assert false report "Incorrect option for select_app" severity error;
end case;
return bram_buff;
end;
signal bram_buff : bram_buff_type := load_selected_app;
begin
process (bram_clk_a)
variable base_index : integer;
begin
if rising_edge(bram_clk_a) then
if bram_rst_a='0' then
if bram_en_a='1' then
base_index := to_integer(unsigned(bram_addr_a))/bytes_per_word;
for each_byte in 0 to bytes_per_word-1 loop
if bram_we_a(each_byte)='1' then
bram_buff(base_index)(each_byte*8+7 downto each_byte*8) <=
bram_wrdata_a(each_byte*8+7 downto each_byte*8);
end if;
end loop;
bram_rddata_a <= bram_buff(base_index);
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
andrewandrepowell/axiplasma
|
hdl/plasoc/plasoc_crossbar.vhd
|
1
|
44293
|
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 14, 2017
--! @brief Contains the entity and architecture of the
--! Plasma-SoC's Crossbar Core. This core should not be
--! utilized directly.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.plasoc_crossbar_pack.all;
--! The Crossbar Core is an interconnect developed so that
--! one or more Slave AXI4-Full interfaces can perform
--! transactions with one or more Master AXI4-Full interfaces.
--!
--! It is critical to have an understanding of the AXI4-Full protocol
--! when it comes to utilizing this Crossbar. Additionally, the Crossbar Core
--! should not be instantiated directly. Instead, a Crossbar Wrapper should
--! be generated with the crossgen python2.7 application. Not only does the
--! Wrapper provide more intuitive interfaces to each of the Slave and Master
--! interfaces, but necessary multiplexers are added to ensure all outputs
--! do not return infinite impedance.
--!
--! The Crossbar is built such that split transactions are supported. Requesting
--! interfaces, such as Slave Address interfaces and Master Response interfaces, can
--! perform a request by presenting either an Address or an ID with an asserted valid
--! signal. Static priorities are used; referring to the Crossbar Wrapper, requesting
--! interfaces closest to the top of the component declaration are given priority over
--! lower interfaces.
--!
--! Information specific to the AXI4-Lite
--! protocol is excluded from here since the information can
--! be found in official ARM AMBA4 AXI documentation.
entity plasoc_crossbar is
generic (
axi_address_width : integer := 16; --! Defines the AXI4-Full address width.
axi_data_width : integer := 32; --! Defines the AXI4-Full data width.
axi_master_amount : integer := 2; --! Defines the number of Master AXI4-Full interfaces.
axi_slave_id_width : integer := 2; --! Defines the ID width of each Slave AXI4-Full interface.
axi_slave_amount : integer := 4; --! Defines the number of Slave AXI4-Full interfaces.
axi_master_base_address : std_logic_vector := X"4000000000000000"; --! Defines the base addresses that refer to the address space of each Master AXI4-Full interface. The position of the address in the address vector corresponds to the position of the Master interface in the signals vector.
axi_master_high_address : std_logic_vector := X"ffffffff3fffffff" --! Defines the high addresses that refer to the address space of each Master AXI4-Full interface. The position of the address in the address vector corresponds to the position of the Master interface in the signals vector.
);
port (
aclk : in std_logic;
aresetn : in std_logic;
s_address_write_connected : out std_logic_vector(axi_slave_amount-1 downto 0); --! Indicates which Slave AXI4-Full Address Write interfaces are connected to a Master interface.
s_data_write_connected : out std_logic_vector(axi_slave_amount-1 downto 0); --! Indicates which Slave AXI4-Full Data Write interfaces are connected to a Master interface.
s_response_write_connected : out std_logic_vector(axi_slave_amount-1 downto 0); --! Indicates which Slave AXI4-Full Response Write interfaces are connected to a Master interface.
s_address_read_connected : out std_logic_vector(axi_slave_amount-1 downto 0); --! Indicates which Slave AXI4-Full Address Read interfaces are connected to a Master interface.
s_data_read_connected : out std_logic_vector(axi_slave_amount-1 downto 0); --! Indicates which Slave AXI4-Full Data Read interfaces are connected to a Master interface.
m_address_write_connected : out std_logic_vector(axi_master_amount-1 downto 0); --! Indicates which Master AXI4-Full Address Write interfaces are connected to a Slave interface.
m_data_write_connected : out std_logic_vector(axi_master_amount-1 downto 0); --! Indicates which Master AXI4-Full Data Write interfaces are connected to a Slave interface.
m_response_write_connected : out std_logic_vector(axi_master_amount-1 downto 0); --! Indicates which Master AXI4-Full Response Write interfaces are connected to a Slave interface.
m_address_read_connected : out std_logic_vector(axi_master_amount-1 downto 0); --! Indicates which Master AXI4-Full Address Read interfaces are connected to a Slave interface.
m_data_read_connected : out std_logic_vector(axi_master_amount-1 downto 0); --! Indicates which Master AXI4-Full Data Read interfaces are connected to a Slave interface.
s_axi_awid : in std_logic_vector(axi_slave_amount*axi_slave_id_width-1 downto 0);
s_axi_awaddr : in std_logic_vector(axi_slave_amount*axi_address_width-1 downto 0);
s_axi_awlen : in std_logic_vector(axi_slave_amount*8-1 downto 0);
s_axi_awsize : in std_logic_vector(axi_slave_amount*3-1 downto 0);
s_axi_awburst : in std_logic_vector(axi_slave_amount*2-1 downto 0);
s_axi_awlock : in std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_awcache : in std_logic_vector(axi_slave_amount*4-1 downto 0);
s_axi_awprot : in std_logic_vector(axi_slave_amount*3-1 downto 0);
s_axi_awqos : in std_logic_vector(axi_slave_amount*4-1 downto 0);
s_axi_awregion : in std_logic_vector(axi_slave_amount*4-1 downto 0);
s_axi_awvalid : in std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_awready : out std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_wdata : in std_logic_vector(axi_slave_amount*axi_data_width-1 downto 0);
s_axi_wstrb : in std_logic_vector(axi_slave_amount*axi_data_width/8-1 downto 0);
s_axi_wlast : in std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_wvalid : in std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_wready : out std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_bid : out std_logic_vector(axi_slave_amount*axi_slave_id_width-1 downto 0);
s_axi_bresp : out std_logic_vector(axi_slave_amount*2-1 downto 0);
s_axi_bvalid : out std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_bready : in std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_arid : in std_logic_vector(axi_slave_amount*axi_slave_id_width-1 downto 0);
s_axi_araddr : in std_logic_vector(axi_slave_amount*axi_address_width-1 downto 0);
s_axi_arlen : in std_logic_vector(axi_slave_amount*8-1 downto 0);
s_axi_arsize : in std_logic_vector(axi_slave_amount*3-1 downto 0);
s_axi_arburst : in std_logic_vector(axi_slave_amount*2-1 downto 0);
s_axi_arlock : in std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_arcache : in std_logic_vector(axi_slave_amount*4-1 downto 0);
s_axi_arprot : in std_logic_vector(axi_slave_amount*3-1 downto 0);
s_axi_arqos : in std_logic_vector(axi_slave_amount*4-1 downto 0);
s_axi_arregion : in std_logic_vector(axi_slave_amount*4-1 downto 0);
s_axi_arvalid : in std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_arready : out std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_rid : out std_logic_vector(axi_slave_amount*axi_slave_id_width-1 downto 0);
s_axi_rdata : out std_logic_vector(axi_slave_amount*axi_data_width-1 downto 0);
s_axi_rresp : out std_logic_vector(axi_slave_amount*2-1 downto 0);
s_axi_rlast : out std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_rvalid : out std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_rready : in std_logic_vector(axi_slave_amount*1-1 downto 0);
m_axi_awid : out std_logic_vector(axi_master_amount*(clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
m_axi_awaddr : out std_logic_vector(axi_master_amount*axi_address_width-1 downto 0);
m_axi_awlen : out std_logic_vector(axi_master_amount*8-1 downto 0);
m_axi_awsize : out std_logic_vector(axi_master_amount*3-1 downto 0);
m_axi_awburst : out std_logic_vector(axi_master_amount*2-1 downto 0);
m_axi_awlock : out std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_awcache : out std_logic_vector(axi_master_amount*4-1 downto 0);
m_axi_awprot : out std_logic_vector(axi_master_amount*3-1 downto 0);
m_axi_awqos : out std_logic_vector(axi_master_amount*4-1 downto 0);
m_axi_awregion : out std_logic_vector(axi_master_amount*4-1 downto 0);
m_axi_awvalid : out std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_awready : in std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_wdata : out std_logic_vector(axi_master_amount*axi_data_width-1 downto 0);
m_axi_wstrb : out std_logic_vector(axi_master_amount*axi_data_width/8-1 downto 0);
m_axi_wlast : out std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_wvalid : out std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_wready : in std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_bid : in std_logic_vector(axi_master_amount*(clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
m_axi_bresp : in std_logic_vector(axi_master_amount*2-1 downto 0);
m_axi_bvalid : in std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_bready : out std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_arid : out std_logic_vector(axi_master_amount*(clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
m_axi_araddr : out std_logic_vector(axi_master_amount*axi_address_width-1 downto 0);
m_axi_arlen : out std_logic_vector(axi_master_amount*8-1 downto 0);
m_axi_arsize : out std_logic_vector(axi_master_amount*3-1 downto 0);
m_axi_arburst : out std_logic_vector(axi_master_amount*2-1 downto 0);
m_axi_arlock : out std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_arcache : out std_logic_vector(axi_master_amount*4-1 downto 0);
m_axi_arprot : out std_logic_vector(axi_master_amount*3-1 downto 0);
m_axi_arqos : out std_logic_vector(axi_master_amount*4-1 downto 0);
m_axi_arregion : out std_logic_vector(axi_master_amount*4-1 downto 0);
m_axi_arvalid : out std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_arready : in std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_rid : in std_logic_vector(axi_master_amount*(clogb2(axi_slave_amount)+axi_slave_id_width)-1 downto 0);
m_axi_rdata : in std_logic_vector(axi_master_amount*axi_data_width-1 downto 0);
m_axi_rresp : in std_logic_vector(axi_master_amount*2-1 downto 0);
m_axi_rlast : in std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_rvalid : in std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_rready : out std_logic_vector(axi_master_amount*1-1 downto 0)
);
end plasoc_crossbar;
architecture Behavioral of plasoc_crossbar is
constant axi_slave_iden_width : integer := clogb2(axi_slave_amount);
constant axi_master_iden_width : integer := clogb2(axi_master_amount);
constant axi_master_id_width : integer := axi_slave_iden_width+axi_slave_id_width;
component plasoc_crossbar_base is
generic (
width : integer := 16;
input_amount : integer := 2;
output_amount : integer := 2);
port (
inputs : in std_logic_vector(width*input_amount-1 downto 0);
enables : in std_logic_vector(input_amount*output_amount-1 downto 0);
outputs : out std_logic_vector(width*output_amount-1 downto 0));
end component;
component plasoc_crossbar_axi4_write_cntrl is
generic (
axi_slave_amount : integer := 2;
axi_master_amount : integer := 4);
port (
aclk : in std_logic;
aresetn : in std_logic;
axi_write_master_iden : in std_logic_vector(axi_slave_amount*clogb2(axi_master_amount)-1 downto 0);
axi_write_slave_iden : in std_logic_vector(axi_master_amount*clogb2(axi_slave_amount)-1 downto 0);
axi_address_write_enables : out std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
axi_data_write_enables : out std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
axi_response_write_enables : out std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
s_axi_awvalid : in std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_wvalid : in std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_wlast : in std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_bready : in std_logic_vector(axi_slave_amount*1-1 downto 0);
m_axi_awready : in std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_wready : in std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_bvalid : in std_logic_vector(axi_master_amount*1-1 downto 0));
end component;
component plasoc_crossbar_axi4_read_cntrl is
generic (
axi_slave_amount : integer := 2;
axi_master_amount : integer := 4);
port (
aclk : in std_logic;
aresetn : in std_logic;
axi_read_master_iden : in std_logic_vector(axi_slave_amount*clogb2(axi_master_amount)-1 downto 0);
axi_read_slave_iden : in std_logic_vector(axi_master_amount*clogb2(axi_slave_amount)-1 downto 0);
axi_address_read_enables : out std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
axi_data_read_enables : out std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
s_axi_arvalid : in std_logic_vector(axi_slave_amount*1-1 downto 0);
s_axi_rready : in std_logic_vector(axi_slave_amount*1-1 downto 0);
m_axi_arready : in std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_rvalid : in std_logic_vector(axi_master_amount*1-1 downto 0);
m_axi_rlast : in std_logic_vector(axi_master_amount*1-1 downto 0));
end component;
function set_crossbar_enables( enables : in std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0) ) return std_logic_vector is
constant cross_enables_width : integer := axi_slave_amount*axi_master_amount;
variable s2m_enables : std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
variable m2s_enables : std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
variable cross_enables : std_logic_vector(2*cross_enables_width-1 downto 0);
begin
for each_slave in 0 to axi_slave_amount-1 loop
for each_master in 0 to axi_master_amount-1 loop
if enables(each_slave+each_master*axi_slave_amount)='1' then
s2m_enables(each_slave+each_master*axi_slave_amount) := '1';
m2s_enables(each_master+each_slave*axi_master_amount) := '1';
else
s2m_enables(each_slave+each_master*axi_slave_amount) := '0';
m2s_enables(each_master+each_slave*axi_master_amount) := '0';
end if;
end loop;
end loop;
cross_enables(cross_enables_width-1 downto 0) := s2m_enables;
cross_enables(2*cross_enables_width-1 downto cross_enables_width) := m2s_enables;
return cross_enables;
end;
function set_connected( enables : in std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0) ) return std_logic_vector is
constant connected_width : integer := axi_slave_amount+axi_master_amount;
variable slave_connected : std_logic_vector(axi_slave_amount-1 downto 0) := (others=>'0');
variable master_connected : std_logic_vector(axi_master_amount-1 downto 0) := (others=>'0');
variable or_reduced : Boolean;
variable connected : std_logic_vector(connected_width-1 downto 0);
begin
for each_slave in 0 to axi_slave_amount-1 loop
or_reduced := False;
for each_master in 0 to axi_master_amount-1 loop
or_reduced := or_reduced or (enables(each_slave+each_master*axi_slave_amount)='1');
end loop;
if or_reduced then
slave_connected(each_slave) := '1';
end if;
end loop;
for each_master in 0 to axi_master_amount-1 loop
or_reduced := False;
for each_slave in 0 to axi_slave_amount-1 loop
or_reduced := or_reduced or (enables(each_slave+each_master*axi_slave_amount)='1');
end loop;
if or_reduced then
master_connected(each_master) := '1';
end if;
end loop;
connected(axi_slave_amount-1 downto 0) := slave_connected;
connected(connected_width-1 downto axi_slave_amount) := master_connected;
return connected;
end;
function decode_master_iden (
address : in std_logic_vector(axi_slave_amount*axi_address_width-1 downto 0);
base_addresses : in std_logic_vector(axi_master_amount*axi_address_width-1 downto 0);
high_addresses : in std_logic_vector(axi_master_amount*axi_address_width-1 downto 0))
return std_logic_vector is
variable master_iden_buff : std_logic_vector(axi_slave_amount*axi_master_iden_width-1 downto 0) := (others=>'0');
variable slave_address : std_logic_vector(axi_address_width-1 downto 0);
variable master_base_address : std_logic_vector(axi_address_width-1 downto 0);
variable master_high_address : std_logic_vector(axi_address_width-1 downto 0);
begin
for each_slave in 0 to axi_slave_amount-1 loop
slave_address := address((1+each_slave)*axi_address_width-1 downto each_slave*axi_address_width);
for each_master in 0 to axi_master_amount-1 loop
master_base_address := base_addresses((1+each_master)*axi_address_width-1 downto each_master*axi_address_width);
master_high_address := high_addresses((1+each_master)*axi_address_width-1 downto each_master*axi_address_width);
if slave_address>=master_base_address and slave_address<=master_high_address then
master_iden_buff((1+each_slave)*axi_master_iden_width-1 downto each_slave*axi_master_iden_width) :=
std_logic_vector(to_unsigned(each_master,axi_master_iden_width));
end if;
end loop;
end loop;
return master_iden_buff;
end;
signal axi_read_slave_iden : std_logic_vector(axi_master_amount*axi_slave_iden_width-1 downto 0);
signal axi_write_slave_iden : std_logic_vector(axi_master_amount*axi_slave_iden_width-1 downto 0);
signal axi_read_master_iden : std_logic_vector(axi_slave_amount*axi_master_iden_width-1 downto 0);
signal axi_write_master_iden : std_logic_vector(axi_slave_amount*axi_master_iden_width-1 downto 0);
signal s_axi_awid_full : std_logic_vector(axi_slave_amount*axi_master_id_width-1 downto 0);
signal s_axi_arid_full : std_logic_vector(axi_slave_amount*axi_master_id_width-1 downto 0);
signal m_axi_rid_from_slave : std_logic_vector(axi_master_amount*axi_slave_id_width-1 downto 0);
signal m_axi_bid_from_slave : std_logic_vector(axi_master_amount*axi_slave_id_width-1 downto 0);
signal axi_address_write_enables : std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
signal axi_address_s2m_write_enables : std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
signal axi_address_m2s_write_enables : std_logic_vector(axi_master_amount*axi_slave_amount-1 downto 0);
signal axi_data_write_enables : std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
signal axi_data_s2m_write_enables : std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
signal axi_data_m2s_write_enables : std_logic_vector(axi_master_amount*axi_slave_amount-1 downto 0);
signal axi_response_write_enables : std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
signal axi_response_s2m_write_enables : std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
signal axi_response_m2s_write_enables : std_logic_vector(axi_master_amount*axi_slave_amount-1 downto 0);
signal axi_address_read_enables : std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
signal axi_address_s2m_read_enables : std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
signal axi_address_m2s_read_enables : std_logic_vector(axi_master_amount*axi_slave_amount-1 downto 0);
signal axi_data_read_enables : std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
signal axi_data_s2m_read_enables : std_logic_vector(axi_slave_amount*axi_master_amount-1 downto 0);
signal axi_data_m2s_read_enables : std_logic_vector(axi_master_amount*axi_slave_amount-1 downto 0);
signal s_address_write_connected_buff : std_logic_vector(axi_slave_amount-1 downto 0);
signal s_data_write_connected_buff : std_logic_vector(axi_slave_amount-1 downto 0);
signal s_response_write_connected_buff : std_logic_vector(axi_slave_amount-1 downto 0);
signal s_address_read_connected_buff : std_logic_vector(axi_slave_amount-1 downto 0);
signal s_data_read_connected_buff : std_logic_vector(axi_slave_amount-1 downto 0);
signal m_address_write_connected_buff : std_logic_vector(axi_master_amount-1 downto 0);
signal m_data_write_connected_buff : std_logic_vector(axi_master_amount-1 downto 0);
signal m_response_write_connected_buff : std_logic_vector(axi_master_amount-1 downto 0);
signal m_address_read_connected_buff : std_logic_vector(axi_master_amount-1 downto 0);
signal m_data_read_connected_buff : std_logic_vector(axi_master_amount-1 downto 0);
begin
s_address_write_connected <= s_address_write_connected_buff;
s_data_write_connected <= s_data_write_connected_buff;
s_response_write_connected <= s_response_write_connected_buff;
s_address_read_connected <= s_address_read_connected_buff;
s_data_read_connected <= s_data_read_connected_buff;
m_address_write_connected <= m_address_write_connected_buff;
m_data_write_connected <= m_data_write_connected_buff;
m_response_write_connected <= m_response_write_connected_buff;
m_address_read_connected <= m_address_read_connected_buff;
m_data_read_connected <= m_data_read_connected_buff;
plasoc_crossbar_axi4_write_cntrl_inst : plasoc_crossbar_axi4_write_cntrl
generic map (
axi_slave_amount => axi_slave_amount,
axi_master_amount => axi_master_amount)
port map (
aclk => aclk,
aresetn => aresetn,
axi_write_master_iden => axi_write_master_iden,
axi_write_slave_iden => axi_write_slave_iden,
axi_address_write_enables => axi_address_write_enables,
axi_data_write_enables => axi_data_write_enables,
axi_response_write_enables => axi_response_write_enables,
s_axi_awvalid => s_axi_awvalid,
s_axi_wvalid => s_axi_wvalid,
s_axi_wlast => s_axi_wlast,
s_axi_bready => s_axi_bready,
m_axi_awready => m_axi_awready,
m_axi_wready => m_axi_wready,
m_axi_bvalid => m_axi_bvalid);
plasoc_crossbar_axi4_read_cntrl_inst : plasoc_crossbar_axi4_read_cntrl
generic map (
axi_slave_amount => axi_slave_amount,
axi_master_amount => axi_master_amount)
port map (
aclk => aclk,
aresetn => aresetn,
axi_read_master_iden => axi_read_master_iden,
axi_read_slave_iden => axi_read_slave_iden,
axi_address_read_enables => axi_address_read_enables,
axi_data_read_enables => axi_data_read_enables,
s_axi_arvalid => s_axi_arvalid,
s_axi_rready => s_axi_rready,
m_axi_arready => m_axi_arready,
m_axi_rvalid => m_axi_rvalid,
m_axi_rlast => m_axi_rlast);
generate_slave_idassigns:
for each_slave in 0 to axi_slave_amount-1 generate
s_axi_awid_full((1+each_slave)*axi_master_id_width-1 downto (1+each_slave)*axi_master_id_width-axi_slave_iden_width) <=
std_logic_vector(to_unsigned(each_slave,axi_slave_iden_width));
s_axi_awid_full(axi_slave_id_width-1+each_slave*axi_master_id_width downto 0+each_slave*axi_master_id_width) <=
s_axi_awid((1+each_slave)*axi_slave_id_width-1 downto 0+each_slave*axi_slave_id_width);
s_axi_arid_full((1+each_slave)*axi_master_id_width-1 downto (1+each_slave)*axi_master_id_width-axi_slave_iden_width) <=
std_logic_vector(to_unsigned(each_slave,axi_slave_iden_width));
s_axi_arid_full(axi_slave_id_width-1+each_slave*axi_master_id_width downto 0+each_slave*axi_master_id_width) <=
s_axi_arid((1+each_slave)*axi_slave_id_width-1 downto 0+each_slave*axi_slave_id_width);
end generate generate_slave_idassigns;
generate_master_idassigns:
for each_master in 0 to axi_master_amount-1 generate
axi_read_slave_iden((1+each_master)*axi_slave_iden_width-1 downto each_master*axi_slave_iden_width) <=
m_axi_rid((1+each_master)*axi_master_id_width-1 downto (1+each_master)*axi_master_id_width-axi_slave_iden_width);
m_axi_rid_from_slave((1+each_master)*axi_slave_id_width-1 downto each_master*axi_slave_id_width) <=
m_axi_rid(axi_slave_id_width-1+each_master*axi_master_id_width downto 0+each_master*axi_master_id_width);
axi_write_slave_iden((1+each_master)*axi_slave_iden_width-1 downto each_master*axi_slave_iden_width) <=
m_axi_bid((1+each_master)*axi_master_id_width-1 downto (1+each_master)*axi_master_id_width-axi_slave_iden_width);
m_axi_bid_from_slave((1+each_master)*axi_slave_id_width-1 downto each_master*axi_slave_id_width) <=
m_axi_bid(axi_slave_id_width-1+each_master*axi_master_id_width downto 0+each_master*axi_master_id_width);
end generate generate_master_idassigns;
process (s_axi_awaddr)
begin
axi_write_master_iden <= decode_master_iden(s_axi_awaddr,axi_master_base_address,axi_master_high_address);
end process;
process (s_axi_araddr)
begin
axi_read_master_iden <= decode_master_iden(s_axi_araddr,axi_master_base_address,axi_master_high_address);
end process;
process (axi_address_write_enables)
constant connected_width : integer := axi_slave_amount+axi_master_amount;
variable connected : std_logic_vector(connected_width-1 downto 0);
begin
connected := set_connected(axi_address_write_enables);
s_address_write_connected_buff <= connected(axi_slave_amount-1 downto 0);
m_address_write_connected_buff <= connected(connected_width-1 downto axi_slave_amount);
end process;
process (axi_data_write_enables)
constant connected_width : integer := axi_slave_amount+axi_master_amount;
variable connected : std_logic_vector(connected_width-1 downto 0);
begin
connected := set_connected(axi_data_write_enables);
s_data_write_connected_buff <= connected(axi_slave_amount-1 downto 0);
m_data_write_connected_buff <= connected(connected_width-1 downto axi_slave_amount);
end process;
process (axi_response_write_enables)
constant connected_width : integer := axi_slave_amount+axi_master_amount;
variable connected : std_logic_vector(connected_width-1 downto 0);
begin
connected := set_connected(axi_response_write_enables);
s_response_write_connected_buff <= connected(axi_slave_amount-1 downto 0);
m_response_write_connected_buff <= connected(connected_width-1 downto axi_slave_amount);
end process;
process (axi_address_read_enables)
constant connected_width : integer := axi_slave_amount+axi_master_amount;
variable connected : std_logic_vector(connected_width-1 downto 0);
begin
connected := set_connected(axi_address_read_enables);
s_address_read_connected_buff <= connected(axi_slave_amount-1 downto 0);
m_address_read_connected_buff <= connected(connected_width-1 downto axi_slave_amount);
end process;
process (axi_data_read_enables)
constant connected_width : integer := axi_slave_amount+axi_master_amount;
variable connected : std_logic_vector(connected_width-1 downto 0);
begin
connected := set_connected(axi_data_read_enables);
s_data_read_connected_buff <= connected(axi_slave_amount-1 downto 0);
m_data_read_connected_buff <= connected(connected_width-1 downto axi_slave_amount);
end process;
process (axi_address_write_enables)
constant cross_enables_width : integer := axi_slave_amount*axi_master_amount;
variable cross_enables : std_logic_vector(2*cross_enables_width-1 downto 0);
begin
cross_enables := set_crossbar_enables(axi_address_write_enables);
axi_address_s2m_write_enables <= cross_enables(cross_enables_width-1 downto 0);
axi_address_m2s_write_enables <= cross_enables(2*cross_enables_width-1 downto cross_enables_width);
end process;
process (axi_data_write_enables)
constant cross_enables_width : integer := axi_slave_amount*axi_master_amount;
variable cross_enables : std_logic_vector(2*cross_enables_width-1 downto 0);
begin
cross_enables := set_crossbar_enables(axi_data_write_enables);
axi_data_s2m_write_enables <= cross_enables(cross_enables_width-1 downto 0);
axi_data_m2s_write_enables <= cross_enables(2*cross_enables_width-1 downto cross_enables_width);
end process;
process (axi_response_write_enables)
constant cross_enables_width : integer := axi_slave_amount*axi_master_amount;
variable cross_enables : std_logic_vector(2*cross_enables_width-1 downto 0);
begin
cross_enables := set_crossbar_enables(axi_response_write_enables);
axi_response_s2m_write_enables <= cross_enables(cross_enables_width-1 downto 0);
axi_response_m2s_write_enables <= cross_enables(2*cross_enables_width-1 downto cross_enables_width);
end process;
process (axi_address_read_enables)
constant cross_enables_width : integer := axi_slave_amount*axi_master_amount;
variable cross_enables : std_logic_vector(2*cross_enables_width-1 downto 0);
begin
cross_enables := set_crossbar_enables(axi_address_read_enables);
axi_address_s2m_read_enables <= cross_enables(cross_enables_width-1 downto 0);
axi_address_m2s_read_enables <= cross_enables(2*cross_enables_width-1 downto cross_enables_width);
end process;
process (axi_data_read_enables)
constant cross_enables_width : integer := axi_slave_amount*axi_master_amount;
variable cross_enables : std_logic_vector(2*cross_enables_width-1 downto 0);
begin
cross_enables := set_crossbar_enables(axi_data_read_enables);
axi_data_s2m_read_enables <= cross_enables(cross_enables_width-1 downto 0);
axi_data_m2s_read_enables <= cross_enables(2*cross_enables_width-1 downto cross_enables_width);
end process;
awid_cross_inst : plasoc_crossbar_base
generic map (width => axi_master_id_width,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_awid_full,enables => axi_address_s2m_write_enables,outputs => m_axi_awid);
awaddr_cross_inst : plasoc_crossbar_base
generic map (width => axi_address_width,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_awaddr,enables => axi_address_s2m_write_enables,outputs => m_axi_awaddr);
awlen_cross_inst : plasoc_crossbar_base
generic map (width => 8,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_awlen,enables => axi_address_s2m_write_enables,outputs => m_axi_awlen);
awsize_cross_inst : plasoc_crossbar_base
generic map (width => 3,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_awsize,enables => axi_address_s2m_write_enables,outputs => m_axi_awsize);
awburst_cross_inst : plasoc_crossbar_base
generic map (width => 2,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_awburst,enables => axi_address_s2m_write_enables,outputs => m_axi_awburst);
awlock_cross_inst : plasoc_crossbar_base
generic map (width => 1,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_awlock,enables => axi_address_s2m_write_enables,outputs => m_axi_awlock);
awcache_cross_inst : plasoc_crossbar_base
generic map (width => 4,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_awcache,enables => axi_address_s2m_write_enables,outputs => m_axi_awcache);
awprot_cross_inst : plasoc_crossbar_base
generic map (width => 3,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_awprot,enables => axi_address_s2m_write_enables,outputs => m_axi_awprot);
awqos_cross_inst : plasoc_crossbar_base
generic map (width => 4,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_awqos,enables => axi_address_s2m_write_enables,outputs => m_axi_awqos);
awregion_cross_inst : plasoc_crossbar_base
generic map (width => 4,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_awregion,enables => axi_address_s2m_write_enables,outputs => m_axi_awregion);
awvalid_cross_inst : plasoc_crossbar_base
generic map (width => 1,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_awvalid,enables => axi_address_s2m_write_enables,outputs => m_axi_awvalid);
awready_cross_inst : plasoc_crossbar_base
generic map (width => 1,input_amount => axi_master_amount,output_amount => axi_slave_amount)
port map (inputs => m_axi_awready,enables => axi_address_m2s_write_enables,outputs => s_axi_awready);
wdata_cross_inst : plasoc_crossbar_base
generic map (width => axi_data_width,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_wdata,enables => axi_data_s2m_write_enables,outputs => m_axi_wdata);
wstrb_cross_inst : plasoc_crossbar_base
generic map (width => axi_data_width/8,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_wstrb,enables => axi_data_s2m_write_enables,outputs => m_axi_wstrb);
wlast_cross_inst : plasoc_crossbar_base
generic map (width => 1,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_wlast,enables => axi_data_s2m_write_enables,outputs => m_axi_wlast);
wvalid_cross_inst : plasoc_crossbar_base
generic map (width => 1,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_wvalid,enables => axi_data_s2m_write_enables,outputs => m_axi_wvalid);
wready_cross_inst : plasoc_crossbar_base
generic map (width => 1,input_amount => axi_master_amount,output_amount => axi_slave_amount)
port map (inputs => m_axi_wready,enables => axi_data_m2s_write_enables,outputs => s_axi_wready);
bid_cross_inst : plasoc_crossbar_base
generic map (width => axi_slave_id_width,input_amount => axi_master_amount,output_amount => axi_slave_amount)
port map (inputs => m_axi_bid_from_slave,enables => axi_response_m2s_write_enables,outputs => s_axi_bid);
bresp_cross_inst : plasoc_crossbar_base
generic map (width => 2,input_amount => axi_master_amount,output_amount => axi_slave_amount)
port map (inputs => m_axi_bresp,enables => axi_response_m2s_write_enables,outputs => s_axi_bresp);
bvalid_cross_inst : plasoc_crossbar_base
generic map (width => 1,input_amount => axi_master_amount,output_amount => axi_slave_amount)
port map (inputs => m_axi_bvalid,enables => axi_response_m2s_write_enables,outputs => s_axi_bvalid);
bready_cross_inst : plasoc_crossbar_base
generic map (width => 1,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_bready,enables => axi_response_s2m_write_enables,outputs => m_axi_bready);
arid_cross_inst : plasoc_crossbar_base
generic map (width => axi_master_id_width,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_arid_full,enables => axi_address_s2m_read_enables,outputs => m_axi_arid);
araddr_cross_inst : plasoc_crossbar_base
generic map (width => axi_address_width,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_araddr,enables => axi_address_s2m_read_enables,outputs => m_axi_araddr);
arlen_cross_inst : plasoc_crossbar_base
generic map (width => 8,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_arlen,enables => axi_address_s2m_read_enables,outputs => m_axi_arlen);
arsize_cross_inst : plasoc_crossbar_base
generic map (width => 3,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_arsize,enables => axi_address_s2m_read_enables,outputs => m_axi_arsize);
arburst_cross_inst : plasoc_crossbar_base
generic map (width => 2,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_arburst,enables => axi_address_s2m_read_enables,outputs => m_axi_arburst);
arlock_cross_inst : plasoc_crossbar_base
generic map (width => 1,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_arlock,enables => axi_address_s2m_read_enables,outputs => m_axi_arlock);
arcache_cross_inst : plasoc_crossbar_base
generic map (width => 4,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_arcache,enables => axi_address_s2m_read_enables,outputs => m_axi_arcache);
arprot_cross_inst : plasoc_crossbar_base
generic map (width => 3,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_arprot,enables => axi_address_s2m_read_enables,outputs => m_axi_arprot);
arqos_cross_inst : plasoc_crossbar_base
generic map (width => 4,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_arqos,enables => axi_address_s2m_read_enables,outputs => m_axi_arqos);
arregion_cross_inst : plasoc_crossbar_base
generic map (width => 4,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_arregion,enables => axi_address_s2m_read_enables,outputs => m_axi_arregion);
arvalid_cross_inst : plasoc_crossbar_base
generic map (width => 1,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_arvalid,enables => axi_address_s2m_read_enables,outputs => m_axi_arvalid);
arready_cross_inst : plasoc_crossbar_base
generic map (width => 1,input_amount => axi_master_amount,output_amount => axi_slave_amount)
port map (inputs => m_axi_arready,enables => axi_address_m2s_read_enables,outputs => s_axi_arready);
rid_cross_inst : plasoc_crossbar_base
generic map (width => axi_slave_id_width,input_amount => axi_master_amount,output_amount => axi_slave_amount)
port map (inputs => m_axi_rid_from_slave,enables => axi_data_m2s_read_enables,outputs => s_axi_rid);
rdata_cross_inst : plasoc_crossbar_base
generic map (width => axi_data_width,input_amount => axi_master_amount,output_amount => axi_slave_amount)
port map (inputs => m_axi_rdata,enables => axi_data_m2s_read_enables,outputs => s_axi_rdata);
rresp_cross_inst : plasoc_crossbar_base
generic map (width => 2,input_amount => axi_master_amount,output_amount => axi_slave_amount)
port map (inputs => m_axi_rresp,enables => axi_data_m2s_read_enables,outputs => s_axi_rresp);
rlast_cross_inst : plasoc_crossbar_base
generic map (width => 1,input_amount => axi_master_amount,output_amount => axi_slave_amount)
port map (inputs => m_axi_rlast,enables => axi_data_m2s_read_enables,outputs => s_axi_rlast);
rvalid_cross_inst : plasoc_crossbar_base
generic map (width => 1,input_amount => axi_master_amount,output_amount => axi_slave_amount)
port map (inputs => m_axi_rvalid,enables => axi_data_m2s_read_enables,outputs => s_axi_rvalid);
rready_cross_inst : plasoc_crossbar_base
generic map (width => 1,input_amount => axi_slave_amount,output_amount => axi_master_amount)
port map (inputs => s_axi_rready,enables => axi_data_s2m_read_enables,outputs => m_axi_rready);
end Behavioral;
|
mit
|
andrewandrepowell/axiplasma
|
hdl/plasoc/plasoc_int_pack.vhd
|
1
|
3856
|
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 17, 2017
--! @brief Contains the package and component declaration of the
--! Plasma-SoC's Interrupt Controller. Please refer to the documentation
--! in plasoc_int.vhd for more information.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
package plasoc_int_pack is
-- Default Interrupt Controller parameters. These values are modifiable. If these parameters are
-- modified, though, modifications will also be necessary for the corresponding header file.
constant default_interrupt_total : integer := 8; --! Defines the default number of available device interrupts.
constant default_int_id_offset : integer := 4; --! For the Interrupt Identifier register, defines the default offset from the Interrupt Controller's axi_base_address.
constant default_int_enables_offset : integer := 0; --! For the Interrupt Enables register, defines the default offset from the instantiations's base address.
constant default_int_active_address : integer := 8; --! For the Interrupt Active register, defines the default offset from the instantiations's base address.
constant axi_resp_okay : std_logic_vector := "00";
-- Function declarations.
function clogb2(bit_depth : in integer ) return integer;
-- Component declaration.
component plasoc_int is
generic(
axi_address_width : integer := 16;
axi_data_width : integer := 32;
axi_int_id_offset : integer := default_int_id_offset;
axi_int_enables_offset : integer := default_int_enables_offset;
axi_int_active_offset : integer := default_int_active_address;
interrupt_total : integer := default_interrupt_total);
port(
aclk : in std_logic;
aresetn : in std_logic;
axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0);
axi_awprot : in std_logic_vector(2 downto 0);
axi_awvalid : in std_logic;
axi_awready : out std_logic;
axi_wvalid : in std_logic;
axi_wready : out std_logic;
axi_wdata : in std_logic_vector(axi_data_width-1 downto 0);
axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0);
axi_bvalid : out std_logic;
axi_bready : in std_logic;
axi_bresp : out std_logic_vector(1 downto 0);
axi_araddr : in std_logic_vector(axi_address_width-1 downto 0);
axi_arprot : in std_logic_vector(2 downto 0);
axi_arvalid : in std_logic;
axi_arready : out std_logic;
axi_rdata : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0');
axi_rvalid : out std_logic;
axi_rready : in std_logic;
axi_rresp : out std_logic_vector(1 downto 0);
cpu_int : out std_logic;
dev_ints : in std_logic_vector(interrupt_total-1 downto 0));
end component;
end;
package body plasoc_int_pack is
function flogb2(bit_depth : in natural ) return integer is
variable result : integer := 0;
variable bit_depth_buff : integer := bit_depth;
begin
while bit_depth_buff>1 loop
bit_depth_buff := bit_depth_buff/2;
result := result+1;
end loop;
return result;
end function flogb2;
function clogb2 (bit_depth : in natural ) return natural is
variable result : integer := 0;
begin
result := flogb2(bit_depth);
if (bit_depth > (2**result)) then
return(result + 1);
else
return result;
end if;
end function clogb2;
end;
|
mit
|
andrewandrepowell/axiplasma
|
hdl/plasma/mem_ctrl.vhd
|
13
|
6562
|
---------------------------------------------------------------------
-- TITLE: Memory Controller
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 1/31/01
-- FILENAME: mem_ctrl.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Memory controller for the Plasma CPU.
-- Supports Big or Little Endian mode.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity mem_ctrl is
port(clk : in std_logic;
reset_in : in std_logic;
pause_in : in std_logic;
nullify_op : in std_logic;
address_pc : in std_logic_vector(31 downto 2);
opcode_out : out std_logic_vector(31 downto 0);
address_in : in std_logic_vector(31 downto 0);
mem_source : in mem_source_type;
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
pause_out : out std_logic;
address_next : out std_logic_vector(31 downto 2);
byte_we_next : out std_logic_vector(3 downto 0);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0));
end; --entity mem_ctrl
architecture logic of mem_ctrl is
--"00" = big_endian; "11" = little_endian
constant ENDIAN_MODE : std_logic_vector(1 downto 0) := "00";
signal opcode_reg : std_logic_vector(31 downto 0);
signal next_opcode_reg : std_logic_vector(31 downto 0);
signal address_reg : std_logic_vector(31 downto 2);
signal byte_we_reg : std_logic_vector(3 downto 0);
signal mem_state_reg : std_logic;
constant STATE_ADDR : std_logic := '0';
constant STATE_ACCESS : std_logic := '1';
begin
mem_proc: process(clk, reset_in, pause_in, nullify_op,
address_pc, address_in, mem_source, data_write,
data_r, opcode_reg, next_opcode_reg, mem_state_reg,
address_reg, byte_we_reg)
variable address_var : std_logic_vector(31 downto 2);
variable data_read_var : std_logic_vector(31 downto 0);
variable data_write_var : std_logic_vector(31 downto 0);
variable opcode_next : std_logic_vector(31 downto 0);
variable byte_we_var : std_logic_vector(3 downto 0);
variable mem_state_next : std_logic;
variable pause_var : std_logic;
variable bits : std_logic_vector(1 downto 0);
begin
byte_we_var := "0000";
pause_var := '0';
data_read_var := ZERO;
data_write_var := ZERO;
mem_state_next := mem_state_reg;
opcode_next := opcode_reg;
case mem_source is
when MEM_READ32 =>
data_read_var := data_r;
when MEM_READ16 | MEM_READ16S =>
if address_in(1) = ENDIAN_MODE(1) then
data_read_var(15 downto 0) := data_r(31 downto 16);
else
data_read_var(15 downto 0) := data_r(15 downto 0);
end if;
if mem_source = MEM_READ16 or data_read_var(15) = '0' then
data_read_var(31 downto 16) := ZERO(31 downto 16);
else
data_read_var(31 downto 16) := ONES(31 downto 16);
end if;
when MEM_READ8 | MEM_READ8S =>
bits := address_in(1 downto 0) xor ENDIAN_MODE;
case bits is
when "00" => data_read_var(7 downto 0) := data_r(31 downto 24);
when "01" => data_read_var(7 downto 0) := data_r(23 downto 16);
when "10" => data_read_var(7 downto 0) := data_r(15 downto 8);
when others => data_read_var(7 downto 0) := data_r(7 downto 0);
end case;
if mem_source = MEM_READ8 or data_read_var(7) = '0' then
data_read_var(31 downto 8) := ZERO(31 downto 8);
else
data_read_var(31 downto 8) := ONES(31 downto 8);
end if;
when MEM_WRITE32 =>
data_write_var := data_write;
byte_we_var := "1111";
when MEM_WRITE16 =>
data_write_var := data_write(15 downto 0) & data_write(15 downto 0);
if address_in(1) = ENDIAN_MODE(1) then
byte_we_var := "1100";
else
byte_we_var := "0011";
end if;
when MEM_WRITE8 =>
data_write_var := data_write(7 downto 0) & data_write(7 downto 0) &
data_write(7 downto 0) & data_write(7 downto 0);
bits := address_in(1 downto 0) xor ENDIAN_MODE;
case bits is
when "00" =>
byte_we_var := "1000";
when "01" =>
byte_we_var := "0100";
when "10" =>
byte_we_var := "0010";
when others =>
byte_we_var := "0001";
end case;
when others =>
end case;
if mem_source = MEM_FETCH then --opcode fetch
address_var := address_pc;
opcode_next := data_r;
mem_state_next := STATE_ADDR;
else
if mem_state_reg = STATE_ADDR then
if pause_in = '0' then
address_var := address_in(31 downto 2);
mem_state_next := STATE_ACCESS;
pause_var := '1';
else
address_var := address_pc;
byte_we_var := "0000";
end if;
else --STATE_ACCESS
if pause_in = '0' then
address_var := address_pc;
opcode_next := next_opcode_reg;
mem_state_next := STATE_ADDR;
byte_we_var := "0000";
else
address_var := address_in(31 downto 2);
byte_we_var := "0000";
end if;
end if;
end if;
if nullify_op = '1' and pause_in = '0' then
opcode_next := ZERO; --NOP after beql
end if;
if reset_in = '1' then
mem_state_reg <= STATE_ADDR;
opcode_reg <= ZERO;
next_opcode_reg <= ZERO;
address_reg <= ZERO(31 downto 2);
byte_we_reg <= "0000";
elsif rising_edge(clk) then
if pause_in = '0' then
address_reg <= address_var;
byte_we_reg <= byte_we_var;
mem_state_reg <= mem_state_next;
opcode_reg <= opcode_next;
if mem_state_reg = STATE_ADDR then
next_opcode_reg <= data_r;
end if;
end if;
end if;
opcode_out <= opcode_reg;
data_read <= data_read_var;
pause_out <= pause_var;
address_next <= address_var;
byte_we_next <= byte_we_var;
address <= address_reg;
byte_we <= byte_we_reg;
data_w <= data_write_var;
end process; --data_proc
end; --architecture logic
|
mit
|
andrewandrepowell/axiplasma
|
hdl/projects/VC707/bd/mig_wrap/ip/mig_wrap_proc_sys_reset_1_0/mig_wrap_proc_sys_reset_1_0_stub.vhdl
|
1
|
1853
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Mar 31 18:24:55 2017
-- Host : LAPTOP-IQ9G3D1I running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top mig_wrap_proc_sys_reset_1_0 -prefix
-- mig_wrap_proc_sys_reset_1_0_ mig_wrap_proc_sys_reset_0_0_stub.vhdl
-- Design : mig_wrap_proc_sys_reset_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7vx485tffg1761-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mig_wrap_proc_sys_reset_1_0 is
Port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end mig_wrap_proc_sys_reset_1_0;
architecture stub of mig_wrap_proc_sys_reset_1_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "proc_sys_reset,Vivado 2016.4";
begin
end;
|
mit
|
andrewandrepowell/axiplasma
|
hdl/plasoc/plasoc_timer_axi4_write_cntrl.vhd
|
1
|
6980
|
-------------------------------------------------------
--! @author Andrew Powell
--! @date January 31, 2017
--! @brief Contains the entity and architecture of the
--! Timer Core's Slave AXI4-Lite Write Controller.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.plasoc_timer_pack.all;
--! The Write Controller implements a Slave AXI4-Lite Write
--! interface in order to allow a Master interface to write to
--! the registers of the core.
--!
--! Information specific to the AXI4-Lite
--! protocol is excluded from this documentation since the information can
--! be found in official ARM AMBA4 AXI documentation.
entity plasoc_timer_axi4_write_cntrl is
generic (
-- AXI4-Lite parameters.
axi_address_width : integer := 16; --! Defines the AXI4-Lite Address Width.
axi_data_width : integer := 32; --! Defines the AXI4-Lite Data Width.
-- Register interface.
reg_control_offset : std_logic_vector := X"0000"; --! Defines the offset for the Control register.
reg_trig_value_offset : std_logic_vector := X"0004" --! Defines the offset for the Trigger Value register.
);
port (
-- Global interface.
aclk : in std_logic; --! Clock. Tested with 50 MHz.
aresetn : in std_logic; --! Reset on low.
-- Slave AXI4-Lite Write interface.
axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Write signal.
axi_awprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Write signal.
axi_awvalid : in std_logic; --! AXI4-Lite Address Write signal.
axi_awready : out std_logic; --! AXI4-Lite Address Write signal.
axi_wvalid : in std_logic; --! AXI4-Lite Write Data signal.
axi_wready : out std_logic; --! AXI4-Lite Write Data signal.
axi_wdata : in std_logic_vector(axi_data_width-1 downto 0); --! AXI4-Lite Write Data signal.
axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0); --! AXI4-Lite Write Data signal.
axi_bvalid : out std_logic; --! AXI4-Lite Write Response signal.
axi_bready : in std_logic; --! AXI4-Lite Write Response signal.
axi_bresp : out std_logic_vector(1 downto 0); --! AXI4-Lite Write Response signal.
-- Register interface.
reg_control : out std_logic_vector(axi_data_width-1 downto 0); --! Control register.
reg_trig_value : out std_logic_vector(axi_data_width-1 downto 0); --! Trigger Value register.
reg_valid : out std_logic := '0' --! When high, enables writing of the Control register.
);
end plasoc_timer_axi4_write_cntrl;
architecture Behavioral of plasoc_timer_axi4_write_cntrl is
type state_type is (state_wait,state_write,state_response);
signal state : state_type := state_wait;
signal axi_awready_buff : std_logic := '0';
signal axi_awaddr_buff : std_logic_vector(axi_address_width-1 downto 0);
signal axi_wready_buff : std_logic := '0';
signal axi_bvalid_buff : std_logic := '0';
begin
axi_awready <= axi_awready_buff;
axi_wready <= axi_wready_buff;
axi_bvalid <= axi_bvalid_buff;
axi_bresp <= axi_resp_okay;
-- Drive the axi write interface.
process (aclk)
begin
-- Perform operations on the clock's positive edge.
if rising_edge(aclk) then
if aresetn='0' then
axi_awready_buff <= '0';
axi_wready_buff <= '0';
axi_bvalid_buff <= '0';
reg_control <= (others=>'0');
reg_trig_value <= (others=>'0');
reg_valid <= '0';
state <= state_wait;
else
-- Drive state machine.
case state is
-- WAIT mode.
when state_wait=>
-- Sample address interface on handshake and go start
-- performing the write operation.
if axi_awvalid='1' and axi_awready_buff='1' then
-- Prevent the master from sending any more control information.
axi_awready_buff <= '0';
-- Sample the address sent from the master.
axi_awaddr_buff <= axi_awaddr;
-- Begin to read data to write.
axi_wready_buff <= '1';
state <= state_write;
-- Let the master interface know the slave is ready
-- to receive address information.
else
axi_awready_buff <= '1';
end if;
-- WRITE mode.
when state_write=>
-- Wait for handshake.
if axi_wvalid='1' and axi_wready_buff='1' then
-- Send valid signal indicating new data may be
-- available.
reg_valid <= '1';
-- Prevent the master from sending any more data.
axi_wready_buff <= '0';
-- Only sample the specified bytes.
for each_byte in 0 to axi_data_width/8-1 loop
if axi_wstrb(each_byte)='1' then
-- Only sample written data if the address is valid.
if axi_awaddr_buff=reg_control_offset then
reg_control(7+each_byte*8 downto each_byte*8) <=
axi_wdata(7+each_byte*8 downto each_byte*8);
elsif axi_awaddr_buff=reg_trig_value_offset then
reg_trig_value(7+each_byte*8 downto each_byte*8) <=
axi_wdata(7+each_byte*8 downto each_byte*8);
end if;
end if;
end loop;
-- Begin to transmit the response.
state <= state_response;
axi_bvalid_buff <= '1';
end if;
-- RESPONSE mode.
when state_response=>
-- Since no new information is available, lower the valid signal.
reg_valid <= '0';
-- Wait for handshake.
if axi_bvalid_buff='1' and axi_bready='1' then
-- Starting waiting for more address information on
-- successful handshake.
axi_bvalid_buff <= '0';
state <= state_wait;
end if;
end case;
end if;
end if;
end process;
end Behavioral;
|
mit
|
andrewandrepowell/axiplasma
|
hdl/plasoc/plasoc_uart.vhd
|
1
|
13682
|
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 14, 2017
--! @brief Contains the entity and architecture of the
--! Plasma-SoC's UART Core.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.plasoc_uart_pack.all;
--! The Plasma-SoC's Universeral Asynchronous Rceiver and
--! Transmitter is implemented so that the CPU can perform
--! 8N1 serial transactions with a host computer. The serial transactions
--! are useful for printing detailed statuses, debugging problems related
--! to software, and in-circuit serial programming. The UART Core depends
--! on the UART developed by (THE AUTHOR'S NAME AND INFORMATION NEEDS TO BE
--! ADDED LATER) for its essential functionality. In other words, the UART Core
--! acts as a wrapper so that the UART has an Master AXI4-Lite interface and
--! and interruption capabilities.
--!
--! The UART Core behaves like any other UART. In order to take advantage of
--! this core, the CPU must read and write to the core's register space. The
--! Control register doesn't actually require any configuration. Instead, the
--! control bits Status In Avail and Status Out Avail indicate the status of the
--! UART Core. If Status In Avail is high, then 8-bit data is available in the In Fifo
--! register. If Status Out Avail is high, then 8-bit data can be written to the Out
--! Fifo Avail register. Both the In Fifo Avail and Out Fifo Avail registers have a width
--! of axi_data_width, however the data is always the least significant bits.
--!
--! Information specific to the AXI4-Lite
--! protocol is excluded from this documentation since the information can
--! be found in official ARM AMBA4 AXI documentation.
entity plasoc_uart is
generic (
fifo_depth : integer := 8; --! Defines the number of 8-bit words that can be bufferred for each of the respective input and output queues.
axi_address_width : integer := 16; --! Defines the AXI4-Lite Address Width.
axi_data_width : integer := 32; --! Defines the AXI4-Lite Data Width.
axi_control_offset : integer := 0; --! Defines the offset for the Control register.
axi_control_status_in_avail_bit_loc : integer := 0; --! Defines the bit location of Status In Avail in the Control register.
axi_control_status_out_avail_bit_loc : integer := 1; --! Defines the bit location of Status Out Avail in the Control register.
axi_in_fifo_offset : integer := 4; --! Defines the offset of the In Fifo register.
axi_out_fifo_offset : integer := 8; --! Defines the offset of the Out Fifo register.
baud : positive := 115200; --! The baud rate of the UART.
clock_frequency : positive := 50000000 --! The frequency of the input clock aclk.
);
port (
-- Global interface.
aclk : in std_logic; --! Clock. Tested with 50 MHz.
aresetn : in std_logic; --! Reset on low. Technically supposed to be asynchronous, however asynchronous resets aren't used.
-- Slave AXI4-Lite Write interface.
axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Write signal.
axi_awprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Write signal.
axi_awvalid : in std_logic; --! AXI4-Lite Address Write signal.
axi_awready : out std_logic; --! AXI4-Lite Address Write signal.
axi_wvalid : in std_logic; --! AXI4-Lite Write Data signal.
axi_wready : out std_logic; --! AXI4-Lite Write Data signal.
axi_wdata : in std_logic_vector(axi_data_width-1 downto 0); --! AXI4-Lite Write Data signal.
axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0); --! AXI4-Lite Write Data signal.
axi_bvalid : out std_logic; --! AXI4-Lite Write Response signal.
axi_bready : in std_logic; --! AXI4-Lite Write Response signal.
axi_bresp : out std_logic_vector(1 downto 0); --! AXI4-Lite Write Response signal.
-- Slave AXI4-Lite Read interface.
axi_araddr : in std_logic_vector(axi_address_width-1 downto 0); --! AXI4-Lite Address Read signal.
axi_arprot : in std_logic_vector(2 downto 0); --! AXI4-Lite Address Read signal.
axi_arvalid : in std_logic; --! AXI4-Lite Address Read signal.
axi_arready : out std_logic; --! AXI4-Lite Address Read signal.
axi_rdata : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0'); --! AXI4-Lite Read Data signal.
axi_rvalid : out std_logic; --! AXI4-Lite Read Data signal.
axi_rready : in std_logic; --! AXI4-Lite Read Data signal.
axi_rresp : out std_logic_vector(1 downto 0); --! AXI4-Lite Read Data signal.
-- UART interface.
tx : out std_logic; --! Serially sends bits at the rate approximately equal to the baud. The communication protocol is always 8N1.
rx : in std_logic; --! Serially receives bits at the rate approximately equal to the baud. The communication protocol should always be 8N1.
-- CPU interface.
status_in_avail : out std_logic --! A signal indicating the state of the Status In Avail bit in the Control register. This signal can be used to interrupt the CPU.
);
end plasoc_uart;
architecture Behavioral of plasoc_uart is
component uart is
generic (
baud : positive;
clock_frequency : positive
);
port (
clock : in std_logic;
nreset : in std_logic;
data_stream_in : in std_logic_vector(7 downto 0);
data_stream_in_stb : in std_logic;
data_stream_in_ack : out std_logic;
data_stream_out : out std_logic_vector(7 downto 0);
data_stream_out_stb : out std_logic;
tx : out std_logic;
rx : in std_logic
);
end component;
component plasoc_uart_axi4_write_cntrl is
generic (
fifo_depth : integer := 8;
axi_address_width : integer := 16;
axi_data_width : integer := 32;
reg_control_offset : std_logic_vector := X"0000";
reg_control_status_in_avail_bit_loc : integer := 0;
reg_control_status_out_avail_bit_loc : integer := 1;
reg_in_fifo_offset : std_logic_vector := X"0004";
reg_out_fifo_offset : std_logic_vector := X"0008");
port (
aclk : in std_logic;
aresetn : in std_logic;
axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0);
axi_awprot : in std_logic_vector(2 downto 0);
axi_awvalid : in std_logic;
axi_awready : out std_logic;
axi_wvalid : in std_logic;
axi_wready : out std_logic;
axi_wdata : in std_logic_vector(axi_data_width-1 downto 0);
axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0);
axi_bvalid : out std_logic;
axi_bready : in std_logic;
axi_bresp : out std_logic_vector(1 downto 0);
reg_out_fifo : out std_logic_vector(7 downto 0);
reg_out_fifo_valid : out std_logic;
reg_out_fifo_ready : in std_logic;
reg_in_avail : out std_logic);
end component;
component plasoc_uart_axi4_read_cntrl is
generic (
fifo_depth : integer := 8;
axi_address_width : integer := 16;
axi_data_width : integer := 32;
reg_control_offset : std_logic_vector := X"0000";
reg_control_status_in_avail_bit_loc : integer := 0;
reg_control_status_out_avail_bit_loc : integer := 1;
reg_in_fifo_offset : std_logic_vector := X"0004";
reg_out_fifo_offset : std_logic_vector := X"0008");
port (
aclk : in std_logic;
aresetn : in std_logic;
axi_araddr : in std_logic_vector(axi_address_width-1 downto 0);
axi_arprot : in std_logic_vector(2 downto 0);
axi_arvalid : in std_logic;
axi_arready : out std_logic;
axi_rdata : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0');
axi_rvalid : out std_logic;
axi_rready : in std_logic;
axi_rresp : out std_logic_vector(1 downto 0);
reg_control_status_in_avail : out std_logic;
reg_control_status_out_avail : in std_logic;
reg_in_fifo : in std_logic_vector(7 downto 0);
reg_in_valid : in std_logic;
reg_in_ready : out std_logic);
end component;
constant axi_control_offset_slv : std_logic_vector := std_logic_vector(to_unsigned(axi_control_offset,axi_address_width));
constant axi_in_fifo_offset_slv : std_logic_vector := std_logic_vector(to_unsigned(axi_in_fifo_offset,axi_address_width));
constant axi_out_fifo_offset_slv : std_logic_vector := std_logic_vector(to_unsigned(axi_out_fifo_offset,axi_address_width));
signal out_fifo : std_logic_vector(7 downto 0);
signal out_fifo_valid : std_logic;
signal out_fifo_ready : std_logic;
signal in_fifo : std_logic_vector(7 downto 0);
signal in_fifo_valid : std_logic;
signal in_fifo_ready : std_logic;
signal reg_in_avail : std_logic;
begin
uart_inst : uart
generic map (
baud => baud,
clock_frequency => clock_frequency)
port map (
clock => aclk,
nreset => aresetn,
data_stream_in => out_fifo,
data_stream_in_stb => out_fifo_valid,
data_stream_in_ack => out_fifo_ready,
data_stream_out => in_fifo,
data_stream_out_stb => in_fifo_valid,
tx => tx, rx => rx);
plasoc_uart_axi4_write_cntrl_inst : plasoc_uart_axi4_write_cntrl
generic map (
fifo_depth => fifo_depth,
axi_address_width => axi_address_width,
axi_data_width => axi_data_width,
reg_control_offset => axi_control_offset_slv,
reg_control_status_in_avail_bit_loc => axi_control_status_in_avail_bit_loc,
reg_control_status_out_avail_bit_loc => axi_control_status_out_avail_bit_loc,
reg_in_fifo_offset => axi_in_fifo_offset_slv,
reg_out_fifo_offset => axi_out_fifo_offset_slv)
port map (
aclk => aclk,
aresetn => aresetn,
axi_awaddr => axi_awaddr,
axi_awprot => axi_awprot,
axi_awvalid => axi_awvalid,
axi_awready => axi_awready,
axi_wvalid => axi_wvalid,
axi_wready => axi_wready,
axi_wdata => axi_wdata,
axi_wstrb => axi_wstrb,
axi_bvalid => axi_bvalid,
axi_bready => axi_bready,
axi_bresp => axi_bresp,
reg_out_fifo => out_fifo,
reg_out_fifo_valid => out_fifo_valid,
reg_out_fifo_ready => out_fifo_ready,
reg_in_avail => reg_in_avail);
plasoc_uart_axi4_read_cntrl_inst : plasoc_uart_axi4_read_cntrl
generic map (
fifo_depth => fifo_depth,
axi_address_width => axi_address_width,
axi_data_width => axi_data_width,
reg_control_offset => axi_control_offset_slv,
reg_control_status_in_avail_bit_loc => axi_control_status_in_avail_bit_loc,
reg_control_status_out_avail_bit_loc => axi_control_status_out_avail_bit_loc,
reg_in_fifo_offset => axi_in_fifo_offset_slv,
reg_out_fifo_offset => axi_out_fifo_offset_slv)
port map (
aclk => aclk,
aresetn => aresetn,
axi_araddr => axi_araddr,
axi_arprot => axi_arprot,
axi_arvalid => axi_arvalid,
axi_arready => axi_arready,
axi_rdata => axi_rdata,
axi_rvalid => axi_rvalid,
axi_rready => axi_rready,
axi_rresp => axi_rresp,
reg_control_status_in_avail => status_in_avail,
reg_control_status_out_avail => reg_in_avail,
reg_in_fifo => in_fifo,
reg_in_valid => in_fifo_valid,
reg_in_ready => in_fifo_ready);
end Behavioral;
|
mit
|
VLSI-EDA/UVVM_All
|
bitvis_vip_i2c/src/i2c_bfm_pkg.vhd
|
2
|
101677
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
--
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
--=================================================================================================
package i2c_bfm_pkg is
--===============================================================================================
-- Types and constants for I2C BFMs
--===============================================================================================
constant C_SCOPE : string := "I2C BFM";
constant C_READ_BIT : std_logic := '1';
constant C_WRITE_BIT : std_logic := '0';
type t_i2c_if is record
scl : std_logic; -- clock
sda : std_logic; -- data
end record;
-- Configuration record to be assigned in the test harness.
type t_i2c_bfm_config is
record
enable_10_bits_addressing : boolean; -- true: 10-bit addressing enabled, false : 7-bit addressing enabled
master_sda_to_scl : time; -- Used in master mode, start condition. From sda active to scl active.
master_scl_to_sda : time; -- Used in master mode, stop condition. From scl inactive to sda inactive.
master_stop_condition_hold_time : time; -- Used in master methods for holding the stop condition. Ensures that the master holds the stop condition for a certain amount of time before the next operation is started.
max_wait_scl_change : time; -- Used as timeout when checking the SCL active period.
max_wait_scl_change_severity : t_alert_level; -- The above timeout will have this severity.
max_wait_sda_change : time; -- Used when receiving and in slave transmit.
max_wait_sda_change_severity : t_alert_level; -- The above timeout will have this severity.
i2c_bit_time : time; -- The bit period.
i2c_bit_time_severity : t_alert_level; -- A master method will report an alert with this severity if a slave performs clock stretching for longer than i2c_bit_time.
acknowledge_severity : t_alert_level; -- Severity if message not acknowledged
slave_mode_address : unsigned(9 downto 0); -- The slave methods expect to receive this address from the I2C master DUT.
slave_mode_address_severity : t_alert_level; -- The methods will report an alert with this severity if the address format is wrong or the address is not as expected.
slave_rw_bit_severity : t_alert_level; -- The methods will report an alert with this severity if the Read/Write bit is not as expected.
reserved_address_severity : t_alert_level; -- The methods will trigger an alert with this severity if the slave address is equal to one of the reserved addresses from the NXP I2C Specification. For a list of reserved addresses, please see the document referred to in section 3.
id_for_bfm : t_msg_id; -- The message ID used as a general message ID in the I2C BFM.
id_for_bfm_wait : t_msg_id; -- The message ID used for logging waits in the I2C BFM.
id_for_bfm_poll : t_msg_id; -- The message ID used for logging polling in the I2C BFM.
end record;
constant C_I2C_BFM_CONFIG_DEFAULT : t_i2c_bfm_config := (
enable_10_bits_addressing => false,
master_sda_to_scl => 20 ns,
master_scl_to_sda => 20 ns,
master_stop_condition_hold_time => 20 ns,
max_wait_scl_change => 10 ms,
max_wait_scl_change_severity => failure,
max_wait_sda_change => 10 ms,
max_wait_sda_change_severity => failure,
i2c_bit_time => -1 ns,
i2c_bit_time_severity => failure,
acknowledge_severity => failure,
slave_mode_address => "0000000000",
slave_mode_address_severity => failure,
slave_rw_bit_severity => failure,
reserved_address_severity => warning,
id_for_bfm => ID_BFM,
id_for_bfm_wait => ID_BFM_WAIT,
id_for_bfm_poll => ID_BFM_POLL
);
--===============================================================================================
-- BFM procedures
--===============================================================================================
------------------------------------------
-- init_i2c_if_signals
------------------------------------------
-- - This function returns an I2C interface with initialized signals.
-- - All I2C signals are initialized to Z
function init_i2c_if_signals (
constant VOID : in t_void
) return t_i2c_if;
------------------------------------------
-- i2c_master_transmit
------------------------------------------
-- This procedure transmits data 'data' to an I2C slave DUT
-- at address 'addr_value'.
procedure i2c_master_transmit (
constant addr_value : in unsigned;
constant data : in t_byte_array;
constant msg : in string;
signal scl : inout std_logic;
signal sda : inout std_logic;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- i2c_master_transmit
------------------------------------------
-- This procedure transmits data 'data' to an I2C slave DUT
-- at address 'addr_value'.
-- The I2C interface in this procedure is given as a t_i2c_if signal record
procedure i2c_master_transmit (
constant addr_value : in unsigned;
constant data : in t_byte_array;
constant msg : in string;
signal i2c_if : inout t_i2c_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- i2c_master_transmit
------------------------------------------
-- This procedure transmits data 'data' to an I2C slave DUT
-- at address 'addr_value'.
-- The I2C interface in this procedure is given as a t_i2c_if signal record
procedure i2c_master_transmit (
constant addr_value : in unsigned;
constant data : in std_logic_vector;
constant msg : in string;
signal i2c_if : inout t_i2c_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- i2c_slave_transmit
------------------------------------------
-- This procedure transmits data 'data' to an I2C master DUT.
procedure i2c_slave_transmit (
constant data : in t_byte_array;
constant msg : in string;
signal scl : inout std_logic;
signal sda : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- i2c_slave_transmit
------------------------------------------
-- This procedure transmits data 'data' to an I2C master DUT.
-- The I2C interface in this procedure is given as a t_i2c_if signal record
procedure i2c_slave_transmit (
constant data : in t_byte_array;
constant msg : in string;
signal i2c_if : inout t_i2c_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- i2c_slave_transmit
------------------------------------------
-- This procedure transmits data 'data' to an I2C master DUT.
-- The I2C interface in this procedure is given as a t_i2c_if signal record
procedure i2c_slave_transmit (
constant data : in std_logic_vector;
constant msg : in string;
signal i2c_if : inout t_i2c_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- i2c_master_receive
------------------------------------------
-- This procedure receives data 'data' from an I2C slave DUT
-- at address 'addr_value'.
procedure i2c_master_receive (
constant addr_value : in unsigned;
variable data : out t_byte_array;
constant msg : in string;
signal scl : inout std_logic;
signal sda : inout std_logic;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like .._check
);
------------------------------------------
-- i2c_master_receive
------------------------------------------
-- This procedure receives data 'data' from an I2C slave DUT
-- at address 'addr_value'.
-- The I2C interface in this procedure is given as a t_i2c_if signal record
procedure i2c_master_receive (
constant addr_value : in unsigned;
variable data : out t_byte_array;
constant msg : in string;
signal i2c_if : inout t_i2c_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like .._check
);
------------------------------------------
-- i2c_master_receive
------------------------------------------
-- This procedure receives data 'data' from an I2C slave DUT
-- at address 'addr_value'.
-- The I2C interface in this procedure is given as a t_i2c_if signal record
procedure i2c_master_receive (
constant addr_value : in unsigned;
variable data : out std_logic_vector;
constant msg : in string;
signal i2c_if : inout t_i2c_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like .._check
);
------------------------------------------
-- i2c_slave_receive
------------------------------------------
-- This procedure receives data 'data' from an I2C master DUT.
-- at address 'addr_value'.
procedure i2c_slave_receive (
variable data : out t_byte_array;
constant msg : in string;
signal scl : inout std_logic;
signal sda : inout std_logic;
constant exp_rw_bit : in std_logic := C_WRITE_BIT;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like .._check
);
------------------------------------------
-- i2c_slave_receive
------------------------------------------
-- This procedure receives data 'data' from an I2C master DUT.
-- The I2C interface in this procedure is given as a t_i2c_if signal record
procedure i2c_slave_receive (
variable data : out t_byte_array;
constant msg : in string;
signal i2c_if : inout t_i2c_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like .._check
);
------------------------------------------
-- i2c_slave_receive
------------------------------------------
-- This procedure receives data 'data' from an I2C master DUT.
-- The I2C interface in this procedure is given as a t_i2c_if signal record
procedure i2c_slave_receive (
variable data : out std_logic_vector;
constant msg : in string;
signal i2c_if : inout t_i2c_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like .._check
);
------------------------------------------
-- i2c_master_check
------------------------------------------
-- This procedure receives an I2C transaction from an I2C slave DUT at address
-- 'addr_value', and compares the read data to the expected data in 'data_exp'.
-- If the read data is inconsistent with the expected data, an alert with
-- severity 'alert_level' is triggered.
-- The I2C interface in this procedure is given as individual signals
procedure i2c_master_check (
constant addr_value : in unsigned;
constant data_exp : in t_byte_array;
constant msg : in string;
signal scl : inout std_logic;
signal sda : inout std_logic;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- i2c_master_check
------------------------------------------
-- This procedure receives an I2C transaction from an I2C slave DUT at address
-- 'addr_value', and compares the read data to the expected data in 'data_exp'.
-- If the read data is inconsistent with the expected data, an alert with
-- severity 'alert_level' is triggered.
-- The I2C interface in this procedure is given as a t_i2c_if signal record
procedure i2c_master_check (
constant addr_value : in unsigned;
constant data_exp : in t_byte_array;
constant msg : in string;
signal i2c_if : inout t_i2c_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- i2c_master_check
------------------------------------------
-- This procedure receives an I2C transaction from an I2C slave DUT at address
-- 'addr_value', and compares the read data to the expected data in 'data_exp'.
-- If the read data is inconsistent with the expected data, an alert with
-- severity 'alert_level' is triggered.
-- The I2C interface in this procedure is given as a t_i2c_if signal record
procedure i2c_master_check (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal i2c_if : inout t_i2c_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- i2c_slave_check
------------------------------------------
-- This procedure receives an I2C transaction from an I2C master DUT,
-- and compares the read data to the expected data in 'data_exp'.
-- If the read data is inconsistent with the expected data, an alert with
-- severity 'alert_level' is triggered.
-- The I2C interface in this procedure is given as individual signals
procedure i2c_slave_check (
constant data_exp : in t_byte_array;
constant msg : in string;
signal scl : inout std_logic;
signal sda : inout std_logic;
constant exp_rw_bit : in std_logic := C_WRITE_BIT;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- i2c_slave_check
------------------------------------------
-- This procedure receives an I2C transaction from an I2C master DUT,
-- and compares the read data to the expected data in 'data_exp'.
-- If the read data is inconsistent with the expected data, an alert with
-- severity 'alert_level' is triggered.
-- The I2C interface in this procedure is given as a t_i2c_if signal record
procedure i2c_slave_check (
constant data_exp : in t_byte_array;
constant msg : in string;
signal i2c_if : inout t_i2c_if;
constant exp_rw_bit : in std_logic := C_WRITE_BIT;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- i2c_slave_check
------------------------------------------
-- This procedure receives an I2C transaction from an I2C master DUT,
-- and compares the read data to the expected data in 'data_exp'.
-- If the read data is inconsistent with the expected data, an alert with
-- severity 'alert_level' is triggered.
-- The I2C interface in this procedure is given as a t_i2c_if signal record
procedure i2c_slave_check (
constant data_exp : in std_logic_vector;
constant msg : in string;
signal i2c_if : inout t_i2c_if;
constant exp_rw_bit : in std_logic := C_WRITE_BIT;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT
);
procedure i2c_master_quick_command (
constant addr_value : in unsigned;
constant msg : in string;
signal i2c_if : inout t_i2c_if;
constant rw_bit : in std_logic := C_WRITE_BIT;
constant exp_ack : in boolean := true;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT
);
end package i2c_bfm_pkg;
--=================================================================================================
--=================================================================================================
package body i2c_bfm_pkg is
---------------------------------------------------------------------------------
-- check slave address
--
-- Compares slave address with known reserved addresses and triggers an alert
-- if equal. Input is a slave address, either 7-bit or 10-bit. Make sure that
-- the correct length address is input to this procedure, i.e., that a 10-bit
-- value is not sent in when the BFM is in 7-bit address mode.
---------------------------------------------------------------------------------
procedure i2c_check_slave_addr(
constant addr_value : in unsigned;
constant alert_level : t_alert_level;
constant scope : in string := C_TB_SCOPE_DEFAULT
) is
constant C_SCOPE : string := scope & ": i2c_check_slave_addr()";
constant head : string := "This address is reserved for ";
constant tail : string := ". Only use this address if you are certain " &
"that the address is never going to be used " &
"for its intended purpose. See I2C-bus specification Rev. 6 " &
"for more information.";
alias a_addr_value : unsigned(6 downto 0) is addr_value(6 downto 0);
begin
if addr_value'length = 7 then
if a_addr_value(6 downto 2) = "00000" then
case a_addr_value(1 downto 0) is
when "00" =>
-- general call (rw = 0)
-- START byte (rw = 1)
alert(alert_level, head & "general call and START byte" & tail, C_SCOPE);
when "01" =>
-- cbus addr
alert(alert_level, head & "CBUS address" & tail, C_SCOPE);
when "10" =>
-- reserved for different bus format
alert(alert_level, head & "different bus format" & tail, C_SCOPE);
when "11" =>
-- reserved for future purposes
alert(alert_level, head & "future purposes" & tail, C_SCOPE);
when others =>
null;
end case;
elsif a_addr_value(6 downto 2) = "00001" then
-- Hs-mode master code
alert(alert_level, head & "High-speed mode (Hs-mode) master code" & tail, C_SCOPE);
elsif a_addr_value(6 downto 2) = "11111" then
-- device ID
alert(alert_level, head & "device ID" & tail, C_SCOPE);
elsif a_addr_value(6 downto 2) = "11110" then
-- 10-bit-addressing
alert(alert_level, head & "10-bit-addressing" & tail, C_SCOPE);
else
-- do nothing
end if;
elsif addr_value'length = 10 then
-- do nothing
else
alert(error, "Invalid address length!", C_SCOPE);
end if;
end procedure;
---------------------------------------------------------------------------------
-- initialize i2c to dut signals
---------------------------------------------------------------------------------
function init_i2c_if_signals (
constant VOID : in t_void
) return t_i2c_if is
variable result : t_i2c_if;
begin
result.sda := 'Z';
result.scl := 'Z';
return result;
end function;
---------------------------------------------------------------------------------
-- check_time_window method here since it is local in uvvm_util.methods_pkg
---------------------------------------------------------------------------------
-- check_time_window is used to check if a given condition occurred between
-- min_time and max_time
-- Usage: wait for requested condition until max_time is reached, then call check_time_window().
-- The input 'success' is needed to distinguish between the following cases:
-- - the signal reached success condition at max_time,
-- - max_time was reached with no success condition
procedure check_time_window(
constant success : boolean; -- F.ex target'event, or target=exp
constant elapsed_time : time;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant name : string;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
-- Sanity check
check_value(max_time >= min_time, TB_ERROR, name & " => min_time must be less than max_time." & LF & add_msg_delimiter(msg), scope, ID_NEVER, msg_id_panel, name);
if elapsed_time < min_time then
alert(alert_level, name & " => Failed. Condition occurred too early, after " &
to_string(elapsed_time, C_LOG_TIME_BASE) & ". " & add_msg_delimiter(msg), scope);
elsif success then
log(msg_id, name & " => OK. Condition occurred after " &
to_string(elapsed_time, C_LOG_TIME_BASE) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else -- max_time reached with no success
alert(alert_level, name & " => Failed. Timed out after " &
to_string(max_time, C_LOG_TIME_BASE) & ". " & add_msg_delimiter(msg), scope);
end if;
end;
procedure i2c_master_transmit_single_byte (
constant byte : in std_logic_vector(7 downto 0);
constant msg : in string;
signal scl : inout std_logic;
signal sda : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT
) is
begin
-- check whether config.i2c_bit_time was set probably
check_value(config.i2c_bit_time /= -1 ns, TB_ERROR, "I2C Bit time was not set in config. " & add_msg_delimiter(msg), C_SCOPE, ID_NEVER, msg_id_panel);
-- Time shall be at the falling edge time of SCL.
for i in 7 downto 0 loop
wait for config.i2c_bit_time/4;
if byte(i) = '1' then
sda <= 'Z';
else
sda <= '0';
end if;
wait for config.i2c_bit_time/4;
scl <= 'Z'; -- release
wait for config.i2c_bit_time/2;
-- check for clock stretching
await_value(scl, '1', MATCH_STD, 0 ns, config.i2c_bit_time, config.i2c_bit_time_severity, msg, scope, ID_NEVER, msg_id_panel);
scl <= '0';
end loop;
end procedure;
procedure i2c_master_receive_single_byte (
variable byte : out std_logic_vector(7 downto 0);
constant msg : in string;
signal scl : inout std_logic;
signal sda : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT
) is
begin
-- check whether config.i2c_bit_time was set probably
check_value(config.i2c_bit_time /= -1 ns, TB_ERROR, "I2C Bit time was not set in config. " & add_msg_delimiter(msg), C_SCOPE, ID_NEVER, msg_id_panel);
-- Time shall be at the falling edge time of SCL.
for i in 7 downto 0 loop
wait for config.i2c_bit_time/2;
scl <= 'Z'; -- release
-- check for clock stretching
await_value(scl, '1', MATCH_STD, 0 ns, config.max_wait_scl_change, config.max_wait_scl_change_severity, msg, scope, ID_NEVER, msg_id_panel);
byte(i) := to_X01(sda);
wait for config.i2c_bit_time/2;
scl <= '0';
end loop;
end procedure;
procedure i2c_master_set_ack (
constant ack : in std_logic;
constant msg : in string;
signal scl : inout std_logic;
signal sda : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT
) is
begin
-- check whether config.i2c_bit_time was set probably
check_value(config.i2c_bit_time /= -1 ns, TB_ERROR, "I2C Bit time was not set in config. " & add_msg_delimiter(msg), C_SCOPE, ID_NEVER, msg_id_panel);
-- Time shall be at the falling edge time of SCL.
wait for config.i2c_bit_time/4;
if ack = '1' then
sda <= 'Z';
else
sda <= '0';
end if;
wait for config.i2c_bit_time/4;
scl <= 'Z'; -- release
wait for config.i2c_bit_time/2;
-- check for clock stretching
await_value(scl, '1', MATCH_STD, 0 ns, config.i2c_bit_time, config.i2c_bit_time_severity, msg, scope, ID_NEVER, msg_id_panel);
scl <= '0';
wait for config.i2c_bit_time/4;
sda <= 'Z'; -- release
end procedure;
procedure i2c_master_check_ack (
constant ack_exp : in std_logic;
constant msg : in string;
signal scl : inout std_logic;
signal sda : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT
) is
begin
-- check whether config.i2c_bit_time was set probably
check_value(config.i2c_bit_time /= -1 ns, TB_ERROR, "I2C Bit time was not set in config. " & add_msg_delimiter(msg), C_SCOPE, ID_NEVER, msg_id_panel);
-- Time shall be at the falling edge time of SCL.
-- Check ACK
-- The master shall drive scl during the acknowledge cycle
-- A valid ack is detected when sda is '0'.
wait for config.i2c_bit_time/4;
sda <= 'Z'; -- release
wait for config.i2c_bit_time/4;
scl <= 'Z';
wait for config.i2c_bit_time/4;
check_value(sda, ack_exp, MATCH_STD, config.acknowledge_severity, msg, scope, ID_NEVER, msg_id_panel);
wait for config.i2c_bit_time/4;
-- check for clock stretching
await_value(scl, '1', MATCH_STD, 0 ns, config.i2c_bit_time, config.i2c_bit_time_severity, msg, scope, ID_NEVER, msg_id_panel);
scl <= '0';
end procedure;
procedure i2c_master_check_ack (
variable v_ack_received : out boolean;
constant ack_exp : in std_logic;
constant msg : in string;
signal scl : inout std_logic;
signal sda : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT
) is
begin
-- check whether config.i2c_bit_time was set probably
check_value(config.i2c_bit_time /= -1 ns, TB_ERROR, "I2C Bit time was not set in config. " & add_msg_delimiter(msg), C_SCOPE, ID_NEVER, msg_id_panel);
-- Time shall be at the falling edge time of SCL.
-- Check ACK
-- The master shall drive scl during the acknowledge cycle
-- A valid ack is detected when sda is '0'.
wait for config.i2c_bit_time/4;
sda <= 'Z'; -- release
wait for config.i2c_bit_time/4;
scl <= 'Z';
wait for config.i2c_bit_time/4;
v_ack_received := check_value(sda, ack_exp, MATCH_STD, NO_ALERT, msg, scope, ID_NEVER, msg_id_panel);
wait for config.i2c_bit_time/4;
if v_ack_received then
-- check for clock stretching
await_value(scl, '1', MATCH_STD, 0 ns, config.i2c_bit_time, config.i2c_bit_time_severity, msg, scope, ID_NEVER, msg_id_panel);
end if;
scl <= '0';
end procedure;
procedure i2c_slave_transmit_single_byte (
constant byte : in std_logic_vector(7 downto 0);
constant msg : in string;
signal scl : inout std_logic;
signal sda : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT
) is
begin
-- check whether config.i2c_bit_time was set probably
check_value(config.i2c_bit_time /= -1 ns, TB_ERROR, "I2C Bit time was not set in config. " & add_msg_delimiter(msg), C_SCOPE, ID_NEVER, msg_id_panel);
-- Time shall be at the falling edge time of SCL.
for i in 7 downto 0 loop
wait for config.i2c_bit_time/4;
if byte(i) = '1' then
sda <= 'Z';
else
sda <= '0';
end if;
await_value(scl, '1', MATCH_STD, 0 ns, config.max_wait_scl_change + config.max_wait_scl_change/100, config.max_wait_scl_change_severity, msg, scope, ID_NEVER, msg_id_panel);
await_value(scl, '0', 0 ns, config.max_wait_scl_change + config.max_wait_scl_change/100, config.max_wait_scl_change_severity, msg, scope, ID_NEVER, msg_id_panel);
end loop;
end procedure;
procedure i2c_slave_receive_single_byte (
variable byte : out std_logic_vector(7 downto 0);
constant msg : in string;
signal scl : inout std_logic;
signal sda : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT
) is
begin
-- check whether config.i2c_bit_time was set probably
check_value(config.i2c_bit_time /= -1 ns, TB_ERROR, "I2C Bit time was not set in config. " & add_msg_delimiter(msg), C_SCOPE, ID_NEVER, msg_id_panel);
-- Time shall be at the falling edge time of SCL.
for i in 7 downto 0 loop
await_value(scl, '1', MATCH_STD, 0 ns, config.max_wait_scl_change + config.max_wait_scl_change/100, config.max_wait_scl_change_severity, msg, scope, ID_NEVER, msg_id_panel);
wait for config.i2c_bit_time/4; -- to sample in the middle of the high period
byte(i) := to_X01(sda);
await_value(scl, '0', 0 ns, config.max_wait_scl_change + config.max_wait_scl_change/100, config.max_wait_scl_change_severity, msg, scope, ID_NEVER, msg_id_panel);
end loop;
end procedure;
procedure i2c_slave_set_ack (
constant ack : in std_logic;
constant msg : in string;
signal scl : inout std_logic;
signal sda : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT
) is
begin
-- check whether config.i2c_bit_time was set probably
check_value(config.i2c_bit_time /= -1 ns, TB_ERROR, "I2C Bit time was not set in config. " & add_msg_delimiter(msg), C_SCOPE, ID_NEVER, msg_id_panel);
-- Time shall be at the falling edge time of SCL.
wait for config.i2c_bit_time/4;
if ack = '1' then
sda <= 'Z';
else
sda <= '0';
end if;
await_value(scl, '1', MATCH_STD, 0 ns, config.max_wait_scl_change + config.max_wait_scl_change/100, config.max_wait_scl_change_severity, msg, scope, ID_NEVER, msg_id_panel);
await_value(scl, '0', 0 ns, config.max_wait_scl_change + config.max_wait_scl_change/100, config.max_wait_scl_change_severity, msg, scope, ID_NEVER, msg_id_panel);
wait for config.i2c_bit_time/4;
sda <= 'Z';
end procedure;
procedure i2c_slave_check_ack (
constant ack_exp : in std_logic;
constant msg : in string;
signal scl : inout std_logic;
signal sda : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT
) is
begin
-- check whether config.i2c_bit_time was set probably
check_value(config.i2c_bit_time /= -1 ns, TB_ERROR, "I2C Bit time was not set in config. " & add_msg_delimiter(msg), C_SCOPE, ID_NEVER, msg_id_panel);
-- Time shall be at the falling edge time of SCL.
-- Check ACK
-- The master shall drive scl during the acknowledge cycle
-- A valid ack is detected when sda is '0'.
wait for config.i2c_bit_time/4;
sda <= 'Z'; -- release
await_value(scl, '1', MATCH_STD, 0 ns, config.max_wait_scl_change + config.max_wait_scl_change/100, config.max_wait_scl_change_severity, msg, scope, ID_NEVER, msg_id_panel);
check_value(sda, ack_exp, MATCH_STD, config.acknowledge_severity, msg, scope, ID_NEVER, msg_id_panel);
await_value(scl, '0', 0 ns, config.max_wait_scl_change + config.max_wait_scl_change/100, config.max_wait_scl_change_severity, msg, scope, ID_NEVER, msg_id_panel);
end procedure;
---------------------------------------------------------------------------------
-- i2c_master_transmit
-- alert if size of data doesn't match with how long sda is kept low
---------------------------------------------------------------------------------
procedure i2c_master_transmit (
constant addr_value : in unsigned;
constant data : in t_byte_array;
constant msg : in string;
signal scl : inout std_logic;
signal sda : inout std_logic;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT
) is
constant proc_name : string := "i2c_master_transmit";
constant proc_call : string := proc_name & "(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) &
", " & to_string(data, HEX, AS_IS, INCL_RADIX) & ")";
constant C_10_BIT_ADDRESS_PATTERN : std_logic_vector(4 downto 0) := "11110";
-- Normalize to the 7 bit addr and 8 bit data widths
variable v_normalized_addr : unsigned(9 downto 0) :=
normalize_and_check(addr_value, config.slave_mode_address, ALLOW_NARROWER, "addr", "config.slave_mode_address", msg);
constant C_FIRST_10_BIT_ADDRESS_BITS : std_logic_vector(6 downto 0) := C_10_BIT_ADDRESS_PATTERN & std_logic_vector(v_normalized_addr(9 downto 8));
procedure i2c_master_transmit_single_byte (
constant byte : in std_logic_vector(7 downto 0)
) is
begin
i2c_master_transmit_single_byte(byte, msg, scl, sda, scope, msg_id_panel, config);
end procedure;
procedure i2c_master_check_ack (
constant ack_exp : in std_logic
) is
begin
i2c_master_check_ack(ack_exp, msg, scl, sda, scope, msg_id_panel, config);
end procedure;
begin
-- check whether config.i2c_bit_time was set probably
check_value(config.i2c_bit_time /= -1 ns, TB_ERROR, "I2C Bit time was not set in config. " & add_msg_delimiter(msg), C_SCOPE, ID_NEVER, msg_id_panel);
if not config.enable_10_bits_addressing then
check_value(v_normalized_addr(9 downto 7), unsigned'("000"), config.slave_mode_address_severity,
"Verifying that top slave address bits (9-7) are not set in 7-bit addressing mode.",
scope, HEX_BIN_IF_INVALID, KEEP_LEADING_0, ID_NEVER, msg_id_panel);
i2c_check_slave_addr(v_normalized_addr(6 downto 0), config.reserved_address_severity, scope);
else
i2c_check_slave_addr(v_normalized_addr, config.reserved_address_severity, scope);
end if;
check_value(data'ascending, failure, "Verifying that data is of ascending type.", scope, ID_NEVER, msg_id_panel);
await_value(sda, '1', MATCH_STD, 0 ns, config.max_wait_sda_change, config.max_wait_sda_change_severity, msg, scope, ID_NEVER, msg_id_panel);
await_value(scl, '1', MATCH_STD, 0 ns, config.max_wait_scl_change, config.max_wait_scl_change_severity, msg, scope, ID_NEVER, msg_id_panel);
if to_X01(sda) = '1' and to_X01(scl) = '1' then
-- do the start condition
sda <= '0';
wait for config.master_sda_to_scl;
scl <= '0';
if sda = '0' then
-- Transmit address
if not config.enable_10_bits_addressing then
i2c_master_transmit_single_byte(std_logic_vector(v_normalized_addr(6 downto 0)) & '0'); -- 7 bit address + write bit
else -- 10-bits addressing enabled
-- transmit 11110<addr bit 9><addr bit 8><Write>
i2c_master_transmit_single_byte(C_FIRST_10_BIT_ADDRESS_BITS & '0'); -- Pattern indicating 10-bit addresing + first 2 bits of 10-bit address + write bit
end if;
-- Check ACK
-- The master shall drive scl during the acknowledge cycle
-- A valid ack is detected when sda is '0'.
i2c_master_check_ack('0');
-- If 10-bits addressing is enabled, transmit second address byte.
if config.enable_10_bits_addressing then
i2c_master_transmit_single_byte(std_logic_vector(v_normalized_addr(7 downto 0))); -- LSB of 10-bit address
-- Check ACK
-- The master shall drive scl during the acknowledge cycle
-- A valid ack is detected when sda is '0'.
i2c_master_check_ack('0');
end if;
-- serially shift out data to sda
for i in 0 to data'length - 1 loop
i2c_master_transmit_single_byte(data(i));
-- Check ACK
-- The master shall drive scl during the acknowledge cycle
-- A valid ack is detected when sda is '0'.
i2c_master_check_ack('0');
end loop;
wait for config.i2c_bit_time/4;
if action_when_transfer_is_done = RELEASE_LINE_AFTER_TRANSFER then
-- do the stop condition
sda <= '0';
wait for config.i2c_bit_time/4;
scl <= 'Z';
-- check for clock stretching
await_value(scl, '1', MATCH_STD, 0 ns, config.i2c_bit_time, config.i2c_bit_time_severity, msg, scope, ID_NEVER, msg_id_panel);
wait for config.master_scl_to_sda;
sda <= 'Z';
else -- action_when_transfer_is_done = HOLD_LINE_AFTER_TRANSFER
-- Do not perform the stop condition. Instead release SDA when SCL is low.
-- This will prepare for a repeated start condition.
sda <= 'Z';
wait for config.i2c_bit_time/4;
scl <= 'Z';
-- check for clock stretching
await_value(scl, '1', MATCH_STD, 0 ns, config.i2c_bit_time, config.i2c_bit_time_severity, msg, scope, ID_NEVER, msg_id_panel);
end if;
wait for config.master_stop_condition_hold_time;
end if;
else
alert(error, proc_call & " sda and scl not inactive (high) when wishing to start " & add_msg_delimiter(msg), scope);
end if;
log(config.id_for_bfm, proc_call & "=> " & to_string(data, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
end procedure;
procedure i2c_master_transmit(
constant addr_value : in unsigned;
constant data : in t_byte_array;
constant msg : in string;
signal i2c_if : inout t_i2c_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT
) is
begin
i2c_master_transmit(addr_value, data, msg,
i2c_if.scl, i2c_if.sda, action_when_transfer_is_done,
scope, msg_id_panel, config);
end procedure;
---------------------------------------------------------------------------------
-- i2c_master_transmit
-- alert if size of data doesn't match with how long sda is kept low
---------------------------------------------------------------------------------
procedure i2c_master_transmit (
constant addr_value : in unsigned;
constant data : in std_logic_vector;
constant msg : in string;
signal i2c_if : inout t_i2c_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT
) is
variable v_bfm_tx_data : std_logic_vector(7 downto 0) := (others => '0');
-- Normalize to the 8 bit data width
variable v_normalized_data : std_logic_vector(7 downto 0) :=
normalize_and_check(data, v_bfm_tx_data, ALLOW_NARROWER, "data", "v_bfm_tx_data", msg);
variable v_byte_array : t_byte_array(0 to 0) := (0 => v_normalized_data);
begin
i2c_master_transmit(addr_value, v_byte_array, msg,
i2c_if.scl, i2c_if.sda, action_when_transfer_is_done,
scope, msg_id_panel, config);
end procedure;
---------------------------------------------------------------------------------
-- i2c_slave_transmit
-- alert if size of data doesn't match with how long sda is kept low
---------------------------------------------------------------------------------
procedure i2c_slave_transmit (
constant data : in t_byte_array;
constant msg : in string;
signal scl : inout std_logic;
signal sda : inout std_logic;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT
) is
constant proc_name : string := "i2c_slave_transmit";
constant proc_call : string := proc_name & "(" & to_string(data, HEX, AS_IS, INCL_RADIX) & ")";
variable v_bfm_rx_data : std_logic_vector(7 downto 0) := (others => '0');
variable v_received_addr : unsigned(9 downto 0) := (others => '0');
constant C_10_BIT_ADDRESS_PATTERN : std_logic_vector(4 downto 0) := "11110";
constant C_FIRST_10_BIT_ADDRESS_BITS : std_logic_vector(6 downto 0) := C_10_BIT_ADDRESS_PATTERN & std_logic_vector(config.slave_mode_address(9 downto 8));
procedure i2c_slave_transmit_single_byte (
constant byte : in std_logic_vector(7 downto 0)
) is
begin
i2c_slave_transmit_single_byte(byte, msg, scl, sda, scope, msg_id_panel, config);
end procedure;
procedure i2c_slave_receive_single_byte (
variable byte : out std_logic_vector(7 downto 0)
) is
begin
i2c_slave_receive_single_byte(byte, msg, scl, sda, scope, msg_id_panel, config);
end procedure;
procedure i2c_slave_set_ack (
constant ack : in std_logic
) is
begin
i2c_slave_set_ack(ack, msg, scl, sda, scope, msg_id_panel, config);
end procedure;
procedure i2c_slave_check_ack (
constant ack_exp : in std_logic
) is
begin
i2c_slave_check_ack(ack_exp, msg, scl, sda, scope, msg_id_panel, config);
end procedure;
begin
if not config.enable_10_bits_addressing then
check_value(config.slave_mode_address(9 downto 7), unsigned'("000"), config.slave_mode_address_severity,
"Verifying that top slave address bits (9-7) are not set in 7-bit addressing mode.",
scope, HEX_BIN_IF_INVALID, KEEP_LEADING_0, ID_NEVER, msg_id_panel);
i2c_check_slave_addr(config.slave_mode_address(6 downto 0), config.reserved_address_severity, scope);
else
i2c_check_slave_addr(config.slave_mode_address, config.reserved_address_severity, scope);
end if;
check_value(data'ascending, failure, "Verifying that data is of ascending type.", scope, ID_NEVER, msg_id_panel);
await_value(sda, '1', MATCH_STD, 0 ns, config.max_wait_sda_change, config.max_wait_sda_change_severity, msg, scope, ID_NEVER, msg_id_panel);
await_value(scl, '1', MATCH_STD, 0 ns, config.max_wait_scl_change, config.max_wait_scl_change_severity, msg, scope, ID_NEVER, msg_id_panel);
if to_X01(sda) = '1' and to_X01(scl) = '1' then
-- await the start condition
await_value(sda, '0', 0 ns, config.max_wait_sda_change + config.max_wait_sda_change/100, config.max_wait_sda_change_severity, msg, scope, ID_NEVER, msg_id_panel);
await_value(scl, '0', 0 ns, config.max_wait_scl_change + config.max_wait_scl_change/100, config.max_wait_scl_change_severity, msg, scope, ID_NEVER, msg_id_panel);
if sda = '0' then
if not config.enable_10_bits_addressing then
-- receive the address bits
i2c_slave_receive_single_byte(v_bfm_rx_data);
v_received_addr(6 downto 0) := unsigned(v_bfm_rx_data(7 downto 1));
-- Check R/W bit
check_value(v_bfm_rx_data(0), '1', config.slave_rw_bit_severity, msg, scope, ID_NEVER, msg_id_panel);
-- Set ACK/NACK based on address
-- The master shall drive scl during the acknowledge cycle
-- A valid ack is detected when sda is '0'.
if v_received_addr = config.slave_mode_address then
-- ACK
i2c_slave_set_ack('0');
else
-- NACK
alert(config.slave_mode_address_severity, proc_call & " wrong slave address!" &
" Expected: " & to_string(config.slave_mode_address, BIN, KEEP_LEADING_0) &
", Got: " & to_string(v_received_addr, BIN, KEEP_LEADING_0) & add_msg_delimiter(msg), scope);
return;
end if;
else -- 10 bit addressing
-- receive the first byte, consisting of "11110<bit 9><bit 8><write>"
i2c_slave_receive_single_byte(v_bfm_rx_data);
v_received_addr(9 downto 8) := unsigned(v_bfm_rx_data(2 downto 1));
-- Check R/W bit
check_value(v_bfm_rx_data(0), '0', config.slave_rw_bit_severity, msg & ": checking R/W bit after first address byte (10-bit addressing)", scope, ID_NEVER, msg_id_panel);
-- Set ACK/NACK based on first received byte
-- The master shall drive scl during the acknowledge cycle
-- A valid ack is detected when sda is '0'.
if v_bfm_rx_data(7 downto 1) = C_FIRST_10_BIT_ADDRESS_BITS then
-- ACK
i2c_slave_set_ack('0');
else
-- NACK
alert(config.slave_mode_address_severity, proc_call & " first byte was other than expected! " & add_msg_delimiter(msg), scope);
return;
end if;
-- Receive LSB of 10-bit address
i2c_slave_receive_single_byte(v_bfm_rx_data);
v_received_addr(7 downto 0) := unsigned(v_bfm_rx_data);
-- Set ACK/NACK based on address
-- The master shall drive scl during the acknowledge cycle
-- A valid ack is detected when sda is '0'.
if v_received_addr = config.slave_mode_address then
-- ACK
i2c_slave_set_ack('0');
else
-- NACK
alert(config.slave_mode_address_severity, proc_call & " wrong slave address!" &
" Expected: " & to_string(config.slave_mode_address, BIN, KEEP_LEADING_0) &
", Got: " & to_string(v_received_addr, BIN, KEEP_LEADING_0) & add_msg_delimiter(msg), scope);
return;
end if;
-- Expect repeated start condition
sda <= 'Z'; -- other side should drive now
await_value(scl, '1', MATCH_STD, 0 ns, config.max_wait_scl_change + config.max_wait_scl_change/100, config.max_wait_scl_change_severity, msg, scope, ID_NEVER, msg_id_panel);
await_value(sda, '1', MATCH_STD, 0 ns, config.master_scl_to_sda + config.master_scl_to_sda/100, config.max_wait_sda_change_severity, msg, scope, ID_NEVER, msg_id_panel);
if to_X01(sda) = '1' and to_X01(scl) = '1' then
-- await the start condition
await_value(sda, '0', 0 ns, config.max_wait_sda_change + config.max_wait_sda_change/100, config.max_wait_sda_change_severity, msg, scope, ID_NEVER, msg_id_panel);
await_value(scl, '0', 0 ns, config.max_wait_scl_change + config.max_wait_scl_change/100, config.max_wait_scl_change_severity, msg, scope, ID_NEVER, msg_id_panel);
if sda = '0' then
-- receive the first 2 address bits again+ read bit, consisting of "11110<bit 9><bit 8><read>"
i2c_slave_receive_single_byte(v_bfm_rx_data);
-- Check R/W bit
check_value(v_bfm_rx_data(0), '1', config.slave_rw_bit_severity, add_msg_delimiter(msg) & ": checking R/W bit after first address byte (10-bit addressing)", scope, ID_NEVER, msg_id_panel);
-- Set ACK/NACK based on first received byte
-- The master shall drive scl during the acknowledge cycle
-- A valid ack is detected when sda is '0'.
if v_bfm_rx_data(7 downto 1) = C_FIRST_10_BIT_ADDRESS_BITS then
-- ACK
i2c_slave_set_ack('0');
else
-- NACK
alert(config.slave_mode_address_severity, proc_call & " first byte was other than expected! " & add_msg_delimiter(msg), scope);
return;
end if;
else
alert(error, proc_call & " sda and scl not inactive (high) when wishing to start after repeated start condition for 10 bit address " & add_msg_delimiter(msg), scope);
end if;
end if;
end if;
for i in 0 to data'length - 1 loop
i2c_slave_transmit_single_byte(data(i));
-- Check ACK
-- The master shall drive scl during the acknowledge cycle
-- A valid ack is detected when sda is '0'.
-- A NACK ('1'/'H') means that the transaction is over.
if i < data'length - 1 then
i2c_slave_check_ack('0');
else -- final data byte expected
i2c_slave_check_ack('1');
end if;
await_value(scl, '0', 0 ns, config.max_wait_scl_change + config.max_wait_scl_change/100, config.max_wait_scl_change_severity, msg, scope, ID_NEVER, msg_id_panel);
end loop;
-- Wait for either the stop condition or preparation for
-- repeated start condition.
sda <= 'Z'; -- other side should drive now
await_value(scl, '1', MATCH_STD, 0 ns, config.max_wait_scl_change + config.max_wait_scl_change/100, config.max_wait_scl_change_severity, msg, scope, ID_NEVER, msg_id_panel);
await_value(sda, '1', MATCH_STD, 0 ns, config.master_scl_to_sda + config.master_scl_to_sda/100, config.max_wait_sda_change_severity, msg, scope, ID_NEVER, msg_id_panel);
end if;
else
alert(error, proc_call & " sda and scl not inactive (high) when wishing to start " & add_msg_delimiter(msg), scope);
end if;
log(config.id_for_bfm, proc_call & "=> " & to_string(data, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
end procedure;
procedure i2c_slave_transmit(
constant data : in t_byte_array;
constant msg : in string;
signal i2c_if : inout t_i2c_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT
) is
begin
i2c_slave_transmit(data, msg,
i2c_if.scl, i2c_if.sda,
scope, msg_id_panel, config);
end procedure;
procedure i2c_slave_transmit(
constant data : in std_logic_vector;
constant msg : in string;
signal i2c_if : inout t_i2c_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT
) is
variable v_bfm_tx_data : std_logic_vector(7 downto 0) := (others => '0');
-- Normalize to the 8 bit data width
variable v_normalized_data : std_logic_vector(7 downto 0) :=
normalize_and_check(data, v_bfm_tx_data, ALLOW_NARROWER, "data", "v_bfm_tx_data", msg);
variable v_byte_array : t_byte_array(0 to 0) := (0 => v_normalized_data);
begin
i2c_slave_transmit(v_byte_array, msg,
i2c_if.scl, i2c_if.sda,
scope, msg_id_panel, config);
end procedure;
---------------------------------------------------------------------------------
-- i2c_master_receive
---------------------------------------------------------------------------------
procedure i2c_master_receive (
constant addr_value : in unsigned;
variable data : out t_byte_array;
constant msg : in string;
signal scl : inout std_logic;
signal sda : inout std_logic;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like .._check
) is
-- Local proc_name; used if called from sequncer or VVC
constant local_proc_name : string := "i2c_master_receive";
-- Local proc_call; used if called from sequncer or VVC
constant local_proc_call : string := local_proc_name & "(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) & ")";
constant C_10_BIT_ADDRESS_PATTERN : std_logic_vector(4 downto 0) := "11110";
-- Normalize to the 7 bit addr and 8 bit data widths
variable v_normalized_addr : unsigned(9 downto 0) :=
normalize_and_check(addr_value, config.slave_mode_address, ALLOW_NARROWER, "addr", "config.slave_mode_address", msg);
constant C_FIRST_10_BIT_ADDRESS_BITS : std_logic_vector(6 downto 0) := C_10_BIT_ADDRESS_PATTERN & std_logic_vector(v_normalized_addr(9 downto 8));
variable v_proc_call : line;
procedure i2c_master_transmit_single_byte (
constant byte : in std_logic_vector(7 downto 0)
) is
begin
i2c_master_transmit_single_byte(byte, msg, scl, sda, scope, msg_id_panel, config);
end procedure;
procedure i2c_master_receive_single_byte (
variable byte : out std_logic_vector(7 downto 0)
) is
begin
i2c_master_receive_single_byte(byte, msg, scl, sda, scope, msg_id_panel, config);
end procedure;
procedure i2c_master_set_ack (
constant ack : in std_logic
) is
begin
i2c_master_set_ack(ack, msg, scl, sda, scope, msg_id_panel, config);
end procedure;
procedure i2c_master_check_ack (
constant ack_exp : in std_logic
) is
begin
i2c_master_check_ack(ack_exp, msg, scl, sda, scope, msg_id_panel, config);
end procedure;
begin
-- check whether config.i2c_bit_time was set probably
check_value(config.i2c_bit_time /= -1 ns, TB_ERROR, "I2C Bit time was not set in config. " & add_msg_delimiter(msg), C_SCOPE, ID_NEVER, msg_id_panel);
-- If called from sequencer/VVC, show 'i2c_master_read...' in log
if ext_proc_call = "" then
write(v_proc_call, local_proc_call);
else
-- If called from other BFM procedure, log 'ext_proc_call while executing i2c_master_read..'
write(v_proc_call, ext_proc_call & " while executing " & local_proc_name);
end if;
if not config.enable_10_bits_addressing then
check_value(v_normalized_addr(9 downto 7), unsigned'("000"), config.slave_mode_address_severity,
"Verifying that top slave address bits (9-7) are not set in 7-bit addressing mode.",
scope, HEX_BIN_IF_INVALID, KEEP_LEADING_0, ID_NEVER, msg_id_panel);
i2c_check_slave_addr(v_normalized_addr(6 downto 0), config.reserved_address_severity, scope);
else
i2c_check_slave_addr(v_normalized_addr(9 downto 0), config.reserved_address_severity, scope);
end if;
check_value(data'ascending, failure, "Verifying that data is of ascending type. " & add_msg_delimiter(msg), scope, ID_NEVER, msg_id_panel);
-- start condition
await_value(sda, '1', MATCH_STD, 0 ns, config.max_wait_sda_change, config.max_wait_sda_change_severity, msg, scope, ID_NEVER, msg_id_panel);
await_value(scl, '1', MATCH_STD, 0 ns, config.max_wait_scl_change, config.max_wait_scl_change_severity, msg, scope, ID_NEVER, msg_id_panel);
if to_X01(sda) = '1' and to_X01(scl) = '1' then
-- do the start condition
sda <= '0';
wait for config.master_sda_to_scl;
scl <= '0';
if sda = '0' then
-- Transmit address
if not config.enable_10_bits_addressing then
i2c_master_transmit_single_byte(std_logic_vector(v_normalized_addr(6 downto 0)) & '1');
else -- 10-bits addressing enabled
-- Transmit Slave Address first 7 bits 11110<addr bit 9><addr bit 8><Write>
i2c_master_transmit_single_byte(C_FIRST_10_BIT_ADDRESS_BITS & '0');
end if;
-- Check ACK
-- The master shall drive scl during the acknowledge cycle
-- A valid ack is detected when sda is '0'.
i2c_master_check_ack('0');
-- If 10-bits addressing is enabled, transmit second address byte.
if config.enable_10_bits_addressing then
i2c_master_transmit_single_byte(std_logic_vector(v_normalized_addr(7 downto 0)));
-- Check ACK
-- The master shall drive scl during the acknowledge cycle
-- A valid ack is detected when sda is '0'.
i2c_master_check_ack('0');
-- Now generate a repeated start condition, send the first byte again (only with read/write-bit set to read), check ack. Then receive data bytes.
-- Generate repeated start condition
wait for config.i2c_bit_time/4;
sda <= 'Z';
wait for config.i2c_bit_time/4;
scl <= 'Z';
-- check for clock stretching
await_value(scl, '1', MATCH_STD, 0 ns, config.i2c_bit_time, config.i2c_bit_time_severity, msg, scope, ID_NEVER, msg_id_panel);
wait for config.master_stop_condition_hold_time;
-- do the start condition
sda <= '0';
wait for config.master_sda_to_scl;
scl <= '0';
if sda = '0' then
-- Transmit Slave Address first 7 bits 11110<addr bit 9><addr bit 8><Read>
i2c_master_transmit_single_byte(C_FIRST_10_BIT_ADDRESS_BITS & '1');
-- Check ACK
-- The master shall drive scl during the acknowledge cycle
-- A valid ack is detected when sda is '0'.
i2c_master_check_ack('0');
else
alert(error, v_proc_call.all & " sda not '0' when expected after repeated start condition for 10-bit addressing! " & add_msg_delimiter(msg), scope);
end if;
end if;
-- receive the data bytes
for i in 0 to data'length-1 loop
i2c_master_receive_single_byte(data(i));
-- Set ACK/NACK
-- The master shall drive scl during the acknowledge cycle
-- A valid ack is detected when sda is '0'.
-- Each byte shall be ACKed except last byte.
-- Transaction ends when master sets NACK.
-- scl has been driven to '0' above
if i < data'length - 1 then
i2c_master_set_ack('0'); -- ACK
else
i2c_master_set_ack('1'); -- NACK
end if;
end loop;
if action_when_transfer_is_done = RELEASE_LINE_AFTER_TRANSFER then
-- do the stop condition
sda <= '0';
wait for config.i2c_bit_time/4;
scl <= 'Z';
-- check for clock stretching
await_value(scl, '1', MATCH_STD, 0 ns, config.i2c_bit_time, config.i2c_bit_time_severity, msg, scope, ID_NEVER, msg_id_panel);
wait for config.master_scl_to_sda;
sda <= 'Z';
else -- action_when_transfer_is_done = HOLD_LINE_AFTER_TRANSFER
-- Do not perform the stop condition. Instead release SDA when SCL is low.
-- This will prepare for a repeated start condition.
sda <= 'Z';
wait for config.i2c_bit_time/4;
scl <= 'Z';
-- check for clock stretching
await_value(scl, '1', MATCH_STD, 0 ns, config.i2c_bit_time, config.i2c_bit_time_severity, msg, scope, ID_NEVER, msg_id_panel);
end if;
wait for config.master_stop_condition_hold_time;
end if;
else
alert(error, v_proc_call.all & " sda and scl not inactive (high) when wishing to start " & add_msg_delimiter(msg), scope);
end if;
if ext_proc_call = "" then -- proc_name = "i2c_master_receive"
log(config.id_for_bfm, v_proc_call.all & "=> " & to_string(data, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
-- Log will be handled by calling procedure (e.g. i2c_master_check)
end if;
end procedure;
procedure i2c_master_receive(
constant addr_value : in unsigned;
variable data : out t_byte_array;
constant msg : in string;
signal i2c_if : inout t_i2c_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- overwrite if called from other procedure like .._check
) is
begin
i2c_master_receive(addr_value, data, msg,
i2c_if.scl, i2c_if.sda, action_when_transfer_is_done,
scope, msg_id_panel, config, ext_proc_call);
end procedure;
procedure i2c_master_receive(
constant addr_value : in unsigned;
variable data : out std_logic_vector;
constant msg : in string;
signal i2c_if : inout t_i2c_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- overwrite if called from other procedure like .._check
) is
variable v_byte_array : t_byte_array(0 to 0);
begin
i2c_master_receive(addr_value, v_byte_array, msg,
i2c_if.scl, i2c_if.sda, action_when_transfer_is_done,
scope, msg_id_panel, config, ext_proc_call);
data := v_byte_array(0);
end procedure;
---------------------------------------------------------------------------------
-- i2c_slave_receive
---------------------------------------------------------------------------------
procedure i2c_slave_receive (
variable data : out t_byte_array;
constant msg : in string;
signal scl : inout std_logic;
signal sda : inout std_logic;
constant exp_rw_bit : in std_logic := C_WRITE_BIT;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like *_check
) is
-- Local proc_name; used if called from sequncer or VVC
constant local_proc_name : string := "i2c_slave_receive";
-- Local proc_call; used if called from sequncer or VVC
constant local_proc_call : string := local_proc_name & "()";
variable v_proc_call : line;
variable v_received_addr : unsigned(9 downto 0) := (others => '0');
variable v_bfm_rx_data : std_logic_vector(7 downto 0);
constant C_10_BIT_ADDRESS_PATTERN : std_logic_vector(4 downto 0) := "11110";
constant C_FIRST_10_BIT_ADDRESS_BITS : std_logic_vector(6 downto 0) := C_10_BIT_ADDRESS_PATTERN & std_logic_vector(config.slave_mode_address(9 downto 8));
procedure i2c_slave_receive_single_byte (
variable byte : out std_logic_vector(7 downto 0)
) is
begin
i2c_slave_receive_single_byte(byte, msg, scl, sda, scope, msg_id_panel, config);
end procedure;
procedure i2c_slave_set_ack (
constant ack : in std_logic
) is
begin
i2c_slave_set_ack(ack, msg, scl, sda, scope, msg_id_panel, config);
end procedure;
begin
-- check whether config.i2c_bit_time was set probably
check_value(config.i2c_bit_time /= -1 ns, TB_ERROR, "I2C Bit time was not set in config. " & add_msg_delimiter(msg), C_SCOPE, ID_NEVER, msg_id_panel);
-- If called from sequencer/VVC, show 'i2c_master_read...' in log
if ext_proc_call = "" then
write(v_proc_call, local_proc_call);
else
-- If called from other BFM procedure, log 'ext_proc_call while executing i2c_slave_read..'
write(v_proc_call, ext_proc_call & " while executing " & local_proc_name);
end if;
if not config.enable_10_bits_addressing then
check_value(config.slave_mode_address(9 downto 7), unsigned'("000"), config.slave_mode_address_severity,
"Verifying that top slave address bits (9-7) are not set in 7-bit addressing mode.",
scope, HEX_BIN_IF_INVALID, KEEP_LEADING_0, ID_NEVER, msg_id_panel);
i2c_check_slave_addr(config.slave_mode_address(6 downto 0), config.reserved_address_severity, scope);
else
i2c_check_slave_addr(config.slave_mode_address, config.reserved_address_severity, scope);
end if;
check_value(data'ascending, failure, "Verifying that data is of ascending type. " & add_msg_delimiter(msg) & ".", scope, ID_NEVER, msg_id_panel);
-- Check that expected data range is 0 when expected read/write bit is read.
if exp_rw_bit = C_READ_BIT then
check_value(data'length, 0, TB_ERROR, "Expected data range must be 0 when expected R/W# bit is Read. " & add_msg_delimiter(msg) & ".", scope, ID_NEVER, msg_id_panel);
end if;
await_value(sda, '1', MATCH_STD, 0 ns, config.max_wait_sda_change, config.max_wait_sda_change_severity, msg, scope, ID_NEVER, msg_id_panel);
await_value(scl, '1', MATCH_STD, 0 ns, config.max_wait_scl_change, config.max_wait_scl_change_severity, msg, scope, ID_NEVER, msg_id_panel);
if to_X01(sda) = '1' and to_X01(scl) = '1' then
-- await the start condition
await_value(sda, '0', 0 ns, config.max_wait_sda_change + config.max_wait_sda_change/100, config.max_wait_sda_change_severity, msg, scope, ID_NEVER, msg_id_panel);
await_value(scl, '0', 0 ns, config.max_wait_scl_change + config.max_wait_scl_change/100, config.max_wait_scl_change_severity, msg, scope, ID_NEVER, msg_id_panel);
if sda = '0' then
if not config.enable_10_bits_addressing then
-- receive the address bits
i2c_slave_receive_single_byte(v_bfm_rx_data);
check_value(v_bfm_rx_data(0), exp_rw_bit, config.slave_rw_bit_severity, msg, scope, ID_NEVER, msg_id_panel); -- R/W bit
-- Set ACK/NACK based on address
-- The master shall drive scl during the acknowledge cycle
-- A valid ack is detected when sda is '0'.
if unsigned(v_bfm_rx_data(7 downto 1)) = config.slave_mode_address(6 downto 0) then
-- ACK
i2c_slave_set_ack('0');
else
-- NACK
alert(config.slave_mode_address_severity, v_proc_call.all & " wrong slave address!" &
" Expected: " & to_string(config.slave_mode_address, BIN, KEEP_LEADING_0) &
", Got: " & to_string(unsigned(v_bfm_rx_data(7 downto 1)), BIN, KEEP_LEADING_0) & add_msg_delimiter(msg), scope);
return;
end if;
else
-- receive the first byte, consisting of "11110<bit 9><bit 8><write>"
i2c_slave_receive_single_byte(v_bfm_rx_data);
v_received_addr(9 downto 8) := unsigned(v_bfm_rx_data(2 downto 1));
-- Check R/W bit
check_value(v_bfm_rx_data(0), exp_rw_bit, config.slave_rw_bit_severity, add_msg_delimiter(msg) & ": checking R/W bit after first address byte (10-bit addressing)", scope, ID_NEVER, msg_id_panel);
-- Set ACK/NACK based on first received byte
-- The master shall drive scl during the acknowledge cycle
-- A valid ack is detected when sda is '0'.
if v_bfm_rx_data(7 downto 1) = C_FIRST_10_BIT_ADDRESS_BITS then
-- ACK
i2c_slave_set_ack('0');
else
-- NACK
alert(config.slave_mode_address_severity, v_proc_call.all & " first byte was other than expected! " & add_msg_delimiter(msg), scope);
return;
end if;
i2c_slave_receive_single_byte(v_bfm_rx_data);
v_received_addr(7 downto 0) := unsigned(v_bfm_rx_data);
-- Set ACK/NACK based on address
-- The master shall drive scl during the acknowledge cycle
-- A valid ack is detected when sda is '0'.
if v_received_addr = config.slave_mode_address then
-- ACK
i2c_slave_set_ack('0');
else
-- NACK
alert(config.slave_mode_address_severity, v_proc_call.all & " wrong slave address!" &
" Expected: " & to_string(config.slave_mode_address, BIN, KEEP_LEADING_0) &
", Got: " & to_string(v_received_addr, BIN, KEEP_LEADING_0) & add_msg_delimiter(msg), scope);
return;
end if;
end if;
-- receive the data bytes
for i in 0 to data'length-1 loop
i2c_slave_receive_single_byte(data(i));
-- Set ACK
-- The master shall drive scl during the acknowledge cycle
-- A valid ack is detected when sda is '0'.
i2c_slave_set_ack('0');
end loop;
-- Wait for either the stop condition or preparation for
-- repeated start condition.
await_value(scl, '1', MATCH_STD, 0 ns, config.max_wait_scl_change + config.max_wait_scl_change/100, config.max_wait_scl_change_severity, msg, scope, ID_NEVER, msg_id_panel);
await_value(sda, '1', MATCH_STD, 0 ns, config.master_scl_to_sda + config.master_scl_to_sda/100, config.max_wait_sda_change_severity, msg, scope, ID_NEVER, msg_id_panel);
end if;
else
alert(error, v_proc_call.all & " sda and scl not inactive (high) when wishing to start " & add_msg_delimiter(msg), scope);
end if;
if ext_proc_call = "" then -- proc_name = "i2c_slave_receive"
log(config.id_for_bfm, v_proc_call.all & "=> " & to_string(data, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
-- Log will be handled by calling procedure (e.g. i2c_slave_check)
end if;
end procedure;
procedure i2c_slave_receive(
variable data : out t_byte_array;
constant msg : in string;
signal i2c_if : inout t_i2c_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like *_check
) is
begin
i2c_slave_receive(data, msg,
i2c_if.scl, i2c_if.sda, C_WRITE_BIT,
scope, msg_id_panel, config, ext_proc_call);
end procedure;
procedure i2c_slave_receive(
variable data : out std_logic_vector;
constant msg : in string;
signal i2c_if : inout t_i2c_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- overwrite if called from other procedure like i2c_slave_check
) is
variable v_byte_array : t_byte_array(0 to 0);
begin
i2c_slave_receive(v_byte_array, msg,
i2c_if.scl, i2c_if.sda, C_WRITE_BIT,
scope, msg_id_panel, config, ext_proc_call);
data := v_byte_array(0);
end procedure;
---------------------------------------------------------------------------------
-- i2c_master_check
---------------------------------------------------------------------------------
-- Perform a read operation, then compare the read value to the data_exp.
procedure i2c_master_check (
constant addr_value : in unsigned;
constant data_exp : in t_byte_array;
constant msg : in string;
signal scl : inout std_logic;
signal sda : inout std_logic;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT
) is
constant proc_name : string := "i2c_master_check";
constant proc_call : string := proc_name & "(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) &
", " & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & ")";
-- Helper variables
variable v_data_array : t_byte_array(data_exp'range);
variable v_check_ok : boolean := true;
variable v_byte_ok : boolean;
begin
-- check whether config.i2c_bit_time was set probably
check_value(config.i2c_bit_time /= -1 ns, TB_ERROR, "I2C Bit time was not set in config. " & add_msg_delimiter(msg), C_SCOPE, ID_NEVER, msg_id_panel);
i2c_master_receive(addr_value, v_data_array, msg, scl, sda, action_when_transfer_is_done, scope, msg_id_panel, config, proc_call);
-- Compare values, but ignore any leading zero's if widths are different.
-- Use ID_NEVER so that check_value method does not log when check is OK,
-- log it here instead.
for i in data_exp'range loop
v_byte_ok := check_value(v_data_array(i), data_exp(i), alert_level, msg, scope, HEX_BIN_IF_INVALID, SKIP_LEADING_0, ID_NEVER, msg_id_panel, proc_call);
if not v_byte_ok then
v_check_ok := false;
end if;
end loop;
if v_check_ok then
log(config.id_for_bfm, proc_call & "=> OK, read data = " & to_string(v_data_array, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
end procedure;
procedure i2c_master_check (
constant addr_value : in unsigned;
constant data_exp : in t_byte_array;
constant msg : in string;
signal i2c_if : inout t_i2c_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT
) is
begin
i2c_master_check(addr_value, data_exp, msg,
i2c_if.scl, i2c_if.sda, action_when_transfer_is_done,
alert_level, scope, msg_id_panel, config);
end procedure;
procedure i2c_master_check (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal i2c_if : inout t_i2c_if;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT
) is
variable v_bfm_rx_data : std_logic_vector(7 downto 0) := (others => '0');
-- Normalize to the 8 bit data width
variable v_normalized_data_exp : std_logic_vector(7 downto 0) :=
normalize_and_check(data_exp, v_bfm_rx_data, ALLOW_NARROWER, "data", "v_bfm_rx_data", msg);
variable v_byte_array : t_byte_array(0 to 0) := (0 => v_normalized_data_exp);
begin
i2c_master_check(addr_value, v_byte_array, msg,
i2c_if.scl, i2c_if.sda, action_when_transfer_is_done,
alert_level, scope, msg_id_panel, config);
end procedure;
---------------------------------------------------------------------------------
-- i2c_slave_check
---------------------------------------------------------------------------------
-- Perform a read operation, then compare the read value to the data_exp.
procedure i2c_slave_check (
constant data_exp : in t_byte_array;
constant msg : in string;
signal scl : inout std_logic;
signal sda : inout std_logic;
constant exp_rw_bit : in std_logic := C_WRITE_BIT;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT
) is
constant proc_name : string := "i2c_slave_check";
constant proc_call : string := proc_name & "(" & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & ")";
-- Helper variables
variable v_data_array : t_byte_array(data_exp'range);
variable v_check_ok : boolean := true;
variable v_byte_ok : boolean;
begin
i2c_slave_receive(v_data_array, msg, scl, sda, exp_rw_bit, scope, msg_id_panel, config, proc_call);
-- Compare values, but ignore any leading zero's if widths are different.
-- Use ID_NEVER so that check_value method does not log when check is OK,
-- log it here instead.
for i in data_exp'range loop
v_byte_ok := check_value(v_data_array(i), data_exp(i), alert_level, msg, scope, HEX_BIN_IF_INVALID, SKIP_LEADING_0, ID_NEVER, msg_id_panel, proc_call);
if not v_byte_ok then
v_check_ok := false;
end if;
end loop;
if v_check_ok then
log(config.id_for_bfm, proc_call & "=> OK, read data = " & to_string(v_data_array, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
end procedure;
procedure i2c_slave_check (
constant data_exp : in t_byte_array;
constant msg : in string;
signal i2c_if : inout t_i2c_if;
constant exp_rw_bit : in std_logic := C_WRITE_BIT;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT
) is
begin
i2c_slave_check(data_exp, msg,
i2c_if.scl, i2c_if.sda, exp_rw_bit,
alert_level, scope, msg_id_panel, config);
end procedure;
procedure i2c_slave_check (
constant data_exp : in std_logic_vector;
constant msg : in string;
signal i2c_if : inout t_i2c_if;
constant exp_rw_bit : in std_logic := C_WRITE_BIT;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT
) is
variable v_bfm_rx_data : std_logic_vector(7 downto 0) := (others => '0');
-- Normalize to the 8 bit data width
variable v_normalized_data_exp : std_logic_vector(7 downto 0) :=
normalize_and_check(data_exp, v_bfm_rx_data, ALLOW_NARROWER, "data", "v_bfm_rx_data", msg);
variable v_byte_array : t_byte_array(0 to 0) := (0 => v_normalized_data_exp);
begin
i2c_slave_check(v_byte_array, msg,
i2c_if.scl, i2c_if.sda, exp_rw_bit,
alert_level, scope, msg_id_panel, config);
end procedure;
---------------------------------------------------------------------------------
-- i2c_master_quick_command
---------------------------------------------------------------------------------
procedure i2c_master_quick_command (
constant addr_value : in unsigned;
constant msg : in string;
signal i2c_if : inout t_i2c_if;
constant rw_bit : in std_logic := C_WRITE_BIT;
constant exp_ack : in boolean := true;
constant action_when_transfer_is_done : in t_action_when_transfer_is_done := RELEASE_LINE_AFTER_TRANSFER;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_i2c_bfm_config := C_I2C_BFM_CONFIG_DEFAULT
) is
constant proc_call : string := "i2c_master_quick_command (A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) &
", rw_bit: " & to_string(rw_bit) & ")";
constant C_10_BIT_ADDRESS_PATTERN : std_logic_vector(4 downto 0) := "11110";
-- Normalize to the 7 bit addr and 8 bit data widths
variable v_normalized_addr : unsigned(9 downto 0) :=
normalize_and_check(addr_value, config.slave_mode_address, ALLOW_NARROWER, "addr", "config.slave_mode_address", msg);
constant C_FIRST_10_BIT_ADDRESS_BITS : std_logic_vector(6 downto 0) := C_10_BIT_ADDRESS_PATTERN & std_logic_vector(v_normalized_addr(9 downto 8));
variable v_ack_received : boolean := false;
variable v_ack_ok : boolean;
variable v_check_ok : boolean := true;
procedure i2c_master_transmit_single_byte (
constant byte : in std_logic_vector(7 downto 0)
) is
begin
i2c_master_transmit_single_byte(byte, msg, i2c_if.scl, i2c_if.sda, scope, msg_id_panel, config);
end procedure;
procedure i2c_master_check_ack (
variable v_ack_received : out boolean;
constant ack_exp : in std_logic
) is
begin
i2c_master_check_ack(v_ack_received, ack_exp, msg, i2c_if.scl, i2c_if.sda, scope, msg_id_panel, config);
end procedure;
begin
-- check whether config.i2c_bit_time was set probably
check_value(config.i2c_bit_time /= -1 ns, TB_ERROR, "I2C Bit time was not set in config. " & add_msg_delimiter(msg), C_SCOPE, ID_NEVER, msg_id_panel);
if not config.enable_10_bits_addressing then
check_value(v_normalized_addr(9 downto 7), unsigned'("000"), config.slave_mode_address_severity,
"Verifying that top slave address bits (9-7) are not set in 7-bit addressing mode. " & add_msg_delimiter(msg),
scope, HEX_BIN_IF_INVALID, KEEP_LEADING_0, ID_NEVER, msg_id_panel);
i2c_check_slave_addr(v_normalized_addr(6 downto 0), config.reserved_address_severity, scope);
else
i2c_check_slave_addr(v_normalized_addr(9 downto 0), config.reserved_address_severity, scope);
end if;
-- start condition
log(config.id_for_bfm, proc_call & "=> Awaiting start condition. " & add_msg_delimiter(msg), scope, msg_id_panel);
await_value(i2c_if.sda, '1', MATCH_STD, 0 ns, config.max_wait_sda_change, config.max_wait_sda_change_severity, msg, scope, ID_NEVER, msg_id_panel);
await_value(i2c_if.scl, '1', MATCH_STD, 0 ns, config.max_wait_scl_change, config.max_wait_scl_change_severity, msg, scope, ID_NEVER, msg_id_panel);
if to_X01(i2c_if.sda) = '1' and to_X01(i2c_if.scl) = '1' then
-- do the start condition
i2c_if.sda <= '0';
wait for config.master_sda_to_scl;
i2c_if.scl <= '0';
if i2c_if.sda = '0' then
-- Transmit address
log(config.id_for_bfm, proc_call & "=> Transmitting address. " & add_msg_delimiter(msg), scope, msg_id_panel);
if not config.enable_10_bits_addressing then
i2c_master_transmit_single_byte(std_logic_vector(v_normalized_addr(6 downto 0)) & rw_bit);
else -- 10-bits addressing enabled
-- Transmit Slave Address first 7 bits 11110<addr bit 9><addr bit 8><Write>
i2c_master_transmit_single_byte(C_FIRST_10_BIT_ADDRESS_BITS & rw_bit);
end if;
log(config.id_for_bfm, proc_call & "=> Address transmitted. " & add_msg_delimiter(msg), scope, msg_id_panel);
-- Check ACK
-- The master shall drive scl during the acknowledge cycle
-- A valid ack is detected when sda is '0'.
log(config.id_for_bfm, proc_call & "=> Checking ACK. " & add_msg_delimiter(msg), scope, msg_id_panel);
i2c_master_check_ack(v_ack_received, '0');
log(config.id_for_bfm, proc_call & "=> ACK was " & to_string(v_ack_received) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
-- If 10-bits addressing is enabled, transmit second address byte.
if config.enable_10_bits_addressing then
log(config.id_for_bfm, proc_call & "=> Transmitting second part of address. " & add_msg_delimiter(msg), scope, msg_id_panel);
i2c_master_transmit_single_byte(std_logic_vector(v_normalized_addr(7 downto 0)));
-- Check ACK
-- The master shall drive scl during the acknowledge cycle
-- A valid ack is detected when sda is '0'.
log(config.id_for_bfm, proc_call & "=> Checking ACK. " & add_msg_delimiter(msg), scope, msg_id_panel);
i2c_master_check_ack(v_ack_received, '0');
log(config.id_for_bfm, proc_call & "=> ACK was " & to_string(v_ack_received) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
-- Now generate a repeated start condition, send the first byte again (only with read/write-bit set to read), check ack. Then receive data bytes.
-- Generate repeated start condition
log(config.id_for_bfm, proc_call & "=> Repeating start condition. " & add_msg_delimiter(msg), scope, msg_id_panel);
wait for config.i2c_bit_time/4;
i2c_if.sda <= 'Z';
wait for config.i2c_bit_time/4;
i2c_if.scl <= 'Z';
-- check for clock stretching
await_value(i2c_if.scl, '1', MATCH_STD, 0 ns, config.i2c_bit_time, config.i2c_bit_time_severity, msg, scope, ID_NEVER, msg_id_panel);
wait for config.master_stop_condition_hold_time;
-- do the start condition
i2c_if.sda <= '0';
wait for config.master_sda_to_scl;
i2c_if.scl <= '0';
if i2c_if.sda = '0' then
-- Transmit Slave Address first 7 bits 11110<addr bit 9><addr bit 8><Write>
log(config.id_for_bfm, proc_call & "=> Transmitting Slave Address first 7 bits. " & add_msg_delimiter(msg), scope, msg_id_panel);
i2c_master_transmit_single_byte(C_FIRST_10_BIT_ADDRESS_BITS & '1');
-- Check ACK
-- The master shall drive scl during the acknowledge cycle
-- A valid ack is detected when sda is '0'.
log(config.id_for_bfm, proc_call & "=> Checking ACK. " & add_msg_delimiter(msg), scope, msg_id_panel);
i2c_master_check_ack(v_ack_received, '0');
log(config.id_for_bfm, proc_call & "=> ACK was " & to_string(v_ack_received) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(error, "i2c_master_quick_command sda not '0' when expected after repeated start condition for 10-bit addressing! " & add_msg_delimiter(msg), scope);
end if;
end if;
-- Do the stop condition if action_when_transfer_is_done is set to RELEASE_LINE_AFTER_TRANSFER
if action_when_transfer_is_done = RELEASE_LINE_AFTER_TRANSFER then
-- do the stop condition
log(config.id_for_bfm, proc_call & "=> Setting stop condition.", scope, msg_id_panel);
i2c_if.sda <= '0';
wait for config.i2c_bit_time/4;
i2c_if.scl <= 'Z';
-- check for clock stretching
await_value(i2c_if.scl, '1', MATCH_STD, 0 ns, config.i2c_bit_time, config.i2c_bit_time_severity, msg, scope, ID_NEVER, msg_id_panel);
wait for config.master_scl_to_sda;
i2c_if.sda <= 'Z';
else -- action_when_transfer_is_done = HOLD_LINE_AFTER_TRANSFER
-- Do not perform the stop condition. Instead release SDA when SCL is low.
-- This will prepare for a repeated start condition.
i2c_if.sda <= 'Z';
wait for config.i2c_bit_time/4;
i2c_if.scl <= 'Z';
-- check for clock stretching
await_value(i2c_if.scl, '1', MATCH_STD, 0 ns, config.i2c_bit_time, config.i2c_bit_time_severity, msg, scope, ID_NEVER, msg_id_panel);
end if;
wait for config.master_stop_condition_hold_time;
end if;
else
alert(error, proc_call & " sda and scl not inactive (high) when wishing to start " & add_msg_delimiter(msg), scope);
end if;
-- Compare values, but ignore any leading zero's if widths are different.
-- Use ID_NEVER so that check_value method does not log when check is OK,
-- log it here instead.
v_ack_ok := check_value(v_ack_received, exp_ack, alert_level, msg, scope, ID_NEVER, msg_id_panel);
if not v_ack_ok then
v_check_ok := false;
end if;
if v_check_ok then
log(config.id_for_bfm, proc_call & "=> OK, slave response was " & to_string(v_ack_received) & ", expected " & to_string(exp_ack) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, proc_call & "=> FAILED, slave response was " & to_string(v_ack_received) & ", expected " & to_string(exp_ack) & ". " & add_msg_delimiter(msg), scope);
end if;
end procedure;
end package body i2c_bfm_pkg;
|
mit
|
VLSI-EDA/UVVM_All
|
uvvm_vvc_framework/src_target_dependent/td_queue_pkg.vhd
|
3
|
2199
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
--===============================================================================================
-- td_cmd_queue_pkg
-- - Target dependent command queue package
--===============================================================================================
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_generic_queue_pkg;
use work.vvc_cmd_pkg.all;
package td_cmd_queue_pkg is new uvvm_vvc_framework.ti_generic_queue_pkg
generic map (t_generic_element => t_vvc_cmd_record);
--===============================================================================================
-- td_result_queue_pkg
-- - Target dependent result queue package
--===============================================================================================
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_generic_queue_pkg;
use work.vvc_cmd_pkg.all;
package td_result_queue_pkg is new uvvm_vvc_framework.ti_generic_queue_pkg
generic map (t_generic_element => t_vvc_result_queue_element);
|
mit
|
MForever78/CPUFly
|
ipcore_dir/Instruction_Memory/simulation/Instruction_Memory_tb_checker.vhd
|
1
|
5766
|
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Instruction_Memory_tb_checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.Instruction_Memory_TB_PKG.ALL;
ENTITY Instruction_Memory_TB_CHECKER IS
GENERIC (
WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END Instruction_Memory_TB_CHECKER;
ARCHITECTURE CHECKER_ARCH OF Instruction_Memory_TB_CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DGEN_INST:ENTITY work.Instruction_Memory_TB_DGEN
GENERIC MAP (
DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
|
mit
|
MForever78/CPUFly
|
ipcore_dir/Instruction_Memory/simulation/Instruction_Memory_tb_stim_gen.vhd
|
1
|
11025
|
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Stimulus Generator For ROM Configuration
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Instruction_Memory_tb_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For ROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.Instruction_Memory_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_ROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_ROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_ROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.Instruction_Memory_TB_PKG.ALL;
ENTITY Instruction_Memory_TB_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
A : OUT STD_LOGIC_VECTOR(12-1 downto 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (31 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END Instruction_Memory_TB_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF Instruction_Memory_TB_STIM_GEN IS
FUNCTION std_logic_vector_len(
hex_str : STD_LOGIC_VECTOR;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR(return_width DOWNTO 0) := (OTHERS => '0');
VARIABLE tmp_z : STD_LOGIC_VECTOR(return_width-(hex_str'LENGTH) DOWNTO 0) := (OTHERS => '0');
BEGIN
tmp := tmp_z & hex_str;
RETURN tmp(return_width-1 DOWNTO 0);
END std_logic_vector_len;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0):= std_logic_vector_len("0",32);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (4095 downto 0) of std_logic_vector(31 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF(input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory(
C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Distributed Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(1,
1,
"Instruction_Memory.mif",
DEFAULT_DATA,
32,
4096);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_AGEN_INST:ENTITY work.Instruction_Memory_TB_AGEN
GENERIC MAP( C_MAX_DEPTH =>4096 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA(2),
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => check_read_addr
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA(2) ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA(2)='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(11 DOWNTO 0) <= READ_ADDR(11 DOWNTO 0);
A <= READ_ADDR_INT ;
CHECK_DATA(0) <= DO_READ;
RD_AGEN_INST:ENTITY work.Instruction_Memory_TB_AGEN
GENERIC MAP( C_MAX_DEPTH => 4096 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_EN_REG: FOR I IN 0 TO 2 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_ROM
PORT MAP(
Q => CHECK_DATA(1),
CLK => CLK,
RST => RST,
D => CHECK_DATA(0)
);
END GENERATE DFF_RIGHT;
DFF_CE_OTHERS: IF ((I>0) AND (I<2)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_ROM
PORT MAP(
Q => CHECK_DATA(I+1),
CLK => CLK,
RST => RST,
D => CHECK_DATA(I)
);
END GENERATE DFF_CE_OTHERS;
END GENERATE BEGIN_EN_REG;
END ARCHITECTURE;
|
mit
|
VLSI-EDA/UVVM_All
|
uvvm_vvc_framework/src/ti_vvc_framework_support_pkg.vhd
|
1
|
24677
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
package ti_vvc_framework_support_pkg is
constant C_VVC_NAME_MAX_LENGTH : natural := 20;
------------------------------------------------------------------------
-- Common support types for UVVM
------------------------------------------------------------------------
type t_immediate_or_queued is (NO_command_type, IMMEDIATE, QUEUED);
type t_flag_record is record
set : std_logic;
reset : std_logic;
is_active : std_logic;
end record;
type t_uvvm_state is (IDLE, PHASE_A, PHASE_B, INIT_COMPLETED);
type t_lastness is (LAST, NOT_LAST);
type t_broadcastable_cmd is (NO_CMD, ENABLE_LOG_MSG, DISABLE_LOG_MSG, FLUSH_COMMAND_QUEUE, INSERT_DELAY, AWAIT_COMPLETION, TERMINATE_CURRENT_COMMAND);
constant C_BROADCAST_CMD_STRING_MAX_LENGTH : natural := 300;
type t_vvc_broadcast_cmd_record is record
operation : t_broadcastable_cmd;
msg_id : t_msg_id;
msg : string(1 to C_BROADCAST_CMD_STRING_MAX_LENGTH);
proc_call : string(1 to C_BROADCAST_CMD_STRING_MAX_LENGTH);
quietness : t_quietness;
delay : time;
timeout : time;
gen_integer : integer;
end record;
constant C_VVC_BROADCAST_CMD_DEFAULT : t_vvc_broadcast_cmd_record := (
operation => NO_CMD,
msg_id => NO_ID,
msg => (others => NUL),
proc_call => (others => NUL),
quietness => NON_QUIET,
delay => 0 ns,
timeout => 0 ns,
gen_integer => -1
);
------------------------------------------------------------------------
-- Common signals for acknowledging a pending command
------------------------------------------------------------------------
shared variable shared_vvc_broadcast_cmd : t_vvc_broadcast_cmd_record := C_VVC_BROADCAST_CMD_DEFAULT;
signal VVC_BROADCAST : std_logic := 'L';
------------------------------------------------------------------------
-- Common signal for signalling between VVCs, used during await_any_completion()
-- Default (when not active): Z
-- Awaiting: 1:
-- Completed: 0
-- This signal is a vector to support multiple sequencers calling await_any_completion simultaneously:
-- - When calling await_any_completion, each sequencer specifies which bit in this global signal the VVCs shall use.
------------------------------------------------------------------------
signal global_awaiting_completion : std_logic_vector(C_MAX_NUM_SEQUENCERS-1 downto 0); -- ACK on global triggers
------------------------------------------------------------------------
-- Shared variables for UVVM framework
------------------------------------------------------------------------
shared variable shared_cmd_idx : integer := 0;
shared variable shared_uvvm_state : t_uvvm_state := IDLE;
-------------------------------------------
-- flag_handler
-------------------------------------------
-- Flag handler is a general flag/semaphore handling mechanism between two separate processes/threads
-- The idea is to allow one process to set a flag and another to reset it. The flag may then be used by both - or others
-- May be used for a message from process 1 to process 2 with acknowledge; - like do-something & done, or valid & ack
procedure flag_handler(
signal flag : inout t_flag_record
);
-------------------------------------------
-- set_flag
-------------------------------------------
-- Sets reset and is_active to 'Z' and pulses set_flag
procedure set_flag(
signal flag : inout t_flag_record
);
-------------------------------------------
-- reset_flag
-------------------------------------------
-- Sets set and is_active to 'Z' and pulses reset_flag
procedure reset_flag(
signal flag : inout t_flag_record
);
-------------------------------------------
-- await_uvvm_initialization
-------------------------------------------
-- Waits until uvvm has been initialized
procedure await_uvvm_initialization(
constant dummy : in t_void
);
-------------------------------------------
-- format_command_idx
-------------------------------------------
-- Converts the command index to string, enclused by
-- C_CMD_IDX_PREFIX and C_CMD_IDX_SUFFIX
impure function format_command_idx(
command_idx : integer
) return string;
--***********************************************
-- BROADCAST COMMANDS
--***********************************************
-------------------------------------------
-- enable_log_msg (Broadcast)
-------------------------------------------
-- Enables a log message for all VVCs
procedure enable_log_msg(
signal VVC_BROADCAST : inout std_logic;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-------------------------------------------
-- disable_log_msg (Broadcast)
-------------------------------------------
-- Disables a log message for all VVCs
procedure disable_log_msg(
signal VVC_BROADCAST : inout std_logic;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-------------------------------------------
-- flush_command_queue (Broadcast)
-------------------------------------------
-- Flushes the command queue for all VVCs
procedure flush_command_queue(
signal VVC_BROADCAST : inout std_logic;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-------------------------------------------
-- insert_delay (Broadcast)
-------------------------------------------
-- Inserts delay into all VVCs (specified as number of clock cycles)
procedure insert_delay(
signal VVC_BROADCAST : inout std_logic;
constant delay : in natural; -- in clock cycles
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-------------------------------------------
-- insert_delay (Broadcast)
-------------------------------------------
-- Inserts delay into all VVCs (specified as time)
procedure insert_delay(
signal VVC_BROADCAST : inout std_logic;
constant delay : in time;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-------------------------------------------
-- await_completion (Broadcast)
-------------------------------------------
-- Wait for all VVCs to finish (specified as time)
procedure await_completion(
signal VVC_BROADCAST : inout std_logic;
constant timeout : in time;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-------------------------------------------
-- terminate_current_command (Broadcast)
-------------------------------------------
-- terminates all current tasks
procedure terminate_current_command(
signal VVC_BROADCAST : inout std_logic;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-------------------------------------------
-- terminate_all_commands (Broadcast)
-------------------------------------------
-- terminates all tasks
procedure terminate_all_commands(
signal VVC_BROADCAST : inout std_logic;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-------------------------------------------
-- transmit_broadcast
-------------------------------------------
-- Common broadcast transmission routine
procedure transmit_broadcast(
signal VVC_BROADCAST : inout std_logic;
constant operation : in t_broadcastable_cmd;
constant proc_call : in string;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET;
constant delay : in time := 0 ns;
constant delay_int : in integer := -1;
constant timeout : in time := std.env.resolution_limit;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
-------------------------------------------
-- get_scope_for_log
-------------------------------------------
-- Returns a string with length <= C_LOG_SCOPE_WIDTH.
-- Inputs vvc_name and channel are truncated to match C_LOG_SCOPE_WIDTH if to long.
-- An alert is issued if C_MINIMUM_VVC_NAME_SCOPE_WIDTH and C_MINIMUM_CHANNEL_SCOPE_WIDTH
-- are to long relative to C_LOG_SCOPE_WIDTH.
impure function get_scope_for_log(
constant vvc_name : string;
constant instance_idx : natural;
constant channel : t_channel
) return string;
-------------------------------------------
-- get_scope_for_log
-------------------------------------------
-- Returns a string with length <= C_LOG_SCOPE_WIDTH.
-- Input vvc_name is truncated to match C_LOG_SCOPE_WIDTH if to long.
-- An alert is issued if C_MINIMUM_VVC_NAME_SCOPE_WIDTH
-- is to long relative to C_LOG_SCOPE_WIDTH.
impure function get_scope_for_log(
constant vvc_name : string;
constant instance_idx : natural
) return string;
end package ti_vvc_framework_support_pkg;
package body ti_vvc_framework_support_pkg is
------------------------------------------------------------------------
--
------------------------------------------------------------------------
-- Flag handler is a general flag/semaphore handling mechanism between two separate processes/threads
-- The idea is to allow one process to set a flag and another to reset it. The flag may then be used by both - or others
-- May be used for a message from process 1 to process 2 with acknowledge; - like do-something & done, or valid & ack
procedure flag_handler(
signal flag : inout t_flag_record
) is
begin
flag.reset <= 'Z';
flag.set <= 'Z';
flag.is_active <= '0';
wait until flag.set = '1';
flag.is_active <= '1';
wait until flag.reset = '1';
flag.is_active <= '0';
end procedure;
procedure set_flag(
signal flag : inout t_flag_record
) is
begin
flag.reset <= 'Z';
flag.is_active <= 'Z';
gen_pulse(flag.set, 0 ns, "set flag");
end procedure;
procedure reset_flag(
signal flag : inout t_flag_record
) is
begin
flag.set <= 'Z';
flag.is_active <= 'Z';
gen_pulse(flag.reset, 0 ns, "reset flag", C_TB_SCOPE_DEFAULT, ID_NEVER);
end procedure;
-- This procedure checks the shared_uvvm_state on each delta cycle
procedure await_uvvm_initialization(
constant dummy : in t_void) is
begin
while (shared_uvvm_state /= INIT_COMPLETED) loop
wait for 0 ns;
end loop;
end procedure;
impure function format_command_idx(
command_idx : integer
) return string is
begin
return C_CMD_IDX_PREFIX & to_string(command_idx) & C_CMD_IDX_SUFFIX;
end;
procedure enable_log_msg(
signal VVC_BROADCAST : inout std_logic;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "enable_log_msg";
constant proc_call : string := proc_name & "(VVC_BROADCAST, " & to_upper(to_string(msg_id)) & ")";
begin
transmit_broadcast(VVC_BROADCAST, ENABLE_LOG_MSG, proc_call, msg_id, msg, quietness, scope => scope);
end procedure;
procedure disable_log_msg(
signal VVC_BROADCAST : inout std_logic;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "disable_log_msg";
constant proc_call : string := proc_name & "(VVC_BROADCAST, " & to_upper(to_string(msg_id)) & ")";
begin
transmit_broadcast(VVC_BROADCAST, DISABLE_LOG_MSG, proc_call, msg_id, msg, quietness, scope => scope);
end procedure;
procedure flush_command_queue(
signal VVC_BROADCAST : inout std_logic;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "flush_command_queue";
constant proc_call : string := proc_name & "(VVC_BROADCAST)";
begin
transmit_broadcast(VVC_BROADCAST, FLUSH_COMMAND_QUEUE, proc_call, NO_ID, msg, scope => scope);
end procedure;
procedure insert_delay(
signal VVC_BROADCAST : inout std_logic;
constant delay : in natural; -- in clock cycles
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "insert_delay";
constant proc_call : string := proc_name & "(VVC_BROADCAST, " & to_string(delay) & ")";
begin
transmit_broadcast(VVC_BROADCAST, FLUSH_COMMAND_QUEUE, proc_call, NO_ID, msg, NON_QUIET, 0 ns, delay, scope => scope);
end procedure;
procedure insert_delay(
signal VVC_BROADCAST : inout std_logic;
constant delay : in time;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "insert_delay";
constant proc_call : string := proc_name & "(VVC_BROADCAST, " & to_string(delay) & ")";
begin
transmit_broadcast(VVC_BROADCAST, INSERT_DELAY, proc_call, NO_ID, msg, NON_QUIET, delay, scope => scope);
end procedure;
procedure await_completion(
signal VVC_BROADCAST : inout std_logic;
constant timeout : in time;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "await_completion";
constant proc_call : string := proc_name & "(VVC_BROADCAST)";
begin
transmit_broadcast(VVC_BROADCAST, AWAIT_COMPLETION, proc_call, NO_ID, msg, NON_QUIET, 0 ns, -1, timeout, scope);
end procedure;
procedure terminate_current_command(
signal VVC_BROADCAST : inout std_logic;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "terminate_current_command";
constant proc_call : string := proc_name & "(VVC_BROADCAST)";
begin
transmit_broadcast(VVC_BROADCAST, TERMINATE_CURRENT_COMMAND, proc_call, NO_ID, msg, scope => scope);
end procedure;
procedure terminate_all_commands(
signal VVC_BROADCAST : inout std_logic;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "terminate_all_commands";
constant proc_call : string := proc_name & "(VVC_BROADCAST)";
begin
flush_command_queue(VVC_BROADCAST, msg);
terminate_current_command(VVC_BROADCAST, msg, scope => scope);
end procedure;
procedure transmit_broadcast(
signal VVC_BROADCAST : inout std_logic;
constant operation : in t_broadcastable_cmd;
constant proc_call : in string;
constant msg_id : in t_msg_id;
constant msg : in string := "";
constant quietness : in t_quietness := NON_QUIET;
constant delay : in time := 0 ns;
constant delay_int : in integer := -1;
constant timeout : in time := std.env.resolution_limit;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)") is
begin
await_semaphore_in_delta_cycles(protected_semaphore);
-- Increment shared_cmd_idx. It is protected by the protected_semaphore and only one sequencer can access the variable at a time.
shared_cmd_idx := shared_cmd_idx + 1;
if global_show_msg_for_uvvm_cmd then
log(ID_UVVM_SEND_CMD, to_string(proc_call) & ": " & add_msg_delimiter(to_string(msg))
& format_command_idx(shared_cmd_idx), scope);
else
log(ID_UVVM_SEND_CMD, to_string(proc_call)
& format_command_idx(shared_cmd_idx), scope);
end if;
shared_vvc_broadcast_cmd.operation := operation;
shared_vvc_broadcast_cmd.msg_id := msg_id;
shared_vvc_broadcast_cmd.msg := (others => NUL); -- default empty
shared_vvc_broadcast_cmd.msg(1 to msg'length) := msg;
shared_vvc_broadcast_cmd.quietness := quietness;
shared_vvc_broadcast_cmd.timeout := timeout;
shared_vvc_broadcast_cmd.delay := delay;
shared_vvc_broadcast_cmd.gen_integer := delay_int;
shared_vvc_broadcast_cmd.proc_call := (others => NUL); -- default empty
shared_vvc_broadcast_cmd.proc_call(1 to proc_call'length) := proc_call;
if VVC_BROADCAST /= 'L' then
-- a VVC is waiting for example in await_completion
wait until VVC_BROADCAST = 'L';
end if;
-- Trigger the broadcast
VVC_BROADCAST <= '1';
wait for 0 ns;
-- set back to 'L' and wait until all VVCs have set it back
VVC_BROADCAST <= 'L';
wait until VVC_BROADCAST = 'L' for timeout; -- Wait for executor
if not (VVC_BROADCAST'event) and VVC_BROADCAST /= 'L' then -- Indicates timeout
tb_error("Timeout while waiting for the broadcast command to be ACK'ed", scope);
else
log(ID_UVVM_CMD_ACK, "ACK received for broadcast command" & format_command_idx(shared_cmd_idx), scope);
end if;
shared_vvc_broadcast_cmd := C_VVC_BROADCAST_CMD_DEFAULT;
wait for 0 ns;
wait for 0 ns;
wait for 0 ns;
wait for 0 ns;
wait for 0 ns;
release_semaphore(protected_semaphore);
end procedure;
impure function get_scope_for_log(
constant vvc_name : string;
constant instance_idx : natural;
constant channel : t_channel
) return string is
constant C_INSTANCE_IDX_STR : string := to_string(instance_idx);
constant C_CHANNEL_STR : string := to_upper(to_string(channel));
constant C_SCOPE_LENGTH : natural := vvc_name'length + C_INSTANCE_IDX_STR'length + C_CHANNEL_STR'length + 2; -- +2 because of the two added commas
variable v_vvc_name_truncation_value : integer;
variable v_channel_truncation_value : integer;
variable v_vvc_name_truncation_idx : integer;
variable v_channel_truncation_idx : integer;
begin
if (C_MINIMUM_VVC_NAME_SCOPE_WIDTH + C_MINIMUM_CHANNEL_SCOPE_WIDTH + C_INSTANCE_IDX_STR'length + 2) > C_LOG_SCOPE_WIDTH then -- +2 because of the two added commas
alert(TB_WARNING, "The combined width of C_MINIMUM_VVC_NAME_SCOPE_WIDTH and C_MINIMUM_CHANNEL_SCOPE_WIDTH cannot be greater than C_LOG_SCOPE_WIDTH - (number of characters in instance) - 2.", C_SCOPE);
end if;
-- If C_SCOPE_LENGTH is not greater than allowed width, return scope
if C_SCOPE_LENGTH <= C_LOG_SCOPE_WIDTH then
return vvc_name & "," & C_INSTANCE_IDX_STR & "," & C_CHANNEL_STR;
-- If C_SCOPE_LENGTH is greater than allowed width
-- Check if vvc_name is greater than minimum width to truncate
elsif vvc_name'length <= C_MINIMUM_VVC_NAME_SCOPE_WIDTH then
return vvc_name & "," & C_INSTANCE_IDX_STR & "," & C_CHANNEL_STR(1 to (C_CHANNEL_STR'length - (C_SCOPE_LENGTH-C_LOG_SCOPE_WIDTH)));
-- Check if channel is greater than minimum width to truncate
elsif C_CHANNEL_STR'length <= C_MINIMUM_CHANNEL_SCOPE_WIDTH then
return vvc_name(1 to (vvc_name'length - (C_SCOPE_LENGTH-C_LOG_SCOPE_WIDTH))) & "," & C_INSTANCE_IDX_STR & "," & C_CHANNEL_STR;
-- If both vvc_name and channel is to be truncated
else
-- Calculate linear scaling of truncation between vvc_name and channel: (a*x)/(a+b), (b*x)/(a+b)
v_vvc_name_truncation_idx := integer(round(real(vvc_name'length * (C_SCOPE_LENGTH-C_LOG_SCOPE_WIDTH)))/real(vvc_name'length + C_CHANNEL_STR'length));
v_channel_truncation_value := integer(round(real(C_CHANNEL_STR'length * (C_SCOPE_LENGTH-C_LOG_SCOPE_WIDTH)))/real(vvc_name'length + C_CHANNEL_STR'length));
-- In case division ended with .5 and both rounded up
if (v_vvc_name_truncation_idx + v_channel_truncation_value) > (C_SCOPE_LENGTH-C_LOG_SCOPE_WIDTH) then
v_channel_truncation_value := v_channel_truncation_value - 1;
end if;
-- Character index to truncate
v_vvc_name_truncation_idx := vvc_name'length - v_vvc_name_truncation_idx;
v_channel_truncation_idx := C_CHANNEL_STR'length - v_channel_truncation_value;
-- If bellow minimum name width
while v_vvc_name_truncation_idx < C_MINIMUM_VVC_NAME_SCOPE_WIDTH loop
v_vvc_name_truncation_idx := v_vvc_name_truncation_idx + 1;
v_channel_truncation_idx := v_channel_truncation_idx - 1;
end loop;
-- If bellow minimum channel width
while v_channel_truncation_idx < C_MINIMUM_CHANNEL_SCOPE_WIDTH loop
v_channel_truncation_idx := v_channel_truncation_idx + 1;
v_vvc_name_truncation_idx := v_vvc_name_truncation_idx - 1;
end loop;
return vvc_name(1 to v_vvc_name_truncation_idx) & "," & C_INSTANCE_IDX_STR & "," & C_CHANNEL_STR(1 to v_channel_truncation_idx);
end if;
end function;
impure function get_scope_for_log(
constant vvc_name : string;
constant instance_idx : natural
) return string is
constant C_INSTANCE_IDX_STR : string := to_string(instance_idx);
constant C_SCOPE_LENGTH : integer := vvc_name'length + C_INSTANCE_IDX_STR'length + 1; -- +1 because of the added comma
begin
if (C_MINIMUM_VVC_NAME_SCOPE_WIDTH + C_INSTANCE_IDX_STR'length + 1) > C_LOG_SCOPE_WIDTH then -- +1 because of the added comma
alert(TB_WARNING, "The width of C_MINIMUM_VVC_NAME_SCOPE_WIDTH cannot be greater than C_LOG_SCOPE_WIDTH - (number of characters in instance) - 1.", C_SCOPE);
end if;
-- If C_SCOPE_LENGTH is not greater than allowed width, return scope
if C_SCOPE_LENGTH <= C_LOG_SCOPE_WIDTH then
return vvc_name & "," & C_INSTANCE_IDX_STR;
-- If C_SCOPE_LENGTH is greater than allowed width truncate vvc_name
else
return vvc_name(1 to (vvc_name'length - (C_SCOPE_LENGTH-C_LOG_SCOPE_WIDTH))) & "," & C_INSTANCE_IDX_STR;
end if;
end function;
end package body ti_vvc_framework_support_pkg;
|
mit
|
VLSI-EDA/UVVM_All
|
bitvis_vip_scoreboard/tb/sb_uart_sbi_demo_tb.vhd
|
1
|
7654
|
--========================================================================================================================
-- Copyright (c) 2018 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library bitvis_uart;
use bitvis_uart.uart_pif_pkg.all;
library bitvis_vip_sbi;
use bitvis_vip_sbi.sbi_bfm_pkg.all;
library bitvis_vip_uart;
use bitvis_vip_uart.uart_bfm_pkg.all;
library bitvis_vip_scoreboard;
use bitvis_vip_scoreboard.slv_sb_pkg.all;
use bitvis_vip_scoreboard.generic_sb_support_pkg.all;
-- Test harness entity
entity sb_uart_sbi_demo_tb is
end entity sb_uart_sbi_demo_tb;
-- Test harness architecture
architecture func of sb_uart_sbi_demo_tb is
constant C_SCOPE : string := "TB";
constant C_ADDR_WIDTH : integer := 3;
constant C_DATA_WIDTH : integer := 8;
-- DSP interface and general control signals
signal clk : std_logic := '0';
signal clk_ena : boolean := false;
signal arst : std_logic := '0';
-- SBI signals
signal sbi_if : t_sbi_if(addr(C_ADDR_WIDTH-1 downto 0),
wdata(C_DATA_WIDTH-1 downto 0),
rdata(C_DATA_WIDTH-1 downto 0)) := init_sbi_if_signals(addr_width => C_ADDR_WIDTH,
data_width => C_DATA_WIDTH);
signal terminate_loop : std_logic := '0';
-- UART signals
signal uart_rx : std_logic := '1';
signal uart_tx : std_logic := '1';
constant C_CLK_PERIOD : time := 10 ns; -- 100 MHz
-- One SB for each side of the DUT
shared variable v_uart_sb : t_generic_sb;
shared variable v_sbi_sb : t_generic_sb;
begin
-----------------------------------------------------------------------------
-- Instantiate DUT
-----------------------------------------------------------------------------
i_uart: entity bitvis_uart.uart
port map (
-- DSP interface and general control signals
clk => clk,
arst => arst,
-- CPU interface
cs => sbi_if.cs,
addr => sbi_if.addr,
wr => sbi_if.wena,
rd => sbi_if.rena,
wdata => sbi_if.wdata,
rdata => sbi_if.rdata,
-- UART signals
rx_a => uart_tx,
tx => uart_rx
);
-----------------------------------------------------------------------------
-- Clock generator
-----------------------------------------------------------------------------
p_clk: clock_generator(clk, clk_ena, C_CLK_PERIOD, "tb clock");
-- Static '1' ready signal for the SBI VVC
sbi_if.ready <= '1';
-- Toggle the reset after 5 clock periods
p_arst: arst <= '1', '0' after 5 *C_CLK_PERIOD;
-----------------------------------------------------------------------------
-- Sequencer
-----------------------------------------------------------------------------
p_sequencer : process
variable v_data : std_logic_vector(7 downto 0);
variable v_uart_config : t_uart_bfm_config;
begin
set_log_file_name("sb_uart_sbi_demo_log.txt");
set_alert_file_name("sb_uart_sbi_demo_alert.txt");
-- Print the configuration to the log
report_global_ctrl(VOID);
report_msg_id_panel(VOID);
--enable_log_msg(ALL_MESSAGES);
disable_log_msg(ID_POS_ACK);
--disable_log_msg(ID_SEQUENCER_SUB);
log(ID_LOG_HDR_XL, "SCOREBOARD UART-SBI DEMO ", C_SCOPE);
------------------------------------------------------------
clk_ena <= true;
wait for 1 ns;
await_value(arst, '0', 0 ns, 6*C_CLK_PERIOD, TB_ERROR, "await deassertion of arst", C_SCOPE);
wait for C_CLK_PERIOD;
------------------------------------------------------------
-- Config
------------------------------------------------------------
-- Set scope of SBs
v_uart_sb.set_scope("SB UART");
v_sbi_sb.set_scope( "SB SBI");
log(ID_LOG_HDR, "Set configuration", C_SCOPE);
v_uart_sb.config(C_SB_CONFIG_DEFAULT, "Set config for SB UART");
v_sbi_sb.config( C_SB_CONFIG_DEFAULT, "Set config for SB SBI");
log(ID_LOG_HDR, "Enable SBs", C_SCOPE);
v_uart_sb.enable(VOID);
v_sbi_sb.enable(VOID);
-- Enable log msg for data
v_uart_sb.enable_log_msg(ID_DATA);
v_sbi_sb.enable_log_msg( ID_DATA);
v_uart_config := C_UART_BFM_CONFIG_DEFAULT;
v_uart_config.bit_time := C_CLK_PERIOD*16;
------------------------------------------------------------
-- UART --> SBI
------------------------------------------------------------
log(ID_LOG_HDR_LARGE, "Send data UART --> SBI", C_SCOPE);
for i in 1 to 5 loop
for j in 1 to 4 loop
v_data := random(8);
v_sbi_sb.add_expected(v_data);
uart_transmit(v_data, "data to DUT", uart_tx, v_uart_config);
end loop;
for j in 1 to 4 loop
sbi_poll_until(to_unsigned(C_ADDR_RX_DATA_VALID, 3), x"01", 0, 100 ns, "wait on data valid", clk, sbi_if, terminate_loop);
sbi_read(to_unsigned(C_ADDR_RX_DATA, 3), v_data, "read data from DUT", clk, sbi_if);
v_sbi_sb.check_received(v_data);
end loop;
end loop;
-- print report of counters
v_sbi_sb.report_counters(VOID);
------------------------------------------------------------
-- SBI --> UART
------------------------------------------------------------
log(ID_LOG_HDR_LARGE, "Send data SBI --> UART", C_SCOPE);
for i in 1 to 5 loop
for j in 1 to 4 loop
v_data := random(8);
v_uart_sb.add_expected(v_data);
sbi_poll_until(to_unsigned(C_ADDR_TX_READY, 3), x"01", 0, 100 ns, "wait on TX ready", clk, sbi_if, terminate_loop);
sbi_write(to_unsigned(C_ADDR_TX_DATA, 3), v_data, "write data to DUT", clk, sbi_if);
uart_receive(v_data, "data from DUT", uart_rx, terminate_loop, v_uart_config);
v_uart_sb.check_received(v_data);
end loop;
end loop;
-- print report of counters
v_uart_sb.report_counters(VOID);
--==================================================================================================
-- Ending the simulation
--------------------------------------------------------------------------------------
wait for 1000 ns; -- to allow some time for completion
report_alert_counters(FINAL); -- Report final counters and print conclusion for simulation (Success/Fail)
log(ID_LOG_HDR, "SIMULATION COMPLETED", C_SCOPE);
std.env.stop;
wait;
end process;
end architecture func;
|
mit
|
VLSI-EDA/UVVM_All
|
bitvis_vip_avalon_mm/src/avalon_mm_vvc.vhd
|
1
|
30201
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.avalon_mm_bfm_pkg.all;
use work.vvc_methods_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_target_support_pkg.all;
use work.td_vvc_entity_support_pkg.all;
use work.td_cmd_queue_pkg.all;
use work.td_result_queue_pkg.all;
--=================================================================================================
entity avalon_mm_vvc is
generic (
GC_ADDR_WIDTH : integer range 1 to C_VVC_CMD_ADDR_MAX_LENGTH := 8; -- Avalon MM address bus
GC_DATA_WIDTH : integer range 1 to C_VVC_CMD_DATA_MAX_LENGTH := 32; -- Avalon MM data bus
GC_INSTANCE_IDX : natural := 1; -- Instance index for this AVALON_MM_VVCT instance
GC_AVALON_MM_CONFIG : t_avalon_mm_bfm_config := C_AVALON_MM_BFM_CONFIG_DEFAULT; -- Behavior specification for BFM
GC_CMD_QUEUE_COUNT_MAX : natural := 1000;
GC_CMD_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING;
GC_RESULT_QUEUE_COUNT_MAX : natural := 1000;
GC_RESULT_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING
);
port (
clk : in std_logic;
avalon_mm_vvc_master_if : inout t_avalon_mm_if := init_avalon_mm_if_signals(GC_ADDR_WIDTH, GC_DATA_WIDTH)
);
begin
-- Check the interface widths to assure that the interface was correctly set up
assert (avalon_mm_vvc_master_if.address'length = GC_ADDR_WIDTH) report "avalon_mm_vvc_master_if.address'length /= GC_ADDR_WIDTH" severity failure;
assert (avalon_mm_vvc_master_if.writedata'length = GC_DATA_WIDTH) report "avalon_mm_vvc_master_if.writedata'length /= GC_DATA_WIDTH" severity failure;
assert (avalon_mm_vvc_master_if.readdata'length = GC_DATA_WIDTH) report "avalon_mm_vvc_master_if.readdata'length /= GC_DATA_WIDTH" severity failure;
assert (avalon_mm_vvc_master_if.byte_enable'length = GC_DATA_WIDTH/8) report "avalon_mm_vvc_master_if.byte_enable'length /= GC_DATA_WIDTH/8" severity failure;
end entity avalon_mm_vvc;
--=================================================================================================
--=================================================================================================
architecture behave of avalon_mm_vvc is
constant C_SCOPE : string := C_VVC_NAME & "," & to_string(GC_INSTANCE_IDX);
constant C_VVC_LABELS : t_vvc_labels := assign_vvc_labels(C_SCOPE, C_VVC_NAME, GC_INSTANCE_IDX, NA);
signal executor_is_busy : boolean := false;
signal queue_is_increasing : boolean := false;
signal read_response_is_busy : boolean := false;
signal response_queue_is_increasing : boolean := false;
signal last_cmd_idx_executed : natural := 0;
signal last_read_response_idx_executed : natural := 0;
signal terminate_current_cmd : t_flag_record;
-- Instantiation of element dedicated Queues
shared variable command_queue : work.td_cmd_queue_pkg.t_generic_queue;
shared variable command_response_queue : work.td_cmd_queue_pkg.t_generic_queue;
shared variable result_queue : work.td_result_queue_pkg.t_generic_queue;
alias vvc_config : t_vvc_config is shared_avalon_mm_vvc_config(GC_INSTANCE_IDX);
alias vvc_status : t_vvc_status is shared_avalon_mm_vvc_status(GC_INSTANCE_IDX);
alias transaction_info : t_transaction_info is shared_avalon_mm_transaction_info(GC_INSTANCE_IDX);
-- Propagation delayed interface signal used when reading data from the slave in the read_response process.
signal avalon_mm_vvc_master_if_pd : t_avalon_mm_if(address(GC_ADDR_WIDTH-1 downto 0),
byte_enable((GC_DATA_WIDTH/8)-1 downto 0),
writedata(GC_DATA_WIDTH-1 downto 0),
readdata(GC_DATA_WIDTH-1 downto 0)) := avalon_mm_vvc_master_if;
begin
--===============================================================================================
-- Constructor
-- - Set up the defaults and show constructor if enabled
--===============================================================================================
work.td_vvc_entity_support_pkg.vvc_constructor(C_SCOPE, GC_INSTANCE_IDX, vvc_config, command_queue, result_queue, GC_AVALON_MM_CONFIG,
GC_CMD_QUEUE_COUNT_MAX, GC_CMD_QUEUE_COUNT_THRESHOLD, GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
GC_RESULT_QUEUE_COUNT_MAX, GC_RESULT_QUEUE_COUNT_THRESHOLD, GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY);
--===============================================================================================
--===============================================================================================
-- Command interpreter
-- - Interpret, decode and acknowledge commands from the central sequencer
--===============================================================================================
cmd_interpreter : process
variable v_cmd_has_been_acked : boolean; -- Indicates if acknowledge_cmd() has been called for the current shared_vvc_cmd
variable v_local_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
begin
-- 0. Initialize the process prior to first command
work.td_vvc_entity_support_pkg.initialize_interpreter(terminate_current_cmd, global_awaiting_completion);
-- initialise shared_vvc_last_received_cmd_idx for channel and instance
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := 0;
-- Then for every single command from the sequencer
loop -- basically as long as new commands are received
-- 1. wait until command targeted at this VVC. Must match VVC name, instance and channel (if applicable)
-- releases global semaphore
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.await_cmd_from_sequencer(C_VVC_LABELS, vvc_config, THIS_VVCT, VVC_BROADCAST, global_vvc_busy, global_vvc_ack, v_local_vvc_cmd);
v_cmd_has_been_acked := false; -- Clear flag
-- update shared_vvc_last_received_cmd_idx with received command index
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := v_local_vvc_cmd.cmd_idx;
-- 2a. Put command on the queue if intended for the executor
-------------------------------------------------------------------------
if v_local_vvc_cmd.command_type = QUEUED then
work.td_vvc_entity_support_pkg.put_command_on_queue(v_local_vvc_cmd, command_queue, vvc_status, queue_is_increasing);
-- 2b. Otherwise command is intended for immediate response
-------------------------------------------------------------------------
elsif v_local_vvc_cmd.command_type = IMMEDIATE then
case v_local_vvc_cmd.operation is
when AWAIT_COMPLETION =>
-- Await completion of all commands in the cmd_executor queue
work.td_vvc_entity_support_pkg.interpreter_await_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed,ID_IMMEDIATE_CMD_WAIT,ID_NEVER);
-- Await completion of all commands in the read_response queue
work.td_vvc_entity_support_pkg.interpreter_await_completion(v_local_vvc_cmd, command_response_queue, vvc_config, read_response_is_busy, C_VVC_LABELS, last_read_response_idx_executed, ID_NEVER, ID_IMMEDIATE_CMD);
when AWAIT_ANY_COMPLETION =>
if not v_local_vvc_cmd.gen_boolean then
-- Called with lastness = NOT_LAST: Acknowledge immediately to let the sequencer continue
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
v_cmd_has_been_acked := true;
end if;
work.td_vvc_entity_support_pkg.interpreter_await_any_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed, global_awaiting_completion);
when DISABLE_LOG_MSG =>
uvvm_util.methods_pkg.disable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when ENABLE_LOG_MSG =>
uvvm_util.methods_pkg.enable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE, v_local_vvc_cmd.quietness);
when FLUSH_COMMAND_QUEUE =>
work.td_vvc_entity_support_pkg.interpreter_flush_command_queue(v_local_vvc_cmd, command_queue, vvc_config, vvc_status, C_VVC_LABELS);
when TERMINATE_CURRENT_COMMAND =>
work.td_vvc_entity_support_pkg.interpreter_terminate_current_command(v_local_vvc_cmd, vvc_config, C_VVC_LABELS, terminate_current_cmd, executor_is_busy);
when FETCH_RESULT =>
work.td_vvc_entity_support_pkg.interpreter_fetch_result(result_queue, v_local_vvc_cmd, vvc_config, C_VVC_LABELS, last_cmd_idx_executed, shared_vvc_response);
when others =>
tb_error("Unsupported command received for IMMEDIATE execution: '" & to_string(v_local_vvc_cmd.operation) & "'", C_SCOPE);
end case;
else
tb_error("command_type is not IMMEDIATE or QUEUED", C_SCOPE);
end if;
-- 3. Acknowledge command after runing or queuing the command
-------------------------------------------------------------------------
if not v_cmd_has_been_acked then
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
end if;
end loop;
end process;
--===============================================================================================
--===============================================================================================
-- Command executor
-- - Fetch and execute the commands.
-- - Note that the read response is handled in the read_response process.
--===============================================================================================
cmd_executor : process
variable v_cmd : t_vvc_cmd_record;
variable v_read_data : t_vvc_result; -- See vvc_cmd_pkg
variable v_timestamp_start_of_current_bfm_access : time := 0 ns;
variable v_timestamp_start_of_last_bfm_access : time := 0 ns;
variable v_timestamp_end_of_last_bfm_access : time := 0 ns;
variable v_command_is_bfm_access : boolean := false;
variable v_prev_command_was_bfm_access : boolean := false;
variable v_normalised_addr : unsigned(GC_ADDR_WIDTH-1 downto 0) := (others => '0');
variable v_normalised_data : std_logic_vector(GC_DATA_WIDTH-1 downto 0) := (others => '0');
variable v_normalised_byte_ena : std_logic_vector((GC_DATA_WIDTH/8)-1 downto 0) := (others => '0');
begin
-- 0. Initialize the process prior to first command
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.initialize_executor(terminate_current_cmd);
loop
-- 1. Set defaults, fetch command and log
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.fetch_command_and_prepare_executor(v_cmd, command_queue, vvc_config, vvc_status, queue_is_increasing, executor_is_busy, C_VVC_LABELS);
-- Set the transaction info for waveview
transaction_info := C_TRANSACTION_INFO_DEFAULT;
transaction_info.operation := v_cmd.operation;
transaction_info.msg := pad_string(to_string(v_cmd.msg), ' ', transaction_info.msg'length);
-- Check if command is a BFM access
v_prev_command_was_bfm_access := v_command_is_bfm_access; -- save for insert_bfm_delay
if v_cmd.operation = WRITE or v_cmd.operation = READ or v_cmd.operation = CHECK or v_cmd.operation = RESET then
v_command_is_bfm_access := true;
else
v_command_is_bfm_access := false;
end if;
-- Insert delay if needed
work.td_vvc_entity_support_pkg.insert_inter_bfm_delay_if_requested(vvc_config => vvc_config,
command_is_bfm_access => v_prev_command_was_bfm_access,
timestamp_start_of_last_bfm_access => v_timestamp_start_of_last_bfm_access,
timestamp_end_of_last_bfm_access => v_timestamp_end_of_last_bfm_access,
scope => C_SCOPE);
if v_command_is_bfm_access then
v_timestamp_start_of_current_bfm_access := now;
end if;
-- 2. Execute the fetched command
-------------------------------------------------------------------------
case v_cmd.operation is -- Only operations in the dedicated record are relevant
-- VVC dedicated operations
--===================================
when WRITE =>
-- Normalise address and data
v_normalised_addr := normalize_and_check(v_cmd.addr, v_normalised_addr, ALLOW_WIDER_NARROWER, "v_cmd.addr", "v_normalised_addr", "avalon_mm_write() called with to wide address. " & v_cmd.msg);
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "v_cmd.data", "v_normalised_data", "avalon_mm_write() called with to wide data. " & v_cmd.msg);
if (v_cmd.byte_enable = (0 to v_cmd.byte_enable'length-1 => '1')) then
v_normalised_byte_ena := (others => '1');
else
v_normalised_byte_ena := normalize_and_check(v_cmd.byte_enable, v_normalised_byte_ena, ALLOW_WIDER_NARROWER, "v_cmd.byte_enable", "v_normalised_byte_ena", "avalon_mm_write() called with to wide byte_enable. " & v_cmd.msg);
end if;
transaction_info.data(GC_DATA_WIDTH - 1 downto 0) := v_normalised_data;
transaction_info.addr(GC_ADDR_WIDTH - 1 downto 0) := v_normalised_addr;
transaction_info.byte_enable((GC_DATA_WIDTH/8) - 1 downto 0) := v_cmd.byte_enable((GC_DATA_WIDTH/8) - 1 downto 0);
-- Call the corresponding procedure in the BFM package.
avalon_mm_write(addr_value => v_normalised_addr,
data_value => v_normalised_data,
msg => format_msg(v_cmd),
clk => clk,
avalon_mm_if => avalon_mm_vvc_master_if,
byte_enable => v_cmd.byte_enable((GC_DATA_WIDTH/8)-1 downto 0),
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
when READ =>
-- Normalise address
v_normalised_addr := normalize_and_check(v_cmd.addr, v_normalised_addr, ALLOW_WIDER_NARROWER, "v_cmd.addr", "v_normalised_addr", "avalon_mm_read() called with to wide address. " & v_cmd.msg);
transaction_info.addr(GC_ADDR_WIDTH - 1 downto 0) := v_normalised_addr;
-- Call the corresponding procedure in the BFM package.
if vvc_config.use_read_pipeline then
-- Stall until response command queue is no longer full
while command_response_queue.get_count(VOID) > vvc_config.num_pipeline_stages loop
wait for vvc_config.bfm_config.clock_period;
end loop;
avalon_mm_read_request( addr_value => v_normalised_addr,
msg => format_msg(v_cmd),
clk => clk,
avalon_mm_if => avalon_mm_vvc_master_if,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
work.td_vvc_entity_support_pkg.put_command_on_queue(v_cmd, command_response_queue, vvc_status, response_queue_is_increasing);
else
avalon_mm_read( addr_value => v_normalised_addr,
data_value => v_read_data(GC_DATA_WIDTH-1 downto 0),
msg => format_msg(v_cmd),
clk => clk,
avalon_mm_if => avalon_mm_vvc_master_if,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
-- Store the result
work.td_vvc_entity_support_pkg.store_result( result_queue => result_queue,
cmd_idx => v_cmd.cmd_idx,
result => v_read_data );
end if;
when CHECK =>
-- Normalise address
v_normalised_addr := normalize_and_check(v_cmd.addr, v_normalised_addr, ALLOW_WIDER_NARROWER, "v_cmd.addr", "v_normalised_addr", "avalon_mm_check() called with to wide address. " & v_cmd.msg);
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "v_cmd.data", "v_normalised_data", "avalon_mm_check() called with to wide data. " & v_cmd.msg);
transaction_info.data(GC_DATA_WIDTH - 1 downto 0) := v_normalised_data;
transaction_info.addr(GC_ADDR_WIDTH - 1 downto 0) := v_normalised_addr;
-- Call the corresponding procedure in the BFM package.
if vvc_config.use_read_pipeline then
-- Wait until response command queue is no longer full
while command_response_queue.get_count(VOID) > vvc_config.num_pipeline_stages loop
wait for vvc_config.bfm_config.clock_period;
end loop;
avalon_mm_read_request( addr_value => v_normalised_addr,
msg => format_msg(v_cmd),
clk => clk,
avalon_mm_if => avalon_mm_vvc_master_if,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config,
ext_proc_call => "avalon_mm_check(A:" & to_string(v_normalised_addr, HEX, AS_IS, INCL_RADIX) & ", " & to_string(v_normalised_data, HEX, AS_IS, INCL_RADIX) & ")"
);
work.td_vvc_entity_support_pkg.put_command_on_queue(v_cmd, command_response_queue, vvc_status, response_queue_is_increasing);
else
avalon_mm_check(addr_value => v_normalised_addr,
data_exp => v_normalised_data,
msg => format_msg(v_cmd),
clk => clk,
avalon_mm_if => avalon_mm_vvc_master_if,
alert_level => v_cmd.alert_level,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
end if;
when RESET =>
-- Call the corresponding procedure in the BFM package.
avalon_mm_reset(clk => clk,
avalon_mm_if => avalon_mm_vvc_master_if,
num_rst_cycles => v_cmd.gen_integer_array(0),
msg => format_msg(v_cmd),
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
when LOCK =>
-- Call the corresponding procedure in the BFM package.
avalon_mm_lock( avalon_mm_if => avalon_mm_vvc_master_if,
msg => format_msg(v_cmd),
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
when UNLOCK =>
-- Call the corresponding procedure in the BFM package.
avalon_mm_unlock( avalon_mm_if => avalon_mm_vvc_master_if,
msg => format_msg(v_cmd),
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
-- UVVM common operations
--===================================
when INSERT_DELAY =>
log(ID_INSERTED_DELAY, "Running: " & to_string(v_cmd.proc_call) & " " & format_command_idx(v_cmd), C_SCOPE, vvc_config.msg_id_panel);
if v_cmd.gen_integer_array(0) = -1 then
-- Delay specified using time
wait until terminate_current_cmd.is_active = '1' for v_cmd.delay;
else
-- Delay specified using integer
wait until terminate_current_cmd.is_active = '1' for v_cmd.gen_integer_array(0) * vvc_config.bfm_config.clock_period;
end if;
when others =>
tb_error("Unsupported local command received for execution: '" & to_string(v_cmd.operation) & "'", C_SCOPE);
end case;
if v_command_is_bfm_access then
v_timestamp_end_of_last_bfm_access := now;
v_timestamp_start_of_last_bfm_access := v_timestamp_start_of_current_bfm_access;
if ((vvc_config.inter_bfm_delay.delay_type = TIME_START2START) and
((now - v_timestamp_start_of_current_bfm_access) > vvc_config.inter_bfm_delay.delay_in_time)) then
alert(vvc_config.inter_bfm_delay.inter_bfm_delay_violation_severity, "BFM access exceeded specified start-to-start inter-bfm delay, " &
to_string(vvc_config.inter_bfm_delay.delay_in_time) & ".", C_SCOPE);
end if;
end if;
-- Reset terminate flag if any occurred
if (terminate_current_cmd.is_active = '1') then
log(ID_CMD_EXECUTOR, "Termination request received", C_SCOPE, vvc_config.msg_id_panel);
uvvm_vvc_framework.ti_vvc_framework_support_pkg.reset_flag(terminate_current_cmd);
end if;
last_cmd_idx_executed <= v_cmd.cmd_idx;
-- Reset the transaction info for waveview
transaction_info := C_TRANSACTION_INFO_DEFAULT;
end loop;
end process;
--===============================================================================================
--===============================================================================================
-- Add a delta cycle to the read response interface signals to avoid reading wrong data.
--===============================================================================================
avalon_mm_vvc_master_if_pd <= transport avalon_mm_vvc_master_if after std.env.resolution_limit;
--===============================================================================================
-- Read response command execution.
-- - READ (and CHECK) data received from the slave after the command executor has issued an
-- read request (or check).
-- - Note the use of propagation delayed avalon_mm_vv_master_if signal
--===============================================================================================
read_response : process
variable v_cmd : t_vvc_cmd_record;
variable v_read_data : t_vvc_result; -- See vvc_cmd_pkg
variable v_normalised_addr : unsigned(GC_ADDR_WIDTH-1 downto 0) := (others => '0');
variable v_normalised_data : std_logic_vector(GC_DATA_WIDTH-1 downto 0) := (others => '0');
begin
-- Set the command response queue up to the same settings as the command queue
command_response_queue.set_scope(C_SCOPE & ":RQ");
command_response_queue.set_queue_count_max(vvc_config.cmd_queue_count_max);
command_response_queue.set_queue_count_threshold(vvc_config.cmd_queue_count_threshold);
command_response_queue.set_queue_count_threshold_severity(vvc_config.cmd_queue_count_threshold_severity);
wait for 0 ns; -- Wait for command response queue to initialize completely
loop
-- Fetch commands
work.td_vvc_entity_support_pkg.fetch_command_and_prepare_executor(v_cmd, command_response_queue, vvc_config, vvc_status, response_queue_is_increasing, read_response_is_busy, C_VVC_LABELS);
-- Normalise address and data
v_normalised_addr := normalize_and_check(v_cmd.addr, v_normalised_addr, ALLOW_WIDER_NARROWER, "addr", "shared_vvc_cmd.addr", "Function called with to wide address. " & v_cmd.msg);
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", "Function called with to wide data. " & v_cmd.msg);
case v_cmd.operation is
when READ =>
-- Initiate read response
avalon_mm_read_response(addr_value => v_normalised_addr,
data_value => v_read_data(GC_DATA_WIDTH-1 downto 0),
msg => format_msg(v_cmd),
clk => clk,
avalon_mm_if => avalon_mm_vvc_master_if_pd,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
-- Store the result
work.td_vvc_entity_support_pkg.store_result( result_queue => result_queue,
cmd_idx => v_cmd.cmd_idx,
result => v_read_data);
when CHECK =>
-- Initiate check response
avalon_mm_check_response( addr_value => v_normalised_addr,
data_exp => v_normalised_data,
msg => format_msg(v_cmd),
clk => clk,
avalon_mm_if => avalon_mm_vvc_master_if_pd,
alert_level => v_cmd.alert_level,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
when others =>
tb_error("Unsupported local command received for execution: '" & to_string(v_cmd.operation) & "'", C_SCOPE);
end case;
last_read_response_idx_executed <= v_cmd.cmd_idx;
end loop;
end process;
--===============================================================================================
--===============================================================================================
-- Command termination handler
-- - Handles the termination request record (sets and resets terminate flag on request)
--===============================================================================================
cmd_terminator : uvvm_vvc_framework.ti_vvc_framework_support_pkg.flag_handler(terminate_current_cmd); -- flag: is_active, set, reset
--===============================================================================================
end behave;
|
mit
|
VLSI-EDA/UVVM_All
|
uvvm_vvc_framework/src/ti_data_stack_pkg.vhd
|
3
|
8489
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_data_queue_pkg.all;
package ti_data_stack_pkg is
shared variable shared_data_stack : t_data_queue;
------------------------------------------
-- uvvm_stack_init
------------------------------------------
-- This function allocates space in the buffer and returns an index that
-- must be used to access the stack.
--
-- - Parameters:
-- - buffer_size_in_bits (natural) - The size of the stack
--
-- - Returns: The index of the initiated stack (natural).
-- Returns 0 on error.
--
impure function uvvm_stack_init(
buffer_size_in_bits : natural
) return natural;
------------------------------------------
-- uvvm_stack_init
------------------------------------------
-- This procedure allocates space in the buffer at the given buffer_idx.
--
-- - Parameters:
-- - buffer_idx - The index of the stack (natural)
-- that shall be initialized.
-- - buffer_size_in_bits (natural) - The size of the stack
--
procedure uvvm_stack_init(
buffer_index : natural;
buffer_size_in_bits : natural
);
------------------------------------------
-- uvvm_stack_push
------------------------------------------
-- This procedure puts data into a stack with index buffer_idx.
-- The size of the data is unconstrained, meaning that
-- it can be any size. Pushing data with a size that is
-- larger than the stack size results in wrapping, i.e.,
-- that when reaching the end the data remaining will over-
-- write the data that was written first.
--
-- - Parameters:
-- - buffer_idx - The index of the stack (natural)
-- that shall be pushed to.
-- - data - The data that shall be pushed (slv)
--
procedure uvvm_stack_push(
buffer_index : natural;
data : std_logic_vector
);
------------------------------------------
-- uvvm_stack_pop
------------------------------------------
-- This function returns the data from the stack
-- and removes the returned data from the stack.
--
-- - Parameters:
-- - buffer_idx - The index of the stack (natural)
-- that shall be read.
-- - entry_size_in_bits - The size of the returned slv (natural)
--
-- - Returns: Data from the stack (slv). The size of the
-- return data is given by the entry_size_in_bits parameter.
-- Attempting to pop from an empty stack is allowed but triggers a
-- TB_WARNING and returns garbage.
-- Attempting to pop a larger value than the stack size is allowed
-- but triggers a TB_WARNING.
--
--
impure function uvvm_stack_pop(
buffer_index : natural;
entry_size_in_bits : natural
) return std_logic_vector;
------------------------------------------
-- uvvm_stack_flush
------------------------------------------
-- This procedure empties the stack given
-- by buffer_idx.
--
-- - Parameters:
-- - buffer_idx - The index of the stack (natural)
-- that shall be flushed.
--
procedure uvvm_stack_flush(
buffer_index : natural
);
------------------------------------------
-- uvvm_stack_peek
------------------------------------------
-- This function returns the data from the stack
-- without removing it.
--
-- - Parameters:
-- - buffer_idx - The index of the stack (natural)
-- that shall be read.
-- - entry_size_in_bits - The size of the returned slv (natural)
--
-- - Returns: Data from the stack. The size of the
-- return data is given by the entry_size_in_bits parameter.
-- Attempting to peek from an empty stack is allowed but triggers a
-- TB_WARNING and returns garbage.
-- Attempting to peek a larger value than the stack size is allowed
-- but triggers a TB_WARNING. Will wrap.
--
--
impure function uvvm_stack_peek(
buffer_index : natural;
entry_size_in_bits : natural
) return std_logic_vector;
------------------------------------------
-- uvvm_stack_get_count
------------------------------------------
-- This function returns a natural indicating the number of elements
-- currently occupying the stack given by buffer_idx.
--
-- - Parameters:
-- - buffer_idx - The index of the stack (natural)
--
-- - Returns: The number of elements occupying the stack (natural).
--
--
impure function uvvm_stack_get_count(
buffer_idx : natural
) return natural;
------------------------------------------
-- uvvm_stack_get_max_count
------------------------------------------
-- This function returns a natural indicating the maximum number
-- of elements that can occupy the stack given by buffer_idx.
--
-- - Parameters:
-- - buffer_idx - The index of the stack (natural)
--
-- - Returns: The maximum number of elements that can be placed
-- in the stack (natural).
--
--
impure function uvvm_stack_get_max_count(
buffer_index : natural
) return natural;
end package ti_data_stack_pkg;
package body ti_data_stack_pkg is
impure function uvvm_stack_init(
buffer_size_in_bits : natural
) return natural is
begin
return shared_data_stack.init_queue(buffer_size_in_bits, "UVVM_STACK");
end function;
procedure uvvm_stack_init(
buffer_index : natural;
buffer_size_in_bits : natural
) is
begin
shared_data_stack.init_queue(buffer_index, buffer_size_in_bits, "UVVM_STACK");
end procedure;
procedure uvvm_stack_push(
buffer_index : natural;
data : std_logic_vector
) is
begin
shared_data_stack.push_back(buffer_index,data);
end procedure;
impure function uvvm_stack_pop(
buffer_index : natural;
entry_size_in_bits : natural
) return std_logic_vector is
begin
return shared_data_stack.pop_back(buffer_index, entry_size_in_bits);
end function;
procedure uvvm_stack_flush(
buffer_index : natural
) is
begin
shared_data_stack.flush(buffer_index);
end procedure;
impure function uvvm_stack_peek(
buffer_index : natural;
entry_size_in_bits : natural
) return std_logic_vector is
begin
return shared_data_stack.peek_back(buffer_index, entry_size_in_bits);
end function;
impure function uvvm_stack_get_count(
buffer_idx : natural
) return natural is
begin
return shared_data_stack.get_count(buffer_idx);
end function;
impure function uvvm_stack_get_max_count(
buffer_index : natural
) return natural is
begin
return shared_data_stack.get_queue_count_max(buffer_index);
end function;
end package body ti_data_stack_pkg;
|
mit
|
VLSI-EDA/UVVM_All
|
bitvis_vip_uart/src/uart_vvc.vhd
|
3
|
3798
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
use work.uart_bfm_pkg.all;
use work.vvc_cmd_pkg.all;
--=================================================================================================
entity uart_vvc is
generic (
GC_DATA_WIDTH : natural range 1 to C_VVC_CMD_DATA_MAX_LENGTH := 8;
GC_INSTANCE_IDX : natural := 1;
GC_UART_CONFIG : t_uart_bfm_config := C_UART_BFM_CONFIG_DEFAULT;
GC_CMD_QUEUE_COUNT_MAX : natural := 1000;
GC_CMD_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING
);
port (
uart_vvc_rx : in std_logic;
uart_vvc_tx : inout std_logic
);
end entity uart_vvc;
--=================================================================================================
--=================================================================================================
architecture struct of uart_vvc is
begin
-- UART RX VVC
i1_uart_rx: entity work.uart_rx_vvc
generic map(
GC_DATA_WIDTH => GC_DATA_WIDTH,
GC_INSTANCE_IDX => GC_INSTANCE_IDX,
GC_CHANNEL => RX,
GC_UART_CONFIG => GC_UART_CONFIG,
GC_CMD_QUEUE_COUNT_MAX => GC_CMD_QUEUE_COUNT_MAX,
GC_CMD_QUEUE_COUNT_THRESHOLD => GC_CMD_QUEUE_COUNT_THRESHOLD,
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY => GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY
)
port map(
uart_vvc_rx => uart_vvc_rx
);
-- UART TX VVC
i1_uart_tx: entity work.uart_tx_vvc
generic map(
GC_DATA_WIDTH => GC_DATA_WIDTH,
GC_INSTANCE_IDX => GC_INSTANCE_IDX,
GC_CHANNEL => TX,
GC_UART_CONFIG => GC_UART_CONFIG,
GC_CMD_QUEUE_COUNT_MAX => GC_CMD_QUEUE_COUNT_MAX,
GC_CMD_QUEUE_COUNT_THRESHOLD => GC_CMD_QUEUE_COUNT_THRESHOLD,
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY => GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY
)
port map(
uart_vvc_tx => uart_vvc_tx
);
end struct;
|
mit
|
VLSI-EDA/UVVM_All
|
xConstrRandFuncCov/src/RandomPkg.vhd
|
3
|
65032
|
--
-- File Name : RandomPkg.vhd
-- Design Unit Name : RandomPkg
-- Revision : STANDARD VERSION
--
-- Maintainer : Jim Lewis email : [email protected]
-- Contributor(s) :
-- Jim Lewis email : [email protected]
-- *
--
-- * In writing procedures normal, poisson, the following sources were referenced :
-- Wikipedia
-- package rnd2 written by John Breen and Ken Christensen
-- package RNG written by Gnanasekaran Swaminathan
--
--
-- Description :
-- RandomPType, a protected type, defined to hold randomization RandomSeeds and
-- function methods to facilitate randomization with uniform and weighted
-- distributions
--
-- Developed for :
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http ://www.SynthWorks.com
--
-- Revision History :
-- Date Version Description
-- 12/2006 : 0.1 Initial revision
-- Numerous revisions for SynthWorks' Advanced VHDL Testbenches and Verification
-- 02/2009 : 1.0 First Public Released Version
-- 02/25/2009 1.1 Replaced reference to std_2008 with a reference to
-- ieee_proposed.standard_additions.all ;
-- 06/2010 1.2 Added Normal and Poisson distributions
-- 03/2011 2.0 Major clean-up. Moved RandomParmType and control to here
-- 07/2011 2.1 Bug fix to convenience functions for slv, unsigned, and signed.
-- 06/2012 2.2 Removed '_' in the name of subprograms FavorBig and FavorSmall
-- 04/2013 2013.04 Changed DistInt. Return array indices now match input
-- Better Min, Max error handling in Uniform, FavorBig, FavorSmall, Normal, Poisson
-- 5/2013 - Removed extra variable declaration in functions RandInt and RandReal
-- 5/2013 2013.05 Big vector randomization added overloading RandUnsigned, RandSlv, and RandSigned
-- Added NULL_RANGE_TYPE to minimize null range warnings
-- 1/2014 2014.01 Added RandTime, RandReal(set), RandIntV, RandRealV, RandTimeV
-- Made sort, revsort from SortListPkg_int visible via aliases
-- 1/2015 2015.01 Changed Assert/Report to Alert
-- 5/2015 2015.06 Revised Alerts to Alert(OSVVM_ALERTLOG_ID, ...) ;
-- 11/2016 2016.11 No changes. Updated release numbers to make documentation and
-- package have consistent release identifiers.
--
-- Copyright (c) 2006 - 2016 by SynthWorks Design Inc. All rights reserved.
--
-- Verbatim copies of this source file may be used and
-- distributed without restriction.
--
-- This source file is free software ; you can redistribute it
-- and/or modify it under the terms of the ARTISTIC License
-- as published by The Perl Foundation ; either version 2.0 of
-- the License, or (at your option) any later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY ; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the Artistic License for details.
--
-- You should have received a copy of the license with this source.
-- If not download it from,
-- http ://www.perlfoundation.org/artistic_license_2_0
--
use work.OsvvmGlobalPkg.all ;
use work.AlertLogPkg.all ;
use work.RandomBasePkg.all ;
use work.SortListPkg_int.all ;
use std.textio.all ;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use ieee.numeric_std_unsigned.all ;
use ieee.math_real.all ;
-- comment out following 3 lines with VHDL-2008. Leave in for VHDL-2002
-- library ieee_proposed ; -- remove with VHDL-2008
-- use ieee_proposed.standard_additions.all ; -- remove with VHDL-2008
-- use ieee_proposed.standard_textio_additions.all ; -- remove with VHDL-2008
package RandomPkg is
-- Uncomment the following with VHDL-2008 package generics.
-- For now they are defined in the package RandomBasePkg.vhd
-- package RandomGenericPkg is
-- generic (
-- type RandomSeedType ; -- base type for randomization
-- procedure Uniform (Result : out real ; Seed : inout RandomSeedType) ;
-- function GenRandSeed(IV : integer_vector) return RandomSeedType ;
-- function GenRandSeed(I : integer) return RandomSeedType ;
-- function GenRandSeed(S : string) return RandomSeedType ;
-- ) ;
-- make things from SortListPkg_int visible
alias sort is work.SortListPkg_int.sort[integer_vector return integer_vector] ;
alias revsort is work.SortListPkg_int.revsort[integer_vector return integer_vector] ;
-- note NULL_RANGE_TYPE should probably be in std.standard
subtype NULL_RANGE_TYPE is integer range 0 downto 1 ;
constant NULL_INTV : integer_vector (NULL_RANGE_TYPE) := (others => 0) ;
-- Supports DistValInt functionality
type DistRecType is record
Value : integer ;
Weight : integer ;
end record ;
type DistType is array (natural range <>) of DistRecType ;
-- Parameters for randomization
-- RandomDistType specifies the distribution to use for randomize
type RandomDistType is (NONE, UNIFORM, FAVOR_SMALL, FAVOR_BIG, NORMAL, POISSON) ;
type RandomParmType is record
Distribution : RandomDistType ;
Mean : Real ; -- also used as probability of success
StdDeviation : Real ; -- also used as number of trials for binomial
end record ;
-- RandomParm IO
function to_string(A : RandomDistType) return string ;
procedure write(variable L : inout line ; A : RandomDistType ) ;
procedure read(variable L : inout line ; A : out RandomDistType ; good : out boolean ) ;
procedure read(variable L : inout line ; A : out RandomDistType ) ;
function to_string(A : RandomParmType) return string ;
procedure write(variable L : inout line ; A : RandomParmType ) ;
procedure read(variable L : inout line ; A : out RandomParmType ; good : out boolean ) ;
procedure read(variable L : inout line ; A : out RandomParmType ) ;
type RandomPType is protected
-- Seed Manipulation
-- Known ambiguity between InitSeed with string and integer_vector
-- Recommendation, use : RV.InitSeed(RV'instance_path) ;
-- For integer_vector use either : RV.InitSeed(IV => (1,5)) ;
-- or : RV.InitSeed(integer_vector'(1,5)) ;
procedure InitSeed (S : string ) ;
procedure InitSeed (I : integer ) ;
procedure InitSeed (IV : integer_vector ) ;
-- SetSeed & GetSeed : Used to save and restore seed values
procedure SetSeed (RandomSeedIn : RandomSeedType ) ;
impure function GetSeed return RandomSeedType ;
-- SeedRandom = SetSeed & GetSeed for SV compatibility
-- replace with aliases when they work in popular simulators
procedure SeedRandom (RandomSeedIn : RandomSeedType ) ;
impure function SeedRandom return RandomSeedType ;
-- alias SeedRandom is SetSeed [RandomSeedType] ;
-- alias SeedRandom is GetSeed [return RandomSeedType] ;
-- Setting Randomization Parameters
-- Allows RandInt to have distributions other than uniform
procedure SetRandomParm (RandomParmIn : RandomParmType) ;
procedure SetRandomParm (
Distribution : RandomDistType ;
Mean : Real := 0.0 ;
Deviation : Real := 0.0
) ;
impure function GetRandomParm return RandomParmType ;
impure function GetRandomParm return RandomDistType ;
-- For compatibility with previous version - replace with alias
procedure SetRandomMode (RandomDistIn : RandomDistType) ;
-- alias SetRandomMode is SetRandomParm [RandomDistType, Real, Real] ;
-- Base Randomization Distributions
-- Uniform : Generate a random number with a Uniform distribution
impure function Uniform (Min, Max : in real) return real ;
impure function Uniform (Min, Max : integer) return integer ;
impure function Uniform (Min, Max : integer ; Exclude : integer_vector) return integer ;
-- FavorSmall
-- Generate random numbers with a greater number of small
-- values than large values
impure function FavorSmall (Min, Max : real) return real ;
impure function FavorSmall (Min, Max : integer) return integer ;
impure function FavorSmall (Min, Max : integer ; Exclude : integer_vector) return integer ;
-- FavorBig
-- Generate random numbers with a greater number of large
-- values than small values
impure function FavorBig (Min, Max : real) return real ;
impure function FavorBig (Min, Max : integer) return integer ;
impure function FavorBig (Min, Max : integer ; Exclude : integer_vector) return integer ;
-- Normal : Generate a random number with a normal distribution
impure function Normal (Mean, StdDeviation : real) return real ;
-- Normal + RandomVal >= Min and RandomVal < Max
impure function Normal (Mean, StdDeviation, Min, Max : real) return real ;
impure function Normal (
Mean : real ;
StdDeviation : real ;
Min : integer ;
Max : integer ;
Exclude : integer_vector := NULL_INTV
) return integer ;
-- Poisson : Generate a random number with a poisson distribution
-- Discrete distribution = only generates integral values
impure function Poisson (Mean : real) return real ;
-- Poisson + RandomVal >= Min and RandomVal < Max
impure function Poisson (Mean, Min, Max : real) return real ;
impure function Poisson (
Mean : real ;
Min : integer ;
Max : integer ;
Exclude : integer_vector := NULL_INTV
) return integer ;
-- randomization with a range
impure function RandInt (Min, Max : integer) return integer ;
impure function RandReal(Min, Max : Real) return real ;
impure function RandTime (Min, Max : time ; Unit : time := ns) return time ;
impure function RandSlv (Min, Max, Size : natural) return std_logic_vector ;
impure function RandUnsigned (Min, Max, Size : natural) return Unsigned ;
impure function RandSigned (Min, Max : integer ; Size : natural ) return Signed ;
impure function RandIntV (Min, Max : integer ; Size : natural) return integer_vector ;
impure function RandIntV (Min, Max : integer ; Unique : natural ; Size : natural) return integer_vector ;
impure function RandRealV (Min, Max : real ; Size : natural) return real_vector ;
impure function RandTimeV (Min, Max : time ; Size : natural ; Unit : time := ns) return time_vector ;
impure function RandTimeV (Min, Max : time ; Unique : natural ; Size : natural ; Unit : time := ns) return time_vector ;
-- randomization with a range and exclude vector
impure function RandInt (Min, Max : integer ; Exclude : integer_vector ) return integer ;
impure function RandTime (Min, Max : time ; Exclude : time_vector ; Unit : time := ns) return time ;
impure function RandSlv (Min, Max : natural ; Exclude : integer_vector ; Size : natural ) return std_logic_vector ;
impure function RandUnsigned (Min, Max : natural ; Exclude : integer_vector ; Size : natural ) return Unsigned ;
impure function RandSigned (Min, Max : integer ; Exclude : integer_vector ; Size : natural ) return Signed ;
impure function RandIntV (Min, Max : integer ; Exclude : integer_vector ; Size : natural) return integer_vector ;
impure function RandIntV (Min, Max : integer ; Exclude : integer_vector ; Unique : natural ; Size : natural) return integer_vector ;
impure function RandTimeV (Min, Max : time ; Exclude : time_vector ; Size : natural ; Unit : in time := ns) return time_vector ;
impure function RandTimeV (Min, Max : time ; Exclude : time_vector ; Unique : natural ; Size : natural ; Unit : in time := ns) return time_vector ;
-- Randomly select a value within a set of values
impure function RandInt ( A : integer_vector ) return integer ;
impure function RandReal ( A : real_vector ) return real ;
impure function RandTime (A : time_vector) return time ;
impure function RandSlv (A : integer_vector ; Size : natural) return std_logic_vector ;
impure function RandUnsigned (A : integer_vector ; Size : natural) return Unsigned ;
impure function RandSigned (A : integer_vector ; Size : natural ) return Signed ;
impure function RandIntV (A : integer_vector ; Size : natural) return integer_vector ;
impure function RandIntV (A : integer_vector ; Unique : natural ; Size : natural) return integer_vector ;
impure function RandRealV (A : real_vector ; Size : natural) return real_vector ;
impure function RandRealV (A : real_vector ; Unique : natural ; Size : natural) return real_vector ;
impure function RandTimeV (A : time_vector ; Size : natural) return time_vector ;
impure function RandTimeV (A : time_vector ; Unique : natural ; Size : natural) return time_vector ;
-- Randomly select a value within a set of values with exclude values (so can skip last or last n)
impure function RandInt ( A, Exclude : integer_vector ) return integer ;
impure function RandReal ( A, Exclude : real_vector ) return real ;
impure function RandTime (A, Exclude : time_vector) return time ;
impure function RandSlv (A, Exclude : integer_vector ; Size : natural) return std_logic_vector ;
impure function RandUnsigned (A, Exclude : integer_vector ; Size : natural) return Unsigned ;
impure function RandSigned (A, Exclude : integer_vector ; Size : natural ) return Signed ;
impure function RandIntV (A, Exclude : integer_vector ; Size : natural) return integer_vector ;
impure function RandIntV (A, Exclude : integer_vector ; Unique : natural ; Size : natural) return integer_vector ;
impure function RandRealV (A, Exclude : real_vector ; Size : natural) return real_vector ;
impure function RandRealV (A, Exclude : real_vector ; Unique : natural ; Size : natural) return real_vector ;
impure function RandTimeV (A, Exclude : time_vector ; Size : natural) return time_vector ;
impure function RandTimeV (A, Exclude : time_vector ; Unique : natural ; Size : natural) return time_vector ;
-- Randomly select between 0 and N-1 based on the specified weight.
-- where N = number values in weight array
impure function DistInt ( Weight : integer_vector ) return integer ;
impure function DistSlv ( Weight : integer_vector ; Size : natural ) return std_logic_vector ;
impure function DistUnsigned ( Weight : integer_vector ; Size : natural ) return unsigned ;
impure function DistSigned ( Weight : integer_vector ; Size : natural ) return signed ;
-- Distribution with just weights and with exclude values
impure function DistInt ( Weight : integer_vector ; Exclude : integer_vector ) return integer ;
impure function DistSlv ( Weight : integer_vector ; Exclude : integer_vector ; Size : natural ) return std_logic_vector ;
impure function DistUnsigned ( Weight : integer_vector ; Exclude : integer_vector ; Size : natural ) return unsigned ;
impure function DistSigned ( Weight : integer_vector ; Exclude : integer_vector ; Size : natural ) return signed ;
-- Distribution with weight and value
impure function DistValInt ( A : DistType ) return integer ;
impure function DistValSlv ( A : DistType ; Size : natural) return std_logic_vector ;
impure function DistValUnsigned ( A : DistType ; Size : natural) return unsigned ;
impure function DistValSigned ( A : DistType ; Size : natural) return signed ;
-- Distribution with weight and value and with exclude values
impure function DistValInt ( A : DistType ; Exclude : integer_vector ) return integer ;
impure function DistValSlv ( A : DistType ; Exclude : integer_vector ; Size : natural) return std_logic_vector ;
impure function DistValUnsigned ( A : DistType ; Exclude : integer_vector ; Size : natural) return unsigned ;
impure function DistValSigned ( A : DistType ; Exclude : integer_vector ; Size : natural) return signed ;
-- Large vector handling.
impure function RandUnsigned (Size : natural) return unsigned ;
impure function RandSlv (Size : natural) return std_logic_vector ;
impure function RandSigned (Size : natural) return signed ;
impure function RandUnsigned (Max : Unsigned) return unsigned ;
impure function RandSlv (Max : std_logic_vector) return std_logic_vector ;
impure function RandSigned (Max : signed) return signed ;
impure function RandUnsigned (Min, Max : unsigned) return unsigned ;
impure function RandSlv (Min, Max : std_logic_vector) return std_logic_vector ;
impure function RandSigned (Min, Max : signed) return signed ;
-- Convenience Functions
impure function RandReal return real ; -- 0.0 to 1.0
impure function RandReal(Max : Real) return real ; -- 0.0 to Max
impure function RandInt (Max : integer) return integer ;
impure function RandSlv (Max, Size : natural) return std_logic_vector ;
impure function RandUnsigned (Max, Size : natural) return Unsigned ;
impure function RandSigned (Max : integer ; Size : natural ) return Signed ;
end protected RandomPType ;
end RandomPkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body RandomPkg is
-----------------------------------------------------------------
-- Local Randomization Support
-----------------------------------------------------------------
constant NULL_SLV : std_logic_vector (NULL_RANGE_TYPE) := (others => '0') ;
constant NULL_UV : unsigned (NULL_RANGE_TYPE) := (others => '0') ;
constant NULL_SV : signed (NULL_RANGE_TYPE) := (others => '0') ;
-----------------------------------------------------------------
-- Scale -- Scale a value to be within a given range
--
function Scale (A, Min, Max : real) return real is
variable ValRange : Real ;
begin
if Max >= Min then
ValRange := Max - Min ;
return A * ValRange + Min ;
else
return real'left ;
end if ;
end function Scale ;
function Scale (A : real ; Min, Max : integer) return integer is
variable ValRange : real ;
variable rMin, rMax : real ;
begin
if Max >= Min then
rMin := real(Min) - 0.5 ;
rMax := real(Max) + 0.5 ;
ValRange := rMax - rMin ;
return integer(round(A * ValRange + rMin)) ;
else
return integer'left ;
end if ;
end function Scale ;
-- create more smaller values
function FavorSmall (A : real) return real is
begin
return 1.0 - sqrt(A) ;
end FavorSmall ;
-- create more larger values
-- alias FavorBig is sqrt[real return real] ;
function FavorBig (A : real) return real is
begin
return sqrt(A) ;
end FavorBig ;
-- local.
function to_time_vector (A : integer_vector ; Unit : time) return time_vector is
variable result : time_vector(A'range) ;
begin
for i in A'range loop
result(i) := A(i) * Unit ;
end loop ;
return result ;
end function to_time_vector ;
-- local
function to_integer_vector (A : time_vector ; Unit : time) return integer_vector is
variable result : integer_vector(A'range) ;
begin
for i in A'range loop
result(i) := A(i) / Unit ;
end loop ;
return result ;
end function to_integer_vector ;
-- Local. Remove the exclude list from the list - integer_vector
procedure RemoveExclude(A, Exclude : integer_vector ; variable NewA : out integer_vector ; variable NewALength : inout natural ) is
alias norm_NewA : integer_vector(1 to NewA'length) is NewA ;
begin
NewALength := 0 ;
for i in A'range loop
if not inside(A(i), Exclude) then
NewALength := NewALength + 1 ;
norm_NewA(NewALength) := A(i) ;
end if ;
end loop ;
end procedure RemoveExclude ;
-- Local. Inside - real_vector
function inside(A : real ; Exclude : real_vector) return boolean is
begin
for i in Exclude'range loop
if A = Exclude(i) then
return TRUE ;
end if ;
end loop ;
return FALSE ;
end function inside ;
-- Local. Remove the exclude list from the list - real_vector
procedure RemoveExclude(A, Exclude : real_vector ; variable NewA : out real_vector ; variable NewALength : inout natural ) is
alias norm_NewA : real_vector(1 to NewA'length) is NewA ;
begin
NewALength := 0 ;
for i in A'range loop
if not inside(A(i), Exclude) then
NewALength := NewALength + 1 ;
norm_NewA(NewALength) := A(i) ;
end if ;
end loop ;
end procedure RemoveExclude ;
-- Local. Inside - time_vector
function inside(A : time ; Exclude : time_vector) return boolean is
begin
for i in Exclude'range loop
if A = Exclude(i) then
return TRUE ;
end if ;
end loop ;
return FALSE ;
end function inside ;
-- Local. Remove the exclude list from the list - time_vector
procedure RemoveExclude(A, Exclude : time_vector ; variable NewA : out time_vector ; variable NewALength : inout natural ) is
alias norm_NewA : time_vector(1 to NewA'length) is NewA ;
begin
NewALength := 0 ;
for i in A'range loop
if not inside(A(i), Exclude) then
NewALength := NewALength + 1 ;
norm_NewA(NewALength) := A(i) ;
end if ;
end loop ;
end procedure RemoveExclude ;
-----------------------------------------------------------------
-- RandomParmType IO
-----------------------------------------------------------------
-----------------------------------------------------------------
function to_string(A : RandomDistType) return string is
begin
return RandomDistType'image(A) ;
end function to_string ;
-----------------------------------------------------------------
procedure write(variable L : inout line ; A : RandomDistType ) is
begin
write(L, to_string(A)) ;
end procedure write ;
-----------------------------------------------------------------
procedure read(variable L : inout line ; A : out RandomDistType ; good : out boolean ) is
variable strval : string(1 to 40) ;
variable len : natural ;
begin
-- procedure SREAD (L : inout LINE ; VALUE : out STRING ; STRLEN : out NATURAL) ;
sread(L, strval, len) ;
A := RandomDistType'value(strval(1 to len)) ;
good := len > 0 ;
end procedure read ;
-----------------------------------------------------------------
procedure read(variable L : inout line ; A : out RandomDistType ) is
variable ReadValid : boolean ;
begin
read(L, A, ReadValid) ;
AlertIfNot( OSVVM_ALERTLOG_ID, ReadValid, "RandomPkg.read[line, RandomDistType] failed", FAILURE) ;
end procedure read ;
-----------------------------------------------------------------
function to_string(A : RandomParmType) return string is
begin
return RandomDistType'image(A.Distribution) & " " &
to_string(A.Mean, 2) & " " & to_string(A.StdDeviation, 2) ;
end function to_string ;
-----------------------------------------------------------------
procedure write(variable L : inout line ; A : RandomParmType ) is
begin
write(L, to_string(A)) ;
end procedure write ;
-----------------------------------------------------------------
procedure read(variable L : inout line ; A : out RandomParmType ; good : out boolean ) is
variable strval : string(1 to 40) ;
variable len : natural ;
variable igood : boolean ;
begin
loop
-- procedure SREAD (L : inout LINE ; VALUE : out STRING ; STRLEN : out NATURAL) ;
sread(L, strval, len) ;
A.Distribution := RandomDistType'value(strval(1 to len)) ;
igood := len > 0 ;
exit when not igood ;
read(L, A.Mean, igood) ;
exit when not igood ;
read(L, A.StdDeviation, igood) ;
exit ;
end loop ;
good := igood ;
end procedure read ;
-----------------------------------------------------------------
procedure read(variable L : inout line ; A : out RandomParmType ) is
variable ReadValid : boolean ;
begin
read(L, A, ReadValid) ;
AlertIfNot( OSVVM_ALERTLOG_ID, ReadValid, "RandomPkg.read[line, RandomParmType] failed", FAILURE) ;
end procedure read ;
-----------------------------------------------------------------
-----------------------------------------------------------------
type RandomPType is protected body
--
-- RandomSeed manipulation
--
variable RandomSeed : RandomSeedType := GenRandSeed(integer_vector'(1,7)) ;
procedure InitSeed (S : string ) is
begin
RandomSeed := GenRandSeed(S) ;
end procedure InitSeed ;
procedure InitSeed (I : integer ) is
begin
RandomSeed := GenRandSeed(I) ;
end procedure InitSeed ;
procedure InitSeed (IV : integer_vector ) is
begin
RandomSeed := GenRandSeed(IV) ;
end procedure InitSeed ;
procedure SetSeed (RandomSeedIn : RandomSeedType ) is
begin
RandomSeed := RandomSeedIn ;
end procedure SetSeed ;
procedure SeedRandom (RandomSeedIn : RandomSeedType ) is
begin
RandomSeed := RandomSeedIn ;
end procedure SeedRandom ;
impure function GetSeed return RandomSeedType is
begin
return RandomSeed ;
end function GetSeed ;
impure function SeedRandom return RandomSeedType is
begin
return RandomSeed ;
end function SeedRandom ;
--
-- randomization mode
--
variable RandomParm : RandomParmType ; -- left most values ok for init
procedure SetRandomParm (RandomParmIn : RandomParmType) is
begin
RandomParm := RandomParmIn ;
end procedure SetRandomParm ;
procedure SetRandomParm (
Distribution : RandomDistType ;
Mean : Real := 0.0 ;
Deviation : Real := 0.0
) is
begin
RandomParm := RandomParmType'(Distribution, Mean, Deviation) ;
end procedure SetRandomParm ;
impure function GetRandomParm return RandomParmType is
begin
return RandomParm ;
end function GetRandomParm ;
impure function GetRandomParm return RandomDistType is
begin
return RandomParm.Distribution ;
end function GetRandomParm ;
-- For compatibility with previous version
procedure SetRandomMode (RandomDistIn : RandomDistType) is
begin
SetRandomParm(RandomDistIn) ;
end procedure SetRandomMode ;
--
-- Base Randomization Distributions
--
--
-- Uniform : Generate a random number with a Uniform distribution
--
impure function Uniform (Min, Max : in real) return real is
variable rRandomVal : real ;
begin
AlertIf (OSVVM_ALERTLOG_ID, Max < Min, "RandomPkg.Uniform: Max < Min", FAILURE) ;
Uniform(rRandomVal, RandomSeed) ;
return scale(rRandomVal, Min, Max) ;
end function Uniform ;
impure function Uniform (Min, Max : integer) return integer is
variable rRandomVal : real ;
begin
AlertIf (OSVVM_ALERTLOG_ID, Max < Min, "RandomPkg.Uniform: Max < Min", FAILURE) ;
Uniform(rRandomVal, RandomSeed) ;
return scale(rRandomVal, Min, Max) ;
end function Uniform ;
impure function Uniform (Min, Max : integer ; Exclude : integer_vector) return integer is
variable iRandomVal : integer ;
variable ExcludeList : SortListPType ;
variable count : integer ;
begin
ExcludeList.add(Exclude, Min, Max) ;
count := ExcludeList.count ;
iRandomVal := Uniform(Min, Max - count) ;
-- adjust count, note iRandomVal changes while checking.
for i in 1 to count loop
exit when iRandomVal < ExcludeList.Get(i) ;
iRandomVal := iRandomVal + 1 ;
end loop ;
ExcludeList.erase ;
return iRandomVal ;
end function Uniform ;
--
-- FavorSmall
-- Generate random numbers with a greater number of small
-- values than large values
--
impure function FavorSmall (Min, Max : real) return real is
variable rRandomVal : real ;
begin
AlertIf (OSVVM_ALERTLOG_ID, Max < Min, "RandomPkg.FavorSmall: Max < Min", FAILURE) ;
Uniform(rRandomVal, RandomSeed) ;
return scale(FavorSmall(rRandomVal), Min, Max) ; -- real
end function FavorSmall ;
impure function FavorSmall (Min, Max : integer) return integer is
variable rRandomVal : real ;
begin
AlertIf (OSVVM_ALERTLOG_ID, Max < Min, "RandomPkg.FavorSmall: Max < Min", FAILURE) ;
Uniform(rRandomVal, RandomSeed) ;
return scale(FavorSmall(rRandomVal), Min, Max) ; -- integer
end function FavorSmall ;
impure function FavorSmall (Min, Max : integer ; Exclude : integer_vector) return integer is
variable iRandomVal : integer ;
variable ExcludeList : SortListPType ;
variable count : integer ;
begin
ExcludeList.add(Exclude, Min, Max) ;
count := ExcludeList.count ;
iRandomVal := FavorSmall(Min, Max - count) ;
-- adjust count, note iRandomVal changes while checking.
for i in 1 to count loop
exit when iRandomVal < ExcludeList.Get(i) ;
iRandomVal := iRandomVal + 1 ;
end loop ;
ExcludeList.erase ;
return iRandomVal ;
end function FavorSmall ;
--
-- FavorBig
-- Generate random numbers with a greater number of large
-- values than small values
--
impure function FavorBig (Min, Max : real) return real is
variable rRandomVal : real ;
begin
AlertIf (OSVVM_ALERTLOG_ID, Max < Min, "RandomPkg.FavorBig: Max < Min", FAILURE) ;
Uniform(rRandomVal, RandomSeed) ;
return scale(FavorBig(rRandomVal), Min, Max) ; -- real
end function FavorBig ;
impure function FavorBig (Min, Max : integer) return integer is
variable rRandomVal : real ;
begin
AlertIf (OSVVM_ALERTLOG_ID, Max < Min, "RandomPkg.FavorBig: Max < Min", FAILURE) ;
Uniform(rRandomVal, RandomSeed) ;
return scale(FavorBig(rRandomVal), Min, Max) ; -- integer
end function FavorBig ;
impure function FavorBig (Min, Max : integer ; Exclude : integer_vector) return integer is
variable iRandomVal : integer ;
variable ExcludeList : SortListPType ;
variable count : integer ;
begin
ExcludeList.add(Exclude, Min, Max) ;
count := ExcludeList.count ;
iRandomVal := FavorBig(Min, Max - count) ;
-- adjust count, note iRandomVal changes while checking.
for i in 1 to count loop
exit when iRandomVal < ExcludeList.Get(i) ;
iRandomVal := iRandomVal + 1 ;
end loop ;
ExcludeList.erase ;
return iRandomVal ;
end function FavorBig ;
-----------------------------------------------------------------
-- Normal
-- Generate a random number with a normal distribution
--
-- Use Box Muller, per Wikipedia :
-- http ://en.wikipedia.org/wiki/Box%E2%80%93Muller_transform
--
-- Use polar method, per Wikipedia :
-- http ://en.wikipedia.org/wiki/Marsaglia_polar_method
--
impure function Normal (Mean, StdDeviation : real) return real is
variable x01, y01 : real ;
variable StdNormalDist : real ; -- mean 0, variance 1
begin
-- add this check to set parameters?
if StdDeviation < 0.0 then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.Normal: Standard deviation must be >= 0.0", FAILURE) ;
return -1.0 ;
end if ;
-- Box Muller
Uniform (x01, RandomSeed) ;
Uniform (y01, RandomSeed) ;
StdNormalDist := sqrt(-2.0 * log(x01)) * cos(math_2_pi*y01) ;
-- Polar form rejected due to mean 50.0, std deviation = 5 resulted
-- in a median of 49
-- -- find two Uniform distributed values with range -1 to 1
-- -- that satisify S = X **2 + Y**2 < 1.0
-- loop
-- Uniform (x01, RandomSeed) ;
-- Uniform (y01, RandomSeed) ;
-- x := 2.0 * x01 - 1.0 ; -- scale to -1 to 1
-- y := 2.0 * y01 - 1.0 ;
-- s := x*x + y*y ;
-- exit when s < 1.0 and s > 0.0 ;
-- end loop ;
-- -- Calculate Standard Normal Distribution
-- StdNormalDist := x * sqrt((-2.0 * log(s)) / s) ;
-- Convert to have Mean and StdDeviation
return StdDeviation * StdNormalDist + Mean ;
end function Normal ;
-- Normal + RandomVal >= Min and RandomVal <= Max
impure function Normal (Mean, StdDeviation, Min, Max : real) return real is
variable rRandomVal : real ;
begin
if Max < Min then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.Normal: Max < Min", FAILURE) ;
return Mean ;
else
loop
rRandomVal := Normal (Mean, StdDeviation) ;
exit when rRandomVal >= Min and rRandomVal <= Max ;
end loop ;
end if ;
return rRandomVal ;
end function Normal ;
-- Normal + RandomVal >= Min and RandomVal <= Max
impure function Normal (
Mean : real ;
StdDeviation : real ;
Min : integer ;
Max : integer ;
Exclude : integer_vector := NULL_INTV
) return integer is
variable iRandomVal : integer ;
begin
if Max < Min then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.Normal: Max < Min", FAILURE) ;
return integer(round(Mean)) ;
else
loop
iRandomVal := integer(round( Normal(Mean, StdDeviation) )) ;
exit when iRandomVal >= Min and iRandomVal <= Max and
not inside(iRandomVal, Exclude) ;
end loop ;
end if ;
return iRandomVal ;
end function Normal ;
-----------------------------------------------------------------
-- Poisson
-- Generate a random number with a poisson distribution
-- Discrete distribution = only generates integral values
--
-- Use knuth method, per Wikipedia :
-- http ://en.wikipedia.org/wiki/Poisson_distribution
--
impure function Poisson (Mean : real) return real is
variable Product : Real := 1.0 ;
variable Bound : Real := 0.0 ;
variable UniformRand : Real := 0.0 ;
variable PoissonRand : Real := 0.0 ;
begin
Bound := exp(-1.0 * Mean) ;
Product := 1.0 ;
-- add this check to set parameters?
if Mean <= 0.0 or Bound <= 0.0 then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.Poisson: Mean < 0 or too large. Mean = " & real'image(Mean), FAILURE) ;
return Mean ;
end if ;
while (Product >= Bound) loop
PoissonRand := PoissonRand + 1.0 ;
Uniform(UniformRand, RandomSeed) ;
Product := Product * UniformRand ;
end loop ;
return PoissonRand ;
end function Poisson ; -- no range
-- Poisson + RandomVal >= Min and RandomVal < Max
impure function Poisson (Mean, Min, Max : real) return real is
variable rRandomVal : real ;
begin
if Max < Min then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.Poisson: Max < Min", FAILURE) ;
return Mean ;
else
loop
rRandomVal := Poisson (Mean) ;
exit when rRandomVal >= Min and rRandomVal <= Max ;
end loop ;
end if ;
return rRandomVal ;
end function Poisson ;
impure function Poisson (
Mean : real ;
Min : integer ;
Max : integer ;
Exclude : integer_vector := NULL_INTV
) return integer is
variable iRandomVal : integer ;
begin
if Max < Min then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.Poisson: Max < Min", FAILURE) ;
return integer(round(Mean)) ;
else
loop
iRandomVal := integer(round( Poisson (Mean) )) ;
exit when iRandomVal >= Min and iRandomVal <= Max and
not inside(iRandomVal, Exclude) ;
end loop ;
end if ;
return iRandomVal ;
end function Poisson ;
--
-- integer randomization with a range
-- Distribution determined by RandomParm
--
impure function RandInt (Min, Max : integer) return integer is
begin
case RandomParm.Distribution is
when NONE | UNIFORM => return Uniform(Min, Max) ;
when FAVOR_SMALL => return FavorSmall(Min, Max) ;
when FAVOR_BIG => return FavorBig (Min, Max) ;
when NORMAL => return Normal(RandomParm.Mean, RandomParm.StdDeviation, Min, Max) ;
when POISSON => return Poisson(RandomParm.Mean, Min, Max) ;
when others =>
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandInt: RandomParm.Distribution not implemented", FAILURE) ;
return integer'low ;
end case ;
end function RandInt ;
--
-- real randomization with a range
-- Distribution determined by RandomParm
--
impure function RandReal(Min, Max : Real) return real is
begin
case RandomParm.Distribution is
when NONE | UNIFORM => return Uniform(Min, Max) ;
when FAVOR_SMALL => return FavorSmall(Min, Max) ;
when FAVOR_BIG => return FavorBig (Min, Max) ;
when NORMAL => return Normal(RandomParm.Mean, RandomParm.StdDeviation, Min, Max) ;
when POISSON => return Poisson(RandomParm.Mean, Min, Max) ;
when others =>
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandReal: Specified RandomParm.Distribution not implemented", FAILURE) ;
return real(integer'low) ;
end case ;
end function RandReal ;
impure function RandTime (Min, Max : time ; Unit :time := ns) return time is
variable IntVal : integer ;
begin
-- if Max - Min > 2**31 result will be out of range
IntVal := RandInt(0, (Max - Min)/Unit) ;
Return Min + Unit*IntVal ;
end function RandTime ;
impure function RandSlv (Min, Max, Size : natural) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(RandInt(Min, Max), Size)) ;
end function RandSlv ;
impure function RandUnsigned (Min, Max, Size : natural) return Unsigned is
begin
return to_unsigned(RandInt(Min, Max), Size) ;
end function RandUnsigned ;
impure function RandSigned (Min, Max : integer ; Size : natural ) return Signed is
begin
return to_signed(RandInt(Min, Max), Size) ;
end function RandSigned ;
impure function RandIntV (Min, Max : integer ; Size : natural) return integer_vector is
variable result : integer_vector(1 to Size) ;
begin
for i in result'range loop
result(i) := RandInt(Min, Max) ;
end loop ;
return result ;
end function RandIntV ;
impure function RandIntV (Min, Max : integer ; Unique : natural ; Size : natural) return integer_vector is
variable result : integer_vector(1 to Size) ;
variable iUnique : natural ;
begin
-- if Unique = 0, it is more efficient to call RandIntV(Min, Max, Size)
iUnique := Unique ;
if Max-Min+1 < Unique then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.(RandIntV | RandRealV | RandTimeV): Unique > number of values available", FAILURE) ;
iUnique := Max-Min+1 ;
end if ;
for i in result'range loop
result(i) := RandInt(Min, Max, result(maximum(1, 1 + i - iUnique) to Size)) ;
end loop ;
return result ;
end function RandIntV ;
impure function RandRealV (Min, Max : real ; Size : natural) return real_vector is
variable result : real_vector(1 to Size) ;
begin
for i in result'range loop
result(i) := RandReal(Min, Max) ;
end loop ;
return result ;
end function RandRealV ;
impure function RandTimeV (Min, Max : time ; Size : natural ; Unit : time := ns) return time_vector is
variable result : time_vector(1 to Size) ;
begin
for i in result'range loop
result(i) := RandTime(Min, Max, Unit) ;
end loop ;
return result ;
end function RandTimeV ;
impure function RandTimeV (Min, Max : time ; Unique : natural ; Size : natural ; Unit : time := ns) return time_vector is
begin
-- if Unique = 0, it is more efficient to call RandTimeV(Min, Max, Size)
return to_time_vector(RandIntV(Min/Unit, Max/Unit, Unique, Size), Unit) ;
end function RandTimeV ;
--
-- integer randomization with a range and exclude vector
-- Distribution determined by RandomParm
--
impure function RandInt (Min, Max : integer ; Exclude : integer_vector ) return integer is
begin
case RandomParm.Distribution is
when NONE | UNIFORM => return Uniform(Min, Max, Exclude) ;
when FAVOR_SMALL => return FavorSmall(Min, Max, Exclude) ;
when FAVOR_BIG => return FavorBig (Min, Max, Exclude) ;
when NORMAL => return Normal(RandomParm.Mean, RandomParm.StdDeviation, Min, Max, Exclude) ;
when POISSON => return Poisson(RandomParm.Mean, Min, Max, Exclude) ;
when others =>
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandInt: Specified RandomParm.Distribution not implemented", FAILURE) ;
return integer'low ;
end case ;
end function RandInt ;
impure function RandTime (Min, Max : time ; Exclude : time_vector ; Unit : time := ns) return time is
variable IntVal : integer ;
begin
-- if Min or Max > 2**31 value will be out of range
return RandInt(Min/Unit, Max/Unit, to_integer_vector(Exclude, Unit)) * Unit ;
end function RandTime ;
impure function RandSlv (Min, Max : natural ; Exclude : integer_vector ; Size : natural ) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(RandInt(Min, Max, Exclude), Size)) ;
end function RandSlv ;
impure function RandUnsigned (Min, Max : natural ; Exclude : integer_vector ; Size : natural ) return Unsigned is
begin
return to_unsigned(RandInt(Min, Max, Exclude), Size) ;
end function RandUnsigned ;
impure function RandSigned (Min, Max : integer ; Exclude : integer_vector ; Size : natural ) return Signed is
begin
return to_signed(RandInt(Min, Max, Exclude), Size) ;
end function RandSigned ;
impure function RandIntV (Min, Max : integer ; Exclude : integer_vector ; Size : natural) return integer_vector is
variable result : integer_vector(1 to Size) ;
begin
for i in result'range loop
result(i) := RandInt(Min, Max, Exclude) ;
end loop ;
return result ;
end function RandIntV ;
impure function RandIntV (Min, Max : integer ; Exclude : integer_vector ; Unique : natural ; Size : natural) return integer_vector is
variable ResultPlus : integer_vector(1 to Size + Exclude'length) ;
begin
-- if Unique = 0, it is more efficient to call RandIntV(Min, Max, Size)
ResultPlus(Size+1 to ResultPlus'right) := Exclude ;
for i in 1 to Size loop
ResultPlus(i) := RandInt(Min, Max, ResultPlus(maximum(1, 1 + i - Unique) to ResultPlus'right)) ;
end loop ;
return ResultPlus(1 to Size) ;
end function RandIntV ;
impure function RandTimeV (Min, Max : time ; Exclude : time_vector ; Size : natural ; Unit : in time := ns) return time_vector is
begin
return to_time_vector( RandIntV(Min/Unit, Max/Unit, to_integer_vector(Exclude, Unit), Size), Unit ) ;
end function RandTimeV ;
impure function RandTimeV (Min, Max : time ; Exclude : time_vector ; Unique : natural ; Size : natural ; Unit : in time := ns) return time_vector is
begin
-- if Unique = 0, it is more efficient to call RandIntV(Min, Max, Size)
return to_time_vector( RandIntV(Min/Unit, Max/Unit, to_integer_vector(Exclude, Unit), Unique, Size), Unit ) ;
end function RandTimeV ;
--
-- Randomly select a value within a set of values
-- Distribution determined by RandomParm
--
impure function RandInt ( A : integer_vector ) return integer is
alias A_norm : integer_vector(1 to A'length) is A ;
begin
return A_norm( RandInt(1, A'length) ) ;
end function RandInt ;
impure function RandReal ( A : real_vector ) return real is
alias A_norm : real_vector(1 to A'length) is A ;
begin
return A_norm( RandInt(1, A'length) ) ;
end function RandReal ;
impure function RandTime ( A : time_vector ) return time is
alias A_norm : time_vector(1 to A'length) is A ;
begin
return A_norm( RandInt(1, A'length) ) ;
end function RandTime ;
impure function RandSlv (A : integer_vector ; Size : natural) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(RandInt(A), Size)) ;
end function RandSlv ;
impure function RandUnsigned (A : integer_vector ; Size : natural) return Unsigned is
begin
return to_unsigned(RandInt(A), Size) ;
end function RandUnsigned ;
impure function RandSigned (A : integer_vector ; Size : natural ) return Signed is
begin
return to_signed(RandInt(A), Size) ;
end function RandSigned ;
impure function RandIntV (A : integer_vector ; Size : natural) return integer_vector is
variable result : integer_vector(1 to Size) ;
begin
for i in result'range loop
result(i) := RandInt(A) ;
end loop ;
return result ;
end function RandIntV ;
impure function RandIntV (A : integer_vector ; Unique : natural ; Size : natural) return integer_vector is
variable result : integer_vector(1 to Size) ;
variable iUnique : natural ;
begin
-- if Unique = 0, it is more efficient to call RandIntV(A, Size)
-- require A'length >= Unique
iUnique := Unique ;
if A'length < Unique then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandIntV: Unique > length of set of values", FAILURE) ;
iUnique := A'length ;
end if ;
for i in result'range loop
result(i) := RandInt(A, result(maximum(1, 1 + i - iUnique) to Size)) ;
end loop ;
return result ;
end function RandIntV ;
impure function RandRealV (A : real_vector ; Size : natural) return real_vector is
variable result : real_vector(1 to Size) ;
begin
for i in result'range loop
result(i) := RandReal(A) ;
end loop ;
return result ;
end function RandRealV ;
impure function RandRealV (A : real_vector ; Unique : natural ; Size : natural) return real_vector is
alias A_norm : real_vector(1 to A'length) is A ;
variable result : real_vector(1 to Size) ;
variable IntResult : integer_vector(result'range) ;
begin
-- randomly generate indices
IntResult := RandIntV(1, A'length, Unique, Size) ;
-- translate indicies into result values
for i in result'range loop
result(i) := A_norm(IntResult(i)) ;
end loop ;
return result ;
end function RandRealV ;
impure function RandTimeV (A : time_vector ; Size : natural) return time_vector is
variable result : time_vector(1 to Size) ;
begin
for i in result'range loop
result(i) := RandTime(A) ;
end loop ;
return result ;
end function RandTimeV ;
impure function RandTimeV (A : time_vector ; Unique : natural ; Size : natural) return time_vector is
alias A_norm : time_vector(1 to A'length) is A ;
variable result : time_vector(1 to Size) ;
variable IntResult : integer_vector(result'range) ;
begin
-- randomly generate indices
IntResult := RandIntV(1, A'length, Unique, Size) ;
-- translate indicies into result values
for i in result'range loop
result(i) := A_norm(IntResult(i)) ;
end loop ;
return result ;
end function RandTimeV ;
--
-- Randomly select a value within a set of values with exclude values (so can skip last or last n)
-- Distribution determined by RandomParm
--
impure function RandInt ( A, Exclude : integer_vector ) return integer is
variable NewA : integer_vector(1 to A'length) ;
variable NewALength : natural ;
begin
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Randomize Index
return NewA(RandInt(1, NewALength)) ;
end function RandInt ;
impure function RandReal ( A, Exclude : real_vector ) return real is
variable NewA : real_vector(1 to A'length) ;
variable NewALength : natural ;
begin
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Randomize Index
return NewA(RandInt(1, NewALength)) ;
end function RandReal ;
impure function RandTime ( A, Exclude : time_vector ) return time is
variable NewA : time_vector(1 to A'length) ;
variable NewALength : natural ;
begin
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Randomize Index
return NewA(RandInt(1, NewALength)) ;
end function RandTime ;
impure function RandSlv (A, Exclude : integer_vector ; Size : natural) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(RandInt(A, Exclude), Size)) ;
end function RandSlv ;
impure function RandUnsigned (A, Exclude : integer_vector ; Size : natural) return Unsigned is
begin
return to_unsigned(RandInt(A, Exclude), Size) ;
end function RandUnsigned ;
impure function RandSigned (A, Exclude : integer_vector ; Size : natural ) return Signed is
begin
return to_signed(RandInt(A, Exclude), Size) ;
end function RandSigned ;
impure function RandIntV (A, Exclude : integer_vector ; Size : natural) return integer_vector is
variable result : integer_vector(1 to Size) ;
variable NewA : integer_vector(1 to A'length) ;
variable NewALength : natural ;
begin
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Randomize Index
for i in result'range loop
result(i) := NewA(RandInt(1, NewALength)) ;
end loop ;
return result ;
end function RandIntV ;
impure function RandIntV (A, Exclude : integer_vector ; Unique : natural ; Size : natural) return integer_vector is
variable result : integer_vector(1 to Size) ;
variable NewA : integer_vector(1 to A'length) ;
variable NewALength, iUnique : natural ;
begin
-- if Unique = 0, it is more efficient to call RandIntV(Min, Max, Size)
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Require NewALength >= Unique
iUnique := Unique ;
if NewALength < Unique then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandIntV: Unique > Length of Set A - Exclude", FAILURE) ;
iUnique := NewALength ;
end if ;
-- Randomize using exclude list of Unique # of newly generated values
for i in result'range loop
result(i) := RandInt(NewA(1 to NewALength), result(maximum(1, 1 + i - iUnique) to Size)) ;
end loop ;
return result ;
end function RandIntV ;
impure function RandRealV (A, Exclude : real_vector ; Size : natural) return real_vector is
variable result : real_vector(1 to Size) ;
variable NewA : real_vector(1 to A'length) ;
variable NewALength : natural ;
begin
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Randomize Index
for i in result'range loop
result(i) := NewA(RandInt(1, NewALength)) ;
end loop ;
return result ;
end function RandRealV ;
impure function RandRealV (A, Exclude : real_vector ; Unique : natural ; Size : natural) return real_vector is
variable result : real_vector(1 to Size) ;
variable NewA : real_vector(1 to A'length) ;
variable NewALength, iUnique : natural ;
begin
-- if Unique = 0, it is more efficient to call RandRealV(Min, Max, Size)
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Require NewALength >= Unique
iUnique := Unique ;
if NewALength < Unique then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandRealV: Unique > Length of Set A - Exclude", FAILURE) ;
iUnique := NewALength ;
end if ;
-- Randomize using exclude list of Unique # of newly generated values
for i in result'range loop
result(i) := RandReal(NewA(1 to NewALength), result(maximum(1, 1 + i - iUnique) to Size)) ;
end loop ;
return result ;
end function RandRealV ;
impure function RandTimeV (A, Exclude : time_vector ; Size : natural) return time_vector is
variable result : time_vector(1 to Size) ;
variable NewA : time_vector(1 to A'length) ;
variable NewALength : natural ;
begin
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Randomize Index
for i in result'range loop
result(i) := NewA(RandInt(1, NewALength)) ;
end loop ;
return result ;
end function RandTimeV ;
impure function RandTimeV (A, Exclude : time_vector ; Unique : natural ; Size : natural) return time_vector is
variable result : time_vector(1 to Size) ;
variable NewA : time_vector(1 to A'length) ;
variable NewALength, iUnique : natural ;
begin
-- if Unique = 0, it is more efficient to call RandRealV(Min, Max, Size)
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Require NewALength >= Unique
iUnique := Unique ;
if NewALength < Unique then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandTimeV: Unique > Length of Set A - Exclude", FAILURE) ;
iUnique := NewALength ;
end if ;
-- Randomize using exclude list of Unique # of newly generated values
for i in result'range loop
result(i) := RandTime(NewA(1 to NewALength), result(maximum(1, 1 + i - iUnique) to Size)) ;
end loop ;
return result ;
end function RandTimeV ;
--
-- Basic Discrete Distributions
-- Always uses Uniform
--
impure function DistInt ( Weight : integer_vector ) return integer is
variable DistArray : integer_vector(weight'range) ;
variable sum : integer ;
variable iRandomVal : integer ;
begin
DistArray := Weight ;
sum := 0 ;
for i in DistArray'range loop
DistArray(i) := DistArray(i) + sum ;
if DistArray(i) < sum then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.DistInt: negative weight or sum > 31 bits", FAILURE) ;
return DistArray'low ; -- allows debugging vs integer'left, out of range
end if ;
sum := DistArray(i) ;
end loop ;
if sum >= 1 then
iRandomVal := Uniform(1, sum) ;
for i in DistArray'range loop
if iRandomVal <= DistArray(i) then
return i ;
end if ;
end loop ;
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.DistInt: randomization failed", FAILURE) ;
else
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.DistInt: No randomization weights", FAILURE) ;
end if ;
return DistArray'low ; -- allows debugging vs integer'left, out of range
end function DistInt ;
impure function DistSlv ( Weight : integer_vector ; Size : natural ) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(DistInt(Weight), Size)) ;
end function DistSlv ;
impure function DistUnsigned ( Weight : integer_vector ; Size : natural ) return unsigned is
begin
return to_unsigned(DistInt(Weight), Size) ;
end function DistUnsigned ;
impure function DistSigned ( Weight : integer_vector ; Size : natural ) return signed is
begin
return to_signed(DistInt(Weight), Size) ;
end function DistSigned ;
--
-- Basic Distributions with exclude values (so can skip last or last n)
-- Always uses Uniform via DistInt
--
impure function DistInt ( Weight : integer_vector ; Exclude : integer_vector ) return integer is
variable DistArray : integer_vector(weight'range) ;
variable ExcludeTemp : integer ;
begin
DistArray := Weight ;
for i in Exclude'range loop
ExcludeTemp := Exclude(i) ;
if ExcludeTemp >= DistArray'low and ExcludeTemp <= DistArray'high then
DistArray(ExcludeTemp) := 0 ;
end if ;
end loop ;
return DistInt(DistArray) ;
end function DistInt ;
impure function DistSlv ( Weight : integer_vector ; Exclude : integer_vector ; Size : natural ) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(DistInt(Weight, Exclude), Size)) ;
end function DistSlv ;
impure function DistUnsigned ( Weight : integer_vector ; Exclude : integer_vector ; Size : natural ) return unsigned is
begin
return to_unsigned(DistInt(Weight, Exclude), Size) ;
end function DistUnsigned ;
impure function DistSigned ( Weight : integer_vector ; Exclude : integer_vector ; Size : natural ) return signed is
begin
return to_signed(DistInt(Weight, Exclude), Size) ;
end function DistSigned ;
--
-- Distribution for sparse values
-- Always uses Uniform via DistInt
--
impure function DistValInt ( A : DistType ) return integer is
variable DistArray : integer_vector(0 to A'length -1) ;
alias DistRecArray : DistType(DistArray'range) is A ;
begin
for i in DistArray'range loop
DistArray(i) := DistRecArray(i).Weight ;
end loop ;
return DistRecArray(DistInt(DistArray)).Value ;
end function DistValInt ;
impure function DistValSlv ( A : DistType ; Size : natural ) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(DistValInt(A), Size)) ;
end function DistValSlv ;
impure function DistValUnsigned ( A : DistType ; Size : natural ) return unsigned is
begin
return to_unsigned(DistValInt(A), Size) ;
end function DistValUnsigned ;
impure function DistValSigned ( A : DistType ; Size : natural ) return signed is
begin
return to_signed(DistValInt(A), Size) ;
end function DistValSigned ;
--
-- Distribution for sparse values with exclude values (so can skip last or last n)
-- Always uses Uniform via DistInt
--
impure function DistValInt ( A : DistType ; Exclude : integer_vector ) return integer is
variable DistArray : integer_vector(0 to A'length -1) ;
alias DistRecArray : DistType(DistArray'range) is A ;
begin
for i in DistRecArray'range loop
if inside(DistRecArray(i).Value, exclude) then
DistArray(i) := 0 ; -- exclude
else
DistArray(i) := DistRecArray(i).Weight ;
end if ;
end loop ;
return DistRecArray(DistInt(DistArray)).Value ;
end function DistValInt ;
impure function DistValSlv ( A : DistType ; Exclude : integer_vector ; Size : natural ) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(DistValInt(A, Exclude), Size)) ;
end function DistValSlv ;
impure function DistValUnsigned ( A : DistType ; Exclude : integer_vector ; Size : natural ) return unsigned is
begin
return to_unsigned(DistValInt(A, Exclude), Size) ;
end function DistValUnsigned ;
impure function DistValSigned ( A : DistType ; Exclude : integer_vector ; Size : natural ) return signed is
begin
return to_signed(DistValInt(A, Exclude), Size) ;
end function DistValSigned ;
--
-- Large vector handling.
--
impure function RandUnsigned (Size : natural) return unsigned is
constant NumLoops : integer := integer(ceil(real(Size)/30.0)) ;
constant Remain : integer := (Size - 1) mod 30 + 1 ; -- range 1 to 30
variable RandVal : unsigned(1 to Size) ;
begin
if size = 0 then
return NULL_UV ; -- Null array
end if ;
for i in 0 to NumLoops-2 loop
RandVal(1 + 30*i to 30 + 30*i) := to_unsigned(RandInt(0, 2**30-1), 30) ;
end loop ;
RandVal(1+30*(NumLoops-1) to Remain + 30*(NumLoops-1)) := to_unsigned(RandInt(0, 2**Remain-1), Remain) ;
return RandVal ;
end function RandUnsigned ;
impure function RandSlv (Size : natural) return std_logic_vector is
begin
return std_logic_vector(RandUnsigned(Size)) ;
end function RandSlv ;
impure function RandSigned (Size : natural) return signed is
begin
return signed(RandUnsigned(Size)) ;
end function RandSigned ;
impure function RandUnsigned (Max : unsigned) return unsigned is
alias normMax : unsigned (Max'length downto 1) is Max ;
variable Result : unsigned(Max'range) := (others => '0') ;
alias normResult : unsigned(normMax'range) is Result ;
variable Size : integer ;
begin
-- Size = -1 if not found or Max'length = 0
Size := find_leftmost(normMax, '1') ;
if Size > 0 then
loop
normResult(Size downto 1) := RandUnsigned(Size) ;
exit when normResult <= Max ;
end loop ;
return Result ; -- = normResult with range same as Max
else
return resize("0", Max'length) ;
end if ;
end function RandUnsigned ;
-- Working version that scales the value
-- impure function RandUnsigned (Max : unsigned) return unsigned is
-- constant MaxVal : unsigned(Max'length+3 downto 1) := (others => '1') ;
-- begin
-- if max'length > 0 then
-- -- "Max'length+3" creates 3 guard bits
-- return resize( RandUnsigned(Max'length+3) * ('0'&Max+1) / ('0'&MaxVal+1), Max'length) ;
-- else
-- return NULL_UV ; -- Null Array
-- end if ;
-- end function RandUnsigned ;
impure function RandSlv (Max : std_logic_vector) return std_logic_vector is
begin
return std_logic_vector(RandUnsigned( unsigned(Max))) ;
end function RandSlv ;
impure function RandSigned (Max : signed) return signed is
begin
if max'length > 0 then
AlertIf (OSVVM_ALERTLOG_ID, Max < 0, "RandomPkg.RandSigned: Max < 0", FAILURE) ;
return signed(RandUnsigned( unsigned(Max))) ;
else
return NULL_SV ; -- Null Array
end if ;
end function RandSigned ;
impure function RandUnsigned (Min, Max : unsigned) return unsigned is
constant LEN : integer := maximum(Max'length, Min'length) ;
begin
if LEN > 0 and Min <= Max then
return RandUnsigned(Max-Min) + Min ;
else
if Len > 0 then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandUnsigned: Max < Min", FAILURE) ;
end if ;
return NULL_UV ;
end if ;
end function RandUnsigned ;
impure function RandSlv (Min, Max : std_logic_vector) return std_logic_vector is
constant LEN : integer := maximum(Max'length, Min'length) ;
begin
if LEN > 0 and Min <= Max then
return RandSlv(Max-Min) + Min ;
else
if Len > 0 then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandSlv: Max < Min", FAILURE) ;
end if ;
return NULL_SlV ;
end if ;
end function RandSlv ;
impure function RandSigned (Min, Max : signed) return signed is
constant LEN : integer := maximum(Max'length, Min'length) ;
begin
if LEN > 0 and Min <= Max then
return resize(RandSigned(resize(Max,LEN+1) - resize(Min,LEN+1)) + Min, LEN) ;
else
if Len > 0 then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandSigned: Max < Min", FAILURE) ;
end if ;
return NULL_SV ;
end if ;
end function RandSigned ;
--
-- Convenience Functions. Resolve into calls into the other functions
--
impure function RandReal return real is
begin
return RandReal(0.0, 1.0) ;
end function RandReal ;
impure function RandReal(Max : Real) return real is -- 0.0 to Max
begin
return RandReal(0.0, Max) ;
end function RandReal ;
impure function RandInt (Max : integer) return integer is
begin
return RandInt(0, Max) ;
end function RandInt ;
impure function RandSlv (Max, Size : natural) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(RandInt(0, Max), Size)) ;
end function RandSlv ;
impure function RandUnsigned (Max, Size : natural) return Unsigned is
begin
return to_unsigned(RandInt(0, Max), Size) ;
end function RandUnsigned ;
impure function RandSigned (Max : integer ; Size : natural ) return Signed is
begin
-- chose 0 to Max rather than -Max to +Max to be same as RandUnsigned, either seems logical
return to_signed(RandInt(0, Max), Size) ;
end function RandSigned ;
end protected body RandomPType ;
end RandomPkg ;
|
mit
|
VLSI-EDA/UVVM_All
|
bitvis_vip_scoreboard/src/predefined_sb.vhd
|
1
|
3108
|
--========================================================================================================================
-- Copyright (c) 2018 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
package local_pkg is
function slv_to_string(
constant value : in std_logic_vector
) return string;
end package local_pkg;
package body local_pkg is
function slv_to_string(
constant value : in std_logic_vector
) return string is
begin
return to_string(value, HEX, KEEP_LEADING_0, INCL_RADIX);
end function;
end package body local_pkg;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
use work.generic_sb_pkg;
use work.local_pkg.all;
------------------------------------------------------------------------------------------
-- Package declarations
------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
--
-- slv_sb_pkg
--
-- Predefined scoreboard package for std_logic_vector. Vector length is defined by
-- the constant C_SB_SLV_WIDTH located under scoreboard adaptions in adaptions_pkg.
--
------------------------------------------------------------------------------------------
package slv_sb_pkg is new work.generic_sb_pkg
generic map (t_element => std_logic_vector(C_SB_SLV_WIDTH-1 downto 0),
element_match => std_match,
to_string_element => slv_to_string);
------------------------------------------------------------------------------------------
--
-- int_sb_pkg
--
-- Predefined scoreboard package for integer.
--
------------------------------------------------------------------------------------------
package int_sb_pkg is new work.generic_sb_pkg
generic map (t_element => integer,
element_match => "=",
to_string_element => to_string);
|
mit
|
MForever78/CPUFly
|
ipcore_dir/Video_Memory/simulation/Video_Memory_tb_stim_gen.vhd
|
1
|
14805
|
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Stimulus Generator For Dual Port RAM Configuration
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Video_Memory_tb_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For ROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.Video_Memory_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_DRAM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_DRAM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_DRAM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.Video_Memory_TB_PKG.ALL;
ENTITY Video_Memory_TB_STIM_GEN IS
PORT(
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
A : OUT STD_LOGIC_VECTOR(12-1 downto 0) := (OTHERS => '0');
D : OUT STD_LOGIC_VECTOR(16-1 downto 0) := (OTHERS => '0');
DPRA : OUT STD_LOGIC_VECTOR(12-1 downto 0) := (OTHERS => '0');
WE : OUT STD_LOGIC := '0';
DATA_IN : IN STD_LOGIC_VECTOR (15 DOWNTO 0); --OUTPUT VECTOR
DATA_IN_B : IN STD_LOGIC_VECTOR (15 DOWNTO 0); --OUTPUT VECTOR
CHECK_DATA : OUT STD_LOGIC_VECTOR(1 downto 0) := (OTHERS => '0')
);
END Video_Memory_TB_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF Video_Memory_TB_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A: INTEGER:=1;
CONSTANT DATA_PART_CNT_B: INTEGER:=1;
SIGNAL WRITE_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT_A : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT_B : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ_REG_A : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
SIGNAL DO_READ_REG_B : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
SIGNAL READ_ADDR_INT_A : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT_B : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL D_INT_A : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL D_INT_B : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE_A : STD_LOGIC := '0';
SIGNAL DO_WRITE_B : STD_LOGIC := '0';
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ_A : STD_LOGIC := '0';
SIGNAL DO_READ_B : STD_LOGIC := '0';
SIGNAL COUNT : integer := 0;
SIGNAL COUNT_B : integer := 0;
CONSTANT WRITE_CNT_A : integer := 8;
CONSTANT READ_CNT_A : integer := 8;
CONSTANT WRITE_CNT_B : integer := 8;
CONSTANT READ_CNT_B : integer := 8;
signal porta_wr_rd : std_logic:='0';
signal portb_wr_rd : std_logic:='0';
signal porta_wr_rd_complete: std_logic:='0';
signal portb_wr_rd_complete: std_logic:='0';
signal incr_cnt : std_logic :='0';
signal incr_cnt_b : std_logic :='0';
SIGNAL PORTB_WR_RD_HAPPENED: STD_LOGIC :='0';
SIGNAL LATCH_PORTA_WR_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_L1 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_L2 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_R1 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_R2 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_HAPPENED: STD_LOGIC :='0';
SIGNAL LATCH_PORTB_WR_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_L1 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_L2 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_R1 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_R2 :STD_LOGIC :='0';
BEGIN
WRITE_ADDR_INT_A(11 DOWNTO 0) <= WRITE_ADDR_A(11 DOWNTO 0);
READ_ADDR_INT_A(11 DOWNTO 0) <= READ_ADDR_A(11 DOWNTO 0);
WRITE_ADDR_INT_B(11 DOWNTO 0) <= WRITE_ADDR_B(11 DOWNTO 0);
READ_ADDR_INT_B(11 DOWNTO 0) <= READ_ADDR_B(11 DOWNTO 0);
A <= IF_THEN_ELSE(DO_WRITE_A='1',WRITE_ADDR_INT_A,READ_ADDR_INT_A);
D <= IF_THEN_ELSE(DO_WRITE_A='1',D_INT_A,D_INT_B);
DPRA <= IF_THEN_ELSE(DO_WRITE_B='1',WRITE_ADDR_INT_B,READ_ADDR_INT_B);
CHECK_DATA(0) <= DO_READ_A;
CHECK_DATA(1) <= DO_READ_B;
DO_WRITE <= DO_WRITE_A OR DO_WRITE_B;
RD_GEN_INST_A:ENTITY work.Video_Memory_TB_AGEN
GENERIC MAP(
C_MAX_DEPTH => 2400
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ_A,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR_A
);
WR_AGEN_INST_A:ENTITY work.Video_Memory_TB_AGEN
GENERIC MAP(
C_MAX_DEPTH => 2400 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_WRITE_A,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR_A
);
WR_DGEN_INST_A:ENTITY work.Video_Memory_TB_DGEN
GENERIC MAP (
DATA_GEN_WIDTH => 16,
DOUT_WIDTH => 16,
DATA_PART_CNT => DATA_PART_CNT_A,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => DO_WRITE_A,
DATA_OUT => D_INT_A
);
RD_AGEN_INST_B:ENTITY work.Video_Memory_TB_AGEN
GENERIC MAP(
C_MAX_DEPTH => 2400
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ_B,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR_B
);
WR_AGEN_INST_B:ENTITY work.Video_Memory_TB_AGEN
GENERIC MAP(
C_MAX_DEPTH => 2400 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_WRITE_B,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR_B
);
WR_DGEN_INST_B:ENTITY work.Video_Memory_TB_DGEN
GENERIC MAP (
DATA_GEN_WIDTH => 16,
DOUT_WIDTH => 16,
DATA_PART_CNT => DATA_PART_CNT_B,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => DO_WRITE_B,
DATA_OUT => D_INT_B
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
LATCH_PORTB_WR_RD_COMPLETE<='0';
ELSIF(PORTB_WR_RD_COMPLETE='1') THEN
LATCH_PORTB_WR_RD_COMPLETE <='1';
ELSIF(PORTA_WR_RD_HAPPENED='1') THEN
LATCH_PORTB_WR_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
PORTB_WR_RD_L1 <='0';
PORTB_WR_RD_L2 <='0';
ELSE
PORTB_WR_RD_L1 <= LATCH_PORTB_WR_RD_COMPLETE;
PORTB_WR_RD_L2 <= PORTB_WR_RD_L1;
END IF;
END IF;
END PROCESS;
PORTA_WR_RD_EN: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
PORTA_WR_RD <='1';
ELSE
PORTA_WR_RD <= PORTB_WR_RD_L2;
END IF;
END IF;
END PROCESS;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
PORTA_WR_RD_R1 <='0';
PORTA_WR_RD_R2 <='0';
ELSE
PORTA_WR_RD_R1 <=PORTA_WR_RD;
PORTA_WR_RD_R2 <=PORTA_WR_RD_R1;
END IF;
END IF;
END PROCESS;
PORTA_WR_RD_HAPPENED <= PORTA_WR_RD_R2;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
LATCH_PORTA_WR_RD_COMPLETE<='0';
ELSIF(PORTA_WR_RD_COMPLETE='1') THEN
LATCH_PORTA_WR_RD_COMPLETE <='1';
ELSIF(PORTB_WR_RD_HAPPENED='1') THEN
LATCH_PORTA_WR_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
PORTA_WR_RD_L1 <='0';
PORTA_WR_RD_L2 <='0';
ELSE
PORTA_WR_RD_L1 <= LATCH_PORTA_WR_RD_COMPLETE;
PORTA_WR_RD_L2 <= PORTA_WR_RD_L1;
END IF;
END IF;
END PROCESS;
PORTB_EN: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
PORTB_WR_RD <='0';
ELSE
PORTB_WR_RD <= PORTA_WR_RD_L2;
END IF;
END IF;
END PROCESS;
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
PORTB_WR_RD_R1 <='0';
PORTB_WR_RD_R2 <='0';
ELSE
PORTB_WR_RD_R1 <=PORTB_WR_RD;
PORTB_WR_RD_R2 <=PORTB_WR_RD_R1;
END IF;
END IF;
END PROCESS;
---double registered of porta complete on portb clk
PORTB_WR_RD_HAPPENED <= PORTB_WR_RD_R2;
PORTA_WR_RD_COMPLETE <= '1' when count=(WRITE_CNT_A+READ_CNT_A) else '0';
start_counter: process(CLK)
begin
if(rising_edge(CLK)) then
if(RST='1') then
incr_cnt <= '0';
elsif(porta_wr_rd ='1') then
incr_cnt <='1';
elsif(porta_wr_rd_complete='1') then
incr_cnt <='0';
end if;
end if;
end process;
COUNTER: process(CLK)
begin
if(rising_edge(CLK)) then
if(RST='1') then
count <= 0;
elsif(incr_cnt='1') then
count<=count+1;
end if;
if(count=(WRITE_CNT_A+READ_CNT_A)) then
count<=0;
end if;
end if;
end process;
DO_WRITE_A<='1' when (count <WRITE_CNT_A and incr_cnt='1') else '0';
DO_READ_A <='1' when (count >WRITE_CNT_A and incr_cnt='1') else '0';
PORTB_WR_RD_COMPLETE <= '1' when count_b=(WRITE_CNT_B+READ_CNT_B) else '0';
startb_counter: process(CLK)
begin
if(rising_edge(CLK)) then
if(RST='1') then
incr_cnt_b <= '0';
elsif(portb_wr_rd ='1') then
incr_cnt_b <='1';
elsif(portb_wr_rd_complete='1') then
incr_cnt_b <='0';
end if;
end if;
end process;
COUNTER_B: process(CLK)
begin
if(rising_edge(CLK)) then
if(RST='1') then
count_b <= 0;
elsif(incr_cnt_b='1') then
count_b<=count_b+1;
end if;
if(count_b=WRITE_CNT_B+READ_CNT_B) then
count_b<=0;
end if;
end if;
end process;
DO_WRITE_B<='1' when (count_b <WRITE_CNT_B and incr_cnt_b='1') else '0';
DO_READ_B <='1' when (count_b >WRITE_CNT_B and incr_cnt_b='1') else '0';
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_DRAM
PORT MAP(
Q => DO_READ_REG_A(0),
CLK => CLK,
RST => RST,
D => DO_READ_A
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_DRAM
PORT MAP(
Q => DO_READ_REG_A(I),
CLK => CLK,
RST => RST,
D => DO_READ_REG_A(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
BEGIN_SHIFT_REG_B: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_DRAM
PORT MAP(
Q => DO_READ_REG_B(0),
CLK => CLK,
RST => RST,
D => DO_READ_B
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_DRAM
PORT MAP(
Q => DO_READ_REG_B(I),
CLK => CLK,
RST => RST,
D => DO_READ_REG_B(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG_B;
WE <= IF_THEN_ELSE(DO_WRITE='1','1','0') ;
END ARCHITECTURE;
|
mit
|
VLSI-EDA/UVVM_All
|
bitvis_vip_gpio/src/vvc_methods_pkg.vhd
|
1
|
12541
|
--========================================================================================================================
-- This VVC was generated with Bitvis VVC Generator
--========================================================================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.gpio_bfm_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_target_support_pkg.all;
--========================================================================================================================
package vvc_methods_pkg is
--========================================================================================================================
-- Types and constants for the GPIO VVC
--========================================================================================================================
constant C_VVC_NAME : string := "GPIO_VVC";
signal GPIO_VVCT : t_vvc_target_record := set_vvc_target_defaults(C_VVC_NAME);
alias THIS_VVCT : t_vvc_target_record is GPIO_VVCT;
alias t_bfm_config is t_gpio_bfm_config;
-- Type found in UVVM-Util types_pkg
constant C_GPIO_INTER_BFM_DELAY_DEFAULT : t_inter_bfm_delay := (
delay_type => NO_DELAY,
delay_in_time => 0 ns,
inter_bfm_delay_violation_severity => warning
);
type t_vvc_config is
record
inter_bfm_delay : t_inter_bfm_delay;
cmd_queue_count_max : natural;
cmd_queue_count_threshold_severity : t_alert_level;
cmd_queue_count_threshold : natural;
result_queue_count_max : natural; -- Maximum number of unfetched results before result_queue is full.
result_queue_count_threshold_severity : t_alert_level; -- An alert with severity 'result_queue_count_threshold_severity' will be issued if command queue exceeds this count.
-- Used for early warning if result queue is almost full. Will be ignored if set to 0.
result_queue_count_threshold : natural; -- Severity of alert to be initiated if exceeding result_queue_count_threshold
bfm_config : t_gpio_bfm_config;
msg_id_panel : t_msg_id_panel;
end record;
type t_vvc_config_array is array (natural range <>) of t_vvc_config;
constant C_GPIO_VVC_CONFIG_DEFAULT : t_vvc_config := (
inter_bfm_delay => C_GPIO_INTER_BFM_DELAY_DEFAULT,
cmd_queue_count_max => C_CMD_QUEUE_COUNT_MAX,
cmd_queue_count_threshold_severity => C_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
cmd_queue_count_threshold => C_CMD_QUEUE_COUNT_THRESHOLD,
result_queue_count_max => C_RESULT_QUEUE_COUNT_MAX,
result_queue_count_threshold_severity => C_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY,
result_queue_count_threshold => C_RESULT_QUEUE_COUNT_THRESHOLD,
bfm_config => C_GPIO_BFM_CONFIG_DEFAULT,
msg_id_panel => C_VVC_MSG_ID_PANEL_DEFAULT
);
type t_vvc_status is
record
current_cmd_idx : natural;
previous_cmd_idx : natural;
pending_cmd_cnt : natural;
end record;
type t_vvc_status_array is array (natural range <>) of t_vvc_status;
constant C_VVC_STATUS_DEFAULT : t_vvc_status := (
current_cmd_idx => 0,
previous_cmd_idx => 0,
pending_cmd_cnt => 0
);
type t_transaction_info is
record
operation : t_operation;
msg : string(1 to C_VVC_CMD_STRING_MAX_LENGTH);
data : std_logic_vector(C_VVC_CMD_DATA_MAX_LENGTH-1 downto 0);
end record;
type t_transaction_info_array is array (natural range <>) of t_transaction_info;
constant C_TRANSACTION_INFO_DEFAULT : t_transaction_info := (
data => (others => '0'),
operation => NO_OPERATION,
msg => (others => ' ')
);
shared variable shared_gpio_vvc_config : t_vvc_config_array(0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => C_GPIO_VVC_CONFIG_DEFAULT);
shared variable shared_gpio_vvc_status : t_vvc_status_array(0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => C_VVC_STATUS_DEFAULT);
shared variable shared_gpio_transaction_info : t_transaction_info_array(0 to C_MAX_VVC_INSTANCE_NUM-1) := (others => C_TRANSACTION_INFO_DEFAULT);
--==========================================================================================
-- Methods dedicated to this VVC
-- - These procedures are called from the testbench in order for the VVC to execute
-- BFM calls towards the given interface. The VVC interpreter will queue these calls
-- and then the VVC executor will fetch the commands from the queue and handle the
-- actual BFM execution.
-- For details on how the BFM procedures work, see the QuickRef.
--==========================================================================================
procedure gpio_set(
signal VVC : inout t_vvc_target_record;
constant instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
procedure gpio_get(
signal VVC : inout t_vvc_target_record;
constant instance_idx : in integer;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
procedure gpio_check(
signal VVC : inout t_vvc_target_record;
constant instance_idx : in integer;
constant data_exp : in std_logic_vector;
constant msg : in string := "";
constant alert_level : in t_alert_level := error;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
procedure gpio_expect(
signal VVC : inout t_vvc_target_record;
constant instance_idx : in integer;
constant data_exp : in std_logic_vector;
constant timeout : in time := 1 us;
constant msg : in string := "";
constant alert_level : in t_alert_level := error;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
);
end package vvc_methods_pkg;
package body vvc_methods_pkg is
--========================================================================================================================
-- Methods dedicated to this VVC
--========================================================================================================================
procedure gpio_set(
signal VVC : inout t_vvc_target_record;
constant instance_idx : in integer;
constant data : in std_logic_vector;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "gpio_set";
constant proc_call : string := proc_name & "(" & to_string(VVC, instance_idx) -- First part common for all
& ", " & ", " & to_string(data, HEX, KEEP_LEADING_0, INCL_RADIX) & ")";
variable v_normalised_data : std_logic_vector(shared_vvc_cmd.data'length-1 downto 0) :=
normalize_and_check(data, shared_vvc_cmd.data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVC, instance_idx, proc_call, msg, QUEUED, SET);
shared_vvc_cmd.operation := SET;
shared_vvc_cmd.data := v_normalised_data;
send_command_to_vvc(VVC, scope => scope);
end procedure;
procedure gpio_get(
signal VVC : inout t_vvc_target_record;
constant instance_idx : in integer;
constant msg : in string := "";
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "gpio_get";
constant proc_call : string := proc_name & "(" & to_string(VVC, instance_idx) -- First part common for all
& ", " & ")";
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVC, instance_idx, proc_call, msg, QUEUED, GET);
shared_vvc_cmd.operation := GET;
send_command_to_vvc(VVC, scope => scope);
end procedure;
procedure gpio_check(
signal VVC : inout t_vvc_target_record;
constant instance_idx : in integer;
constant data_exp : in std_logic_vector;
constant msg : in string := "";
constant alert_level : in t_alert_level := error;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "gpio_check";
constant proc_call : string := proc_name & "(" & to_string(VVC, instance_idx) -- First part common for all
& ", " & to_string(data_exp, HEX, KEEP_LEADING_0, INCL_RADIX) & ")";
variable v_normalised_data : std_logic_vector(shared_vvc_cmd.data_exp'length-1 downto 0) :=
normalize_and_check(data_exp, shared_vvc_cmd.data_exp, ALLOW_WIDER_NARROWER, "data_exp", "shared_vvc_cmd.data_exp", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVC, instance_idx, proc_call, msg, QUEUED, CHECK);
shared_vvc_cmd.data_exp := v_normalised_data;
shared_vvc_cmd.alert_level := alert_level;
shared_vvc_cmd.operation := CHECK;
send_command_to_vvc(VVC, scope => scope);
end procedure;
procedure gpio_expect(
signal VVC : inout t_vvc_target_record;
constant instance_idx : in integer;
constant data_exp : in std_logic_vector;
constant timeout : in time := 1 us;
constant msg : in string := "";
constant alert_level : in t_alert_level := error;
constant scope : in string := C_TB_SCOPE_DEFAULT & "(uvvm)"
) is
constant proc_name : string := "gpio_expect";
constant proc_call : string := proc_name & "(" & to_string(VVC, instance_idx) -- First part common for all
& ", " & to_string(data_exp, HEX, KEEP_LEADING_0, INCL_RADIX) & ")";
variable v_normalised_data : std_logic_vector(shared_vvc_cmd.data_exp'length-1 downto 0) :=
normalize_and_check(data_exp, shared_vvc_cmd.data_exp, ALLOW_WIDER_NARROWER, "data_exp", "shared_vvc_cmd.data_exp", proc_call & " called with to wide data. " & add_msg_delimiter(msg));
begin
-- Create command by setting common global 'VVCT' signal record and dedicated VVC 'shared_vvc_cmd' record
-- locking semaphore in set_general_target_and_command_fields to gain exclusive right to VVCT and shared_vvc_cmd
-- semaphore gets unlocked in await_cmd_from_sequencer of the targeted VVC
set_general_target_and_command_fields(VVC, instance_idx, proc_call, msg, QUEUED, EXPECT);
shared_vvc_cmd.data_exp := v_normalised_data;
shared_vvc_cmd.timeout := timeout;
shared_vvc_cmd.alert_level := alert_level;
send_command_to_vvc(VVC, scope => scope);
end procedure;
end package body vvc_methods_pkg;
|
mit
|
MForever78/CPUFly
|
ipcore_dir/Ram/simulation/bmg_tb_pkg.vhd
|
30
|
6206
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_tb_pkg.vhd
--
-- Description:
-- BMG Testbench Package files
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE :STRING)
RETURN STRING;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE :STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER;
END BMG_TB_PKG;
PACKAGE BODY BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER IS
VARIABLE DIV : INTEGER;
BEGIN
DIV := DATA_VALUE/DIVISOR;
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
DIV := DIV+1;
END IF;
RETURN DIV;
END DIVROUNDUP;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE : STD_LOGIC)
RETURN STD_LOGIC IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER IS
VARIABLE RETVAL : INTEGER := 0;
BEGIN
IF CONDITION=FALSE THEN
RETVAL:=FALSE_CASE;
ELSE
RETVAL:=TRUE_CASE;
END IF;
RETURN RETVAL;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE : STRING)
RETURN STRING IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
-------------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER IS
VARIABLE WIDTH : INTEGER := 0;
VARIABLE CNT : INTEGER := 1;
BEGIN
IF (DATA_VALUE <= 1) THEN
WIDTH := 1;
ELSE
WHILE (CNT < DATA_VALUE) LOOP
WIDTH := WIDTH + 1;
CNT := CNT *2;
END LOOP;
END IF;
RETURN WIDTH;
END LOG2ROUNDUP;
END BMG_TB_PKG;
|
mit
|
MForever78/CPUFly
|
ipcore_dir/Font/simulation/Font_tb_pkg.vhd
|
1
|
6033
|
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Font_tb_pkg.vhd
--
-- Description:
-- DMG Testbench Package files
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE Font_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE :STRING)
RETURN STRING;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE :STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER;
END Font_TB_PKG;
PACKAGE BODY Font_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER IS
VARIABLE DIV : INTEGER;
BEGIN
DIV := DATA_VALUE/DIVISOR;
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
DIV := DIV+1;
END IF;
RETURN DIV;
END DIVROUNDUP;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE : STD_LOGIC)
RETURN STD_LOGIC IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER IS
VARIABLE RETVAL : INTEGER := 0;
BEGIN
IF CONDITION=FALSE THEN
RETVAL:=FALSE_CASE;
ELSE
RETVAL:=TRUE_CASE;
END IF;
RETURN RETVAL;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE : STRING)
RETURN STRING IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
-------------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER IS
VARIABLE WIDTH : INTEGER := 0;
VARIABLE CNT : INTEGER := 1;
BEGIN
IF (DATA_VALUE <= 1) THEN
WIDTH := 1;
ELSE
WHILE (CNT < DATA_VALUE) LOOP
WIDTH := WIDTH + 1;
CNT := CNT *2;
END LOOP;
END IF;
RETURN WIDTH;
END LOG2ROUNDUP;
END Font_TB_PKG;
|
mit
|
MForever78/CPUFly
|
ipcore_dir/Instruction_Memory/simulation/Instruction_Memory_tb_stim_gen ([email protected] 2015-09-19-15-43-09).vhd
|
1
|
11029
|
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Stimulus Generator For ROM Configuration
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Instruction_Memory_tb_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For ROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.Instruction_Memory_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_ROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_ROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_ROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.Instruction_Memory_TB_PKG.ALL;
ENTITY Instruction_Memory_TB_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
A : OUT STD_LOGIC_VECTOR(14-1 downto 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (31 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END Instruction_Memory_TB_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF Instruction_Memory_TB_STIM_GEN IS
FUNCTION std_logic_vector_len(
hex_str : STD_LOGIC_VECTOR;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR(return_width DOWNTO 0) := (OTHERS => '0');
VARIABLE tmp_z : STD_LOGIC_VECTOR(return_width-(hex_str'LENGTH) DOWNTO 0) := (OTHERS => '0');
BEGIN
tmp := tmp_z & hex_str;
RETURN tmp(return_width-1 DOWNTO 0);
END std_logic_vector_len;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0):= std_logic_vector_len("0",32);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (16383 downto 0) of std_logic_vector(31 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF(input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory(
C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Distributed Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(1,
1,
"Instruction_Memory.mif",
DEFAULT_DATA,
32,
16384);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_AGEN_INST:ENTITY work.Instruction_Memory_TB_AGEN
GENERIC MAP( C_MAX_DEPTH =>16384 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA(2),
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => check_read_addr
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA(2) ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA(2)='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(13 DOWNTO 0) <= READ_ADDR(13 DOWNTO 0);
A <= READ_ADDR_INT ;
CHECK_DATA(0) <= DO_READ;
RD_AGEN_INST:ENTITY work.Instruction_Memory_TB_AGEN
GENERIC MAP( C_MAX_DEPTH => 16384 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_EN_REG: FOR I IN 0 TO 2 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_ROM
PORT MAP(
Q => CHECK_DATA(1),
CLK => CLK,
RST => RST,
D => CHECK_DATA(0)
);
END GENERATE DFF_RIGHT;
DFF_CE_OTHERS: IF ((I>0) AND (I<2)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_ROM
PORT MAP(
Q => CHECK_DATA(I+1),
CLK => CLK,
RST => RST,
D => CHECK_DATA(I)
);
END GENERATE DFF_CE_OTHERS;
END GENERATE BEGIN_EN_REG;
END ARCHITECTURE;
|
mit
|
VLSI-EDA/UVVM_All
|
bitvis_vip_axilite/src/axilite_bfm_pkg.vhd
|
1
|
33077
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
--=================================================================================================
package axilite_bfm_pkg is
--===============================================================================================
-- Types and constants for AXILITE BFMs
--===============================================================================================
constant C_SCOPE : string := "AXILITE BFM";
type t_axilite_response_status is (OKAY, SLVERR, DECERR, EXOKAY); -- EXOKAY not supported for AXI-Lite, will raise TB_FAILURE
type t_axilite_protection is(
UNPRIVILIGED_UNSECURE_DATA,
UNPRIVILIGED_UNSECURE_INSTRUCTION,
UNPRIVILIGED_SECURE_DATA,
UNPRIVILIGED_SECURE_INSTRUCTION,
PRIVILIGED_UNSECURE_DATA,
PRIVILIGED_UNSECURE_INSTRUCTION,
PRIVILIGED_SECURE_DATA,
PRIVILIGED_SECURE_INSTRUCTION
);
-- Configuration record to be assigned in the test harness.
type t_axilite_bfm_config is
record
max_wait_cycles : natural; -- Used for setting the maximum cycles to wait before an alert is issued when waiting for ready and valid signals from the DUT.
max_wait_cycles_severity : t_alert_level; -- The above timeout will have this severity
clock_period : time; -- Period of the clock signal.
clock_period_margin : time; -- Input clock period margin to specified clock_period
clock_margin_severity : t_alert_level; -- The above margin will have this severity
setup_time : time; -- Setup time for generated signals, set to clock_period/4
hold_time : time; -- Hold time for generated signals, set to clock_period/4
expected_response : t_axilite_response_status; -- Sets the expected response for both read and write transactions.
expected_response_severity : t_alert_level; -- A response mismatch will have this severity.
protection_setting : t_axilite_protection; -- Sets the AXI access permissions (e.g. write to data/instruction, privileged and secure access).
num_aw_pipe_stages : natural; -- Write Address Channel pipeline steps.
num_w_pipe_stages : natural; -- Write Data Channel pipeline steps.
num_ar_pipe_stages : natural; -- Read Address Channel pipeline steps.
num_r_pipe_stages : natural; -- Read Data Channel pipeline steps.
num_b_pipe_stages : natural; -- Response Channel pipeline steps.
id_for_bfm : t_msg_id; -- The message ID used as a general message ID in the AXI-Lite BFM
id_for_bfm_wait : t_msg_id; -- The message ID used for logging waits in the AXI-Lite BFM
id_for_bfm_poll : t_msg_id; -- The message ID used for logging polling in the AXI-Lite BFM
end record;
constant C_AXILITE_BFM_CONFIG_DEFAULT : t_axilite_bfm_config := (
max_wait_cycles => 10,
max_wait_cycles_severity => TB_FAILURE,
clock_period => 10 ns,
clock_period_margin => 0 ns,
clock_margin_severity => TB_ERROR,
setup_time => 2.5 ns,
hold_time => 2.5 ns,
expected_response => OKAY,
expected_response_severity => TB_FAILURE,
protection_setting => UNPRIVILIGED_UNSECURE_DATA,
num_aw_pipe_stages => 1,
num_w_pipe_stages => 1,
num_ar_pipe_stages => 1,
num_r_pipe_stages => 1,
num_b_pipe_stages => 1,
id_for_bfm => ID_BFM,
id_for_bfm_wait => ID_BFM_WAIT,
id_for_bfm_poll => ID_BFM_POLL
);
-- AXI-Lite Interface signals
type t_axilite_write_address_channel is record
--DUT inputs
awaddr : std_logic_vector;
awvalid : std_logic;
awprot : std_logic_vector(2 downto 0); -- [0: '0' - unpriviliged access, '1' - priviliged access; 1: '0' - secure access, '1' - non-secure access, 2: '0' - Data access, '1' - Instruction accesss]
--DUT outputs
awready : std_logic;
end record;
type t_axilite_write_data_channel is record
--DUT inputs
wdata : std_logic_vector;
wstrb : std_logic_vector;
wvalid : std_logic;
--DUT outputs
wready : std_logic;
end record;
type t_axilite_write_response_channel is record
--DUT inputs
bready : std_logic;
--DUT outputs
bresp : std_logic_vector(1 downto 0);
bvalid : std_logic;
end record;
type t_axilite_read_address_channel is record
--DUT inputs
araddr : std_logic_vector;
arvalid : std_logic;
arprot : std_logic_vector(2 downto 0); -- [0: '0' - unpriviliged access, '1' - priviliged access; 1: '0' - secure access, '1' - non-secure access, 2: '0' - Data access, '1' - Instruction accesss]
--DUT outputs
arready : std_logic;
end record;
type t_axilite_read_data_channel is record
--DUT inputs
rready : std_logic;
--DUT outputs
rdata : std_logic_vector;
rresp : std_logic_vector(1 downto 0);
rvalid : std_logic;
end record;
type t_axilite_if is record
write_address_channel : t_axilite_write_address_channel;
write_data_channel : t_axilite_write_data_channel;
write_response_channel : t_axilite_write_response_channel;
read_address_channel : t_axilite_read_address_channel;
read_data_channel : t_axilite_read_data_channel;
end record;
--===============================================================================================
-- BFM procedures
--===============================================================================================
------------------------------------------
-- init_axilite_if_signals
------------------------------------------
-- - This function returns an AXILITE interface with initialized signals.
-- - All AXILITE input signals are initialized to 0
-- - All AXILITE output signals are initialized to Z
-- - awprot and arprot are initialized to UNPRIVILIGED_UNSECURE_DATA
function init_axilite_if_signals(
addr_width : natural;
data_width : natural
) return t_axilite_if;
------------------------------------------
-- axilite_write
------------------------------------------
-- This procedure writes data to the AXILITE interface specified in axilite_if
-- - The protection setting is set to UNPRIVILIGED_UNSECURE_DATA in this procedure
-- - The byte enable input is set to 1 for all bytes in this procedure
-- - When the write is completed, a log message is issued with log ID id_for_bfm
procedure axilite_write (
constant addr_value : in unsigned;
constant data_value : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal axilite_if : inout t_axilite_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axilite_bfm_config := C_AXILITE_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- axilite_write
------------------------------------------
-- This procedure writes data to the AXILITE interface specified in axilite_if
-- - When the write is completed, a log message is issued with log ID id_for_bfm
procedure axilite_write (
constant addr_value : in unsigned;
constant data_value : in std_logic_vector;
constant byte_enable : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal axilite_if : inout t_axilite_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axilite_bfm_config := C_AXILITE_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- axilite_read
------------------------------------------
-- This procedure reads data from the AXILITE interface specified in axilite_if,
-- and returns the read data in data_value.
procedure axilite_read (
constant addr_value : in unsigned;
variable data_value : out std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal axilite_if : inout t_axilite_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axilite_bfm_config := C_AXILITE_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like axilite_check
);
------------------------------------------
-- axilite_check
------------------------------------------
-- This procedure reads data from the AXILITE interface specified in axilite_if,
-- and compares it to the data in data_exp.
-- - If the received data inconsistent with data_exp, an alert with severity
-- alert_level is issued.
-- - If the received data was correct, a log message with ID id_for_bfm is issued.
procedure axilite_check (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal axilite_if : inout t_axilite_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axilite_bfm_config := C_AXILITE_BFM_CONFIG_DEFAULT
);
end package axilite_bfm_pkg;
--=================================================================================================
--=================================================================================================
package body axilite_bfm_pkg is
----------------------------------------------------
-- Support procedures
----------------------------------------------------
function to_slv(
protection : t_axilite_protection
) return std_logic_vector is
variable v_prot_slv : std_logic_vector(2 downto 0);
begin
case protection is
when UNPRIVILIGED_UNSECURE_DATA =>
v_prot_slv := "010";
when UNPRIVILIGED_UNSECURE_INSTRUCTION =>
v_prot_slv := "011";
when UNPRIVILIGED_SECURE_DATA =>
v_prot_slv := "000";
when UNPRIVILIGED_SECURE_INSTRUCTION =>
v_prot_slv := "001";
when PRIVILIGED_UNSECURE_DATA =>
v_prot_slv := "110";
when PRIVILIGED_UNSECURE_INSTRUCTION =>
v_prot_slv := "111";
when PRIVILIGED_SECURE_DATA =>
v_prot_slv := "100";
when PRIVILIGED_SECURE_INSTRUCTION =>
v_prot_slv := "101";
end case;
return v_prot_slv;
end function;
function to_slv(
axilite_response_status : t_axilite_response_status;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel
) return std_logic_vector is
variable v_axilite_response_status_slv : std_logic_vector(1 downto 0);
begin
check_value(axilite_response_status /= EXOKAY, TB_FAILURE, "EXOKAY response status is not supported in AXI-Lite", scope, ID_NEVER, msg_id_panel);
case axilite_response_status is
when OKAY =>
v_axilite_response_status_slv := "00";
when SLVERR =>
v_axilite_response_status_slv := "10";
when DECERR =>
v_axilite_response_status_slv := "11";
when EXOKAY =>
v_axilite_response_status_slv := "01";
end case;
return v_axilite_response_status_slv;
end function;
function to_axilite_response_status(
resp : std_logic_vector(1 downto 0);
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel
) return t_axilite_response_status is
begin
check_value(resp /= "01", TB_FAILURE, "EXOKAY response status is not supported in AXI-Lite", scope, ID_NEVER, msg_id_panel);
case resp is
when "00" =>
return OKAY;
when "10" =>
return SLVERR;
when "11" =>
return DECERR;
when others =>
return EXOKAY;
end case;
end function;
----------------------------------------------------
-- BFM procedures
----------------------------------------------------
function init_axilite_if_signals(
addr_width : natural;
data_width : natural
) return t_axilite_if is
variable init_if : t_axilite_if( write_address_channel( awaddr( addr_width -1 downto 0)),
write_data_channel( wdata( data_width -1 downto 0),
wstrb(( data_width/8) -1 downto 0)),
read_address_channel( araddr( addr_width -1 downto 0)),
read_data_channel( rdata( data_width -1 downto 0)));
begin
-- Write Address Channel
init_if.write_address_channel.awaddr := (init_if.write_address_channel.awaddr'range => '0');
init_if.write_address_channel.awvalid := '0';
init_if.write_address_channel.awprot := to_slv(UNPRIVILIGED_UNSECURE_DATA); --"010"
init_if.write_address_channel.awready := 'Z';
-- Write Data Channel
init_if.write_data_channel.wdata := (init_if.write_data_channel.wdata'range => '0');
init_if.write_data_channel.wstrb := (init_if.write_data_channel.wstrb'range => '0');
init_if.write_data_channel.wvalid := '0';
init_if.write_data_channel.wready := 'Z';
-- Write Response Channel
init_if.write_response_channel.bready := '0';
init_if.write_response_channel.bresp := (init_if.write_response_channel.bresp'range => 'Z');
init_if.write_response_channel.bvalid := 'Z';
-- Read Address Channel
init_if.read_address_channel.araddr := (init_if.read_address_channel.araddr'range => '0');
init_if.read_address_channel.arvalid := '0';
init_if.read_address_channel.arprot := to_slv(UNPRIVILIGED_UNSECURE_DATA); --"010"
init_if.read_address_channel.arready := 'Z';
-- Read Data Channel
init_if.read_data_channel.rready := '0';
init_if.read_data_channel.rdata := (init_if.read_data_channel.rdata'range => 'Z');
init_if.read_data_channel.rresp := (init_if.read_data_channel.rresp'range => 'Z');
init_if.read_data_channel.rvalid := 'Z';
return init_if;
end function;
procedure axilite_write (
constant addr_value : in unsigned;
constant data_value : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal axilite_if : inout t_axilite_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axilite_bfm_config := C_AXILITE_BFM_CONFIG_DEFAULT
) is
constant C_BYTE_ENABLE : std_logic_vector(axilite_if.write_data_channel.wstrb'length-1 downto 0) := (others => '1');
begin
axilite_write(addr_value, data_value, C_BYTE_ENABLE, msg, clk, axilite_if, scope, msg_id_panel, config);
end procedure axilite_write;
procedure axilite_write (
constant addr_value : in unsigned;
constant data_value : in std_logic_vector;
constant byte_enable : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal axilite_if : inout t_axilite_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axilite_bfm_config := C_AXILITE_BFM_CONFIG_DEFAULT
) is
constant proc_name : string := "axilite_write";
constant proc_call : string := "axilite_write(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) &
", " & to_string(data_value, HEX, AS_IS, INCL_RADIX) & ")";
constant max_pipe_stages : integer := maximum(config.num_w_pipe_stages, config.num_aw_pipe_stages);
variable v_await_awready : boolean := true;
variable v_await_wready : boolean := true;
variable v_await_bvalid : boolean := true;
-- Normalize to the DUT addr/data widths
variable v_normalized_addr : std_logic_vector(axilite_if.write_address_channel.awaddr'length-1 downto 0) :=
normalize_and_check(std_logic_vector(addr_value), axilite_if.write_address_channel.awaddr, ALLOW_NARROWER, "addr", "axilite_if.write_address_channel.awaddr", msg);
variable v_normalized_data : std_logic_vector(axilite_if.write_data_channel.wdata'length-1 downto 0) :=
normalize_and_check(data_value, axilite_if.write_data_channel.wdata, ALLOW_NARROWER, "data", "axilite_if.write_data_channel.wdata", msg);
-- Helper variables
variable v_last_rising_edge : time := -1 ns; -- time stamp for clk period checking
begin
check_value(v_normalized_data'length = 32 or v_normalized_data'length = 64, TB_ERROR, "AXI-lite data width must be either 32 or 64!", scope, ID_NEVER, msg_id_panel);
-- setup_time and hold_time checking
check_value(config.setup_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that setup_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(config.hold_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that hold_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(config.setup_time > 0 ns, TB_FAILURE, "Sanity check: Check that setup_time is more than 0 ns.", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(config.hold_time > 0 ns, TB_FAILURE, "Sanity check: Check that hold_time is more than 0 ns.", scope, ID_NEVER, msg_id_panel, proc_call);
for cycle in 0 to config.max_wait_cycles loop
-- check if enough room for setup_time in low period
if (clk = '0') and (config.setup_time > (config.clock_period/2 - clk'last_event))then
await_value(clk, '1', 0 ns, config.clock_period/2, TB_FAILURE, proc_call & ": timeout waiting for clk low period for setup_time.");
end if;
-- Wait setup_time specified in config record
wait_until_given_time_before_rising_edge(clk, config.setup_time, config.clock_period);
if cycle = config.num_w_pipe_stages then
axilite_if.write_data_channel.wdata <= v_normalized_data;
axilite_if.write_data_channel.wstrb <= byte_enable;
axilite_if.write_data_channel.wvalid <= '1';
end if;
if cycle = config.num_aw_pipe_stages then
axilite_if.write_address_channel.awaddr <= v_normalized_addr;
axilite_if.write_address_channel.awvalid <= '1';
axilite_if.write_address_channel.awprot <= to_slv(config.protection_setting);
end if;
wait until rising_edge(clk);
-- check if clk period since last rising edge is within specifications and take a new time stamp
if v_last_rising_edge > -1 ns then
check_value_in_range(now - v_last_rising_edge, config.clock_period - config.clock_period_margin, config.clock_period + config.clock_period_margin, config.clock_margin_severity, "checking clk period is within requirement.");
end if;
v_last_rising_edge := now; -- time stamp for clk period checking
if axilite_if.write_data_channel.wready = '1' and cycle >= config.num_w_pipe_stages then
axilite_if.write_data_channel.wvalid <= '0' after config.clock_period/4;
v_await_wready := false;
end if;
if axilite_if.write_address_channel.awready = '1' and cycle >= config.num_aw_pipe_stages then
axilite_if.write_address_channel.awvalid <= '0' after config.clock_period/4;
v_await_awready := false;
end if;
if not v_await_awready and not v_await_wready then
exit;
end if;
end loop;
check_value(not v_await_wready, config.max_wait_cycles_severity, ": Timeout waiting for WREADY", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(not v_await_awready, config.max_wait_cycles_severity, ": Timeout waiting for AWREADY", scope, ID_NEVER, msg_id_panel, proc_call);
-- check if enough room for setup_time before next clk rising edge
if (clk = '0') and (config.setup_time > (config.clock_period/2 - clk'last_event))then
await_value(clk, '1', 0 ns, config.clock_period/2, TB_FAILURE, proc_call & ": timeout waiting for clk low period for setup_time.");
end if;
-- Wait setup_time specified in config record
wait_until_given_time_before_rising_edge(clk, config.setup_time, config.clock_period);
axilite_if.write_response_channel.bready <= '1';
for cycle in 0 to config.max_wait_cycles loop
wait until rising_edge(clk);
-- check if clk period since last rising edge is within specifications and take a new time stamp
if v_last_rising_edge > -1 ns then
check_value_in_range(now - v_last_rising_edge, config.clock_period - config.clock_period_margin, config.clock_period + config.clock_period_margin, config.clock_margin_severity, "checking clk period is within requirement.");
end if;
v_last_rising_edge := now; -- time stamp for clk period checking
if axilite_if.write_response_channel.bvalid = '1' then
check_value(axilite_if.write_response_channel.bresp, to_slv(config.expected_response), config.expected_response_severity, ": BRESP detected", scope, BIN, AS_IS, ID_NEVER, msg_id_panel, proc_call);
-- Wait hold_time specified in config record
wait_until_given_time_after_rising_edge(clk, config.hold_time);
axilite_if.write_response_channel.bready <= '0';
v_await_bvalid := false;
end if;
if not v_await_bvalid then
exit;
end if;
end loop;
check_value(not v_await_bvalid, config.max_wait_cycles_severity, ": Timeout waiting for BVALID", scope, ID_NEVER, msg_id_panel, proc_call);
axilite_if.write_address_channel.awaddr(axilite_if.write_address_channel.awaddr'length-1 downto 0) <= (others => '0');
axilite_if.write_address_channel.awvalid <= '0';
axilite_if.write_data_channel.wdata(axilite_if.write_data_channel.wdata'length-1 downto 0) <= (others => '0');
axilite_if.write_data_channel.wstrb(axilite_if.write_data_channel.wstrb'length-1 downto 0) <= (others => '1');
axilite_if.write_data_channel.wvalid <= '0';
log(config.id_for_bfm, proc_call & " completed. " & add_msg_delimiter(msg), scope, msg_id_panel);
end procedure axilite_write;
procedure axilite_read (
constant addr_value : in unsigned;
variable data_value : out std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal axilite_if : inout t_axilite_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axilite_bfm_config := C_AXILITE_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like axilite_check
) is
constant local_proc_name : string := "axilite_read"; -- Local proc_name; used if called from sequncer or VVC
constant local_proc_call : string := local_proc_name & "(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) & ")"; -- Local proc_call; used if called from sequncer or VVC
-- Normalize to the DUT addr/data widths
variable v_normalized_addr : std_logic_vector(axilite_if.read_address_channel.araddr'length-1 downto 0) :=
normalize_and_check(std_logic_vector(addr_value), axilite_if.read_address_channel.araddr, ALLOW_NARROWER, "addr", "axilite_if.read_address_channel.araddr", msg);
-- Helper variables
variable v_proc_call : line;
variable v_await_arready : boolean := true;
variable v_await_rvalid : boolean := true;
variable v_data_value : std_logic_vector(axilite_if.read_data_channel.rdata'length-1 downto 0);
variable v_last_rising_edge : time := -1 ns; -- time stamp for clk period checking
begin
-- setup_time and hold_time checking
check_value(config.setup_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that setup_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, local_proc_call);
check_value(config.hold_time < config.clock_period/2, TB_FAILURE, "Sanity check: Check that hold_time do not exceed clock_period/2.", scope, ID_NEVER, msg_id_panel, local_proc_call);
check_value(config.setup_time > 0 ns, TB_FAILURE, "Sanity check: Check that setup_time is more than 0 ns.", scope, ID_NEVER, msg_id_panel, local_proc_call);
check_value(config.hold_time > 0 ns, TB_FAILURE, "Sanity check: Check that hold_time is more than 0 ns.", scope, ID_NEVER, msg_id_panel, local_proc_call);
-- If called from sequencer/VVC, show 'axilite_read...' in log
if ext_proc_call = "" then
write(v_proc_call, local_proc_call);
else
-- If called from other BFM procedure like axilite_expect, log 'axilite_check(..) while executing axilite_read..'
write(v_proc_call, ext_proc_call & " while executing " & local_proc_name);
end if;
check_value(v_data_value'length = 32 or v_data_value'length = 64, TB_ERROR, "AXI-lite data width must be either 32 or 64!" & add_msg_delimiter(msg), scope, ID_NEVER, msg_id_panel);
-- Wait setup_time specified in config record
wait_until_given_time_before_rising_edge(clk, config.setup_time, config.clock_period);
axilite_if.read_address_channel.araddr <= v_normalized_addr;
axilite_if.read_address_channel.arvalid <= '1';
for cycle in 0 to config.max_wait_cycles loop
if axilite_if.read_address_channel.arready = '1' and cycle > 0 then
axilite_if.read_address_channel.arvalid <= '0';
axilite_if.read_address_channel.araddr(axilite_if.read_address_channel.araddr'length-1 downto 0) <= (others => '0');
axilite_if.read_address_channel.arprot <= to_slv(config.protection_setting);
v_await_arready := false;
end if;
if v_await_arready then
wait until rising_edge(clk);
-- check if clk period since last rising edge is within specifications and take a new time stamp
if v_last_rising_edge > -1 ns then
check_value_in_range(now - v_last_rising_edge, config.clock_period - config.clock_period_margin, config.clock_period + config.clock_period_margin, config.clock_margin_severity, "checking clk period is within requirement.");
end if;
v_last_rising_edge := now; -- time stamp for clk period checking
else
exit;
end if;
end loop;
check_value(not v_await_arready, config.max_wait_cycles_severity, ": Timeout waiting for ARREADY", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
-- Wait setup_time specified in config record
wait_until_given_time_before_rising_edge(clk, config.setup_time, config.clock_period);
axilite_if.read_data_channel.rready <= '1';
for cycle in 0 to config.max_wait_cycles loop
if axilite_if.read_data_channel.rvalid = '1' and cycle > 0 then
v_await_rvalid := false;
check_value(axilite_if.read_data_channel.rresp, to_slv(config.expected_response), config.expected_response_severity, ": RRESP detected", scope, BIN, AS_IS, ID_NEVER, msg_id_panel, v_proc_call.all);
v_data_value := axilite_if.read_data_channel.rdata;
-- Wait hold time specified in config record
wait_until_given_time_after_rising_edge(clk, config.clock_period/4);
axilite_if.read_data_channel.rready <= '0';
end if;
if v_await_rvalid then
wait until rising_edge(clk);
-- check if clk period since last rising edge is within specifications and take a new time stamp
if v_last_rising_edge > -1 ns then
check_value_in_range(now - v_last_rising_edge, config.clock_period - config.clock_period_margin, config.clock_period + config.clock_period_margin, config.clock_margin_severity, "checking clk period is within requirement.");
end if;
v_last_rising_edge := now; -- time stamp for clk period checking
else
exit;
end if;
end loop;
check_value(not v_await_rvalid, config.max_wait_cycles_severity, ": Timeout waiting for RVALID", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
data_value := v_data_value;
if ext_proc_call = "" then -- proc_name = "axilite_read" then
log(config.id_for_bfm, v_proc_call.all & "=> " & to_string(v_data_value, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
end if;
end procedure axilite_read;
procedure axilite_check (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal axilite_if : inout t_axilite_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axilite_bfm_config := C_AXILITE_BFM_CONFIG_DEFAULT
) is
constant proc_name : string := "axilite_check";
constant proc_call : string := "axilite_check(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) & ", " & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & ")";
variable v_data_value : std_logic_vector(axilite_if.write_data_channel.wdata'length-1 downto 0) := (others => '0');
variable v_check_ok : boolean;
-- Normalize to the DUT addr/data widths
variable v_normalized_data : std_logic_vector(axilite_if.write_data_channel.wdata'length-1 downto 0) :=
normalize_and_check(data_exp, axilite_if.write_data_channel.wdata, ALLOW_NARROWER, "data", "axilite_if.write_data_channel.wdata", msg);
begin
axilite_read(addr_value, v_data_value, msg, clk, axilite_if, scope, msg_id_panel, config, proc_call);
v_check_ok := true;
for i in 0 to v_normalized_data'length-1 loop
if v_normalized_data(i) = '-' or v_normalized_data(i) = v_data_value(i) then
v_check_ok := true;
else
v_check_ok := false;
exit;
end if;
end loop;
if not v_check_ok then
alert(alert_level, proc_call & "=> Failed. slv Was " & to_string(v_data_value, HEX, AS_IS, INCL_RADIX) & ". Expected " & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & "." & LF & add_msg_delimiter(msg), scope);
else
log(config.id_for_bfm, proc_call & "=> OK, received data = " & to_string(v_normalized_data, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
end procedure axilite_check;
end package body axilite_bfm_pkg;
|
mit
|
VLSI-EDA/UVVM_All
|
bitvis_uart/src/uart_pif.vhd
|
3
|
3359
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.uart_pif_pkg.all;
entity uart_pif is
port(
arst : in std_logic;
clk : in std_logic;
-- CPU interface
cs : in std_logic;
addr : in unsigned;
wr : in std_logic;
rd : in std_logic;
wdata : in std_logic_vector(7 downto 0);
rdata : out std_logic_vector(7 downto 0) := (others => '0');
--
p2c : out t_p2c;
c2p : in t_c2p
);
end uart_pif;
architecture rtl of uart_pif is
signal p2c_i : t_p2c; -- internal version of output
signal rdata_i : std_logic_vector(7 downto 0) := (others => '0');
begin
-- Assigning internally used signals to outputs
p2c <= p2c_i;
--
-- Auxiliary Register Control.
--
-- Provides read/write/trigger strobes and write data to auxiliary
-- registers and fields, i.e., registers and fields implemented in core.
--
p_aux : process (wdata, addr, cs, wr, rd)
begin
-- Defaults
p2c_i.awo_tx_data <= (others => '0');
p2c_i.awo_tx_data_we <= '0';
p2c_i.aro_rx_data_re <= '0';
-- Write decoding
if wr = '1' and cs = '1' then
case to_integer(addr) is
when C_ADDR_TX_DATA =>
p2c_i.awo_tx_data <= wdata;
p2c_i.awo_tx_data_we <= '1';
when others =>
null;
end case;
end if;
-- Read Enable Decoding
if rd = '1' and cs = '1' then
case to_integer(addr) is
when C_ADDR_RX_DATA =>
p2c_i.aro_rx_data_re <= '1';
when others =>
null;
end case;
end if;
end process p_aux;
p_read_reg : process(cs, addr, rd, c2p, p2c_i)
begin
-- default values
rdata_i <= (others => '0');
if cs = '1' and rd = '1' then
case to_integer(addr) is
when C_ADDR_RX_DATA =>
rdata_i(7 downto 0) <= c2p.aro_rx_data;
when C_ADDR_RX_DATA_VALID =>
rdata_i(0) <= c2p.aro_rx_data_valid;
when C_ADDR_TX_READY =>
rdata_i(0) <= c2p.aro_tx_ready;
when others =>
null;
end case;
end if;
end process p_read_reg;
rdata <= rdata_i;
end rtl;
|
mit
|
Given-Jiang/Binarization
|
tb_Binarization/hdl/alt_dspbuilder_cast_GN46N4UJ5S.vhd
|
20
|
844
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GN46N4UJ5S is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic;
output : out std_logic_vector(0 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GN46N4UJ5S is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 1 + 1 ,
width_inr=> 0,
width_outl=> 1,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(0) => input,
xin(1) => '0', yout => output
);
end architecture;
|
mit
|
Given-Jiang/Binarization
|
tb_Binarization/db/alt_dspbuilder_SInitDelay.vhd
|
20
|
3601
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 7.2)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2007 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_SInitDelay is
generic (
lpm_width : positive :=8;
lpm_delay : positive :=2;
SequenceLength : positive :=1;
SequenceValue : std_logic_vector :="1";
ResetValue : std_logic_vector :="00000001"
);
port (
dataa : in std_logic_vector(lpm_width-1 downto 0);
clock : in std_logic ;
ena : in std_logic :='1';
aclr : in std_logic :='0';
user_aclr : in std_logic :='0';
sclr : in std_logic :='0';
result : out std_logic_vector(lpm_width-1 downto 0) :=(others=>'0')
);
end alt_dspbuilder_SInitDelay;
architecture SInitDelay_SYNTH of alt_dspbuilder_SInitDelay is
type StdUArray is array (lpm_delay-1 downto 0) of std_logic_vector (lpm_width-1 downto 0);
signal DelayLine : StdUArray;
signal dataa_int : std_logic_vector(lpm_width-1 downto 0);
signal seqenable : std_logic ;
signal enadff : std_logic ;
signal aclr_i : std_logic ;
begin
aclr_i <= aclr or user_aclr;
u0: alt_dspbuilder_sAltrPropagate generic map(QTB=>DSPBuilderQTB, QTB_PRODUCT => DSPBuilderProduct, QTB_VERSION => DSPBuilderVersion , width=> lpm_width)
port map (d => dataa, r => dataa_int);
gnoseq: if ((SequenceLength=1) and (SequenceValue="1")) generate
enadff <= ena;
end generate gnoseq;
gseq: if not ((SequenceLength=1) and (SequenceValue="1")) generate
u:alt_dspbuilder_vecseq generic map (SequenceLength=>SequenceLength,SequenceValue=>SequenceValue)
port map (clock=>clock, ena=>ena, aclr=>aclr_i, sclr=>sclr, yout=> seqenable);
enadff <= seqenable and ena;
end generate gseq;
gen1:if lpm_delay=1 generate
process(clock, aclr_i)
begin
if aclr_i='1' then
result <= ResetValue;
elsif clock'event and clock='1' then
if (sclr ='1') then
result <= ResetValue;
elsif enadff ='1' then
result <= dataa_int;
end if;
end if;
end process;
end generate;
gen2:if lpm_delay>1 generate
process(clock, aclr_i)
begin
if aclr_i='1' then
DelayLine <= (others => ResetValue);
elsif clock'event and clock='1' then
if (sclr='1') then
DelayLine <= (others => ResetValue);
elsif (enadff='1') then
DelayLine(0) <= dataa_int;
for i in 1 to lpm_delay-1 loop
DelayLine(i) <= DelayLine(i-1);
end loop;
end if;
end if;
end process;
result <= DelayLine(lpm_delay-1);
end generate;
end SInitDelay_SYNTH;
|
mit
|
Given-Jiang/Binarization
|
Binarization_dspbuilder/hdl/alt_dspbuilder_vcc.vhd
|
20
|
747
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_vcc is
port (
output : out std_logic
);
end entity alt_dspbuilder_vcc;
architecture rtl of alt_dspbuilder_vcc is
component alt_dspbuilder_vcc_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_vcc_GN;
begin
alt_dspbuilder_vcc_GN_0: if true generate
inst_alt_dspbuilder_vcc_GN_0: alt_dspbuilder_vcc_GN
port map(output => output);
end generate;
end architecture rtl;
|
mit
|
KaskMartin/Digiloogika_ALU
|
ALU_FPGA/mux.vhdl
|
2
|
1315
|
------------------------------------------------------------------------------
-- File: mux.vhd
------------------------------------------------------------------------------
--Multiplexer design
--The output is chosen based on 2 bit control signal from 4 signals with length 4 bits
--If control signal is '00' then input F1_in is chosen to the output m_o
--If '01' then input F2_in is chosen to the output m_o
--If '10' then input F3_in is chosen to the output m_o
--If '11' then input F4_in is chosen to the output m_o
library IEEE;
use IEEE.std_logic_1164.all;
--Multiplexer entity
entity Mux is
port ( m_op : in STD_LOGIC_VECTOR (1 downto 0);
F1_in : in STD_LOGIC_VECTOR (3 downto 0);
F2_in : in STD_LOGIC_VECTOR (3 downto 0);
F3_in : in STD_LOGIC_VECTOR (3 downto 0);
F4_in : in STD_LOGIC_VECTOR (3 downto 0);
m_o : out STD_LOGIC_VECTOR (3 downto 0));
end Mux;
--Architecture of the multiplexer
architecture RTL of Mux is
begin
--Behavioural process DISP_MUX
DISP_MUX: process ( F1_in, F2_in, F3_in, F4_in, m_op ) --sensitivity list
begin
case m_op is
when "00" => m_o <= F1_in;
when "01" => m_o <= F2_in;
when "10" => m_o <= F3_in;
when "11" => m_o <= F4_in;
when others => m_o <= F1_in;
end case;
end process DISP_MUX;
end RTL;
|
mit
|
Given-Jiang/Binarization
|
tb_Binarization/altera_lnsim/generic_28nm_hp_mlab_cell_impl/_primary.vhd
|
5
|
2780
|
library verilog;
use verilog.vl_types.all;
entity generic_28nm_hp_mlab_cell_impl is
generic(
logical_ram_name: string := "lutram";
logical_ram_depth: integer := 0;
logical_ram_width: integer := 0;
first_address : integer := 0;
last_address : integer := 0;
first_bit_number: integer := 0;
mixed_port_feed_through_mode: string := "new";
init_file : string := "NONE";
data_width : integer := 20;
address_width : integer := 6;
byte_enable_mask_width: integer := 1;
byte_size : integer := 1;
port_b_data_out_clock: string := "none";
port_b_data_out_clear: string := "none";
lpm_type : string := "common_28nm_mlab_cell";
lpm_hint : string := "true";
mem_init0 : string := ""
);
port(
portadatain : in vl_logic_vector;
portaaddr : in vl_logic_vector;
portabyteenamasks: in vl_logic_vector;
portbaddr : in vl_logic_vector;
clk0 : in vl_logic;
clk1 : in vl_logic;
ena0 : in vl_logic;
ena1 : in vl_logic;
ena2 : in vl_logic;
clr : in vl_logic;
devclrn : in vl_logic;
devpor : in vl_logic;
portbdataout : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of logical_ram_name : constant is 1;
attribute mti_svvh_generic_type of logical_ram_depth : constant is 1;
attribute mti_svvh_generic_type of logical_ram_width : constant is 1;
attribute mti_svvh_generic_type of first_address : constant is 1;
attribute mti_svvh_generic_type of last_address : constant is 1;
attribute mti_svvh_generic_type of first_bit_number : constant is 1;
attribute mti_svvh_generic_type of mixed_port_feed_through_mode : constant is 1;
attribute mti_svvh_generic_type of init_file : constant is 1;
attribute mti_svvh_generic_type of data_width : constant is 1;
attribute mti_svvh_generic_type of address_width : constant is 1;
attribute mti_svvh_generic_type of byte_enable_mask_width : constant is 1;
attribute mti_svvh_generic_type of byte_size : constant is 1;
attribute mti_svvh_generic_type of port_b_data_out_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_data_out_clear : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of mem_init0 : constant is 1;
end generic_28nm_hp_mlab_cell_impl;
|
mit
|
MrDoomBringer/DSD-Labs
|
Lab 9/vendi.vhd
|
1
|
4597
|
-- FPGA Clock Circuit for Altera DE-2 board
-- Cliff Chapman
-- 11/04/2013
--
-- Lab 9 - Digital Systems Design
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_signed.ALL;
ENTITY vendi IS
PORT (
-- Coins input
nickel_in : IN STD_LOGIC;
dime_in : IN STD_LOGIC;
quarter_in : IN STD_LOGIC;
-- User actions
dispense : IN STD_LOGIC;
coin_return : IN STD_LOGIC;
-- Machine data
clk : IN STD_LOGIC;
rst : IN STD_LOGIC := '1';
-- LED dispense status
change_back : OUT STD_LOGIC;
red_bull : OUT STD_LOGIC;
-- Coin amount displays
HEX0_disp : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
HEX1_disp : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
);
END vendi;
ARCHITECTURE a OF vendi IS
COMPONENT sevenseg_bcd_display
PORT (
r : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
s : IN STD_LOGIC := '1'; -- Select tied to '1' by default to show numeric values
HEX0, HEX1, HEX2 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0)
);
END COMPONENT;
SIGNAL coin_val : STD_LOGIC_VECTOR (7 DOWNTO 0);
-- Build an enumerated type for the state machine
-- This feels like a GREAT way to screw yourself over with
-- overloading common names. Maybe that's just me.
-- Either way that's why we have the _s hungarian postfix on these.
TYPE state_type IS
( idle_s, nickle_s, dime_s, quarter_s
, enough_s, excess_s, vend_s, change_s
);
-- Register to hold the current state
SIGNAL state : state_type;
BEGIN
-- Display output of current coin value
display : sevenseg_bcd_display PORT MAP (
r => coin_val,
s => '1',
HEX2 => OPEN,
HEX1 => HEX1_disp,
HEX0 => HEX0_disp
);
state_monitor : PROCESS (rst, clk)
BEGIN
IF (rst = '0') THEN
state <= idle_s;
ELSIF (rising_edge(clk)) THEN
CASE state IS
-- IDLE STATE
WHEN idle_s =>
IF (nickel_in = '1') THEN
state <= nickle_s;
ELSIF (dime_in = '1') THEN
state <= dime_s;
ELSIF (quarter_in = '1') THEN
state <= quarter_s;
ELSIF (coin_val >= "01001011") THEN
state <= enough_s;
ELSE
state <= idle_s;
END IF;
-- Coins states
WHEN nickle_s =>
IF (coin_val >= "01001011") THEN
state <= enough_s;
ELSE
state <= idle_s;
END IF;
WHEN dime_s =>
IF (coin_val >= "01001011") THEN
state <= enough_s;
ELSE
state <= idle_s;
END IF;
WHEN quarter_s =>
IF (coin_val >= "01001011") THEN
state <= enough_s;
ELSE
state <= idle_s;
END IF;
-- Enough money
WHEN enough_s =>
IF (coin_return = '1') THEN
state <= change_s;
ELSIF (dispense = '1') THEN
state <= vend_s;
ELSIF (nickel_in = '1') THEN
state <= excess_s;
ELSIF (dime_in = '1') THEN
state <= excess_s;
ELSIF (quarter_in = '1') THEN
state <= excess_s;
ELSE
state <= enough_s;
END IF;
-- Too much money (Display may overload, can store up to 255 cents)
-- TODO: add auto-return dump for values over 2 dollars?
WHEN excess_s =>
IF (coin_return = '1') THEN
state <= change_s;
ELSIF (dispense = '1') THEN
state <= vend_s;
-- Coin block again
ELSIF (nickel_in = '1') THEN
state <= excess_s;
ELSIF (dime_in = '1') THEN
state <= excess_s;
ELSIF (quarter_in = '1') THEN
state <= excess_s;
ELSE
state <= excess_s;
END IF;
WHEN vend_s =>
IF (coin_val = "00000000") THEN
state <= idle_s;
ELSIF (coin_val > "00000000") THEN
state <= change_s;
END IF;
WHEN OTHERS =>
state <= idle_s;
END CASE;
END IF;
END PROCESS state_monitor;
PROCESS (state)
BEGIN
IF (state = vend_s) THEN
red_bull <= '1';
ELSE
red_bull <= '0';
END IF;
IF (state = change_s) THEN
change_back <= '1';
ELSIF (state = excess_s) THEN
change_back <= '1';
ELSE
change_back <= '0';
END IF;
END PROCESS;
state_output : PROCESS (state, clk, rst)
VARIABLE coin_cnt : STD_LOGIC_VECTOR (7 DOWNTO 0) := "00000000";
BEGIN
IF (rst = '0') THEN
coin_cnt := "00000000";
ELSIF (rising_edge(clk) AND rst = '1') THEN
CASE state IS
WHEN nickle_s => coin_cnt := coin_cnt + "00000101";
WHEN dime_s => coin_cnt := coin_cnt + "00001010";
WHEN quarter_s => coin_cnt := coin_cnt + "00011001";
WHEN vend_s => coin_cnt := coin_cnt - "01001011";
WHEN change_s => coin_cnt := "00000000";
WHEN OTHERS => coin_cnt := coin_cnt;
END CASE;
ELSE
coin_cnt := coin_cnt;
END IF;
coin_val <= coin_cnt;
END PROCESS state_output;
END ARCHITECTURE;
|
mit
|
Given-Jiang/Binarization
|
Binarization_dspbuilder/db/alt_dspbuilder_testbench_salt_GN7Z4SHGOK.vhd
|
17
|
1749
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
library std;
use std.textio.all;
entity alt_dspbuilder_testbench_salt_GN7Z4SHGOK is
generic ( XFILE : string := "default");
port(
clock : in std_logic;
aclr : in std_logic;
output : out std_logic_vector(31 downto 0));
end entity;
architecture rtl of alt_dspbuilder_testbench_salt_GN7Z4SHGOK is
function to_std_logic (B: character) return std_logic is
begin
case B is
when '0' => return '0';
when '1' => return '1';
when OTHERS => return 'X';
end case;
end;
function to_std_logic_vector (B: string) return
std_logic_vector is
variable res: std_logic_vector (B'range);
begin
for i in B'range loop
case B(i) is
when '0' => res(i) := '0';
when '1' => res(i) := '1';
when OTHERS => res(i) := 'X';
end case;
end loop;
return res;
end;
procedure skip_type_header(file f:text) is
use STD.textio.all;
variable in_line : line;
begin
readline(f, in_line);
end procedure skip_type_header ;
file InputFile : text open read_mode is XFILE;
Begin
-- salt generator
skip_type_header(InputFile);
-- Reading Simulink Input
Input_pInput:process(clock, aclr)
variable s : string(1 to 32) ;
variable ptr : line ;
begin
if (aclr = '1') then
output <= (others=>'0');
elsif (not endfile(InputFile)) then
if clock'event and clock='0' then
readline(Inputfile, ptr);
read(ptr, s);
output <= to_std_logic_vector(s);
end if ;
end if ;
end process ;
end architecture;
|
mit
|
Given-Jiang/Binarization
|
Binarization_dspbuilder/db/alt_dspbuilder_SBF.vhd
|
20
|
8869
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_SBF is
generic (
width_inl : natural :=10;
width_inr : natural :=10;
width_outl : natural :=8;
width_outr : natural :=8;
round : natural :=1;
satur : natural :=1;
lpm_signed : BusArithm :=BusIsSigned
);
port (
xin : in std_logic_vector(width_inl+width_inr-1 downto 0);
yout : out std_logic_vector(width_outl+width_outr-1 downto 0)
);
end alt_dspbuilder_SBF;
architecture SBF_SYNTH of alt_dspbuilder_SBF is
signal youtround : std_logic_vector(width_inl+width_outr-1 downto 0);
signal youtroundc : std_logic_vector(width_outl+width_outr-1 downto 0);
signal xinextc : std_logic_vector(width_outl+width_inr-1 downto 0) ;
signal xin_int : std_logic_vector(width_inl+width_inr-1 downto 0);
begin
u0: alt_dspbuilder_sAltrPropagate generic map(QTB=>DSPBuilderQTB, QTB_PRODUCT => DSPBuilderProduct, QTB_VERSION => DSPBuilderVersion , width=> width_inl+width_inr)
port map (d => xin, r => xin_int);
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--(width_inl>=width_outl) and (width_inr>=width_outr)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
sbf_a:if (width_inl>=width_outl) and (width_inr>=width_outr) generate
gnsnr:if (round = 0) generate
gnsat:if (satur=0) generate
gl:for i in 0 to width_outl+width_outr-1 generate
yout(i) <= xin_int(i+width_inr-width_outr);
end generate ;
end generate gnsat;
gsat:if (satur>0) generate
gl:for i in 0 to width_inl+width_outr-1 generate
youtround(i) <= xin_int(i+width_inr-width_outr);
end generate ;
us:alt_dspbuilder_ASAT
generic map ( widthin => width_inl+width_outr,
widthout => width_outl+width_outr,
lpm_signed => lpm_signed)
port map ( xin => youtround,
yout => yout);
end generate gsat;
end generate ;
rnd:if (round>0)generate
ura:alt_dspbuilder_AROUND
generic map ( widthin => width_inl+width_inr,
widthout => width_inl+width_outr)
port map ( xin => xin_int,
yout => youtround);
gns:if satur=0 generate
yout(width_outl+width_outr-1 downto 0) <= youtround(width_outl+width_outr-1 downto 0);
end generate gns;
gs:if (satur>0) generate
us:alt_dspbuilder_ASAT
generic map ( widthin => width_inl+width_outr,
widthout => width_outl+width_outr,
lpm_signed => lpm_signed)
port map ( xin => youtround,
yout => yout
);
end generate gs;
end generate rnd;
end generate sbf_a;
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
-- (width_inl>width_outl) and (width_inr<width_outr)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
sbf_b:if (width_inl>=width_outl) and (width_inr<width_outr) generate
ns:if (satur=0) generate
gc:for i in 0 to width_outr-width_inr-1 generate
yout(i) <= '0';
end generate gc;
gl:for i in width_outr-width_inr to width_outl+width_outr-1 generate
yout(i) <= xin_int(i+width_inr-width_outr);
end generate ;
end generate ns ;
gs:if (satur>0) generate
gc:for i in 0 to width_outr-width_inr-1 generate
youtround(i) <= '0';
end generate gc;
gl:for i in width_outr-width_inr to width_inl+width_outr-1 generate
youtround(i) <= xin_int(i+width_inr-width_outr);
end generate ;
us:alt_dspbuilder_ASAT
generic map ( widthin => width_inl+width_outr,
widthout => width_outl+width_outr,
lpm_signed => lpm_signed)
port map ( xin => youtround,
yout => yout);
end generate gs ;
end generate sbf_b;
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
-- (width_inl<width_outl) and (width_inr>width_outr)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
sbf_c:if (width_inl<width_outl) and (width_inr>=width_outr) generate
gnsnr:if (round = 0) generate
gl:for i in 0 to width_inl+width_outr-1 generate
yout(i) <= xin_int(i+width_inr-width_outr);
end generate ;
gc:for i in width_inl+width_outr to width_outl+width_outr-1 generate
yout(i) <= xin_int( width_inl+width_inr-1);
end generate ;
end generate ;
rnd:if (round > 0) generate
xinextc(width_inl+width_inr-1 downto 0) <= xin_int(width_inl+width_inr-1 downto 0);
gxinextc:for i in width_inl+width_inr to width_outl+width_inr-1 generate
xinextc(i) <= xin_int(width_inl+width_inr-1);
end generate gxinextc;
urb:alt_dspbuilder_AROUND
generic map ( widthin => width_outl+width_inr,
widthout => width_outl+width_outr)
port map ( xin => xinextc,
yout => youtroundc);
yout <= youtroundc;
end generate rnd ;
end generate sbf_c;
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
-- (width_inl<width_outl) and (width_inr<width_outr)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------
sbf_d:if (width_inl<width_outl) and (width_inr<width_outr) generate
gl:for i in width_outr-width_inr to width_inl+width_outr-1 generate
yout(i) <= xin_int(i+width_inr-width_outr);
end generate gl;
gc:for i in 0 to width_outr-width_inr-1 generate
yout(i) <= '0';
end generate gc;
gcv:for i in width_inl+width_outr to width_outl+width_outr-1 generate
yout(i) <= xin_int( width_inl+width_inr-1);
end generate gcv;
end generate sbf_d;
end SBF_SYNTH;
|
mit
|
Given-Jiang/Binarization
|
tb_Binarization/hdl/alt_dspbuilder_multiplexer_GNCALBUTDR.vhd
|
12
|
1253
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_multiplexer_GNCALBUTDR is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
use_one_hot_select_bus : natural := 0;
width : positive := 24;
pipeline : natural := 0;
number_inputs : natural := 2);
port(
clock : in std_logic;
aclr : in std_logic;
sel : in std_logic_vector(0 downto 0);
result : out std_logic_vector(23 downto 0);
ena : in std_logic;
user_aclr : in std_logic;
in0 : in std_logic_vector(23 downto 0);
in1 : in std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_multiplexer_GNCALBUTDR is
signal data_muxin : std_logic_vector(47 downto 0);
Begin
data_muxin <= in1 & in0 ;
nto1Multiplexeri : alt_dspbuilder_sMuxAltr generic map (
lpm_pipeline =>0,
lpm_size => 2,
lpm_widths => 1 ,
lpm_width => 24 ,
SelOneHot => 0 )
port map (
clock => clock,
ena => ena,
user_aclr => user_aclr,
aclr => aclr,
data => data_muxin,
sel => sel,
result => result);
end architecture;
|
mit
|
Given-Jiang/Binarization
|
Binarization_dspbuilder/hdl/Binarization_GN.vhd
|
2
|
10406
|
-- Binarization_GN.vhd
-- Generated using ACDS version 13.1 162 at 2015.02.27.10:26:08
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Binarization_GN is
port (
Avalon_ST_Source_data : out std_logic_vector(23 downto 0); -- Avalon_ST_Source_data.wire
Avalon_ST_Sink_data : in std_logic_vector(23 downto 0) := (others => '0'); -- Avalon_ST_Sink_data.wire
Avalon_MM_Slave_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- Avalon_MM_Slave_writedata.wire
Avalon_ST_Sink_valid : in std_logic := '0'; -- Avalon_ST_Sink_valid.wire
Clock : in std_logic := '0'; -- Clock.clk
aclr : in std_logic := '0'; -- .reset_n
Avalon_ST_Sink_ready : out std_logic; -- Avalon_ST_Sink_ready.wire
Avalon_MM_Slave_write : in std_logic := '0'; -- Avalon_MM_Slave_write.wire
Avalon_MM_Slave_address : in std_logic_vector(1 downto 0) := (others => '0'); -- Avalon_MM_Slave_address.wire
Avalon_ST_Source_ready : in std_logic := '0'; -- Avalon_ST_Source_ready.wire
Avalon_ST_Source_valid : out std_logic; -- Avalon_ST_Source_valid.wire
Avalon_ST_Source_startofpacket : out std_logic; -- Avalon_ST_Source_startofpacket.wire
Avalon_ST_Sink_startofpacket : in std_logic := '0'; -- Avalon_ST_Sink_startofpacket.wire
Avalon_ST_Sink_endofpacket : in std_logic := '0'; -- Avalon_ST_Sink_endofpacket.wire
Avalon_ST_Source_endofpacket : out std_logic -- Avalon_ST_Source_endofpacket.wire
);
end entity Binarization_GN;
architecture rtl of Binarization_GN is
component alt_dspbuilder_clock_GNF343OQUJ is
port (
aclr : in std_logic := 'X'; -- reset
aclr_n : in std_logic := 'X'; -- reset_n
aclr_out : out std_logic; -- reset
clock : in std_logic := 'X'; -- clk
clock_out : out std_logic -- clk
);
end component alt_dspbuilder_clock_GNF343OQUJ;
component alt_dspbuilder_port_GNOC3SGKQJ is
port (
input : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(23 downto 0) -- wire
);
end component alt_dspbuilder_port_GNOC3SGKQJ;
component alt_dspbuilder_port_GN37ALZBS4 is
port (
input : in std_logic := 'X'; -- wire
output : out std_logic -- wire
);
end component alt_dspbuilder_port_GN37ALZBS4;
component Binarization_GN_Binarization_Binarization_Module is
port (
Clock : in std_logic := 'X'; -- clk
aclr : in std_logic := 'X'; -- reset
data_out : out std_logic_vector(23 downto 0); -- wire
addr : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire
eop : in std_logic := 'X'; -- wire
sop : in std_logic := 'X'; -- wire
writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
data_in : in std_logic_vector(23 downto 0) := (others => 'X'); -- wire
write : in std_logic := 'X' -- wire
);
end component Binarization_GN_Binarization_Binarization_Module;
component alt_dspbuilder_port_GN6TDLHAW6 is
port (
input : in std_logic_vector(1 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(1 downto 0) -- wire
);
end component alt_dspbuilder_port_GN6TDLHAW6;
component alt_dspbuilder_port_GNEPKLLZKY is
port (
input : in std_logic_vector(31 downto 0) := (others => 'X'); -- wire
output : out std_logic_vector(31 downto 0) -- wire
);
end component alt_dspbuilder_port_GNEPKLLZKY;
signal avalon_st_sink_valid_0_output_wire : std_logic; -- Avalon_ST_Sink_valid_0:output -> Avalon_ST_Source_valid_0:input
signal avalon_st_sink_startofpacket_0_output_wire : std_logic; -- Avalon_ST_Sink_startofpacket_0:output -> [Avalon_ST_Source_startofpacket_0:input, Binarization_Binarization_Module_0:sop]
signal avalon_st_sink_endofpacket_0_output_wire : std_logic; -- Avalon_ST_Sink_endofpacket_0:output -> [Avalon_ST_Source_endofpacket_0:input, Binarization_Binarization_Module_0:eop]
signal avalon_st_source_ready_0_output_wire : std_logic; -- Avalon_ST_Source_ready_0:output -> Avalon_ST_Sink_ready_0:input
signal avalon_mm_slave_address_0_output_wire : std_logic_vector(1 downto 0); -- Avalon_MM_Slave_address_0:output -> Binarization_Binarization_Module_0:addr
signal avalon_mm_slave_write_0_output_wire : std_logic; -- Avalon_MM_Slave_write_0:output -> Binarization_Binarization_Module_0:write
signal avalon_mm_slave_writedata_0_output_wire : std_logic_vector(31 downto 0); -- Avalon_MM_Slave_writedata_0:output -> Binarization_Binarization_Module_0:writedata
signal avalon_st_sink_data_0_output_wire : std_logic_vector(23 downto 0); -- Avalon_ST_Sink_data_0:output -> Binarization_Binarization_Module_0:data_in
signal binarization_binarization_module_0_data_out_wire : std_logic_vector(23 downto 0); -- Binarization_Binarization_Module_0:data_out -> Avalon_ST_Source_data_0:input
signal clock_0_clock_output_reset : std_logic; -- Clock_0:aclr_out -> Binarization_Binarization_Module_0:aclr
signal clock_0_clock_output_clk : std_logic; -- Clock_0:clock_out -> Binarization_Binarization_Module_0:Clock
begin
clock_0 : component alt_dspbuilder_clock_GNF343OQUJ
port map (
clock_out => clock_0_clock_output_clk, -- clock_output.clk
aclr_out => clock_0_clock_output_reset, -- .reset
clock => Clock, -- clock.clk
aclr_n => aclr -- .reset_n
);
avalon_st_sink_data_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => Avalon_ST_Sink_data, -- input.wire
output => avalon_st_sink_data_0_output_wire -- output.wire
);
avalon_st_sink_endofpacket_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => Avalon_ST_Sink_endofpacket, -- input.wire
output => avalon_st_sink_endofpacket_0_output_wire -- output.wire
);
binarization_binarization_module_0 : component Binarization_GN_Binarization_Binarization_Module
port map (
Clock => clock_0_clock_output_clk, -- Clock.clk
aclr => clock_0_clock_output_reset, -- .reset
data_out => binarization_binarization_module_0_data_out_wire, -- data_out.wire
addr => avalon_mm_slave_address_0_output_wire, -- addr.wire
eop => avalon_st_sink_endofpacket_0_output_wire, -- eop.wire
sop => avalon_st_sink_startofpacket_0_output_wire, -- sop.wire
writedata => avalon_mm_slave_writedata_0_output_wire, -- writedata.wire
data_in => avalon_st_sink_data_0_output_wire, -- data_in.wire
write => avalon_mm_slave_write_0_output_wire -- write.wire
);
avalon_mm_slave_address_0 : component alt_dspbuilder_port_GN6TDLHAW6
port map (
input => Avalon_MM_Slave_address, -- input.wire
output => avalon_mm_slave_address_0_output_wire -- output.wire
);
avalon_mm_slave_writedata_0 : component alt_dspbuilder_port_GNEPKLLZKY
port map (
input => Avalon_MM_Slave_writedata, -- input.wire
output => avalon_mm_slave_writedata_0_output_wire -- output.wire
);
avalon_st_source_valid_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => avalon_st_sink_valid_0_output_wire, -- input.wire
output => Avalon_ST_Source_valid -- output.wire
);
avalon_st_sink_valid_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => Avalon_ST_Sink_valid, -- input.wire
output => avalon_st_sink_valid_0_output_wire -- output.wire
);
avalon_st_source_endofpacket_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => avalon_st_sink_endofpacket_0_output_wire, -- input.wire
output => Avalon_ST_Source_endofpacket -- output.wire
);
avalon_st_source_startofpacket_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => avalon_st_sink_startofpacket_0_output_wire, -- input.wire
output => Avalon_ST_Source_startofpacket -- output.wire
);
avalon_st_source_ready_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => Avalon_ST_Source_ready, -- input.wire
output => avalon_st_source_ready_0_output_wire -- output.wire
);
avalon_mm_slave_write_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => Avalon_MM_Slave_write, -- input.wire
output => avalon_mm_slave_write_0_output_wire -- output.wire
);
avalon_st_sink_ready_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => avalon_st_source_ready_0_output_wire, -- input.wire
output => Avalon_ST_Sink_ready -- output.wire
);
avalon_st_sink_startofpacket_0 : component alt_dspbuilder_port_GN37ALZBS4
port map (
input => Avalon_ST_Sink_startofpacket, -- input.wire
output => avalon_st_sink_startofpacket_0_output_wire -- output.wire
);
avalon_st_source_data_0 : component alt_dspbuilder_port_GNOC3SGKQJ
port map (
input => binarization_binarization_module_0_data_out_wire, -- input.wire
output => Avalon_ST_Source_data -- output.wire
);
end architecture rtl; -- of Binarization_GN
|
mit
|
KaskMartin/Digiloogika_ALU
|
ALU_FPGA/toplevel.vhd
|
1
|
3598
|
----------------------------------------------------------------------------------
-- Home assignement in "Digitaalloogika ja -süsteemid" (http://priit.ati.ttu.ee/?page_id=2320)
-- ALU FPGA synthesis on Playground FPGA
-- (Playground FPGA toplevel module by Keijo Lass, Priit Ruberg)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity toplevel is
port(
clk: in std_logic; --clock in, 100MHz
JA: in std_logic_vector(7 downto 0); --JA port input
JB: in std_logic_vector(7 downto 0); --JB port input
JC: in std_logic_vector(7 downto 0); --JC port input
JD: in std_logic_vector(7 downto 0); --JD port input
LED: out std_logic_vector(7 downto 0)); --LEDs
end toplevel;
architecture RTL of toplevel is
--the component for PORTER is created
component PORTER is
Port(JA_P: in std_logic_vector(7 downto 0); --JA port input
JB_P: in std_logic_vector(7 downto 0); --JB port input
JC_P: in std_logic_vector(7 downto 0); --JC port input
-- JD_P: in std_logic_vector(7 downto 0); --JD port input
LED_P: out std_logic_vector(7 downto 0); --LEDs
a : out STD_LOGIC_VECTOR (3 downto 0); --4 bit input
b : out STD_LOGIC_VECTOR (3 downto 0); -- 4 bit input
op : out STD_LOGIC_VECTOR (1 downto 0);
o : in STD_LOGIC_VECTOR (3 downto 0));
end component;
--the component for first function is created
component func1 is
Port ( a, b : in STD_LOGIC_VECTOR (3 downto 0); --4 bit input
o : out STD_LOGIC_VECTOR (3 downto 0)); --4 bit output
end component;
--the component for second function is created
component func2 is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0); --4 bit input
o : out STD_LOGIC_VECTOR (3 downto 0)); --4 bit output
end component;
--the component for third function is created
component func3 is
Port ( a, b : in STD_LOGIC_VECTOR (3 downto 0); -- 4 bit input
o : out STD_LOGIC_VECTOR (3 downto 0)); --4 bit output
end component;
--the component for forth function is created
component func4 is
Port ( a, b : in STD_LOGIC_VECTOR (3 downto 0); -- 4 bit input
o : out STD_LOGIC_VECTOR (3 downto 0)); --4 bit output
end component;
--the component for mux is created
component mux is
Port (m_op : in STD_LOGIC_VECTOR (1 downto 0);
F1_in : in STD_LOGIC_VECTOR (3 downto 0); --4 bit input
F2_in : in STD_LOGIC_VECTOR (3 downto 0); --4 bit input
F3_in : in STD_LOGIC_VECTOR (3 downto 0); --4 bit input
F4_in : in STD_LOGIC_VECTOR (3 downto 0); --4 bit input
m_o : out STD_LOGIC_VECTOR (3 downto 0)); --4 bit output
end component;
signal a, b, o : STD_LOGIC_VECTOR (3 downto 0):="0000";
signal op : STD_LOGIC_VECTOR (1 downto 0):="00";
signal F1_out, F2_out, F3_out, F4_out : STD_LOGIC_VECTOR (3 downto 0):="0000";
begin --beginning of the architecture
--components are port mapped according to workinstructions: http://priit.ati.ttu.ee/?page_id=2320
PO : PORTER port map (JA_P => JA,
JB_P => JB,
JC_P => JC,
-- JD_P => JD,
LED_P => LED,
a => a,
b => b,
op => op,
o => o);
F1 : func1 port map (a => a,
b => b ,
o => F1_out);
F2 : func2 port map (a => a,
o => F2_out);
F3 : func3 port map (a => a,
b => b ,
o => F3_out);
F4 : func4 port map (a => a,
b => b,
o => F4_out);
MUX_tl : mux port map (m_op => op,
F1_in => F1_out,
F2_in => F2_out,
F3_in => F3_out,
F4_in => F4_out,
m_o => o);
end RTL;
|
mit
|
KaskMartin/Digiloogika_ALU
|
ALU_FPGA/func_3.vhdl
|
2
|
965
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
-- Fun3 = clr A, B (seada sõna A B-nda biti väärtuseks '0')
entity func3 is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0); --4 bit input
b : in STD_LOGIC_VECTOR (3 downto 0); -- 4 bit input
o : out STD_LOGIC_VECTOR (3 downto 0)); --4 bit output
end func3;
architecture design of func3 is
signal a_sign, b_sign, o_sign: signed(3 downto 0);
signal pos_sign: signed(1 downto 0);
begin
a_sign <= signed(a);
b_sign <= signed(b);
pos_sign <= b_sign(1 downto 0);
DISP_F3: process ( a_sign , o_sign , pos_sign )
begin
case pos_sign is
when "00" =>
o_sign <= ("1110" and a_sign);
when "01" =>
o_sign <= ("1101" and a_sign);
when "10" =>
o_sign <= ("1011" and a_sign);
when "11" =>
o_sign <= ("0111" and a_sign);
when others =>
o_sign <= a_sign;
end case;
end process DISP_F3;
o <= std_logic_vector(o_sign);
end design;
|
mit
|
Given-Jiang/Binarization
|
Binarization_dspbuilder/db/alt_dspbuilder_sdecoderaltr.vhd
|
17
|
2703
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
library lpm;
use lpm.lpm_components.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_sdecoderaltr is
generic
(
width : natural :=8;
pipeline : natural :=0;
decode : std_logic_vector :="00000000"
);
port
(
data : in std_logic_vector (width-1 downto 0);
clock : in std_logic;
aclr : in std_logic;
user_aclr : in std_logic;
sclr : in std_logic;
dec : out std_logic
);
end alt_dspbuilder_sdecoderaltr;
architecture syn of alt_dspbuilder_sdecoderaltr is
signal sdec : std_logic_vector(width-1 downto 0);
signal idec : std_logic;
signal aclr_i : std_logic;
begin
aclr_i <= aclr or user_aclr;
gw: if width=(decode'length) generate
idec <= '1' when data=decode else '0';
end generate gw;
gg: if width<decode'length generate
g:for i in 0 to width-1 generate
sdec(i) <= decode(i);
end generate g;
idec <= '1' when data=sdec else '0';
end generate gg;
gl: if width>decode'length generate
sdec(decode'length-1 downto 0) <= decode(decode'length-1 downto 0);
g:for i in decode'length to width-1 generate
sdec(i) <= sdec(decode'length-1);
end generate g;
idec <= '1' when data=sdec else '0';
end generate gl;
gcomb:if 0=pipeline generate
dec<=idec;
end generate gcomb;
greg:if 0<pipeline generate
process(clock,aclr_i)
begin
if aclr_i='1' then
dec<='0';
elsif clock'event and clock='1' then
if sclr='1' then
dec<='0';
else
dec<=idec;
end if;
end if;
end process;
end generate greg;
end syn;
|
mit
|
Given-Jiang/Binarization
|
tb_Binarization/altera_lnsim/altera_pll/_primary.vhd
|
5
|
26906
|
library verilog;
use verilog.vl_types.all;
entity altera_pll is
generic(
reference_clock_frequency: string := "0 ps";
fractional_vco_multiplier: string := "false";
pll_type : string := "General";
pll_subtype : string := "General";
number_of_clocks: integer := 1;
operation_mode : string := "internal feedback";
deserialization_factor: integer := 4;
data_rate : integer := 0;
sim_additional_refclk_cycles_to_lock: integer := 0;
output_clock_frequency0: string := "0 ps";
phase_shift0 : string := "0 ps";
duty_cycle0 : integer := 50;
output_clock_frequency1: string := "0 ps";
phase_shift1 : string := "0 ps";
duty_cycle1 : integer := 50;
output_clock_frequency2: string := "0 ps";
phase_shift2 : string := "0 ps";
duty_cycle2 : integer := 50;
output_clock_frequency3: string := "0 ps";
phase_shift3 : string := "0 ps";
duty_cycle3 : integer := 50;
output_clock_frequency4: string := "0 ps";
phase_shift4 : string := "0 ps";
duty_cycle4 : integer := 50;
output_clock_frequency5: string := "0 ps";
phase_shift5 : string := "0 ps";
duty_cycle5 : integer := 50;
output_clock_frequency6: string := "0 ps";
phase_shift6 : string := "0 ps";
duty_cycle6 : integer := 50;
output_clock_frequency7: string := "0 ps";
phase_shift7 : string := "0 ps";
duty_cycle7 : integer := 50;
output_clock_frequency8: string := "0 ps";
phase_shift8 : string := "0 ps";
duty_cycle8 : integer := 50;
output_clock_frequency9: string := "0 ps";
phase_shift9 : string := "0 ps";
duty_cycle9 : integer := 50;
output_clock_frequency10: string := "0 ps";
phase_shift10 : string := "0 ps";
duty_cycle10 : integer := 50;
output_clock_frequency11: string := "0 ps";
phase_shift11 : string := "0 ps";
duty_cycle11 : integer := 50;
output_clock_frequency12: string := "0 ps";
phase_shift12 : string := "0 ps";
duty_cycle12 : integer := 50;
output_clock_frequency13: string := "0 ps";
phase_shift13 : string := "0 ps";
duty_cycle13 : integer := 50;
output_clock_frequency14: string := "0 ps";
phase_shift14 : string := "0 ps";
duty_cycle14 : integer := 50;
output_clock_frequency15: string := "0 ps";
phase_shift15 : string := "0 ps";
duty_cycle15 : integer := 50;
output_clock_frequency16: string := "0 ps";
phase_shift16 : string := "0 ps";
duty_cycle16 : integer := 50;
output_clock_frequency17: string := "0 ps";
phase_shift17 : string := "0 ps";
duty_cycle17 : integer := 50;
m_cnt_hi_div : integer := 1;
m_cnt_lo_div : integer := 1;
m_cnt_bypass_en : string := "false";
m_cnt_odd_div_duty_en: string := "false";
n_cnt_hi_div : integer := 1;
n_cnt_lo_div : integer := 1;
n_cnt_bypass_en : string := "false";
n_cnt_odd_div_duty_en: string := "false";
c_cnt_hi_div0 : integer := 1;
c_cnt_lo_div0 : integer := 1;
c_cnt_bypass_en0: string := "false";
c_cnt_in_src0 : string := "ph_mux_clk";
c_cnt_odd_div_duty_en0: string := "false";
c_cnt_prst0 : integer := 1;
c_cnt_ph_mux_prst0: integer := 0;
c_cnt_hi_div1 : integer := 1;
c_cnt_lo_div1 : integer := 1;
c_cnt_bypass_en1: string := "false";
c_cnt_in_src1 : string := "ph_mux_clk";
c_cnt_odd_div_duty_en1: string := "false";
c_cnt_prst1 : integer := 1;
c_cnt_ph_mux_prst1: integer := 0;
c_cnt_hi_div2 : integer := 1;
c_cnt_lo_div2 : integer := 1;
c_cnt_bypass_en2: string := "false";
c_cnt_in_src2 : string := "ph_mux_clk";
c_cnt_odd_div_duty_en2: string := "false";
c_cnt_prst2 : integer := 1;
c_cnt_ph_mux_prst2: integer := 0;
c_cnt_hi_div3 : integer := 1;
c_cnt_lo_div3 : integer := 1;
c_cnt_bypass_en3: string := "false";
c_cnt_in_src3 : string := "ph_mux_clk";
c_cnt_odd_div_duty_en3: string := "false";
c_cnt_prst3 : integer := 1;
c_cnt_ph_mux_prst3: integer := 0;
c_cnt_hi_div4 : integer := 1;
c_cnt_lo_div4 : integer := 1;
c_cnt_bypass_en4: string := "false";
c_cnt_in_src4 : string := "ph_mux_clk";
c_cnt_odd_div_duty_en4: string := "false";
c_cnt_prst4 : integer := 1;
c_cnt_ph_mux_prst4: integer := 0;
c_cnt_hi_div5 : integer := 1;
c_cnt_lo_div5 : integer := 1;
c_cnt_bypass_en5: string := "false";
c_cnt_in_src5 : string := "ph_mux_clk";
c_cnt_odd_div_duty_en5: string := "false";
c_cnt_prst5 : integer := 1;
c_cnt_ph_mux_prst5: integer := 0;
c_cnt_hi_div6 : integer := 1;
c_cnt_lo_div6 : integer := 1;
c_cnt_bypass_en6: string := "false";
c_cnt_in_src6 : string := "ph_mux_clk";
c_cnt_odd_div_duty_en6: string := "false";
c_cnt_prst6 : integer := 1;
c_cnt_ph_mux_prst6: integer := 0;
c_cnt_hi_div7 : integer := 1;
c_cnt_lo_div7 : integer := 1;
c_cnt_bypass_en7: string := "false";
c_cnt_in_src7 : string := "ph_mux_clk";
c_cnt_odd_div_duty_en7: string := "false";
c_cnt_prst7 : integer := 1;
c_cnt_ph_mux_prst7: integer := 0;
c_cnt_hi_div8 : integer := 1;
c_cnt_lo_div8 : integer := 1;
c_cnt_bypass_en8: string := "false";
c_cnt_in_src8 : string := "ph_mux_clk";
c_cnt_odd_div_duty_en8: string := "false";
c_cnt_prst8 : integer := 1;
c_cnt_ph_mux_prst8: integer := 0;
c_cnt_hi_div9 : integer := 1;
c_cnt_lo_div9 : integer := 1;
c_cnt_bypass_en9: string := "false";
c_cnt_in_src9 : string := "ph_mux_clk";
c_cnt_odd_div_duty_en9: string := "false";
c_cnt_prst9 : integer := 1;
c_cnt_ph_mux_prst9: integer := 0;
c_cnt_hi_div10 : integer := 1;
c_cnt_lo_div10 : integer := 1;
c_cnt_bypass_en10: string := "false";
c_cnt_in_src10 : string := "ph_mux_clk";
c_cnt_odd_div_duty_en10: string := "false";
c_cnt_prst10 : integer := 1;
c_cnt_ph_mux_prst10: integer := 0;
c_cnt_hi_div11 : integer := 1;
c_cnt_lo_div11 : integer := 1;
c_cnt_bypass_en11: string := "false";
c_cnt_in_src11 : string := "ph_mux_clk";
c_cnt_odd_div_duty_en11: string := "false";
c_cnt_prst11 : integer := 1;
c_cnt_ph_mux_prst11: integer := 0;
c_cnt_hi_div12 : integer := 1;
c_cnt_lo_div12 : integer := 1;
c_cnt_bypass_en12: string := "false";
c_cnt_in_src12 : string := "ph_mux_clk";
c_cnt_odd_div_duty_en12: string := "false";
c_cnt_prst12 : integer := 1;
c_cnt_ph_mux_prst12: integer := 0;
c_cnt_hi_div13 : integer := 1;
c_cnt_lo_div13 : integer := 1;
c_cnt_bypass_en13: string := "false";
c_cnt_in_src13 : string := "ph_mux_clk";
c_cnt_odd_div_duty_en13: string := "false";
c_cnt_prst13 : integer := 1;
c_cnt_ph_mux_prst13: integer := 0;
c_cnt_hi_div14 : integer := 1;
c_cnt_lo_div14 : integer := 1;
c_cnt_bypass_en14: string := "false";
c_cnt_in_src14 : string := "ph_mux_clk";
c_cnt_odd_div_duty_en14: string := "false";
c_cnt_prst14 : integer := 1;
c_cnt_ph_mux_prst14: integer := 0;
c_cnt_hi_div15 : integer := 1;
c_cnt_lo_div15 : integer := 1;
c_cnt_bypass_en15: string := "false";
c_cnt_in_src15 : string := "ph_mux_clk";
c_cnt_odd_div_duty_en15: string := "false";
c_cnt_prst15 : integer := 1;
c_cnt_ph_mux_prst15: integer := 0;
c_cnt_hi_div16 : integer := 1;
c_cnt_lo_div16 : integer := 1;
c_cnt_bypass_en16: string := "false";
c_cnt_in_src16 : string := "ph_mux_clk";
c_cnt_odd_div_duty_en16: string := "false";
c_cnt_prst16 : integer := 1;
c_cnt_ph_mux_prst16: integer := 0;
c_cnt_hi_div17 : integer := 1;
c_cnt_lo_div17 : integer := 1;
c_cnt_bypass_en17: string := "false";
c_cnt_in_src17 : string := "ph_mux_clk";
c_cnt_odd_div_duty_en17: string := "false";
c_cnt_prst17 : integer := 1;
c_cnt_ph_mux_prst17: integer := 0;
pll_vco_div : integer := 1;
pll_output_clk_frequency: string := "0 MHz";
pll_cp_current : integer := 0;
pll_bwctrl : integer := 0;
pll_fractional_division: integer := 1;
pll_fractional_cout: integer := 24;
pll_dsm_out_sel : string := "1st_order";
mimic_fbclk_type: string := "gclk";
pll_fbclk_mux_1 : string := "glb";
pll_fbclk_mux_2 : string := "fb_1";
pll_m_cnt_in_src: string := "ph_mux_clk";
pll_vcoph_div : integer := 1;
refclk1_frequency: string := "0 MHz";
pll_clkin_0_src : string := "clk_0";
pll_clkin_1_src : string := "clk_0";
pll_clk_loss_sw_en: string := "false";
pll_auto_clk_sw_en: string := "false";
pll_manu_clk_sw_en: string := "false";
pll_clk_sw_dly : integer := 0
);
port(
refclk : in vl_logic;
refclk1 : in vl_logic;
fbclk : in vl_logic;
rst : in vl_logic;
phase_en : in vl_logic;
updn : in vl_logic;
num_phase_shifts: in vl_logic_vector(2 downto 0);
scanclk : in vl_logic;
cntsel : in vl_logic_vector(4 downto 0);
reconfig_to_pll : in vl_logic_vector(63 downto 0);
extswitch : in vl_logic;
adjpllin : in vl_logic;
cclk : in vl_logic;
outclk : out vl_logic_vector;
fboutclk : out vl_logic;
locked : out vl_logic;
phase_done : out vl_logic;
reconfig_from_pll: out vl_logic_vector(63 downto 0);
activeclk : out vl_logic;
clkbad : out vl_logic_vector(1 downto 0);
phout : out vl_logic_vector(7 downto 0);
lvds_clk : out vl_logic_vector(1 downto 0);
loaden : out vl_logic_vector(1 downto 0);
cascade_out : out vl_logic_vector;
zdbfbclk : inout vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of reference_clock_frequency : constant is 1;
attribute mti_svvh_generic_type of fractional_vco_multiplier : constant is 1;
attribute mti_svvh_generic_type of pll_type : constant is 1;
attribute mti_svvh_generic_type of pll_subtype : constant is 1;
attribute mti_svvh_generic_type of number_of_clocks : constant is 1;
attribute mti_svvh_generic_type of operation_mode : constant is 1;
attribute mti_svvh_generic_type of deserialization_factor : constant is 1;
attribute mti_svvh_generic_type of data_rate : constant is 1;
attribute mti_svvh_generic_type of sim_additional_refclk_cycles_to_lock : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency0 : constant is 1;
attribute mti_svvh_generic_type of phase_shift0 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle0 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency1 : constant is 1;
attribute mti_svvh_generic_type of phase_shift1 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle1 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency2 : constant is 1;
attribute mti_svvh_generic_type of phase_shift2 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle2 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency3 : constant is 1;
attribute mti_svvh_generic_type of phase_shift3 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle3 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency4 : constant is 1;
attribute mti_svvh_generic_type of phase_shift4 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle4 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency5 : constant is 1;
attribute mti_svvh_generic_type of phase_shift5 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle5 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency6 : constant is 1;
attribute mti_svvh_generic_type of phase_shift6 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle6 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency7 : constant is 1;
attribute mti_svvh_generic_type of phase_shift7 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle7 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency8 : constant is 1;
attribute mti_svvh_generic_type of phase_shift8 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle8 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency9 : constant is 1;
attribute mti_svvh_generic_type of phase_shift9 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle9 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency10 : constant is 1;
attribute mti_svvh_generic_type of phase_shift10 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle10 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency11 : constant is 1;
attribute mti_svvh_generic_type of phase_shift11 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle11 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency12 : constant is 1;
attribute mti_svvh_generic_type of phase_shift12 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle12 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency13 : constant is 1;
attribute mti_svvh_generic_type of phase_shift13 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle13 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency14 : constant is 1;
attribute mti_svvh_generic_type of phase_shift14 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle14 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency15 : constant is 1;
attribute mti_svvh_generic_type of phase_shift15 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle15 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency16 : constant is 1;
attribute mti_svvh_generic_type of phase_shift16 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle16 : constant is 1;
attribute mti_svvh_generic_type of output_clock_frequency17 : constant is 1;
attribute mti_svvh_generic_type of phase_shift17 : constant is 1;
attribute mti_svvh_generic_type of duty_cycle17 : constant is 1;
attribute mti_svvh_generic_type of m_cnt_hi_div : constant is 1;
attribute mti_svvh_generic_type of m_cnt_lo_div : constant is 1;
attribute mti_svvh_generic_type of m_cnt_bypass_en : constant is 1;
attribute mti_svvh_generic_type of m_cnt_odd_div_duty_en : constant is 1;
attribute mti_svvh_generic_type of n_cnt_hi_div : constant is 1;
attribute mti_svvh_generic_type of n_cnt_lo_div : constant is 1;
attribute mti_svvh_generic_type of n_cnt_bypass_en : constant is 1;
attribute mti_svvh_generic_type of n_cnt_odd_div_duty_en : constant is 1;
attribute mti_svvh_generic_type of c_cnt_hi_div0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_lo_div0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_bypass_en0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_odd_div_duty_en0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst0 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_hi_div1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_lo_div1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_bypass_en1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_odd_div_duty_en1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst1 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_hi_div2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_lo_div2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_bypass_en2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_odd_div_duty_en2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst2 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_hi_div3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_lo_div3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_bypass_en3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_odd_div_duty_en3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst3 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_hi_div4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_lo_div4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_bypass_en4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_odd_div_duty_en4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst4 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_hi_div5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_lo_div5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_bypass_en5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_odd_div_duty_en5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst5 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_hi_div6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_lo_div6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_bypass_en6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_odd_div_duty_en6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst6 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_hi_div7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_lo_div7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_bypass_en7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_odd_div_duty_en7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst7 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_hi_div8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_lo_div8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_bypass_en8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_odd_div_duty_en8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst8 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_hi_div9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_lo_div9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_bypass_en9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_odd_div_duty_en9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst9 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_hi_div10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_lo_div10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_bypass_en10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_odd_div_duty_en10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst10 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_hi_div11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_lo_div11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_bypass_en11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_odd_div_duty_en11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst11 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_hi_div12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_lo_div12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_bypass_en12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_odd_div_duty_en12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst12 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_hi_div13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_lo_div13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_bypass_en13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_odd_div_duty_en13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst13 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_hi_div14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_lo_div14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_bypass_en14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_odd_div_duty_en14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst14 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_hi_div15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_lo_div15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_bypass_en15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_odd_div_duty_en15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst15 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_hi_div16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_lo_div16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_bypass_en16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_odd_div_duty_en16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst16 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_hi_div17 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_lo_div17 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_bypass_en17 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_in_src17 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_odd_div_duty_en17 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_prst17 : constant is 1;
attribute mti_svvh_generic_type of c_cnt_ph_mux_prst17 : constant is 1;
attribute mti_svvh_generic_type of pll_vco_div : constant is 1;
attribute mti_svvh_generic_type of pll_output_clk_frequency : constant is 1;
attribute mti_svvh_generic_type of pll_cp_current : constant is 1;
attribute mti_svvh_generic_type of pll_bwctrl : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_division : constant is 1;
attribute mti_svvh_generic_type of pll_fractional_cout : constant is 1;
attribute mti_svvh_generic_type of pll_dsm_out_sel : constant is 1;
attribute mti_svvh_generic_type of mimic_fbclk_type : constant is 1;
attribute mti_svvh_generic_type of pll_fbclk_mux_1 : constant is 1;
attribute mti_svvh_generic_type of pll_fbclk_mux_2 : constant is 1;
attribute mti_svvh_generic_type of pll_m_cnt_in_src : constant is 1;
attribute mti_svvh_generic_type of pll_vcoph_div : constant is 1;
attribute mti_svvh_generic_type of refclk1_frequency : constant is 1;
attribute mti_svvh_generic_type of pll_clkin_0_src : constant is 1;
attribute mti_svvh_generic_type of pll_clkin_1_src : constant is 1;
attribute mti_svvh_generic_type of pll_clk_loss_sw_en : constant is 1;
attribute mti_svvh_generic_type of pll_auto_clk_sw_en : constant is 1;
attribute mti_svvh_generic_type of pll_manu_clk_sw_en : constant is 1;
attribute mti_svvh_generic_type of pll_clk_sw_dly : constant is 1;
end altera_pll;
|
mit
|
MrDoomBringer/DSD-Labs
|
Lab 9/BCD_to_sevenseg.vhd
|
3
|
7271
|
-- BCD display for hex displays
-- (c) Cliff Chapman 2013
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_signed.ALL;
-- Seven segment display output
--
ENTITY sevenseg_bcd_display IS
port (
-- Input value to display
R : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
-- Hex/Dec display select
S : IN STD_LOGIC;
-- sevenseg outputs
HEX0 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) := "1111111";
HEX1 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) := "1111111";
HEX2 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) := "1111111"
);
END sevenseg_bcd_display;
ARCHITECTURE display OF sevenseg_bcd_display IS
-- Hex output displays, customized for Altera DE2 board. May require
-- redefinition for different board setups.
CONSTANT hex_blk : STD_LOGIC_VECTOR (6 DOWNTO 0) := "1111111";
CONSTANT hex_neg : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0111111";
CONSTANT hex_zer : STD_LOGIC_VECTOR (6 DOWNTO 0) := "1000000";
CONSTANT hex_one : STD_LOGIC_VECTOR (6 DOWNTO 0) := "1111001";
CONSTANT hex_two : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0100100";
CONSTANT hex_thr : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0110000";
CONSTANT hex_fou : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0011001";
CONSTANT hex_fiv : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0010010";
CONSTANT hex_six : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0000010";
CONSTANT hex_sev : STD_LOGIC_VECTOR (6 DOWNTO 0) := "1111000";
CONSTANT hex_eig : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0000000";
CONSTANT hex_nin : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0011000";
CONSTANT hex_0xa : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0001000";
CONSTANT hex_0xb : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0000011";
CONSTANT hex_0xc : STD_LOGIC_VECTOR (6 DOWNTO 0) := "1000110";
CONSTANT hex_0xd : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0100001";
CONSTANT hex_0xe : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0000110";
CONSTANT hex_0xf : STD_LOGIC_VECTOR (6 DOWNTO 0) := "0001110";
-- Internal buffer signals for display select
SIGNAL HEX0_buff_hex : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL HEX1_buff_hex : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL HEX2_buff_hex : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL HEX0_buff_dec : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL HEX1_buff_dec : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL HEX2_buff_dec : STD_LOGIC_VECTOR (6 DOWNTO 0);
BEGIN
-- Generate a hex display
display_hex : PROCESS (R)
ALIAS high_bit : STD_LOGIC_VECTOR (3 DOWNTO 0) IS R (7 DOWNTO 4);
ALIAS low_bit : STD_LOGIC_VECTOR (3 DOWNTO 0) IS R (3 DOWNTO 0);
BEGIN
CASE high_bit IS
WHEN "0000" => HEX1_buff_hex <= hex_zer;
WHEN "0001" => HEX1_buff_hex <= hex_one;
WHEN "0010" => HEX1_buff_hex <= hex_two;
WHEN "0011" => HEX1_buff_hex <= hex_thr;
WHEN "0100" => HEX1_buff_hex <= hex_fou;
WHEN "0101" => HEX1_buff_hex <= hex_fiv;
WHEN "0110" => HEX1_buff_hex <= hex_six;
WHEN "0111" => HEX1_buff_hex <= hex_sev;
WHEN "1000" => HEX1_buff_hex <= hex_eig;
WHEN "1001" => HEX1_buff_hex <= hex_nin;
WHEN "1010" => HEX1_buff_hex <= hex_0xa;
WHEN "1011" => HEX1_buff_hex <= hex_0xb;
WHEN "1100" => HEX1_buff_hex <= hex_0xc;
WHEN "1101" => HEX1_buff_hex <= hex_0xd;
WHEN "1110" => HEX1_buff_hex <= hex_0xe;
WHEN "1111" => HEX1_buff_hex <= hex_0xf;
WHEN OTHERS => HEX1_buff_hex <= hex_blk;
END CASE;
CASE low_bit IS
WHEN "0000" => HEX2_buff_hex <= hex_zer;
WHEN "0001" => HEX2_buff_hex <= hex_one;
WHEN "0010" => HEX2_buff_hex <= hex_two;
WHEN "0011" => HEX2_buff_hex <= hex_thr;
WHEN "0100" => HEX2_buff_hex <= hex_fou;
WHEN "0101" => HEX2_buff_hex <= hex_fiv;
WHEN "0110" => HEX2_buff_hex <= hex_six;
WHEN "0111" => HEX2_buff_hex <= hex_sev;
WHEN "1000" => HEX2_buff_hex <= hex_eig;
WHEN "1001" => HEX2_buff_hex <= hex_nin;
WHEN "1010" => HEX2_buff_hex <= hex_0xa;
WHEN "1011" => HEX2_buff_hex <= hex_0xb;
WHEN "1100" => HEX2_buff_hex <= hex_0xc;
WHEN "1101" => HEX2_buff_hex <= hex_0xd;
WHEN "1110" => HEX2_buff_hex <= hex_0xe;
WHEN "1111" => HEX2_buff_hex <= hex_0xf;
WHEN OTHERS => HEX2_buff_hex <= hex_blk;
END CASE;
END PROCESS display_hex;
-- Generate a decimal display
display_dec: PROCESS (R)
ALIAS sign_bit : STD_LOGIC IS R (7);
VARIABLE r_lower: STD_LOGIC_VECTOR (7 DOWNTO 0);
VARIABLE r_buff : STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
-- Select value to work off of
IF (sign_bit='1') THEN
HEX0_buff_dec <= hex_neg;
r_buff := (NOT(R) + "00000001");
ELSIF (sign_bit='0') THEN
HEX0_buff_dec <= hex_blk;
r_buff := R;
ELSE
HEX0_buff_dec <= hex_blk;
r_buff := "00000000";
END IF;
-- Display higher digit
IF (r_buff >= "00000000" AND r_buff < "00001010") THEN -- Within 0-9
HEX1_buff_dec <= hex_zer;
r_lower := r_buff;
ELSIF (r_buff >= "00001010" AND r_buff < "00010100") THEN -- Within 10-19
HEX1_buff_dec <= hex_one;
r_lower := r_buff - "00001010";
ELSIF (r_buff >= "00010100" AND r_buff < "00011110") THEN -- Within 20-29
HEX1_buff_dec <= hex_two;
r_lower := r_buff - "00010100";
ELSIF (r_buff >= "00011110" AND r_buff < "00101000") THEN -- Within 30-39
HEX1_buff_dec <= hex_thr;
r_lower := r_buff - "00011110";
ELSIF (r_buff >= "00101000" AND r_buff < "00110010") THEN -- Within 40-49
HEX1_buff_dec <= hex_fou;
r_lower := r_buff - "00101000";
ELSIF (r_buff >= "00110010" AND r_buff < "00111100") THEN -- Within 50-59
HEX1_buff_dec <= hex_fiv;
r_lower := r_buff - "00110010";
ELSIF (r_buff >= "00111100" AND r_buff < "01000110") THEN -- Within 60-69
HEX1_buff_dec <= hex_six;
r_lower := r_buff - "00111100";
ELSIF (r_buff >= "01000110" AND r_buff < "01010000") THEN -- Within 70-79
HEX1_buff_dec <= hex_sev;
r_lower := r_buff - "01000110";
ELSIF (r_buff >= "01010000" AND r_buff < "01011010") THEN -- Within 80-89
HEX1_buff_dec <= hex_eig;
r_lower := r_buff - "01010000";
ELSIF (r_buff >= "01011010" AND r_buff < "01100100") THEN -- Within 90-99
HEX1_buff_dec <= hex_nin;
r_lower := r_buff - "01011010";
ELSE -- 99 is the highest value we can reliably display. Higher is out of range
HEX1_buff_dec <= hex_neg;
r_lower := "11111111";
END IF;
-- Display lower digit
CASE r_lower IS
WHEN "00000000" => HEX2_buff_dec <= hex_zer;
WHEN "00000001" => HEX2_buff_dec <= hex_one;
WHEN "00000010" => HEX2_buff_dec <= hex_two;
WHEN "00000011" => HEX2_buff_dec <= hex_thr;
WHEN "00000100" => HEX2_buff_dec <= hex_fou;
WHEN "00000101" => HEX2_buff_dec <= hex_fiv;
WHEN "00000110" => HEX2_buff_dec <= hex_six;
WHEN "00000111" => HEX2_buff_dec <= hex_sev;
WHEN "00001000" => HEX2_buff_dec <= hex_eig;
WHEN "00001001" => HEX2_buff_dec <= hex_nin;
WHEN "11111111" => HEX2_buff_dec <= hex_neg; -- Out of range
WHEN OTHERS => HEX2_buff_dec <= hex_zer;
END CASE;
END PROCESS display_dec;
-- Select display type for output
select_display : PROCESS (S, HEX0_buff_hex, HEX1_buff_hex, HEX2_buff_hex, HEX0_buff_dec, HEX1_buff_dec, HEX2_buff_dec)
BEGIN
IF (s = '0') THEN
HEX2 <= hex_blk;
HEX1 <= HEX1_buff_hex;
HEX0 <= HEX2_buff_hex;
ELSIF (s = '1') THEN
HEX2 <= HEX0_buff_dec;
HEX1 <= HEX1_buff_dec;
HEX0 <= HEX2_buff_dec;
ELSE
HEX2 <= hex_blk;
HEX1 <= hex_blk;
HEX0 <= hex_blk;
END IF;
END PROCESS select_display;
END display;
|
mit
|
Given-Jiang/Binarization
|
tb_Binarization/hdl/alt_dspbuilder_cast_GNSB3OXIQS.vhd
|
16
|
853
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GNSB3OXIQS is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(0 downto 0);
output : out std_logic);
end entity;
architecture rtl of alt_dspbuilder_cast_GNSB3OXIQS is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 1 + 1 ,
width_inr=> 0,
width_outl=> 1,
width_outr=> 0,
lpm_signed=> BusIsUnsigned ,
round=> round,
satur=> saturate)
port map (
xin(0 downto 0) => input,
xin(1) => '0', yout(0) => output
);
end architecture;
|
mit
|
Given-Jiang/Binarization
|
tb_Binarization/altera_lnsim/altera_syncram/_primary.vhd
|
5
|
9140
|
library verilog;
use verilog.vl_types.all;
entity altera_syncram is
generic(
width_a : integer := 1;
widthad_a : integer := 1;
numwords_a : integer := 0;
outdata_reg_a : string := "UNREGISTERED";
address_aclr_a : string := "NONE";
outdata_aclr_a : string := "NONE";
indata_aclr_a : string := "NONE";
wrcontrol_aclr_a: string := "NONE";
byteena_aclr_a : string := "NONE";
width_byteena_a : integer := 1;
width_b : integer := 1;
widthad_b : integer := 1;
numwords_b : integer := 0;
rdcontrol_reg_b : string := "CLOCK1";
address_reg_b : string := "CLOCK1";
outdata_reg_b : string := "UNREGISTERED";
outdata_aclr_b : string := "NONE";
rdcontrol_aclr_b: string := "NONE";
indata_reg_b : string := "CLOCK1";
byteena_reg_b : string := "CLOCK1";
indata_aclr_b : string := "NONE";
wrcontrol_aclr_b: string := "NONE";
address_aclr_b : string := "NONE";
byteena_aclr_b : string := "NONE";
width_byteena_b : integer := 1;
clock_enable_input_a: string := "NORMAL";
clock_enable_output_a: string := "NORMAL";
clock_enable_input_b: string := "NORMAL";
clock_enable_output_b: string := "NORMAL";
clock_enable_core_a: string := "USE_INPUT_CLKEN";
clock_enable_core_b: string := "USE_INPUT_CLKEN";
read_during_write_mode_port_a: string := "NEW_DATA_NO_NBE_READ";
read_during_write_mode_port_b: string := "NEW_DATA_NO_NBE_READ";
read_during_write_mode_mixed_ports: string := "DONT_CARE";
enable_ecc : string := "FALSE";
width_eccstatus : integer := 3;
ecc_pipeline_stage_enabled: string := "FALSE";
operation_mode : string := "BIDIR_DUAL_PORT";
byte_size : integer := 0;
ram_block_type : string := "AUTO";
init_file : string := "UNUSED";
init_file_layout: string := "UNUSED";
maximum_depth : integer := 0;
intended_device_family: string := "Stratix V";
lpm_hint : string := "UNUSED";
lpm_type : string := "altsyncram";
implement_in_les: string := "OFF";
power_up_uninitialized: string := "FALSE";
sim_show_memory_data_in_port_b_layout: string := "OFF";
is_lutram : vl_notype;
is_bidir_and_wrcontrol_addb_clk0: vl_notype;
is_bidir_and_wrcontrol_addb_clk1: vl_notype;
dual_port_addreg_b_clk0: vl_notype;
dual_port_addreg_b_clk1: vl_notype;
i_byte_size_tmp : vl_notype;
i_lutram_read : vl_notype;
enable_mem_data_b_reading: vl_notype;
wrcontrol_wraddress_reg_b: vl_notype;
is_write_on_positive_edge: integer := 1;
lutram_single_port_fast_read: vl_notype;
lutram_dual_port_fast_read: vl_notype;
s3_address_aclr_a: vl_notype;
s3_address_aclr_b: vl_notype;
i_address_aclr_family_a: vl_notype;
i_address_aclr_family_b: vl_notype
);
port(
wren_a : in vl_logic;
wren_b : in vl_logic;
rden_a : in vl_logic;
rden_b : in vl_logic;
data_a : in vl_logic_vector;
data_b : in vl_logic_vector;
address_a : in vl_logic_vector;
address_b : in vl_logic_vector;
clock0 : in vl_logic;
clock1 : in vl_logic;
clocken0 : in vl_logic;
clocken1 : in vl_logic;
clocken2 : in vl_logic;
clocken3 : in vl_logic;
aclr0 : in vl_logic;
aclr1 : in vl_logic;
byteena_a : in vl_logic_vector;
byteena_b : in vl_logic_vector;
addressstall_a : in vl_logic;
addressstall_b : in vl_logic;
q_a : out vl_logic_vector;
q_b : out vl_logic_vector;
eccstatus : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of width_a : constant is 1;
attribute mti_svvh_generic_type of widthad_a : constant is 1;
attribute mti_svvh_generic_type of numwords_a : constant is 1;
attribute mti_svvh_generic_type of outdata_reg_a : constant is 1;
attribute mti_svvh_generic_type of address_aclr_a : constant is 1;
attribute mti_svvh_generic_type of outdata_aclr_a : constant is 1;
attribute mti_svvh_generic_type of indata_aclr_a : constant is 1;
attribute mti_svvh_generic_type of wrcontrol_aclr_a : constant is 1;
attribute mti_svvh_generic_type of byteena_aclr_a : constant is 1;
attribute mti_svvh_generic_type of width_byteena_a : constant is 1;
attribute mti_svvh_generic_type of width_b : constant is 1;
attribute mti_svvh_generic_type of widthad_b : constant is 1;
attribute mti_svvh_generic_type of numwords_b : constant is 1;
attribute mti_svvh_generic_type of rdcontrol_reg_b : constant is 1;
attribute mti_svvh_generic_type of address_reg_b : constant is 1;
attribute mti_svvh_generic_type of outdata_reg_b : constant is 1;
attribute mti_svvh_generic_type of outdata_aclr_b : constant is 1;
attribute mti_svvh_generic_type of rdcontrol_aclr_b : constant is 1;
attribute mti_svvh_generic_type of indata_reg_b : constant is 1;
attribute mti_svvh_generic_type of byteena_reg_b : constant is 1;
attribute mti_svvh_generic_type of indata_aclr_b : constant is 1;
attribute mti_svvh_generic_type of wrcontrol_aclr_b : constant is 1;
attribute mti_svvh_generic_type of address_aclr_b : constant is 1;
attribute mti_svvh_generic_type of byteena_aclr_b : constant is 1;
attribute mti_svvh_generic_type of width_byteena_b : constant is 1;
attribute mti_svvh_generic_type of clock_enable_input_a : constant is 1;
attribute mti_svvh_generic_type of clock_enable_output_a : constant is 1;
attribute mti_svvh_generic_type of clock_enable_input_b : constant is 1;
attribute mti_svvh_generic_type of clock_enable_output_b : constant is 1;
attribute mti_svvh_generic_type of clock_enable_core_a : constant is 1;
attribute mti_svvh_generic_type of clock_enable_core_b : constant is 1;
attribute mti_svvh_generic_type of read_during_write_mode_port_a : constant is 1;
attribute mti_svvh_generic_type of read_during_write_mode_port_b : constant is 1;
attribute mti_svvh_generic_type of read_during_write_mode_mixed_ports : constant is 1;
attribute mti_svvh_generic_type of enable_ecc : constant is 1;
attribute mti_svvh_generic_type of width_eccstatus : constant is 1;
attribute mti_svvh_generic_type of ecc_pipeline_stage_enabled : constant is 1;
attribute mti_svvh_generic_type of operation_mode : constant is 1;
attribute mti_svvh_generic_type of byte_size : constant is 1;
attribute mti_svvh_generic_type of ram_block_type : constant is 1;
attribute mti_svvh_generic_type of init_file : constant is 1;
attribute mti_svvh_generic_type of init_file_layout : constant is 1;
attribute mti_svvh_generic_type of maximum_depth : constant is 1;
attribute mti_svvh_generic_type of intended_device_family : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of implement_in_les : constant is 1;
attribute mti_svvh_generic_type of power_up_uninitialized : constant is 1;
attribute mti_svvh_generic_type of sim_show_memory_data_in_port_b_layout : constant is 1;
attribute mti_svvh_generic_type of is_lutram : constant is 3;
attribute mti_svvh_generic_type of is_bidir_and_wrcontrol_addb_clk0 : constant is 3;
attribute mti_svvh_generic_type of is_bidir_and_wrcontrol_addb_clk1 : constant is 3;
attribute mti_svvh_generic_type of dual_port_addreg_b_clk0 : constant is 3;
attribute mti_svvh_generic_type of dual_port_addreg_b_clk1 : constant is 3;
attribute mti_svvh_generic_type of i_byte_size_tmp : constant is 3;
attribute mti_svvh_generic_type of i_lutram_read : constant is 3;
attribute mti_svvh_generic_type of enable_mem_data_b_reading : constant is 3;
attribute mti_svvh_generic_type of wrcontrol_wraddress_reg_b : constant is 3;
attribute mti_svvh_generic_type of is_write_on_positive_edge : constant is 1;
attribute mti_svvh_generic_type of lutram_single_port_fast_read : constant is 3;
attribute mti_svvh_generic_type of lutram_dual_port_fast_read : constant is 3;
attribute mti_svvh_generic_type of s3_address_aclr_a : constant is 3;
attribute mti_svvh_generic_type of s3_address_aclr_b : constant is 3;
attribute mti_svvh_generic_type of i_address_aclr_family_a : constant is 3;
attribute mti_svvh_generic_type of i_address_aclr_family_b : constant is 3;
end altera_syncram;
|
mit
|
Given-Jiang/Binarization
|
tb_Binarization/hdl/alt_dspbuilder_decoder.vhd
|
7
|
1660
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_decoder is
generic (
DECODE : string := "00000000";
PIPELINE : natural := 0;
WIDTH : natural := 8
);
port (
dec : out std_logic;
clock : in std_logic;
sclr : in std_logic;
data : in std_logic_vector(width-1 downto 0);
aclr : in std_logic;
ena : in std_logic
);
end entity alt_dspbuilder_decoder;
architecture rtl of alt_dspbuilder_decoder is
component alt_dspbuilder_decoder_GNSCEXJCJK is
generic (
DECODE : string := "000000000000000000001111";
PIPELINE : natural := 0;
WIDTH : natural := 24
);
port (
aclr : in std_logic;
clock : in std_logic;
data : in std_logic_vector(24-1 downto 0);
dec : out std_logic;
ena : in std_logic;
sclr : in std_logic
);
end component alt_dspbuilder_decoder_GNSCEXJCJK;
begin
alt_dspbuilder_decoder_GNSCEXJCJK_0: if ((DECODE = "000000000000000000001111") and (PIPELINE = 0) and (WIDTH = 24)) generate
inst_alt_dspbuilder_decoder_GNSCEXJCJK_0: alt_dspbuilder_decoder_GNSCEXJCJK
generic map(DECODE => "000000000000000000001111", PIPELINE => 0, WIDTH => 24)
port map(aclr => aclr, clock => clock, data => data, dec => dec, ena => ena, sclr => sclr);
end generate;
assert not (((DECODE = "000000000000000000001111") and (PIPELINE = 0) and (WIDTH = 24)))
report "Please run generate again" severity error;
end architecture rtl;
|
mit
|
Given-Jiang/Binarization
|
Binarization_dspbuilder/db/alt_dspbuilder_gnd.vhd
|
20
|
747
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_gnd is
port (
output : out std_logic
);
end entity alt_dspbuilder_gnd;
architecture rtl of alt_dspbuilder_gnd is
component alt_dspbuilder_gnd_GN is
port (
output : out std_logic
);
end component alt_dspbuilder_gnd_GN;
begin
alt_dspbuilder_gnd_GN_0: if true generate
inst_alt_dspbuilder_gnd_GN_0: alt_dspbuilder_gnd_GN
port map(output => output);
end generate;
end architecture rtl;
|
mit
|
Given-Jiang/Binarization
|
Binarization_dspbuilder/db/alt_dspbuilder_testbench_capture.vhd
|
10
|
676
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_testbench_capture is
end entity alt_dspbuilder_testbench_capture;
architecture rtl of alt_dspbuilder_testbench_capture is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
mit
|
Given-Jiang/Binarization
|
Binarization_dspbuilder/db/alt_dspbuilder_logical_bit_op.vhd
|
10
|
667
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_logical_bit_op is
end entity alt_dspbuilder_logical_bit_op;
architecture rtl of alt_dspbuilder_logical_bit_op is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
mit
|
Given-Jiang/Binarization
|
Binarization_dspbuilder/hdl/Binarization.vhd
|
2
|
2729
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity Binarization is
port (
Avalon_MM_Slave_address : in std_logic_vector(2-1 downto 0);
Avalon_MM_Slave_write : in std_logic;
Avalon_MM_Slave_writedata : in std_logic_vector(32-1 downto 0);
Avalon_ST_Sink_data : in std_logic_vector(24-1 downto 0);
Avalon_ST_Sink_endofpacket : in std_logic;
Avalon_ST_Sink_ready : out std_logic;
Avalon_ST_Sink_startofpacket : in std_logic;
Avalon_ST_Sink_valid : in std_logic;
Avalon_ST_Source_data : out std_logic_vector(24-1 downto 0);
Avalon_ST_Source_endofpacket : out std_logic;
Avalon_ST_Source_ready : in std_logic;
Avalon_ST_Source_startofpacket : out std_logic;
Avalon_ST_Source_valid : out std_logic;
Clock : in std_logic;
aclr : in std_logic
);
end entity Binarization;
architecture rtl of Binarization is
component Binarization_GN is
port (
Avalon_MM_Slave_address : in std_logic_vector(2-1 downto 0);
Avalon_MM_Slave_write : in std_logic;
Avalon_MM_Slave_writedata : in std_logic_vector(32-1 downto 0);
Avalon_ST_Sink_data : in std_logic_vector(24-1 downto 0);
Avalon_ST_Sink_endofpacket : in std_logic;
Avalon_ST_Sink_ready : out std_logic;
Avalon_ST_Sink_startofpacket : in std_logic;
Avalon_ST_Sink_valid : in std_logic;
Avalon_ST_Source_data : out std_logic_vector(24-1 downto 0);
Avalon_ST_Source_endofpacket : out std_logic;
Avalon_ST_Source_ready : in std_logic;
Avalon_ST_Source_startofpacket : out std_logic;
Avalon_ST_Source_valid : out std_logic;
Clock : in std_logic;
aclr : in std_logic
);
end component Binarization_GN;
begin
Binarization_GN_0: if true generate
inst_Binarization_GN_0: Binarization_GN
port map(Avalon_MM_Slave_address => Avalon_MM_Slave_address, Avalon_MM_Slave_write => Avalon_MM_Slave_write, Avalon_MM_Slave_writedata => Avalon_MM_Slave_writedata, Avalon_ST_Sink_data => Avalon_ST_Sink_data, Avalon_ST_Sink_endofpacket => Avalon_ST_Sink_endofpacket, Avalon_ST_Sink_ready => Avalon_ST_Sink_ready, Avalon_ST_Sink_startofpacket => Avalon_ST_Sink_startofpacket, Avalon_ST_Sink_valid => Avalon_ST_Sink_valid, Avalon_ST_Source_data => Avalon_ST_Source_data, Avalon_ST_Source_endofpacket => Avalon_ST_Source_endofpacket, Avalon_ST_Source_ready => Avalon_ST_Source_ready, Avalon_ST_Source_startofpacket => Avalon_ST_Source_startofpacket, Avalon_ST_Source_valid => Avalon_ST_Source_valid, Clock => Clock, aclr => aclr);
end generate;
end architecture rtl;
|
mit
|
Given-Jiang/Binarization
|
tb_Binarization/altera_lnsim/generic_mux/_primary.vhd
|
5
|
266
|
library verilog;
use verilog.vl_types.all;
entity generic_mux is
port(
din : in vl_logic_vector(63 downto 0);
sel : in vl_logic_vector(5 downto 0);
dout : out vl_logic
);
end generic_mux;
|
mit
|
hubertokf/VHDL-Sequential-Multiplier
|
regshifter.vhd
|
1
|
990
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity regshifter is
port(
pp : in std_logic_vector(31 downto 0);
valIn : in std_logic_vector(63 downto 0);
mr : in std_logic_vector(31 downto 0);
carry : in std_logic;
enable : in std_logic_vector(1 downto 0);
clk : in std_logic;
rst : in std_logic;
out1 : out std_logic_vector(63 downto 0)
);
end entity;
architecture rtl of regshifter is
signal Temp: std_logic_vector(63 downto 0);
begin
process(valIn, clk, rst)
begin
if rst = '1' then
Temp <= "0000000000000000000000000000000000000000000000000000000000000000";
elsif (clk='1' and clk'event) then
Temp <= valIn;
if ( enable = "00" ) then
Temp <= valIn;
elsif ( enable = "01" ) then
Temp(31 downto 0) <= mr;
elsif ( enable = "10" ) then
Temp(63 downto 32) <= pp;
elsif ( enable = "11" ) then
Temp <= carry & valIn(63 downto 1);
end if;
end if;
end process;
out1 <= Temp;
end rtl;
|
mit
|
Predator01/Levi
|
Downloads/ProySisDigAva (11-11-2015)/P17_Hierarchical_Clock_Complete/Cont0a5.vhd
|
6
|
1369
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:08:49 10/06/2010
-- Design Name:
-- Module Name: Cont0a5 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Cont0a5 is
port (
Load : in STD_LOGIC;
Enable : in STD_LOGIC;
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
Valor : in STD_LOGIC_VECTOR (3 downto 0);
TCO : out STD_LOGIC;
Cuenta : out STD_LOGIC_VECTOR (3 downto 0));
end Cont0a5;
architecture Behavioral of Cont0a5 is
signal Cont : integer range 0 to 9;
begin
process (Rst,Clk,Cont)
begin
if (Rst = '1') then
Cont <= 0;
elsif (rising_edge(Clk)) then
if (Load = '1') then
Cont <= conv_integer(Valor);
elsif (Enable = '1') then
if Cont = 5 then
Cont <= 0;
else
Cont <= Cont + 1;
end if;
end if;
end if;
Cuenta <= conv_std_logic_vector(Cont,4);
end process;
--Terminal Count Out
TCO <= '1' when Cont = 5 else
'0';
end Behavioral;
|
mit
|
Predator01/Levi
|
P02_Prime_Detector/Prime_Detector.vhd
|
1
|
1579
|
----------------------------------------------------------------------------------
-- Company: ITESM
-- Engineer: Miguel Gonzalez A01203712
--
-- Create Date: 15:17:18 08/20/2015
-- Design Name: Optimus_Prime
-- Module Name: Prime_Detector - Behavioral
-- Project Name: Prime Detector
-- Target Devices: None
-- Tool versions: ISE v14.7
-- Description: Prime detector 3 bits of input A,B,C
-- 3 bits of output D(Prime), E(odd), F(even)
-- Dependencies: Nope
--
-- Revision: 1.0.0
-- Revision 0.01 - File Created
-- Additional Comments: I Love VHDL
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Prime_Detector is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
Dout : out STD_LOGIC; -- Prime
Eout : out STD_LOGIC; -- Odd
Fout : out STD_LOGIC); -- Even
end Prime_Detector;
architecture Behavioral of Prime_Detector is
begin
Dout <= '1' when (
(A='0' and B='1' and C='0') or
(A='0' and B='1' and C='1') or
(A='1' and B='0' and C='1') or
(A='1' and B='1' and C='1')
) else '0';
Eout <= '1' when C='1' else '0';
Fout <= '1' when not C='1' else '0';
end Behavioral;
|
mit
|
Predator01/Levi
|
Downloads/ProySisDigAva (11-11-2015)/P18a_Shift_Register_8_bit_SN74164/Shift_Register.vhd
|
1
|
3122
|
----------------------------------------------------------------------------------
-- Company: ITESM CQ
-- Engineer: Miguel Gonzalez A0123712
--
-- Create Date: 09:13:49 10/13/2015
-- Design Name:
-- Module Name: Shift_Register - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Implementation of a 8 bit shift register
--
-- Dependencies: None
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity Shift_Register is
Port ( Clk : in STD_LOGIC;
A : in STD_LOGIC;
B : in STD_LOGIC;
Clr : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (0 to 7));
end Shift_Register;
architecture Behavioral of Shift_Register is
--Embedded signal
signal Reg : BIT_VECTOR (0 to 7);
signal AnB : STD_LOGIC;
--frequency devider
--Declaraciones de constantes
constant Fosc : integer := 100000000; --Frecuencia del oscilador de tabletas NEXYS 3
constant Fdiv : integer := 10; --Frecuencia deseada del divisor
constant CtaMax : integer := Fosc / Fdiv; --Cuenta maxima a la que hay que llegar
--Declaracion de signals
signal Cont : integer range 0 to CtaMax;
signal ClkOut : STD_LOGIC;
signal ret : STD_LOGIC:= '0';
begin
--Proceso que Divide la Frecuencia de entrada para obtener una Frecuencia de 1 Hz
process (Clr, Clk)
begin
if Clr = '0' then
Cont <= 0;
elsif (rising_edge(Clk)) then
if Cont = CtaMax then
Cont <= 0;
ClkOut <= '1';
else
Cont <= Cont + 1;
ClkOut<= '0';
end if;
end if;
end process;
-- Describe the shift-right register
-- AnB <= A and B;
-- shift_reg: process(Clk, Clr, ClkOut)
-- begin
-- if (Clr = '0') then
-- Reg <= (others => '0');
-- elsif (rising_edge(Clk) and ClkOut='1') then
-- Reg <= (AnB & Reg(0 to 6));
--
-- end if;
-- end process shift_reg;
-- Q <= Reg;
--
-- Describe the shift-left register
-- AnB <= A and B;
-- shift_reg: process(Clk, Clr, ClkOut)
-- begin
-- if (Clr = '0') then
-- Reg <= (others => '0');
-- elsif (rising_edge(Clk) and ClkOut='1') then
-- Reg <= (Reg(1 to 7) & AnB);
--
-- end if;
-- end process shift_reg;
-- Q <= Reg;
-- Describe the shift-left-rigth register
AnB <= A and B;
shift_reg: process(Clk, Clr, ClkOut, ret)
begin
if (Clr = '0') then
Reg <= (others => '0');
Reg(0) <= '1';
Ret <= '0';
elsif (rising_edge(Clk) and ClkOut='1') then
-- Determinar el orden del shifteo
if ret = '1' then
-- Shift left
-- Reg <= (Reg(1 to 7) & '0');
Reg <= Reg sll 1;
else
-- Shift right
-- Reg <= ('0' & Reg(0 to 6));
Reg <= Reg srl 1;
end if;
-- Checar condicion de cambio de bandera
if Reg = "00000010" then
ret <= '1';
end if;
if Reg = "01000000" then
ret <= '0';
end if;
end if;
end process shift_reg;
Q <= To_StdLogicVector(Reg);
end Behavioral;
|
mit
|
Predator01/Levi
|
Downloads/Hierarchical_Clock_Complete/P17_Hierarchical_Clock_Complete/P17_Hierarchical_Clock_Complete/Cont0a9.vhd
|
3
|
1481
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:52:23 10/06/2010
-- Design Name:
-- Module Name: Cont0a9 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Cont0a9 is
port (
Load : in STD_LOGIC;
Enable : in STD_LOGIC;
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
Valor : in STD_LOGIC_VECTOR (3 downto 0);
TCO : out STD_LOGIC;
Cuenta : out STD_LOGIC_VECTOR (3 downto 0));
end Cont0a9;
architecture Behavioral of Cont0a9 is
signal Cont : integer range 0 to 9;
begin
process (Rst,Clk,Cont)
begin
if (Rst = '1') then
Cont <= 0;
elsif (rising_edge(Clk)) then
if (Load = '1') then
--Covertir de STD_LOGIC_VECTOR a Integer
Cont <= conv_integer(Valor);
elsif (Enable = '1') then
if Cont = 9 then
Cont <= 0;
else
Cont <= Cont + 1;
end if;
end if;
end if;
--Convertir de Integer a STD_LOGIC_VECTOR, dejar Cuenta en 4-bits
Cuenta <= conv_std_logic_vector(Cont,4);
end process;
--Terminal Count Out
TCO <= '1' when Cont = 9 else
'0';
end Behavioral;
|
mit
|
Predator01/Levi
|
Downloads/ProySisDigAva (11-11-2015)/P17_Hierarchical_Clock_Complete/Cont0a9.vhd
|
3
|
1481
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:52:23 10/06/2010
-- Design Name:
-- Module Name: Cont0a9 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Cont0a9 is
port (
Load : in STD_LOGIC;
Enable : in STD_LOGIC;
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
Valor : in STD_LOGIC_VECTOR (3 downto 0);
TCO : out STD_LOGIC;
Cuenta : out STD_LOGIC_VECTOR (3 downto 0));
end Cont0a9;
architecture Behavioral of Cont0a9 is
signal Cont : integer range 0 to 9;
begin
process (Rst,Clk,Cont)
begin
if (Rst = '1') then
Cont <= 0;
elsif (rising_edge(Clk)) then
if (Load = '1') then
--Covertir de STD_LOGIC_VECTOR a Integer
Cont <= conv_integer(Valor);
elsif (Enable = '1') then
if Cont = 9 then
Cont <= 0;
else
Cont <= Cont + 1;
end if;
end if;
end if;
--Convertir de Integer a STD_LOGIC_VECTOR, dejar Cuenta en 4-bits
Cuenta <= conv_std_logic_vector(Cont,4);
end process;
--Terminal Count Out
TCO <= '1' when Cont = 9 else
'0';
end Behavioral;
|
mit
|
Predator01/Levi
|
Downloads/ProySisDigAva (11-11-2015)/P00_FullAdder/One_Bit_Full_Adder/Full_Adder_1_Bit.vhd
|
1
|
1296
|
----------------------------------------------------------------------------------
-- Company: ITESM
-- Engineer: Elmer Homero
--
-- Create Date: 11:24:19 08/19/2015
-- Design Name:
-- Module Name: Full_Adder_1_Bit - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE Webpack 14.7
-- Description: 1-bit Full Adder implementation
--
-- Dependencies: None
--
-- Revision: 1.0
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Full_Adder_1_Bit is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
Sout : out STD_LOGIC;
Cout : out STD_LOGIC);
end Full_Adder_1_Bit;
architecture Behavioral of Full_Adder_1_Bit is
begin
-- 1-bit Adder definition
Sout <= A xor B xor Cin;
Cout <= (A and B) or (A and Cin) or (B and Cin);
end Behavioral;
|
mit
|
Predator01/Levi
|
PF30Nov/PF_Robot_Sumo/PKG_ROBOT_SUMO.vhd
|
1
|
2287
|
--
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package PKG_ROBOT_SUMO is
-- Types
-- MOTOR
type motor_state_values is (MOTOR_HIGH, MOTOR_LOW);
-- ROBOT
type robot_state_values is (ROBOT_DETECT, ROBOT_FOWARD,
ROBOT_REVERSE, ROBOT_STOP);
type ultrasonic_state_values is (ULTRASONIC_FAR,ULTRASONIC_CLOSE);
-- Constants
constant MOTOR_TH_MICOS : integer := 1500;-- in microseconds
constant MOTOR_TL_MICROS : integer := 18500;
constant MOTOR_MAX : integer := 20_000;
constant ULTRASONIC_MAX : integer := 100_000;
constant ULTRASONIC_CENTI : integer := 100_000;
-- ROBOT
constant ROBOT_MAX : integer := 20_000;
-- type <new_type> is
-- record
-- <type_name> : std_logic_vector( 7 downto 0);
-- <type_name> : std_logic;
-- end record;
--
-- Declare constants
--
-- constant <constant_name> : time := <time_unit> ns;
-- constant <constant_name> : integer := <value;
--
-- Declare functions and procedure
--
-- function <function_name> (signal <signal_name> : in <type_declaration>) return <type_declaration>;
-- procedure <procedure_name> (<type_declaration> <constant_name> : in <type_declaration>);
--
end PKG_ROBOT_SUMO;
package body PKG_ROBOT_SUMO is
---- Example 1
-- function <function_name> (signal <signal_name> : in <type_declaration> ) return <type_declaration> is
-- variable <variable_name> : <type_declaration>;
-- begin
-- <variable_name> := <signal_name> xor <signal_name>;
-- return <variable_name>;
-- end <function_name>;
---- Example 2
-- function <function_name> (signal <signal_name> : in <type_declaration>;
-- signal <signal_name> : in <type_declaration> ) return <type_declaration> is
-- begin
-- if (<signal_name> = '1') then
-- return <signal_name>;
-- else
-- return 'Z';
-- end if;
-- end <function_name>;
---- Procedure Example
-- procedure <procedure_name> (<type_declaration> <constant_name> : in <type_declaration>) is
--
-- begin
--
-- end <procedure_name>;
end PKG_ROBOT_SUMO;
|
mit
|
Predator01/Levi
|
P00_FullAdder/One_Bit_Full_Adder/Full-Adder_Bit.vhd
|
1
|
1262
|
----------------------------------------------------------------------------------
-- Company: ITESM
-- Engineer: Miguel Angel
--
-- Create Date: 11:24:19 08/19/2015
-- Design Name:
-- Module Name: Full-Adder_Bit - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE Webpack 14.7
-- Description:
-- 1-bit full adder
--
-- Dependencies:
--
-- Revision: 1.0
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
-- library UNISIM;
-- use UNISIM.VComponents.all;
entity Full_Adder_Bit is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
c : in STD_LOGIC;
sout : out STD_LOGIC;
Cout : out STD_LOGIC
);
end Full_Adder_Bit;
architecture Behavioral of Full_Adder_Bit is
begin
-- 1-bit Adder definition
Sout <= A xor B xor c;
Cout <= (A and B) or (A and c) or (B and c);
end Behavioral;
|
mit
|
boztalay/HighSchoolSeniorProject
|
FPGA Stuff/OZ4_Mandelbrot/Hardware/OZ4_Mandelbrot/stack_in_MUX.vhd
|
2
|
1047
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity stack_in_MUX is
port(sel : in std_logic_vector(2 downto 0);
ctl_immediate : in std_logic_vector(31 downto 0);
ALU_result : in std_logic_vector(31 downto 0);
IO_ipins_data : in std_logic_vector(31 downto 0);
IO_iport_data : in std_logic_vector(31 downto 0);
mem_data_out : in std_logic_vector(31 downto 0);
output : out std_logic_vector(31 downto 0));
end stack_in_MUX;
architecture Behavioral of stack_in_MUX is
begin
main : process(sel, ctl_immediate, ALU_result, IO_ipins_data, IO_iport_data, mem_data_out) is
begin
case (sel) is
when "000" =>
output <= ctl_immediate;
when "001" =>
output <= ALU_result;
when "010" =>
output <= IO_ipins_data;
when "011" =>
output <= IO_iport_data;
when others =>
output <= mem_data_out;
end case;
end process;
end Behavioral;
|
mit
|
boztalay/HighSchoolSeniorProject
|
FPGA Stuff/OZ4_Mandelbrot/Hardware/FPMultiply/FPMultiply_top.vhd
|
1
|
875
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity FPMultiply_top is
port(switches : in std_logic_vector(7 downto 0);
result : out std_logic_vector(7 downto 0));
end FPMultiply_top;
architecture Behavioral of FPMultiply_top is
component FPMultiply is
port( A : in std_logic_vector(31 downto 0);
B : in std_logic_vector(31 downto 0);
R : out std_logic_vector(31 downto 0));
end component;
signal result_s : std_logic_vector(31 downto 0);
signal A_s, B_s : std_logic_vector(31 downto 0);
begin
A_s <= x"0000000" & switches(3 downto 0);
B_s <= x"0000000" & switches(7 downto 4);
fpm : FPMultiply
port map( A => A_s,
B => B_s,
R => result_s);
result <= result_s(7 downto 0);
end Behavioral;
|
mit
|
pallavagarwal07/YourHonour
|
server/views/js/ace-builds/demo/kitchen-sink/docs/vhdl.vhd
|
472
|
830
|
library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
|
mit
|
boztalay/HighSchoolSeniorProject
|
FPGA Stuff/OZ3_Mandelbrot/IprtReg.vhd
|
3
|
865
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:03:18 10/26/2009
-- Design Name:
-- Module Name: IprtReg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity IprtReg is
end IprtReg;
architecture Behavioral of IprtReg is
begin
end Behavioral;
|
mit
|
emusan/emu_awg
|
src/dac_serial.vhd
|
1
|
5607
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity dac_serial is
port(
SPI_SCK: out std_logic; -- spi clock
DAC_CS: out std_logic; -- chip select
SPI_MOSI_1: out std_logic; -- Master output, slave (DAC) input
SPI_MOSI_2: out std_logic; -- Master output, slave (DAC) input
--SPI_MISO: in std_logic; -- Master input, slave (DAC) output
--- control ---
data_in_1: in std_logic_vector(11 downto 0);
data_in_2: in std_logic_vector(11 downto 0);
ready_flag: out std_logic; -- sending data flag
send_data: in std_logic; -- send sine data over SPI
clk: in std_logic -- master clock
);
end dac_serial;
architecture Behavioral of dac_serial is
signal current_bit: integer range 0 to 15 := 0;
signal ready_flag_sig: std_logic;
signal spi_clk_delay: std_logic;
signal dac_cs_delay: std_logic;
begin
process(clk)
begin
if(rising_edge(clk)) then
if(send_data = '1') and (ready_flag_sig = '1') then
ready_flag_sig <= '0';
dac_cs_delay <= '0';
elsif ready_flag_sig = '0' then
if(spi_clk_delay = '1') then
spi_clk_delay <= '0';
else
spi_clk_delay <= '1';
current_bit <= current_bit + 1;
case current_bit is
-- command
when 2 => SPI_MOSI_1 <= '0';
SPI_MOSI_2 <= '0';
when 3 => SPI_MOSI_1 <= '0';
SPI_MOSI_2 <= '0';
-- data
when 4 => SPI_MOSI_1 <= data_in_1(11);
SPI_MOSI_2 <= data_in_2(11);
when 5 => SPI_MOSI_1 <= data_in_1(10);
SPI_MOSI_2 <= data_in_2(10);
when 6 => SPI_MOSI_1 <= data_in_1(9);
SPI_MOSI_2 <= data_in_2(9);
when 7 => SPI_MOSI_1 <= data_in_1(8);
SPI_MOSI_2 <= data_in_2(8);
when 8 => SPI_MOSI_1 <= data_in_1(7);
SPI_MOSI_2 <= data_in_2(7);
when 9 => SPI_MOSI_1 <= data_in_1(6);
SPI_MOSI_2 <= data_in_2(6);
when 10 => SPI_MOSI_1 <= data_in_1(5);
SPI_MOSI_2 <= data_in_2(5);
when 11 => SPI_MOSI_1 <= data_in_1(4);
SPI_MOSI_2 <= data_in_2(4);
when 12 => SPI_MOSI_1 <= data_in_1(3);
SPI_MOSI_2 <= data_in_2(3);
when 13 => SPI_MOSI_1 <= data_in_1(2);
SPI_MOSI_2 <= data_in_2(2);
when 14 => SPI_MOSI_1 <= data_in_1(1);
SPI_MOSI_2 <= data_in_2(1);
when 15 => SPI_MOSI_1 <= data_in_1(0);
SPI_MOSI_2 <= data_in_2(0);
ready_flag_sig <= '1';
-- other
when others => SPI_MOSI_1 <= '0'; -- used for don't cares
SPI_MOSI_2 <= '0';
end case;
end if;
else
dac_cs_delay <= '1';
current_bit <= 0;
spi_clk_delay <= dac_cs_delay;
end if;
DAC_CS <= dac_cs_delay;
SPI_SCK <= spi_clk_delay;
ready_flag <= ready_flag_sig;
end if;
end process;
end Behavioral;
--library IEEE;
--use IEEE.std_logic_1164.all;
--use IEEE.numeric_std.all;
--
--entity dac_serial is
-- port (
-- dac_clk: out std_logic;
-- dac_sync: out std_logic;
-- dac_data: out std_logic;
-- data_in: in std_logic_vector(11 downto 0);
-- ready: out std_logic;
-- send: in std_logic;
-- clk: in std_logic
-- );
--end dac_serial;
--
--architecture behavioral of dac_serial is
--
-- current_bit: unsigned(3 downto 0);
-- divide_counter: unsigned(3 downto 0);
-- sending: std_logic;
-- data_en: std_logic;
-- send_en: std_logic;
--
--begin
-- clk_divide:process(clk)
-- begin
-- if(rising_edge(clk)) then
-- if(divide_counter = to_unsigned(5,4)) then
-- divide_counter <= divide_counter + '1';
-- send_en <= '1';
-- elsif(divide_counter = to_unsigned(10,4)) then
-- divide_counter <= (others => '0');
-- data_en <= '1';
-- send_en <= '1';
-- else
-- divide_counter <= divide_counter + '1';
-- data_en <= '0';
-- send_en <= '0';
-- end if;
-- end if;
-- end process;
--
-- serial_clk: process(clk)
-- begin
-- if(rising_edge(clk)) then
-- if(sending = '1') then
--
-- end process;
--
-- serial_data: process(clk)
-- begin
-- if(rising_edge(clk)) then
-- if(send = '1') and (sending = '0') then
-- sending <= '1';
-- sending <= '1';
-- ready <= '0';
-- current_bit <= "0000";
-- dac_data <= '0';
-- elsif(data_en = '1') then
-- if(sending = '1') then
-- current_bit <= current_bit + '1';
-- dac_sync <= '0';
-- case current_bit is
-- when "0000" =>
-- dac_data <= '0'; -- don't care
-- when "0001" =>
-- dac_data <= '0'; -- don't care
-- when "0010" =>
-- dac_data <= '0'; -- 0 for normal operation
-- when "0011" =>
-- dac_data <= '0'; -- 0 for normal operation
-- when "0100" =>
-- dac_data <= data_in(11);
-- when "0101" =>
-- dac_data <= data_in(10);
-- when "0110" =>
-- dac_data <= data_in(9);
-- when "0111" =>
-- dac_data <= data_in(8);
-- when "1000" =>
-- dac_data <= data_in(7);
-- when "1001" =>
-- dac_data <= data_in(6);
-- when "1010" =>
-- dac_data <= data_in(5);
-- when "1011" =>
-- dac_data <= data_in(4);
-- when "1100" =>
-- dac_data <= data_in(3);
-- when "1101" =>
-- dac_data <= data_in(2);
-- when "1110" =>
-- dac_data <= data_in(1);
-- when "1111" =>
-- dac_data <= data_in(0);
-- when others =>
-- dac_data <= '0';
-- end case;
-- else
-- dac_sync <= '1';
-- ready <= '0';
-- current_bit <= "0000";
-- dac_data <= '0';
-- end if;
-- end if;
-- end if;
-- end process;
--
--end behavioral;
|
mit
|
Predator01/Levi
|
Downloads/ProySisDigAva (11-11-2015)/P17b_Hierarchical_Clock_Assignment/Cont0a9_tb.vhd
|
1
|
3025
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:16:10 10/09/2015
-- Design Name:
-- Module Name: D:/ProySisDigAva/P17b_Hierarchical_Clock/Cont0a9_tb.vhd
-- Project Name: P17_Hierarchical_Clock
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Cont0a9
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Cont0a9_tb IS
END Cont0a9_tb;
ARCHITECTURE behavior OF Cont0a9_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Cont0a9
PORT(
Load : IN std_logic;
Enable : IN std_logic;
Rst : IN std_logic;
Clk : IN std_logic;
Valor : IN std_logic_vector(3 downto 0);
TCO : OUT std_logic;
Cuenta : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal Load : std_logic := '0';
signal Enable : std_logic := '0';
signal Rst : std_logic := '0';
signal Clk : std_logic := '0';
signal Valor : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal TCO : std_logic;
signal Cuenta : std_logic_vector(3 downto 0);
-- Clock period definitions
constant Clk_period : time := 100 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Cont0a9 PORT MAP (
Load => Load,
Enable => Enable,
Rst => Rst,
Clk => Clk,
Valor => Valor,
TCO => TCO,
Cuenta => Cuenta
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for Clk_period*1;
-- insert stimulus here
-- Reset the counter
Rst <= '1';
Load <= '0';
Enable <= '1';
Valor <= "0010";
wait for Clk_period*1;
-- Check count
Rst <= '0';
Load <= '0';
Enable <= '1';
Valor <= "0010";
wait for Clk_period*15;
-- Check load
Rst <= '0';
Load <= '1';
Enable <= '1';
Valor <= "0010";
wait for Clk_period*1;
-- Count from load value
Rst <= '0';
Load <= '0';
Enable <= '1';
Valor <= "0010";
wait;
end process;
END;
|
mit
|
Predator01/Levi
|
PF30Nov/PF_Robot_Sumo/U4_1-Freq_Div.vhd
|
1
|
923
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:52:32 11/22/2015
-- Design Name:
-- Module Name: U4_1-Freq_Div - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity U4_1-Freq_Div is
end U4_1-Freq_Div;
architecture Behavioral of U4_1-Freq_Div is
begin
end Behavioral;
|
mit
|
Predator01/Levi
|
PF_Robot_Sumo/Detector_Linea.vhd
|
2
|
1698
|
----------------------------------------------------------------------------------
-- Company: ITESM CQ
-- Engineer: Andres Cortez A01209780
--
-- Create Date: 10:39:53 11/10/2015
-- Design Name:
-- Module Name: Motor - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Line detector that control the infrared sensor in the robot
--
-- Dependencies:
--
-- Revision:
-- Revision 0.0.1 - File Created
-- Revision 1.0.0 - Motor Implementation
-- Revision 3.0.0 - Adres implementation Line Detector
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.PKG_ROBOT_SUMO.all;
entity Detector_Linea is
Port (
in_Rst_dl : in STD_LOGIC;
in_Clk : in STD_LOGIC;
in_line_dl : in STD_LOGIC;
out_Line : out STD_LOGIC);
end Detector_Linea;
architecture Behavioral of Detector_Linea is
-- Componentes del modulo
-- Comp: U1 Divisor de frequencia 100/1
component Freq_Div
port (
in_Rst : in STD_LOGIC;
in_Clk : in STD_LOGIC;
out_time_base : out STD_LOGIC);
end component;
--Comp: U2 Modulo principal del detector de linea
component Line_Detection
port(
in_Rst : in STD_LOGIC;
in_Clk : in STD_LOGIC;
in_time_base : in STD_LOGIC;
in_line_smld : in STD_LOGIC;
out_line: out STD_LOGIC);
end component;
-- seniales embebidas
-- 1 bit
signal time_base : STD_LOGIC;
begin
-- Instanciar componentes
U3_1 : Freq_Div
port map(in_Rst_dl, in_clk, time_base);
U3_2 : Line_Detection
port map(in_Rst_dl, in_clk, time_base, in_line_dl, out_Line);
end Behavioral;
|
mit
|
boztalay/HighSchoolSeniorProject
|
FPGA Stuff/OZ4_Mandelbrot/Hardware/OZ4_Mandelbrot/FPMultiply.vhd
|
1
|
4180
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity FPMultiply is
port( A_in : in std_logic_vector(31 downto 0);
B_in : in std_logic_vector(31 downto 0);
R : out std_logic_vector(31 downto 0));
end FPMultiply;
architecture Behavioral of FPMultiply is
type array16x32 is array (15 downto 0) of std_logic_vector(31 downto 0);
signal shiftArray : array16x32;-- := (others => (others => '0'));
signal resultRaw : std_logic_vector(31 downto 0) := (others => '0');
signal resultCut, resultSigned : std_logic_vector(15 downto 0) := (others => '0');
signal A, B, Ashrt, Bshrt : std_logic_vector(15 downto 0);
signal sign : std_logic;
begin
Ashrt <= A_in(31 downto 16);
Bshrt <= B_in(31 downto 16);
signs : process (Ashrt, Bshrt) is
begin
sign <= Ashrt(15) xor Bshrt(15); --Sign is 0 if the result is positive, 1 if negative
--Flip A if it's negative
if Ashrt(15) = '1' then
A <= (not Ashrt) + 1;
else
A <= Ashrt;
end if;
--Flip B if it's negative
if Bshrt(15) = '1' then
B <= (not Bshrt) + 1;
else
B <= Bshrt;
end if;
end process;
shift_mul : process (A, B) is
begin
if B(0) = '1' then
shiftArray(0) <= "0000000000000000" & A;
else
shiftArray(0) <= (others => '0');
end if;
if B(1) = '1' then
shiftArray(1) <= "000000000000000" & A & "0";
else
shiftArray(1) <= (others => '0');
end if;
if B(2) = '1' then
shiftArray(2) <= "00000000000000" & A & "00";
else
shiftArray(2) <= (others => '0');
end if;
if B(3) = '1' then
shiftArray(3) <= "0000000000000" & A & "000";
else
shiftArray(3) <= (others => '0');
end if;
if B(4) = '1' then
shiftArray(4) <= "000000000000" & A & "0000";
else
shiftArray(4) <= (others => '0');
end if;
if B(5) = '1' then
shiftArray(5) <= "00000000000" & A & "00000";
else
shiftArray(5) <= (others => '0');
end if;
if B(6) = '1' then
shiftArray(6) <= "0000000000" & A & "000000";
else
shiftArray(6) <= (others => '0');
end if;
if B(7) = '1' then
shiftArray(7) <= "000000000" & A & "0000000";
else
shiftArray(7) <= (others => '0');
end if;
if B(8) = '1' then
shiftArray(8) <= "00000000" & A & "00000000";
else
shiftArray(8) <= (others => '0');
end if;
if B(9) = '1' then
shiftArray(9) <= "0000000" & A & "000000000";
else
shiftArray(9) <= (others => '0');
end if;
if B(10) = '1' then
shiftArray(10) <= "000000" & A & "0000000000";
else
shiftArray(10) <= (others => '0');
end if;
if B(11) = '1' then
shiftArray(11) <= "00000" & A & "00000000000";
else
shiftArray(11) <= (others => '0');
end if;
if B(12) = '1' then
shiftArray(12) <= "0000" & A & "000000000000";
else
shiftArray(12) <= (others => '0');
end if;
if B(13) = '1' then
shiftArray(13) <= "000" & A & "0000000000000";
else
shiftArray(13) <= (others => '0');
end if;
if B(14) = '1' then
shiftArray(14) <= "00" & A & "00000000000000";
else
shiftArray(14) <= (others => '0');
end if;
if B(15) = '1' then
shiftArray(15) <= "0" & A & "000000000000000";
else
shiftArray(15) <= (others => '0');
end if;
end process;
resultRaw <= shiftArray(0) + shiftArray(1) + shiftArray(2) + shiftArray(3) + shiftArray(4) + shiftArray(5) + shiftArray(6) + shiftArray(7) +
shiftArray(8) + shiftArray(9) + shiftArray(10) + shiftArray(11) + shiftArray(12) + shiftArray(13) + shiftArray(14) + shiftArray(15);
saturate : process(resultRaw) is
begin
if resultRaw > x"07FFFFFF" then
resultCut <= x"7FFF";
else
resultCut <= resultRaw(27 downto 12); --Take the middle out as the result
end if;
end process;
apply_sign : process(sign, resultCut) is
begin
if sign = '1' then
resultSigned <= (not resultCut) + 1;
else
resultSigned <= resultCut;
end if;
end process;
R <= resultSigned & x"0000";
end Behavioral;
|
mit
|
Predator01/Levi
|
PF_Partes/PF_Robot/Motor.vhd
|
2
|
3279
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:08:07 11/30/2015
-- Design Name:
-- Module Name: Motor - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Motor is
Port (
in_clk : in STD_LOGIC;
in_Rst : in STD_LOGIC;
in_Action_m : in STD_LOGIC_VECTOR(1 downto 0);
out_motor : out STD_LOGIC);
end Motor;
architecture Behavioral of Motor is
-- State definition
type state_values is (HIGH,LOW);
signal pres_state, next_state : state_values;
-- Define the State duration times for the variable
-- time duration FSM
-- All times are expressed in microseconds
signal tH : integer := 1500;
signal tL : integer := 18500;
-- Define signals used by frequency divider
constant Fosc : integer := 100_000_000; --Frecuencia del oscilador de Nexys3
constant Fdiv : integer := 1_000_000; --Frecuencia deseada del divisor
constant CtaMax : integer := Fosc / Fdiv; --Cuenta maxima a la que hay que llegar
signal Cont : integer range 0 to CtaMax;
signal TimeBase : STD_LOGIC;
-- Define a second counter, used to determine how much
-- time has been spent in a State
signal SecondCount : integer range 0 to 20_000;
-- Define a signal that gives the amount of time
-- to be spent in a State
signal StateDuration : integer range 0 to 20_000;
begin
-- Generate a TimeBase of one second
freqdiv: process (in_Rst,in_clk)
begin
if in_Rst = '1' then
Cont <= 0;
elsif (rising_edge(in_clk)) then
if Cont = CtaMax then
Cont <= 0;
TimeBase <= '1';
else
Cont <= Cont + 1;
TimeBase <= '0';
end if;
end if;
end process freqdiv;
statereg : process(in_clk,TimeBase,in_Rst)
begin
if in_Rst = '1' then
pres_state <= HIGH;
SecondCount <= 0;
elsif (rising_edge(in_clk) and TimeBase = '1') then
if SecondCount = StateDuration-1 then
pres_state <= next_state;
SecondCount <= 0;
else
SecondCount <= SecondCount + 1;
end if;
end if;
end process statereg;
cal: process (in_Action_m)
begin
-- 00 es adelante
-- 01 es atras
-- 10 es stop
if(in_Action_m = "00") then
tH <= 1000;
tL <= 19000;
elsif(in_Action_m = "01") then
tH <= 2000;
tL <= 18000;
else -- 10 es stop
tH <= 1500;
tL <= 18500;
end if;
end process cal;
fsm : process (pres_state, tH, tL)
begin
case (pres_state) is
when HIGH =>
next_state <= LOW;
StateDuration <= tH;
when LOW =>
next_state <= HIGH;
StateDuration <= tL;
when others =>
next_state <= LOW;
StateDuration <= tH;
end case;
end process fsm;
output : process (pres_state)
begin
case (pres_state) is
when HIGH =>
out_motor <= '1';
when LOW =>
out_motor <= '0';
when others =>
out_motor <= '1';
end case;
end process output;
end Behavioral;
|
mit
|
boztalay/HighSchoolSeniorProject
|
FPGA Stuff/OZ3_Mandelbrot/OZ3_Sys_Top.vhd
|
1
|
2850
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity OZ3_Sys_Top is
port(clk : in std_logic;
rst : in std_logic);
end OZ3_Sys_Top;
architecture Behavioral of OZ3_Sys_Top is
component OZ3 is
Port ( main_clock : in STD_LOGIC;
reset : in STD_LOGIC;
input_pins : in STD_LOGIC_VECTOR(15 downto 0);
input_port : in STD_LOGIC_VECTOR(31 downto 0);
instruction_from_iROM : in STD_LOGIC_VECTOR(31 downto 0);
data_from_dRAM : in STD_LOGIC_VECTOR(31 downto 0);
output_pins : out STD_LOGIC_VECTOR(15 downto 0);
output_port : out STD_LOGIC_VECTOR(31 downto 0);
output_port_enable : out STD_LOGIC;
addr_to_iROM : out STD_LOGIC_VECTOR(22 downto 0);
data_to_dRAM : out STD_LOGIC_VECTOR(31 downto 0);
addr_to_dRAM : out STD_LOGIC_VECTOR(22 downto 0);
WR_to_dRAM : out STD_LOGIC);
end component;
component data_memory is
port(clk : in std_logic;
rst : in std_logic;
address : in std_logic_vector(31 downto 0);
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
we : in std_logic);
end component;
COMPONENT program_memory
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
signal OZ3_ipins, OZ3_opins : std_logic_vector(15 downto 0);
signal OZ3_iport, OZ3_oport : std_logic_vector(31 downto 0);
signal OZ3_oport_we : std_logic;
signal prog_mem_addr : std_logic_vector(22 downto 0);
signal prog_mem_out : std_logic_vector(31 downto 0);
signal data_mem_addr : std_logic_vector(22 downto 0);
signal data_mem_real_addr : std_logic_vector(31 downto 0);
signal data_mem_out, data_mem_in : std_logic_vector(31 downto 0);
signal data_mem_we : std_logic;
begin
CPU : OZ3
port map(
main_clock => clk,
reset => rst,
input_pins => OZ3_ipins,
input_port => OZ3_iport,
instruction_from_iROM => prog_mem_out,
data_from_dRAM => data_mem_out,
output_pins => OZ3_opins,
output_port => OZ3_oport,
output_port_enable => OZ3_oport_we,
addr_to_iROM => prog_mem_addr,
data_to_dRAM => data_mem_in,
addr_to_dRAM => data_mem_addr,
WR_to_dRAM => data_mem_we
);
data_mem_real_addr <= "000000000" & data_mem_addr;
dmem : data_memory
port map(
clk => clk,
rst => rst,
address => data_mem_real_addr,
data_in => data_mem_in,
data_out => data_mem_out,
we => data_mem_we
);
pmem : program_memory
port map(
clka => clk,
addra => prog_mem_addr(8 downto 0),
douta => prog_mem_out
);
end Behavioral;
|
mit
|
Predator01/Levi
|
Downloads/ProySisDigAva (11-11-2015)/P23a_Servo_Control_with_Inputs/ServoControl.vhd
|
1
|
3399
|
----------------------------------------------------------------------------------
-- Company: ITESM
-- Engineer: Alam (formely Rick)
--
-- Create Date: 11:42:22 11/04/2015
-- Design Name:
-- Module Name: UKStopLight - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies: Controlling a Stop Light; the kind found
-- in the United Kingdom.
-- Moore FSM will be used
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity ServoControl is
Port ( Clk : in STD_LOGIC;
Rst : in STD_LOGIC;
Input : in STD_LOGIC_VECTOR(7 downto 0);
Servo : out STD_LOGIC);
end ServoControl;
architecture Behavioral of ServoControl is
-- State definition
type state_values is (HIGH,LOW);
signal pres_state, next_state : state_values;
-- Define the State duration times for the variable
-- time duration FSM
-- All times are expressed in microseconds
signal tH : integer range 0 to 20_000;
signal tL : integer range 0 to 20_000;
signal Tmp : integer range 0 to 20_000;
-- Define signals used by frequency divider
constant Fosc : integer := 100_000_000; --Frecuencia del oscilador de Nexys3
constant Fdiv : integer := 1_000_000; --Frecuencia deseada del divisor
constant CtaMax : integer := Fosc / Fdiv; --Cuenta maxima a la que hay que llegar
signal Cont : integer range 0 to CtaMax;
signal TimeBase : STD_LOGIC;
-- Define a second counter, used to determine how much
-- time has been spent in a State
signal SecondCount : integer range 0 to 20_000;
-- Define a signal that gives the amount of time
-- to be spent in a State
signal StateDuration : integer range 0 to 20_000;
begin
-- Generate a TimeBase of one second
freqdiv: process (Rst, Clk)
begin
if Rst = '1' then
Cont <= 0;
elsif (rising_edge(Clk)) then
if Cont = CtaMax then
Cont <= 0;
TimeBase <= '1';
else
Cont <= Cont + 1;
TimeBase <= '0';
end if;
end if;
end process freqdiv;
-- Calculate tH and tL
Tmp <= (CONV_INTEGER(Input) * 1000) / 256;
tH <= Tmp + 1000;
tL <= 20000 - tH;
statereg : process(Clk,TimeBase,Rst)
begin
if Rst = '1' then
pres_state <= HIGH;
SecondCount <= 0;
elsif (rising_edge(Clk) and TimeBase = '1') then
if SecondCount = StateDuration-1 then
pres_state <= next_state;
SecondCount <= 0;
else
SecondCount <= SecondCount + 1;
end if;
end if;
end process statereg;
fsm : process (pres_state,tH,tL)
begin
case (pres_state) is
when HIGH =>
next_state <= LOW;
StateDuration <= tH;
when LOW =>
next_state <= HIGH;
StateDuration <= tL;
when others =>
next_state <= LOW;
StateDuration <= tH;
end case;
end process fsm;
output : process (pres_state)
begin
case (pres_state) is
when HIGH =>
Servo <= '1';
when LOW =>
Servo <= '0';
when others =>
Servo <= '1';
end case;
end process output;
end Behavioral;
|
mit
|
boztalay/HighSchoolSeniorProject
|
FPGA Stuff/OZ3_Mandelbrot/Keyboard.vhd
|
2
|
2616
|
----------------------------------------------------------------------------------
--Ben Oztalay, 2009-2010
--
--Module Title: Keyboard
--Module Description:
-- This is a simple module that eases the interface with a keyboard. It takes the
-- PS/2 bus clock and data pins as inputs, as well as an acknowledgment signal. The
-- outputs are the 8-bit scan code and a signal that tells the host device that
-- the scan code is ready. Every 11 clock cycles, when the entire packet has been sent,
-- the code_ready output is driven high, and stays high until the acknowledgement
-- input is raised to '1'. It doesn't take scan codes while the code_ready output
-- is high.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Keyboard is
Port ( key_clock : in STD_LOGIC;
key_data : in STD_LOGIC;
acknowledge : in STD_LOGIC;
scan_code : out STD_LOGIC_VECTOR (7 downto 0);
code_ready : out STD_LOGIC);
end Keyboard;
architecture Behavioral of Keyboard is
--//Components\\--
component Gen_Shift_Reg_Falling is
generic (size : integer);
Port ( clock : in STD_LOGIC;
enable : in STD_LOGIC;
reset : in STD_LOGIC;
data_in : in STD_LOGIC;
data_out : out STD_LOGIC_VECTOR ((size-1) downto 0));
end component;
--\\Components//--
--//Signals\\--
signal code_ready_sig : STD_LOGIC;
signal enable : STD_LOGIC;
signal reg_out : STD_LOGIC_VECTOR(10 downto 0);
--\\Signals//--
begin
count_chk : process (key_clock, acknowledge, enable) is
variable count : integer := 0;
variable ready : STD_LOGIC := '0';
begin
if enable = '1' then
if falling_edge(key_clock) then
count := count + 1;
if count = 11 then
count := 0;
ready := '1';
end if;
end if;
end if;
if (ready = '1') and (acknowledge = '1') then
ready := '0';
end if;
code_ready_sig <= ready;
end process;
shift_reg : Gen_Shift_Reg_Falling generic map (size => 11)
port map (clock => key_clock,
enable => enable,
reset => '0',
data_in => key_data,
data_out => reg_out);
enable <= (not (key_clock and code_ready_sig));
code_ready <= code_ready_sig;
scan_code <= reg_out(2) & reg_out(3) & reg_out(4) & reg_out(5) & reg_out(6) & reg_out(7) & reg_out(8) & reg_out(9);
end Behavioral;
|
mit
|
Predator01/Levi
|
Downloads/ProySisDigAva (11-11-2015)/P22_ServoControl/ServoControl.vhd
|
1
|
1676
|
----------------------------------------------------------------------------------
-- Company: ITESM QRO
-- Engineer: Felipe Gasca
--
-- Create Date: 08:05:27 10/03/2012
-- Design Name:
-- Module Name: ServoControl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ServoControl is
Port ( Angulo : in STD_LOGIC_VECTOR (7 downto 0);
Clk : in STD_LOGIC;
Rst : in STD_LOGIC;
Senal : out STD_LOGIC);
end ServoControl;
architecture Behavioral of ServoControl is
--Embedded Signal needed by Frequency divider
--Frequency divider counter declaration
constant MaxCta: natural := 2000000; --definir valor de acuerda a la tableta
signal ContDiv : natural range 0 to MaxCta;
--Embedded Signal neede for DivDisp
Signal PulsoNecesario : natural;
begin
PulsoNecesario <= 100000 + conv_integer(Angulo) * 392;
--Frequency divider section
DivFrec: process(Rst,Clk)
begin
--Asinchronous Reset
if (Rst = '1') then
ContDiv <= 0;
elsif (rising_edge (Clk)) then
--Check if counter has reached the final count
if (ContDiv = MaxCta) then
ContDiv <= 0;
else
--no ha transcurrido un segundo, seguir incrementando el contador
ContDiv <= ContDiv + 1;
end if;
end if;
end process DivFrec;
Senal <= '1' when ContDiv < PulsoNecesario else
'0';
end Behavioral;
|
mit
|
Predator01/Levi
|
Downloads/ProySisDigAva (11-11-2015)/P04a_SN74LS138/SN74LS138.vhd
|
1
|
1732
|
----------------------------------------------------------------------------------
-- Company: ITESM
-- Engineer:
--
-- Create Date: 11:15:42 09/02/2015
-- Design Name:
-- Module Name: SN74LS138 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Implmentation of a TTL
-- 74LS138 Decoder Chip
-- Dependencies:
--
-- Revision: 1.0
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SN74LS138 is
Port ( -- Select Lines
C : in STD_LOGIC;
B : in STD_LOGIC;
A : in STD_LOGIC;
-- Enable Lines
G2A : in STD_LOGIC;
G2B : in STD_LOGIC;
G1 : in STD_LOGIC;
-- Output Lines
Y : out STD_LOGIC_VECTOR (0 to 7));
end SN74LS138;
architecture Behavioral of SN74LS138 is
-- Embedded signals declaration
signal G2 : STD_LOGIC;
signal Sel : STD_LOGIC_VECTOR (2 downto 0);
begin
-- Group G2A and G2B to make G2 according to the
-- Data Sheet
G2 <= G2A or G2B;
-- Group Select line C,B and A for simpler handling
Sel <= C & B & A;
-- Define the truth table using:
-- Concurrent Behavioral
--YYYYYYYY
--01234567
Y <= "11111111" when (G2 = '1') else
"11111111" when (G1 = '0') else
"01111111" when (Sel = "000") else
"10111111" when (Sel = "001") else
"11011111" when (Sel = "010") else
"11101111" when (Sel = "011") else
"11110111" when (Sel = "100") else
"11111011" when (Sel = "101") else
"11111101" when (Sel = "110") else
"11111110";
end Behavioral;
|
mit
|
hubertokf/VHDL-Sequential-Multiplier
|
mux2to1.vhd
|
1
|
343
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux2to1 is
Port ( SEL : in STD_LOGIC;
A : in STD_LOGIC_VECTOR (31 downto 0);
X : out STD_LOGIC_VECTOR (31 downto 0));
end mux2to1;
architecture Behavioral of mux2to1 is
begin
X <= A when (SEL = '1') else "00000000000000000000000000000000";
end Behavioral;
|
mit
|
emusan/emu_awg
|
src/lcd_controller.vhd
|
1
|
21575
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:54:36 04/11/2014
-- Design Name:
-- Module Name: lcd_controller - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity lcd_controller is
port(
amp_adjust: in std_logic_vector(23 downto 0); -- ch1 (5 downto 0) ch2 (11 downto 6) ch3 (17 downto 12) ch4 (23 downto 18)
freq_adjust: in std_logic_vector(39 downto 0); -- ch 1 (9 downto 0) ch2 (19 downto 10) ch3 (29 downto 20) ch4 (39 downto 30)
phase_adjust: in std_logic_vector(31 downto 0); -- ch 1 (7 downto 0) ch2 (15 downto 8) ch3 (23 downto 16) ch4 (31 downto 24)
pwm_adjust: in std_logic_vector(39 downto 0); -- ch 1 (9 downto 0) ch2 (19 downto 10) ch3 (29 downto 20) ch4 (39 downto 30)
current_channel: in std_logic_vector(1 downto 0);
current_mode: in std_logic_vector(1 downto 0);
lcd_data: out std_logic_vector(3 downto 0);
lcd_e: out std_logic;
lcd_rw: out std_logic;
lcd_rs: out std_logic;
clk: in std_logic
);
end lcd_controller;
architecture Behavioral of lcd_controller is
signal initialization_step: integer range 0 to 100;
signal running_step: integer range 0 to 98;
signal running: std_logic := '0';
signal delay_small: std_logic;
signal delay_small_count: unsigned(2 downto 0); -- used between rs,rw,data, and en. approx 80ns
signal delay_mid: std_logic;
signal delay_mid_count: unsigned(4 downto 0); -- used between en high and low. approx over 250ns
signal delay_large: std_logic;
signal delay_large_count: unsigned(7 downto 0); -- used between each set of 4-bits. approx over 1us
signal delay_btw_sigs: std_logic;
signal delay_btw_sigs_count: unsigned(11 downto 0); -- used between packets of data. approx over 40us
signal delay_huge: std_logic;
signal delay_huge_count: unsigned(19 downto 0); -- used twice in init approx 41ms
signal is_delay: std_logic;
signal upper_mode: std_logic_vector(3 downto 0);
signal lower_mode: std_logic_vector(3 downto 0);
signal upper_val1: std_logic_vector(3 downto 0);
signal upper_val2: std_logic_vector(3 downto 0);
signal upper_val3: std_logic_vector(3 downto 0);
signal lower_val1: std_logic_vector(3 downto 0);
signal lower_val2: std_logic_vector(3 downto 0);
signal lower_val3: std_logic_vector(3 downto 0);
signal current_value: std_logic_vector(9 downto 0);
begin
is_delay <= delay_small or delay_mid or delay_large or delay_btw_sigs or delay_huge;
with current_mode select
upper_mode <= "0100" when "00",
"0101" when "01",
"0100" when "10",
"0101" when "11",
"0100" when others;
with current_mode select
lower_mode <= "0110" when "00",
"0000" when "01",
"0001" when "10",
"0111" when "11",
"0001" when others;
upper_val1 <= "0011";
lower_val1 <= "00" & current_value(9 downto 8);
upper_val2 <= "0011" when (unsigned(current_value(7 downto 4)) < 10) else "0100";
lower_val2 <= current_value(7 downto 4) when (unsigned(current_value(7 downto 4)) < 10) else std_logic_vector(unsigned(current_value(7 downto 4)) - 9);
upper_val3 <= "0011" when (unsigned(current_value(3 downto 0)) < 10) else "0100";
lower_val3 <= current_value(3 downto 0) when (unsigned(current_value(3 downto 0)) < 10) else std_logic_vector(unsigned(current_value(3 downto 0)) - 9);
process(clk)
begin
if(rising_edge(clk)) then
case current_mode is
when "00" =>
case current_channel is
when "00" => current_value <= freq_adjust(9 downto 0);
when "01" => current_value <= freq_adjust(19 downto 10);
when "10" => current_value <= freq_adjust(29 downto 20);
when "11" => current_value <= freq_adjust(39 downto 30);
when others => current_value <= freq_adjust(9 downto 0);
end case;
when "01" =>
case current_channel is
when "00" => current_value <= "00" & phase_adjust(7 downto 0);
when "01" => current_value <= "00" & phase_adjust(15 downto 8);
when "10" => current_value <= "00" & phase_adjust(23 downto 16);
when "11" => current_value <= "00" & phase_adjust(31 downto 24);
when others => current_value <= "00" & phase_adjust(7 downto 0);
end case;
when "10" =>
case current_channel is
when "00" => current_value <= "0000" & amp_adjust(5 downto 0);
when "01" => current_value <= "0000" & amp_adjust(11 downto 6);
when "10" => current_value <= "0000" & amp_adjust(17 downto 12);
when "11" => current_value <= "0000" & amp_adjust(23 downto 18);
when others => current_value <= "0000" & amp_adjust(5 downto 0);
end case;
when "11" =>
case current_channel is
when "00" => current_value <= pwm_adjust(9 downto 0);
when "01" => current_value <= pwm_adjust(19 downto 10);
when "10" => current_value <= pwm_adjust(29 downto 20);
when "11" => current_value <= pwm_adjust(39 downto 30);
when others => current_value <= pwm_adjust(9 downto 0);
end case;
when others =>
case current_channel is
when "00" => current_value <= freq_adjust(9 downto 0);
when "01" => current_value <= freq_adjust(19 downto 10);
when "10" => current_value <= freq_adjust(29 downto 20);
when "11" => current_value <= freq_adjust(39 downto 30);
when others => current_value <= freq_adjust(9 downto 0);
end case;
end case;
if(is_delay = '0' and running = '0') then
initialization_step <= initialization_step + 1;
case initialization_step is
when 0 => delay_huge <= '1'; -- wait 15ms or longer
lcd_e <= '0';
lcd_rw <= '1';
lcd_rs <= '1';
when 1 => lcd_data <= "0011"; -- write 0x3
delay_small <= '1';
when 2 => lcd_e <= '1'; -- pulse LCD_E high for 12 clock cycles
delay_mid <= '1';
when 3 => lcd_e <= '0'; -- end pulse
delay_huge <= '1'; -- wait 4.1ms or more
when 4 => lcd_e <= '1'; -- pulse LCD_E high for 12 clock cycles
delay_mid <= '1';
when 5 => lcd_e <= '0'; -- end pulse
delay_huge <= '1'; -- wait 100us or more
when 6 => lcd_e <= '1'; -- pulse LCD_E high for 12 clock cycles
delay_mid <= '1';
when 7 => lcd_e <= '0'; -- end pulse
delay_huge <= '1'; -- wait 40us or more
when 8 => lcd_data <= "0010"; -- write 0x2
delay_small <= '1';
when 9 => lcd_e <= '1'; -- pulse LCD_E high for 12 clock cycles
delay_mid <= '1';
when 10 => lcd_e <= '0';
lcd_rw <= '0';
lcd_rs <= '0';
delay_huge <= '1'; -- wait 40us or longer
----------------------------------------------------------
-- send function set 0x28
----------------------------------------------------------
when 11 => lcd_data <= "0010";
lcd_rs <= '0';
lcd_rw <= '0';
delay_small <= '1';
when 12 => lcd_e <= '1';
delay_mid <= '1';
when 13 => lcd_e <= '0';
delay_small <= '1';
when 14 => lcd_rs <= '1';
lcd_rw <= '1';
delay_large <= '1';
when 15 => lcd_data <= "1000";
lcd_rs <= '0';
lcd_rw <= '0';
delay_small <= '1';
when 16 => lcd_e <= '1';
delay_mid <= '1';
when 17 => lcd_e <= '0';
delay_small <= '1';
when 18 => lcd_rs <= '1';
lcd_rw <= '1';
delay_huge <= '1';
----------------------------------------------------------
-- send entry mode set 0x06
----------------------------------------------------------
-- when 19 => lcd_data <= "0000";
-- lcd_rs <= '0';
-- lcd_rw <= '0';
-- delay_small <= '1';
-- when 20 => lcd_e <= '1';
-- delay_mid <= '1';
-- when 21 => lcd_e <= '0';
-- delay_small <= '1';
-- when 22 => lcd_rs <= '1';
-- lcd_rw <= '1';
-- delay_large <= '1';
--
-- when 23 => lcd_data <= "0110";
-- lcd_rs <= '0';
-- lcd_rw <= '0';
-- delay_small <= '1';
-- when 24 => lcd_e <= '1';
-- delay_mid <= '1';
-- when 25 => lcd_e <= '0';
-- delay_small <= '1';
-- when 26 => lcd_rs <= '1';
-- lcd_rw <= '1';
-- delay_huge <= '1';
----------------------------------------------------------
-- send power on
----------------------------------------------------------
when 19 => lcd_data <= "0000";
lcd_rs <= '0';
lcd_rw <= '0';
delay_small <= '1';
when 20 => lcd_e <= '1';
delay_mid <= '1';
when 21 => lcd_e <= '0';
delay_small <= '1';
when 22 => lcd_rs <= '1';
lcd_rw <= '1';
delay_large <= '1';
when 23 => lcd_data <= "1111";
lcd_rs <= '0';
lcd_rw <= '0';
delay_small <= '1';
when 24 => lcd_e <= '1';
delay_mid <= '1';
when 25 => lcd_e <= '0';
delay_small <= '1';
when 26 => lcd_rs <= '1';
lcd_rw <= '1';
delay_btw_sigs <= '1';
----------------------------------------------------------
-- clear display 0x01
----------------------------------------------------------
when 35 => lcd_data <= "0000";
lcd_rs <= '0';
lcd_rw <= '0';
delay_small <= '1';
when 36 => lcd_e <= '1';
delay_mid <= '1';
when 37 => lcd_e <= '0';
delay_small <= '1';
when 38 => lcd_rs <= '1';
lcd_rw <= '1';
delay_large <= '1';
when 39 => lcd_data <= "0001";
lcd_rs <= '0';
lcd_rw <= '0';
delay_small <= '1';
when 40 => lcd_e <= '1';
delay_mid <= '1';
when 41 => lcd_e <= '0';
delay_small <= '1';
when 42 => lcd_rs <= '1';
lcd_rw <= '1';
delay_huge <= '1';
when 43 => delay_huge <= '1';
when 44 => running <= '1';
when others => lcd_data <= "0000";
delay_huge <= '1';
--running <= '1';
end case; -- initialization steps
elsif(is_delay = '0' and running = '1') then
running_step <= running_step + 1;
case running_step is
----------------------------------------------------------
-- clear display 0x01
----------------------------------------------------------
when 0 => lcd_data <= "0000";
lcd_rs <= '0';
lcd_rw <= '0';
delay_small <= '1';
when 1 => lcd_e <= '1';
delay_mid <= '1';
when 2 => lcd_e <= '0';
delay_small <= '1';
when 3 => lcd_rs <= '1';
lcd_rw <= '1';
delay_large <= '1';
when 4 => lcd_data <= "0001";
lcd_rs <= '0';
lcd_rw <= '0';
delay_small <= '1';
when 5 => lcd_e <= '1';
delay_mid <= '1';
when 6 => lcd_e <= '0';
delay_small <= '1';
when 7 => lcd_rs <= '1';
lcd_rw <= '1';
delay_btw_sigs <= '1';
----------------------------------------------------------
-- C
----------------------------------------------------------
when 10 => lcd_data <= "0100";
lcd_rs <= '1';
lcd_rw <= '0';
delay_small <= '1';
when 11 => lcd_e <= '1';
delay_mid <= '1';
when 12 => lcd_e <= '0';
delay_small <= '1';
when 13 => lcd_rs <= '1';
lcd_rw <= '1';
delay_large <= '1';
when 14 => lcd_data <= "0011";
lcd_rs <= '1';
lcd_rw <= '0';
delay_small <= '1';
when 15 => lcd_e <= '1';
delay_mid <= '1';
when 16 => lcd_e <= '0';
delay_small <= '1';
when 17 => lcd_rs <= '1';
lcd_rw <= '1';
delay_btw_sigs <= '1';
----------------------------------------------------------
-- h
----------------------------------------------------------
when 18 => lcd_data <= "0110";
lcd_rs <= '1';
lcd_rw <= '0';
delay_small <= '1';
when 19 => lcd_e <= '1';
delay_mid <= '1';
when 20 => lcd_e <= '0';
delay_small <= '1';
when 21 => lcd_rs <= '1';
lcd_rw <= '1';
delay_large <= '1';
when 22 => lcd_data <= "1000";
lcd_rs <= '1';
lcd_rw <= '0';
delay_small <= '1';
when 23 => lcd_e <= '1';
delay_mid <= '1';
when 24 => lcd_e <= '0';
delay_small <= '1';
when 25 => lcd_rs <= '1';
lcd_rw <= '1';
delay_btw_sigs <= '1';
----------------------------------------------------------
-- :
----------------------------------------------------------
when 26 => lcd_data <= "0011";
lcd_rs <= '1';
lcd_rw <= '0';
delay_small <= '1';
when 27 => lcd_e <= '1';
delay_mid <= '1';
when 28 => lcd_e <= '0';
delay_small <= '1';
when 29 => lcd_rs <= '1';
lcd_rw <= '1';
delay_large <= '1';
when 30 => lcd_data <= "1010";
lcd_rs <= '1';
lcd_rw <= '0';
delay_small <= '1';
when 31 => lcd_e <= '1';
delay_mid <= '1';
when 32 => lcd_e <= '0';
delay_small <= '1';
when 33 => lcd_rs <= '1';
lcd_rw <= '1';
delay_btw_sigs <= '1';
----------------------------------------------------------
-- <space>
----------------------------------------------------------
when 34 => lcd_data <= "0010";
lcd_rs <= '1';
lcd_rw <= '0';
delay_small <= '1';
when 35 => lcd_e <= '1';
delay_mid <= '1';
when 36 => lcd_e <= '0';
delay_small <= '1';
when 37 => lcd_rs <= '1';
lcd_rw <= '1';
delay_large <= '1';
when 38 => lcd_data <= "0000";
lcd_rs <= '1';
lcd_rw <= '0';
delay_small <= '1';
when 39 => lcd_e <= '1';
delay_mid <= '1';
when 40 => lcd_e <= '0';
delay_small <= '1';
when 41 => lcd_rs <= '1';
lcd_rw <= '1';
delay_btw_sigs <= '1';
----------------------------------------------------------
-- channel num
----------------------------------------------------------
when 42 => lcd_data <= "0011";
lcd_rs <= '1';
lcd_rw <= '0';
delay_small <= '1';
when 43 => lcd_e <= '1';
delay_mid <= '1';
when 44 => lcd_e <= '0';
delay_small <= '1';
when 45 => lcd_rs <= '1';
lcd_rw <= '1';
delay_large <= '1';
when 46 => lcd_data <= "00" & current_channel;
lcd_rs <= '1';
lcd_rw <= '0';
delay_small <= '1';
when 47 => lcd_e <= '1';
delay_mid <= '1';
when 48 => lcd_e <= '0';
delay_small <= '1';
when 49 => lcd_rs <= '1';
lcd_rw <= '1';
delay_btw_sigs <= '1';
----------------------------------------------------------
-- newline
----------------------------------------------------------
when 50 => lcd_data <= "1100";
lcd_rs <= '0';
lcd_rw <= '0';
delay_small <= '1';
when 51 => lcd_e <= '1';
delay_mid <= '1';
when 52 => lcd_e <= '0';
delay_small <= '1';
when 53 => lcd_rs <= '1';
lcd_rw <= '1';
delay_large <= '1';
when 54 => lcd_data <= "0000";
lcd_rs <= '0';
lcd_rw <= '0';
delay_small <= '1';
when 55 => lcd_e <= '1';
delay_mid <= '1';
when 56 => lcd_e <= '0';
delay_small <= '1';
when 57 => lcd_rs <= '1';
lcd_rw <= '1';
delay_btw_sigs <= '1';
----------------------------------------------------------
-- mode
----------------------------------------------------------
when 58 => lcd_data <= upper_mode;
lcd_rs <= '1';
lcd_rw <= '0';
delay_small <= '1';
when 59 => lcd_e <= '1';
delay_mid <= '1';
when 60 => lcd_e <= '0';
delay_small <= '1';
when 61 => lcd_rs <= '1';
lcd_rw <= '1';
delay_large <= '1';
when 62 => lcd_data <= lower_mode;
lcd_rs <= '1';
lcd_rw <= '0';
delay_small <= '1';
when 63 => lcd_e <= '1';
delay_mid <= '1';
when 64 => lcd_e <= '0';
delay_small <= '1';
when 65 => lcd_rs <= '1';
lcd_rw <= '1';
delay_btw_sigs <= '1';
----------------------------------------------------------
-- =
----------------------------------------------------------
when 66 => lcd_data <= "0011";
lcd_rs <= '1';
lcd_rw <= '0';
delay_small <= '1';
when 67 => lcd_e <= '1';
delay_mid <= '1';
when 68 => lcd_e <= '0';
delay_small <= '1';
when 69 => lcd_rs <= '1';
lcd_rw <= '1';
delay_large <= '1';
when 70 => lcd_data <= "1101";
lcd_rs <= '1';
lcd_rw <= '0';
delay_small <= '1';
when 71 => lcd_e <= '1';
delay_mid <= '1';
when 72 => lcd_e <= '0';
delay_small <= '1';
when 73 => lcd_rs <= '1';
lcd_rw <= '1';
delay_btw_sigs <= '1';
----------------------------------------------------------
-- <p1>
----------------------------------------------------------
when 74 => lcd_data <= upper_val1;
lcd_rs <= '1';
lcd_rw <= '0';
delay_small <= '1';
when 75 => lcd_e <= '1';
delay_mid <= '1';
when 76 => lcd_e <= '0';
delay_small <= '1';
when 77 => lcd_rs <= '1';
lcd_rw <= '1';
delay_large <= '1';
when 78 => lcd_data <= lower_val1;
lcd_rs <= '1';
lcd_rw <= '0';
delay_small <= '1';
when 79 => lcd_e <= '1';
delay_mid <= '1';
when 80 => lcd_e <= '0';
delay_small <= '1';
when 81 => lcd_rs <= '1';
lcd_rw <= '1';
delay_btw_sigs <= '1';
----------------------------------------------------------
-- <p2>
----------------------------------------------------------
when 82 => lcd_data <= upper_val2;
lcd_rs <= '1';
lcd_rw <= '0';
delay_small <= '1';
when 83 => lcd_e <= '1';
delay_mid <= '1';
when 84 => lcd_e <= '0';
delay_small <= '1';
when 85 => lcd_rs <= '1';
lcd_rw <= '1';
delay_large <= '1';
when 86 => lcd_data <= lower_val2;
lcd_rs <= '1';
lcd_rw <= '0';
delay_small <= '1';
when 87 => lcd_e <= '1';
delay_mid <= '1';
when 88 => lcd_e <= '0';
delay_small <= '1';
when 89 => lcd_rs <= '1';
lcd_rw <= '1';
delay_btw_sigs <= '1';
----------------------------------------------------------
-- <p3>
----------------------------------------------------------
when 90 => lcd_data <= upper_val3;
lcd_rs <= '1';
lcd_rw <= '0';
delay_small <= '1';
when 91 => lcd_e <= '1';
delay_mid <= '1';
when 92 => lcd_e <= '0';
delay_small <= '1';
when 93 => lcd_rs <= '1';
lcd_rw <= '1';
delay_large <= '1';
when 94 => lcd_data <= lower_val3;
lcd_rs <= '1';
lcd_rw <= '0';
delay_small <= '1';
when 95 => lcd_e <= '1';
delay_mid <= '1';
when 96 => lcd_e <= '0';
delay_small <= '1';
when 97 => lcd_rs <= '1';
lcd_rw <= '1';
delay_btw_sigs <= '1';
----------------------------------------------------------
when others => lcd_data <= "0000";
delay_huge <= '1';
----------------------------------------------------------
end case;
elsif(delay_small = '1') then
delay_small_count <= delay_small_count + 1;
if(delay_small_count = "111") then
delay_small <= '0';
end if;
elsif(delay_mid = '1') then
delay_mid_count <= delay_mid_count + 1;
if(delay_mid_count = "11111") then
delay_mid <= '0';
end if;
elsif(delay_large = '1') then
delay_large_count <= delay_large_count + 1;
if(delay_large_count = "11111111") then
delay_large <= '0';
end if;
elsif(delay_btw_sigs = '1') then
delay_btw_sigs_count <= delay_btw_sigs_count + 1;
if(delay_btw_sigs_count = "111111111111") then
delay_btw_sigs <= '0';
end if;
elsif(delay_huge = '1') then
delay_huge_count <= delay_huge_count + 1;
if(delay_huge_count = "111111111111111111") then
delay_huge <= '0';
end if;
else
delay_small <= '0';
delay_mid <= '0';
delay_large <= '0';
delay_btw_sigs <= '0';
delay_huge <= '0';
end if;
end if;
end process;
end Behavioral;
|
mit
|
Predator01/Levi
|
PF_Robot_Sumo/Motor.vhd
|
1
|
2712
|
----------------------------------------------------------------------------------
-- Company: ITESM CQ
-- Engineer: Miguel Gonzalez A01203712
--
-- Create Date: 10:39:53 11/10/2015
-- Design Name:
-- Module Name: Motor - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Motor module that control 1 motor
--
-- Dependencies:
--
-- Revision:
-- Revision 0.0.1 - File Created
-- Revision 1.0.0 - Motor Implementation
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.PKG_ROBOT_SUMO.all;
entity Motor is
Port (
in_Rst : in STD_LOGIC;
in_Clk : in STD_LOGIC;
in_Action_m : in STD_LOGIC_VECTOR(1 downto 0);
out_motor : out STD_LOGIC);
end Motor;
architecture Behavioral of Motor is
-- Componentes del modulo
-- Comp: U1 Divisor de frequencia 100/1
component Freq_Div
port (
in_Rst : in STD_LOGIC;
in_Clk : in STD_LOGIC;
out_time_base : out STD_LOGIC);
end component;
-- Comp: U2 State Register for motor
component State_Reg_Motor
port (
in_clk : in STD_LOGIC;
in_time_base : in STD_LOGIC;
in_rst : in STD_LOGIC;
in_next_state : in motor_state_values;
in_state_duration : in integer;
out_pres_state : out motor_state_values);
end component;
-- Comp: U3 Finite State Machine motor
component FSM_motor
port (
in_pres_state : in motor_state_values;
in_th : in integer;
in_tl : in integer;
out_next_state: out motor_state_values;
state_duration : out integer);
end component;
-- Comp : U4 Output
component Output_motor
port (
in_pres_state : in motor_state_values;
out_motor : out STD_LOGIC);
end component;
-- Comp : U5 Equation_motor
component Equation_motor
port (
in_action : in STD_LOGIC_VECTOR(1 downto 0);
out_th : out integer;
out_tl : out integer);
end component;
-- seniales embebidas
-- 1 bit
signal time_base : STD_LOGIC;
-- 2 o mas bits
-- of types
signal pres_state, next_state: motor_state_values;
-- integers
signal tH : integer range 0 to MOTOR_MAX;
signal tL : integer range 0 to MOTOR_MAX;
signal curr_state_duration : integer range 0 to MOTOR_MAX;
begin
-- Instanciar componentes
U1_1 : Freq_Div
port map(in_rst, in_clk, time_base);
U1_2 : State_Reg_Motor
port map(
in_clk,
time_base,
in_rst,
next_state,
curr_state_duration,
pres_state);
U1_5 : Equation_motor
port map(in_Action_m, tH, tL);
U1_3 : FSM_motor
port map(pres_state, tH, tL, next_state,
curr_state_duration);
U1_4 : Output_motor
port map(pres_state, out_motor);
end Behavioral;
|
mit
|
Predator01/Levi
|
P29_Servo_Control/P23_Servo_Control/UKStopLight.vhd
|
3
|
3158
|
----------------------------------------------------------------------------------
-- Company: ITESM
-- Engineer: Alam (formely Rick)
--
-- Create Date: 11:42:22 11/04/2015
-- Design Name:
-- Module Name: UKStopLight - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies: Controlling a Stop Light; the kind found
-- in the United Kingdom.
-- Moore FSM will be used
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity ServoControl is
Port ( Clk : in STD_LOGIC;
Rst : in STD_LOGIC;
Servo : out STD_LOGIC);
end ServoControl;
architecture Behavioral of ServoControl is
-- State definition
type state_values is (HIGH,LOW);
signal pres_state, next_state : state_values;
-- Define the State duration times for the variable
-- time duration FSM
-- All times are expressed in microseconds
constant tH : integer := 1500;
constant tL : integer := 18500;
-- Define signals used by frequency divider
constant Fosc : integer := 100_000_000; --Frecuencia del oscilador de Nexys3
constant Fdiv : integer := 1_000_000; --Frecuencia deseada del divisor
constant CtaMax : integer := Fosc / Fdiv; --Cuenta maxima a la que hay que llegar
signal Cont : integer range 0 to CtaMax;
signal TimeBase : STD_LOGIC;
-- Define a second counter, used to determine how much
-- time has been spent in a State
signal SecondCount : integer range 0 to tL;
-- Define a signal that gives the amount of time
-- to be spent in a State
signal StateDuration : integer range 0 to tL;
begin
-- Generate a TimeBase of one second
freqdiv: process (Rst, Clk)
begin
if Rst = '1' then
Cont <= 0;
elsif (rising_edge(Clk)) then
if Cont = CtaMax then
Cont <= 0;
TimeBase <= '1';
else
Cont <= Cont + 1;
TimeBase <= '0';
end if;
end if;
end process freqdiv;
statereg : process(Clk,TimeBase,Rst)
begin
if Rst = '1' then
pres_state <= HIGH;
SecondCount <= 0;
elsif (rising_edge(Clk) and TimeBase = '1') then
if SecondCount = StateDuration-1 then
pres_state <= next_state;
SecondCount <= 0;
else
SecondCount <= SecondCount + 1;
end if;
end if;
end process statereg;
fsm : process (pres_state)
begin
case (pres_state) is
when HIGH =>
next_state <= LOW;
StateDuration <= tH;
when LOW =>
next_state <= HIGH;
StateDuration <= tL;
when others =>
next_state <= LOW;
StateDuration <= tH;
end case;
end process fsm;
output : process (pres_state)
begin
case (pres_state) is
when HIGH =>
Servo <= '1';
when LOW =>
Servo <= '0';
when others =>
Servo <= '1';
end case;
end process output;
end Behavioral;
|
mit
|
emusan/emu_awg
|
src/spi_buffer.vhd
|
1
|
2247
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:53:27 04/04/2014
-- Design Name:
-- Module Name: spi_buffer - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity spi_buffer is
port(
sine_in: in std_logic_vector(47 downto 0); -- ch1 (11 downto 0) ch2 (23 downto 12) ch3 (35 downto 24) ch4 (47 downto 36)
square_in: in std_logic_vector(47 downto 0); -- ch1 (11 downto 0) ch2 (23 downto 12) ch3 (35 downto 24) ch4 (47 downto 36)
ch_select: in std_logic_vector(3 downto 0);
spi_sine_out: out std_logic_vector(11 downto 0);
spi_ready: in std_logic;
channel: in std_logic_vector(1 downto 0);
clk: in std_logic
);
end spi_buffer;
architecture Behavioral of spi_buffer is
begin
process(clk)
begin
if(rising_edge(clk)) then
if(spi_ready = '1') then
case channel is
when "00" =>
if(ch_select(0) = '0') then
spi_sine_out <= sine_in(11 downto 0);
else
spi_sine_out <= square_in(11 downto 0);
end if;
when "01" =>
if(ch_select(1) = '0') then
spi_sine_out <= sine_in(23 downto 12);
else
spi_sine_out <= square_in(23 downto 12);
end if;
when "10" =>
if(ch_select(2) = '0') then
spi_sine_out <= sine_in(35 downto 24);
else
spi_sine_out <= square_in(35 downto 24);
end if;
when "11" =>
if(ch_select(3) = '0') then
spi_sine_out <= sine_in(47 downto 36);
else
spi_sine_out <= square_in(47 downto 36);
end if;
when others => spi_sine_out <= (others => '0');
end case;
end if;
end if;
end process;
end Behavioral;
|
mit
|
emusan/emu_awg
|
src/ramlut.vhd
|
1
|
1805
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:10:50 03/29/2014
-- Design Name:
-- Module Name: ramlut - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ramlut is
generic(
sine_length_bits: integer := 10
);
port(
x_in: in std_logic_vector(sine_length_bits-1 downto 0);
sine_out: out std_logic_vector(11 downto 0); -- 12 bit output for DAC
clk: in std_logic
);
end ramlut;
architecture Behavioral of ramlut is
type sine_mem_type is array (0 to (2**sine_length_bits) - 1) of unsigned(11 downto 0);
function initialize_ram return sine_mem_type is
variable temp_mem: sine_mem_type;
constant x_scale: real := 0.000976;
constant y_adjust: real := 1.0;
constant y_scale: real := 2047.0;
begin
for i in 0 to (2**sine_length_bits) - 1 loop
temp_mem(i) := to_unsigned(integer((sin(real(i) * 2.0 * MATH_PI * x_scale) + y_adjust) * y_scale),12);
end loop;
return temp_mem;
end;
constant sine_mem: sine_mem_type := initialize_ram;
begin
process(clk)
begin
if(rising_edge(clk)) then
sine_out <= std_logic_vector(sine_mem(to_integer(unsigned(x_in))));
end if;
end process;
end Behavioral;
|
mit
|
Predator01/Levi
|
P04_SN74LS138/SN74LS138_TB.vhd
|
1
|
3335
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:58:33 09/02/2015
-- Design Name:
-- Module Name: D:/ProySisDigAva/Levi/P04_SN74LS138/SN74LS138_TB.vhd
-- Project Name: P04_SN74LS138
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: SN74LS138
--
-- Dependencies: This is Test Bench for a 74LS138 Design
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY SN74LS138_TB IS
END SN74LS138_TB;
ARCHITECTURE behavior OF SN74LS138_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT SN74LS138
PORT(
A : IN std_logic;
B : IN std_logic;
C : IN std_logic;
G2A : IN std_logic;
G2B : IN std_logic;
G1 : IN std_logic;
Y : OUT std_logic_vector(0 to 7));
END COMPONENT;
--Inputs
signal A : std_logic := '0';
signal B : std_logic := '0';
signal C : std_logic := '0';
signal G2A : std_logic := '0';
signal G2B : std_logic := '0';
signal G1 : std_logic := '0';
--Outputs
signal Y : std_logic_vector(0 to 7);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
--constant <clock>_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: SN74LS138 PORT MAP (
A => A,
B => B,
C => C,
G2A => G2A,
G2B => G2B,
G1 => G1,
Y => Y
);
-- -- Clock process definitions
-- <clock>_process :process
-- begin
-- <clock> <= '0';
-- wait for <clock>_period/2;
-- <clock> <= '1';
-- wait for <clock>_period/2;
-- end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
-- wait for <clock>_period*10;
-- insert stimulus here
-- Test cases for G2 = 1
G2A <= '0'; G2B <= '1';
wait for 100 ns;
G2A <= '1'; G2B <= '0';
wait for 100 ns;
G2A <= '1'; G2B <= '1';
wait for 100 ns;
-- Test case for G1 = 1
G1 <= '0';
wait for 100 ns;
-- Test cases when enable
G1 <= '1'; G2A <= '0'; G2B <= '0';
C <= '0'; B <= '0'; A <= '0'; -- 0
wait for 100 ns;
C <= '0'; B <= '0'; A <= '1'; -- 1
wait for 100 ns;
C <= '0'; B <= '1'; A <= '0'; -- 2
wait for 100 ns;
C <= '0'; B <= '1'; A <= '1'; -- 3
wait for 100 ns;
C <= '1'; B <= '0'; A <= '0'; -- 4
wait for 100 ns;
C <= '1'; B <= '0'; A <= '1'; -- 5
wait for 100 ns;
C <= '1'; B <= '1'; A <= '0'; -- 6
wait for 100 ns;
C <= '1'; B <= '1'; A <= '1'; --7
wait;
end process;
END;
|
mit
|
Predator01/Levi
|
P09_Binary_to_Gray_Code_Converter/Binary_to_Gray_Code_Converter.vhd
|
1
|
1217
|
----------------------------------------------------------------------------------
-- Company: ITESM
-- Engineer: Miguel Gonzalez A01203712
--
-- Create Date: 15:49:32 09/08/2015
-- Design Name:
-- Module Name: Binary_to_Gray_Code_Converter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: A generic Binary to Gray Code Converter
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Binary_to_Gray_Code_Converter is
generic (n : Integer := 4);
Port ( Binary : in STD_LOGIC_VECTOR (n-1 downto 0);
Gray : out STD_LOGIC_VECTOR (n-1 downto 0));
end Binary_to_Gray_Code_Converter;
architecture Behavioral of Binary_to_Gray_Code_Converter is
begin
--First
Gray(n-1) <= Binary(n-1);
Gray(n-2 downto 0) <= Binary(n-2 downto 0) xor Binary(n-1 downto 1);
-- Generic
-- Gray(n-1) <= Binary(n-1);
-- xor_for:
-- for index in n-2 downto 0 generate
-- begin
-- Gray(index) <= Binary(index+1) xor Binary(index);
-- end generate;
end Behavioral;
|
mit
|
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