repo_name
stringlengths 6
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| path
stringlengths 5
236
| copies
stringclasses 54
values | size
stringlengths 1
8
| content
stringlengths 0
1.04M
⌀ | license
stringclasses 15
values |
|---|---|---|---|---|---|
abidrahmank/MyRoughWork
|
vitbi/input_mem.vhd
|
1
|
2143
|
----------------------------------------------------
-------CODE FOR INRAM(COMMENTED TO WORK AS A ROM)-----
----------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.all;
--library UNISIM;
--use UNISIM.VComponents.all;
----------------------------------------------------
entity INPUT_MEM is
port (CLK ,reset : in std_logic;
--CLR : in std_logic;
--WE : in std_logic;
--EN : in std_logic;
--INPUT_DI : in std_logic_vector(1 downto 0);
INPUT_DO : out std_logic_vector(1 downto 0));
end INPUT_MEM;
----------------------------------------------------
architecture inp_memarch of INPUT_MEM is
type INRAM_type is array (0 TO 15) of std_logic_vector (1 downto 0);
signal INADDR: std_logic_vector (3 downto 0);
signal INRAM: INRAM_type:= ("11",
"10",
"11",
"11",
"01",
"01",
"11",
"11",
"10",
"11",
"11",
"01",
"01",
"11",
"00",
"00");
----------------------------------------------------
component MOD16UP is
port(CLK:in std_logic;
reset :in std_logic;
Q_UP : out std_logic_vector(3 downto 0));
end component;
----------------------------------------------------
begin
counter: MOD16UP port map (CLK,reset,INADDR);----GIVE CLR IN SENSITIVITY LIST IF IT IS USED IN THE CIRCUIT
process (CLK,reset)
begin
if (reset='1') then
INPUT_DO <= "00" ;
elsif CLK'event and CLK = '1' then
--if EN = '1' then
--- if WE = '1' then
-- INRAM(conv_integer(INADDR)) <= INPUT_DI;----(uncomment id used as INRAM)
--end if;
INPUT_DO <= INRAM(conv_integer(INADDR+1)) ;
--- end if;
--end if;
end if;
end process;
end inp_memarch;
----------------------------------------------------
----------------------------------------------------
----------------------------------------------------
|
mit
|
ssabogal/nocturnal
|
ip_repo/router/src/router_struct_tb.vhd
|
1
|
10460
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity router_struct_tb is
end entity;
architecture structure of router_struct_tb is
component router_struct is
generic (
ADDR_X : natural range 0 to 3 := 0;
ADDR_Y : natural range 0 to 3 := 0;
N_INST : boolean := true;
S_INST : boolean := true;
E_INST : boolean := true;
W_INST : boolean := true
);
port (
CLOCK : in std_logic;
RESET : in std_logic;
-- local
L_DIN : in std_logic_vector(31 downto 0);
L_VIN : in std_logic;
L_RIN : out std_logic;
L_DOUT : out std_logic_vector(31 downto 0);
L_VOUT : out std_logic;
L_ROUT : in std_logic;
-- north
N_DIN : in std_logic_vector(31 downto 0);
N_VIN : in std_logic;
N_RIN : out std_logic;
N_DOUT : out std_logic_vector(31 downto 0);
N_VOUT : out std_logic;
N_ROUT : in std_logic;
-- south
S_DIN : in std_logic_vector(31 downto 0);
S_VIN : in std_logic;
S_RIN : out std_logic;
S_DOUT : out std_logic_vector(31 downto 0);
S_VOUT : out std_logic;
S_ROUT : in std_logic;
-- east
E_DIN : in std_logic_vector(31 downto 0);
E_VIN : in std_logic;
E_RIN : out std_logic;
E_DOUT : out std_logic_vector(31 downto 0);
E_VOUT : out std_logic;
E_ROUT : in std_logic;
-- west
W_DIN : in std_logic_vector(31 downto 0);
W_VIN : in std_logic;
W_RIN : out std_logic;
W_DOUT : out std_logic_vector(31 downto 0);
W_VOUT : out std_logic;
W_ROUT : in std_logic
);
end component;
constant ADDR_X : natural range 0 to 3 := 1;
constant ADDR_Y : natural range 0 to 3 := 1;
constant N_INST : boolean := true;
constant S_INST : boolean := true;
constant E_INST : boolean := true;
constant W_INST : boolean := true;
signal CLOCK : std_logic := '0';
signal RESET : std_logic := '0';
-- local
signal L_DIN : std_logic_vector(31 downto 0) := (others => 'X');
signal L_VIN : std_logic := '0';
signal L_RIN : std_logic;
signal L_DOUT : std_logic_vector(31 downto 0);
signal L_VOUT : std_logic;
signal L_ROUT : std_logic := '0';
-- north
signal N_DIN : std_logic_vector(31 downto 0) := (others => 'X');
signal N_VIN : std_logic := '0';
signal N_RIN : std_logic;
signal N_DOUT : std_logic_vector(31 downto 0);
signal N_VOUT : std_logic;
signal N_ROUT : std_logic := '0';
-- south
signal S_DIN : std_logic_vector(31 downto 0) := (others => 'X');
signal S_VIN : std_logic := '0';
signal S_RIN : std_logic;
signal S_DOUT : std_logic_vector(31 downto 0);
signal S_VOUT : std_logic;
signal S_ROUT : std_logic := '0';
-- east
signal E_DIN : std_logic_vector(31 downto 0) := (others => 'X');
signal E_VIN : std_logic := '0';
signal E_RIN : std_logic;
signal E_DOUT : std_logic_vector(31 downto 0);
signal E_VOUT : std_logic;
signal E_ROUT : std_logic := '0';
-- west
signal W_DIN : std_logic_vector(31 downto 0) := (others => 'X');
signal W_VIN : std_logic := '0';
signal W_RIN : std_logic;
signal W_DOUT : std_logic_vector(31 downto 0);
signal W_VOUT : std_logic;
signal W_ROUT : std_logic := '0';
constant PKT_SIZE : positive := 8;
begin
UUT: router_struct
generic map (
ADDR_X => ADDR_X,
ADDR_Y => ADDR_Y,
N_INST => N_INST,
S_INST => S_INST,
E_INST => E_INST,
W_INST => W_INST
)
port map (
CLOCK => CLOCK,
RESET => RESET,
-- local
L_DIN => L_DIN,
L_VIN => L_VIN,
L_RIN => L_RIN,
L_DOUT => L_DOUT,
L_VOUT => L_VOUT,
L_ROUT => L_ROUT,
-- north
N_DIN => N_DIN,
N_VIN => N_VIN,
N_RIN => N_RIN,
N_DOUT => N_DOUT,
N_VOUT => N_VOUT,
N_ROUT => N_ROUT,
-- south
S_DIN => S_DIN,
S_VIN => S_VIN,
S_RIN => S_RIN,
S_DOUT => S_DOUT,
S_VOUT => S_VOUT,
S_ROUT => S_ROUT,
-- east
E_DIN => E_DIN,
E_VIN => E_VIN,
E_RIN => E_RIN,
E_DOUT => E_DOUT,
E_VOUT => E_VOUT,
E_ROUT => E_ROUT,
-- west
W_DIN => W_DIN,
W_VIN => W_VIN,
W_RIN => W_RIN,
W_DOUT => W_DOUT,
W_VOUT => W_VOUT,
W_ROUT => W_ROUT
);
CLOCK <= not CLOCK after 5 ns;
RESET <= '1', '0' after 20 ns;
-- local
L_PROC: process
begin
wait for 100 ns;
L_DIN <= X"00000000"; --west
L_VIN <= '1';
wait until rising_edge(CLOCK);
L_DIN <= X"10000000";
L_VIN <= '1';
wait until rising_edge(CLOCK);
L_DIN <= std_logic_vector(to_unsigned(PKT_SIZE, 32));
L_VIN <= '1';
wait until rising_edge(CLOCK);
for i in 1 to PKT_SIZE - 3 loop
L_DIN <= std_logic_vector(to_unsigned(i, 32));
L_VIN <= '1';
wait until rising_edge(CLOCK);
end loop;
L_DIN <= (others => 'X');
L_VIN <= '0';
wait for 200 ns;
L_DIN <= X"50000001"; --local
L_VIN <= '1';
wait until rising_edge(CLOCK);
L_DIN <= X"10000000";
L_VIN <= '1';
wait until rising_edge(CLOCK);
L_DIN <= std_logic_vector(to_unsigned(PKT_SIZE, 32));
L_VIN <= '1';
wait until rising_edge(CLOCK);
for i in 1 to PKT_SIZE - 3 loop
L_DIN <= std_logic_vector(to_unsigned(i, 32));
L_VIN <= '1';
wait until rising_edge(CLOCK);
end loop;
L_DIN <= (others => 'X');
L_VIN <= '0';
wait;
end process;
-- north
N_PROC: process
begin
wait for 100 ns;
N_DIN <= X"F0000000"; --east
N_VIN <= '1';
wait until rising_edge(CLOCK);
N_DIN <= X"10000000";
N_VIN <= '1';
wait until rising_edge(CLOCK);
N_DIN <= std_logic_vector(to_unsigned(PKT_SIZE, 32));
N_VIN <= '1';
wait until rising_edge(CLOCK);
for i in 1 to PKT_SIZE - 3 loop
N_DIN <= std_logic_vector(to_unsigned(i, 32));
N_VIN <= '1';
wait until rising_edge(CLOCK);
end loop;
N_DIN <= (others => 'X');
N_VIN <= '0';
wait for 200 ns;
N_DIN <= X"00000001"; --west
N_VIN <= '1';
wait until rising_edge(CLOCK);
N_DIN <= X"10000000";
N_VIN <= '1';
wait until rising_edge(CLOCK);
N_DIN <= std_logic_vector(to_unsigned(PKT_SIZE, 32));
N_VIN <= '1';
wait until rising_edge(CLOCK);
for i in 1 to PKT_SIZE - 3 loop
N_DIN <= std_logic_vector(to_unsigned(i, 32));
N_VIN <= '1';
wait until rising_edge(CLOCK);
end loop;
N_DIN <= (others => 'X');
N_VIN <= '0';
wait;
end process;
-- south
S_PROC: process
begin
wait for 100 ns;
S_DIN <= X"70000000"; --north
S_VIN <= '1';
wait until rising_edge(CLOCK);
S_DIN <= X"10000000";
S_VIN <= '1';
wait until rising_edge(CLOCK);
S_DIN <= std_logic_vector(to_unsigned(PKT_SIZE, 32));
S_VIN <= '1';
wait until rising_edge(CLOCK);
for i in 1 to PKT_SIZE - 3 loop
S_DIN <= std_logic_vector(to_unsigned(i, 32));
S_VIN <= '1';
wait until rising_edge(CLOCK);
end loop;
S_DIN <= (others => 'X');
S_VIN <= '0';
wait for 200 ns;
S_DIN <= X"40000001"; --south
S_VIN <= '1';
wait until rising_edge(CLOCK);
S_DIN <= X"10000000";
S_VIN <= '1';
wait until rising_edge(CLOCK);
S_DIN <= std_logic_vector(to_unsigned(PKT_SIZE, 32));
S_VIN <= '1';
wait until rising_edge(CLOCK);
for i in 1 to PKT_SIZE - 3 loop
S_DIN <= std_logic_vector(to_unsigned(i, 32));
S_VIN <= '1';
wait until rising_edge(CLOCK);
end loop;
S_DIN <= (others => 'X');
S_VIN <= '0';
wait;
end process;
-- east
E_PROC: process
begin
wait for 100 ns;
E_DIN <= X"40000000"; --south
E_VIN <= '1';
wait until rising_edge(CLOCK);
E_DIN <= X"10000000";
E_VIN <= '1';
wait until rising_edge(CLOCK);
E_DIN <= std_logic_vector(to_unsigned(PKT_SIZE, 32));
E_VIN <= '1';
wait until rising_edge(CLOCK);
for i in 1 to PKT_SIZE - 3 loop
E_DIN <= std_logic_vector(to_unsigned(i, 32));
E_VIN <= '1';
wait until rising_edge(CLOCK);
end loop;
E_DIN <= (others => 'X');
E_VIN <= '0';
wait for 200 ns;
E_DIN <= X"70000001"; --north
E_VIN <= '1';
wait until rising_edge(CLOCK);
E_DIN <= X"10000000";
E_VIN <= '1';
wait until rising_edge(CLOCK);
E_DIN <= std_logic_vector(to_unsigned(PKT_SIZE, 32));
E_VIN <= '1';
wait until rising_edge(CLOCK);
for i in 1 to PKT_SIZE - 3 loop
E_DIN <= std_logic_vector(to_unsigned(i, 32));
E_VIN <= '1';
wait until rising_edge(CLOCK);
end loop;
E_DIN <= (others => 'X');
E_VIN <= '0';
wait;
end process;
-- west
W_PROC: process
begin
wait for 100 ns;
W_DIN <= X"50000000"; --local
W_VIN <= '1';
wait until rising_edge(CLOCK);
W_DIN <= X"10000000";
W_VIN <= '1';
wait until rising_edge(CLOCK);
W_DIN <= std_logic_vector(to_unsigned(PKT_SIZE, 32));
W_VIN <= '1';
wait until rising_edge(CLOCK);
for i in 1 to PKT_SIZE - 3 loop
W_DIN <= std_logic_vector(to_unsigned(i, 32));
W_VIN <= '1';
wait until rising_edge(CLOCK);
end loop;
W_DIN <= (others => 'X');
W_VIN <= '0';
wait for 200 ns;
W_DIN <= X"F0000001"; --east
W_VIN <= '1';
wait until rising_edge(CLOCK);
W_DIN <= X"10000000";
W_VIN <= '1';
wait until rising_edge(CLOCK);
W_DIN <= std_logic_vector(to_unsigned(PKT_SIZE, 32));
W_VIN <= '1';
wait until rising_edge(CLOCK);
for i in 1 to PKT_SIZE - 3 loop
W_DIN <= std_logic_vector(to_unsigned(i, 32));
W_VIN <= '1';
wait until rising_edge(CLOCK);
end loop;
W_DIN <= (others => 'X');
W_VIN <= '0';
wait;
end process;
-- output
O_PROC: process
begin
wait for 500 ns;
for i in 1 to 8 loop
L_ROUT <= '1';
N_ROUT <= '1';
S_ROUT <= '1';
E_ROUT <= '1';
W_ROUT <= '1';
wait until rising_edge(CLOCK);
end loop;
L_ROUT <= '0';
N_ROUT <= '0';
S_ROUT <= '0';
E_ROUT <= '0';
W_ROUT <= '0';
wait for 200 ns;
for i in 1 to 8 loop
L_ROUT <= '1';
N_ROUT <= '1';
S_ROUT <= '1';
E_ROUT <= '1';
W_ROUT <= '1';
wait until rising_edge(CLOCK);
end loop;
L_ROUT <= '0';
N_ROUT <= '0';
S_ROUT <= '0';
E_ROUT <= '0';
W_ROUT <= '0';
wait;
end process;
end architecture;
|
mit
|
ssabogal/nocturnal
|
noc_dev/noc_dev.srcs/sources_1/bd/sys/ip/sys_axi_nic_10_2/src/FIFO_32x4K/synth/FIFO_32x4K.vhd
|
9
|
39096
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fifo_generator:13.1
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fifo_generator_v13_1_3;
USE fifo_generator_v13_1_3.fifo_generator_v13_1_3;
ENTITY FIFO_32x4K IS
PORT (
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(12 DOWNTO 0)
);
END FIFO_32x4K;
ARCHITECTURE FIFO_32x4K_arch OF FIFO_32x4K IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF FIFO_32x4K_arch: ARCHITECTURE IS "yes";
COMPONENT fifo_generator_v13_1_3 IS
GENERIC (
C_COMMON_CLOCK : INTEGER;
C_SELECT_XPM : INTEGER;
C_COUNT_TYPE : INTEGER;
C_DATA_COUNT_WIDTH : INTEGER;
C_DEFAULT_VALUE : STRING;
C_DIN_WIDTH : INTEGER;
C_DOUT_RST_VAL : STRING;
C_DOUT_WIDTH : INTEGER;
C_ENABLE_RLOCS : INTEGER;
C_FAMILY : STRING;
C_FULL_FLAGS_RST_VAL : INTEGER;
C_HAS_ALMOST_EMPTY : INTEGER;
C_HAS_ALMOST_FULL : INTEGER;
C_HAS_BACKUP : INTEGER;
C_HAS_DATA_COUNT : INTEGER;
C_HAS_INT_CLK : INTEGER;
C_HAS_MEMINIT_FILE : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_RD_DATA_COUNT : INTEGER;
C_HAS_RD_RST : INTEGER;
C_HAS_RST : INTEGER;
C_HAS_SRST : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_VALID : INTEGER;
C_HAS_WR_ACK : INTEGER;
C_HAS_WR_DATA_COUNT : INTEGER;
C_HAS_WR_RST : INTEGER;
C_IMPLEMENTATION_TYPE : INTEGER;
C_INIT_WR_PNTR_VAL : INTEGER;
C_MEMORY_TYPE : INTEGER;
C_MIF_FILE_NAME : STRING;
C_OPTIMIZATION_MODE : INTEGER;
C_OVERFLOW_LOW : INTEGER;
C_PRELOAD_LATENCY : INTEGER;
C_PRELOAD_REGS : INTEGER;
C_PRIM_FIFO_TYPE : STRING;
C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
C_PROG_EMPTY_TYPE : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
C_PROG_FULL_TYPE : INTEGER;
C_RD_DATA_COUNT_WIDTH : INTEGER;
C_RD_DEPTH : INTEGER;
C_RD_FREQ : INTEGER;
C_RD_PNTR_WIDTH : INTEGER;
C_UNDERFLOW_LOW : INTEGER;
C_USE_DOUT_RST : INTEGER;
C_USE_ECC : INTEGER;
C_USE_EMBEDDED_REG : INTEGER;
C_USE_PIPELINE_REG : INTEGER;
C_POWER_SAVING_MODE : INTEGER;
C_USE_FIFO16_FLAGS : INTEGER;
C_USE_FWFT_DATA_COUNT : INTEGER;
C_VALID_LOW : INTEGER;
C_WR_ACK_LOW : INTEGER;
C_WR_DATA_COUNT_WIDTH : INTEGER;
C_WR_DEPTH : INTEGER;
C_WR_FREQ : INTEGER;
C_WR_PNTR_WIDTH : INTEGER;
C_WR_RESPONSE_LATENCY : INTEGER;
C_MSGON_VAL : INTEGER;
C_ENABLE_RST_SYNC : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_ERROR_INJECTION_TYPE : INTEGER;
C_SYNCHRONIZER_STAGE : INTEGER;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_HAS_AXI_WR_CHANNEL : INTEGER;
C_HAS_AXI_RD_CHANNEL : INTEGER;
C_HAS_SLAVE_CE : INTEGER;
C_HAS_MASTER_CE : INTEGER;
C_ADD_NGC_CONSTRAINT : INTEGER;
C_USE_COMMON_OVERFLOW : INTEGER;
C_USE_COMMON_UNDERFLOW : INTEGER;
C_USE_DEFAULT_SETTINGS : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_AXI_ADDR_WIDTH : INTEGER;
C_AXI_DATA_WIDTH : INTEGER;
C_AXI_LEN_WIDTH : INTEGER;
C_AXI_LOCK_WIDTH : INTEGER;
C_HAS_AXI_ID : INTEGER;
C_HAS_AXI_AWUSER : INTEGER;
C_HAS_AXI_WUSER : INTEGER;
C_HAS_AXI_BUSER : INTEGER;
C_HAS_AXI_ARUSER : INTEGER;
C_HAS_AXI_RUSER : INTEGER;
C_AXI_ARUSER_WIDTH : INTEGER;
C_AXI_AWUSER_WIDTH : INTEGER;
C_AXI_WUSER_WIDTH : INTEGER;
C_AXI_BUSER_WIDTH : INTEGER;
C_AXI_RUSER_WIDTH : INTEGER;
C_HAS_AXIS_TDATA : INTEGER;
C_HAS_AXIS_TID : INTEGER;
C_HAS_AXIS_TDEST : INTEGER;
C_HAS_AXIS_TUSER : INTEGER;
C_HAS_AXIS_TREADY : INTEGER;
C_HAS_AXIS_TLAST : INTEGER;
C_HAS_AXIS_TSTRB : INTEGER;
C_HAS_AXIS_TKEEP : INTEGER;
C_AXIS_TDATA_WIDTH : INTEGER;
C_AXIS_TID_WIDTH : INTEGER;
C_AXIS_TDEST_WIDTH : INTEGER;
C_AXIS_TUSER_WIDTH : INTEGER;
C_AXIS_TSTRB_WIDTH : INTEGER;
C_AXIS_TKEEP_WIDTH : INTEGER;
C_WACH_TYPE : INTEGER;
C_WDCH_TYPE : INTEGER;
C_WRCH_TYPE : INTEGER;
C_RACH_TYPE : INTEGER;
C_RDCH_TYPE : INTEGER;
C_AXIS_TYPE : INTEGER;
C_IMPLEMENTATION_TYPE_WACH : INTEGER;
C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
C_IMPLEMENTATION_TYPE_RACH : INTEGER;
C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
C_APPLICATION_TYPE_WACH : INTEGER;
C_APPLICATION_TYPE_WDCH : INTEGER;
C_APPLICATION_TYPE_WRCH : INTEGER;
C_APPLICATION_TYPE_RACH : INTEGER;
C_APPLICATION_TYPE_RDCH : INTEGER;
C_APPLICATION_TYPE_AXIS : INTEGER;
C_PRIM_FIFO_TYPE_WACH : STRING;
C_PRIM_FIFO_TYPE_WDCH : STRING;
C_PRIM_FIFO_TYPE_WRCH : STRING;
C_PRIM_FIFO_TYPE_RACH : STRING;
C_PRIM_FIFO_TYPE_RDCH : STRING;
C_PRIM_FIFO_TYPE_AXIS : STRING;
C_USE_ECC_WACH : INTEGER;
C_USE_ECC_WDCH : INTEGER;
C_USE_ECC_WRCH : INTEGER;
C_USE_ECC_RACH : INTEGER;
C_USE_ECC_RDCH : INTEGER;
C_USE_ECC_AXIS : INTEGER;
C_ERROR_INJECTION_TYPE_WACH : INTEGER;
C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
C_ERROR_INJECTION_TYPE_RACH : INTEGER;
C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
C_DIN_WIDTH_WACH : INTEGER;
C_DIN_WIDTH_WDCH : INTEGER;
C_DIN_WIDTH_WRCH : INTEGER;
C_DIN_WIDTH_RACH : INTEGER;
C_DIN_WIDTH_RDCH : INTEGER;
C_DIN_WIDTH_AXIS : INTEGER;
C_WR_DEPTH_WACH : INTEGER;
C_WR_DEPTH_WDCH : INTEGER;
C_WR_DEPTH_WRCH : INTEGER;
C_WR_DEPTH_RACH : INTEGER;
C_WR_DEPTH_RDCH : INTEGER;
C_WR_DEPTH_AXIS : INTEGER;
C_WR_PNTR_WIDTH_WACH : INTEGER;
C_WR_PNTR_WIDTH_WDCH : INTEGER;
C_WR_PNTR_WIDTH_WRCH : INTEGER;
C_WR_PNTR_WIDTH_RACH : INTEGER;
C_WR_PNTR_WIDTH_RDCH : INTEGER;
C_WR_PNTR_WIDTH_AXIS : INTEGER;
C_HAS_DATA_COUNTS_WACH : INTEGER;
C_HAS_DATA_COUNTS_WDCH : INTEGER;
C_HAS_DATA_COUNTS_WRCH : INTEGER;
C_HAS_DATA_COUNTS_RACH : INTEGER;
C_HAS_DATA_COUNTS_RDCH : INTEGER;
C_HAS_DATA_COUNTS_AXIS : INTEGER;
C_HAS_PROG_FLAGS_WACH : INTEGER;
C_HAS_PROG_FLAGS_WDCH : INTEGER;
C_HAS_PROG_FLAGS_WRCH : INTEGER;
C_HAS_PROG_FLAGS_RACH : INTEGER;
C_HAS_PROG_FLAGS_RDCH : INTEGER;
C_HAS_PROG_FLAGS_AXIS : INTEGER;
C_PROG_FULL_TYPE_WACH : INTEGER;
C_PROG_FULL_TYPE_WDCH : INTEGER;
C_PROG_FULL_TYPE_WRCH : INTEGER;
C_PROG_FULL_TYPE_RACH : INTEGER;
C_PROG_FULL_TYPE_RDCH : INTEGER;
C_PROG_FULL_TYPE_AXIS : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_PROG_EMPTY_TYPE_WACH : INTEGER;
C_PROG_EMPTY_TYPE_WDCH : INTEGER;
C_PROG_EMPTY_TYPE_WRCH : INTEGER;
C_PROG_EMPTY_TYPE_RACH : INTEGER;
C_PROG_EMPTY_TYPE_RDCH : INTEGER;
C_PROG_EMPTY_TYPE_AXIS : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
C_REG_SLICE_MODE_WACH : INTEGER;
C_REG_SLICE_MODE_WDCH : INTEGER;
C_REG_SLICE_MODE_WRCH : INTEGER;
C_REG_SLICE_MODE_RACH : INTEGER;
C_REG_SLICE_MODE_RDCH : INTEGER;
C_REG_SLICE_MODE_AXIS : INTEGER
);
PORT (
backup : IN STD_LOGIC;
backup_marker : IN STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
srst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
wr_rst : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_assert : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full_thresh_negate : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
int_clk : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
injectsbiterr : IN STD_LOGIC;
sleep : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
wr_ack : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
underflow : OUT STD_LOGIC;
data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rd_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
wr_rst_busy : OUT STD_LOGIC;
rd_rst_busy : OUT STD_LOGIC;
m_aclk : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
m_aclk_en : IN STD_LOGIC;
s_aclk_en : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wready : IN STD_LOGIC;
m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_bvalid : IN STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_arvalid : OUT STD_LOGIC;
m_axi_arready : IN STD_LOGIC;
m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axi_rvalid : IN STD_LOGIC;
m_axi_rready : OUT STD_LOGIC;
s_axis_tvalid : IN STD_LOGIC;
s_axis_tready : OUT STD_LOGIC;
s_axis_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_tstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_tlast : IN STD_LOGIC;
s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tvalid : OUT STD_LOGIC;
m_axis_tready : IN STD_LOGIC;
m_axis_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_tstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_tlast : OUT STD_LOGIC;
m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
axi_aw_injectsbiterr : IN STD_LOGIC;
axi_aw_injectdbiterr : IN STD_LOGIC;
axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_aw_sbiterr : OUT STD_LOGIC;
axi_aw_dbiterr : OUT STD_LOGIC;
axi_aw_overflow : OUT STD_LOGIC;
axi_aw_underflow : OUT STD_LOGIC;
axi_aw_prog_full : OUT STD_LOGIC;
axi_aw_prog_empty : OUT STD_LOGIC;
axi_w_injectsbiterr : IN STD_LOGIC;
axi_w_injectdbiterr : IN STD_LOGIC;
axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_w_sbiterr : OUT STD_LOGIC;
axi_w_dbiterr : OUT STD_LOGIC;
axi_w_overflow : OUT STD_LOGIC;
axi_w_underflow : OUT STD_LOGIC;
axi_w_prog_full : OUT STD_LOGIC;
axi_w_prog_empty : OUT STD_LOGIC;
axi_b_injectsbiterr : IN STD_LOGIC;
axi_b_injectdbiterr : IN STD_LOGIC;
axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_b_sbiterr : OUT STD_LOGIC;
axi_b_dbiterr : OUT STD_LOGIC;
axi_b_overflow : OUT STD_LOGIC;
axi_b_underflow : OUT STD_LOGIC;
axi_b_prog_full : OUT STD_LOGIC;
axi_b_prog_empty : OUT STD_LOGIC;
axi_ar_injectsbiterr : IN STD_LOGIC;
axi_ar_injectdbiterr : IN STD_LOGIC;
axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
axi_ar_sbiterr : OUT STD_LOGIC;
axi_ar_dbiterr : OUT STD_LOGIC;
axi_ar_overflow : OUT STD_LOGIC;
axi_ar_underflow : OUT STD_LOGIC;
axi_ar_prog_full : OUT STD_LOGIC;
axi_ar_prog_empty : OUT STD_LOGIC;
axi_r_injectsbiterr : IN STD_LOGIC;
axi_r_injectdbiterr : IN STD_LOGIC;
axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
axi_r_sbiterr : OUT STD_LOGIC;
axi_r_dbiterr : OUT STD_LOGIC;
axi_r_overflow : OUT STD_LOGIC;
axi_r_underflow : OUT STD_LOGIC;
axi_r_prog_full : OUT STD_LOGIC;
axi_r_prog_empty : OUT STD_LOGIC;
axis_injectsbiterr : IN STD_LOGIC;
axis_injectdbiterr : IN STD_LOGIC;
axis_prog_full_thresh : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
axis_data_count : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
axis_wr_data_count : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
axis_rd_data_count : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
axis_sbiterr : OUT STD_LOGIC;
axis_dbiterr : OUT STD_LOGIC;
axis_overflow : OUT STD_LOGIC;
axis_underflow : OUT STD_LOGIC;
axis_prog_full : OUT STD_LOGIC;
axis_prog_empty : OUT STD_LOGIC
);
END COMPONENT fifo_generator_v13_1_3;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF FIFO_32x4K_arch: ARCHITECTURE IS "fifo_generator_v13_1_3,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF FIFO_32x4K_arch : ARCHITECTURE IS "FIFO_32x4K,fifo_generator_v13_1_3,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF FIFO_32x4K_arch: ARCHITECTURE IS "FIFO_32x4K,fifo_generator_v13_1_3,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.1,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_SELECT_XPM=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=10,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=18,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=18,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINI" &
"T_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=4kx4,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1022,C_PROG_FULL_THRESH_N" &
"EGATE_VAL=1021,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=10,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=10,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_T" &
"YPE=1,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1," &
"C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=0,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=32,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=1,C_AXIS_TSTRB_WIDTH=4,C_AXIS_TKEEP_WIDTH=4,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=2,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=2,C_IMPLEMENTATION_TYPE_RACH=2,C_IMPLEMENTATION_TYPE_RD" &
"CH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=4kx9,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_" &
"INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=32,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=4096,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_" &
"WR_PNTR_WIDTH_AXIS=12,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=1,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=15,C_" &
"PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=15,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=15,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=4095,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=14,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=14,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1" &
"4,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=4094,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 slave_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 slave_aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS TDATA";
BEGIN
U0 : fifo_generator_v13_1_3
GENERIC MAP (
C_COMMON_CLOCK => 1,
C_SELECT_XPM => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => 10,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => 18,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => 18,
C_ENABLE_RLOCS => 0,
C_FAMILY => "zynq",
C_FULL_FLAGS_RST_VAL => 1,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 0,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 0,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 0,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 1,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 1,
C_PRELOAD_REGS => 0,
C_PRIM_FIFO_TYPE => "4kx4",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 1022,
C_PROG_FULL_THRESH_NEGATE_VAL => 1021,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 10,
C_RD_DEPTH => 1024,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => 10,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 0,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => 10,
C_WR_DEPTH => 1024,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => 10,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_EN_SAFETY_CKT => 0,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 1,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 0,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 32,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 1,
C_AXIS_TSTRB_WIDTH => 4,
C_AXIS_TKEEP_WIDTH => 4,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 2,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 2,
C_IMPLEMENTATION_TYPE_RACH => 2,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "4kx9",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 32,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 4096,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 12,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 1,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 15,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 15,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 15,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 4095,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 14,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 14,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 14,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 4094,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => '0',
srst => '0',
wr_clk => '0',
wr_rst => '0',
rd_clk => '0',
rd_rst => '0',
din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 18)),
wr_en => '0',
rd_en => '0',
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
m_aclk => '0',
s_aclk => s_aclk,
s_aresetn => s_aresetn,
m_aclk_en => '0',
s_aclk_en => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_bready => '0',
m_axi_awready => '0',
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_rready => '0',
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
s_axis_tvalid => s_axis_tvalid,
s_axis_tready => s_axis_tready,
s_axis_tdata => s_axis_tdata,
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => m_axis_tready,
m_axis_tdata => m_axis_tdata,
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 12)),
axis_data_count => axis_data_count
);
END FIFO_32x4K_arch;
|
mit
|
OgliariNatan/projetointegrador_II
|
D_7SEG/debug_ram.vhd
|
1
|
6461
|
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: debug_ram.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 17.0.0 Build 595 04/25/2017 SJ Standard Edition
-- ************************************************************
--Copyright (C) 2017 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Intel and sold by Intel or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY debug_ram IS
PORT
(
address : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END debug_ram;
ARCHITECTURE SYN OF debug_ram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
q <= sub_wire0(31 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone IV E",
lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=dbg",
lpm_type => "altsyncram",
numwords_a => 32,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => 5,
width_a => 32,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "dbg"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING ""
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "5"
-- Retrieval info: PRIVATE: WidthData NUMERIC "32"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=dbg"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 5 0 INPUT NODEFVAL "address[4..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 5 0 address 0 0 5 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL debug_ram.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL debug_ram.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL debug_ram.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL debug_ram.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL debug_ram_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
mit
|
Beck-Sisyphus/EE471
|
Lab2/simulation/modelsim/rtl_work/decoder11_2048/_primary.vhd
|
2
|
232
|
library verilog;
use verilog.vl_types.all;
entity decoder11_2048 is
port(
\in\ : in vl_logic_vector(10 downto 0);
\out\ : out vl_logic_vector(2047 downto 0)
);
end decoder11_2048;
|
mit
|
Beck-Sisyphus/EE471
|
Lab4/simulation/modelsim/rtl_work/@i@mtest/_primary.vhd
|
1
|
237
|
library verilog;
use verilog.vl_types.all;
entity IMtest is
generic(
d : integer := 20
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of d : constant is 1;
end IMtest;
|
mit
|
rccoder/CPU-Summer-Term-HIT
|
CPU/ALU.vhd
|
1
|
3022
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:46:08 07/26/2015
-- Design Name:
-- Module Name: ALU_module - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALU is
port(
-- ʵÏÖ×¼±¸ºÍÔËË㹦ÄÜ
enable_t : in std_logic ; -- ×¼±¸ºÍÔËË㹦ÄÜʹÄÜÐźÅ
ir : in std_logic_vector(15 downto 0);
-- Ïò·Ã´æ¿ØÖÆÄ£¿éÊä³ö
sig_reg7aluout : out std_logic_vector ( 15 downto 0 ); -- ÔÝ´æÆ÷Êä³ö¶Ë¿Ú
sig_reg7addrout : out std_logic_vector ( 15 downto 0 ); -- 8λµØÖ·Êä³ö¶Ë¿Ú
--reg7_out : out std_logic_vector ( 7 downto 0 );
-- ʵÏÖ»Øд¹¦ÄÜ
enable_wb : in std_logic ; -- »Øд¹¦ÄÜʹÄÜ
reg_wb : in std_logic_vector (7 downto 0 ); -- »Øд½ÓÊն˿Ú
-- ½øλ±êÖ¾
cy : out std_logic
);
end ALU;
architecture Behavioral of ALU is
type registers_8 is array (7 downto 0) of std_logic_vector(7 downto 0);
signal reg : registers_8; -- Êý×éÐÍ8¸ö8λ¼Ä´æÆ÷
signal addr : std_logic_vector ( 7 downto 0 ); -- ÔÝ´æÆ÷
begin
get_ready : process (enable_t,addr)
variable a,b : std_logic_vector ( 7 downto 0 );
variable tempa , tempb ,tempsum: std_logic_vector (8 downto 0 ); -- ½øλ±êÖ¾¼ÆËã
begin
a := reg(conv_integer(ir(10 downto 8)));
b := reg(conv_integer(ir(2 downto 0)));
addr <= ir( 7 downto 0 );
tempa := '0'&a;
tempb := '0'&b;
if enable_t = '1' then
case ir(15 downto 11) is
when "00000"=> tempsum := tempa + tempb ; --ADD
when "00001"=> tempsum := tempa - tempb ; --SUB
when "00010"=> tempsum := tempb; --MOV
when "10010"=> tempsum := '0'&addr; --MVI
when "11011"=> tempsum := '0'&addr; --LDA
when "11000"=> tempsum := tempa; --STA
when "10001"=> tempsum := '0'&addr; --JMP
when "10000"=> tempsum := tempa; --JZ
--when "11111"=> tempsum := '0'&addr; --IN
--when "11100"=> tempsum :=tempa; --OUT
when others=> tempsum :="ZZZZZZZZZ";
end case;
--sig_reg7aluout <= reg(7)&tempsum ( 7 downto 0 );
sig_reg7aluout <= "00000000"&tempsum ( 7 downto 0 );
cy <= tempsum (8) ;
sig_reg7addrout <= reg(7)&addr;
end if ;
end process;
write_back : process (reg_wb,enable_wb)
begin
if enable_wb = '1' then
reg(conv_integer(ir(10 downto 8))) <= reg_wb;
end if;
end process;
end Behavioral;
|
mit
|
kklt92/RISC_Microprocessor
|
RISC_microprocessor/src/ReorderBuffer.vhd
|
1
|
4650
|
--******************************************************************************--
-- Author: Weihao Ming --
-- Date: 2014-01-13 --
-- Module: EE3A1 RISC Microprocessor --
-- Description: Re-order buffer. Placing before instruction decoder --
-- and automatic re-order instruction for --
-- microprocessor. --
--******************************************************************************--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
ENTITY reorderBuffer IS
PORT( in1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
out1: OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clk: IN STD_LOGIC);
END ENTITY reorderBuffer;
ARCHITECTURE rtl OF reorderBuffer IS
TYPE buffer_array IS ARRAY( 0 TO 5) OF STD_LOGIC_VECTOR ( 31 DOWNTO 0);
SIGNAL buffer_data: buffer_array:= (X"00000000", X"00000000", X"00000000", -- 6 addresses buffer.
X"00000000", X"00000000", X"00000000");
BEGIN
PROCESS(clk)
variable i: integer := 2; -- i is for pre-running instruction.
variable j: integer := 0; -- j is for post-running instruction.
variable c: integer := 0; -- 0 for incomplete output. 1 for complete.
variable output1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000000"; -- Temperaryly store output.
variable buffer_temp : buffer_array := buffer_data; -- Copy all the data in buffer to
BEGIN -- re-order it. and pushing everything
IF(rising_edge(clk)) THEN -- forward to fullfill empty address.
i := 2;
j := 0;
c := 0;
WHILE ( i < 6 ) LOOP -- Storing incoming instruction in an empty address.
IF( buffer_data(i) /= X"00000000")THEN
i := i + 1;
ELSE
buffer_data(i) <= in1;
buffer_temp(i) := in1;
i := 0;
EXIT;
END IF;
END LOOP;
i := 2;
j := 0;
c := 0;
WHILE ( i < 6 ) LOOP
IF( buffer_data(0) = X"00000000") -- If previous two instructions are both no-op,
AND (buffer_data(1) = X"00000000") THEN -- then output first no no-op instruction.
IF(buffer_data(i) /= X"00000000") THEN
out1 <= buffer_data(i);
buffer_data(i) <= X"00000000";
buffer_temp(i) := X"00000000";
output1 := buffer_data(i);
i := 2;
c := 1;
EXIT;
ELSE
i := i+1;
END IF;
ELSIF (buffer_data(1)(15 DOWNTO 11) = buffer_data(2)(25 DOWNTO 21)) THEN -- If current reading is previous written,
out1 <= buffer_data(2); -- then output to meet multiplexer funtion.
output1 := buffer_data(2);
buffer_data(2) <= X"00000000";
buffer_temp(2) := X"00000000";
i :=2;
c :=1;
EXIT;
ELSE
j := 0; -- Check if there is data hazard. if so, then reorder.
WHILE ( j < 3 ) LOOP
IF(buffer_data(j) /= X"00000000") THEN
IF( buffer_data(i)(25 DOWNTO 21) /= buffer_data(j)(15 DOWNTO 11)) THEN
IF(buffer_data(i)(20 DOWNTO 16) /= buffer_data(j)(15 DOWNTO 11)) THEN
IF(buffer_data(i) /= X"00000000") THEN
out1 <= buffer_data(i);
output1 := buffer_data(i);
buffer_data(i) <= X"00000000";
buffer_temp(i) := X"00000000";
i := 2;
j := 0;
c := 1;
EXIT;
ELSE
j := j+1;
END IF;
ELSE
j := j+1;
END IF;
ELSE
j := j+1;
END IF;
ELSE
j := j + 1;
END IF;
END LOOP;
END IF;
IF ( c = 0) THEN
i := i + 1;
ELSE
i := 2;
j := 0;
EXIT;
END IF;
END LOOP;
IF ( c = 0) THEN -- If there will be data harzard for all buffer instruction,
out1 <= X"00000000"; -- then output no-op.
output1 := X"00000000";
c := 1;
END IF;
buffer_data(0) <= buffer_data(1);
buffer_data(1) <= output1;
i := 2;
WHILE( i < 5) LOOP -- Pushing buffer data forward to fullfill empty address.
IF(buffer_temp(i) = X"00000000") THEN
buffer_temp(i) := buffer_temp(i+1);
buffer_temp(i+1) := X"00000000";
END IF;
i := i+1;
END LOOP;
i:=2;
WHILE( i < 6) LOOP -- Writing temperary data to address.
buffer_data(i) <= buffer_temp(i);
i := i+1;
END LOOP;
END IF;
END PROCESS;
END ARCHITECTURE rtl;
|
mit
|
Beck-Sisyphus/EE471
|
Lab4/simulation/modelsim/rtl_work/or@gate/_primary.vhd
|
1
|
449
|
library verilog;
use verilog.vl_types.all;
entity orGate is
port(
busOR : out vl_logic_vector(31 downto 0);
busA : in vl_logic_vector(31 downto 0);
busB : in vl_logic_vector(31 downto 0);
zOR : out vl_logic;
oOR : out vl_logic;
cOR : out vl_logic;
\nOR\ : out vl_logic
);
end orGate;
|
mit
|
OgliariNatan/projetointegrador_II
|
D_7SEG/clockDivider.vhd
|
1
|
689
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY clockDivider IS
PORT ( CLOCKIN : IN STD_LOGIC;
FreqIn : IN INTEGER;
freqOut : IN INTEGER;
CLOCKOUT : OUT STD_LOGIC
);
END clockDivider;
ARCHITECTURE behavior OF clockDivider IS
SIGNAL clock : STD_LOGIC := '0';
CONSTANT COUNT_MAX : INTEGER := ((freqIn / freqOut) / 2) - 1;
BEGIN
PROCESS(CLOCKIN)
VARIABLE counter : INTEGER RANGE 0 TO COUNT_MAX := 0;
BEGIN
IF (CLOCKIN'EVENT AND CLOCKIN = '1') THEN
IF counter < COUNT_MAX THEN
counter := counter + 1;
ELSE
counter := 0;
clock <= NOT clock;
END IF;
END IF;
END PROCESS;
CLOCKOUT <= clock;
END;
|
mit
|
rccoder/CPU-Summer-Term-HIT
|
chapter4/fpga0/FPGA0.vhd
|
1
|
1620
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:30:30 07/20/2015
-- Design Name:
-- Module Name: FPGA0 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity FPGA0 is
Port ( k0 : in STD_LOGIC_VECTOR (7 downto 0);
k1 : in STD_LOGIC_VECTOR (7 downto 0);
k2 : in STD_LOGIC_VECTOR (7 downto 0);
k3 : in STD_LOGIC_VECTOR (7 downto 0);
k4 : in STD_LOGIC_VECTOR (7 downto 0);
s0 : out STD_LOGIC_VECTOR (7 downto 0);
s1 : out STD_LOGIC_VECTOR (7 downto 0);
s2 : out STD_LOGIC_VECTOR (7 downto 0);
s3 : out STD_LOGIC_VECTOR (7 downto 0);
s4 : out STD_LOGIC_VECTOR (7 downto 0);
s5 : out STD_LOGIC_VECTOR (7 downto 0);
A : out STD_LOGIC_VECTOR (7 downto 0);
B : out STD_LOGIC_VECTOR (7 downto 0));
end FPGA0;
architecture Behavioral of FPGA0 is
begin
process(k0, k1, k2, k3, k4)
begin
s0 <= k0;
s3 <= k0;
s1 <= k1;
s4 <= k1;
s2 <= k2;
s5 <= k2;
B <= k3;
A <= k4;
end process;
end Behavioral;
|
mit
|
OgliariNatan/projetointegrador_II
|
D_7SEG/freq_counter.vhd
|
1
|
1402
|
-- *
-- * freq_counter.vhd
-- *
-- * Created on: Mar 21, 2017
-- * Author: Renan Augusto Starke
-- *
-- * IFSC -- DALEN--
--------------------------------------------/
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity freq_counter is
port(
clk : in std_logic;
rst : in std_logic;
pulse : in std_logic;
err : out std_logic;
data_out : out std_logic_vector(15 downto 0)
);
end entity freq_counter;
architecture RTL of freq_counter is
signal count, prev_count : std_logic_vector(15 downto 0);
begin
-- simple counter process
-- max frequency is clk
process(clk, rst)
begin
if (rst = '1') then
count <= (others => '0');
else
if rising_edge(clk) then
count <= count + 1;
end if;
end if;
end process;
process(pulse, rst)
begin
if (rst = '1') then
prev_count <= (others => '0');
data_out <= (others => '0');
else
if rising_edge(pulse) then
if (prev_count < count) then
data_out <= count - prev_count;
err <= '0';
elsif (prev_count > count) then
data_out <= prev_count + count;
err <= '0';
else
data_out <= (others => '0');
err <= '1';
end if;
prev_count <= count;
end if;
end if;
end process;
end architecture RTL;
|
mit
|
rccoder/CPU-Summer-Term-HIT
|
chapter3/decode4.vhd
|
1
|
1348
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:45:16 07/16/2015
-- Design Name:
-- Module Name: decode4 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity decode4 is
port(
d : in std_logic_vector(3 downto 0);
enable : in std_logic;
q8, q9, q11 : out std_logic
);
end decode4 ;
architecture main of decode4 is
begin
process( enable, d )
begin
if enable = '1' then
case d is
when "1000" => q8 <= '0'; q9 <= '1'; q11 <= '1';
when "1001" => q8 <= '1'; q9 <= '0'; q11 <= '1';
when "1011" => q8 <= '1'; q9 <= '1'; q11 <= '0';
when others => q8 <= '1'; q9 <= '1'; q11 <= '1';
end case;
else
q8 <= '1'; q9 <= '1'; q11 <= '1';
end if;
end process;
end main;
|
mit
|
rccoder/CPU-Summer-Term-HIT
|
chapter3/reg8.vhd
|
1
|
1126
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:46:07 07/16/2015
-- Design Name:
-- Module Name: reg8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity reg8 is
port(
clrn, clk : in std_logic;
d : in std_logic_vector(7 downto 0);
q : out std_logic_vector(7 downto 0)
);
end reg8 ;
architecture main of reg8 is
begin
process(clk, clrn)
begin
if clrn = '0' then
q <= "00000000";
elsif clk = '1' and clk'event then
q <= d;
end if;
end process;
end main;
|
mit
|
djanowski/pygmentize
|
vendor/pygments/tests/examplefiles/test.vhdl
|
75
|
4446
|
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_testbench is --test
generic ( -- test
n : integer := 8 -- test
); -- test
end top_testbench; -- test
architecture top_testbench_arch of top_testbench is
component top is
generic (
n : integer
) ;
port (
clk : in std_logic;
rst : in std_logic;
d1 : in std_logic_vector (n-1 downto 0);
d2 : in std_logic_vector (n-1 downto 0);
operation : in std_logic;
result : out std_logic_vector (2*n-1 downto 0)
);
end component;
signal clk : std_logic;
signal rst : std_logic;
signal operation : std_logic;
signal d1 : std_logic_vector (n-1 downto 0);
signal d2 : std_logic_vector (n-1 downto 0);
signal result : std_logic_vector (2*n-1 downto 0);
type test_type is ( a1, a2, a3, a4, a5, a6, a7, a8, a9, a10);
attribute enum_encoding of my_state : type is "001 010 011 100 111";
begin
TESTUNIT : top generic map (n => n)
port map (clk => clk,
rst => rst,
d1 => d1,
d2 => d2,
operation => operation,
result => result);
clock_process : process
begin
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end process;
data_process : process
begin
-- test case #1
operation <= '0';
rst <= '1';
wait for 5 ns;
rst <= '0';
wait for 5 ns;
d1 <= std_logic_vector(to_unsigned(60, d1'length));
d2 <= std_logic_vector(to_unsigned(12, d2'length));
wait for 360 ns;
assert (result = std_logic_vector(to_unsigned(720, result'length)))
report "Test case #1 failed" severity error;
-- test case #2
operation <= '0';
rst <= '1';
wait for 5 ns;
rst <= '0';
wait for 5 ns;
d1 <= std_logic_vector(to_unsigned(55, d1'length));
d2 <= std_logic_vector(to_unsigned(1, d2'length));
wait for 360 ns;
assert (result = std_logic_vector(to_unsigned(55, result'length)))
report "Test case #2 failed" severity error;
-- etc
end process;
end top_testbench_arch;
configuration testbench_for_top of top_testbench is
for top_testbench_arch
for TESTUNIT : top
use entity work.top(top_arch);
end for;
end for;
end testbench_for_top;
function compare(A: std_logic, B: std_Logic) return std_logic is
constant pi : real := 3.14159;
constant half_pi : real := pi / 2.0;
constant cycle_time : time := 2 ns;
constant N, N5 : integer := 5;
begin
if (A = '0' and B = '1') then
return B;
else
return A;
end if ;
end compare;
procedure print(P : std_logic_vector(7 downto 0);
U : std_logic_vector(3 downto 0)) is
variable my_line : line;
alias swrite is write [line, string, side, width] ;
begin
swrite(my_line, "sqrt( ");
write(my_line, P);
swrite(my_line, " )= ");
write(my_line, U);
writeline(output, my_line);
end print;
entity add32csa is -- one stage of carry save adder for multiplier
port(
b : in std_logic; -- a multiplier bit
a : in std_logic_vector(31 downto 0); -- multiplicand
sum_in : in std_logic_vector(31 downto 0); -- sums from previous stage
cin : in std_logic_vector(31 downto 0); -- carrys from previous stage
sum_out : out std_logic_vector(31 downto 0); -- sums to next stage
cout : out std_logic_vector(31 downto 0)); -- carrys to next stage
end add32csa;
ARCHITECTURE circuits of add32csa IS
SIGNAL zero : STD_LOGIC_VECTOR(31 downto 0) := X"00000000";
SIGNAL aa : std_logic_vector(31 downto 0) := X"00000000";
COMPONENT fadd -- duplicates entity port
PoRT(a : in std_logic;
b : in std_logic;
cin : in std_logic;
s : out std_logic;
cout : out std_logic);
end comPonent fadd;
begin -- circuits of add32csa
aa <= a when b='1' else zero after 1 ns;
stage: for I in 0 to 31 generate
sta: fadd port map(aa(I), sum_in(I), cin(I) , sum_out(I), cout(I));
end generate stage;
end architecture circuits; -- of add32csa
|
mit
|
briannkym/583final
|
Breakout/src/Character.vhd
|
1
|
8436
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Char is
port(
rainbow : in std_logic;
charnum : in std_logic_vector(7 downto 0);
x : in std_logic_vector(2 downto 0);
y : in std_logic_vector(2 downto 0);
R : out std_logic_vector(3 downto 0);
G : out std_logic_vector(3 downto 0);
B : out std_logic_vector(3 downto 0));
end Char;
architecture dataflow of Char is
constant leta: std_logic_vector(0 to 63):=
"0001100000111100001001000110011001111110010000101100001111000011";
constant letb: std_logic_vector(0 to 63):=
"1111110011000110110000111111110011001110110000111100001111111110";
constant letc: std_logic_vector(0 to 63):=
"0001111001110011110000001100000011000000110000000111001100011110";
constant letd: std_logic_vector(0 to 63):=
"1111110011001110110000111100001111000011110000111100111011111100";
constant lete: std_logic_vector(0 to 63):=
"1111111111000001110000001111000011111000110000001100000111111111";
constant letf: std_logic_vector(0 to 63):=
"1111111111000001110000001111001011111110110000001100000011100000";
constant letg: std_logic_vector(0 to 63):=
"0011110011100111110000001100000011000111110000111110011100111100";
constant leth: std_logic_vector(0 to 63):=
"1110011111000011110000111110011111111111110000111100001111100111";
constant leti: std_logic_vector(0 to 63):=
"1111111110011001000110000001100000011000000110001001100111111111";
constant letj: std_logic_vector(0 to 63):=
"1111111100001100000011000000110011101100110011001100110001111000";
constant letk: std_logic_vector(0 to 63):=
"1110001111000110110111001111000011011000110011001100011011100011";
constant letl: std_logic_vector(0 to 63):=
"1110000011000000110000001100000011000000110000001100000111111111";
constant letm: std_logic_vector(0 to 63):=
"1100001111000011111001111111111111011011110000111100001111000011";
constant letn: std_logic_vector(0 to 63):=
"1100011111100011111100111101101111001111110001111100001111100111";
constant leto: std_logic_vector(0 to 63):=
"0011110011100111110000111100001111000011110000111110011100111100";
constant letp: std_logic_vector(0 to 63):=
"1111110011000111110000111100011111111110110000001100000011100000";
constant letq: std_logic_vector(0 to 63):=
"0001100000111100001001000110011001111110010000101100001111000011";
constant letr: std_logic_vector(0 to 63):=
"1111110011000111110000111100011011111100110011001100011011100111";
constant lets: std_logic_vector(0 to 63):=
"0011111111100001110000000111000000111100000011101100011101111110";
constant lett: std_logic_vector(0 to 63):=
"1111111110011001000110000001100000011000000110000001100000111100";
constant letu: std_logic_vector(0 to 63):=
"1110011111000011110000111100001111000011110000111110011100111100";
constant letv: std_logic_vector(0 to 63):=
"1110011111000011111001110110011001100110001001000011110000011000";
constant letw: std_logic_vector(0 to 63):=
"0001100000111100001001000110011001111110010000101100001111000011";
constant letx: std_logic_vector(0 to 63):=
"0001100000111100001001000110011001111110010000101100001111000011";
constant lety: std_logic_vector(0 to 63):=
"1100001101100110001001000011110000011000000110000001100000111100";
constant letz: std_logic_vector(0 to 63):=
"0001100000111100001001000110011001111110010000101100001111000011";
signal pixel: std_logic :='0';
begin
process(x, y, charnum)
begin
case charnum is
when x"00" =>
if(leta(to_integer(unsigned(y & "000") +
unsigned("000" & x))) = '1') then
pixel<='1';
else
pixel<='0';
end if;
when x"01" =>
if(letb(to_integer(unsigned(y & "000") +
unsigned("000" & x))) = '1') then
pixel<='1';
else
pixel<='0';
end if;
when x"02" =>
if(letc(to_integer(unsigned(y & "000") +
unsigned("000" & x))) = '1') then
pixel<='1';
else
pixel<='0';
end if;
when x"03" =>
if(letd(to_integer(unsigned(y & "000") +
unsigned("000" & x))) = '1') then
pixel<='1';
else
pixel<='0';
end if;
when x"04" =>
if(lete(to_integer(unsigned(y & "000") +
unsigned("000" & x))) = '1') then
pixel<='1';
else
pixel<='0';
end if;
when x"05" =>
if(letf(to_integer(unsigned(y & "000") +
unsigned("000" & x))) = '1') then
pixel<='1';
else
pixel<='0';
end if;
when x"06" =>
if(letg(to_integer(unsigned(y & "000") +
unsigned("000" & x))) = '1') then
pixel<='1';
else
pixel<='0';
end if;
when x"07" =>
if(leth(to_integer(unsigned(y & "000") +
unsigned("000" & x))) = '1') then
pixel<='1';
else
pixel<='0';
end if;
when x"08" =>
if(leti(to_integer(unsigned(y & "000") +
unsigned("000" & x))) = '1') then
pixel<='1';
else
pixel<='0';
end if;
when x"09" =>
if(letj(to_integer(unsigned(y & "000") +
unsigned("000" & x))) = '1') then
pixel<='1';
else
pixel<='0';
end if;
when x"0a" =>
if(letk(to_integer(unsigned(y & "000") +
unsigned("000" & x))) = '1') then
pixel<='1';
else
pixel<='0';
end if;
when x"0b" =>
if(letl(to_integer(unsigned(y & "000") +
unsigned("000" & x))) = '1') then
pixel<='1';
else
pixel<='0';
end if;
when x"0c" =>
if(letm(to_integer(unsigned(y & "000") +
unsigned("000" & x))) = '1') then
pixel<='1';
else
pixel<='0';
end if;
when x"0d" =>
if(letn(to_integer(unsigned(y & "000") +
unsigned("000" & x))) = '1') then
pixel<='1';
else
pixel<='0';
end if;
when x"0e" =>
if(leto(to_integer(unsigned(y & "000") +
unsigned("000" & x))) = '1') then
pixel<='1';
else
pixel<='0';
end if;
when x"0f" =>
if(letp(to_integer(unsigned(y & "000") +
unsigned("000" & x))) = '1') then
pixel<='1';
else
pixel<='0';
end if;
when x"10" =>
if(letq(to_integer(unsigned(y & "000") +
unsigned("000" & x))) = '1') then
pixel<='1';
else
pixel<='0';
end if;
when x"11" =>
if(letr(to_integer(unsigned(y & "000") +
unsigned("000" & x))) = '1') then
pixel<='1';
else
pixel<='0';
end if;
when x"12" =>
if(lets(to_integer(unsigned(y & "000") +
unsigned("000" & x))) = '1') then
pixel<='1';
else
pixel<='0';
end if;
when x"13" =>
if(lett(to_integer(unsigned(y & "000") +
unsigned("000" & x))) = '1') then
pixel<='1';
else
pixel<='0';
end if;
when x"14" =>
if(letu(to_integer(unsigned(y & "000") +
unsigned("000" & x))) = '1') then
pixel<='1';
else
pixel<='0';
end if;
when x"15" =>
if(letv(to_integer(unsigned(y & "000") +
unsigned("000" & x))) = '1') then
pixel<='1';
else
pixel<='0';
end if;
when x"16" =>
if(letw(to_integer(unsigned(y & "000") +
unsigned("000" & x))) = '1') then
pixel<='1';
else
pixel<='0';
end if;
when x"17" =>
if(letx(to_integer(unsigned(y & "000") +
unsigned("000" & x))) = '1') then
pixel<='1';
else
pixel<='0';
end if;
when x"18" =>
if(lety(to_integer(unsigned(y & "000") +
unsigned("000" & x))) = '1') then
pixel<='1';
else
pixel<='0';
end if;
when x"19" =>
if(letz(to_integer(unsigned(y & "000") +
unsigned("000" & x))) = '1') then
pixel<='1';
else
pixel<='0';
end if;
when others =>
end case;
end process;
process (pixel, rainbow)
begin
if(pixel='1') then
if(rainbow='1') then
case y is
when "000" =>
R <= "1110";
G <= "0000";
B <= "0000";
when "001" =>
R <= "1110";
G <= "0110";
B <= "0000";
when "010" =>
R <= "1110";
G <= "1110";
B <= "0000";
when "011" =>
R <= "0000";
G <= "1110";
B <= "0000";
when "100" =>
R <= "0000";
G <= "0000";
B <= "1100";
when "101" =>
R <= "1000";
G <= "0000";
B <= "1100";
when others =>
R <= "1110";
G <= "0000";
B <= "0000";
end case;
else
R <="1000";
G <="1000";
B <="1000";
end if;
else
R <=x"0";
G <=x"0";
B <=x"0";
end if;
end process;
end dataflow;
|
mit
|
maikmerten/riscv-tomthumb
|
src/vhdl/cpu/constants.vhd
|
1
|
6715
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package constants is
constant XLEN: integer := 32;
constant XLEN_ZERO: std_logic_vector(XLEN-1 downto 0) := X"00000000";
constant XLEN_ONE: std_logic_vector(XLEN-1 downto 0) := X"00000001";
constant RESET_VECTOR: std_logic_vector(XLEN-1 downto 0) := X"00000000";
constant TRAP_VECTOR: std_logic_vector(XLEN-1 downto 0) := X"00000004";
constant INTERRUPT_VECTOR: std_logic_vector(XLEN-1 downto 0) := X"00000008";
-- Opcodes
constant OP_OP: std_logic_vector(4 downto 0) := "01100"; -- R-type
constant OP_CUSTOM0: std_logic_vector(4 downto 0) := "00010"; -- R-type
constant OP_JALR: std_logic_vector(4 downto 0) := "11001"; -- I-type
constant OP_LOAD: std_logic_vector(4 downto 0) := "00000"; -- I-type
constant OP_OPIMM: std_logic_vector(4 downto 0) := "00100"; -- I-type
constant OP_SYSTEM: std_logic_vector(4 downto 0) := "11100"; -- I-type
constant OP_MISCMEM: std_logic_vector(4 downto 0) := "00011"; -- I-type?
constant OP_STORE: std_logic_vector(4 downto 0) := "01000"; -- S-type
constant OP_BRANCH: std_logic_vector(4 downto 0) := "11000"; -- SB-type
constant OP_LUI: std_logic_vector(4 downto 0) := "01101"; -- U-type
constant OP_AUIPC: std_logic_vector(4 downto 0) := "00101"; -- U-type
constant OP_JAL: std_logic_vector(4 downto 0) := "11011"; -- UJ-type
constant FUNC_JALR: std_logic_vector(2 downto 0) := "000";
-- Functions
constant FUNC_BEQ: std_logic_vector(2 downto 0) := "000";
constant FUNC_BNE: std_logic_vector(2 downto 0) := "001";
constant FUNC_BLT: std_logic_vector(2 downto 0) := "100";
constant FUNC_BGE: std_logic_vector(2 downto 0) := "101";
constant FUNC_BLTU: std_logic_vector(2 downto 0) := "110";
constant FUNC_BGEU: std_logic_vector(2 downto 0) := "111";
constant FUNC_LB: std_logic_vector(2 downto 0) := "000";
constant FUNC_LH: std_logic_vector(2 downto 0) := "001";
constant FUNC_LW: std_logic_vector(2 downto 0) := "010";
constant FUNC_LBU: std_logic_vector(2 downto 0) := "100";
constant FUNC_LHU: std_logic_vector(2 downto 0) := "101";
constant FUNC_SB: std_logic_vector(2 downto 0) := "000";
constant FUNC_SH: std_logic_vector(2 downto 0) := "001";
constant FUNC_SW: std_logic_vector(2 downto 0) := "010";
constant FUNC_ADDI: std_logic_vector(2 downto 0) := "000";
constant FUNC_SLLI: std_logic_vector(2 downto 0) := "001";
constant FUNC_SLTI: std_logic_vector(2 downto 0) := "010";
constant FUNC_SLTIU: std_logic_vector(2 downto 0) := "011";
constant FUNC_XORI: std_logic_vector(2 downto 0) := "100";
constant FUNC_SRLI_SRAI: std_logic_vector(2 downto 0) := "101";
constant FUNC_ORI: std_logic_vector(2 downto 0) := "110";
constant FUNC_ANDI: std_logic_vector(2 downto 0) := "111";
constant FUNC_ADD_SUB: std_logic_vector(2 downto 0) := "000";
constant FUNC_SLL: std_logic_vector(2 downto 0) := "001";
constant FUNC_SLT: std_logic_vector(2 downto 0) := "010";
constant FUNC_SLTU: std_logic_vector(2 downto 0) := "011";
constant FUNC_XOR: std_logic_vector(2 downto 0) := "100";
constant FUNC_SRL_SRA: std_logic_vector(2 downto 0) := "101";
constant FUNC_OR: std_logic_vector(2 downto 0) := "110";
constant FUNC_AND: std_logic_vector(2 downto 0) := "111";
constant FUNC_FENCE: std_logic_vector(2 downto 0) := "000";
constant FUNC_FENCEI: std_logic_vector(2 downto 0) := "001";
constant FUNC_SCALL_SBREAK: std_logic_vector(2 downto 0) := "000";
constant FUNC_RD: std_logic_vector(2 downto 0) := "010";
constant R0: std_logic_vector(4 downto 0) := "00000";
constant R1: std_logic_vector(4 downto 0) := "00001";
constant R2: std_logic_vector(4 downto 0) := "00010";
constant R3: std_logic_vector(4 downto 0) := "00011";
constant R4: std_logic_vector(4 downto 0) := "00100";
constant R5, T0: std_logic_vector(4 downto 0) := "00101";
constant R6, T1: std_logic_vector(4 downto 0) := "00110";
constant R7, T2: std_logic_vector(4 downto 0) := "00111";
constant R8: std_logic_vector(4 downto 0) := "01000";
constant R9: std_logic_vector(4 downto 0) := "01001";
constant R10: std_logic_vector(4 downto 0) := "01010";
constant R11: std_logic_vector(4 downto 0) := "01011";
constant R12: std_logic_vector(4 downto 0) := "01100";
constant R13: std_logic_vector(4 downto 0) := "01101";
constant R14: std_logic_vector(4 downto 0) := "01110";
constant R15: std_logic_vector(4 downto 0) := "01111";
constant R16: std_logic_vector(4 downto 0) := "10000";
constant R17: std_logic_vector(4 downto 0) := "10001";
constant R18: std_logic_vector(4 downto 0) := "10010";
constant R19: std_logic_vector(4 downto 0) := "10011";
constant R20: std_logic_vector(4 downto 0) := "10100";
constant R21: std_logic_vector(4 downto 0) := "10101";
constant R22: std_logic_vector(4 downto 0) := "10110";
constant R23: std_logic_vector(4 downto 0) := "10111";
constant R24: std_logic_vector(4 downto 0) := "11000";
constant R25: std_logic_vector(4 downto 0) := "11001";
constant R26: std_logic_vector(4 downto 0) := "11010";
constant R27: std_logic_vector(4 downto 0) := "11011";
constant R28: std_logic_vector(4 downto 0) := "11100";
constant R29: std_logic_vector(4 downto 0) := "11101";
constant R30: std_logic_vector(4 downto 0) := "11110";
constant R31: std_logic_vector(4 downto 0) := "11111";
-- muxer ports
constant MUX_BUS_ADDR_PORTS: integer := 2;
constant MUX_BUS_ADDR_PORT_ALU: integer := 0;
constant MUX_BUS_ADDR_PORT_PC: integer := 1;
constant MUX_REG_DATA_PORTS: integer := 4;
constant MUX_REG_DATA_PORT_ALU: integer := 0;
constant MUX_REG_DATA_PORT_BUS: integer := 1;
constant MUX_REG_DATA_PORT_IMM: integer := 2;
constant MUX_REG_DATA_PORT_TRAPRET: integer := 3;
constant MUX_ALU_DAT1_PORTS: integer := 2;
constant MUX_ALU_DAT1_PORT_S1: integer := 0;
constant MUX_ALU_DAT1_PORT_PC: integer := 1;
constant MUX_ALU_DAT2_PORTS: integer := 3;
constant MUX_ALU_DAT2_PORT_S2: integer := 0;
constant MUX_ALU_DAT2_PORT_IMM: integer := 1;
constant MUX_ALU_DAT2_PORT_INSTLEN: integer := 2;
attribute enum_encoding : string;
-- ALU operations, signalled by decode unit
type aluops_t is (ALU_ADD, ALU_SUB, ALU_AND, ALU_OR, ALU_XOR, ALU_SLT, ALU_SLTU, ALU_SLL, ALU_SRL, ALU_SRA);
--attribute enum_encoding of aluops_t : type is "sequential";
-- commands for bus unit
type busops_t is (BUS_READB, BUS_READBU, BUS_READH, BUS_READHU, BUS_READW, BUS_WRITEB, BUS_WRITEH, BUS_WRITEW);
attribute enum_encoding of busops_t : type is "one-hot";
-- commands for program counter unit (PCU)
type pcuops_t is (PCU_SETPC, PCU_ENTERTRAP, PCU_RETTRAP, PCU_ENTERINT, PCU_RETINT);
attribute enum_encoding of pcuops_t : type is "one-hot";
-- commands for register unit
type regops_t is (REGOP_READ, REGOP_WRITE);
attribute enum_encoding of regops_t : type is "sequential";
end constants;
package body constants is
end constants;
|
mit
|
miree/vhdl_cores
|
delay/delay_tb.vhd
|
1
|
1200
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.delay_pkg.all;
entity delay_tb is
end entity;
architecture simulation of delay_tb is
constant clk_period : time := 5 ns;
-- generics for the device under test
constant test_depth : integer := 7; -- delay length of 2^3
constant test_bit_width : integer := 8;
-- signals to connect to fifo
signal clk : std_logic;
signal rst : std_logic;
signal d,q : std_logic_vector ( test_bit_width-1 downto 0 ) := (others => '0');
begin
-- instantiate device under test (dut)
dut : work.delay_pkg.delay
generic map (
depth => test_depth,
bit_width => test_bit_width
)
port map (
clk_i => clk,
rst_i => rst,
d_i => d,
q_o => q
);
clk_gen: process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
rst_initial: process
begin
rst <= '1';
wait for clk_period*20;
rst <= '0';
wait;
end process;
count: process(clk)
begin
if rising_edge(clk) then
d <= std_logic_vector(unsigned(d) + x"01");
end if;
end process;
end architecture;
|
mit
|
jpcofr/PDUAMaude
|
PDUAMaudeModel/doc/PDUA spec/PDUA VHDL Source/MDR.vhdl
|
1
|
1457
|
-- ***********************************************
-- ** PROYECTO PDUA **
-- ** Modulo: MDR (Registro de datos) **
-- ** Creacion: Julio 07 **
-- ** Revisión: Marzo 08 **
-- ** Por: MGH-CMUA-UNIANDES **
-- ***********************************************
-- Descripcion:
-- Registro de Datos
-- HMDR (habilitador)
-- _____|_
-- RD_WR -->| |
-- DATA_EX_in -->| |<-- DATA_ALU
-- DATA_EX_out <--| |--> DATA_C
-- |_______|
--
-- ***********************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity MDR is
Port ( DATA_EX_in : in std_logic_vector(7 downto 0);
DATA_EX_out : out std_logic_vector(7 downto 0);
DATA_ALU : in std_logic_vector(7 downto 0);
DATA_C : out std_logic_vector(7 downto 0);
HMDR : in std_logic;
RD_WR : in std_logic);
end MDR;
architecture Behavioral of MDR is
begin
process(DATA_EX_in,DATA_ALU,HMDR,RD_WR)
begin
if HMDR = '0' then -- no acceso a memoria
DATA_EX_out <= (others => 'Z');
DATA_C <= DATA_ALU;
elsif RD_WR = '0' then --lectura
--DATA_EX_out <= (others => 'Z');
DATA_C <= DATA_EX_in;
else
DATA_EX_out <= DATA_ALU;
DATA_C <= DATA_ALU;
end if;
end process;
end Behavioral;
|
mit
|
Ecodev/gims
|
htdocs/lib/ace-builds/demo/kitchen-sink/docs/vhdl.vhd
|
472
|
830
|
library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
|
mit
|
miree/vhdl_cores
|
maw/maw.vhd
|
1
|
1797
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity maw is
generic (
-- window width is 2^depth
depth : integer;
input_bit_width : integer
);
port (
clk_i , rst_i : in std_logic;
value_i : in unsigned ( input_bit_width-1 downto 0 );
-- the ouput value's maximum is 2^input_bit_width * 2^depth
value_o : out unsigned ( input_bit_width+depth-1 downto 0 )
);
end entity;
architecture rtl of maw is
signal delayed : std_logic_vector ( input_bit_width-1 downto 0 );
signal sum : unsigned (input_bit_width+depth-1 downto 0);
signal add, sub : unsigned (input_bit_width+depth-1 downto 0);
begin
buf : entity work.delay
generic map (
depth => depth,
bit_width => input_bit_width
)
port map (
clk_i => clk_i,
rst_i => rst_i,
q_o => delayed, -- type conversion only works for inputs (see line below)
-- so here an additional signal is used for type matching
d_i => std_logic_vector(value_i)
);
process (clk_i)
variable leading_zeros : unsigned (depth-1 downto 0) := (others => '0');
begin
if rising_edge(clk_i) then
if rst_i = '1' then
value_o <= (others => '0');
sum <= (others => '0');
sub <= (others => '0');
add <= (others => '0');
else
add <= leading_zeros & value_i ;
sub <= leading_zeros & unsigned(delayed);
-- here it is imporatant to do the subtraction first,
-- otherwise the intermediate value can overflow (be greater than 2^input_bit_width * 2^depth)
sum <= sum - sub + add;
value_o <= sum;
end if;
end if;
end process;
end architecture;
|
mit
|
miree/vhdl_cores
|
uart/uart_chipsim.vhd
|
1
|
4449
|
package uart_chipsim_pkg is
procedure uart_chipsim_init(stop_unitl_connected : boolean);
attribute foreign of uart_chipsim_init : procedure is "VHPIDIRECT uart_chipsim_init";
-- if the function returns a positive integer, it is a valid value
-- if the function returns a negative value it is either
-- TIMEOUT, meaning that nothing was read
-- or HANGUP, meaning that the client disconnected
function uart_chipsim_read(timeout_value : integer) return integer;
attribute foreign of uart_chipsim_read : function is "VHPIDIRECT uart_chipsim_read";
procedure uart_chipsim_write(x : integer);
attribute foreign of uart_chipsim_write : procedure is "VHPIDIRECT uart_chipsim_write";
procedure uart_chipsim_flush;
attribute foreign of uart_chipsim_flush : procedure is "VHPIDIRECT uart_chipsim_flush";
shared variable my_var : integer := 43;
end package;
package body uart_chipsim_pkg is
procedure uart_chipsim_init(stop_unitl_connected : boolean) is
begin
assert false report "VHPI" severity failure;
end procedure;
function uart_chipsim_read(timeout_value : integer) return integer is
begin
assert false report "VHPI" severity failure;
return 0;
end function;
procedure uart_chipsim_write(x : integer) is
begin
assert false report "VHPI" severity failure;
end procedure;
procedure uart_chipsim_flush is
begin
assert false report "VHPI" severity failure;
end procedure;
end package body;
library ieee;
use ieee.math_real.log2;
use ieee.math_real.ceil;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.uart_chipsim_pkg.all;
entity uart_chipsim is
generic (
g_wait_until_connected : boolean := true;
g_continue_after_disconnect : boolean := true;
g_baud_rate : integer := 9600
);
port (
tx_o : out std_logic;
rx_i : in std_logic
);
end entity;
architecture simulation of uart_chipsim is
signal tx : std_logic := '1';
signal clk_internal : std_logic := '1';
constant clk_internal_period : time := 100 ms / g_baud_rate;
signal value_from_file : integer := -1;
signal tx_dat, rx_dat : std_logic_vector(7 downto 0) := (others => '0');
signal tx_stb, rx_stb : std_logic := '0';
signal tx_stall : std_logic := '0';
function fix_rx_dat(rx : std_logic_vector(7 downto 0)) return std_logic_vector is
variable result : std_logic_vector(rx'range) := rx;
begin
for i in result'range loop
if result(i) /= '1' then
result(i) := '0';
end if;
end loop;
return result;
end function;
begin
-- clock generation
clk_internal <= not clk_internal after clk_internal_period/2;
-- instantiate a uart serializer
uart_tx_inst: entity work.uart_tx
generic map (
g_clk_freq => g_baud_rate*10,
g_baud_rate => g_baud_rate,
g_bits => 8)
port map (
clk_i => clk_internal,
dat_i => tx_dat,
stb_i => tx_stb,
stall_o => tx_stall,
tx_o => tx_o
);
uart_rx_inst: entity work.uart_rx
generic map (
g_clk_freq => g_baud_rate*10,
g_baud_rate => g_baud_rate,
g_bits => 8)
port map (
clk_i => clk_internal,
dat_o => rx_dat,
stb_o => rx_stb,
rx_i => rx_i
);
main: process
variable client_connected : boolean;
variable stop_until_client_connects : boolean := g_wait_until_connected;
begin
wait until rising_edge(clk_internal);
while true loop
uart_chipsim_init(stop_until_client_connects);
stop_until_client_connects := not g_continue_after_disconnect;
client_connected := true;
while client_connected loop
wait until rising_edge(clk_internal);
-- get value from device
if value_from_file < 0 then
value_from_file <= uart_chipsim_read(timeout_value=>0);
if value_from_file = -2 then
client_connected := false;
end if;
end if;
-- provide value to simulation
tx_stb <= '0';
if value_from_file >= 0 and tx_stall = '0' then
tx_dat <= std_logic_vector(to_signed(value_from_file,8));
tx_stb <= '1';
value_from_file <= -1;
end if;
if rx_stb = '1' then
uart_chipsim_write(to_integer(unsigned(fix_rx_dat(rx_dat))));
uart_chipsim_flush;
end if;
end loop;
end loop;
end process;
end architecture;
|
mit
|
maikmerten/riscv-tomthumb
|
src/vhdl/cpu/pcu_tb.vhd
|
1
|
2364
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.constants.all;
entity pcu_tb is
end pcu_tb;
architecture Behavior of pcu_tb is
constant I_clk_period : time := 10 ns;
signal I_clk, I_reset : std_logic := '0';
signal I_en: std_logic := '1';
signal I_op: pcuops_t;
signal I_data, O_data, O_trapret: std_logic_vector(XLEN-1 downto 0);
begin
-- instantiate unit under test
uut: entity work.pcu port map(
I_clk => I_clk,
I_en => I_en,
I_reset => I_reset,
I_op => I_op,
I_data => I_data,
O_data => O_data,
O_trapret => O_trapret
);
proc_clock: process
begin
I_clk <= '0';
wait for I_clk_period/2;
I_clk <= '1';
wait for I_clk_period/2;
end process;
proc_stimuli: process
begin
-- test setting the program counter
wait until falling_edge(I_clk);
I_data <= X"CAFEBABE";
I_op <= PCU_SETPC;
wait until falling_edge(I_clk);
assert O_data = X"CAFEBABE" report "wrong value" severity failure;
-- test entering and returning from a trap
wait until falling_edge(I_clk);
I_data <= X"CAFEBABE";
I_op <= PCU_SETPC;
wait until falling_edge(I_clk);
assert O_data = X"CAFEBABE" report "wrong value" severity failure;
I_data <= X"BEEFCAFE";
I_op <= PCU_ENTERTRAP;
wait until falling_edge(I_clk);
assert O_data = TRAP_VECTOR report "wrong value" severity failure;
I_op <= PCU_RETTRAP;
wait until falling_edge(I_clk);
assert O_data = X"BEEFCAFE" report "wrong value" severity failure;
I_data <= X"CAFEBABE";
I_op <= PCU_SETPC;
wait until falling_edge(I_clk);
assert O_data = X"CAFEBABE" report "wrong value" severity failure;
assert O_trapret = X"BEEFCAFE" report "wrong value" severity failure;
-- test entering and returning from an interrupt
wait until falling_edge(I_clk);
I_data <= X"CAFEBABE";
I_op <= PCU_SETPC;
wait until falling_edge(I_clk);
assert O_data = X"CAFEBABE" report "wrong value" severity failure;
I_data <= X"BEEFCAFE";
I_op <= PCU_ENTERINT;
wait until falling_edge(I_clk);
assert O_data = INTERRUPT_VECTOR report "wrong value" severity failure;
I_op <= PCU_RETINT;
wait until falling_edge(I_clk);
assert O_data = X"CAFEBABE" report "wrong value" severity failure;
wait for I_clk_period;
assert false report "end of simulation" severity failure;
end process;
end architecture;
|
mit
|
maikmerten/riscv-tomthumb
|
src/vhdl/cpu/pcu.vhd
|
1
|
1962
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.constants.all;
entity pcu is
port(
I_clk: in std_logic;
I_en: in std_logic;
I_reset: in std_logic;
I_op: in pcuops_t;
I_data: in std_logic_vector(XLEN-1 downto 0);
O_data: out std_logic_vector(XLEN-1 downto 0);
O_trapret: out std_logic_vector(XLEN-1 downto 0)
);
end pcu;
architecture Behavioral of pcu is
signal pc,ret_trap,ret_interrupt: std_logic_vector(XLEN-1 downto 1) := RESET_VECTOR(XLEN-1 downto 1);
begin
process(I_clk, I_en, I_reset, I_op, I_data)
variable newpc: std_logic_vector(XLEN-1 downto 0) := XLEN_ZERO;
begin
if rising_edge(I_clk) and I_en = '1' then
case I_op is
-- load and output program counter value
when PCU_SETPC =>
pc <= I_data(XLEN-1 downto 1);
-- output trap vector and save return address
-- NOTE: a return address needs to be computed beforehand
-- for that, the ALU will compute (PC + INSTR_LEN)
when PCU_ENTERTRAP =>
ret_trap <= I_data(XLEN-1 downto 1);
pc <= TRAP_VECTOR(XLEN-1 downto 1);
-- set program counter to trap return address
when PCU_RETTRAP =>
pc <= ret_trap;
-- output interrupt vector and save return address
-- Note: the return address is the original pc value, unlike traps
when PCU_ENTERINT =>
ret_interrupt <= pc;
pc <= INTERRUPT_VECTOR(XLEN-1 downto 1);
-- set program counter to interrupt return address
when PCU_RETINT =>
pc <= ret_interrupt;
end case;
if I_reset = '1' then
pc <= RESET_VECTOR(XLEN-1 downto 1);
ret_trap <= RESET_VECTOR(XLEN-1 downto 1);
ret_interrupt <= RESET_VECTOR(XLEN-1 downto 1);
end if;
end if;
end process;
-- process to drive O_data
process(pc)
begin
O_data <= pc & '0';
end process;
-- process to drive O_trapret
process(ret_trap)
begin
O_trapret <= ret_trap & '0';
end process;
end Behavioral;
|
mit
|
maikmerten/riscv-tomthumb
|
boards/de0-nano/vhdl/wizpll/wizpll.vhd
|
1
|
14812
|
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: wizpll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 15.1.0 Build 185 10/21/2015 SJ Lite Edition
-- ************************************************************
--Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus Prime License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY wizpll IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC
);
END wizpll;
ARCHITECTURE SYN OF wizpll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
width_clock : NATURAL
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire4_bv(0 DOWNTO 0) <= "0";
sub_wire4 <= To_stdlogicvector(sub_wire4_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
sub_wire2 <= inclk0;
sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=wizpll",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
width_clock => 5
)
PORT MAP (
inclk => sub_wire3,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "10"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "5.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "wizpll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "10"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL wizpll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL wizpll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL wizpll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL wizpll.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL wizpll.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL wizpll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
mit
|
maikmerten/riscv-tomthumb
|
src/vhdl/leds/leds_wb8.vhd
|
1
|
923
|
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.constants.all;
entity leds_wb8 is
Port(
-- naming according to Wishbone B4 spec
ADR_I: in std_logic_vector(31 downto 0);
CLK_I: in std_logic;
DAT_I: in std_logic_vector(7 downto 0);
STB_I: in std_logic;
WE_I: in std_logic;
ACK_O: out std_logic;
DAT_O: out std_logic_vector(7 downto 0);
-- control signal for onboard LEDs
O_leds: out std_logic_vector(7 downto 0)
);
end leds_wb8;
architecture Behavioral of leds_wb8 is
signal led_value: std_logic_vector(7 downto 0) := X"00";
begin
O_leds <= led_value;
process(CLK_I)
begin
if rising_edge(CLK_I) then
if STB_I = '1' then
if WE_I = '1' and ADR_I(3 downto 0) = X"0" then
led_value <= DAT_I;
else
DAT_O <= led_value;
end if;
ACK_O <= '1';
else
ACK_O <= '0';
end if;
end if;
end process;
end Behavioral;
|
mit
|
Derek-X-Wang/VGA-Text-Generator
|
VGA-Text-Generator.srcs/sources_1/new/wrapper.vhd
|
1
|
3564
|
-- This is a wrapper made for calling Pixel_On_Text.vhd form verilog
-- Since I'm not familiar with mapping string and structure(point_2d) bewteen verilog and vhdl, this is a simple walkaround.
-- By using Pixel_On_Text2.vhd, this file may not be necessary anymore.
-- However, sometimes it's a bit more convenient to group all you text in one place.
-- I also include some sample code for acheiving dynamic text(a simple way).
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
-- note this line.The package is compiled to this directory by default.
-- so don't forget to include this directory.
library work;
-- this line also is must.This includes the particular package into your program.
use work.commonPak.all;
entity wrapper is
Port (
clk: in std_logic;
xCoord: in std_logic_vector(11 downto 0);
yCoord: in std_logic_vector(11 downto 0);
pixOn: out std_logic
);
end wrapper;
architecture Behavioral of wrapper is
signal h : integer := to_integer(signed(xCoord));
signal v : integer := to_integer(signed(yCoord));
-- results
signal d1 : std_logic := '0';
signal d2 : std_logic := '0';
signal d3 : std_logic := '0';
begin
textElement1: entity work.Pixel_On_Text
generic map (
textLength => 38
)
port map(
clk => clk,
displayText => "Pixel_On_Text -- test 1!@#$ at (50,50)",
position => (50, 50),
horzCoord => h,
vertCoord => v,
pixel => d1
);
textElement2: entity work.Pixel_On_Text
generic map (
textLength => 39
)
port map(
clk => clk,
displayText => "Pixel_On_Text -- test 2%^&* at (500,50)",
position => (500, 50),
horzCoord => h,
vertCoord => v,
pixel => d2
);
textElement3: entity work.Pixel_On_Text
generic map (
textLength => 41
)
port map(
clk => clk,
displayText => "Pixel_On_Text -- test 3()_+-= at (50,130)",
position => (50, 130),
horzCoord => h,
vertCoord => v,
pixel => d3
);
-- -- This is a simply way for a dynamic text. Of course, I know you probably have a better solution :)
-- -- With a new input "timeDiv", we can switch on different string
-- with timeDiv select
-- timeDivDigitNum <= "Time/Div: 0.8 sec/div " when 0,
-- "Time/Div: 0.2 sec/div " when 1,
-- "Time/Div: 0.1 sec/div " when 2,
-- "Time/Div: 100 ms/div " when 3,
-- "Time/Div: 50 ms/div " when 4,
-- "Time/Div: 10 ms/div " when 5,
-- "Time/Div: 1 ms/div " when 6,
-- "Time/Div: 0.1ms/div " when 7,
-- "Time/Div: unknown " when OTHERS;
-- textDrawElement4: entity work.Pixel_On_Text
-- generic map (
-- textLength => 23
-- )
-- port map(
-- clk => clk,
-- reset => reset,
-- textPassage => timeDivDigitNum ,--& integer'image(timeDiv),
-- position => (70, 90),
-- hCount => h,
-- vCount => v,
-- drawElement => d4
-- );
pixelInTextGroup: process(clk)
begin
if rising_edge(clk) then
-- the pixel is on when one of the text matched
pixOn <= d1 or d2 or d3;
end if;
end process;
end Behavioral;
|
mit
|
notti/schaltungstechnik_vertiefung
|
Assignement/Task5/ps2receiver.vhd
|
1
|
3532
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
entity ps2Receiver is
generic(
TIMEOUT :integer := 5000 -- = 100us at 50Mhz
);
port(
clk : in std_logic;
rst : in std_logic;
-- data
rxData : out std_logic_vector(7 downto 0);
-- module sync signals
dataReady : out std_logic;
dataFetched : in std_logic;
-- ps2 pins
ps2Data : in std_logic;
ps2Clk : in std_logic
);
end entity ps2Receiver;
architecture RTL of ps2Receiver is
signal ps2Clk_sync : std_logic_vector(1 downto 0);
signal ps2Clk_dly : std_logic;
signal ps2Clk_fall : std_logic;
type state_type is (idle, wait_start, shift, check);
signal fsm : state_type;
signal data : std_logic_vector(10 downto 0);
signal bit_cnt : integer;
signal timeout_cnt : integer;
function xor_many(input : std_logic_vector) return std_logic is
variable result : std_logic;
variable i : integer;
begin
result := '0';
for i in input'low to input'high
loop
result := result xor input(i);
end loop;
return result;
end;
begin
ps2Clk_synchronizer: process(clk)
begin
if rising_edge(clk) then
ps2Clk_sync <= ps2Clk & ps2Clk_sync(1);
end if;
end process ps2Clk_synchronizer;
ps2Clk_delay: process(clk)
begin
if rising_edge(clk) then
ps2Clk_dly <= ps2Clk_sync(0);
end if;
end process ps2Clk_delay;
ps2Clk_fall <= (not ps2Clk_sync(0)) and ps2Clk_dly;
timeout_process: process(clk, rst)
begin
if rst = '1' then
timeout_cnt <= 0;
elsif rising_edge(clk) then
if ps2Clk_fall = '1' or timeout_cnt = TIMEOUT then
timeout_cnt <= 0;
else
timeout_cnt <= timeout_cnt + 1;
end if;
end if;
end process;
fsm_p: process(clk, rst)
begin
if rst = '1' then
fsm <= idle;
bit_cnt <= 0;
data <= (others => '1');
rxData <= (others => '0');
dataReady <= '0';
elsif rising_edge(clk) then
case fsm is
when idle =>
if dataFetched = '1' then
fsm <= wait_start;
dataReady <= '0';
end if;
when wait_start =>
if ps2Clk_fall = '1' and ps2Data = '0' then
fsm <= shift;
bit_cnt <= 0;
data <= (10 => '0', others => '1');
end if;
when shift =>
if timeout_cnt = TIMEOUT then
fsm <= idle;
end if;
if ps2Clk_fall = '1' then
bit_cnt <= bit_cnt + 1;
data <= ps2Data & data(10 downto 1);
end if;
if bit_cnt = 10 then
fsm <= check;
end if;
when check =>
fsm <= idle;
if xor_many(data(9 downto 1)) = '1' and data(0) = '0' and data(10) = '1' then
rxData <= data(8 downto 1);
dataReady <= '1';
end if;
end case;
end if;
end process fsm_p;
end architecture RTL;
|
mit
|
lucas2213690/TEC429--Projetos-de-Circuitos-Digitais
|
PBL_3/Comparador21.vhd
|
1
|
5041
|
-- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_compare
-- ============================================================
-- File Name: Comparador21.vhd
-- Megafunction Name(s):
-- lpm_compare
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.0 Build 132 02/25/2009 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY Comparador21 IS
PORT
(
clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
AeB : OUT STD_LOGIC ;
AgB : OUT STD_LOGIC
);
END Comparador21;
ARCHITECTURE SYN OF comparador21 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2_bv : BIT_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (4 DOWNTO 0);
COMPONENT lpm_compare
GENERIC (
lpm_hint : STRING;
lpm_pipeline : NATURAL;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
clock : IN STD_LOGIC ;
AgB : OUT STD_LOGIC ;
AeB : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire2_bv(4 DOWNTO 0) <= "10101";
sub_wire2 <= To_stdlogicvector(sub_wire2_bv);
AgB <= sub_wire0;
AeB <= sub_wire1;
lpm_compare_component : lpm_compare
GENERIC MAP (
lpm_hint => "ONE_INPUT_IS_CONSTANT=YES",
lpm_pipeline => 1,
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 5
)
PORT MAP (
dataa => dataa,
datab => sub_wire2,
clock => clock,
AgB => sub_wire0,
AeB => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "1"
-- Retrieval info: PRIVATE: AgeB NUMERIC "0"
-- Retrieval info: PRIVATE: AgtB NUMERIC "1"
-- Retrieval info: PRIVATE: AleB NUMERIC "0"
-- Retrieval info: PRIVATE: AltB NUMERIC "0"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "ACEX1K"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
-- Retrieval info: PRIVATE: Latency NUMERIC "1"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "21"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=YES"
-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "5"
-- Retrieval info: USED_PORT: AeB 0 0 0 0 OUTPUT NODEFVAL AeB
-- Retrieval info: USED_PORT: AgB 0 0 0 0 OUTPUT NODEFVAL AgB
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: dataa 0 0 5 0 INPUT NODEFVAL dataa[4..0]
-- Retrieval info: CONNECT: AeB 0 0 0 0 @AeB 0 0 0 0
-- Retrieval info: CONNECT: AgB 0 0 0 0 @AgB 0 0 0 0
-- Retrieval info: CONNECT: @dataa 0 0 5 0 dataa 0 0 5 0
-- Retrieval info: CONNECT: @datab 0 0 5 0 21 0 0 0 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL Comparador21.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Comparador21.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Comparador21.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Comparador21.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Comparador21_inst.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Comparador21_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL Comparador21_wave*.jpg TRUE
-- Retrieval info: LIB_FILE: lpm
|
mit
|
dawsonjon/Chips-Demo
|
synthesis/nexys_4/svga_hello_world/pwm.vhd
|
15
|
1069
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PWM is
generic(
MAX_VAL : integer := 256;
CLOCK_DIVIDER : integer := 256
);
port(
CLK : in std_logic;
DATA : in std_logic_vector(31 downto 0);
DATA_STB : in std_logic;
DATA_ACK : out std_logic;
OUT_BIT : out std_logic
);
end entity PWM;
architecture RTL of PWM is
signal TIMER : integer range 0 to CLOCK_DIVIDER - 1 := CLOCK_DIVIDER - 1;
signal COUNT : integer range 0 to MAX_VAL - 1 := 0;
signal PWM_VAL : integer range 0 to MAX_VAL := 0;
begin
DATA_ACK <= '1';
process
begin
wait until rising_edge(CLK);
if DATA_STB = '1' then
PWM_VAL <= to_integer(unsigned(DATA));
end if;
if TIMER = 0 then
if COUNT = MAX_VAL - 1 then
COUNT <= 0;
else
COUNT <= COUNT + 1;
end if;
TIMER <= CLOCK_DIVIDER-1;
else
TIMER <= TIMER-1;
end if;
if COUNT >= PWM_VAL then
OUT_BIT <= '0';
else
OUT_BIT <= '1';
end if;
end process;
end architecture RTL;
|
mit
|
dawsonjon/Chips-Demo
|
synthesis/nexys_4/audio_output/pwm.vhd
|
15
|
1069
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PWM is
generic(
MAX_VAL : integer := 256;
CLOCK_DIVIDER : integer := 256
);
port(
CLK : in std_logic;
DATA : in std_logic_vector(31 downto 0);
DATA_STB : in std_logic;
DATA_ACK : out std_logic;
OUT_BIT : out std_logic
);
end entity PWM;
architecture RTL of PWM is
signal TIMER : integer range 0 to CLOCK_DIVIDER - 1 := CLOCK_DIVIDER - 1;
signal COUNT : integer range 0 to MAX_VAL - 1 := 0;
signal PWM_VAL : integer range 0 to MAX_VAL := 0;
begin
DATA_ACK <= '1';
process
begin
wait until rising_edge(CLK);
if DATA_STB = '1' then
PWM_VAL <= to_integer(unsigned(DATA));
end if;
if TIMER = 0 then
if COUNT = MAX_VAL - 1 then
COUNT <= 0;
else
COUNT <= COUNT + 1;
end if;
TIMER <= CLOCK_DIVIDER-1;
else
TIMER <= TIMER-1;
end if;
if COUNT >= PWM_VAL then
OUT_BIT <= '0';
else
OUT_BIT <= '1';
end if;
end process;
end architecture RTL;
|
mit
|
dawsonjon/Chips-Demo
|
synthesis/nexys_4/image_processor/bsp.vhd
|
15
|
24719
|
-------------------------------------------------------------------------------
---
--- CHIPS - 2.0 Simple Web App Demo
---
--- :Author: Jonathan P Dawson
--- :Date: 04/04/2014
--- :email: [email protected]
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2014
---
--------------------------------------------------------------------------------
---
--- +--------------+
--- | CLOCK TREE |
--- +--------------+
--- | >-- CLK1 (50MHz) ---> CLK
--- CLK_IN >--> |
--- | >-- CLK2 (100MHz)
--- | | +-------+
--- | +-- CLK3 (125MHz) ->+ ODDR2 +-->[GTXCLK]
--- | | | |
--- | +-- CLK3_N (125MHZ) ->+ |
--- | | +-------+
--- RST >-----> >-- CLK4 (200MHz)
--- | |
--- | |
--- | | CLK >--+--------+
--- | | | |
--- | | +--v-+ +--v-+
--- | | | | | |
--- | LOCKED >------> >---> >-------> INTERNAL_RESET
--- | | | | | |
--- +--------------+ +----+ +----+
---
--- +-------------+
--- | USER DESIGN |
--- +-------------+
--- | |
--- | <-------< SWITCHES
--- | |
--- | >-------> LEDS
--- | |
--- | <-------< BUTTONS
--- | |
--- | >-------> SEVEN_SEGMENT_CATHODE
--- | |
--- | >-------> SEVEN_SEGMENT_ANNODE
--- | |
--- | | +--------------+
--- | | | UART |
--- | | +--------------+
--- | >-----> >-----> RS232-TX
--- | | | |
--- | | | <-------< RS232-RX
--- +---v-----^---+ +--------------+
--- | |
--- | |
--- +---v-----^---+
--- | ETHERNET |
--- | MAC |
--- +-------------+
--- | +------> [PHY_RESET]
--- | |
---[RXCLK] ----->+ +------> [TXCLK]
--- | |
--- | |
--- | |
--- [RXD] ----->+ +------> [TXD]
--- | |
--- [RXDV] ----->+ +------> [TXEN]
--- | |
--- [RXER] ----->+ +------> [TXER]
--- | |
--- | |
--- +-------------+
---
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity BSP is
port(
CLK_IN : in std_logic;
RST : in std_logic;
--PHY INTERFACE
ETH_CLK : out std_logic;
PHY_RESET_N : out std_logic;
RXDV : in std_logic;
RXER : in std_logic;
RXD : in std_logic_vector(1 downto 0);
TXD : out std_logic_vector(1 downto 0);
TXEN : out std_logic;
JC : inout std_logic_vector(7 downto 0);
--I2C
SDA : inout std_logic;
SCL : inout std_logic;
--PS2 keyboard interface
KD : in std_logic;
KC : in std_logic;
--AUDIO interface
AUDIO : out std_logic;
AUDIO_EN : out std_logic;
--VGA interface
VGA_R : out Std_logic_vector(3 downto 0);
VGA_G : out Std_logic_vector(3 downto 0);
VGA_B : out Std_logic_vector(3 downto 0);
HSYNCH : out Std_logic;
VSYNCH : out Std_logic;
--LEDS
GPIO_LEDS : out std_logic_vector(15 downto 0);
GPIO_SWITCHES : in std_logic_vector(15 downto 0);
GPIO_BUTTONS : in std_logic_vector(4 downto 0);
--RGB LED
LED_R_PWM : out std_logic;
LED_G_PWM : out std_logic;
LED_B_PWM : out std_logic;
SEVEN_SEGMENT_CATHODE : out std_logic_vector(6 downto 0);
SEVEN_SEGMENT_ANNODE : out std_logic_vector(7 downto 0);
--RS232 INTERFACE
RS232_RX : in std_logic;
RS232_TX : out std_logic
);
end entity BSP;
architecture RTL of BSP is
component rmii_ethernet is
port(
CLK : in std_logic;
RST : in std_logic;
ETH_CLK : in std_logic;
PHY_RESET : out std_logic;
--MII IF
TXD : out std_logic_vector(1 downto 0);
TXER : out std_logic;
TXEN : out std_logic;
RXD : in std_logic_vector(1 downto 0);
RXER : in std_logic;
RXDV : in std_logic;
--RX STREAM
TX : in std_logic_vector(15 downto 0);
TX_STB : in std_logic;
TX_ACK : out std_logic;
--RX STREAM
RX : out std_logic_vector(15 downto 0);
RX_STB : out std_logic;
RX_ACK : in std_logic
);
end component rmii_ethernet;
component CHARSVGA is
port (
CLK : in Std_logic;
DATA : in Std_logic_vector(31 downto 0);
DATA_ACK : out Std_logic;
DATA_STB : in Std_logic;
--VGA interface
VGACLK : in Std_logic;
RST : in Std_logic;
R : out Std_logic;
G : out Std_logic;
B : out Std_logic;
HSYNCH : out Std_logic;
VSYNCH : out Std_logic
);
end component CHARSVGA;
component PWM is
generic(
MAX_VAL : integer := 256;
CLOCK_DIVIDER : integer := 256
);
port(
CLK : in std_logic;
DATA : in std_logic_vector(31 downto 0);
DATA_STB : in std_logic;
DATA_ACK : out std_logic;
OUT_BIT : out std_logic
);
end component PWM;
component KEYBOARD is
port (
CLK : in Std_logic;
RST : in Std_logic;
DATA_STB : out Std_logic;
DATA_ACK : in Std_logic;
DATA : out Std_logic_vector (31 downto 0);
KD : in Std_logic;
KC : in Std_logic
);
end component KEYBOARD;
component I2C is
generic(
CLOCKS_PER_SECOND : integer := 50000000;
SPEED : integer := 100000
);
port(
CLK : in std_logic;
RST : in std_logic;
SDA : inout std_logic;
SCL : inout std_logic;
I2C_IN : in std_logic_vector(31 downto 0);
I2C_IN_STB : in std_logic;
I2C_IN_ACK : out std_logic;
I2C_OUT : out std_logic_vector(31 downto 0);
I2C_OUT_STB : out std_logic;
I2C_OUT_ACK : in std_logic
);
end component I2C;
component USER_DESIGN is
port(
CLK : in std_logic;
RST : in std_logic;
OUTPUT_LEDS : out std_logic_vector(31 downto 0);
OUTPUT_LEDS_STB : out std_logic;
OUTPUT_LEDS_ACK : in std_logic;
INPUT_SWITCHES : in std_logic_vector(31 downto 0);
INPUT_SWITCHES_STB : in std_logic;
INPUT_SWITCHES_ACK : out std_logic;
INPUT_BUTTONS : in std_logic_vector(31 downto 0);
INPUT_BUTTONS_STB : in std_logic;
INPUT_BUTTONS_ACK : out std_logic;
OUTPUT_VGA : out Std_logic_vector(31 downto 0);
OUTPUT_VGA_ACK : in Std_logic;
OUTPUT_VGA_STB : out Std_logic;
OUTPUT_AUDIO : out std_logic_vector(31 downto 0);
OUTPUT_AUDIO_STB : out std_logic;
OUTPUT_AUDIO_ACK : in std_logic;
OUTPUT_LED_R : out std_logic_vector(31 downto 0);
OUTPUT_LED_R_STB : out std_logic;
OUTPUT_LED_R_ACK : in std_logic;
OUTPUT_LED_G : out std_logic_vector(31 downto 0);
OUTPUT_LED_G_STB : out std_logic;
OUTPUT_LED_G_ACK : in std_logic;
OUTPUT_LED_B : out std_logic_vector(31 downto 0);
OUTPUT_LED_B_STB : out std_logic;
OUTPUT_LED_B_ACK : in std_logic;
OUTPUT_SEVEN_SEGMENT_CATHODE : out std_logic_vector(31 downto 0);
OUTPUT_SEVEN_SEGMENT_CATHODE_STB : out std_logic;
OUTPUT_SEVEN_SEGMENT_CATHODE_ACK : in std_logic;
OUTPUT_SEVEN_SEGMENT_ANNODE : out std_logic_vector(31 downto 0);
OUTPUT_SEVEN_SEGMENT_ANNODE_STB : out std_logic;
OUTPUT_SEVEN_SEGMENT_ANNODE_ACK : in std_logic;
INPUT_PS2 : in std_logic_vector(31 downto 0);
INPUT_PS2_STB : in std_logic;
INPUT_PS2_ACK : out std_logic;
INPUT_I2C : in std_logic_vector(31 downto 0);
INPUT_I2C_STB : in std_logic;
INPUT_I2C_ACK : out std_logic;
OUTPUT_I2C : out std_logic_vector(31 downto 0);
OUTPUT_I2C_STB : out std_logic;
OUTPUT_I2C_ACK : in std_logic;
--ETH RX STREAM
INPUT_ETH_RX : in std_logic_vector(31 downto 0);
INPUT_ETH_RX_STB : in std_logic;
INPUT_ETH_RX_ACK : out std_logic;
--ETH TX STREAM
OUTPUT_ETH_TX : out std_logic_vector(31 downto 0);
OUTPUT_ETH_TX_STB : out std_logic;
OUTPUT_ETH_TX_ACK : in std_logic;
--RS232 RX STREAM
INPUT_RS232_RX : in std_logic_vector(31 downto 0);
INPUT_RS232_RX_STB : in std_logic;
INPUT_RS232_RX_ACK : out std_logic;
--RS232 TX STREAM
OUTPUT_RS232_TX : out std_logic_vector(31 downto 0);
OUTPUT_RS232_TX_STB : out std_logic;
OUTPUT_RS232_TX_ACK : in std_logic
);
end component;
component SERIAL_INPUT is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
RX : in std_logic;
OUT1 : out std_logic_vector(7 downto 0);
OUT1_STB : out std_logic;
OUT1_ACK : in std_logic
);
end component SERIAL_INPUT;
component SERIAL_OUTPUT is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
TX : out std_logic;
IN1 : in std_logic_vector(7 downto 0);
IN1_STB : in std_logic;
IN1_ACK : out std_logic
);
end component serial_output;
component pwm_audio is
generic(
CLOCK_FREQUENCY : integer := 50000000;
SAMPLE_RATE : integer := 44100;
AUDIO_BITS : integer := 8
);
port(
CLK : in std_logic;
RST : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);
DATA_IN_STB : in std_logic;
DATA_IN_ACK : out std_logic;
AUDIO : out std_logic
);
end component pwm_audio;
--chips signals
signal CLK : std_logic;
--clock tree signals
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clk2x : std_logic;
signal clkfx : std_logic;
signal clkfx180 : std_logic;
signal clkdv : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
signal CLK_OUT1 : std_logic;
signal CLK_OUT2 : std_logic;
signal CLK_OUT3 : std_logic;
signal CLK_OUT3_N : std_logic;
signal CLK_OUT4 : std_logic;
signal NOT_LOCKED : std_logic;
signal RST_INV : std_logic;
signal INTERNAL_RST : std_logic;
--GPIO signals
signal OUTPUT_LEDS : std_logic_vector(31 downto 0);
signal OUTPUT_LEDS_STB : std_logic;
signal OUTPUT_LEDS_ACK : std_logic;
signal INPUT_SWITCHES : std_logic_vector(31 downto 0);
signal INPUT_SWITCHES_STB : std_logic;
signal INPUT_SWITCHES_ACK : std_logic;
signal GPIO_SWITCHES_D : std_logic_vector(15 downto 0);
signal INPUT_BUTTONS : std_logic_vector(31 downto 0);
signal INPUT_BUTTONS_STB : std_logic;
signal INPUT_BUTTONS_ACK : std_logic;
signal GPIO_BUTTONS_D : std_logic_vector(4 downto 0);
--SEVEN SEGMENT DISPLAY STREAM
signal OUTPUT_SEVEN_SEGMENT_CATHODE : std_logic_vector(31 downto 0);
signal OUTPUT_SEVEN_SEGMENT_CATHODE_STB : std_logic;
signal OUTPUT_SEVEN_SEGMENT_CATHODE_ACK : std_logic;
signal OUTPUT_SEVEN_SEGMENT_ANNODE : std_logic_vector(31 downto 0);
signal OUTPUT_SEVEN_SEGMENT_ANNODE_STB : std_logic;
signal OUTPUT_SEVEN_SEGMENT_ANNODE_ACK : std_logic;
--AUDIO
signal OUTPUT_AUDIO : std_logic_vector(31 downto 0);
signal OUTPUT_AUDIO_STB : std_logic;
signal OUTPUT_AUDIO_ACK : std_logic;
--Interface for SVGA
signal VGACLK : std_logic;
signal VGA_RR : std_logic;
signal VGA_GG : std_logic;
signal VGA_BB : std_logic;
signal OUTPUT_VGA : std_logic_vector(31 downto 0);
signal OUTPUT_VGA_ACK : std_logic;
signal OUTPUT_VGA_STB : std_logic;
--PS2 interface for kb/mouse
signal PS2_STB : std_logic;
signal PS2_ACK : std_logic;
signal PS2 : std_logic_vector (31 downto 0);
--I2C interface for temperature monitor
signal INPUT_I2C : std_logic_vector(31 downto 0);
signal INPUT_I2C_STB : std_logic;
signal INPUT_I2C_ACK : std_logic;
signal OUTPUT_I2C : std_logic_vector(31 downto 0);
signal OUTPUT_I2C_STB : std_logic;
signal OUTPUT_I2C_ACK : std_logic;
--ETH TX STREAM
signal ETH_TX : std_logic_vector(31 downto 0);
signal ETH_TX_STB : std_logic;
signal ETH_TX_ACK : std_logic;
--ETH RX STREAM
signal ETH_RX : std_logic_vector(31 downto 0);
signal ETH_RX_STB : std_logic;
signal ETH_RX_ACK : std_logic;
--RS232 RX STREAM
signal INPUT_RS232_RX : std_logic_vector(31 downto 0);
signal INPUT_RS232_RX_STB : std_logic;
signal INPUT_RS232_RX_ACK : std_logic;
--RS232 TX STREAM
signal OUTPUT_RS232_TX : std_logic_vector(31 downto 0);
signal OUTPUT_RS232_TX_STB : std_logic;
signal OUTPUT_RS232_TX_ACK : std_logic;
--tri color LED signals
signal LED_R : std_logic_vector(31 downto 0);
signal LED_R_STB : std_logic;
signal LED_R_ACK : std_logic;
signal LED_G : std_logic_vector(31 downto 0);
signal LED_G_STB : std_logic;
signal LED_G_ACK : std_logic;
signal LED_B : std_logic_vector(31 downto 0);
signal LED_B_STB : std_logic;
signal LED_B_ACK : std_logic;
begin
ethernet_inst_1 : rmii_ethernet port map(
CLK => CLK,
RST => INTERNAL_RST,
--GMII IF
ETH_CLK => CLK_OUT1,
TXD => TXD,
TXER => open,
TXEN => TXEN,
PHY_RESET => PHY_RESET_N,
RXD => RXD,
RXER => RXER,
RXDV => RXDV,
--RX STREAM
TX => ETH_TX(15 downto 0),
TX_STB => ETH_TX_STB,
TX_ACK => ETH_TX_ACK,
--RX STREAM
RX => ETH_RX(15 downto 0),
RX_STB => ETH_RX_STB,
RX_ACK => ETH_RX_ACK
);
CHARSVGA_INST_1 : CHARSVGA port map(
CLK => CLK,
DATA => OUTPUT_VGA,
DATA_ACK => OUTPUT_VGA_ACK,
DATA_STB => OUTPUT_VGA_STB,
--VGA interface
VGACLK => VGACLK,
RST => INTERNAL_RST,
R => VGA_RR,
G => VGA_GG,
B => VGA_BB,
HSYNCH => HSYNCH,
VSYNCH => VSYNCH
);
generate_vga : for I in 0 to 3 generate
VGA_R(I) <= VGA_RR;
VGA_G(I) <= VGA_GG;
VGA_B(I) <= VGA_BB;
end generate;
pwm_audio_inst_1 : pwm_audio
generic map(
CLOCK_FREQUENCY => 50000000,
SAMPLE_RATE => 44100,
AUDIO_BITS => 8
) port map (
CLK => CLK,
RST => INTERNAL_RST,
DATA_IN => OUTPUT_AUDIO,
DATA_IN_STB => OUTPUT_AUDIO_STB,
DATA_IN_ACK => OUTPUT_AUDIO_ACK,
AUDIO => AUDIO
);
AUDIO_EN <= '1';
JC(0) <= OUTPUT_AUDIO_STB;
JC(1) <= OUTPUT_AUDIO_ACK;
USER_DESIGN_INST_1 : USER_DESIGN port map(
CLK => CLK,
RST => INTERNAL_RST,
--GPIO interfaces
OUTPUT_LEDS => OUTPUT_LEDS,
OUTPUT_LEDS_STB => OUTPUT_LEDS_STB,
OUTPUT_LEDS_ACK => OUTPUT_LEDS_ACK,
INPUT_SWITCHES => INPUT_SWITCHES,
INPUT_SWITCHES_STB => INPUT_SWITCHES_STB,
INPUT_SWITCHES_ACK => INPUT_SWITCHES_ACK,
INPUT_BUTTONS => INPUT_BUTTONS,
INPUT_BUTTONS_STB => INPUT_BUTTONS_STB,
INPUT_BUTTONS_ACK => INPUT_BUTTONS_ACK,
--VGA interfave
OUTPUT_VGA => OUTPUT_VGA,
OUTPUT_VGA_ACK => OUTPUT_VGA_ACK,
OUTPUT_VGA_STB => OUTPUT_VGA_STB,
--TRI color LED interface
OUTPUT_LED_R => LED_R,
OUTPUT_LED_R_STB => LED_R_STB,
OUTPUT_LED_R_ACK => LED_R_ACK,
OUTPUT_LED_G => LED_G,
OUTPUT_LED_G_STB => LED_G_STB,
OUTPUT_LED_G_ACK => LED_G_ACK,
OUTPUT_LED_B => LED_B,
OUTPUT_LED_B_STB => LED_B_STB,
OUTPUT_LED_B_ACK => LED_B_ACK,
--RS232 RX STREAM
INPUT_RS232_RX => INPUT_RS232_RX,
INPUT_RS232_RX_STB => INPUT_RS232_RX_STB,
INPUT_RS232_RX_ACK => INPUT_RS232_RX_ACK,
--RS232 TX STREAM
OUTPUT_RS232_TX => OUTPUT_RS232_TX,
OUTPUT_RS232_TX_STB => OUTPUT_RS232_TX_STB,
OUTPUT_RS232_TX_ACK => OUTPUT_RS232_TX_ACK,
--AUDIO OUT
OUTPUT_AUDIO => OUTPUT_AUDIO,
OUTPUT_AUDIO_STB => OUTPUT_AUDIO_STB,
OUTPUT_AUDIO_ACK => OUTPUT_AUDIO_ACK,
--SEVEN SEGMENT DISPLAY INTERFACE
OUTPUT_SEVEN_SEGMENT_CATHODE => OUTPUT_SEVEN_SEGMENT_CATHODE,
OUTPUT_SEVEN_SEGMENT_CATHODE_STB => OUTPUT_SEVEN_SEGMENT_CATHODE_STB,
OUTPUT_SEVEN_SEGMENT_CATHODE_ACK => OUTPUT_SEVEN_SEGMENT_CATHODE_ACK,
OUTPUT_SEVEN_SEGMENT_ANNODE => OUTPUT_SEVEN_SEGMENT_ANNODE,
OUTPUT_SEVEN_SEGMENT_ANNODE_STB => OUTPUT_SEVEN_SEGMENT_ANNODE_STB,
OUTPUT_SEVEN_SEGMENT_ANNODE_ACK => OUTPUT_SEVEN_SEGMENT_ANNODE_ACK,
--PS2 KEYBOAD INTERFACE
INPUT_PS2_STB => PS2_STB,
INPUT_PS2_ACK => PS2_ACK,
INPUT_PS2 => PS2,
--I2C interface for temperature monitor
INPUT_I2C => OUTPUT_I2C,
INPUT_I2C_STB => OUTPUT_I2C_STB,
INPUT_I2C_ACK => OUTPUT_I2C_ACK,
OUTPUT_I2C => INPUT_I2C,
OUTPUT_I2C_STB => INPUT_I2C_STB,
OUTPUT_I2C_ACK => INPUT_I2C_ACK,
--ETH RX STREAM
INPUT_ETH_RX => ETH_RX,
INPUT_ETH_RX_STB => ETH_RX_STB,
INPUT_ETH_RX_ACK => ETH_RX_ACK,
--ETH TX STREAM
OUTPUT_ETH_TX => ETH_TX,
OUTPUT_ETH_TX_STB => ETH_TX_STB,
OUTPUT_ETH_TX_ACK => ETH_TX_ACK
);
SERIAL_OUTPUT_INST_1 : SERIAL_OUTPUT generic map(
CLOCK_FREQUENCY => 50000000,
BAUD_RATE => 115200
)port map(
CLK => CLK,
RST => INTERNAL_RST,
TX => RS232_TX,
IN1 => OUTPUT_RS232_TX(7 downto 0),
IN1_STB => OUTPUT_RS232_TX_STB,
IN1_ACK => OUTPUT_RS232_TX_ACK
);
SERIAL_INPUT_INST_1 : SERIAL_INPUT generic map(
CLOCK_FREQUENCY => 50000000,
BAUD_RATE => 115200
) port map (
CLK => CLK,
RST => INTERNAL_RST,
RX => RS232_RX,
OUT1 => INPUT_RS232_RX(7 downto 0),
OUT1_STB => INPUT_RS232_RX_STB,
OUT1_ACK => INPUT_RS232_RX_ACK
);
INPUT_RS232_RX(15 downto 8) <= (others => '0');
I2C_INST_1 : I2C generic map(
CLOCKS_PER_SECOND => 50000000,
SPEED => 10000
) port map (
CLK => CLK,
RST => INTERNAL_RST,
SDA => SDA,
SCL => SCL,
I2C_IN => INPUT_I2C,
I2C_IN_STB => INPUT_I2C_STB,
I2C_IN_ACK =>INPUT_I2C_ACK,
I2C_OUT => OUTPUT_I2C,
I2C_OUT_STB => OUTPUT_I2C_STB,
I2C_OUT_ACK => OUTPUT_I2C_ACK
);
PWM_INST_1 : PWM generic map(
MAX_VAL => 255,
CLOCK_DIVIDER => 1000
) port map (
CLK => CLK,
DATA => LED_R,
DATA_STB => LED_R_STB,
DATA_ACK => LED_R_ACK,
OUT_BIT => LED_R_PWM
);
PWM_INST_2 : PWM generic map(
MAX_VAL => 255,
CLOCK_DIVIDER => 1000
) port map (
CLK => CLK,
DATA => LED_G,
DATA_STB => LED_G_STB,
DATA_ACK => LED_G_ACK,
OUT_BIT => LED_G_PWM
);
PWM_INST_3 : PWM generic map(
MAX_VAL => 255,
CLOCK_DIVIDER => 1000
) port map (
CLK => CLK,
DATA => LED_B,
DATA_STB => LED_B_STB,
DATA_ACK => LED_B_ACK,
OUT_BIT => LED_B_PWM
);
KEYBOARD_INST1 : KEYBOARD port map(
CLK => CLK,
RST => INTERNAL_RST,
DATA_STB => PS2_STB,
DATA_ACK => PS2_ACK,
DATA => PS2,
KD => KD,
KC => KC
);
process
begin
wait until rising_edge(CLK);
NOT_LOCKED <= not LOCKED_INTERNAL;
INTERNAL_RST <= NOT_LOCKED;
if OUTPUT_LEDS_STB = '1' then
GPIO_LEDS <= OUTPUT_LEDS(15 downto 0);
end if;
OUTPUT_LEDS_ACK <= '1';
if OUTPUT_SEVEN_SEGMENT_ANNODE_STB = '1' then
SEVEN_SEGMENT_ANNODE <= not OUTPUT_SEVEN_SEGMENT_ANNODE(7 downto 0);
end if;
OUTPUT_SEVEN_SEGMENT_ANNODE_ACK <= '1';
if OUTPUT_SEVEN_SEGMENT_CATHODE_STB = '1' then
SEVEN_SEGMENT_CATHODE <= not OUTPUT_SEVEN_SEGMENT_CATHODE(6 downto 0);
end if;
OUTPUT_SEVEN_SEGMENT_CATHODE_ACK <= '1';
INPUT_SWITCHES_STB <= '1';
GPIO_SWITCHES_D <= GPIO_SWITCHES;
INPUT_SWITCHES <= (others => '0');
INPUT_SWITCHES(15 downto 0) <= GPIO_SWITCHES_D;
INPUT_BUTTONS_STB <= '1';
GPIO_BUTTONS_D <= GPIO_BUTTONS;
INPUT_BUTTONS <= (others => '0');
INPUT_BUTTONS(4 downto 0) <= GPIO_BUTTONS_D;
end process;
-------------------------
-- Output Output
-- Clock Freq (MHz)
-------------------------
-- CLK_OUT1 50.000
-- CLK_OUT2 100.000
-- CLK_OUT3 125.000
-- CLK_OUT4 200.000
----------------------------------
-- Input Clock Input Freq (MHz)
----------------------------------
-- primary 100.000
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 4,
CLKFX_MULTIPLY => 5,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 10.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => clk2x,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => clkfx180,
CLKDV => clkdv,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => LOCKED_INTERNAL,
STATUS => status_internal,
RST => RST_INV,
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
clkfb <= CLK_OUT2;
BUFG_INST1 : BUFG
port map
(O => CLK_OUT1,
I => clkdv);
BUFG_INST2 : BUFG
port map
(O => CLK_OUT2,
I => clk0);
BUFG_INST3 : BUFG
port map
(O => CLK_OUT3,
I => clkfx);
BUFG_INST4 : BUFG
port map
(O => CLK_OUT3_N,
I => clkfx180);
BUFG_INST5 : BUFG
port map
(O => CLK_OUT4,
I => clk2x);
RST_INV <= not RST;
ETH_CLK <= CLK_OUT1;
VGACLK <= CLK_OUT1;
-- Chips CLK frequency selection
-------------------------------------
CLK <= CLK_OUT1; --50 MHz
--CLK <= CLK_OUT2; --100 MHz
--CLK <= CLK_OUT3; --125 MHz
--CLK <= CLK_OUT4; --200 MHz
end architecture RTL;
|
mit
|
dawsonjon/Chips-Demo
|
synthesis/nexys_4/audio_output/bsp.vhd
|
15
|
24719
|
-------------------------------------------------------------------------------
---
--- CHIPS - 2.0 Simple Web App Demo
---
--- :Author: Jonathan P Dawson
--- :Date: 04/04/2014
--- :email: [email protected]
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2014
---
--------------------------------------------------------------------------------
---
--- +--------------+
--- | CLOCK TREE |
--- +--------------+
--- | >-- CLK1 (50MHz) ---> CLK
--- CLK_IN >--> |
--- | >-- CLK2 (100MHz)
--- | | +-------+
--- | +-- CLK3 (125MHz) ->+ ODDR2 +-->[GTXCLK]
--- | | | |
--- | +-- CLK3_N (125MHZ) ->+ |
--- | | +-------+
--- RST >-----> >-- CLK4 (200MHz)
--- | |
--- | |
--- | | CLK >--+--------+
--- | | | |
--- | | +--v-+ +--v-+
--- | | | | | |
--- | LOCKED >------> >---> >-------> INTERNAL_RESET
--- | | | | | |
--- +--------------+ +----+ +----+
---
--- +-------------+
--- | USER DESIGN |
--- +-------------+
--- | |
--- | <-------< SWITCHES
--- | |
--- | >-------> LEDS
--- | |
--- | <-------< BUTTONS
--- | |
--- | >-------> SEVEN_SEGMENT_CATHODE
--- | |
--- | >-------> SEVEN_SEGMENT_ANNODE
--- | |
--- | | +--------------+
--- | | | UART |
--- | | +--------------+
--- | >-----> >-----> RS232-TX
--- | | | |
--- | | | <-------< RS232-RX
--- +---v-----^---+ +--------------+
--- | |
--- | |
--- +---v-----^---+
--- | ETHERNET |
--- | MAC |
--- +-------------+
--- | +------> [PHY_RESET]
--- | |
---[RXCLK] ----->+ +------> [TXCLK]
--- | |
--- | |
--- | |
--- [RXD] ----->+ +------> [TXD]
--- | |
--- [RXDV] ----->+ +------> [TXEN]
--- | |
--- [RXER] ----->+ +------> [TXER]
--- | |
--- | |
--- +-------------+
---
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity BSP is
port(
CLK_IN : in std_logic;
RST : in std_logic;
--PHY INTERFACE
ETH_CLK : out std_logic;
PHY_RESET_N : out std_logic;
RXDV : in std_logic;
RXER : in std_logic;
RXD : in std_logic_vector(1 downto 0);
TXD : out std_logic_vector(1 downto 0);
TXEN : out std_logic;
JC : inout std_logic_vector(7 downto 0);
--I2C
SDA : inout std_logic;
SCL : inout std_logic;
--PS2 keyboard interface
KD : in std_logic;
KC : in std_logic;
--AUDIO interface
AUDIO : out std_logic;
AUDIO_EN : out std_logic;
--VGA interface
VGA_R : out Std_logic_vector(3 downto 0);
VGA_G : out Std_logic_vector(3 downto 0);
VGA_B : out Std_logic_vector(3 downto 0);
HSYNCH : out Std_logic;
VSYNCH : out Std_logic;
--LEDS
GPIO_LEDS : out std_logic_vector(15 downto 0);
GPIO_SWITCHES : in std_logic_vector(15 downto 0);
GPIO_BUTTONS : in std_logic_vector(4 downto 0);
--RGB LED
LED_R_PWM : out std_logic;
LED_G_PWM : out std_logic;
LED_B_PWM : out std_logic;
SEVEN_SEGMENT_CATHODE : out std_logic_vector(6 downto 0);
SEVEN_SEGMENT_ANNODE : out std_logic_vector(7 downto 0);
--RS232 INTERFACE
RS232_RX : in std_logic;
RS232_TX : out std_logic
);
end entity BSP;
architecture RTL of BSP is
component rmii_ethernet is
port(
CLK : in std_logic;
RST : in std_logic;
ETH_CLK : in std_logic;
PHY_RESET : out std_logic;
--MII IF
TXD : out std_logic_vector(1 downto 0);
TXER : out std_logic;
TXEN : out std_logic;
RXD : in std_logic_vector(1 downto 0);
RXER : in std_logic;
RXDV : in std_logic;
--RX STREAM
TX : in std_logic_vector(15 downto 0);
TX_STB : in std_logic;
TX_ACK : out std_logic;
--RX STREAM
RX : out std_logic_vector(15 downto 0);
RX_STB : out std_logic;
RX_ACK : in std_logic
);
end component rmii_ethernet;
component CHARSVGA is
port (
CLK : in Std_logic;
DATA : in Std_logic_vector(31 downto 0);
DATA_ACK : out Std_logic;
DATA_STB : in Std_logic;
--VGA interface
VGACLK : in Std_logic;
RST : in Std_logic;
R : out Std_logic;
G : out Std_logic;
B : out Std_logic;
HSYNCH : out Std_logic;
VSYNCH : out Std_logic
);
end component CHARSVGA;
component PWM is
generic(
MAX_VAL : integer := 256;
CLOCK_DIVIDER : integer := 256
);
port(
CLK : in std_logic;
DATA : in std_logic_vector(31 downto 0);
DATA_STB : in std_logic;
DATA_ACK : out std_logic;
OUT_BIT : out std_logic
);
end component PWM;
component KEYBOARD is
port (
CLK : in Std_logic;
RST : in Std_logic;
DATA_STB : out Std_logic;
DATA_ACK : in Std_logic;
DATA : out Std_logic_vector (31 downto 0);
KD : in Std_logic;
KC : in Std_logic
);
end component KEYBOARD;
component I2C is
generic(
CLOCKS_PER_SECOND : integer := 50000000;
SPEED : integer := 100000
);
port(
CLK : in std_logic;
RST : in std_logic;
SDA : inout std_logic;
SCL : inout std_logic;
I2C_IN : in std_logic_vector(31 downto 0);
I2C_IN_STB : in std_logic;
I2C_IN_ACK : out std_logic;
I2C_OUT : out std_logic_vector(31 downto 0);
I2C_OUT_STB : out std_logic;
I2C_OUT_ACK : in std_logic
);
end component I2C;
component USER_DESIGN is
port(
CLK : in std_logic;
RST : in std_logic;
OUTPUT_LEDS : out std_logic_vector(31 downto 0);
OUTPUT_LEDS_STB : out std_logic;
OUTPUT_LEDS_ACK : in std_logic;
INPUT_SWITCHES : in std_logic_vector(31 downto 0);
INPUT_SWITCHES_STB : in std_logic;
INPUT_SWITCHES_ACK : out std_logic;
INPUT_BUTTONS : in std_logic_vector(31 downto 0);
INPUT_BUTTONS_STB : in std_logic;
INPUT_BUTTONS_ACK : out std_logic;
OUTPUT_VGA : out Std_logic_vector(31 downto 0);
OUTPUT_VGA_ACK : in Std_logic;
OUTPUT_VGA_STB : out Std_logic;
OUTPUT_AUDIO : out std_logic_vector(31 downto 0);
OUTPUT_AUDIO_STB : out std_logic;
OUTPUT_AUDIO_ACK : in std_logic;
OUTPUT_LED_R : out std_logic_vector(31 downto 0);
OUTPUT_LED_R_STB : out std_logic;
OUTPUT_LED_R_ACK : in std_logic;
OUTPUT_LED_G : out std_logic_vector(31 downto 0);
OUTPUT_LED_G_STB : out std_logic;
OUTPUT_LED_G_ACK : in std_logic;
OUTPUT_LED_B : out std_logic_vector(31 downto 0);
OUTPUT_LED_B_STB : out std_logic;
OUTPUT_LED_B_ACK : in std_logic;
OUTPUT_SEVEN_SEGMENT_CATHODE : out std_logic_vector(31 downto 0);
OUTPUT_SEVEN_SEGMENT_CATHODE_STB : out std_logic;
OUTPUT_SEVEN_SEGMENT_CATHODE_ACK : in std_logic;
OUTPUT_SEVEN_SEGMENT_ANNODE : out std_logic_vector(31 downto 0);
OUTPUT_SEVEN_SEGMENT_ANNODE_STB : out std_logic;
OUTPUT_SEVEN_SEGMENT_ANNODE_ACK : in std_logic;
INPUT_PS2 : in std_logic_vector(31 downto 0);
INPUT_PS2_STB : in std_logic;
INPUT_PS2_ACK : out std_logic;
INPUT_I2C : in std_logic_vector(31 downto 0);
INPUT_I2C_STB : in std_logic;
INPUT_I2C_ACK : out std_logic;
OUTPUT_I2C : out std_logic_vector(31 downto 0);
OUTPUT_I2C_STB : out std_logic;
OUTPUT_I2C_ACK : in std_logic;
--ETH RX STREAM
INPUT_ETH_RX : in std_logic_vector(31 downto 0);
INPUT_ETH_RX_STB : in std_logic;
INPUT_ETH_RX_ACK : out std_logic;
--ETH TX STREAM
OUTPUT_ETH_TX : out std_logic_vector(31 downto 0);
OUTPUT_ETH_TX_STB : out std_logic;
OUTPUT_ETH_TX_ACK : in std_logic;
--RS232 RX STREAM
INPUT_RS232_RX : in std_logic_vector(31 downto 0);
INPUT_RS232_RX_STB : in std_logic;
INPUT_RS232_RX_ACK : out std_logic;
--RS232 TX STREAM
OUTPUT_RS232_TX : out std_logic_vector(31 downto 0);
OUTPUT_RS232_TX_STB : out std_logic;
OUTPUT_RS232_TX_ACK : in std_logic
);
end component;
component SERIAL_INPUT is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
RX : in std_logic;
OUT1 : out std_logic_vector(7 downto 0);
OUT1_STB : out std_logic;
OUT1_ACK : in std_logic
);
end component SERIAL_INPUT;
component SERIAL_OUTPUT is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
TX : out std_logic;
IN1 : in std_logic_vector(7 downto 0);
IN1_STB : in std_logic;
IN1_ACK : out std_logic
);
end component serial_output;
component pwm_audio is
generic(
CLOCK_FREQUENCY : integer := 50000000;
SAMPLE_RATE : integer := 44100;
AUDIO_BITS : integer := 8
);
port(
CLK : in std_logic;
RST : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);
DATA_IN_STB : in std_logic;
DATA_IN_ACK : out std_logic;
AUDIO : out std_logic
);
end component pwm_audio;
--chips signals
signal CLK : std_logic;
--clock tree signals
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clk2x : std_logic;
signal clkfx : std_logic;
signal clkfx180 : std_logic;
signal clkdv : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
signal CLK_OUT1 : std_logic;
signal CLK_OUT2 : std_logic;
signal CLK_OUT3 : std_logic;
signal CLK_OUT3_N : std_logic;
signal CLK_OUT4 : std_logic;
signal NOT_LOCKED : std_logic;
signal RST_INV : std_logic;
signal INTERNAL_RST : std_logic;
--GPIO signals
signal OUTPUT_LEDS : std_logic_vector(31 downto 0);
signal OUTPUT_LEDS_STB : std_logic;
signal OUTPUT_LEDS_ACK : std_logic;
signal INPUT_SWITCHES : std_logic_vector(31 downto 0);
signal INPUT_SWITCHES_STB : std_logic;
signal INPUT_SWITCHES_ACK : std_logic;
signal GPIO_SWITCHES_D : std_logic_vector(15 downto 0);
signal INPUT_BUTTONS : std_logic_vector(31 downto 0);
signal INPUT_BUTTONS_STB : std_logic;
signal INPUT_BUTTONS_ACK : std_logic;
signal GPIO_BUTTONS_D : std_logic_vector(4 downto 0);
--SEVEN SEGMENT DISPLAY STREAM
signal OUTPUT_SEVEN_SEGMENT_CATHODE : std_logic_vector(31 downto 0);
signal OUTPUT_SEVEN_SEGMENT_CATHODE_STB : std_logic;
signal OUTPUT_SEVEN_SEGMENT_CATHODE_ACK : std_logic;
signal OUTPUT_SEVEN_SEGMENT_ANNODE : std_logic_vector(31 downto 0);
signal OUTPUT_SEVEN_SEGMENT_ANNODE_STB : std_logic;
signal OUTPUT_SEVEN_SEGMENT_ANNODE_ACK : std_logic;
--AUDIO
signal OUTPUT_AUDIO : std_logic_vector(31 downto 0);
signal OUTPUT_AUDIO_STB : std_logic;
signal OUTPUT_AUDIO_ACK : std_logic;
--Interface for SVGA
signal VGACLK : std_logic;
signal VGA_RR : std_logic;
signal VGA_GG : std_logic;
signal VGA_BB : std_logic;
signal OUTPUT_VGA : std_logic_vector(31 downto 0);
signal OUTPUT_VGA_ACK : std_logic;
signal OUTPUT_VGA_STB : std_logic;
--PS2 interface for kb/mouse
signal PS2_STB : std_logic;
signal PS2_ACK : std_logic;
signal PS2 : std_logic_vector (31 downto 0);
--I2C interface for temperature monitor
signal INPUT_I2C : std_logic_vector(31 downto 0);
signal INPUT_I2C_STB : std_logic;
signal INPUT_I2C_ACK : std_logic;
signal OUTPUT_I2C : std_logic_vector(31 downto 0);
signal OUTPUT_I2C_STB : std_logic;
signal OUTPUT_I2C_ACK : std_logic;
--ETH TX STREAM
signal ETH_TX : std_logic_vector(31 downto 0);
signal ETH_TX_STB : std_logic;
signal ETH_TX_ACK : std_logic;
--ETH RX STREAM
signal ETH_RX : std_logic_vector(31 downto 0);
signal ETH_RX_STB : std_logic;
signal ETH_RX_ACK : std_logic;
--RS232 RX STREAM
signal INPUT_RS232_RX : std_logic_vector(31 downto 0);
signal INPUT_RS232_RX_STB : std_logic;
signal INPUT_RS232_RX_ACK : std_logic;
--RS232 TX STREAM
signal OUTPUT_RS232_TX : std_logic_vector(31 downto 0);
signal OUTPUT_RS232_TX_STB : std_logic;
signal OUTPUT_RS232_TX_ACK : std_logic;
--tri color LED signals
signal LED_R : std_logic_vector(31 downto 0);
signal LED_R_STB : std_logic;
signal LED_R_ACK : std_logic;
signal LED_G : std_logic_vector(31 downto 0);
signal LED_G_STB : std_logic;
signal LED_G_ACK : std_logic;
signal LED_B : std_logic_vector(31 downto 0);
signal LED_B_STB : std_logic;
signal LED_B_ACK : std_logic;
begin
ethernet_inst_1 : rmii_ethernet port map(
CLK => CLK,
RST => INTERNAL_RST,
--GMII IF
ETH_CLK => CLK_OUT1,
TXD => TXD,
TXER => open,
TXEN => TXEN,
PHY_RESET => PHY_RESET_N,
RXD => RXD,
RXER => RXER,
RXDV => RXDV,
--RX STREAM
TX => ETH_TX(15 downto 0),
TX_STB => ETH_TX_STB,
TX_ACK => ETH_TX_ACK,
--RX STREAM
RX => ETH_RX(15 downto 0),
RX_STB => ETH_RX_STB,
RX_ACK => ETH_RX_ACK
);
CHARSVGA_INST_1 : CHARSVGA port map(
CLK => CLK,
DATA => OUTPUT_VGA,
DATA_ACK => OUTPUT_VGA_ACK,
DATA_STB => OUTPUT_VGA_STB,
--VGA interface
VGACLK => VGACLK,
RST => INTERNAL_RST,
R => VGA_RR,
G => VGA_GG,
B => VGA_BB,
HSYNCH => HSYNCH,
VSYNCH => VSYNCH
);
generate_vga : for I in 0 to 3 generate
VGA_R(I) <= VGA_RR;
VGA_G(I) <= VGA_GG;
VGA_B(I) <= VGA_BB;
end generate;
pwm_audio_inst_1 : pwm_audio
generic map(
CLOCK_FREQUENCY => 50000000,
SAMPLE_RATE => 44100,
AUDIO_BITS => 8
) port map (
CLK => CLK,
RST => INTERNAL_RST,
DATA_IN => OUTPUT_AUDIO,
DATA_IN_STB => OUTPUT_AUDIO_STB,
DATA_IN_ACK => OUTPUT_AUDIO_ACK,
AUDIO => AUDIO
);
AUDIO_EN <= '1';
JC(0) <= OUTPUT_AUDIO_STB;
JC(1) <= OUTPUT_AUDIO_ACK;
USER_DESIGN_INST_1 : USER_DESIGN port map(
CLK => CLK,
RST => INTERNAL_RST,
--GPIO interfaces
OUTPUT_LEDS => OUTPUT_LEDS,
OUTPUT_LEDS_STB => OUTPUT_LEDS_STB,
OUTPUT_LEDS_ACK => OUTPUT_LEDS_ACK,
INPUT_SWITCHES => INPUT_SWITCHES,
INPUT_SWITCHES_STB => INPUT_SWITCHES_STB,
INPUT_SWITCHES_ACK => INPUT_SWITCHES_ACK,
INPUT_BUTTONS => INPUT_BUTTONS,
INPUT_BUTTONS_STB => INPUT_BUTTONS_STB,
INPUT_BUTTONS_ACK => INPUT_BUTTONS_ACK,
--VGA interfave
OUTPUT_VGA => OUTPUT_VGA,
OUTPUT_VGA_ACK => OUTPUT_VGA_ACK,
OUTPUT_VGA_STB => OUTPUT_VGA_STB,
--TRI color LED interface
OUTPUT_LED_R => LED_R,
OUTPUT_LED_R_STB => LED_R_STB,
OUTPUT_LED_R_ACK => LED_R_ACK,
OUTPUT_LED_G => LED_G,
OUTPUT_LED_G_STB => LED_G_STB,
OUTPUT_LED_G_ACK => LED_G_ACK,
OUTPUT_LED_B => LED_B,
OUTPUT_LED_B_STB => LED_B_STB,
OUTPUT_LED_B_ACK => LED_B_ACK,
--RS232 RX STREAM
INPUT_RS232_RX => INPUT_RS232_RX,
INPUT_RS232_RX_STB => INPUT_RS232_RX_STB,
INPUT_RS232_RX_ACK => INPUT_RS232_RX_ACK,
--RS232 TX STREAM
OUTPUT_RS232_TX => OUTPUT_RS232_TX,
OUTPUT_RS232_TX_STB => OUTPUT_RS232_TX_STB,
OUTPUT_RS232_TX_ACK => OUTPUT_RS232_TX_ACK,
--AUDIO OUT
OUTPUT_AUDIO => OUTPUT_AUDIO,
OUTPUT_AUDIO_STB => OUTPUT_AUDIO_STB,
OUTPUT_AUDIO_ACK => OUTPUT_AUDIO_ACK,
--SEVEN SEGMENT DISPLAY INTERFACE
OUTPUT_SEVEN_SEGMENT_CATHODE => OUTPUT_SEVEN_SEGMENT_CATHODE,
OUTPUT_SEVEN_SEGMENT_CATHODE_STB => OUTPUT_SEVEN_SEGMENT_CATHODE_STB,
OUTPUT_SEVEN_SEGMENT_CATHODE_ACK => OUTPUT_SEVEN_SEGMENT_CATHODE_ACK,
OUTPUT_SEVEN_SEGMENT_ANNODE => OUTPUT_SEVEN_SEGMENT_ANNODE,
OUTPUT_SEVEN_SEGMENT_ANNODE_STB => OUTPUT_SEVEN_SEGMENT_ANNODE_STB,
OUTPUT_SEVEN_SEGMENT_ANNODE_ACK => OUTPUT_SEVEN_SEGMENT_ANNODE_ACK,
--PS2 KEYBOAD INTERFACE
INPUT_PS2_STB => PS2_STB,
INPUT_PS2_ACK => PS2_ACK,
INPUT_PS2 => PS2,
--I2C interface for temperature monitor
INPUT_I2C => OUTPUT_I2C,
INPUT_I2C_STB => OUTPUT_I2C_STB,
INPUT_I2C_ACK => OUTPUT_I2C_ACK,
OUTPUT_I2C => INPUT_I2C,
OUTPUT_I2C_STB => INPUT_I2C_STB,
OUTPUT_I2C_ACK => INPUT_I2C_ACK,
--ETH RX STREAM
INPUT_ETH_RX => ETH_RX,
INPUT_ETH_RX_STB => ETH_RX_STB,
INPUT_ETH_RX_ACK => ETH_RX_ACK,
--ETH TX STREAM
OUTPUT_ETH_TX => ETH_TX,
OUTPUT_ETH_TX_STB => ETH_TX_STB,
OUTPUT_ETH_TX_ACK => ETH_TX_ACK
);
SERIAL_OUTPUT_INST_1 : SERIAL_OUTPUT generic map(
CLOCK_FREQUENCY => 50000000,
BAUD_RATE => 115200
)port map(
CLK => CLK,
RST => INTERNAL_RST,
TX => RS232_TX,
IN1 => OUTPUT_RS232_TX(7 downto 0),
IN1_STB => OUTPUT_RS232_TX_STB,
IN1_ACK => OUTPUT_RS232_TX_ACK
);
SERIAL_INPUT_INST_1 : SERIAL_INPUT generic map(
CLOCK_FREQUENCY => 50000000,
BAUD_RATE => 115200
) port map (
CLK => CLK,
RST => INTERNAL_RST,
RX => RS232_RX,
OUT1 => INPUT_RS232_RX(7 downto 0),
OUT1_STB => INPUT_RS232_RX_STB,
OUT1_ACK => INPUT_RS232_RX_ACK
);
INPUT_RS232_RX(15 downto 8) <= (others => '0');
I2C_INST_1 : I2C generic map(
CLOCKS_PER_SECOND => 50000000,
SPEED => 10000
) port map (
CLK => CLK,
RST => INTERNAL_RST,
SDA => SDA,
SCL => SCL,
I2C_IN => INPUT_I2C,
I2C_IN_STB => INPUT_I2C_STB,
I2C_IN_ACK =>INPUT_I2C_ACK,
I2C_OUT => OUTPUT_I2C,
I2C_OUT_STB => OUTPUT_I2C_STB,
I2C_OUT_ACK => OUTPUT_I2C_ACK
);
PWM_INST_1 : PWM generic map(
MAX_VAL => 255,
CLOCK_DIVIDER => 1000
) port map (
CLK => CLK,
DATA => LED_R,
DATA_STB => LED_R_STB,
DATA_ACK => LED_R_ACK,
OUT_BIT => LED_R_PWM
);
PWM_INST_2 : PWM generic map(
MAX_VAL => 255,
CLOCK_DIVIDER => 1000
) port map (
CLK => CLK,
DATA => LED_G,
DATA_STB => LED_G_STB,
DATA_ACK => LED_G_ACK,
OUT_BIT => LED_G_PWM
);
PWM_INST_3 : PWM generic map(
MAX_VAL => 255,
CLOCK_DIVIDER => 1000
) port map (
CLK => CLK,
DATA => LED_B,
DATA_STB => LED_B_STB,
DATA_ACK => LED_B_ACK,
OUT_BIT => LED_B_PWM
);
KEYBOARD_INST1 : KEYBOARD port map(
CLK => CLK,
RST => INTERNAL_RST,
DATA_STB => PS2_STB,
DATA_ACK => PS2_ACK,
DATA => PS2,
KD => KD,
KC => KC
);
process
begin
wait until rising_edge(CLK);
NOT_LOCKED <= not LOCKED_INTERNAL;
INTERNAL_RST <= NOT_LOCKED;
if OUTPUT_LEDS_STB = '1' then
GPIO_LEDS <= OUTPUT_LEDS(15 downto 0);
end if;
OUTPUT_LEDS_ACK <= '1';
if OUTPUT_SEVEN_SEGMENT_ANNODE_STB = '1' then
SEVEN_SEGMENT_ANNODE <= not OUTPUT_SEVEN_SEGMENT_ANNODE(7 downto 0);
end if;
OUTPUT_SEVEN_SEGMENT_ANNODE_ACK <= '1';
if OUTPUT_SEVEN_SEGMENT_CATHODE_STB = '1' then
SEVEN_SEGMENT_CATHODE <= not OUTPUT_SEVEN_SEGMENT_CATHODE(6 downto 0);
end if;
OUTPUT_SEVEN_SEGMENT_CATHODE_ACK <= '1';
INPUT_SWITCHES_STB <= '1';
GPIO_SWITCHES_D <= GPIO_SWITCHES;
INPUT_SWITCHES <= (others => '0');
INPUT_SWITCHES(15 downto 0) <= GPIO_SWITCHES_D;
INPUT_BUTTONS_STB <= '1';
GPIO_BUTTONS_D <= GPIO_BUTTONS;
INPUT_BUTTONS <= (others => '0');
INPUT_BUTTONS(4 downto 0) <= GPIO_BUTTONS_D;
end process;
-------------------------
-- Output Output
-- Clock Freq (MHz)
-------------------------
-- CLK_OUT1 50.000
-- CLK_OUT2 100.000
-- CLK_OUT3 125.000
-- CLK_OUT4 200.000
----------------------------------
-- Input Clock Input Freq (MHz)
----------------------------------
-- primary 100.000
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 4,
CLKFX_MULTIPLY => 5,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 10.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => clk2x,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => clkfx180,
CLKDV => clkdv,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => LOCKED_INTERNAL,
STATUS => status_internal,
RST => RST_INV,
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
clkfb <= CLK_OUT2;
BUFG_INST1 : BUFG
port map
(O => CLK_OUT1,
I => clkdv);
BUFG_INST2 : BUFG
port map
(O => CLK_OUT2,
I => clk0);
BUFG_INST3 : BUFG
port map
(O => CLK_OUT3,
I => clkfx);
BUFG_INST4 : BUFG
port map
(O => CLK_OUT3_N,
I => clkfx180);
BUFG_INST5 : BUFG
port map
(O => CLK_OUT4,
I => clk2x);
RST_INV <= not RST;
ETH_CLK <= CLK_OUT1;
VGACLK <= CLK_OUT1;
-- Chips CLK frequency selection
-------------------------------------
CLK <= CLK_OUT1; --50 MHz
--CLK <= CLK_OUT2; --100 MHz
--CLK <= CLK_OUT3; --125 MHz
--CLK <= CLK_OUT4; --200 MHz
end architecture RTL;
|
mit
|
dawsonjon/Chips-Demo
|
demo/bsp_components/test_bench/pwm_tb.vhd
|
1
|
1653
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PWM_TB is
end entity;
architecture RTL of PWM_TB is
component PWM is
generic(
MAX_VAL : integer := 256;
CLOCK_DIVIDER : integer := 256
);
port(
CLK : in std_logic;
DATA : in std_logic_vector(31 downto 0);
DATA_STB : in std_logic;
DATA_ACK : out std_logic;
OUT_BIT : out std_logic
);
end component PWM;
signal CLK : std_logic;
signal DATA : std_logic_vector(31 downto 0);
signal DATA_STB : std_logic;
signal DATA_ACK : std_logic;
signal OUT_BIT : std_logic;
begin
process
begin
while True loop
CLK <= '0';
wait for 10.0 ns;
CLK <= '1';
wait for 10.0 ns;
end loop;
wait;
end process;
PWM_INST_1 : PWM generic map(
MAX_VAL => 255,
CLOCK_DIVIDER => 10
) port map(
CLK => CLK,
DATA => DATA,
DATA_STB => DATA_STB,
DATA_ACK => DATA_ACK,
OUT_BIT => OUT_BIT
);
process
begin
wait for 200 ns;
wait until rising_edge(CLK);
DATA <= X"000000FF";
DATA_STB <= '1';
wait until rising_edge(CLK);
DATA_STB <= '0';
wait for 200 us;
wait until rising_edge(CLK);
DATA <= X"0000007F";
DATA_STB <= '1';
wait until rising_edge(CLK);
DATA_STB <= '0';
wait for 200 us;
wait until rising_edge(CLK);
DATA <= X"0000003F";
DATA_STB <= '1';
wait until rising_edge(CLK);
DATA_STB <= '0';
wait for 200 us;
wait until rising_edge(CLK);
DATA <= X"00000000";
DATA_STB <= '1';
wait until rising_edge(CLK);
DATA_STB <= '0';
wait;
end process;
end architecture RTL;
|
mit
|
dawsonjon/Chips-Demo
|
synthesis/nexys_4/benchmark/svga_package.vhd
|
15
|
25646
|
-- ****************************************************************************
-- Filename :svga_package.vhd
-- Project :Wishbone VGA Core
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2005-12-18
-- ****************************************************************************
-- Description :A package defining the carachter glyphs.
-- ****************************************************************************
-- Dependencies :Standard Libraries
-- ****************************************************************************
-- Revision History :
--
-- Date :2005-12-18
-- Author :Jonathan P Dawson
-- Modification: Created File
--
-- ****************************************************************************
-- Copyright (C) Jonathan P Dawson 2005
-- ****************************************************************************
library IEEE;
use Ieee.std_logic_1164.all;
package PIXPACKAGE is
type PIX_ARRAY_TYPE is array (0 to 2047) of Std_logic_vector(7 downto 0);
constant PIXARRAY : PIX_ARRAY_TYPE := (
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --0d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --1d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --2d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --3d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --4d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --5d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --6d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --7d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --8d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --9d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --10d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --11d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --12d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --13d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --14d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --15d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --16d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --17d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --18d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --19d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --20d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --21d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --22d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --23d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --24d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --25d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --26d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --27d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --28d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --29d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --30d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --31d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --space
"00001000","00001000","00001000","00001000","00000000","00001000","00000000","00000000", --!
"00010100","00010100","00000000","00000000","00000000","00000000","00000000","00000000", --"
"00000000","00010100","00111110","00010100","00111110","00010100","00000000","00000000", --#
"00001000","00111100","00001010","00011100","00101000","00011110","00001000","00000000", --$
"10001110","01001010","00101110","00010000","11101000","10100100","11100010","00000000", --%
"00001100","00010010","00010010","00001100","00110010","00010010","01101100","00000000", ----'
"00001000","00001000","00000000","00000000","00000000","00000000","00000000","00000000", --(
"00001000","00000100","00000010","00000010","00000010","00000100","00001000","00000000", --)
"00001000","00010000","00100000","00100000","00100000","00010000","00001000","00000000", --*
"00001000","00111110","00010100","00100010","00000000","00000000","00000000","00000000", --+
"00010000","00010000","00010000","11111110","00010000","00010000","00010000","00000000", --,
"00000000","00000000","00000000","00000000","00000000","00001000","00001000","00000000", ---
"00000000","00000000","00000000","00111110","00000000","00000000","00000000","00000000", --.
"00000000","00000000","00000000","00000000","00000000","00001000","00000000","00000000", --/
"01000000","00100000","00010000","00001000","00000100","00000010","00000000","00000000", --0
"00011100","00110010","00101010","00101010","00100110","00011100","00000000","00000000", --1
"00001000","00001100","00001000","00001000","00001000","00111110","00000000","00000000", --2
"00011100","00100010","00010000","00001000","00000100","00111110","00000000","00000000", --3
"00011100","00100010","00010000","00100000","00100010","00011100","00000000","00000000", --4
"00011000","00010100","00010010","00111110","00010000","00111100","00000000","00000000", --5
"00111110","00000010","00111110","00100000","00100010","00011100","00000000","00000000", --6
"00011100","00100010","00000010","00011110","00100010","00011100","00000000","00000000", --7
"00111110","00100010","00100000","00010000","00001000","00001000","00000000","00000000", --8
"00011100","00100010","00011100","00100010","00100010","00011100","00000000","00000000", --9
"00011100","00100010","00111100","00100000","00100010","00011100","00000000","00000000", --:
"00000000","00001000","00000000","00000000","00000000","00001000","00000000","00000000", --;
"00000000","00001000","00000000","00000000","00000000","00001000","00001000","00000000", --<
"00010000","00001000","00000100","00000010","00000100","00001000","00010000","00000000", --=
"00000000","00000000","00111110","00000000","00000000","00111110","00000000","00000000", -->
"00000010","00000100","00001000","00010000","00001000","00000100","00000010","00000000", --?
"00011100","00100010","00011000","00001000","00000000","00001000","00000000","00000000", --@
"01111100","10000010","10111010","10101010","10111010","10100010","01101100","00000000", --A
"00011100","00100010","00111110","00100010","00100010","00100010","00000000","00000000", --B
"00011110","00100010","00011110","00100010","00100010","00011110","00000000","00000000", --C
"00011100","00100010","00000010","00000010","00100010","00011100","00000000","00000000", --D
"00011110","00100010","00100010","00100010","00100010","00011110","00000000","00000000", --E
"00111110","00000010","00011110","00000010","00000010","00111110","00000000","00000000", --F
"00111110","00000010","00011110","00000010","00000010","00000010","00000000","00000000", --G
"00011100","00100010","00000010","00111010","00100010","00011100","00000000","00000000", --H
"00100010","00100010","00111110","00100010","00100010","00100010","00000000","00000000", --I
"00111110","00001000","00001000","00001000","00001000","00111110","00000000","00000000", --J
"00111000","00010000","00010000","00010000","00010010","00001100","00000000","00000000", --K
"00010010","00001010","00000110","00001010","00010010","00100010","00000000","00000000", --L
"00000010","00000010","00000010","00000010","00000010","00111110","00000000","00000000", --M
"00100010","00110110","00101010","00101010","00100010","00100010","00000000","00000000", --N
"00100010","00100010","00100110","00101010","00110010","00100010","00000000","00000000", --O
"00011100","00100010","00100010","00100010","00100010","00011100","00000000","00000000", --P
"00011110","00100010","00100010","00011110","00000010","00000010","00000000","00000000", --Q
"00011100","00100010","00100010","00100010","00100010","00011100","01101000","00000000", --R
"00011110","00100010","00011110","00001010","00010010","00100010","00000000","00000000", --S
"00111100","00000010","00011100","00100000","00100000","00011110","00000000","00000000", --T
"00111110","00001000","00001000","00001000","00001000","00001000","00000000","00000000", --U
"00100010","00100010","00100010","00100010","00100010","00011100","00000000","00000000", --V
"00100010","00100010","00100010","00010100","00010100","00001000","00000000","00000000", --W
"00100010","00100010","00100010","00101010","00101010","00010100","00000000","00000000", --X
"00100010","00010100","00001000","00001000","00010100","00100010","00000000","00000000", --Y
"00100010","00100010","00011100","00001000","00001000","00001000","00000000","00000000", --Z
"00111110","00010000","00001000","00000100","00000010","00111110","00000000","00000000", --[
"00011000","00001000","00001000","00001000","00001000","00001000","00011000","00000000", --\
"00000010","00000100","00001000","00010000","00100000","01000000","00000000","00000000", --]
"00011000","00010000","00010000","00010000","00010000","00010000","00011000","00000000", --^
"00001000","00010100","00100010","00000000","00000000","00000000","00000000","00000000", --_
"00000000","00000000","00000000","00000000","00000000","00000000","11111111","00000000", --`
"00001000","00010000","00000000","00000000","00000000","00000000","00000000","00000000", --a
"00000000","00011100","00100000","00111100","00100010","01011100","00000000","00000000", --b
"00000010","00000010","00011010","00100110","00100010","00011110","00000000","00000000", --c
"00000000","00011100","00000010","00000010","00100010","00011100","00000000","00000000", --d
"00100000","00100000","00101100","00110010","00100010","00111100","00000000","00000000", --e
"00000000","00011100","00100010","00111110","00000010","00011100","00000000","00000000", --f
"00011100","00100010","00000010","00001110","00000010","00000010","00000000","00000000", --g
"00000000","00111100","00100010","00100010","00111100","00100000","00011100","00000000", --h
"00000010","00000010","00011010","00100110","00100010","00100010","00000000","00000000", --i
"00001000","00000000","00001100","00001000","00001000","00011100","00000000","00000000", --j
"00010000","00000000","00011000","00010000","00010000","00010010","00001100","00000000", --k
"00000010","00010010","00001010","00001110","00010010","00100010","00000000","00000000", --l
"00001100","00001000","00001000","00001000","00001000","00111110","00000000","00000000", --m
"00000000","00010110","00101010","00101010","00101010","00101010","00000000","00000000", --n
"00000000","00011010","00100100","00100100","00100100","00100100","00000000","00000000", --o
"00000000","00011100","00100010","00100010","00100010","00011100","00000000","00000000", --p
"00000000","00011110","00100010","00100010","00011110","00000010","00000010","00000000", --q
"00000000","00101100","00110010","00100010","00111100","00100000","00100000","00000000", --r
"00000000","00011010","00100100","00000100","00000100","00000100","00000000","00000000", --s
"00000000","00111100","00000010","00011100","00100000","00011110","00000000","00000000", --t
"00000010","00000010","00001110","00000010","00100010","00011100","00000000","00000000", --u
"00000000","00010010","00010010","00010010","00010010","00101100","00000000","00000000", --v
"00000000","00100010","00100010","00010100","00010100","00001000","00000000","00000000", --w
"00000000","00100010","00100010","00101010","00101010","00010100","00000000","00000000", --x
"00000000","00100010","00010100","00001000","00010100","00100010","00000000","00000000", --y
"00000000","00100010","00100010","00100010","00111100","00100000","00011100","00000000", --z
"00000000","00111110","00010000","00001000","00000100","00111110","00000000","00000000", --{
"00010000","00001000","00001000","00000100","00001000","00001000","00010000","00000000", --|
"00001000","00001000","00001000","00001000","00001000","00001000","00001000","00000000", --}
"00000100","00001000","00001000","00010000","00001000","00001000","00000100","00000000", --~
"00000000","00000000","00001100","10010010","01100000","00000000","00000000","00000000", --del
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --0d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --1d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --2d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --3d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --4d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --5d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --6d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --7d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --8d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --9d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --10d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --11d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --12d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --13d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --14d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --15d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --16d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --17d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --18d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --19d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --20d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --21d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --22d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --23d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --24d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --25d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --26d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --27d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --28d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --29d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --30d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --31d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --space
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --!
"00001000","00001000","00001000","00001000","00000000","00001000","00000000","00000000", --"
"00010100","00010100","00000000","00000000","00000000","00000000","00000000","00000000", --#
"00000000","00010100","00111110","00010100","00111110","00010100","00000000","00000000", --$
"00001000","00111100","00001010","00011100","00101000","00011110","00001000","00000000", --%
"10001110","01001010","00101110","00010000","11101000","10100100","11100010","00000000", ----'
"00001100","00010010","00010010","00001100","00110010","00010010","01101100","00000000", --(
"00001000","00001000","00000000","00000000","00000000","00000000","00000000","00000000", --)
"00001000","00000100","00000010","00000010","00000010","00000100","00001000","00000000", --*
"00001000","00010000","00100000","00100000","00100000","00010000","00001000","00000000", --+
"00001000","00111110","00010100","00100010","00000000","00000000","00000000","00000000", --,
"00010000","00010000","00010000","11111110","00010000","00010000","00010000","00000000", ---
"00000000","00000000","00000000","00000000","00000000","00001000","00001000","00000000", --.
"00000000","00000000","00000000","00111110","00000000","00000000","00000000","00000000", --/
"00000000","00000000","00000000","00000000","00000000","00001000","00000000","00000000", --0
"01000000","00100000","00010000","00001000","00000100","00000010","00000000","00000000", --1
"00011100","00110010","00101010","00101010","00100110","00011100","00000000","00000000", --2
"00001000","00001100","00001000","00001000","00001000","00111110","00000000","00000000", --3
"00011100","00100010","00010000","00001000","00000100","00111110","00000000","00000000", --4
"00011100","00100010","00010000","00100000","00100010","00011100","00000000","00000000", --5
"00011000","00010100","00010010","00111110","00010000","00111100","00000000","00000000", --6
"00111110","00000010","00111110","00100000","00100010","00011100","00000000","00000000", --7
"00011100","00100010","00000010","00011110","00100010","00011100","00000000","00000000", --8
"00111110","00100010","00100000","00010000","00001000","00001000","00000000","00000000", --9
"00011100","00100010","00011100","00100010","00100010","00011100","00000000","00000000", --:
"00011100","00100010","00111100","00100000","00100010","00011100","00000000","00000000", --;
"00000000","00001000","00000000","00000000","00000000","00001000","00000000","00000000", --<
"00000000","00001000","00000000","00000000","00000000","00001000","00001000","00000000", --=
"00010000","00001000","00000100","00000010","00000100","00001000","00010000","00000000", -->
"00000000","00000000","00111110","00000000","00000000","00111110","00000000","00000000", --?
"00000010","00000100","00001000","00010000","00001000","00000100","00000010","00000000", --@
"00011100","00100010","00011000","00001000","00000000","00001000","00000000","00000000", --A
"01111100","10000010","10111010","10101010","10111010","10100010","01101100","00000000", --B
"00011100","00100010","00111110","00100010","00100010","00100010","00000000","00000000", --C
"00011110","00100010","00011110","00100010","00100010","00011110","00000000","00000000", --D
"00011100","00100010","00000010","00000010","00100010","00011100","00000000","00000000", --E
"00011110","00100010","00100010","00100010","00100010","00011110","00000000","00000000", --F
"00111110","00000010","00011110","00000010","00000010","00111110","00000000","00000000", --G
"00111110","00000010","00011110","00000010","00000010","00000010","00000000","00000000", --H
"00011100","00100010","00000010","00111010","00100010","00011100","00000000","00000000", --I
"00100010","00100010","00111110","00100010","00100010","00100010","00000000","00000000", --J
"00111110","00001000","00001000","00001000","00001000","00111110","00000000","00000000", --K
"00111000","00010000","00010000","00010000","00010010","00001100","00000000","00000000", --L
"00010010","00001010","00000110","00001010","00010010","00100010","00000000","00000000", --M
"00000010","00000010","00000010","00000010","00000010","00111110","00000000","00000000", --N
"00100010","00110110","00101010","00101010","00100010","00100010","00000000","00000000", --O
"00100010","00100010","00100110","00101010","00110010","00100010","00000000","00000000", --P
"00011100","00100010","00100010","00100010","00100010","00011100","00000000","00000000", --Q
"00011110","00100010","00100010","00011110","00000010","00000010","00000000","00000000", --R
"00011100","00100010","00100010","00100010","00100010","00011100","01101000","00000000", --S
"00011110","00100010","00011110","00001010","00010010","00100010","00000000","00000000", --T
"00111100","00000010","00011100","00100000","00100000","00011110","00000000","00000000", --U
"00111110","00001000","00001000","00001000","00001000","00001000","00000000","00000000", --V
"00100010","00100010","00100010","00100010","00100010","00011100","00000000","00000000", --W
"00100010","00100010","00100010","00010100","00010100","00001000","00000000","00000000", --X
"00100010","00100010","00100010","00101010","00101010","00010100","00000000","00000000", --Y
"00100010","00010100","00001000","00001000","00010100","00100010","00000000","00000000", --Z
"00100010","00100010","00011100","00001000","00001000","00001000","00000000","00000000", --[
"00111110","00010000","00001000","00000100","00000010","00111110","00000000","00000000", --\
"00011000","00001000","00001000","00001000","00001000","00001000","00011000","00000000", --]
"00000010","00000100","00001000","00010000","00100000","01000000","00000000","00000000", --^
"00011000","00010000","00010000","00010000","00010000","00010000","00011000","00000000", --_
"00001000","00010100","00100010","00000000","00000000","00000000","00000000","00000000", --`
"00000000","00000000","00000000","00000000","00000000","00000000","11111111","00000000", --a
"00001000","00010000","00000000","00000000","00000000","00000000","00000000","00000000", --b
"00000000","00011100","00100000","00111100","00100010","01011100","00000000","00000000", --c
"00000010","00000010","00011010","00100110","00100010","00011110","00000000","00000000", --d
"00000000","00011100","00000010","00000010","00100010","00011100","00000000","00000000", --e
"00100000","00100000","00101100","00110010","00100010","00111100","00000000","00000000", --f
"00000000","00011100","00100010","00111110","00000010","00011100","00000000","00000000", --g
"00011100","00100010","00000010","00001110","00000010","00000010","00000000","00000000", --h
"00000000","00111100","00100010","00100010","00111100","00100000","00011100","00000000", --i
"00000010","00000010","00011010","00100110","00100010","00100010","00000000","00000000", --j
"00001000","00000000","00001100","00001000","00001000","00011100","00000000","00000000", --k
"00010000","00000000","00011000","00010000","00010000","00010010","00001100","00000000", --l
"00000010","00010010","00001010","00001110","00010010","00100010","00000000","00000000", --m
"00001100","00001000","00001000","00001000","00001000","00111110","00000000","00000000", --n
"00000000","00010110","00101010","00101010","00101010","00101010","00000000","00000000", --o
"00000000","00011010","00100100","00100100","00100100","00100100","00000000","00000000", --p
"00000000","00011100","00100010","00100010","00100010","00011100","00000000","00000000", --q
"00000000","00011110","00100010","00100010","00011110","00000010","00000010","00000000", --r
"00000000","00101100","00110010","00100010","00111100","00100000","00100000","00000000", --s
"00000000","00011010","00100100","00000100","00000100","00000100","00000000","00000000", --t
"00000000","00111100","00000010","00011100","00100000","00011110","00000000","00000000", --u
"00000010","00000010","00001110","00000010","00100010","00011100","00000000","00000000", --v
"00000000","00010010","00010010","00010010","00010010","00101100","00000000","00000000", --w
"00000000","00100010","00100010","00010100","00010100","00001000","00000000","00000000", --x
"00000000","00100010","00100010","00101010","00101010","00010100","00000000","00000000", --y
"00000000","00100010","00010100","00001000","00010100","00100010","00000000","00000000", --z
"00000000","00100010","00100010","00100010","00111100","00100000","00011100","00000000", --{
"00000000","00111110","00010000","00001000","00000100","00111110","00000000","00000000", --|
"00010000","00001000","00001000","00000100","00001000","00001000","00010000","00000000", --}
"00001000","00001000","00001000","00001000","00001000","00001000","00001000","00000000", --~
"00000100","00001000","00001000","00010000","00001000","00001000","00000100","00000000", --del
"00000000","00000000","00001100","10010010","01100000","00000000","00000000","00000000",
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000");
end PIXPACKAGE;
|
mit
|
dawsonjon/Chips-Demo
|
synthesis/nexys_4/image_processor/svga_package.vhd
|
15
|
25646
|
-- ****************************************************************************
-- Filename :svga_package.vhd
-- Project :Wishbone VGA Core
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2005-12-18
-- ****************************************************************************
-- Description :A package defining the carachter glyphs.
-- ****************************************************************************
-- Dependencies :Standard Libraries
-- ****************************************************************************
-- Revision History :
--
-- Date :2005-12-18
-- Author :Jonathan P Dawson
-- Modification: Created File
--
-- ****************************************************************************
-- Copyright (C) Jonathan P Dawson 2005
-- ****************************************************************************
library IEEE;
use Ieee.std_logic_1164.all;
package PIXPACKAGE is
type PIX_ARRAY_TYPE is array (0 to 2047) of Std_logic_vector(7 downto 0);
constant PIXARRAY : PIX_ARRAY_TYPE := (
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --0d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --1d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --2d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --3d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --4d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --5d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --6d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --7d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --8d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --9d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --10d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --11d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --12d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --13d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --14d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --15d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --16d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --17d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --18d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --19d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --20d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --21d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --22d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --23d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --24d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --25d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --26d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --27d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --28d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --29d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --30d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --31d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --space
"00001000","00001000","00001000","00001000","00000000","00001000","00000000","00000000", --!
"00010100","00010100","00000000","00000000","00000000","00000000","00000000","00000000", --"
"00000000","00010100","00111110","00010100","00111110","00010100","00000000","00000000", --#
"00001000","00111100","00001010","00011100","00101000","00011110","00001000","00000000", --$
"10001110","01001010","00101110","00010000","11101000","10100100","11100010","00000000", --%
"00001100","00010010","00010010","00001100","00110010","00010010","01101100","00000000", ----'
"00001000","00001000","00000000","00000000","00000000","00000000","00000000","00000000", --(
"00001000","00000100","00000010","00000010","00000010","00000100","00001000","00000000", --)
"00001000","00010000","00100000","00100000","00100000","00010000","00001000","00000000", --*
"00001000","00111110","00010100","00100010","00000000","00000000","00000000","00000000", --+
"00010000","00010000","00010000","11111110","00010000","00010000","00010000","00000000", --,
"00000000","00000000","00000000","00000000","00000000","00001000","00001000","00000000", ---
"00000000","00000000","00000000","00111110","00000000","00000000","00000000","00000000", --.
"00000000","00000000","00000000","00000000","00000000","00001000","00000000","00000000", --/
"01000000","00100000","00010000","00001000","00000100","00000010","00000000","00000000", --0
"00011100","00110010","00101010","00101010","00100110","00011100","00000000","00000000", --1
"00001000","00001100","00001000","00001000","00001000","00111110","00000000","00000000", --2
"00011100","00100010","00010000","00001000","00000100","00111110","00000000","00000000", --3
"00011100","00100010","00010000","00100000","00100010","00011100","00000000","00000000", --4
"00011000","00010100","00010010","00111110","00010000","00111100","00000000","00000000", --5
"00111110","00000010","00111110","00100000","00100010","00011100","00000000","00000000", --6
"00011100","00100010","00000010","00011110","00100010","00011100","00000000","00000000", --7
"00111110","00100010","00100000","00010000","00001000","00001000","00000000","00000000", --8
"00011100","00100010","00011100","00100010","00100010","00011100","00000000","00000000", --9
"00011100","00100010","00111100","00100000","00100010","00011100","00000000","00000000", --:
"00000000","00001000","00000000","00000000","00000000","00001000","00000000","00000000", --;
"00000000","00001000","00000000","00000000","00000000","00001000","00001000","00000000", --<
"00010000","00001000","00000100","00000010","00000100","00001000","00010000","00000000", --=
"00000000","00000000","00111110","00000000","00000000","00111110","00000000","00000000", -->
"00000010","00000100","00001000","00010000","00001000","00000100","00000010","00000000", --?
"00011100","00100010","00011000","00001000","00000000","00001000","00000000","00000000", --@
"01111100","10000010","10111010","10101010","10111010","10100010","01101100","00000000", --A
"00011100","00100010","00111110","00100010","00100010","00100010","00000000","00000000", --B
"00011110","00100010","00011110","00100010","00100010","00011110","00000000","00000000", --C
"00011100","00100010","00000010","00000010","00100010","00011100","00000000","00000000", --D
"00011110","00100010","00100010","00100010","00100010","00011110","00000000","00000000", --E
"00111110","00000010","00011110","00000010","00000010","00111110","00000000","00000000", --F
"00111110","00000010","00011110","00000010","00000010","00000010","00000000","00000000", --G
"00011100","00100010","00000010","00111010","00100010","00011100","00000000","00000000", --H
"00100010","00100010","00111110","00100010","00100010","00100010","00000000","00000000", --I
"00111110","00001000","00001000","00001000","00001000","00111110","00000000","00000000", --J
"00111000","00010000","00010000","00010000","00010010","00001100","00000000","00000000", --K
"00010010","00001010","00000110","00001010","00010010","00100010","00000000","00000000", --L
"00000010","00000010","00000010","00000010","00000010","00111110","00000000","00000000", --M
"00100010","00110110","00101010","00101010","00100010","00100010","00000000","00000000", --N
"00100010","00100010","00100110","00101010","00110010","00100010","00000000","00000000", --O
"00011100","00100010","00100010","00100010","00100010","00011100","00000000","00000000", --P
"00011110","00100010","00100010","00011110","00000010","00000010","00000000","00000000", --Q
"00011100","00100010","00100010","00100010","00100010","00011100","01101000","00000000", --R
"00011110","00100010","00011110","00001010","00010010","00100010","00000000","00000000", --S
"00111100","00000010","00011100","00100000","00100000","00011110","00000000","00000000", --T
"00111110","00001000","00001000","00001000","00001000","00001000","00000000","00000000", --U
"00100010","00100010","00100010","00100010","00100010","00011100","00000000","00000000", --V
"00100010","00100010","00100010","00010100","00010100","00001000","00000000","00000000", --W
"00100010","00100010","00100010","00101010","00101010","00010100","00000000","00000000", --X
"00100010","00010100","00001000","00001000","00010100","00100010","00000000","00000000", --Y
"00100010","00100010","00011100","00001000","00001000","00001000","00000000","00000000", --Z
"00111110","00010000","00001000","00000100","00000010","00111110","00000000","00000000", --[
"00011000","00001000","00001000","00001000","00001000","00001000","00011000","00000000", --\
"00000010","00000100","00001000","00010000","00100000","01000000","00000000","00000000", --]
"00011000","00010000","00010000","00010000","00010000","00010000","00011000","00000000", --^
"00001000","00010100","00100010","00000000","00000000","00000000","00000000","00000000", --_
"00000000","00000000","00000000","00000000","00000000","00000000","11111111","00000000", --`
"00001000","00010000","00000000","00000000","00000000","00000000","00000000","00000000", --a
"00000000","00011100","00100000","00111100","00100010","01011100","00000000","00000000", --b
"00000010","00000010","00011010","00100110","00100010","00011110","00000000","00000000", --c
"00000000","00011100","00000010","00000010","00100010","00011100","00000000","00000000", --d
"00100000","00100000","00101100","00110010","00100010","00111100","00000000","00000000", --e
"00000000","00011100","00100010","00111110","00000010","00011100","00000000","00000000", --f
"00011100","00100010","00000010","00001110","00000010","00000010","00000000","00000000", --g
"00000000","00111100","00100010","00100010","00111100","00100000","00011100","00000000", --h
"00000010","00000010","00011010","00100110","00100010","00100010","00000000","00000000", --i
"00001000","00000000","00001100","00001000","00001000","00011100","00000000","00000000", --j
"00010000","00000000","00011000","00010000","00010000","00010010","00001100","00000000", --k
"00000010","00010010","00001010","00001110","00010010","00100010","00000000","00000000", --l
"00001100","00001000","00001000","00001000","00001000","00111110","00000000","00000000", --m
"00000000","00010110","00101010","00101010","00101010","00101010","00000000","00000000", --n
"00000000","00011010","00100100","00100100","00100100","00100100","00000000","00000000", --o
"00000000","00011100","00100010","00100010","00100010","00011100","00000000","00000000", --p
"00000000","00011110","00100010","00100010","00011110","00000010","00000010","00000000", --q
"00000000","00101100","00110010","00100010","00111100","00100000","00100000","00000000", --r
"00000000","00011010","00100100","00000100","00000100","00000100","00000000","00000000", --s
"00000000","00111100","00000010","00011100","00100000","00011110","00000000","00000000", --t
"00000010","00000010","00001110","00000010","00100010","00011100","00000000","00000000", --u
"00000000","00010010","00010010","00010010","00010010","00101100","00000000","00000000", --v
"00000000","00100010","00100010","00010100","00010100","00001000","00000000","00000000", --w
"00000000","00100010","00100010","00101010","00101010","00010100","00000000","00000000", --x
"00000000","00100010","00010100","00001000","00010100","00100010","00000000","00000000", --y
"00000000","00100010","00100010","00100010","00111100","00100000","00011100","00000000", --z
"00000000","00111110","00010000","00001000","00000100","00111110","00000000","00000000", --{
"00010000","00001000","00001000","00000100","00001000","00001000","00010000","00000000", --|
"00001000","00001000","00001000","00001000","00001000","00001000","00001000","00000000", --}
"00000100","00001000","00001000","00010000","00001000","00001000","00000100","00000000", --~
"00000000","00000000","00001100","10010010","01100000","00000000","00000000","00000000", --del
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --0d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --1d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --2d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --3d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --4d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --5d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --6d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --7d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --8d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --9d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --10d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --11d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --12d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --13d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --14d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --15d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --16d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --17d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --18d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --19d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --20d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --21d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --22d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --23d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --24d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --25d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --26d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --27d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --28d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --29d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --30d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --31d
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --space
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000", --!
"00001000","00001000","00001000","00001000","00000000","00001000","00000000","00000000", --"
"00010100","00010100","00000000","00000000","00000000","00000000","00000000","00000000", --#
"00000000","00010100","00111110","00010100","00111110","00010100","00000000","00000000", --$
"00001000","00111100","00001010","00011100","00101000","00011110","00001000","00000000", --%
"10001110","01001010","00101110","00010000","11101000","10100100","11100010","00000000", ----'
"00001100","00010010","00010010","00001100","00110010","00010010","01101100","00000000", --(
"00001000","00001000","00000000","00000000","00000000","00000000","00000000","00000000", --)
"00001000","00000100","00000010","00000010","00000010","00000100","00001000","00000000", --*
"00001000","00010000","00100000","00100000","00100000","00010000","00001000","00000000", --+
"00001000","00111110","00010100","00100010","00000000","00000000","00000000","00000000", --,
"00010000","00010000","00010000","11111110","00010000","00010000","00010000","00000000", ---
"00000000","00000000","00000000","00000000","00000000","00001000","00001000","00000000", --.
"00000000","00000000","00000000","00111110","00000000","00000000","00000000","00000000", --/
"00000000","00000000","00000000","00000000","00000000","00001000","00000000","00000000", --0
"01000000","00100000","00010000","00001000","00000100","00000010","00000000","00000000", --1
"00011100","00110010","00101010","00101010","00100110","00011100","00000000","00000000", --2
"00001000","00001100","00001000","00001000","00001000","00111110","00000000","00000000", --3
"00011100","00100010","00010000","00001000","00000100","00111110","00000000","00000000", --4
"00011100","00100010","00010000","00100000","00100010","00011100","00000000","00000000", --5
"00011000","00010100","00010010","00111110","00010000","00111100","00000000","00000000", --6
"00111110","00000010","00111110","00100000","00100010","00011100","00000000","00000000", --7
"00011100","00100010","00000010","00011110","00100010","00011100","00000000","00000000", --8
"00111110","00100010","00100000","00010000","00001000","00001000","00000000","00000000", --9
"00011100","00100010","00011100","00100010","00100010","00011100","00000000","00000000", --:
"00011100","00100010","00111100","00100000","00100010","00011100","00000000","00000000", --;
"00000000","00001000","00000000","00000000","00000000","00001000","00000000","00000000", --<
"00000000","00001000","00000000","00000000","00000000","00001000","00001000","00000000", --=
"00010000","00001000","00000100","00000010","00000100","00001000","00010000","00000000", -->
"00000000","00000000","00111110","00000000","00000000","00111110","00000000","00000000", --?
"00000010","00000100","00001000","00010000","00001000","00000100","00000010","00000000", --@
"00011100","00100010","00011000","00001000","00000000","00001000","00000000","00000000", --A
"01111100","10000010","10111010","10101010","10111010","10100010","01101100","00000000", --B
"00011100","00100010","00111110","00100010","00100010","00100010","00000000","00000000", --C
"00011110","00100010","00011110","00100010","00100010","00011110","00000000","00000000", --D
"00011100","00100010","00000010","00000010","00100010","00011100","00000000","00000000", --E
"00011110","00100010","00100010","00100010","00100010","00011110","00000000","00000000", --F
"00111110","00000010","00011110","00000010","00000010","00111110","00000000","00000000", --G
"00111110","00000010","00011110","00000010","00000010","00000010","00000000","00000000", --H
"00011100","00100010","00000010","00111010","00100010","00011100","00000000","00000000", --I
"00100010","00100010","00111110","00100010","00100010","00100010","00000000","00000000", --J
"00111110","00001000","00001000","00001000","00001000","00111110","00000000","00000000", --K
"00111000","00010000","00010000","00010000","00010010","00001100","00000000","00000000", --L
"00010010","00001010","00000110","00001010","00010010","00100010","00000000","00000000", --M
"00000010","00000010","00000010","00000010","00000010","00111110","00000000","00000000", --N
"00100010","00110110","00101010","00101010","00100010","00100010","00000000","00000000", --O
"00100010","00100010","00100110","00101010","00110010","00100010","00000000","00000000", --P
"00011100","00100010","00100010","00100010","00100010","00011100","00000000","00000000", --Q
"00011110","00100010","00100010","00011110","00000010","00000010","00000000","00000000", --R
"00011100","00100010","00100010","00100010","00100010","00011100","01101000","00000000", --S
"00011110","00100010","00011110","00001010","00010010","00100010","00000000","00000000", --T
"00111100","00000010","00011100","00100000","00100000","00011110","00000000","00000000", --U
"00111110","00001000","00001000","00001000","00001000","00001000","00000000","00000000", --V
"00100010","00100010","00100010","00100010","00100010","00011100","00000000","00000000", --W
"00100010","00100010","00100010","00010100","00010100","00001000","00000000","00000000", --X
"00100010","00100010","00100010","00101010","00101010","00010100","00000000","00000000", --Y
"00100010","00010100","00001000","00001000","00010100","00100010","00000000","00000000", --Z
"00100010","00100010","00011100","00001000","00001000","00001000","00000000","00000000", --[
"00111110","00010000","00001000","00000100","00000010","00111110","00000000","00000000", --\
"00011000","00001000","00001000","00001000","00001000","00001000","00011000","00000000", --]
"00000010","00000100","00001000","00010000","00100000","01000000","00000000","00000000", --^
"00011000","00010000","00010000","00010000","00010000","00010000","00011000","00000000", --_
"00001000","00010100","00100010","00000000","00000000","00000000","00000000","00000000", --`
"00000000","00000000","00000000","00000000","00000000","00000000","11111111","00000000", --a
"00001000","00010000","00000000","00000000","00000000","00000000","00000000","00000000", --b
"00000000","00011100","00100000","00111100","00100010","01011100","00000000","00000000", --c
"00000010","00000010","00011010","00100110","00100010","00011110","00000000","00000000", --d
"00000000","00011100","00000010","00000010","00100010","00011100","00000000","00000000", --e
"00100000","00100000","00101100","00110010","00100010","00111100","00000000","00000000", --f
"00000000","00011100","00100010","00111110","00000010","00011100","00000000","00000000", --g
"00011100","00100010","00000010","00001110","00000010","00000010","00000000","00000000", --h
"00000000","00111100","00100010","00100010","00111100","00100000","00011100","00000000", --i
"00000010","00000010","00011010","00100110","00100010","00100010","00000000","00000000", --j
"00001000","00000000","00001100","00001000","00001000","00011100","00000000","00000000", --k
"00010000","00000000","00011000","00010000","00010000","00010010","00001100","00000000", --l
"00000010","00010010","00001010","00001110","00010010","00100010","00000000","00000000", --m
"00001100","00001000","00001000","00001000","00001000","00111110","00000000","00000000", --n
"00000000","00010110","00101010","00101010","00101010","00101010","00000000","00000000", --o
"00000000","00011010","00100100","00100100","00100100","00100100","00000000","00000000", --p
"00000000","00011100","00100010","00100010","00100010","00011100","00000000","00000000", --q
"00000000","00011110","00100010","00100010","00011110","00000010","00000010","00000000", --r
"00000000","00101100","00110010","00100010","00111100","00100000","00100000","00000000", --s
"00000000","00011010","00100100","00000100","00000100","00000100","00000000","00000000", --t
"00000000","00111100","00000010","00011100","00100000","00011110","00000000","00000000", --u
"00000010","00000010","00001110","00000010","00100010","00011100","00000000","00000000", --v
"00000000","00010010","00010010","00010010","00010010","00101100","00000000","00000000", --w
"00000000","00100010","00100010","00010100","00010100","00001000","00000000","00000000", --x
"00000000","00100010","00100010","00101010","00101010","00010100","00000000","00000000", --y
"00000000","00100010","00010100","00001000","00010100","00100010","00000000","00000000", --z
"00000000","00100010","00100010","00100010","00111100","00100000","00011100","00000000", --{
"00000000","00111110","00010000","00001000","00000100","00111110","00000000","00000000", --|
"00010000","00001000","00001000","00000100","00001000","00001000","00010000","00000000", --}
"00001000","00001000","00001000","00001000","00001000","00001000","00001000","00000000", --~
"00000100","00001000","00001000","00010000","00001000","00001000","00000100","00000000", --del
"00000000","00000000","00001100","10010010","01100000","00000000","00000000","00000000",
"00000000","00000000","00000000","00000000","00000000","00000000","00000000","00000000");
end PIXPACKAGE;
|
mit
|
onkelthomas/HW_SW_LU_Gr3_2015
|
work/work/vhdl/textmode_controller/font_rom.vhd
|
2
|
1768
|
----------------------------------------------------------------------------------
-- Company: TU Wien - ECS Group --
-- Engineer: Thomas Polzer --
-- --
-- Create Date: 21.09.2010 --
-- Design Name: DIDELU --
-- Module Name: font_rom --
-- Project Name: DIDELU --
-- Description: Font ROM - Entity --
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- LIBRARIES --
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.font_pkg.all;
use work.math_pkg.all;
----------------------------------------------------------------------------------
-- ENTITY --
----------------------------------------------------------------------------------
entity font_rom is
port
(
vga_clk : in std_logic;
char : in std_logic_vector(log2c(CHAR_COUNT) - 1 downto 0);
char_height_pixel : in std_logic_vector(log2c(CHAR_HEIGHT) - 1 downto 0);
decoded_char : out std_logic_vector(0 to CHAR_WIDTH - 1)
);
end entity font_rom;
--- EOF ---
|
mit
|
onkelthomas/HW_SW_LU_Gr3_2015
|
template/template/vhdl/textmode_controller/font_rom.vhd
|
2
|
1768
|
----------------------------------------------------------------------------------
-- Company: TU Wien - ECS Group --
-- Engineer: Thomas Polzer --
-- --
-- Create Date: 21.09.2010 --
-- Design Name: DIDELU --
-- Module Name: font_rom --
-- Project Name: DIDELU --
-- Description: Font ROM - Entity --
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- LIBRARIES --
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.font_pkg.all;
use work.math_pkg.all;
----------------------------------------------------------------------------------
-- ENTITY --
----------------------------------------------------------------------------------
entity font_rom is
port
(
vga_clk : in std_logic;
char : in std_logic_vector(log2c(CHAR_COUNT) - 1 downto 0);
char_height_pixel : in std_logic_vector(log2c(CHAR_HEIGHT) - 1 downto 0);
decoded_char : out std_logic_vector(0 to CHAR_WIDTH - 1)
);
end entity font_rom;
--- EOF ---
|
mit
|
onkelthomas/HW_SW_LU_Gr3_2015
|
template/template/vhdl/textmode_controller/cursor_controller_pkg.vhd
|
2
|
1512
|
----------------------------------------------------------------------------------
-- LIBRARIES --
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.math_pkg.all;
----------------------------------------------------------------------------------
-- PACKAGE --
----------------------------------------------------------------------------------
package cursor_controller_pkg is
component cursor_controller is
generic
(
CLK_FREQ : integer;
BLINK_PERIOD : time range 1 ms to 2000 ms;
ROW_COUNT : integer;
COLUM_COUNT : integer;
COLOR_WIDTH : integer
);
port
(
clk : in std_logic;
res_n : in std_logic;
cursor_state : in std_logic_vector(1 downto 0);
cursor_color : in std_logic_vector(COLOR_WIDTH-1 downto 0);
position_row : in std_logic_vector(log2c(ROW_COUNT)-1 downto 0);
position_colum : in std_logic_vector(log2c(COLUM_COUNT)-1 downto 0);
vram_addr_row : in std_logic_vector(log2c(ROW_COUNT)-1 downto 0);
vram_addr_colum : in std_logic_vector(log2c(COLUM_COUNT)-1 downto 0);
vram_rd : in std_logic;
vram_data_color_in : in std_logic_vector(COLOR_WIDTH-1 downto 0);
vram_data_color_out : out std_logic_vector(COLOR_WIDTH-1 downto 0)
);
end component cursor_controller;
end package cursor_controller_pkg;
|
mit
|
kuasha/traviscitest
|
samplejsapp/app/bower_components/ace-builds/demo/kitchen-sink/docs/vhdl.vhd
|
472
|
830
|
library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
|
mit
|
dawsonjon/Chips-Demo
|
demo/bsp/atlys/serial_in.vhd
|
20
|
4970
|
--------------------------------------------------------------------------------
---
--- SERIAL INPUT
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: [email protected]
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A Serial Input Component
---
--------------------------------------------------------------------------------
---
---Serial Input
---============
---
---Read a stream of data from a serial UART
---
---Outputs
-----------
---
--- + OUT1 : Serial data stream
---
---Generics
-----------
---
--- + baud_rate
--- + clock frequency
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SERIAL_INPUT is
generic(
CLOCK_FREQUENCY : integer;
BAUD_RATE : integer
);
port(
CLK : in std_logic;
RST : in std_logic;
RX : in std_logic;
OUT1 : out std_logic_vector(7 downto 0);
OUT1_STB : out std_logic;
OUT1_ACK : in std_logic
);
end entity SERIAL_INPUT;
architecture RTL of SERIAL_INPUT is
type SERIAL_IN_STATE_TYPE is (IDLE, START, RX0, RX1, RX2, RX3, RX4, RX5, RX6, RX7, STOP, OUTPUT_DATA);
signal STATE : SERIAL_IN_STATE_TYPE;
signal STREAM : std_logic_vector(7 downto 0);
signal STREAM_STB : std_logic;
signal STREAM_ACK : std_logic;
signal COUNT : integer Range 0 to 3;
signal BIT_SPACING : integer Range 0 to 15;
signal INT_SERIAL : std_logic;
signal SERIAL_DEGLITCH : std_logic_Vector(1 downto 0);
constant CLOCK_DIVIDER : unsigned(11 downto 0) := To_unsigned(CLOCK_FREQUENCY/(BAUD_RATE * 16), 12);
signal BAUD_COUNT : unsigned(11 downto 0);
signal X16CLK_EN : std_logic;
begin
process
begin
wait until rising_edge(CLK);
if BAUD_COUNT = CLOCK_DIVIDER then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '1';
else
BAUD_COUNT <= BAUD_COUNT + 1;
X16CLK_EN <= '0';
end if;
if RST = '1' then
BAUD_COUNT <= (others => '0');
X16CLK_EN <= '0';
end if;
end process;
process
begin
wait until rising_edge(CLK);
SERIAL_DEGLITCH <= SERIAL_DEGLITCH(0) & RX;
if X16CLK_EN = '1' then
if SERIAL_DEGLITCH(1) = '0' then
if COUNT = 0 then
INT_SERIAL <= '0';
else
COUNT <= COUNT - 1;
end if;
else
if COUNT = 3 then
INT_SERIAL <= '1';
else
COUNT <= COUNT + 1;
end if;
end if;
end if;
if RST = '1' then
SERIAL_DEGLITCH <= "11";
end if;
end process;
process
begin
wait until rising_edge(CLK);
if X16CLK_EN = '1' then
if BIT_SPACING = 15 then
BIT_SPACING <= 0;
else
BIT_SPACING <= BIT_SPACING + 1;
end if;
end if;
case STATE is
when IDLE =>
BIT_SPACING <= 0;
if X16CLK_EN = '1' and INT_SERIAL = '0' then
STATE <= START;
end if;
when START =>
if X16CLK_EN = '1' and BIT_SPACING = 7 then
BIT_SPACING <= 0;
STATE <= RX0;
end if;
when RX0 =>
if X16CLK_EN = '1' and BIT_SPACING = 15 then
OUT1(0) <= INT_SERIAL;
BIT_SPACING <= 0;
STATE <= RX1;
end if;
when RX1 =>
if X16CLK_EN = '1' and BIT_SPACING = 15 then
OUT1(1) <= INT_SERIAL;
BIT_SPACING <= 0;
STATE <= RX2;
end if;
when RX2 =>
if X16CLK_EN = '1' and BIT_SPACING = 15 then
OUT1(2) <= INT_SERIAL;
BIT_SPACING <= 0;
STATE <= RX3;
end if;
when RX3 =>
if X16CLK_EN = '1' and BIT_SPACING = 15 then
OUT1(3) <= INT_SERIAL;
BIT_SPACING <= 0;
STATE <= RX4;
end if;
when RX4 =>
if X16CLK_EN = '1' and BIT_SPACING = 15 then
OUT1(4) <= INT_SERIAL;
BIT_SPACING <= 0;
STATE <= RX5;
end if;
when RX5 =>
if X16CLK_EN = '1' and BIT_SPACING = 15 then
OUT1(5) <= INT_SERIAL;
BIT_SPACING <= 0;
STATE <= RX6;
end if;
when RX6 =>
if X16CLK_EN = '1' and BIT_SPACING = 15 then
OUT1(6) <= INT_SERIAL;
BIT_SPACING <= 0;
STATE <= RX7;
end if;
when RX7 =>
if X16CLK_EN = '1' and BIT_SPACING = 15 then
OUT1(7) <= INT_SERIAL;
BIT_SPACING <= 0;
STATE <= STOP;
end if;
when STOP =>
if X16CLK_EN = '1' and BIT_SPACING = 15 then
BIT_SPACING <= 0;
STATE <= OUTPUT_DATA;
OUT1_STB <= '1';
end if;
when OUTPUT_DATA =>
if OUT1_ACK = '1' then
OUT1_STB <= '0';
STATE <= IDLE;
end if;
when others =>
STATE <= IDLE;
end case;
if RST = '1' then
STATE <= IDLE;
OUT1_STB <= '0';
end if;
end process;
end architecture RTL;
|
mit
|
dawsonjon/Chips-Demo
|
synthesis/nexys_4/audio_output/svga_timing_gen.vhd
|
15
|
5488
|
-- ****************************************************************************
-- Filename :svga_timing_gen.vhd
-- Project :Wishbone VGA Core
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2005-12-18
-- ****************************************************************************
-- Description :Generates video timings for a caracter maped video
-- display. Generates sync signals, the address of a
-- character within the screen and the address of a pixel
-- within a character.
-- ****************************************************************************
-- Dependencies :Standard Libraries
-- ****************************************************************************
-- Revision History :
--
-- Date :2005-12-18
-- Author :Jonathan P Dawson
-- Modification: Created File
--
-- ****************************************************************************
-- Copyright (C) Jonathan P Dawson 2005
-- ****************************************************************************
library IEEE;
use Ieee.std_logic_1164.all;
use Ieee.numeric_std.all;
entity VIDEO_TIME_GEN is
port (
CLK : in Std_logic;
RST : in Std_logic;
CHARADDR : out Std_logic_vector(12 downto 0);
PIXROW : out Std_logic_vector(2 downto 0);
PIXCOL : out Std_logic_vector(2 downto 0);
HSYNCH : out Std_logic;
VSYNCH : out Std_logic;
BLANK : out Std_logic);
end VIDEO_TIME_GEN;
architecture RTL of VIDEO_TIME_GEN is
signal PIX_ROW_ADDRESS : Unsigned(2 downto 0);
signal PIX_COL_ADDRESS : Unsigned(2 downto 0);
signal ROW_ADDRESS : Unsigned(12 downto 0);
signal COL_ADDRESS : Unsigned(6 downto 0);
signal VTIMER : Unsigned(9 downto 0);
signal HTIMER : Unsigned(10 downto 0);
signal VTIMER_EN : Std_logic;
signal VBLANK : Std_logic;
signal HBLANK : Std_logic;
signal INTVSYNCH : Std_logic;
signal INTHSYNCH : Std_logic;
constant HSYNCHTIME : Integer := 120;
constant HACTIVETIME : Integer := 800;
constant FPORCHTIME : Integer := 64;
constant BPORCHTIME : Integer := 56;
constant VSYNCHTIME : Integer := 6;
constant VACTIVETIME : Integer := 600;
constant VFPORCHTIME : Integer := 35;
constant VBPORCHTIME : Integer := 21;
begin
process
begin
wait until rising_edge(CLK);
if VBLANK = '0' and HBLANK = '0' then
if PIX_COL_ADDRESS = To_unsigned(7, 3) then
PIX_COL_ADDRESS <= (others => '0');
if COL_ADDRESS = To_unsigned(99, 7) then
COL_ADDRESS <= (others => '0');
if PIX_ROW_ADDRESS = To_unsigned(7, 3) then
PIX_ROW_ADDRESS <= (others => '0');
if ROW_ADDRESS = To_unsigned(7400, 13) then
ROW_ADDRESS <= (others => '0');
else
ROW_ADDRESS <= ROW_ADDRESS + 100;
end if;
else
PIX_ROW_ADDRESS <= PIX_ROW_ADDRESS + 1;
end if;
else
COL_ADDRESS <= COL_ADDRESS + 1;
end if;
else
PIX_COL_ADDRESS <= PIX_COL_ADDRESS +1;
end if;
end if;
if RST = '1' then
PIX_COL_ADDRESS <= (others => '0');
PIX_ROW_ADDRESS <= (others => '0');
COL_ADDRESS <= (others => '0');
ROW_ADDRESS <= (others => '0');
end if;
end process;
process
begin
wait until rising_edge(CLK);
if VTIMER_EN = '1' then
VTIMER <= VTIMER + 1;
if VTIMER = To_unsigned(VSYNCHTIME, 10) then
INTVSYNCH <= '1';
end if;
if VTIMER = To_unsigned(VSYNCHTIME
+ VFPORCHTIME, 10) then
VBLANK <= '0';
end if;
if VTIMER = To_unsigned(VSYNCHTIME
+ VFPORCHTIME
+ VACTIVETIME, 10) then
VBLANK <= '1';
end if;
if VTIMER = To_unsigned(VSYNCHTIME
+ VFPORCHTIME
+ VACTIVETIME
+ VBPORCHTIME, 10) then
INTVSYNCH <= '0';
VTIMER <= (others => '0');
end if;
end if;
if RST = '1' then
VTIMER <= (others => '0');
INTVSYNCH <= '0';
VBLANK <= '1';
end if;
end process;
process
begin
wait until Rising_edge(CLK);
HTIMER <= HTIMER + 1;
VTIMER_EN <= '0';
if HTIMER = To_unsigned(HSYNCHTIME, 11) then
INTHSYNCH <= '1';
end if;
if HTIMER = To_unsigned(HSYNCHTIME
+ FPORCHTIME, 11) then
HBLANK <= '0';
end if;
if HTIMER = To_unsigned(HSYNCHTIME
+ FPORCHTIME
+ HACTIVETIME, 11) then
HBLANK <= '1';
end if;
if HTIMER = To_unsigned(HSYNCHTIME
+ FPORCHTIME
+ HACTIVETIME
+ BPORCHTIME, 11) then
INTHSYNCH <= '0';
VTIMER_EN <= '1';
HTIMER <= (others => '0');
end if;
if RST = '1' then
HTIMER <= (others => '0');
INTHSYNCH <= '0';
HBLANK <= '1';
VTIMER_EN <= '1';
end if;
end process;
HSYNCH <= INTHSYNCH;
VSYNCH <= INTVSYNCH;
BLANK <= HBLANK or VBLANK;
CHARADDR <= Std_logic_vector(ROW_ADDRESS + COL_ADDRESS);
PIXCOL <= Std_logic_vector(PIX_COL_ADDRESS);
PIXROW <= Std_logic_vector(PIX_ROW_ADDRESS);
end RTL;
|
mit
|
dawsonjon/Chips-Demo
|
synthesis/nexys_4/hello_world/pwm_audio.vhd
|
15
|
1817
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwm_audio is
generic(
CLOCK_FREQUENCY : integer := 50000000;
SAMPLE_RATE : integer := 44000;
AUDIO_BITS : integer := 8
);
port(
CLK : in std_logic;
RST : in std_logic;
DATA_IN : in std_logic_vector(31 downto 0);
DATA_IN_STB : in std_logic;
DATA_IN_ACK : out std_logic;
AUDIO : out std_logic
);
end entity pwm_audio;
architecture RTL of pwm_audio is
constant MAX_COUNT : integer := (clock_frequency/sample_rate)-1;
type state_type is (GET_SAMPLE, PLAY_SAMPLE);
signal STATE : STATE_TYPE;
signal S_DATA_IN_ACK : std_logic;
signal COUNT : integer range 0 to MAX_COUNT;
signal SAMPLE : unsigned (audio_bits-1 downto 0);
signal SIGMA : unsigned (audio_bits downto 0);
signal DELTA : unsigned (audio_bits downto 0);
signal COMPARATOR : unsigned (audio_bits downto 0);
begin
process
begin
wait until rising_edge(CLK);
case STATE is
when GET_SAMPLE =>
S_DATA_IN_ACK <= '1';
if S_DATA_IN_ACK = '1' and DATA_IN_STB = '1' then
S_DATA_IN_ACK <= '0';
SAMPLE <= unsigned(DATA_IN(AUDIO_BITS-1 downto 0));
STATE <= PLAY_SAMPLE;
COUNT <= 0;
end if;
when PLAY_SAMPLE =>
if COUNT = MAX_COUNT then
STATE <= GET_SAMPLE;
else
COUNT <= COUNT + 1;
end if;
end case;
SIGMA <= SIGMA + DELTA;
if RST = '1' then
STATE <= GET_SAMPLE;
SIGMA <= (others => '0');
SAMPLE <= (others => '0');
S_DATA_IN_ACK <= '0';
end if;
end process;
DELTA <= SAMPLE - COMPARATOR;
COMPARATOR <= SIGMA(AUDIO_BITS) & to_unsigned(0, audio_bits);
AUDIO <= SIGMA(AUDIO_BITS);
DATA_IN_ACK <= S_DATA_IN_ACK;
end architecture RTL;
|
mit
|
dawsonjon/Chips-Demo
|
synthesis/nexys_4/hello_world/rmii_ethernet.vhd
|
15
|
25834
|
--------------------------------------------------------------------------------
---
--- Ethernet MAC
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: [email protected]
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A ethernet MAC
---
--------------------------------------------------------------------------------
---
---Gigabit Ethernet
---================
---
---Send and receive Ethernet packets. Using a Ethernet Physical Interface.
---
---Features:
---
---+ Supports 100/10 ethernet only via a mii interface.
---+ Supports full duplex mode only.
---
---Interface
------------
---:input: TX - Data to send (16 bits).
---:output: RX - Data to send (16 bits).
---
---Ethernet Packet Structure
----------------------------
---
---+-------------+-------------+--------+--------+---------+---------+-----+
---| Description | destination | source | length | payload | padding | FSC |
---+=============+=============+========+========+=========+=========+=====+
---| Bytes | 6 | 6 | 2 | 0-1500 | 0-46 | 4 |
---+-------------+-------------+--------+--------+---------+---------+-----+
---
---Notes:
---
---+ The *length* field is the length of the ethernet payload.
---+ The *Ethernet Output* block will automatically append the FSC to
--- outgoing packets.
---+ The *FSC* of incoming packets will be checked, and bad packets will
--- be discarded. The *FSC* will be stripped from incoming packets.
---+ The length of the *payload* + *padding* must be 46-1500 bytes.
---+ Incoming packets of incorrect *length* will be discarded.
---
---Usage
--------
---
---Transmit
---~~~~~~~~
---The first 16 bit word on the TX input is interpreted as the length of the
---packet in bytes (including the MAC address, length and payload, but not the
---preamble or FSC). Subsequent words on the TX input are interpreted as the
---content of the packet. If length is an odd number of bytes, then the least
---significant byte of the last word will be ignored.
---The FSC will be appended for you, but you need to supply the destination,
---source and length fields.
---
---Receive
---~~~~~~~~
---The first 16 bit word on the RX output will be the length of the packet in
---bytes (including the MAC address, length and payload, but not the
---preamble or FSC). Subsequent words on the RX output will be the
---content of the packet. If length is an odd number of bytes, then the least
---significant byte of the last word will not contain usefull data.
---The FSC will be stripped from incoming packets, but the destination,
---source and length fields will be included.
---
---Hardware details
-------------------
---This component uses three clocks, the local clock used to transfer data
---between components, the TX, and RX clocks which come from the PHY
---
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity rmii_ethernet is
port(
CLK : in std_logic;
RST : in std_logic;
ETH_CLK : in std_logic;
--GMII IF
TXER : out std_logic;
TXEN : out std_logic;
TXD : out std_logic_vector(1 downto 0);
PHY_RESET : out std_logic;
RXER : in std_logic;
RXDV : in std_logic;
RXD : in std_logic_vector(1 downto 0);
--RX STREAM
TX : in std_logic_vector(15 downto 0);
TX_STB : in std_logic;
TX_ACK : out std_logic;
--RX STREAM
RX : out std_logic_vector(15 downto 0);
RX_STB : out std_logic;
RX_ACK : in std_logic
);
end entity rmii_ethernet;
architecture RTL of rmii_ethernet is
-- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
-- data width: 8
-- convention: the first serial bit is D[0]
function NEXTCRC32_D8
(DATA: std_logic_vector(7 downto 0);
CRC: std_logic_vector(31 downto 0))
return std_logic_vector is
variable D: std_logic_vector(7 downto 0);
variable C: std_logic_vector(31 downto 0);
variable NEWCRC: std_logic_vector(31 downto 0);
begin
D := DATA;
C := CRC;
NewCRC(0):=C(24) xor C(30) xor D(1) xor D(7);
NewCRC(1):=C(25) xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1)
xor D(7);
NewCRC(2):=C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6) xor C(24)
xor C(30) xor D(1) xor D(7);
NewCRC(3):=C(27) xor D(4) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0)
xor D(6);
NewCRC(4):=C(28) xor D(3) xor C(27) xor D(4) xor C(26) xor D(5) xor C(24)
xor C(30) xor D(1) xor D(7);
NewCRC(5):=C(29) xor D(2) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25)
xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(6):=C(30) xor D(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26)
xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(7):=C(31) xor D(0) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26)
xor D(5) xor C(24) xor D(7);
NewCRC(8):=C(0) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6)
xor C(24) xor D(7);
NewCRC(9):=C(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5)
xor C(25) xor D(6);
NewCRC(10):=C(2) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26) xor D(5)
xor C(24) xor D(7);
NewCRC(11):=C(3) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6)
xor C(24) xor D(7);
NewCRC(12):=C(4) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5)
xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(13):=C(5) xor C(30) xor D(1) xor C(29) xor D(2) xor C(27) xor D(4)
xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(14):=C(6) xor C(31) xor D(0) xor C(30) xor D(1) xor C(28) xor D(3)
xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(15):=C(7) xor C(31) xor D(0) xor C(29) xor D(2) xor C(28) xor D(3)
xor C(27) xor D(4);
NewCRC(16):=C(8) xor C(29) xor D(2) xor C(28) xor D(3) xor C(24) xor D(7);
NewCRC(17):=C(9) xor C(30) xor D(1) xor C(29) xor D(2) xor C(25) xor D(6);
NewCRC(18):=C(10) xor C(31) xor D(0) xor C(30) xor D(1) xor C(26) xor D(5);
NewCRC(19):=C(11) xor C(31) xor D(0) xor C(27) xor D(4);
NewCRC(20):=C(12) xor C(28) xor D(3);
NewCRC(21):=C(13) xor C(29) xor D(2);
NewCRC(22):=C(14) xor C(24) xor D(7);
NewCRC(23):=C(15) xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(24):=C(16) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(25):=C(17) xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(26):=C(18) xor C(28) xor D(3) xor C(27) xor D(4) xor C(24) xor C(30)
xor D(1) xor D(7);
NewCRC(27):=C(19) xor C(29) xor D(2) xor C(28) xor D(3) xor C(25) xor C(31)
xor D(0) xor D(6);
NewCRC(28):=C(20) xor C(30) xor D(1) xor C(29) xor D(2) xor C(26) xor D(5);
NewCRC(29):=C(21) xor C(31) xor D(0) xor C(30) xor D(1) xor C(27) xor D(4);
NewCRC(30):=C(22) xor C(31) xor D(0) xor C(28) xor D(3);
NewCRC(31):=C(23) xor C(29) xor D(2);
return NEWCRC;
end NEXTCRC32_D8;
-- Reverse the input vector.
function REVERSED(slv: std_logic_vector) return std_logic_vector is
variable result: std_logic_vector(slv'reverse_range);
begin
for i in slv'range loop
result(i) := slv(i);
end loop;
return result;
end REVERSED;
--constants
constant ADDRESS_BITS : integer := 11;
constant ADDRESS_MAX : integer := (2**ADDRESS_BITS) - 1;
--memories
type TX_MEMORY_TYPE is array (0 to 1024) of
std_logic_vector(15 downto 0);
shared variable TX_MEMORY : TX_MEMORY_TYPE;
type RX_MEMORY_TYPE is array (0 to ADDRESS_MAX) of
std_logic_vector(15 downto 0);
shared variable RX_MEMORY : RX_MEMORY_TYPE;
type ADDRESS_ARRAY is array (0 to 31) of
unsigned(ADDRESS_BITS - 1 downto 0);
--state variables
type TX_PHY_STATE_TYPE is (WAIT_NEW_PACKET, PREAMBLE,
SFD_0, SFD_1, SFD_2, SFD_3, SEND_DATA_0, SEND_DATA_1, SEND_DATA_2, SEND_DATA_3,
SEND_DATA_4, SEND_DATA_5, SEND_DATA_6, SEND_DATA_7, SEND_CRC_15,
SEND_CRC_14, SEND_CRC_13, SEND_CRC_12, SEND_CRC_11, SEND_CRC_10,
SEND_CRC_9, SEND_CRC_8, SEND_CRC_7, SEND_CRC_6,
SEND_CRC_5, SEND_CRC_4, SEND_CRC_3,
SEND_CRC_2, SEND_CRC_1, SEND_CRC_0, DONE_STATE);
signal TX_PHY_STATE : TX_PHY_STATE_TYPE;
type TX_PACKET_STATE_TYPE is(GET_LENGTH, GET_DATA, SEND_PACKET,
WAIT_NOT_DONE);
signal TX_PACKET_STATE : TX_PACKET_STATE_TYPE;
type RX_PHY_STATE_TYPE is (WAIT_START, PREAMBLE,
DATA_0, DATA_1, DATA_2, DATA_3, DATA_4,
DATA_5, DATA_6, DATA_7, END_OF_FRAME, NOTIFY_NEW_PACKET);
signal RX_PHY_STATE : RX_PHY_STATE_TYPE;
type RX_PACKET_STATE_TYPE is (WAIT_INITIALISE, WAIT_NEW_PACKET, SEND_DATA,
PREFETCH0, PREFETCH1, SEND_LENGTH);
signal RX_PACKET_STATE : RX_PACKET_STATE_TYPE;
--TX signals
signal TX_WRITE : std_logic;
signal TX_WRITE_DATA : std_logic_vector(15 downto 0);
signal TX_READ_DATA : std_logic_vector(15 downto 0);
signal TX_WRITE_ADDRESS : integer range 0 to 1024;
signal TX_WRITE_ADDRESS_DEL : integer range 0 to 1024;
signal TX_READ_ADDRESS : integer range 0 to 1024;
signal TX_CRC : std_logic_vector(31 downto 0);
signal TX_IN_COUNT : integer range 0 to 1024;
signal TX_OUT_COUNT : integer range 0 to 1024;
signal TX_PACKET_LENGTH : std_logic_vector(15 downto 0);
signal GO, GO_DEL, GO_SYNC : std_logic;
signal DONE, DONE_DEL, DONE_SYNC : std_logic;
signal S_TX_ACK : std_logic;
signal PREAMBLE_COUNT : integer range 0 to 27;
--RX signals
signal RX_WRITE_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_READ_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_START_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_PACKET_LENGTH : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_START_ADDRESS_BUFFER : ADDRESS_ARRAY;
signal RX_PACKET_LENGTH_BUFFER : ADDRESS_ARRAY;
signal RX_WRITE_BUFFER : integer range 0 to 31;
signal RX_READ_BUFFER : integer range 0 to 31;
signal RX_BUFFER_BUSY : std_logic_vector(31 downto 0);
signal RX_BUFFER_BUSY_DEL : std_logic_vector(31 downto 0);
signal RX_BUFFER_BUSY_SYNC : std_logic_vector(31 downto 0);
signal RX_START_ADDRESS_SYNC : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_PACKET_LENGTH_SYNC : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_END_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_WRITE_DATA : std_logic_vector(15 downto 0);
signal RX_WRITE_ENABLE : std_logic;
signal RX_ERROR : std_logic;
signal RX_CRC : std_logic_vector(31 downto 0);
signal RXD_D : std_logic_vector(1 downto 0);
signal LOW_NIBBLE : std_logic_vector(5 downto 0);
signal RXDV_D : std_logic;
signal RXER_D : std_logic;
begin
--This process is in the local clock domain.
--It gets data and puts it into a RAM.
--Once a packets worth of data has been stored it is
--sent to the packet sending state machine.
TX_PACKET_FSM : process
begin
wait until rising_edge(CLK);
TX_WRITE <= '0';
case TX_PACKET_STATE is
when GET_LENGTH =>
S_TX_ACK <= '1';
if S_TX_ACK = '1' and TX_STB = '1' then
S_TX_ACK <= '0';
TX_PACKET_LENGTH <= TX;
TX_IN_COUNT <= 2;
TX_PACKET_STATE <= GET_DATA;
end if;
when GET_DATA =>
S_TX_ACK <= '1';
if S_TX_ACK = '1' and TX_STB = '1' then
TX_WRITE_DATA <= TX;
TX_WRITE <= '1';
if TX_IN_COUNT >= unsigned(TX_PACKET_LENGTH) then
TX_PACKET_STATE <= SEND_PACKET;
S_TX_ACK <= '0';
else
TX_WRITE_ADDRESS <= TX_WRITE_ADDRESS + 1;
TX_IN_COUNT <= TX_IN_COUNT + 2;
end if;
end if;
when SEND_PACKET =>
GO <= '1';
TX_WRITE_ADDRESS <= 0;
if DONE_SYNC = '1' then
GO <= '0';
TX_PACKET_STATE <= WAIT_NOT_DONE;
end if;
when WAIT_NOT_DONE =>
if DONE_SYNC = '0' then
TX_PACKET_STATE <= GET_LENGTH;
end if;
end case;
if RST = '1' then
TX_PACKET_STATE <= GET_LENGTH;
TX_WRITE_ADDRESS <= 0;
S_TX_ACK <= '0';
GO <= '0';
end if;
end process TX_PACKET_FSM;
TX_ACK <= S_TX_ACK;
--This process writes data into a dual port RAM
WRITE_DUAL_PORT_MEMORY : process
begin
wait until rising_edge(CLK);
TX_WRITE_ADDRESS_DEL <= TX_WRITE_ADDRESS;
if TX_WRITE = '1' then
TX_MEMORY(TX_WRITE_ADDRESS_DEL) := TX_WRITE_DATA;
end if;
end process;
--This process read data from a dual port RAM
READ_DUAL_PORT_MEMORY : process
begin
wait until rising_edge(ETH_CLK);
TX_READ_DATA <= TX_MEMORY(TX_READ_ADDRESS);
end process;
--This process synchronises ethernet signals
--to the TX clock domain
LOCAL_TO_TXCLK : process
begin
wait until rising_edge(ETH_CLK);
GO_DEL <= GO; GO_SYNC <= GO_DEL;
end process;
--This process synchronises local signals to the ethernet clock domain
TXCLK_TO_LOCAL : process
begin
wait until rising_edge(CLK);
DONE_DEL <= DONE; DONE_SYNC <= DONE_DEL;
end process;
--Transmit the stored packet via the phy.
TX_PHY_FSM : process
variable CRC : std_logic_vector(7 downto 0);
begin
wait until rising_edge(ETH_CLK);
case TX_PHY_STATE is
when WAIT_NEW_PACKET =>
if GO_SYNC = '1' then
TX_PHY_STATE <= PREAMBLE;
TX_READ_ADDRESS <= 0;
TX_OUT_COUNT <= to_integer(unsigned(TX_PACKET_LENGTH)-1);
PREAMBLE_COUNT <= 27;
end if;
when PREAMBLE =>
TXD <= "01";
TXEN <= '1';
if PREAMBLE_COUNT = 0 then
TX_PHY_STATE <= SFD_0;
else
PREAMBLE_COUNT <= PREAMBLE_COUNT - 1;
end if;
when SFD_0 =>
TXD <= "01";
TX_PHY_STATE <= SFD_1;
when SFD_1 =>
TXD <= "01";
TX_PHY_STATE <= SFD_2;
when SFD_2 =>
TXD <= "01";
TX_PHY_STATE <= SFD_3;
when SFD_3 =>
TXD <= "11";
TX_PHY_STATE <= SEND_DATA_0;
TX_CRC <= X"FFFFFFFF";
when SEND_DATA_0 =>
TXD <= TX_READ_DATA(9 downto 8);
TX_PHY_STATE <= SEND_DATA_1;
when SEND_DATA_1 =>
TXD <= TX_READ_DATA(11 downto 10);
TX_PHY_STATE <= SEND_DATA_2;
when SEND_DATA_2 =>
TXD <= TX_READ_DATA(13 downto 12);
TX_PHY_STATE <= SEND_DATA_3;
when SEND_DATA_3 =>
TX_CRC <= NEXTCRC32_D8(TX_READ_DATA(15 downto 8), TX_CRC);
TXD <= TX_READ_DATA(15 downto 14);
If TX_OUT_COUNT = 0 then
TX_PHY_STATE <= SEND_CRC_15;
else
TX_PHY_STATE <= SEND_DATA_4;
TX_OUT_COUNT <= TX_OUT_COUNT - 1;
end if;
when SEND_DATA_4 =>
TXD <= TX_READ_DATA(1 downto 0);
TX_PHY_STATE <= SEND_DATA_5;
when SEND_DATA_5 =>
TXD <= TX_READ_DATA(3 downto 2);
TX_PHY_STATE <= SEND_DATA_6;
when SEND_DATA_6 =>
TXD <= TX_READ_DATA(5 downto 4);
TX_PHY_STATE <= SEND_DATA_7;
TX_READ_ADDRESS <= TX_READ_ADDRESS + 1;
when SEND_DATA_7 =>
TX_CRC <= NEXTCRC32_D8(TX_READ_DATA(7 downto 0), TX_CRC);
TXD <= TX_READ_DATA(7 downto 6);
If TX_OUT_COUNT = 0 then
TX_PHY_STATE <= SEND_CRC_15;
else
TX_PHY_STATE <= SEND_DATA_0;
TX_OUT_COUNT <= TX_OUT_COUNT - 1;
end if;
when SEND_CRC_15 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_14;
when SEND_CRC_14 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_13;
when SEND_CRC_13 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_12;
when SEND_CRC_12 =>
CRC := not REVERSED(TX_CRC(31 downto 24));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_11;
when SEND_CRC_11 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_10;
when SEND_CRC_10 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_9;
when SEND_CRC_9 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_8;
when SEND_CRC_8 =>
CRC := not REVERSED(TX_CRC(23 downto 16));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_7;
when SEND_CRC_7 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_6;
when SEND_CRC_6 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_5;
when SEND_CRC_5 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_4;
when SEND_CRC_4 =>
CRC := not REVERSED(TX_CRC(15 downto 8));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= SEND_CRC_3;
when SEND_CRC_3 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(1 downto 0);
TX_PHY_STATE <= SEND_CRC_2;
when SEND_CRC_2 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(3 downto 2);
TX_PHY_STATE <= SEND_CRC_1;
when SEND_CRC_1 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(5 downto 4);
TX_PHY_STATE <= SEND_CRC_0;
when SEND_CRC_0 =>
CRC := not REVERSED(TX_CRC(7 downto 0));
TXD <= CRC(7 downto 6);
TX_PHY_STATE <= DONE_STATE;
when DONE_STATE =>
TXEN <= '0';
DONE <= '1';
if GO_SYNC = '0' then
TX_PHY_STATE <= WAIT_NEW_PACKET;
DONE <= '0';
end if;
end case;
if RST = '1' then
TXEN <= '0';
TX_PHY_STATE <= WAIT_NEW_PACKET;
DONE <= '0';
TXD <= (others => '0');
end if;
end process TX_PHY_FSM;
TXER <= '0';
--This process reads data out of the phy and puts it into a buffer.
--There are many buffers on the RX side to cope with data arriving at
--a high rate. If a very large packet is received, followed by many small
--packets, a large number of packets need to be stored.
RX_PHY_FSM : process
begin
wait until rising_edge(ETH_CLK);
RX_WRITE_ENABLE <= '0';
RXDV_D <= RXDV;
RXER_D <= RXER;
RXD_D <= RXD;
case RX_PHY_STATE is
when WAIT_START =>
if RXDV_D = '1' and RXD_D = "01" then
RX_PHY_STATE <= PREAMBLE;
RX_ERROR <= '0';
end if;
when PREAMBLE =>
if RXD_D = "11" then
RX_PHY_STATE <= DATA_0;
RX_START_ADDRESS <= RX_WRITE_ADDRESS;
RX_PACKET_LENGTH <= to_unsigned(0, ADDRESS_BITS);
RX_CRC <= X"ffffffff";
elsif RXD_D /= "11" then
RX_PHY_STATE <= WAIT_START;
end if;
when DATA_0 =>
RX_WRITE_DATA(9 downto 8) <= RXD_D;
LOW_NIBBLE(1 downto 0) <= RXD_D;
if RXDV_D = '1' then
RX_PHY_STATE <= DATA_1;
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when DATA_1 =>
RX_WRITE_DATA(11 downto 10) <= RXD_D;
LOW_NIBBLE(3 downto 2) <= RXD_D;
RX_PHY_STATE <= DATA_2;
when DATA_2 =>
RX_WRITE_DATA(13 downto 12) <= RXD_D;
LOW_NIBBLE(5 downto 4) <= RXD_D;
RX_PHY_STATE <= DATA_3;
when DATA_3 =>
RX_WRITE_DATA(15 downto 14) <= RXD_D;
RX_PACKET_LENGTH <= RX_PACKET_LENGTH + 1;
RX_PHY_STATE <= DATA_4;
RX_CRC <= nextCRC32_D8(RXD_D & LOW_NIBBLE, RX_CRC);
when DATA_4 =>
RX_WRITE_DATA(1 downto 0) <= RXD_D;
LOW_NIBBLE(1 downto 0) <= RXD_D;
if RXDV_D = '1' then
RX_PHY_STATE <= DATA_5;
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when DATA_5 =>
RX_WRITE_DATA(3 downto 2) <= RXD_D;
LOW_NIBBLE(3 downto 2) <= RXD_D;
RX_PHY_STATE <= DATA_6;
when DATA_6 =>
RX_WRITE_DATA(5 downto 4) <= RXD_D;
LOW_NIBBLE(5 downto 4) <= RXD_D;
RX_PHY_STATE <= DATA_7;
when DATA_7 =>
RX_WRITE_DATA(7 downto 6) <= RXD_D;
RX_WRITE_ENABLE <= '1';
RX_PACKET_LENGTH <= RX_PACKET_LENGTH + 1;
RX_PHY_STATE <= DATA_0;
RX_CRC <= nextCRC32_D8(RXD_D & LOW_NIBBLE, RX_CRC);
when END_OF_FRAME =>
if RX_ERROR = '1' then
RX_PHY_STATE <= WAIT_START;
elsif RX_PACKET_LENGTH < 64 then
RX_PHY_STATE <= WAIT_START;
elsif RX_PACKET_LENGTH > 1518 then
RX_PHY_STATE <= WAIT_START;
elsif RX_CRC /= X"C704dd7B" then
RX_PHY_STATE <= WAIT_START;
else
RX_PHY_STATE <= NOTIFY_NEW_PACKET;
end if;
when NOTIFY_NEW_PACKET =>
RX_PHY_STATE <= WAIT_START;
RX_START_ADDRESS_BUFFER(RX_WRITE_BUFFER) <= RX_START_ADDRESS;
RX_PACKET_LENGTH_BUFFER(RX_WRITE_BUFFER) <= RX_PACKET_LENGTH;
if RX_WRITE_BUFFER = 31 then
RX_WRITE_BUFFER <= 0;
else
RX_WRITE_BUFFER <= RX_WRITE_BUFFER + 1;
end if;
end case;
if RXER_D = '1' then
RX_ERROR <= '1';
end if;
if RST = '1' then
RX_PHY_STATE <= WAIT_START;
end if;
end process RX_PHY_FSM;
--generate a signal for each buffer to indicate that is is being used.
GENERATE_BUFFER_BUSY : process
begin
wait until rising_edge(ETH_CLK);
for I in 0 to 31 loop
if I = RX_WRITE_BUFFER then
RX_BUFFER_BUSY(I) <= '1';
else
RX_BUFFER_BUSY(I) <= '0';
end if;
end loop;
end process GENERATE_BUFFER_BUSY;
--This is the memory that implements the RX buffers
WRITE_RX_MEMORY : process
begin
wait until rising_edge(ETH_CLK);
if RX_WRITE_ENABLE = '1' then
RX_MEMORY(to_integer(RX_WRITE_ADDRESS)) := RX_WRITE_DATA;
RX_WRITE_ADDRESS <= RX_WRITE_ADDRESS + 1;
end if;
if RST = '1' then
RX_WRITE_ADDRESS <= (others => '0');
end if;
end process WRITE_RX_MEMORY;
SYNCHRONISE_BUFFER_BUSY : process
begin
wait until rising_edge(CLK);
RX_BUFFER_BUSY_DEL <= RX_BUFFER_BUSY;
RX_BUFFER_BUSY_SYNC <= RX_BUFFER_BUSY_DEL;
end process SYNCHRONISE_BUFFER_BUSY;
--CLK __/""\__/" _/" "\__/""\
--RX_BUFFER_BUSY_SYNC[0] ""\_______ ____________
--RX_BUFFER_BUSY_SYNC[1] ________/" "\__________
--RX_BUFFER_BUSY_SYNC[2] __________ _______/""""
-- ^
-- Start to read packet 0 here.
-- Note: since RX_BUFFER_BUSY originates in a different clock domain,
-- it is possible that a clock cycle or so could elapse between
-- RX_BUFFER_BUSY_SYNC[0] becoming low and RX_BUFFER_BUSY_SYNC[1] becoming
-- high. We are relying on the delay through the state machine to be
-- long enough that we don't try to read BUFFER1 during this period.
RX_PACKET_FSM : process
begin
wait until rising_edge(CLK);
case RX_PACKET_STATE is
when WAIT_INITIALISE =>
if RX_BUFFER_BUSY_SYNC(0) = '1' then
RX_PACKET_STATE <= WAIT_NEW_PACKET;
RX_READ_BUFFER <= 0;
end if;
when WAIT_NEW_PACKET =>
if RX_BUFFER_BUSY_SYNC(RX_READ_BUFFER) = '0' then
RX_PACKET_STATE <= SEND_LENGTH;
RX_START_ADDRESS_SYNC <= RX_START_ADDRESS_BUFFER(RX_READ_BUFFER);
RX_PACKET_LENGTH_SYNC <= RX_PACKET_LENGTH_BUFFER(RX_READ_BUFFER);
RX <=
std_logic_vector(
resize(RX_PACKET_LENGTH_BUFFER(RX_READ_BUFFER)-4, 16));
RX_STB <= '1';
end if;
when SEND_LENGTH =>
if RX_ACK = '1' then
RX_PACKET_STATE <= PREFETCH0;
RX_STB <= '0';
end if;
when PREFETCH0 =>
RX_READ_ADDRESS <= RX_START_ADDRESS_SYNC;
RX_END_ADDRESS <= RX_START_ADDRESS_SYNC + (RX_PACKET_LENGTH_SYNC-3)/2;
RX_PACKET_STATE <= PREFETCH1;
when PREFETCH1 =>
RX_READ_ADDRESS <= RX_READ_ADDRESS + 1;
RX <= RX_MEMORY(to_integer(RX_READ_ADDRESS));
RX_STB <= '1';
RX_PACKET_STATE <= SEND_DATA;
when SEND_DATA =>
if RX_ACK = '1' then
RX_READ_ADDRESS <= RX_READ_ADDRESS + 1;
RX <= RX_MEMORY(to_integer(RX_READ_ADDRESS));
if RX_READ_ADDRESS = RX_END_ADDRESS then --don't send last packet
RX_STB <= '0';
RX_PACKET_STATE <= WAIT_NEW_PACKET;
if RX_READ_BUFFER = 31 then
RX_READ_BUFFER <= 0;
else
RX_READ_BUFFER <= RX_READ_BUFFER + 1;
end if;
end if;
end if;
end case;
if RST = '1' then
RX_STB <= '0';
RX_PACKET_STATE <= WAIT_INITIALISE;
end if;
end process RX_PACKET_FSM;
----------------------------------------------------------------------
-- RESET PHY CHIP
----------------------------------------------------------------------
PHY_RESET <= not RST;
end architecture RTL;
|
mit
|
HSCD-SS16/HSCD-SS16
|
VHDL/testbench/timer_tb.vhd
|
1
|
1324
|
ENTITY timer_tb IS
-- empty
END timer_tb;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ARCHITECTURE verhalten OF timer_tb IS
CONSTANT RSTDEF: std_ulogic := '0';
CONSTANT FRQMAX: natural := natural(50.0e6);
CONSTANT tpd: time := 1 sec / FRQMAX;
CONSTANT dly: time := 1 sec / 307.2e3;
COMPONENT timer
GENERIC(RSTDEF: std_logic);
PORT(rst: IN std_logic; -- reset, RSTDEF active
clk: IN std_logic; -- clock, rising edge active
irq: OUT std_logic; -- interrupt request, high active
iack: IN std_logic); -- interrupt acknowledge, high active
END COMPONENT;
SIGNAL rst: std_logic := RSTDEF;
SIGNAL clk: std_logic := '0';
SIGNAL hlt: std_logic := '0';
SIGNAL irq: std_logic := '0';
SIGNAL iack: std_logic := '0';
BEGIN
rst <= RSTDEF, NOT RSTDEF AFTER 5*tpd;
clk <= not(clk) AFTER tpd/2 WHEN hlt='0' ELSE clk;
hlt <= '0', '1' AFTER 10*dly;
iack <= irq AFTER 3*tpd;
-- -----------------------------------------------------------------------------------------
u1: timer
GENERIC MAP(RSTDEF => RSTDEF)
PORT MAP(rst => rst,
clk => clk,
irq => irq,
iack => iack);
END verhalten;
|
mit
|
onkelthomas/HW_SW_LU_Gr3_2015
|
work/work/vhdl/common/synchronizer/sync_pkg.vhd
|
2
|
359
|
library ieee;
use ieee.std_logic_1164.all;
package sync_pkg is
component sync is
generic
(
SYNC_STAGES : integer range 2 to integer'high;
RESET_VALUE : std_logic
);
port
(
sys_clk : in std_logic;
sys_res_n : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
end component sync;
end package sync_pkg;
|
mit
|
dawsonjon/Chips-Demo
|
synthesis/nexys_4/seven_segment/keyboard.vhd
|
16
|
2713
|
-- ****************************************************************************
-- Filename :keyboard.vhd
-- Project :Wishbone SOC
-- Version :0.1
-- Author :Jonathan P Dawson
-- Created Date :2006-04-14
-- ****************************************************************************
-- Description :PS/2 keyboard decoder
-- ****************************************************************************
-- Dependencies :Standard Libraries
-- ****************************************************************************
-- Revision History :
--
-- Date :2006-04-14
-- Author :Jonathan P Dawson
-- Modification: Created File
--
-- ****************************************************************************
-- Copyright (C) Jonathan P Dawson 2005
-- ****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity KEYBOARD is
port (
CLK : in Std_logic;
RST : in Std_logic;
DATA_STB : out Std_logic;
DATA_ACK : in Std_logic;
DATA : out Std_logic_vector (31 downto 0);
KD : in Std_logic;
KC : in Std_logic
);
end KEYBOARD;
architecture RTL of KEYBOARD is
type STATETYPE is (
INITIALISE,
SEND_DATA,
GET_DATA);
signal STATE : STATETYPE;
signal LAST_KC, INT_KC, INT_KD, KC_DEL, KD_DEL, S_DATA_STB : std_logic;
signal INT_DATA : std_logic_vector(10 downto 0);
signal BIT_COUNT : integer range 0 to 10;
signal TIMEOUT : integer range 0 to 50000000;
begin
process
begin
wait until rising_edge(CLK);
KD_DEL <= KD;
KC_DEL <= KC;
INT_KD <= KD_DEL;
INT_KC <= KC_DEL;
end process;
process
begin
wait until rising_edge(CLK);
LAST_KC <= INT_KC;
case STATE is
when INITIALISE =>
STATE <= GET_DATA;
BIT_COUNT <= 0;
when GET_DATA =>
if TIMEOUT = 0 then
STATE <= INITIALISE;
TIMEOUT <= 50000000;
else
TIMEOUT <= TIMEOUT - 1;
end if;
if LAST_KC = '1' and INT_KC = '0' then
INT_DATA(BIT_COUNT) <= INT_KD;
if BIT_COUNT = 10 then
BIT_COUNT <= 0;
STATE <= SEND_DATA;
else
BIT_COUNT <= BIT_COUNT + 1;
end if;
end if;
when SEND_DATA =>
S_DATA_STB <= '1';
DATA(7 downto 0) <= INT_DATA(8 downto 1);
if S_DATA_STB = '1' and DATA_ACK = '1' then
S_DATA_STB <= '0';
STATE <= GET_DATA;
end if;
end case;
if RST = '1' then
STATE <= INITIALISE;
S_DATA_STB <= '0';
end if;
end process;
DATA_STB <= S_DATA_STB;
end RTL;
|
mit
|
dawsonjon/Chips-Demo
|
demo/bsp_components/test_bench/ethernet_tb.vhd
|
1
|
3513
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ethernet_tb is
end entity ethernet_tb;
architecture RTL of ethernet_tb is
component ethernet is
port(
OBSERVE : out std_logic_vector(31 downto 0);
CLK : in std_logic;
RST : in std_logic;
ETH_CLK : in std_logic;
--GMII IF
TXER : out std_logic;
TXEN : out std_logic;
TXD : out std_logic_vector(1 downto 0);
PHY_RESET : out std_logic;
RXER : in std_logic;
RXDV : in std_logic;
RXD : in std_logic_vector(1 downto 0);
--RX STREAM
TX : in std_logic_vector(15 downto 0);
TX_STB : in std_logic;
TX_ACK : out std_logic;
--RX STREAM
RX : out std_logic_vector(15 downto 0);
RX_STB : out std_logic;
RX_ACK : in std_logic
);
end component ethernet;
type PACKET_TYPE is array(0 to 1024) of std_logic_vector(15 downto 0);
signal PACKET : PACKET_TYPE := (
0=>X"0100", --length
others => X"AAAA"
);
signal I : integer := 0;
signal J : integer := 0;
signal GO : boolean := True;
signal OBSERVE : std_logic_vector(31 downto 0);
signal CLK : std_logic;
signal RST : std_logic;
signal ETH_CLK : std_logic;
--GMII IF
signal TXER : std_logic;
signal TXEN : std_logic;
signal TXD : std_logic_vector(1 downto 0);
signal PHY_RESET : std_logic;
signal RXER : std_logic;
signal RXDV : std_logic;
signal RXD : std_logic_vector(1 downto 0);
--RX STREAM
signal TX : std_logic_vector(15 downto 0);
signal TX_STB : std_logic;
signal TX_ACK : std_logic;
--RX STREAM
signal RX : std_logic_vector(15 downto 0);
signal RX_STB : std_logic;
signal RX_ACK : std_logic;
begin
process
begin
while True loop
CLK <= '1';
wait for 5 ns;
CLK <= '0';
wait for 5 ns;
end loop;
wait;
end process;
process
begin
while True loop
ETH_CLK <= '1';
wait for 10 ns;
ETH_CLK <= '0';
wait for 10 ns;
end loop;
wait;
end process;
process
begin
RST <= '1';
wait for 100 ns;
RST <= '0';
wait;
end process;
ethernet_inst1 : ethernet port map(
OBSERVE => OBSERVE,
CLK => CLK,
RST => RST,
ETH_CLK => ETH_CLK,
PHY_RESET => PHY_RESET,
--GMII IF
TXER => TXER,
TXEN => TXEN,
TXD => TXD,
RXER => TXER,
RXDV => TXEN,
RXD => TXD,
--RX STREAM
TX => TX,
TX_STB => TX_STB,
TX_ACK => TX_ACK,
--RX STREAM
RX => RX,
RX_STB => RX_STB,
RX_ACK => RX_ACK
);
process
begin
wait until rising_edge(CLK);
if GO then
TX <= PACKET(I);
TX_STB <= '1';
if TX_STB = '1' and TX_ACK = '1' then
if I = 129 then
TX_STB <= '0';
GO <= FALSE;
else
I <= I+1;
end if;
end if;
end if;
end process;
process
begin
wait until rising_edge(CLK);
RX_ACK <= '1';
if RX_STB = '1' and RX_ACK = '1' then
if J = 128 then
report "TEST HAS PASSED" severity failure;
end if;
if RX /= PACKET(J) then
report "INCORRECT DATA RECEIVED" severity failure;
end if;
J <= J+1;
end if;
end process;
end architecture RTL;
|
mit
|
dawsonjon/Chips-Demo
|
synthesis/nexys_4/raw_ethernet/bram.vhd
|
15
|
847
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity BRAM is
generic(
DEPTH : integer := 7500;
WIDTH : integer := 8
);
port(
CLK_IN : in std_logic;
CLK_OUT : in std_logic;
WE : in std_logic;
DIN : in std_logic_vector;
AIN : in std_logic_vector;
DOUT : out std_logic_vector;
AOUT : in std_logic_vector
);
end entity BRAM;
architecture RTL of BRAM is
type MEMORY_TYPE is array (0 to DEPTH - 1) of Std_logic_vector(WIDTH-1 downto 0);
shared variable MEMORY : MEMORY_TYPE;
begin
process
begin
wait until rising_edge(CLK_IN);
if WE = '1' then
MEMORY(to_integer(unsigned(AIN))) := DIN;
end if;
end process;
process
begin
wait until rising_edge(CLK_OUT);
DOUT <= MEMORY(to_integer(unsigned(AOUT)));
end process;
end architecture RTL;
|
mit
|
HSCD-SS16/HSCD-SS16
|
Aufgabe1/VHDL/system.vhd
|
1
|
6587
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY system IS
PORT(rst: IN std_logic; -- system reset, high active
clk: IN std_logic; -- system clock, 50 MHz, rising edge active
btn0: IN std_logic; -- push button, low active
rxd: IN std_logic; -- receiver signal
txd: OUT std_logic; -- transmitter signal
evn1: OUT std_logic; -- event1, interrupt, high active
evn2: OUT std_logic; -- event2, RETURNI, high active
led0: OUT std_logic; -- led, low active
led1: OUT std_logic); -- led, low active
END system;
library unisim;
use unisim.vcomponents.all;
ARCHITECTURE structure OF system IS
CONSTANT RSTDEF: std_ulogic := '1'; -- high active
COMPONENT FDSx2
PORT(D : IN std_ulogic; -- data input
Q : OUT std_ulogic; -- data output
S : IN std_ulogic; -- preset, high active
C : IN std_ulogic); -- clock, rising edge active
END COMPONENT;
COMPONENT timer
GENERIC(RSTDEF: std_logic);
PORT(rst: IN std_logic; -- reset, RSTDEF active
clk: IN std_logic; -- clock, rising edge active
irq: OUT std_logic; -- interrupt request, high active
iack: IN std_logic); -- interrupt acknowledge, high active
END COMPONENT;
COMPONENT kcpsm3
Port ( address : out std_logic_vector(9 downto 0);
instruction : in std_logic_vector(17 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
out_port : out std_logic_vector(7 downto 0);
read_strobe : out std_logic;
in_port : in std_logic_vector(7 downto 0);
interrupt : in std_logic;
interrupt_ack : out std_logic;
reset : in std_logic;
clk : in std_logic);
end COMPONENT;
COMPONENT programm
PORT ( address : in std_logic_vector(9 downto 0);
instruction : out std_logic_vector(17 downto 0);
clk : in std_logic);
END COMPONENT;
SIGNAL reset : std_logic; -- high active
SIGNAL sbtn0 : std_logic;
SIGNAL srxd : std_logic;
SIGNAL enable : std_logic_vector(8 DOWNTO 0);
SIGNAL led : std_logic_vector(1 DOWNTO 0);
SIGNAL en0 : std_logic;
SIGNAL en1 : std_logic;
SIGNAL address : std_logic_vector( 9 downto 0);
SIGNAL instruction : std_logic_vector(17 downto 0);
SIGNAL port_id : std_logic_vector( 7 downto 0);
SIGNAL write_strobe : std_logic; -- high active
SIGNAL out_port : std_logic_vector( 7 downto 0);
SIGNAL read_strobe : std_logic; -- high active
SIGNAL in_port : std_logic_vector( 7 downto 0);
SIGNAL interrupt : std_logic; -- high active
SIGNAL interrupt_ack : std_logic; -- high active
BEGIN
-- -----------------------------------------------------------------------------
evn1 <= interrupt;
evn2 <= '1' WHEN instruction(17 DOWNTO 14)="1110" ELSE '0';
-- Resetgenarator und Synchronisation des Resetsignals mit dem System
sync_rst: FDSx2
PORT MAP(D => '0',
Q => reset,
S => rst,
C => clk);
-- -----------------------------------------------------------------------------
-- Synchronisation des Eingangssignals RXD mit dem System
sync_rxd: FDSx2
PORT MAP(D => rxd,
Q => srxd,
S => reset,
C => clk);
-- -----------------------------------------------------------------------------
-- Synchronisation des Eingangssignals BTN0 mit dem System
sync_btn0: FDSx2
PORT MAP(D => btn0,
Q => sbtn0,
S => reset,
C => clk);
-- -----------------------------------------------------------------------------
en1 <= enable(1) AND write_strobe;
-- Flipflop fuer das serielle Datenausgangssignal TXD
txd_ff: FDSE
--synthesis translate_off
generic map (INIT => '1')
--synthesis translate_on
PORT MAP(D => out_port(0),
Q => txd,
CE => en1,
S => reset,
C => clk);
en0 <= enable(0) AND write_strobe;
-- Flipflop fuer das Steuerungssignals der LED0
led0_ff: FDSE
--synthesis translate_off
generic map (INIT => '1')
--synthesis translate_on
PORT MAP(D => out_port(0),
Q => led(0),
CE => en0,
S => reset,
C => clk);
-- Flipflop fuer das Steuerungssignals der LED1
led1_ff: FDSE
--synthesis translate_off
generic map (INIT => '1')
--synthesis translate_on
PORT MAP(D => out_port(1),
Q => led(1),
CE => en0,
S => reset,
C => clk);
led0 <= led(0);
led1 <= led(1);
-- -----------------------------------------------------------------------------
-- Timer
t1: timer
GENERIC MAP(RSTDEF => RSTDEF)
PORT MAP(rst => reset,
clk => clk,
irq => interrupt,
iack => interrupt_ack);
-- -----------------------------------------------------------------------------
-- Dekoder
WITH port_id(3 DOWNTO 0) SELECT
enable <= "000000001" WHEN "0000",
"000000010" WHEN "0001",
"000000100" WHEN "0010",
"000001000" WHEN "0011",
"000010000" WHEN "0100",
"000100000" WHEN "0101",
"001000000" WHEN "0110",
"010000000" WHEN "0111",
"100000000" WHEN "1000",
"000000000" WHEN OTHERS;
WITH port_id(3 DOWNTO 0) SELECT
in_port <= "00000" & sbtn0 & led WHEN "0000",
"0000000" & srxd WHEN "0001",
"00000000" WHEN OTHERS;
-- -----------------------------------------------------------------------------
cpu: kcpsm3
PORT MAP(reset => reset,
clk => clk,
address => address,
instruction => instruction,
port_id => port_id,
write_strobe => write_strobe,
out_port => out_port,
read_strobe => read_strobe,
in_port => in_port,
interrupt => interrupt,
interrupt_ack => interrupt_ack);
-- -----------------------------------------------------------------------------
-- programm memory
rom: programm
PORT MAP(clk => clk,
address => address,
instruction => instruction);
END structure;
|
mit
|
dawsonjon/Chips-Demo
|
synthesis/nexys_4/hello_world/i2c.vhd
|
15
|
8318
|
--- COMMAND
--- =======
---
--- Bits (7:0)
--- ----------
--- (For write byte only) data payload byte
---
--- Bit (8)
--- -------
--- 1 = read byte
--- 0 = write byte
---
--- Bit (9)
--- -------
--- 1 = SEND_START
---
--- Bit (10)
--- --------
--- 1 = SEND_STOP
---
--- Bit (11)
--- --------
--- (For read byte only) 1 = SEND_ACK
---
--- RESPONSE
--- ========
---
--- Bits (7:0)
--- ----------
--- (For read byte only) data payload byte
---
--- Bit (0)
--- -------
--- (For write byte only) 1 = NACK, 0 = ACK
---
library ieee;
use ieee.std_logic_1164.all;
entity I2C is
generic(
CLOCKS_PER_SECOND : integer := 50000000;
SPEED : integer := 100000
);
port(
CLK : in std_logic;
RST : in std_logic;
SDA : inout std_logic;
SCL : inout std_logic;
I2C_IN : in std_logic_vector(31 downto 0);
I2C_IN_STB : in std_logic;
I2C_IN_ACK : out std_logic;
I2C_OUT : out std_logic_vector(31 downto 0);
I2C_OUT_STB : out std_logic;
I2C_OUT_ACK : in std_logic
);
end entity I2C;
architecture RTL of I2C is
constant I2C_DELAY : integer := CLOCKS_PER_SECOND / (2*SPEED);
type STATE_TYPE is (
MAIN_0, MAIN_1, MAIN_2, MAIN_3, GET_BYTE_0, GET_BYTE_1, GET_BYTE_2,
GET_BYTE_3, SEND_BYTE_0, SEND_BYTE_1, SEND_BYTE_2, SEND_BYTE_3, SEND_BYTE_4,
SEND_BIT_0, SEND_BIT_1, SEND_BIT_2, GET_BIT_0, GET_BIT_1, GET_BIT_2,
SEND_START_0, SEND_START_1, SEND_START_2, SEND_START_3, SEND_START_4,
SEND_STOP_0, SEND_STOP_1, SEND_STOP_2, SEND_STOP_3, SEND_STOP_4
);
signal STATE, GET_BYTE_RETURN, SEND_BYTE_RETURN, SEND_BIT_RETURN, GET_BIT_RETURN,
SEND_STOP_RETURN, SEND_START_RETURN : STATE_TYPE;
signal TIMER : integer range 0 to I2C_DELAY;
signal COUNT : integer range 0 to 7;
signal COMMAND : std_logic_vector(31 downto 0);
signal RESPONSE : std_logic_vector(31 downto 0);
signal STARTED : std_logic;
signal S_I2C_IN_ACK : std_logic;
signal S_I2C_OUT_STB : std_logic;
signal SDA_I_D, SDA_I_SYNCH, SDA_I, SDA_O : std_logic;
signal SCL_I_D, SCL_I_SYNCH, SCL_I, SCL_O : std_logic;
signal BIT : std_logic;
begin
SDA <= 'Z' when SDA_O = '1' else '0';
SDA_I <= '1' when SDA /= '0' else '0';
SCL <= 'Z' when SCL_O = '1' else '0';
SCL_I <= '1' when SCL /= '0' else '0';
process
begin
wait until rising_edge(CLK);
SDA_I_D <= SDA_I;
SDA_I_SYNCH <= SDA_I_D;
SCL_I_D <= SCL_I;
SCL_I_SYNCH <= SCL_I_D;
case STATE is
--MAIN SUBROUTINE
when MAIN_0 =>
COUNT <= 7;
TIMER <= I2C_DELAY;
STATE <= MAIN_1;
STARTED <= '0';
when MAIN_1 =>
S_I2C_IN_ACK <= '1';
if I2C_IN_STB = '1' and S_I2C_IN_ACK = '1' then
S_I2C_IN_ACK <= '0';
COMMAND <= I2C_IN;
STATE <= MAIN_2;
end if;
when MAIN_2 =>
if COMMAND(8) = '1' then
RESPONSE <= (others => '0');
STATE <= GET_BYTE_0;
GET_BYTE_RETURN <= MAIN_3;
else
RESPONSE <= (others => '0');
STATE <= SEND_BYTE_0;
SEND_BYTE_RETURN <= MAIN_3;
end if;
when MAIN_3 =>
S_I2C_OUT_STB <= '1';
I2C_OUT <= RESPONSE;
if I2C_OUT_ACK = '1' and S_I2C_OUT_STB = '1' then
S_I2C_OUT_STB <= '0';
STATE <= MAIN_1;
end if;
--GET BYTE SUBROUTINE
when GET_BYTE_0 =>
STATE <= GET_BIT_0;
GET_BIT_RETURN <= GET_BYTE_1;
when GET_BYTE_1 =>
RESPONSE(COUNT) <= BIT;
if COUNT = 0 then
COUNT <= 7;
STATE <= GET_BYTE_2;
else
COUNT <= COUNT - 1;
STATE <= GET_BYTE_0;
end if;
when GET_BYTE_2 =>
--SEND NACK ACK = 0 NACK = 1
BIT <= COMMAND(11);
STATE <= SEND_BIT_0;
SEND_BIT_RETURN <= GET_BYTE_3;
when GET_BYTE_3 =>
if COMMAND(10) = '1' then
STATE <= SEND_STOP_0;
SEND_STOP_RETURN <= GET_BYTE_RETURN;
else
STATE <= GET_BYTE_RETURN;
end if;
--SEND BYTE SUBROUTINE
when SEND_BYTE_0 =>
if COMMAND(9) = '1' then
STATE <= SEND_START_0;
SEND_START_RETURN <= SEND_BYTE_1;
else
STATE <= SEND_BYTE_1;
end if;
when SEND_BYTE_1 =>
BIT <= COMMAND(COUNT);
STATE <= SEND_BIT_0;
SEND_BIT_RETURN <= SEND_BYTE_2;
when SEND_BYTE_2 =>
if COUNT = 0 then
COUNT <= 7;
STATE <= SEND_BYTE_3;
else
COUNT <= COUNT - 1;
STATE <= SEND_BYTE_1;
end if;
when SEND_BYTE_3 =>
--GET ACK
STATE <= GET_BIT_0;
GET_BIT_RETURN <= SEND_BYTE_4;
when SEND_BYTE_4 =>
--1 = NACK, 0 = ACK
RESPONSE(0) <= BIT;
if COMMAND(10) = '1' then
STATE <= SEND_STOP_0;
SEND_START_RETURN <= SEND_BYTE_RETURN;
else
STATE <= SEND_BYTE_RETURN;
end if;
--SEND START SUBROUTINE
when SEND_START_0 =>
if STARTED = '0' then
STATE <= SEND_START_1;
else
STATE <= SEND_START_4;
end if;
when SEND_START_1 =>
SDA_O <= '1';
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= SEND_START_2;
else
TIMER <= TIMER - 1;
end if;
when SEND_START_2 =>
SCL_O <= '1';
if SCL_I_SYNCH = '1' then
STATE <= SEND_START_3;
end if;
when SEND_START_3 =>
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= SEND_START_4;
else
TIMER <= TIMER - 1;
end if;
when SEND_START_4 =>
SDA_O <= '0';
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= SEND_START_RETURN;
SCL_O <= '0';
STARTED <= '1';
else
TIMER <= TIMER - 1;
end if;
--SEND STOP SUBROUTINE
when SEND_STOP_0 =>
SDA_O <= '0';
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= SEND_STOP_1;
else
TIMER <= TIMER - 1;
end if;
when SEND_STOP_1 =>
SCL_O <= '1';
if SCL_I_SYNCH = '1' then
STATE <= SEND_STOP_2;
end if;
when SEND_STOP_2 =>
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= SEND_STOP_3;
SDA_O <= '1';
else
TIMER <= TIMER - 1;
end if;
when SEND_STOP_3 =>
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= SEND_STOP_4;
else
TIMER <= TIMER - 1;
end if;
when SEND_STOP_4 =>
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= SEND_STOP_RETURN;
STARTED <= '0';
else
TIMER <= TIMER - 1;
end if;
--SEND BIT SUBROUTINE
when SEND_BIT_0 =>
SDA_O <= BIT;
SCL_O <= '0';
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= SEND_BIT_1;
else
TIMER <= TIMER - 1;
end if;
when SEND_BIT_1 =>
--CLOCK STRETCHING
SCL_O <= '1';
if SCL_I_SYNCH = '1' then
STATE <= SEND_BIT_2;
end if;
when SEND_BIT_2 =>
if TIMER = 0 then
TIMER <= I2C_DELAY;
SCL_O <= '0';
STATE <= SEND_BIT_RETURN;
else
TIMER <= TIMER - 1;
end if;
--GET BIT SUBROUTINE
when GET_BIT_0 =>
SDA_O <= '1';
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= GET_BIT_1;
else
TIMER <= TIMER - 1;
end if;
when GET_BIT_1 =>
--CLOCK STRETCHING
SCL_O <= '1';
if SCL_I_SYNCH = '1' then
STATE <= GET_BIT_2;
end if;
when GET_BIT_2 =>
BIT <= SDA_I_SYNCH;
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= GET_BIT_RETURN;
SCL_O <= '0';
else
TIMER <= TIMER - 1;
end if;
end case;
if RST = '1' then
STATE <= MAIN_0;
S_I2C_OUT_STB <= '0';
SDA_O <= '1';
SCL_O <= '1';
end if;
end process;
I2C_OUT_STB <= S_I2C_OUT_STB;
I2C_IN_ACK <= S_I2C_IN_ACK;
end RTL;
|
mit
|
dawsonjon/Chips-Demo
|
synthesis/nexys_4/clock/i2c.vhd
|
15
|
8318
|
--- COMMAND
--- =======
---
--- Bits (7:0)
--- ----------
--- (For write byte only) data payload byte
---
--- Bit (8)
--- -------
--- 1 = read byte
--- 0 = write byte
---
--- Bit (9)
--- -------
--- 1 = SEND_START
---
--- Bit (10)
--- --------
--- 1 = SEND_STOP
---
--- Bit (11)
--- --------
--- (For read byte only) 1 = SEND_ACK
---
--- RESPONSE
--- ========
---
--- Bits (7:0)
--- ----------
--- (For read byte only) data payload byte
---
--- Bit (0)
--- -------
--- (For write byte only) 1 = NACK, 0 = ACK
---
library ieee;
use ieee.std_logic_1164.all;
entity I2C is
generic(
CLOCKS_PER_SECOND : integer := 50000000;
SPEED : integer := 100000
);
port(
CLK : in std_logic;
RST : in std_logic;
SDA : inout std_logic;
SCL : inout std_logic;
I2C_IN : in std_logic_vector(31 downto 0);
I2C_IN_STB : in std_logic;
I2C_IN_ACK : out std_logic;
I2C_OUT : out std_logic_vector(31 downto 0);
I2C_OUT_STB : out std_logic;
I2C_OUT_ACK : in std_logic
);
end entity I2C;
architecture RTL of I2C is
constant I2C_DELAY : integer := CLOCKS_PER_SECOND / (2*SPEED);
type STATE_TYPE is (
MAIN_0, MAIN_1, MAIN_2, MAIN_3, GET_BYTE_0, GET_BYTE_1, GET_BYTE_2,
GET_BYTE_3, SEND_BYTE_0, SEND_BYTE_1, SEND_BYTE_2, SEND_BYTE_3, SEND_BYTE_4,
SEND_BIT_0, SEND_BIT_1, SEND_BIT_2, GET_BIT_0, GET_BIT_1, GET_BIT_2,
SEND_START_0, SEND_START_1, SEND_START_2, SEND_START_3, SEND_START_4,
SEND_STOP_0, SEND_STOP_1, SEND_STOP_2, SEND_STOP_3, SEND_STOP_4
);
signal STATE, GET_BYTE_RETURN, SEND_BYTE_RETURN, SEND_BIT_RETURN, GET_BIT_RETURN,
SEND_STOP_RETURN, SEND_START_RETURN : STATE_TYPE;
signal TIMER : integer range 0 to I2C_DELAY;
signal COUNT : integer range 0 to 7;
signal COMMAND : std_logic_vector(31 downto 0);
signal RESPONSE : std_logic_vector(31 downto 0);
signal STARTED : std_logic;
signal S_I2C_IN_ACK : std_logic;
signal S_I2C_OUT_STB : std_logic;
signal SDA_I_D, SDA_I_SYNCH, SDA_I, SDA_O : std_logic;
signal SCL_I_D, SCL_I_SYNCH, SCL_I, SCL_O : std_logic;
signal BIT : std_logic;
begin
SDA <= 'Z' when SDA_O = '1' else '0';
SDA_I <= '1' when SDA /= '0' else '0';
SCL <= 'Z' when SCL_O = '1' else '0';
SCL_I <= '1' when SCL /= '0' else '0';
process
begin
wait until rising_edge(CLK);
SDA_I_D <= SDA_I;
SDA_I_SYNCH <= SDA_I_D;
SCL_I_D <= SCL_I;
SCL_I_SYNCH <= SCL_I_D;
case STATE is
--MAIN SUBROUTINE
when MAIN_0 =>
COUNT <= 7;
TIMER <= I2C_DELAY;
STATE <= MAIN_1;
STARTED <= '0';
when MAIN_1 =>
S_I2C_IN_ACK <= '1';
if I2C_IN_STB = '1' and S_I2C_IN_ACK = '1' then
S_I2C_IN_ACK <= '0';
COMMAND <= I2C_IN;
STATE <= MAIN_2;
end if;
when MAIN_2 =>
if COMMAND(8) = '1' then
RESPONSE <= (others => '0');
STATE <= GET_BYTE_0;
GET_BYTE_RETURN <= MAIN_3;
else
RESPONSE <= (others => '0');
STATE <= SEND_BYTE_0;
SEND_BYTE_RETURN <= MAIN_3;
end if;
when MAIN_3 =>
S_I2C_OUT_STB <= '1';
I2C_OUT <= RESPONSE;
if I2C_OUT_ACK = '1' and S_I2C_OUT_STB = '1' then
S_I2C_OUT_STB <= '0';
STATE <= MAIN_1;
end if;
--GET BYTE SUBROUTINE
when GET_BYTE_0 =>
STATE <= GET_BIT_0;
GET_BIT_RETURN <= GET_BYTE_1;
when GET_BYTE_1 =>
RESPONSE(COUNT) <= BIT;
if COUNT = 0 then
COUNT <= 7;
STATE <= GET_BYTE_2;
else
COUNT <= COUNT - 1;
STATE <= GET_BYTE_0;
end if;
when GET_BYTE_2 =>
--SEND NACK ACK = 0 NACK = 1
BIT <= COMMAND(11);
STATE <= SEND_BIT_0;
SEND_BIT_RETURN <= GET_BYTE_3;
when GET_BYTE_3 =>
if COMMAND(10) = '1' then
STATE <= SEND_STOP_0;
SEND_STOP_RETURN <= GET_BYTE_RETURN;
else
STATE <= GET_BYTE_RETURN;
end if;
--SEND BYTE SUBROUTINE
when SEND_BYTE_0 =>
if COMMAND(9) = '1' then
STATE <= SEND_START_0;
SEND_START_RETURN <= SEND_BYTE_1;
else
STATE <= SEND_BYTE_1;
end if;
when SEND_BYTE_1 =>
BIT <= COMMAND(COUNT);
STATE <= SEND_BIT_0;
SEND_BIT_RETURN <= SEND_BYTE_2;
when SEND_BYTE_2 =>
if COUNT = 0 then
COUNT <= 7;
STATE <= SEND_BYTE_3;
else
COUNT <= COUNT - 1;
STATE <= SEND_BYTE_1;
end if;
when SEND_BYTE_3 =>
--GET ACK
STATE <= GET_BIT_0;
GET_BIT_RETURN <= SEND_BYTE_4;
when SEND_BYTE_4 =>
--1 = NACK, 0 = ACK
RESPONSE(0) <= BIT;
if COMMAND(10) = '1' then
STATE <= SEND_STOP_0;
SEND_START_RETURN <= SEND_BYTE_RETURN;
else
STATE <= SEND_BYTE_RETURN;
end if;
--SEND START SUBROUTINE
when SEND_START_0 =>
if STARTED = '0' then
STATE <= SEND_START_1;
else
STATE <= SEND_START_4;
end if;
when SEND_START_1 =>
SDA_O <= '1';
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= SEND_START_2;
else
TIMER <= TIMER - 1;
end if;
when SEND_START_2 =>
SCL_O <= '1';
if SCL_I_SYNCH = '1' then
STATE <= SEND_START_3;
end if;
when SEND_START_3 =>
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= SEND_START_4;
else
TIMER <= TIMER - 1;
end if;
when SEND_START_4 =>
SDA_O <= '0';
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= SEND_START_RETURN;
SCL_O <= '0';
STARTED <= '1';
else
TIMER <= TIMER - 1;
end if;
--SEND STOP SUBROUTINE
when SEND_STOP_0 =>
SDA_O <= '0';
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= SEND_STOP_1;
else
TIMER <= TIMER - 1;
end if;
when SEND_STOP_1 =>
SCL_O <= '1';
if SCL_I_SYNCH = '1' then
STATE <= SEND_STOP_2;
end if;
when SEND_STOP_2 =>
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= SEND_STOP_3;
SDA_O <= '1';
else
TIMER <= TIMER - 1;
end if;
when SEND_STOP_3 =>
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= SEND_STOP_4;
else
TIMER <= TIMER - 1;
end if;
when SEND_STOP_4 =>
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= SEND_STOP_RETURN;
STARTED <= '0';
else
TIMER <= TIMER - 1;
end if;
--SEND BIT SUBROUTINE
when SEND_BIT_0 =>
SDA_O <= BIT;
SCL_O <= '0';
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= SEND_BIT_1;
else
TIMER <= TIMER - 1;
end if;
when SEND_BIT_1 =>
--CLOCK STRETCHING
SCL_O <= '1';
if SCL_I_SYNCH = '1' then
STATE <= SEND_BIT_2;
end if;
when SEND_BIT_2 =>
if TIMER = 0 then
TIMER <= I2C_DELAY;
SCL_O <= '0';
STATE <= SEND_BIT_RETURN;
else
TIMER <= TIMER - 1;
end if;
--GET BIT SUBROUTINE
when GET_BIT_0 =>
SDA_O <= '1';
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= GET_BIT_1;
else
TIMER <= TIMER - 1;
end if;
when GET_BIT_1 =>
--CLOCK STRETCHING
SCL_O <= '1';
if SCL_I_SYNCH = '1' then
STATE <= GET_BIT_2;
end if;
when GET_BIT_2 =>
BIT <= SDA_I_SYNCH;
if TIMER = 0 then
TIMER <= I2C_DELAY;
STATE <= GET_BIT_RETURN;
SCL_O <= '0';
else
TIMER <= TIMER - 1;
end if;
end case;
if RST = '1' then
STATE <= MAIN_0;
S_I2C_OUT_STB <= '0';
SDA_O <= '1';
SCL_O <= '1';
end if;
end process;
I2C_OUT_STB <= S_I2C_OUT_STB;
I2C_IN_ACK <= S_I2C_IN_ACK;
end RTL;
|
mit
|
16-bit-risc/16-bit-risc
|
vhdl/inctwo.vhd
|
4
|
302
|
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity inctwo is
port (DIN : in std_logic_vector(15 downto 0);
DOUT : out std_logic_vector(15 downto 0));
end inctwo;
architecture Logic of inctwo is
begin
ADD_COMP : add16 port map(DIN,"0000000000000010",DOUT);
end Logic;
|
mit
|
16-bit-risc/16-bit-risc
|
vhdl/add16.vhd
|
4
|
453
|
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity add16 is
port (X,Y : in std_logic_vector(15 downto 0);
Z : out std_logic_vector(15 downto 0));
end add16;
architecture Logic of add16 is
signal C : std_logic_vector(4 downto 0);
begin
C(0)<='0';
adx : for i in 0 to 3 generate
ADD_COMP : add4 port map(X((i*4)+3 downto i*4),Y((i*4)+3 downto i*4),C(i),Z((i*4)+3 downto i*4),C(i+1));
end generate adx;
end Logic;
|
mit
|
mikeek/FIT
|
INP/proj_1/fpga/ledc8x8.vhd
|
1
|
1805
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity ledc8x8 is
port(
SMCLK: in std_logic;
RESET: in std_logic;
ROW: out std_logic_vector(7 downto 0);
LED: out std_logic_vector(7 downto 0)
);
end entity ledc8x8;
architecture main of ledc8x8 is
signal ce: std_logic := '1';
signal switch: std_logic := '0';
signal ctrl_cnt: std_logic_vector(21 downto 0) := (others => '0');
signal row_cnt: std_logic_vector(7 downto 0) := "10000000";
signal led_state: std_logic_vector(7 downto 0) := "01110111";
begin
ctrl_proc: process(SMCLK, RESET)
begin
if (RESET = '1') then
ctrl_cnt <= (others => '0');
elsif ((SMCLK'event) and (SMCLK = '1')) then
ctrl_cnt <= ctrl_cnt + 1;
if (ctrl_cnt(7 downto 0) = "11111111") then
ce <= '1';
else
ce <= '0';
end if;
end if;
switch <= ctrl_cnt(21);
end process;
row_proc: process(SMCLK, RESET)
begin
if (RESET = '1') then
row_cnt <= "10000000";
elsif ((SMCLK'event) and (SMCLK = '1') and (ce = '1')) then
row_cnt <= row_cnt(0) & row_cnt(7 downto 1);
end if;
ROW <= row_cnt;
end process;
dec_proc: process(SMCLK)
begin
case row_cnt is
when "10000000" => led_state <= "01110111";
when "01000000" => led_state <= "00100111";
when "00100000" => led_state <= "01010111";
when "00010000" => led_state <= "01110110";
when "00001000" => led_state <= "01110101";
when "00000100" => led_state <= "11110011";
when "00000010" => led_state <= "11110101";
when "00000001" => led_state <= "11110110";
when others => led_state <= (others => '1');
end case;
end process;
blink_proc: process(SMCLK)
begin
if (switch = '0') then
LED <= led_state;
else
LED <= (others => '1');
end if;
end process;
end architecture main;
|
mit
|
mikeek/FIT
|
IVH/proj_1/fpga/top.vhd
|
1
|
24944
|
-- VHDL projekt - Hodiny + budík na VGA výstup pomocí zaøízení FitKit 2.0
-- Aplikace po nahrání do FitKitu zobrazuje na VGA výstupu hodiny.
-- Ty na zaèátku poèítají od 00:00:00. Hodiny lze nastavit pomocí klávesnice na FitKitu.
-- Aplikace té umí funkci budíku (pouze vizuální). Po nastavení èasu pro budík kontroluje,
-- zda se ji shoduje aktuální èas s tím budíkovým. Pokud ano, hodiny blikají s periodou 0.5 s.
-- Ovládání:
-- # - vstup do nastavení hodin, potvrzení nastavení hodin, potvrzení nastavení budíku
-- * - vstup do nastavení budíku
-- A - zapnutí/vypnutí budíku (indikace teèkou nalevo od hodin) + vypnutí blikání budíku
-- 0-9 - nastavení konkrétní hodnoty na zvýraznìné pozici pøi editaci
-- Aplikace byla vytvoøena jako semestrální projekt do pøedmìtu IVH na FIT VUT, 2012/2013.
-- Náleí k ní i dokumentace s podrobnìjími informacemi.
-- Datum vytvoøení: 1.5.2013
-- Datum poslední editace: 26.5.2013
-- Vytvoøili:
-- Michal Kozubík, xkozub03, student 1BIA FIT VUT Brno, [email protected]
-- Marek Hurta, xhurta01, student 1BIA FIT VUT Brno, [email protected]
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.vga_controller_cfg.all;
use work.clkgen_cfg.all;
entity fsm is
port(
CLK : in std_logic;
RESET : in std_logic;
KEY : in std_logic_vector(15 downto 0);
value : out integer range 0 to 15;
CNTS : out std_logic_vector(13 downto 0)
);
end entity fsm;
architecture main of tlv_pc_ifc is
-- perioda pro èítaè, který pøi pouitém CLK generuje signál s periodou 1 sekunda
constant period: integer := 7372800;
-- vektor pro data z klávesnice
signal kb_data_out: std_logic_vector(15 downto 0);
-- hodnoty jednotlivých èíslic hodin a budíku
subtype small is integer range 0 to 10;
signal cnt: integer := 0;
signal cnt_sj: small := 0;
signal cnt_mj: small := 0;
signal cnt_hj: small := 0;
signal cnt_sd: small := 0;
signal cnt_md: small := 0;
signal cnt_hd: small := 0;
signal al_sj: small := 0;
signal al_sd: small := 0;
signal al_mj: small := 0;
signal al_md: small := 0;
signal al_hj: small := 0;
signal al_hd: small := 0;
-- signaly znaèící vygenerování sekundy, minuty, hodiny
signal sec : std_logic := '0';
signal min: std_logic := '0';
signal hour: std_logic := '0';
-- hodnota zmáèknuté klávesy pøijata z koneèného automatu
signal value: integer range 0 to 15 := 0;
-- signály pro identifikaci práce koneèného automatu (ve které fázi se nachází)
-- CNTS(0) = '1' => zápis do desítkové pozice hodin (cnt_hd nebo al_hd)
-- CNTS(1) = '1' => zápis do jednotkové pozice hodin (cnt_hj nebo al_hj)
-- CNTS(2) = '1' => zápis do desítkové pozice minut (cnt_md nebo al_md)
-- CNTS(3) = '1' => zápis do jednotkové pozice minut (cnt_mj nebo al_mj)
-- CNTS(4) = '1' => zápis do desítkové pozice sekund (cnt_sd nebo al_sd)
-- CNTS(5) = '1' => zápis do jednotkové pozice sekund (cnt_sj nebo al_sj)
-- CNTS(6) = '1' => èekání na zápis na desítkovou pozici hodin (zvýraznìna první pozice na VGA výstupu)
-- CNTS(7) = '1' => èekání na zápis na jednotkovou pozici hodin (zvýraznìna druhá pozice na VGA výstupu)
-- CNTS(8) = '1' => èekání na zápis na desítkovou pozici minut (zvýraznìna tøetí pozice na VGA výstupu)
-- CNTS(9) = '1' => èekání na zápis na jednotkovou pozici minut (zvýraznìna ètvrtá pozice na VGA výstupu)
-- CNTS(10) = '1' => èekání na zápis na desítkovou pozici sekund (zvýraznìna pátá pozice na VGA výstupu)
-- CNTS(11) = '1' => èekání na zápis na jednotkovou pozici sekund (zvýraznìna está pozice na VGA výstupu)
-- CNTS(12) => '0' => probíhá nastavování hodin, '1' => probíhá nastavování budíku
-- CNTS(13) => '0' => budík je neaktivní, '1' => budík je aktivován
signal CNTS: std_logic_vector(13 downto 0) := (others => '0');
-- BLINK(0) => blikání hodin ('0' viditelné na výstupu, '1' výstup prázdný)
-- BLINK(1) = '1' => blikání hodin zapnuto
signal BLINK: std_logic_vector(1 downto 0) := (others => '1');
-- signály potøebné pro práci s VGA výstupem
signal vga_mode: std_logic_vector (60 downto 0);
signal red: std_logic_vector (2 downto 0);
signal green: std_logic_vector (2 downto 0);
signal blue: std_logic_vector (2 downto 0);
signal rgb_sj: std_logic_vector (8 downto 0);
signal rgb_mj: std_logic_vector (8 downto 0);
signal rgb_hj: std_logic_vector (8 downto 0);
signal rgb_sd: std_logic_vector (8 downto 0);
signal rgb_md: std_logic_vector (8 downto 0);
signal rgb_hd: std_logic_vector (8 downto 0);
signal rgbf: std_logic_vector (8 downto 0);
signal vga_row: std_logic_vector (11 downto 0);
signal vga_col: std_logic_vector (11 downto 0);
signal rom_col: integer range 0 to 8;
signal sec_wrj: std_logic := '0';
signal min_wrj: std_logic := '0';
signal hr_wrj: std_logic := '0';
signal sec_wrd: std_logic := '0';
signal min_wrd: std_logic := '0';
signal hr_wrd: std_logic := '0';
-- ROM pamì s uloenými èíslicemi 0 - 9
type pamet is array(0 to 8*10-1) of std_logic_vector (0 to 7);
signal rom_digit: pamet := ("00000000", -- 0
"00111100",
"00100100",
"00100100",
"00100100",
"00111100",
"00000000",
(others => '0'),
"00000000", -- 1
"00000100",
"00000100",
"00000100",
"00000100",
"00000100",
"00000000",
(others => '0'),
"00000000", -- 2
"00111100",
"00000100",
"00111100",
"00100000",
"00111100",
"00000000",
(others => '0'),
"00000000", -- 3
"00111100",
"00000100",
"00111100",
"00000100",
"00111100",
"00000000",
(others => '0'),
"00000000", -- 4
"00100100",
"00100100",
"00111100",
"00000100",
"00000100",
"00000000",
(others => '0'),
"00000000", -- 5
"00111100",
"00100000",
"00111100",
"00000100",
"00111100",
"00000000",
(others => '0'),
"00000000", -- 6
"00111100",
"00100000",
"00111100",
"00100100",
"00111100",
"00000000",
(others => '0'),
"00000000", -- 7
"00111100",
"00000100",
"00000100",
"00000100",
"00000100",
"00000000",
(others => '0'),
"00000000", -- 8
"00111100",
"00100100",
"00111100",
"00100100",
"00111100",
"00000000",
(others => '0'),
"00000000", -- 9
"00111100",
"00100100",
"00111100",
"00000100",
"00111100",
"00000000",
(others => '0'));
begin
-- namapování entity pro práci s klávesnicí na FitKitu
kbc_u : entity work.keyboard_controller_high
-- pragma translate off
generic map(
READ_INTERVAL => 32
)
-- pragma translate on
port map(
CLK => SMCLK,
RST => RESET,
DATA_OUT => kb_data_out,
KB_KIN => KIN,
KB_KOUT => KOUT
);
-- namapování entity pro práci s koneèným automatem
fistma: entity fsm
port map(
CLK => SMCLK,
RESET => RESET,
KEY => kb_data_out,
value => value,
CNTS => CNTS
);
-- namapování entity pro práci s VGA výstupem
vga: entity work.vga_controller(arch_vga_controller)
port map(
CLK => CLK,
RST => RESET,
ENABLE => '1',
MODE => vga_mode,
DATA_RED => red,
DATA_GREEN => green,
DATA_BLUE => blue,
ADDR_COLUMN => vga_col,
ADDR_ROW => vga_row,
VGA_RED => RED_V,
VGA_GREEN => GREEN_V,
VGA_BLUE => BLUE_V,
VGA_HSYNC => HSYNC_V,
VGA_VSYNC => VSYNC_V
);
setmode(r640x480x60, vga_mode);
rom_col <= conv_integer(vga_col(5 downto 3));
-- zjitìní pro kadý counter jestli se pro nìj v pamìtí nachází '1' nebo '0'
-- také se rozhoduje, jestli se zobrazují èíslice hodin nebo budíku (pøo jeho nastavování)
sec_wrj <= rom_digit(al_sj*8 + conv_integer(vga_row(5 downto 3)))(rom_col) when (CNTS(12) = '1') else
rom_digit(cnt_sj*8 + conv_integer(vga_row(5 downto 3)))(rom_col);
sec_wrd <= rom_digit(al_sd*8 + conv_integer(vga_row(5 downto 3)))(rom_col) when (CNTS(12) = '1') else
rom_digit(cnt_sd*8 + conv_integer(vga_row(5 downto 3)))(rom_col);
min_wrj <= rom_digit(al_mj*8 + conv_integer(vga_row(5 downto 3)))(rom_col) when (CNTS(12) = '1') else
rom_digit(cnt_mj*8 + conv_integer(vga_row(5 downto 3)))(rom_col);
min_wrd <= rom_digit(al_md*8 + conv_integer(vga_row(5 downto 3)))(rom_col) when (CNTS(12) = '1') else
rom_digit(cnt_md*8 + conv_integer(vga_row(5 downto 3)))(rom_col);
hr_wrj <= rom_digit(al_hj*8 + conv_integer(vga_row(5 downto 3)))(rom_col) when (CNTS(12) = '1') else
rom_digit(cnt_hj*8 + conv_integer(vga_row(5 downto 3)))(rom_col);
hr_wrd <= rom_digit(al_hd*8 + conv_integer(vga_row(5 downto 3)))(rom_col) when (CNTS(12) = '1') else
rom_digit(cnt_hd*8 + conv_integer(vga_row(5 downto 3)))(rom_col);
-- nastavení barev pro vechny zjitìné hodnoty
-- aktuálnì nastavovaná èíslice je zvýraznìna modøe
-- klasické hodinové èíslice jsou zelené a èíslice budíku fialové
rgb_sj <= "000"&"101"&"000" when (sec_wrj = '1') and (CNTS(11) = '0') and (CNTS(12) = '0') else
"101"&"000"&"101" when (sec_wrj = '1') and (CNTS(11) = '0') and (CNTS(12) = '1') else
"000"&"000"&"101" when (sec_wrj = '1') and (CNTS(11) = '1') else
"000"&"000"&"000";
rgb_sd <= "000"&"101"&"000" when (sec_wrd = '1') and (CNTS(10) = '0') and (CNTS(12) = '0') else
"101"&"000"&"101" when (sec_wrd = '1') and (CNTS(10) = '0') and (CNTS(12) = '1') else
"000"&"000"&"101" when (sec_wrd = '1') and (CNTS(10) = '1') else
"000"&"000"&"000";
rgb_mj <= "000"&"101"&"000" when (min_wrj = '1') and (CNTS(9) = '0') and (CNTS(12) = '0') else
"101"&"000"&"101" when (min_wrj = '1') and (CNTS(9) = '0') and (CNTS(12) = '1') else
"000"&"000"&"101" when (min_wrj = '1') and (CNTS(9) = '1') else
"000"&"000"&"000";
rgb_md <= "000"&"101"&"000" when (min_wrd = '1') and (CNTS(8) = '0') and (CNTS(12) = '0') else
"101"&"000"&"101" when (min_wrd = '1') and (CNTS(8) = '0') and (CNTS(12) = '1') else
"000"&"000"&"101" when (min_wrd = '1') and (CNTS(8) = '1') else
"000"&"000"&"000";
rgb_hj <= "000"&"101"&"000" when (hr_wrj = '1') and (CNTS(7) = '0') and (CNTS(12) = '0') else
"101"&"000"&"101" when (hr_wrj = '1') and (CNTS(7) = '0') and (CNTS(12) = '1') else
"000"&"000"&"101" when (hr_wrj = '1') and (CNTS(7) = '1') else
"000"&"000"&"000";
rgb_hd <= "000"&"101"&"000" when (hr_wrd = '1') and (CNTS(6) = '0') and (CNTS(12) = '0') else
"101"&"000"&"101" when (hr_wrd = '1') and (CNTS(6) = '0') and (CNTS(12) = '1') else
"000"&"000"&"101" when (hr_wrd = '1') and (CNTS(6) = '1') else
"000"&"000"&"000";
-- pøi aktivním probliknutí se nezobrazí nic
rgbf <= "000"&"000"&"000" when BLINK(0) = '1' else
-- Tecka indikujici nastaveni alarmu:
"000"&"101"&"101" when (vga_row(11 downto 2) = "0000111011") and ((vga_col(9 downto 2)= "00011111")) and (CNTS(13) = '1') else
-- Dvojtecka mezi minutami a sekundami:
"101"&"000"&"000" when (vga_row(11 downto 3) = "000011101") and ((vga_col(8 downto 2) = "1011111")) else
"101"&"000"&"000" when (vga_row(11 downto 3) = "000011001") and ((vga_col(8 downto 2) = "1011111")) else
-- Dvojtecka mezi Hodinami a minutami:
"101"&"000"&"000" when (vga_row(11 downto 3) = "000011101") and ((vga_col(8 downto 2) = "0111111")) else
"101"&"000"&"000" when (vga_row(11 downto 3) = "000011001") and ((vga_col(8 downto 2) = "0111111")) else
-- Samotne cislice dle pozice na výstupu:
rgb_sj when (vga_row(11 downto 6) = "000011") and ((vga_col(8 downto 6) = "111")) else
rgb_sd when (vga_row(11 downto 6) = "000011") and ((vga_col(8 downto 6) = "110")) else
rgb_mj when (vga_row(11 downto 6) = "000011") and ((vga_col(8 downto 6) = "101")) else
rgb_md when (vga_row(11 downto 6) = "000011") and ((vga_col(8 downto 6) = "100")) else
rgb_hj when (vga_row(11 downto 6) = "000011") and ((vga_col(8 downto 6) = "011")) else
rgb_hd when (vga_row(11 downto 6) = "000011") and ((vga_col(8 downto 6) = "010")) else
"000"&"000"&"000";
red <= rgbf(8 downto 6);
green <= rgbf(5 downto 3);
blue <= rgbf(2 downto 0);
-- GENERATOR SEKUNDOVEHO SIGNALU
process (SMCLK)
begin
if (SMCLK'event) and (SMCLK = '1') then
sec <= '0';
-- nastavení blikání pøi aktivovaném budíku a pøi shodì hodin a minut
-- hodiny blikají minutu a nebo do zmáèknutí '#', '*' nebo 'A'
if ((cnt = period -1) or (cnt = period / 2)) then
if ((CNTS(13) = '1') and (cnt_hd = al_hd) and (cnt_hj = al_hj) and (cnt_md = al_md) and (cnt_mj = al_mj)) then
BLINK(1) <= '1';
else
BLINK(1) <= '0';
end if;
if (CNTS(6) = '1') then
BLINK(1) <= '0';
BLINK(0) <= '0';
elsif (BLINK(1) = '1') then
BLINK(0) <= not BLINK(0);
else
BLINK(0) <= '0';
end if;
end if;
if (cnt = period -1) then
cnt <= 0;
sec <= '1';
else
cnt <= cnt + 1;
end if;
end if;
end process;
-- GENERATOR MINUTOVEHO SIGNALU + nastaveni sekundovych pozic
process (SMCLK)
begin
if (SMCLK'event) and (SMCLK = '1') then
min <= '0';
if (CNTS(4) = '1') then
if (CNTS(12) = '1') then
al_sd <= value;
else
cnt_sd <= value;
end if;
elsif (CNTS(5) = '1') then
if (CNTS(12) = '1') then
al_sj <= value;
else
cnt_sj <= value;
end if;
end if;
if (sec = '1') then
if (cnt_sj = 9) and (cnt_sd = 5) then
cnt_sj <= 0;
cnt_sd <= 0;
min <= '1';
else
cnt_sj <= cnt_sj +1;
if (cnt_sj = 9) then
cnt_sj <= 0;
cnt_sd <= cnt_sd + 1;
end if;
end if;
end if;
end if;
end process;
-- GENERATOR HODINOVEHO SIGNALU + nastaveni minutových pozic
process (SMCLK)
begin
if (SMCLK'event) and (SMCLK = '1') then
hour <= '0';
if (CNTS(2) = '1') then
if (CNTS(12) = '1') then
al_md <= value;
else
cnt_md <= value;
end if;
elsif (CNTS(3) = '1') then
if (CNTS(12) = '1') then
al_mj <= value;
else
cnt_mj <= value;
end if;
end if;
if (min = '1') then
if (cnt_mj = 9) and (cnt_md = 5) then
cnt_mj <= 0;
cnt_md <= 0;
hour <= '1';
else
cnt_mj <= cnt_mj + 1;
if (cnt_mj = 9) then
cnt_mj <= 0;
cnt_md <= cnt_md + 1;
end if;
end if;
end if;
end if;
end process;
-- POCITADLO HODIN + nastaveni hodinových pozic
process (SMCLK)
begin
if (SMCLK'event) and (SMCLK = '1') then
if (CNTS(0) = '1') then
if (CNTS(12) = '1') then
al_hd <= value;
else
cnt_hd <= value;
end if;
elsif (CNTS(1) = '1') then
if (CNTS(12) = '1') then
al_hj <= value;
else
cnt_hj <= value;
end if;
end if;
if (hour = '1') then
if (cnt_hj = 3) and (cnt_hd = 2) then
cnt_hj <= 0;
cnt_hd <= 0;
else
cnt_hj <= cnt_hj + 1;
if (cnt_hj = 9) then
cnt_hj <= 0;
cnt_hd <= cnt_hd + 1;
end if;
end if;
end if;
end if;
end process;
end main;
-- KONEÈNÝ AUTOMAT
-- pùvodní verze neobsahovala stavy AL_..., nastavování budíku probíhalo pøes stejné stavy jako u hodin,
-- jen se pøedem nastavil CNTS(12) na '1' + pomocný signál alarm takté na '1', ale bohue se oba tyto signály
-- ihned nulovaly a nebylo moné identifikovat nastavování alarmu (nepøili jsme na pùvod tohoto chování).
-- Proto je pouíto více stavù ne by bylo potøeba + po pøechodu do nastavení hodin se budík automaticky
-- vypne a je nutno jej znovu zapnout po nastavení hodin.
-- Testování na hodnotu signálu alarm jsme zachovali pro pøedstavu pùvodního návrhu.
architecture behavioral of fsm is
-- funkce pro pøevod hodnoty vektoru klávesnice na hodnotu zmáèklé klávesy
function log2(val : integer) return natural is
variable result : natural;
begin
for i in 0 to 31 loop
if (val <= (2 ** i)) then
result := i;
exit;
end if;
end loop;
return result;
end function;
type t_state is (Hour2, Hour11, Hour12, Min2, Min1, Sec2, Sec1, IDLE, IDLE2,
AL_Hour2, AL_Hour11, AL_Hour12, AL_Min2, AL_Min1, AL_Sec2, AL_Sec1);
signal present_state, next_state: t_state;
signal tmp: integer;
signal alarm: std_logic;
begin
sync_logic : process(CLK)
begin
if (RESET = '1') then
present_state <= IDLE;
elsif (CLK'event AND CLK = '1') then
present_state <= next_state;
end if;
end process sync_logic;
next_state_logic : process(present_state, KEY)
begin
case (present_state) is
---------------------------------------------
when Hour2 =>
next_state <= Hour2;
if (KEY(1 downto 0) /= "00") then
next_state <= Hour11;
elsif (KEY(2) = '1') then
next_state <= Hour12;
elsif (KEY(15) = '1') then
if (alarm = '1') then
next_state <= IDLE2;
else
next_state <= IDLE;
end if;
end if;
---------------------------------------------
when Hour11 =>
next_state <= Hour11;
if (KEY(9 downto 0) /= "0000000000") then
next_state <= Min2;
elsif (KEY(15) = '1') then
if (alarm = '1') then
next_state <= IDLE2;
else
next_state <= IDLE;
end if;
end if;
---------------------------------------------
when Hour12 =>
next_state <= Hour12;
if (KEY(3 downto 0) /= "0000") then
next_state <= Min2;
elsif (KEY(15) = '1') then
if (alarm = '1') then
next_state <= IDLE2;
else
next_state <= IDLE;
end if;
end if;
---------------------------------------------
when Min2 =>
next_state <= Min2;
if (KEY(5 downto 0) /= "000000") then
next_state <= Min1;
elsif (KEY(15) = '1') then
if (alarm = '1') then
next_state <= IDLE2;
else
next_state <= IDLE;
end if;
end if;
---------------------------------------------
when Min1 =>
next_state <= Min1;
if (KEY(9 downto 0) /= "0000000000") then
next_state <= Sec2;
elsif (KEY(15) = '1') then
if (alarm = '1') then
next_state <= IDLE2;
else
next_state <= IDLE;
end if;
end if;
---------------------------------------------
when Sec2 =>
next_state <= Sec2;
if (KEY(5 downto 0) /= "000000") then
next_state <= Sec1;
elsif (KEY(15) = '1') then
if (alarm = '1') then
next_state <= IDLE2;
else
next_state <= IDLE;
end if;
end if;
---------------------------------------------
when Sec1 =>
next_state <= Sec1;
if (KEY(9 downto 0) /= "0000000000") then
next_state <= Hour2;
elsif (KEY(15) = '1') then
if (alarm = '1') then
next_state <= IDLE2;
else
next_state <= IDLE;
end if;
end if;
---------------------------------------------
when AL_Hour2 =>
next_state <= AL_Hour2;
if (KEY(1 downto 0) /= "00") then
next_state <= AL_Hour11;
elsif (KEY(2) = '1') then
next_state <= AL_Hour12;
elsif (KEY(15) = '1') then
next_state <= IDLE2;
end if;
---------------------------------------------
when AL_Hour11 =>
next_state <= AL_Hour11;
if (KEY(9 downto 0) /= "0000000000") then
next_state <= AL_Min2;
elsif (KEY(15) = '1') then
next_state <= IDLE2;
end if;
---------------------------------------------
when AL_Hour12 =>
next_state <= AL_Hour12;
if (KEY(3 downto 0) /= "0000") then
next_state <= AL_Min2;
elsif (KEY(15) = '1') then
next_state <= IDLE2;
end if;
---------------------------------------------
when AL_Min2 =>
next_state <= AL_Min2;
if (KEY(5 downto 0) /= "000000") then
next_state <= AL_Min1;
elsif (KEY(15) = '1') then
next_state <= IDLE2;
end if;
---------------------------------------------
when AL_Min1 =>
next_state <= AL_Min1;
if (KEY(9 downto 0) /= "0000000000") then
next_state <= AL_Sec2;
elsif (KEY(15) = '1') then
next_state <= IDLE2;
end if;
---------------------------------------------
when AL_Sec2 =>
next_state <= AL_Sec2;
if (KEY(5 downto 0) /= "000000") then
next_state <= AL_Sec1;
elsif (KEY(15) = '1') then
next_state <= IDLE2;
end if;
---------------------------------------------
when AL_Sec1 =>
next_state <= AL_Sec1;
if (KEY(9 downto 0) /= "0000000000") then
next_state <= AL_Hour2;
elsif (KEY(15) = '1') then
next_state <= IDLE2;
end if;
---------------------------------------------
when IDLE =>
next_state <= IDLE;
if (KEY(15) = '1') then
next_state <= Hour2;
elsif (KEY(10) = '1') then
next_state <= IDLE2;
elsif (KEY(14) = '1') then
next_state <= AL_Hour2;
end if;
---------------------------------------------
when IDLE2 =>
next_state <= IDLE2;
if (KEY(15) = '1') then
next_state <= Hour2;
elsif (KEY(10) = '1') then
next_state <= IDLE;
elsif (KEY(14) = '1') then
next_state <= AL_Hour2;
end if;
---------------------------------------------
when others =>
end case;
end process next_state_logic;
output_logic : process(present_state, KEY)
begin
tmp <= log2(conv_integer(KEY(9 downto 0)));
case (present_state) is
---------------------------------------------
when Hour2 | AL_Hour2 =>
if (present_state = AL_Hour2) then
CNTS(13) <= '1';
CNTS(12) <= '1';
alarm <= '1';
end if;
CNTS(6) <= '1';
if (KEY(2 downto 0) /= "000") then
CNTS(6) <= '0';
CNTS(5) <= '0';
CNTS(0) <= '1';
value <= tmp;
end if;
---------------------------------------------
when Hour11 | AL_Hour11 =>
if (present_state = AL_Hour11) then
CNTS(13) <= '1';
CNTS(12) <= '1';
alarm <= '1';
end if;
CNTS(7) <= '1';
if (KEY(9 downto 0) /= "0000000000") then
CNTS(7) <= '0';
CNTS(0) <= '0';
CNTS(1) <= '1';
value <= tmp;
end if;
---------------------------------------------
when Hour12 | AL_Hour12 =>
if (present_state = AL_Hour12) then
CNTS(13) <= '1';
CNTS(12) <= '1';
alarm <= '1';
end if;
CNTS(7) <= '1';
if (KEY(3 downto 0) /= "0000") then
CNTS(7) <= '0';
CNTS(0) <= '0';
CNTS(1) <= '1';
value <= tmp;
end if;
---------------------------------------------
when Min2 | AL_Min2 =>
if (present_state = AL_Min2) then
CNTS(13) <= '1';
CNTS(12) <= '1';
alarm <= '1';
end if;
CNTS(8) <= '1';
if (KEY(5 downto 0) /= "000000") then
CNTS(8) <= '0';
CNTS(1) <= '0';
CNTS(2) <= '1';
value <= tmp;
end if;
---------------------------------------------
when Min1 | AL_Min1 =>
if (present_state = AL_Min1) then
CNTS(13) <= '1';
CNTS(12) <= '1';
alarm <= '1';
end if;
CNTS(9) <= '1';
if (KEY(9 downto 0) /= "0000000000") then
CNTS(9) <= '0';
CNTS(2) <= '0';
CNTS(3) <= '1';
value <= tmp;
end if;
---------------------------------------------
when Sec2 | AL_Sec2 =>
if (present_state = AL_Sec2) then
CNTS(13) <= '1';
CNTS(12) <= '1';
alarm <= '1';
end if;
CNTS(10) <= '1';
if (KEY(5 downto 0) /= "000000") then
CNTS(10) <= '0';
CNTS(3) <= '0';
CNTS(4) <= '1';
value <= tmp;
end if;
---------------------------------------------
when Sec1 | AL_Sec1 =>
if (present_state = AL_Sec1) then
CNTS(13) <= '1';
CNTS(12) <= '1';
alarm <= '1';
end if;
CNTS(11) <= '1';
if (KEY(9 downto 0) /= "0000000000") then
CNTS(11) <= '0';
CNTS(4) <= '0';
CNTS(5) <= '1';
value <= tmp;
end if;
---------------------------------------------
when IDLE =>
CNTS(13 downto 0) <= "00000000000000";
alarm <= '0';
if (KEY(14) = '1') then
CNTS(12) <= '1';
CNTS(13) <= '1';
alarm <= '1';
end if;
---------------------------------------------
when IDLE2 =>
CNTS(13 downto 0) <= "10000000000000";
alarm <= '1';
if (KEY(14) = '1') then
CNTS(12) <= '1';
end if;
---------------------------------------------
when others =>
end case;
end process output_logic;
end architecture behavioral;
|
mit
|
danielfpedro/mock-bs
|
js/vendor/ace-builds/demo/kitchen-sink/docs/vhdl.vhd
|
472
|
830
|
library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
|
mit
|
agural/AVR-Processor
|
src/AVR/ALUCommands.vhd
|
1
|
3973
|
-----------------------------------------------------------------------------
--
-- AVR opcode package
--
-- This package defines opcode constants for the complete AVR instruction
-- set. Not all variants of the AVR implement all instructions.
--
-- Revision History
-- 4/27/98 Glen George initial revision
-- 4/14/00 Glen George updated comments
-- 4/22/02 Glen George added new instructions
-- 4/22/02 Glen George updated comments
-- 5/16/02 Glen George fixed LPM instruction constant
--
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package ALUCommands is
-- ALU Blocks for ALUBlockSel
constant ALUAddBlock : std_logic_vector(1 downto 0) := "00";
constant ALUFBlock : std_logic_vector(1 downto 0) := "01";
constant ALUShiftBlock : std_logic_vector(1 downto 0) := "10";
constant ALUMulBlock : std_logic_vector(1 downto 0) := "11";
-- ALU Block Instructions for BlockInstructionSel
--F Block
constant FBlockZERO : std_logic_vector(3 downto 0) := "0000";
constant FBlockNOR : std_logic_vector(3 downto 0) := "0001";
constant FBlockNOTA : std_logic_vector(3 downto 0) := "0011";
constant FBlockNOTB : std_logic_vector(3 downto 0) := "0101";
constant FBlockXOR : std_logic_vector(3 downto 0) := "0110";
constant FBlockNAND : std_logic_vector(3 downto 0) := "0111";
constant FBlockAND : std_logic_vector(3 downto 0) := "1000";
constant FBlockXNOR : std_logic_vector(3 downto 0) := "1001";
constant FBlockOR : std_logic_vector(3 downto 0) := "1110";
constant FBlockONE : std_logic_vector(3 downto 0) := "1111";
--Shift Block
--bit 2 - shift 1 vs shift 4
--bit 1:0 - high bit source: 00 => 0, 01 => A0, 10 => An
constant ShiftBlockArith : std_logic_vector(3 downto 0) := "0010";
constant ShiftBlockLog : std_logic_vector(3 downto 0) := "0000";
constant ShiftBlockRot : std_logic_vector(3 downto 0) := "0001";
constant ShiftBlockSwap : std_logic_vector(3 downto 0) := "0100";
--Add Block
constant AddBlockAdd : std_logic_vector(3 downto 0) := "0000";
constant AddBlockSub : std_logic_vector(3 downto 0) := "0010";
constant AddBlockAddCarry : std_logic_vector(3 downto 0) := "0001";
constant AddBlockSubCarry : std_logic_vector(3 downto 0) := "0011";
constant AddBlockNeg : std_logic_vector(3 downto 0) := "0100";
--Multiply Block
constant MulBlockLowByte : std_logic_vector(3 downto 0) := "0000";
constant MulBlockHighByte : std_logic_vector(3 downto 0) := "0001";
-- ALU Flags
constant flag_C : integer := 0;
constant flag_Z : integer := 1;
constant flag_N : integer := 2;
constant flag_V : integer := 3;
constant flag_S : integer := 4;
constant flag_H : integer := 5;
constant flag_T : integer := 6;
constant flag_I : integer := 7;
-- ALU Flag Masks ITHSVNZC
constant flag_mask_ZCNVSH : std_logic_vector(7 downto 0) := "00111111";
constant flag_mask_ZCNVS : std_logic_vector(7 downto 0) := "00011111";
constant flag_mask_ZNVS : std_logic_vector(7 downto 0) := "00011110";
constant flag_mask_T : std_logic_vector(7 downto 0) := "01000000";
constant flag_mask_ZC : std_logic_vector(7 downto 0) := "00000011";
constant flag_mask_KEEPALL: std_logic_vector(7 downto 0) := "00000000";
-- ALU Operand 2 Select (ALUOp2Sel) Values
constant RegOp2 : std_logic := '0'; --Operand 2 is from registers
constant ImmedOp2 : std_logic := '1'; --Operand 2 is immediate
constant StatusBitClear : std_logic := '0';
constant StatusBitSet : std_logic := '1';
end package;
|
mit
|
agural/AVR-Processor
|
src/AVR/PMAUnit.vhd
|
1
|
3041
|
----------------------------------------------------------------------------------
-- Company: Caltech EE 119B
-- Engineer: Albert Gural and Bryan He
--
-- Design Name: AVR-Processor
-- Module Name: PMAUnit - DataFlow
-- Project Name: AVR-Processor
-- Target Devices: Xilinx Spartan III XC3S1200EFGG3204C
-- Tool versions: Xilinx ISE 14.7
-- Description: Keeps an updated program counter (PC) and is responsible for
-- fetching new instructions.
--
-- Revision: 1.0
-- For file history, see https://github.com/agural/AVR-Processor
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity PMAUnit is
port (
ProgAB : out std_logic_vector(15 downto 0); -- address for program memory
ProgDB : in std_logic_vector(15 downto 0); -- data from program memory
PCUpdateSel : in std_logic_vector( 1 downto 0); -- source of next program counter
NextPC : out std_logic_vector(15 downto 0); -- next program counter
PCOffset : in std_logic_vector(11 downto 0); -- increment for program counter
NewIns : in std_logic; -- indicates new instruction should be loaded
IR : out std_logic_vector(15 downto 0); -- instruction register
NewPCZ : in std_logic_vector(15 downto 0); -- from Z register
NewPCS : in std_logic_vector(15 downto 0); -- from stack
Reset : in std_logic; -- reset
Clk : in std_logic -- system clock
);
end PMAUnit;
architecture DataFlow of PMAUnit is
signal PC : std_logic_vector(15 downto 0);
signal IncrementedPC : std_logic_vector(15 downto 0);
constant ResetValue : std_logic_vector(15 downto 0) := (others => '0');
begin
ProgAB <= PC;
IncrementedPC <= std_logic_vector(signed(PC) + signed(PCOffset));
NextPC <= IncrementedPC;
process (Clk)
begin
if (rising_edge(Clk)) then
if (NewIns = '1') then
IR <= ProgDB;
end if;
if (PCUpdateSel = "00") then
PC <= IncrementedPC;
elsif (PCUpdateSel = "01") then
PC <= ProgDB;
elsif (PCUpdateSel = "10") then
PC <= NewPCZ;
elsif (PCUpdateSel = "11") then
PC <= NewPCS;
else
PC <= (others => 'X');
end if;
if (Reset = '0') then
PC <= ResetValue;
end if;
end if;
end process;
end DataFlow;
|
mit
|
elainemielas/CVUT_BI-PNO
|
project2/receiver.vhd
|
1
|
8066
|
library IEEE;
use IEEE.std_logic_1164.all;
entity RECEIVER is
port (
PS2_DATA : in std_logic; -- serial PS2 input
PS2_CLK : in std_logic; -- serial PS2 clock
CLK : in std_logic; -- standard 50MHz clock
RESET : in std_logic;
SCAN_CODE : out std_logic_vector ( 7 downto 0 );
NEW_SC : out std_logic
);
end RECEIVER;
architecture RECEIVER_BODY of RECEIVER is
type T_STATE is ( W_START, R_START, W_0, R_0, W_1, R_1, W_2, R_2, W_3, R_3, W_4, R_4, W_5, R_5, W_6, R_6, W_7, R_7, W_PAR, R_PAR, W_END, R_END, VALID );
signal STATE, NEXT_STATE : T_STATE;
signal PAR, PS2_PAR, PS2_END : std_logic;
signal SC : std_logic_vector ( 7 downto 0 );
signal SC_LOAD : std_logic;
signal SC_RESET : std_logic;
signal PAR_LOAD : std_logic;
signal END_LOAD : std_logic;
signal SC_OUT : std_logic;
begin
SCPR : process ( CLK )
begin
if CLK = '1' and CLK'event then
if RESET = '1' then
SC <= "00000000";
elsif SC_LOAD = '1' then
SC <= PS2_DATA & SC ( 7 downto 1 ) ;
end if;
end if;
end process;
PARPR : process ( CLK )
begin
if CLK = '1' and CLK'event then
if RESET = '1' or SC_RESET = '1' then
PAR <= '1';
elsif SC_LOAD = '1' then
if PS2_DATA = '1' then
PAR <= not PAR;
else
PAR <= PAR;
end if;
end if;
end if;
end process;
PS2_PARPR : process ( CLK )
begin
if CLK = '1' and CLK'event then
if RESET = '1' or SC_RESET = '1' then
PS2_PAR <= '0';
elsif PAR_LOAD = '1' then
PS2_PAR <= PS2_DATA;
else
PS2_PAR <= PS2_PAR;
end if;
end if;
end process;
ENDPR : process ( CLK )
begin
if CLK = '1' and CLK'event then
if RESET = '1' or SC_RESET = '1' then
PS2_END <= '0';
elsif END_LOAD = '1' then
PS2_END <= PS2_DATA;
else
PS2_END <= PS2_END;
end if;
end if;
end process;
SC_OUT_PR : process ( CLK )
begin
if CLK = '1' and CLK'event then
if RESET = '1' then
SCAN_CODE <= "00000000";
elsif SC_OUT = '1' then
SCAN_CODE <= SC;
end if;
end if;
end process;
TRANP : process ( STATE, PS2_DATA, PS2_CLK, PAR, PS2_PAR, PS2_END )
begin
case STATE is
when W_START => if PS2_CLK = '1' then
NEXT_STATE <= W_START;
else
NEXT_STATE <= R_START;
end if;
when R_START => if PS2_CLK = '0' then
NEXT_STATE <= R_START;
else
NEXT_STATE <= W_0;
end if;
when W_0 => if PS2_CLK = '1' then
NEXT_STATE <= W_0;
else
NEXT_STATE <= R_0;
end if;
when R_0 => if PS2_CLK = '0' then
NEXT_STATE <= R_0;
else
NEXT_STATE <= W_1;
end if;
when W_1 => if PS2_CLK = '1' then
NEXT_STATE <= W_1;
else
NEXT_STATE <= R_1;
end if;
when R_1 => if PS2_CLK = '0' then
NEXT_STATE <= R_1;
else
NEXT_STATE <= W_2;
end if;
when W_2 => if PS2_CLK = '1' then
NEXT_STATE <= W_2;
else
NEXT_STATE <= R_2;
end if;
when R_2 => if PS2_CLK = '0' then
NEXT_STATE <= R_2;
else
NEXT_STATE <= W_3;
end if;
when W_3 => if PS2_CLK = '1' then
NEXT_STATE <= W_3;
else
NEXT_STATE <= R_3;
end if;
when R_3 => if PS2_CLK = '0' then
NEXT_STATE <= R_3;
else
NEXT_STATE <= W_4;
end if;
when W_4 => if PS2_CLK = '1' then
NEXT_STATE <= W_4;
else
NEXT_STATE <= R_4;
end if;
when R_4 => if PS2_CLK = '0' then
NEXT_STATE <= R_4;
else
NEXT_STATE <= W_5;
end if;
when W_5 => if PS2_CLK = '1' then
NEXT_STATE <= W_5;
else
NEXT_STATE <= R_5;
end if;
when R_5 => if PS2_CLK = '0' then
NEXT_STATE <= R_5;
else
NEXT_STATE <= W_6;
end if;
when W_6 => if PS2_CLK = '1' then
NEXT_STATE <= W_6;
else
NEXT_STATE <= R_6;
end if;
when R_6 => if PS2_CLK = '0' then
NEXT_STATE <= R_6;
else
NEXT_STATE <= W_7;
end if;
when W_7 => if PS2_CLK = '1' then
NEXT_STATE <= W_7;
else
NEXT_STATE <= R_7;
end if;
when R_7 => if PS2_CLK = '0' then
NEXT_STATE <= R_7;
else
NEXT_STATE <= W_PAR;
end if;
when W_PAR => if PS2_CLK = '1' then
NEXT_STATE <= W_PAR;
else
NEXT_STATE <= R_PAR;
end if;
when R_PAR => if PS2_CLK = '0' then
NEXT_STATE <= R_PAR;
else
NEXT_STATE <= W_END;
end if;
when W_END => if PS2_CLK = '1' then
NEXT_STATE <= W_END;
else
NEXT_STATE <= R_END;
end if;
when R_END => if PS2_CLK = '0' then
NEXT_STATE <= R_END;
else
if PAR = PS2_PAR and PS2_END = '1' then
NEXT_STATE <= VALID;
else
NEXT_STATE <= W_START;
end if;
end if;
when VALID => NEXT_STATE <= W_START;
end case;
end process;
STATEP : process ( CLK )
begin
if CLK = '1' and CLK'event then
if RESET = '1' then
STATE <= W_START;
else
STATE <= NEXT_STATE;
end if;
end if;
end process;
OUTP : process ( STATE, PS2_DATA, PS2_CLK, PAR, PS2_PAR, PS2_END, SC )
begin
case STATE is
when W_START => NEW_SC <= '0';
SC_LOAD <= '0';
SC_RESET <= '0';
PAR_LOAD <= '0';
END_LOAD <= '0';
SC_OUT <= '0';
when R_START => NEW_SC <= '0';
SC_LOAD <= '0';
SC_RESET <= '1';
PAR_LOAD <= '0';
END_LOAD <= '0';
SC_OUT <= '0';
when W_0 | W_1 | W_2 | W_3 | W_4 | W_5 | W_6 | W_7 => if PS2_CLK = '0' then
SC_LOAD <= '1';
else
SC_LOAD <= '0';
end if;
NEW_SC <= '0';
SC_RESET <= '0';
PAR_LOAD <= '0';
END_LOAD <= '0';
SC_OUT <= '0';
when W_PAR => if PS2_CLK = '0' then
PAR_LOAD <= '1';
else
PAR_LOAD <= '0';
end if;
NEW_SC <= '0';
SC_LOAD <= '0';
SC_RESET <= '0';
END_LOAD <= '0';
SC_OUT <= '0';
when W_END => if PS2_CLK = '0' then
END_LOAD <= '1';
else
END_LOAD <= '0';
end if;
NEW_SC <= '0';
SC_LOAD <= '0';
SC_RESET <= '0';
PAR_LOAD <= '0';
SC_OUT <= '0';
when R_END => if PS2_CLK = '1' and PAR = PS2_PAR and PS2_END = '1' then
SC_OUT <= '1';
else
SC_OUT <= '0';
end if;
NEW_SC <= '0';
SC_LOAD <= '0';
SC_RESET <= '0';
PAR_LOAD <= '0';
END_LOAD <= '0';
when VALID => NEW_SC <= '1';
SC_LOAD <= '0';
SC_RESET <= '0';
PAR_LOAD <= '0';
END_LOAD <= '0';
SC_OUT <= '0';
when others => NEW_SC <= '0';
SC_LOAD <= '0';
SC_RESET <= '0';
PAR_LOAD <= '0';
END_LOAD <= '0';
SC_OUT <= '0';
end case;
end process;
end RECEIVER_BODY;
|
mit
|
AndyMcC0/UVVM_All
|
bitvis_vip_uart/src/uart_vvc.vhd
|
3
|
3798
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
use work.uart_bfm_pkg.all;
use work.vvc_cmd_pkg.all;
--=================================================================================================
entity uart_vvc is
generic (
GC_DATA_WIDTH : natural range 1 to C_VVC_CMD_DATA_MAX_LENGTH := 8;
GC_INSTANCE_IDX : natural := 1;
GC_UART_CONFIG : t_uart_bfm_config := C_UART_BFM_CONFIG_DEFAULT;
GC_CMD_QUEUE_COUNT_MAX : natural := 1000;
GC_CMD_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING
);
port (
uart_vvc_rx : in std_logic;
uart_vvc_tx : inout std_logic
);
end entity uart_vvc;
--=================================================================================================
--=================================================================================================
architecture struct of uart_vvc is
begin
-- UART RX VVC
i1_uart_rx: entity work.uart_rx_vvc
generic map(
GC_DATA_WIDTH => GC_DATA_WIDTH,
GC_INSTANCE_IDX => GC_INSTANCE_IDX,
GC_CHANNEL => RX,
GC_UART_CONFIG => GC_UART_CONFIG,
GC_CMD_QUEUE_COUNT_MAX => GC_CMD_QUEUE_COUNT_MAX,
GC_CMD_QUEUE_COUNT_THRESHOLD => GC_CMD_QUEUE_COUNT_THRESHOLD,
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY => GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY
)
port map(
uart_vvc_rx => uart_vvc_rx
);
-- UART TX VVC
i1_uart_tx: entity work.uart_tx_vvc
generic map(
GC_DATA_WIDTH => GC_DATA_WIDTH,
GC_INSTANCE_IDX => GC_INSTANCE_IDX,
GC_CHANNEL => TX,
GC_UART_CONFIG => GC_UART_CONFIG,
GC_CMD_QUEUE_COUNT_MAX => GC_CMD_QUEUE_COUNT_MAX,
GC_CMD_QUEUE_COUNT_THRESHOLD => GC_CMD_QUEUE_COUNT_THRESHOLD,
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY => GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY
)
port map(
uart_vvc_tx => uart_vvc_tx
);
end struct;
|
mit
|
AndyMcC0/UVVM_All
|
bitvis_vip_axilite/src/axilite_bfm_pkg.vhd
|
1
|
28141
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
--=================================================================================================
package axilite_bfm_pkg is
--===============================================================================================
-- Types and constants for AXILITE BFMs
--===============================================================================================
constant C_SCOPE : string := "AXILITE BFM";
type t_axilite_response_status is (OKAY, SLVERR, DECERR, EXOKAY); -- EXOKAY not supported for AXI-Lite, will raise TB_FAILURE
type t_axilite_protection is(
UNPRIVILIGED_UNSECURE_DATA,
UNPRIVILIGED_UNSECURE_INSTRUCTION,
UNPRIVILIGED_SECURE_DATA,
UNPRIVILIGED_SECURE_INSTRUCTION,
PRIVILIGED_UNSECURE_DATA,
PRIVILIGED_UNSECURE_INSTRUCTION,
PRIVILIGED_SECURE_DATA,
PRIVILIGED_SECURE_INSTRUCTION
);
-- Configuration record to be assigned in the test harness.
type t_axilite_bfm_config is
record
max_wait_cycles : natural; -- Used for setting the maximum cycles to wait before an alert is issued when waiting for ready and valid signals from the DUT.
max_wait_cycles_severity : t_alert_level; -- The above timeout will have this severity
clock_period : time; -- Period of the clock signal.
expected_response : t_axilite_response_status; -- Sets the expected response for both read and write transactions.
expected_response_severity : t_alert_level; -- A response mismatch will have this severity.
protection_setting : t_axilite_protection; -- Sets the AXI access permissions (e.g. write to data/instruction, privileged and secure access).
num_aw_pipe_stages : natural; -- Write Address Channel pipeline steps.
num_w_pipe_stages : natural; -- Write Data Channel pipeline steps.
num_ar_pipe_stages : natural; -- Read Address Channel pipeline steps.
num_r_pipe_stages : natural; -- Read Data Channel pipeline steps.
num_b_pipe_stages : natural; -- Response Channel pipeline steps.
id_for_bfm : t_msg_id; -- The message ID used as a general message ID in the AXI-Lite BFM
id_for_bfm_wait : t_msg_id; -- The message ID used for logging waits in the AXI-Lite BFM
id_for_bfm_poll : t_msg_id; -- The message ID used for logging polling in the AXI-Lite BFM
end record;
constant C_AXILITE_BFM_CONFIG_DEFAULT : t_axilite_bfm_config := (
max_wait_cycles => 10,
max_wait_cycles_severity => TB_FAILURE,
clock_period => 10 ns,
expected_response => OKAY,
expected_response_severity => TB_FAILURE,
protection_setting => UNPRIVILIGED_UNSECURE_DATA,
num_aw_pipe_stages => 1,
num_w_pipe_stages => 1,
num_ar_pipe_stages => 1,
num_r_pipe_stages => 1,
num_b_pipe_stages => 1,
id_for_bfm => ID_BFM,
id_for_bfm_wait => ID_BFM_WAIT,
id_for_bfm_poll => ID_BFM_POLL
);
-- AXI-Lite Interface signals
type t_axilite_write_address_channel is record
--DUT inputs
awaddr : std_logic_vector;
awvalid : std_logic;
awprot : std_logic_vector(2 downto 0); -- [0: '0' - unpriviliged access, '1' - priviliged access; 1: '0' - secure access, '1' - non-secure access, 2: '0' - Data access, '1' - Instruction accesss]
--DUT outputs
awready : std_logic;
end record;
type t_axilite_write_data_channel is record
--DUT inputs
wdata : std_logic_vector;
wstrb : std_logic_vector;
wvalid : std_logic;
--DUT outputs
wready : std_logic;
end record;
type t_axilite_write_response_channel is record
--DUT inputs
bready : std_logic;
--DUT outputs
bresp : std_logic_vector(1 downto 0);
bvalid : std_logic;
end record;
type t_axilite_read_address_channel is record
--DUT inputs
araddr : std_logic_vector;
arvalid : std_logic;
arprot : std_logic_vector(2 downto 0); -- [0: '0' - unpriviliged access, '1' - priviliged access; 1: '0' - secure access, '1' - non-secure access, 2: '0' - Data access, '1' - Instruction accesss]
--DUT outputs
arready : std_logic;
end record;
type t_axilite_read_data_channel is record
--DUT inputs
rready : std_logic;
--DUT outputs
rdata : std_logic_vector;
rresp : std_logic_vector(1 downto 0);
rvalid : std_logic;
end record;
type t_axilite_if is record
write_address_channel : t_axilite_write_address_channel;
write_data_channel : t_axilite_write_data_channel;
write_response_channel : t_axilite_write_response_channel;
read_address_channel : t_axilite_read_address_channel;
read_data_channel : t_axilite_read_data_channel;
end record;
--===============================================================================================
-- BFM procedures
--===============================================================================================
------------------------------------------
-- init_axilite_if_signals
------------------------------------------
-- - This function returns an AXILITE interface with initialized signals.
-- - All AXILITE input signals are initialized to 0
-- - All AXILITE output signals are initialized to Z
-- - awprot and arprot are initialized to UNPRIVILIGED_UNSECURE_DATA
function init_axilite_if_signals(
addr_width : natural;
data_width : natural
) return t_axilite_if;
------------------------------------------
-- axilite_write
------------------------------------------
-- This procedure writes data to the AXILITE interface specified in axilite_if
-- - The protection setting is set to UNPRIVILIGED_UNSECURE_DATA in this procedure
-- - The byte enable input is set to 1 for all bytes in this procedure
-- - When the write is completed, a log message is issued with log ID id_for_bfm
procedure axilite_write (
constant addr_value : in unsigned;
constant data_value : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal axilite_if : inout t_axilite_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axilite_bfm_config := C_AXILITE_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- axilite_write
------------------------------------------
-- This procedure writes data to the AXILITE interface specified in axilite_if
-- - When the write is completed, a log message is issued with log ID id_for_bfm
procedure axilite_write (
constant addr_value : in unsigned;
constant data_value : in std_logic_vector;
constant byte_enable : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal axilite_if : inout t_axilite_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axilite_bfm_config := C_AXILITE_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- axilite_read
------------------------------------------
-- This procedure reads data from the AXILITE interface specified in axilite_if,
-- and returns the read data in data_value.
procedure axilite_read (
constant addr_value : in unsigned;
variable data_value : out std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal axilite_if : inout t_axilite_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axilite_bfm_config := C_AXILITE_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like axilite_check
);
------------------------------------------
-- axilite_check
------------------------------------------
-- This procedure reads data from the AXILITE interface specified in axilite_if,
-- and compares it to the data in data_exp.
-- - If the received data inconsistent with data_exp, an alert with severity
-- alert_level is issued.
-- - If the received data was correct, a log message with ID id_for_bfm is issued.
procedure axilite_check (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal axilite_if : inout t_axilite_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axilite_bfm_config := C_AXILITE_BFM_CONFIG_DEFAULT
);
end package axilite_bfm_pkg;
--=================================================================================================
--=================================================================================================
package body axilite_bfm_pkg is
----------------------------------------------------
-- Support procedures
----------------------------------------------------
function to_slv(
protection : t_axilite_protection
) return std_logic_vector is
variable v_prot_slv : std_logic_vector(2 downto 0);
begin
case protection is
when UNPRIVILIGED_UNSECURE_DATA =>
v_prot_slv := "010";
when UNPRIVILIGED_UNSECURE_INSTRUCTION =>
v_prot_slv := "011";
when UNPRIVILIGED_SECURE_DATA =>
v_prot_slv := "000";
when UNPRIVILIGED_SECURE_INSTRUCTION =>
v_prot_slv := "001";
when PRIVILIGED_UNSECURE_DATA =>
v_prot_slv := "110";
when PRIVILIGED_UNSECURE_INSTRUCTION =>
v_prot_slv := "111";
when PRIVILIGED_SECURE_DATA =>
v_prot_slv := "100";
when PRIVILIGED_SECURE_INSTRUCTION =>
v_prot_slv := "101";
end case;
return v_prot_slv;
end function;
function to_slv(
axilite_response_status : t_axilite_response_status;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel
) return std_logic_vector is
variable v_axilite_response_status_slv : std_logic_vector(1 downto 0);
begin
check_value(axilite_response_status /= EXOKAY, TB_FAILURE, "EXOKAY response status is not supported in AXI-Lite", scope, ID_NEVER, msg_id_panel);
case axilite_response_status is
when OKAY =>
v_axilite_response_status_slv := "00";
when SLVERR =>
v_axilite_response_status_slv := "10";
when DECERR =>
v_axilite_response_status_slv := "11";
when EXOKAY =>
v_axilite_response_status_slv := "01";
end case;
return v_axilite_response_status_slv;
end function;
function to_axilite_response_status(
resp : std_logic_vector(1 downto 0);
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel
) return t_axilite_response_status is
begin
check_value(resp /= "01", TB_FAILURE, "EXOKAY response status is not supported in AXI-Lite", scope, ID_NEVER, msg_id_panel);
case resp is
when "00" =>
return OKAY;
when "10" =>
return SLVERR;
when "11" =>
return DECERR;
when others =>
return EXOKAY;
end case;
end function;
----------------------------------------------------
-- BFM procedures
----------------------------------------------------
function init_axilite_if_signals(
addr_width : natural;
data_width : natural
) return t_axilite_if is
variable init_if : t_axilite_if( write_address_channel( awaddr( addr_width -1 downto 0)),
write_data_channel( wdata( data_width -1 downto 0),
wstrb(( data_width/8) -1 downto 0)),
read_address_channel( araddr( addr_width -1 downto 0)),
read_data_channel( rdata( data_width -1 downto 0)));
begin
-- Write Address Channel
init_if.write_address_channel.awaddr := (init_if.write_address_channel.awaddr'range => '0');
init_if.write_address_channel.awvalid := '0';
init_if.write_address_channel.awprot := to_slv(UNPRIVILIGED_UNSECURE_DATA); --"010"
init_if.write_address_channel.awready := 'Z';
-- Write Data Channel
init_if.write_data_channel.wdata := (init_if.write_data_channel.wdata'range => '0');
init_if.write_data_channel.wstrb := (init_if.write_data_channel.wstrb'range => '0');
init_if.write_data_channel.wvalid := '0';
init_if.write_data_channel.wready := 'Z';
-- Write Response Channel
init_if.write_response_channel.bready := '0';
init_if.write_response_channel.bresp := (init_if.write_response_channel.bresp'range => 'Z');
init_if.write_response_channel.bvalid := 'Z';
-- Read Address Channel
init_if.read_address_channel.araddr := (init_if.read_address_channel.araddr'range => '0');
init_if.read_address_channel.arvalid := '0';
init_if.read_address_channel.arprot := to_slv(UNPRIVILIGED_UNSECURE_DATA); --"010"
init_if.read_address_channel.arready := 'Z';
-- Read Data Channel
init_if.read_data_channel.rready := '0';
init_if.read_data_channel.rdata := (init_if.read_data_channel.rdata'range => 'Z');
init_if.read_data_channel.rresp := (init_if.read_data_channel.rresp'range => 'Z');
init_if.read_data_channel.rvalid := 'Z';
return init_if;
end function;
procedure axilite_write (
constant addr_value : in unsigned;
constant data_value : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal axilite_if : inout t_axilite_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axilite_bfm_config := C_AXILITE_BFM_CONFIG_DEFAULT
) is
constant C_BYTE_ENABLE : std_logic_vector(axilite_if.write_data_channel.wstrb'length-1 downto 0) := (others => '1');
begin
axilite_write(addr_value, data_value, C_BYTE_ENABLE, msg, clk, axilite_if, scope, msg_id_panel, config);
end procedure axilite_write;
procedure axilite_write (
constant addr_value : in unsigned;
constant data_value : in std_logic_vector;
constant byte_enable : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal axilite_if : inout t_axilite_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axilite_bfm_config := C_AXILITE_BFM_CONFIG_DEFAULT
) is
constant proc_name : string := "axilite_write";
constant proc_call : string := "axilite_write(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) &
", " & to_string(data_value, HEX, AS_IS, INCL_RADIX) & ")";
constant max_pipe_stages : integer := maximum(config.num_w_pipe_stages, config.num_aw_pipe_stages);
variable v_await_awready : boolean := true;
variable v_await_wready : boolean := true;
variable v_await_bvalid : boolean := true;
-- Normalize to the DUT addr/data widths
variable v_normalized_addr : std_logic_vector(axilite_if.write_address_channel.awaddr'length-1 downto 0) :=
normalize_and_check(std_logic_vector(addr_value), axilite_if.write_address_channel.awaddr, ALLOW_NARROWER, "addr", "axilite_if.write_address_channel.awaddr", msg);
variable v_normalized_data : std_logic_vector(axilite_if.write_data_channel.wdata'length-1 downto 0) :=
normalize_and_check(data_value, axilite_if.write_data_channel.wdata, ALLOW_NARROWER, "data", "axilite_if.write_data_channel.wdata", msg);
begin
check_value(v_normalized_data'length = 32 or v_normalized_data'length = 64, TB_ERROR, "AXI-lite data width must be either 32 or 64!", scope, ID_NEVER, msg_id_panel);
for cycle in 0 to config.max_wait_cycles loop
wait_until_given_time_before_rising_edge(clk, config.clock_period/4, config.clock_period);
if cycle = config.num_w_pipe_stages then
axilite_if.write_data_channel.wdata <= v_normalized_data;
axilite_if.write_data_channel.wstrb <= byte_enable;
axilite_if.write_data_channel.wvalid <= '1';
end if;
if cycle = config.num_aw_pipe_stages then
axilite_if.write_address_channel.awaddr <= v_normalized_addr;
axilite_if.write_address_channel.awvalid <= '1';
axilite_if.write_address_channel.awprot <= to_slv(config.protection_setting);
end if;
wait until rising_edge(clk);
if axilite_if.write_data_channel.wready = '1' and cycle >= config.num_w_pipe_stages then
axilite_if.write_data_channel.wvalid <= '0' after config.clock_period/4;
v_await_wready := false;
end if;
if axilite_if.write_address_channel.awready = '1' and cycle >= config.num_aw_pipe_stages then
axilite_if.write_address_channel.awvalid <= '0' after config.clock_period/4;
v_await_awready := false;
end if;
if not v_await_awready and not v_await_wready then
exit;
end if;
end loop;
check_value(not v_await_wready, config.max_wait_cycles_severity, ": Timeout waiting for WREADY", scope, ID_NEVER, msg_id_panel, proc_call);
check_value(not v_await_awready, config.max_wait_cycles_severity, ": Timeout waiting for AWREADY", scope, ID_NEVER, msg_id_panel, proc_call);
wait_until_given_time_before_rising_edge(clk, config.clock_period/4, config.clock_period);
axilite_if.write_response_channel.bready <= '1';
for cycle in 0 to config.max_wait_cycles loop
wait until rising_edge(clk);
if axilite_if.write_response_channel.bvalid = '1' then
check_value(axilite_if.write_response_channel.bresp, to_slv(config.expected_response), config.expected_response_severity, ": BRESP detected", scope, BIN, AS_IS, ID_NEVER, msg_id_panel, proc_call);
wait_until_given_time_after_rising_edge(clk, config.clock_period/4);
axilite_if.write_response_channel.bready <= '0';
v_await_bvalid := false;
end if;
if not v_await_bvalid then
exit;
end if;
end loop;
check_value(not v_await_bvalid, config.max_wait_cycles_severity, ": Timeout waiting for BVALID", scope, ID_NEVER, msg_id_panel, proc_call);
axilite_if.write_address_channel.awaddr(axilite_if.write_address_channel.awaddr'length-1 downto 0) <= (others => '0');
axilite_if.write_address_channel.awvalid <= '0';
axilite_if.write_data_channel.wdata(axilite_if.write_data_channel.wdata'length-1 downto 0) <= (others => '0');
axilite_if.write_data_channel.wstrb(axilite_if.write_data_channel.wstrb'length-1 downto 0) <= (others => '1');
axilite_if.write_data_channel.wvalid <= '0';
log(config.id_for_bfm, proc_call & " completed. " & add_msg_delimiter(msg), scope, msg_id_panel);
end procedure axilite_write;
procedure axilite_read (
constant addr_value : in unsigned;
variable data_value : out std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal axilite_if : inout t_axilite_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axilite_bfm_config := C_AXILITE_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like axilite_check
) is
constant local_proc_name : string := "axilite_read"; -- Local proc_name; used if called from sequncer or VVC
constant local_proc_call : string := local_proc_name & "(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) & ")"; -- Local proc_call; used if called from sequncer or VVC
-- Normalize to the DUT addr/data widths
variable v_normalized_addr : std_logic_vector(axilite_if.read_address_channel.araddr'length-1 downto 0) :=
normalize_and_check(std_logic_vector(addr_value), axilite_if.read_address_channel.araddr, ALLOW_NARROWER, "addr", "axilite_if.read_address_channel.araddr", msg);
variable v_proc_call : line;
variable v_await_arready : boolean := true;
variable v_await_rvalid : boolean := true;
variable v_data_value : std_logic_vector(axilite_if.read_data_channel.rdata'length-1 downto 0);
begin
-- If called from sequencer/VVC, show 'axilite_read...' in log
if ext_proc_call = "" then
write(v_proc_call, local_proc_call);
else
-- If called from other BFM procedure like axilite_expect, log 'axilite_check(..) while executing axilite_read..'
write(v_proc_call, ext_proc_call & " while executing " & local_proc_name);
end if;
check_value(v_data_value'length = 32 or v_data_value'length = 64, TB_ERROR, "AXI-lite data width must be either 32 or 64!" & add_msg_delimiter(msg), scope, ID_NEVER, msg_id_panel);
wait_until_given_time_before_rising_edge(clk, config.clock_period/4, config.clock_period);
axilite_if.read_address_channel.araddr <= v_normalized_addr;
axilite_if.read_address_channel.arvalid <= '1';
for cycle in 0 to config.max_wait_cycles loop
if axilite_if.read_address_channel.arready = '1' and cycle > 0 then
axilite_if.read_address_channel.arvalid <= '0';
axilite_if.read_address_channel.araddr(axilite_if.read_address_channel.araddr'length-1 downto 0) <= (others => '0');
axilite_if.read_address_channel.arprot <= to_slv(config.protection_setting);
v_await_arready := false;
end if;
if v_await_arready then
wait until rising_edge(clk);
else
exit;
end if;
end loop;
check_value(not v_await_arready, config.max_wait_cycles_severity, ": Timeout waiting for ARREADY", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
wait_until_given_time_before_rising_edge(clk, config.clock_period/4, config.clock_period);
axilite_if.read_data_channel.rready <= '1';
for cycle in 0 to config.max_wait_cycles loop
if axilite_if.read_data_channel.rvalid = '1' and cycle > 0 then
v_await_rvalid := false;
check_value(axilite_if.read_data_channel.rresp, to_slv(config.expected_response), config.expected_response_severity, ": RRESP detected", scope, BIN, AS_IS, ID_NEVER, msg_id_panel, v_proc_call.all);
v_data_value := axilite_if.read_data_channel.rdata;
wait_until_given_time_after_rising_edge(clk, config.clock_period/4);
axilite_if.read_data_channel.rready <= '0';
end if;
if v_await_rvalid then
wait until rising_edge(clk);
else
exit;
end if;
end loop;
check_value(not v_await_rvalid, config.max_wait_cycles_severity, ": Timeout waiting for RVALID", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
data_value := v_data_value;
if ext_proc_call = "" then -- proc_name = "axilite_read" then
log(config.id_for_bfm, v_proc_call.all & "=> " & to_string(v_data_value, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
end if;
end procedure axilite_read;
procedure axilite_check (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal axilite_if : inout t_axilite_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_axilite_bfm_config := C_AXILITE_BFM_CONFIG_DEFAULT
) is
constant proc_name : string := "axilite_check";
constant proc_call : string := "axilite_check(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) & ", " & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & ")";
variable v_data_value : std_logic_vector(axilite_if.write_data_channel.wdata'length-1 downto 0) := (others => '0');
variable v_check_ok : boolean;
-- Normalize to the DUT addr/data widths
variable v_normalized_data : std_logic_vector(axilite_if.write_data_channel.wdata'length-1 downto 0) :=
normalize_and_check(data_exp, axilite_if.write_data_channel.wdata, ALLOW_NARROWER, "data", "axilite_if.write_data_channel.wdata", msg);
begin
axilite_read(addr_value, v_data_value, msg, clk, axilite_if, scope, msg_id_panel, config, proc_call);
v_check_ok := true;
for i in 0 to v_normalized_data'length-1 loop
if v_normalized_data(i) = '-' or v_normalized_data(i) = v_data_value(i) then
v_check_ok := true;
else
v_check_ok := false;
exit;
end if;
end loop;
if not v_check_ok then
alert(alert_level, proc_call & "=> Failed. slv Was " & to_string(v_data_value, HEX, AS_IS, INCL_RADIX) & ". Expected " & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & "." & LF & add_msg_delimiter(msg), scope);
else
log(config.id_for_bfm, proc_call & "=> OK, received data = " & to_string(v_normalized_data, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
end procedure axilite_check;
end package body axilite_bfm_pkg;
|
mit
|
kiwih/subleq-vhdl
|
core.vhd
|
1
|
2690
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_signed.all;
--A single-cycle core for running a one-instruction computer
--Instructions are 24 bits
--[00000000] [00000000] [00000000]
-- A B C
--Executes
----(1) [B] = [B] - [A]
----(2) if [B] - [A] <= 0 GOTO C
entity core is
generic(
ADDR_SIZE : integer := 8;
INSTRUCTION_SIZE : integer := 24; --should be 3x ADDR_SIZE
DATA_SIZE: integer := 16
);
port(
CLK : in std_logic;
RESET : in std_logic;
INSTRUCTION_MEMORY_ADDR : out std_logic_vector(ADDR_SIZE - 1 downto 0);
INSTRUCTION_MEMORY_DATA_OUT: in std_logic_vector(INSTRUCTION_SIZE - 1 downto 0);
DATA_MEMORY_ADDR_A : out std_logic_vector(ADDR_SIZE - 1 downto 0);
DATA_MEMORY_DATA_OUT_A : in std_logic_vector(DATA_SIZE - 1 downto 0);
DATA_MEMORY_ADDR_B : out std_logic_vector(ADDR_SIZE - 1 downto 0);
DATA_MEMORY_DATA_OUT_B : in std_logic_vector(DATA_SIZE - 1 downto 0);
DATA_MEMORY_DATA_IN_B : out std_logic_vector(DATA_SIZE - 1 downto 0);
DATA_MEMORY_WRITE_EN_B : out std_logic
);
end entity core;
architecture beh of core is
signal pc : std_logic_vector(ADDR_SIZE - 1 downto 0) := (others => '0');
signal current_instruction : std_logic_vector(INSTRUCTION_SIZE - 1 downto 0);
signal op_a : std_logic_vector(INSTRUCTION_SIZE/3 - 1 downto 0);
signal op_b : std_logic_vector(INSTRUCTION_SIZE/3 - 1 downto 0);
signal op_c : std_logic_vector(INSTRUCTION_SIZE/3 - 1 downto 0);
signal data_a : std_logic_vector(DATA_SIZE - 1 downto 0);
signal data_b : std_logic_vector(DATA_SIZE - 1 downto 0);
signal data_out : std_logic_vector(DATA_SIZE - 1 downto 0);
begin
INSTRUCTION_MEMORY_ADDR <= pc;
current_instruction <= INSTRUCTION_MEMORY_DATA_OUT;
op_c <= current_instruction(1 * INSTRUCTION_SIZE/3 - 1 downto 0 * INSTRUCTION_SIZE/3);
op_b <= current_instruction(2 * INSTRUCTION_SIZE/3 - 1 downto 1 * INSTRUCTION_SIZE/3);
op_a <= current_instruction(3 * INSTRUCTION_SIZE/3 - 1 downto 2 * INSTRUCTION_SIZE/3);
-- op_c <= current_instruction(7 downto 0);
-- op_b <= current_instruction(15 downto 8);
-- op_a <= current_instruction(23 downto 16);
DATA_MEMORY_ADDR_A <= op_a;
DATA_MEMORY_ADDR_B <= op_b;
DATA_MEMORY_WRITE_EN_B <= '1';
DATA_MEMORY_DATA_IN_B <= data_out;
data_a <= DATA_MEMORY_DATA_OUT_A;
data_b <= DATA_MEMORY_DATA_OUT_B;
data_out <= data_b - data_a;
process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
pc <= (others => '0');
elsif (data_b - data_a) <= 0 then
pc <= op_c;
else
pc <= pc + 1;
end if;
end if;
end process;
end architecture;
|
mit
|
AndyMcC0/UVVM_All
|
bitvis_irqc/src/irqc_pif_pkg.vhd
|
3
|
3063
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis IRQC Library : irqc_pif_pkg
--
-- Description : See dedicated powerpoint presentation and README-file(s)
------------------------------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package irqc_pif_pkg is
-- Change this to a generic when generic in packages is allowed (VHDL 2008)
constant C_NUM_SOURCES : integer := 6; -- 1 <= C_NUM_SOURCES <= Data width
-- Notation for regs: (Included in constant name as info to SW)
-- - RW: Readable and writable reg.
-- - RO: Read only reg. (output from IP)
-- - WO: Write only reg. (typically single cycle strobe to IP)
-- Notation for signals (or fields in record) going between PIF and core:
-- Same notations as for register-constants above, but
-- a preceeding 'a' (e.g. awo) means the register is auxiliary to the PIF.
-- This means no flop in the PIF, but in the core. (Or just a dummy-register with no flop)
constant C_ADDR_IRR : integer := 0;
constant C_ADDR_IER : integer := 1;
constant C_ADDR_ITR : integer := 2;
constant C_ADDR_ICR : integer := 3;
constant C_ADDR_IPR : integer := 4;
constant C_ADDR_IRQ2CPU_ENA : integer := 5;
constant C_ADDR_IRQ2CPU_DISABLE : integer := 6;
constant C_ADDR_IRQ2CPU_ALLOWED : integer := 7;
-- Signals from pif to core
type t_p2c is record
rw_ier : std_logic_vector(C_NUM_SOURCES-1 downto 0);
awt_itr : std_logic_vector(C_NUM_SOURCES-1 downto 0);
awt_icr : std_logic_vector(C_NUM_SOURCES-1 downto 0);
awt_irq2cpu_ena : std_logic;
awt_irq2cpu_disable : std_logic;
end record t_p2c;
-- Signals from core to PIF
type t_c2p is record
aro_irr : std_logic_vector(C_NUM_SOURCES-1 downto 0);
aro_ipr : std_logic_vector(C_NUM_SOURCES-1 downto 0);
aro_irq2cpu_allowed : std_logic;
end record t_c2p;
end package irqc_pif_pkg;
|
mit
|
AndyMcC0/UVVM_All
|
bitvis_irqc/src/irqc_pif.vhd
|
3
|
4203
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis IRQC Library : irqc_pif
--
-- Description : See dedicated powerpoint presentation and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.irqc_pif_pkg.all;
entity irqc_pif is
port(
arst : in std_logic;
clk : in std_logic;
-- CPU interface
cs : in std_logic;
addr : in unsigned;
wr : in std_logic;
rd : in std_logic;
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0) := (others => '0');
--
p2c : out t_p2c;
c2p : in t_c2p
);
end irqc_pif;
architecture rtl of irqc_pif is
signal p2c_i : t_p2c; -- internal version of output
signal dout_i : std_logic_vector(7 downto 0) := (others => '0');
begin
-- Assigning internally used signals to outputs
p2c <= p2c_i;
p_read_reg : process(cs, addr, rd, c2p, p2c_i)
begin
-- default values
dout_i <= (others => '0');
if cs = '1' and rd = '1' then
case to_integer(addr) is
when C_ADDR_IRR =>
dout_i(C_NUM_SOURCES-1 downto 0) <= c2p.aro_irr;
when C_ADDR_IER =>
dout_i(C_NUM_SOURCES-1 downto 0) <= p2c_i.rw_ier;
when C_ADDR_IPR =>
dout_i(C_NUM_SOURCES-1 downto 0) <= c2p.aro_ipr;
when C_ADDR_IRQ2CPU_ALLOWED =>
dout_i(0) <= c2p.aro_irq2cpu_allowed;
when others =>
null;
end case;
end if;
end process p_read_reg;
dout <= dout_i;
-- Writing to registers that are not functionally manipulated
p_write_reg : process(clk, arst)
begin
if arst = '1' then
p2c_i.rw_ier <= (others => '0');
elsif rising_edge(clk) then
if cs = '1' and wr = '1' then
case to_integer(addr) is
when C_ADDR_IER =>
p2c_i.rw_ier <= din(C_NUM_SOURCES-1 downto 0);
-- Auxiliary write (below)
when others =>
null;
end case;
end if;
end if;
end process p_write_reg;
-- Writing to registers that are functionally manipulated and/or located outside PIF (or dummy registers)
p_aux : process(wr, addr, din)
begin
-- Note that arst is not considered here, but must be considered in any clocked process in the core
-- Default - always to return to these values
p2c_i.awt_icr(C_NUM_SOURCES-1 downto 0) <= (others => '0');
p2c_i.awt_itr(C_NUM_SOURCES-1 downto 0) <= (others => '0');
p2c_i.awt_irq2cpu_ena <= '0';
p2c_i.awt_irq2cpu_disable <= '0';
if (cs = '1' and wr = '1') then
case to_integer(addr) is
when C_ADDR_ITR =>
p2c_i.awt_itr <= din(C_NUM_SOURCES-1 downto 0);
when C_ADDR_ICR =>
p2c_i.awt_icr <= din(C_NUM_SOURCES-1 downto 0);
when C_ADDR_IRQ2CPU_ENA =>
p2c_i.awt_irq2cpu_ena <= din(0);
when C_ADDR_IRQ2CPU_DISABLE =>
p2c_i.awt_irq2cpu_disable <= din(0);
when others =>
null;
end case;
end if;
end process p_aux;
end rtl;
|
mit
|
FlatTargetInk/Spartan-HW
|
led_increment.vhd
|
1
|
1483
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:06:33 04/28/2017
-- Design Name:
-- Module Name: led_increment - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity led_increment is
generic(count_width : INTEGER := 8);
Port( INPUT : in STD_LOGIC;
EN : in STD_LOGIC;
RST : in STD_LOGIC;
LEDS : out STD_LOGIC_VECTOR);
end led_increment;
architecture Behavioral of led_increment is
signal COUNTER : STD_LOGIC_VECTOR(count_width-1 downto 0) := (OTHERS => '0');
signal ZEROS : STD_LOGIC_VECTOR(count_width-1 downto 0) := (OTHERS => '0');
begin
LEDS <= COUNTER;
incrementer: process(RST,EN,INPUT)
begin
if (RST = '1') then
COUNTER <= ZEROS;
elsif (INPUT'event and INPUT = '1' and EN = '1') then
COUNTER <= COUNTER + '1';
end if;
end process;
end Behavioral;
|
mit
|
FlatTargetInk/Spartan-HW
|
button_debounce.vhd
|
1
|
1680
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:16:23 04/28/2017
-- Design Name:
-- Module Name: button_debounce - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity button_debounce is
Port( CLK : in STD_LOGIC;
EN : in STD_LOGIC;
BTN : in STD_LOGIC_VECTOR (3 downto 0);
DBTN : out STD_LOGIC_VECTOR (3 downto 0));
end button_debounce;
architecture Structural of button_debounce is
signal DEBOUNCED : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
begin
DBTN <= DEBOUNCED;
BTN_0: entity work.debounce
port map(CLK => CLK,
EN => EN,
INPUT => BTN(0),
OUTPUT => DEBOUNCED(0));
BTN_1: entity work.debounce
port map(CLK => CLK,
EN => EN,
INPUT => BTN(1),
OUTPUT => DEBOUNCED(1));
BTN_2: entity work.debounce
port map(CLK => CLK,
EN => EN,
INPUT => BTN(2),
OUTPUT => DEBOUNCED(2));
BTN_3: entity work.debounce
port map(CLK => CLK,
EN => EN,
INPUT => BTN(3),
OUTPUT => DEBOUNCED(3));
end Structural;
-- vim:set ts=3 sw=3 noexpandtab:
|
mit
|
AndyMcC0/UVVM_All
|
uvvm_vvc_framework/src_target_dependent/td_target_support_pkg.vhd
|
1
|
14794
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.vvc_cmd_pkg.all;
package td_target_support_pkg is
signal global_vvc_ack : std_logic; -- ACK on global triggers
signal global_vvc_busy : std_logic := 'L'; -- ACK on global triggers
shared variable protected_multicast_semaphore : t_protected_semaphore;
shared variable protected_acknowledge_index : t_protected_acknowledge_cmd_idx;
type t_vvc_target_record_unresolved is record -- VVC dedicated to assure signature differences between equal common methods
trigger : std_logic;
vvc_name : string(1 to C_LOG_SCOPE_WIDTH-2); -- as scope is vvc_name & ',' and number
vvc_instance_idx : integer;
vvc_channel : t_channel;
end record;
constant C_VVC_TARGET_RECORD_DEFAULT : t_vvc_target_record_unresolved := (
trigger => 'L',
vvc_name => (others => '?'),
vvc_instance_idx => -1,
vvc_channel => NA
); --
type t_vvc_target_record_drivers is array (natural range <> ) of t_vvc_target_record_unresolved;
function resolved ( input_vector : t_vvc_target_record_drivers) return t_vvc_target_record_unresolved;
subtype t_vvc_target_record is resolved t_vvc_target_record_unresolved;
-------------------------------------------
-- to_string
-------------------------------------------
-- to_string method for VVC name, instance and channel
-- - If channel is set to NA, it will not be included in the string
function to_string(
value : t_vvc_target_record;
vvc_instance : integer := -1;
vvc_channel : t_channel := NA
) return string;
-------------------------------------------
-- format_command_idx
-------------------------------------------
-- Returns an encapsulated command index as string
impure function format_command_idx(
command : t_vvc_cmd_record -- VVC dedicated
) return string;
-------------------------------------------
-- send_command_to_vvc
-------------------------------------------
-- Sends command to VVC and waits for ACK or timeout
-- - Logs with ID_UVVM_SEND_CMD when sending to VVC
-- - Logs with ID_UVVM_CMD_ACK when ACK or timeout occurs
procedure send_command_to_vvc( -- VVC dedicated shared command used shared_vvc_cmd
signal vvc_target : inout t_vvc_target_record;
constant timeout : in time := std.env.resolution_limit
);
-------------------------------------------
-- set_vvc_target_defaults
-------------------------------------------
-- Returns a vvc target record with vvc_name and values specified in C_VVC_TARGET_RECORD_DEFAULT
function set_vvc_target_defaults (
constant vvc_name : in string
) return t_vvc_target_record;
-------------------------------------------
-- set_general_target_and_command_fields
-------------------------------------------
-- Sets target index and channel, and updates shared_vvc_cmd
procedure set_general_target_and_command_fields ( -- VVC dedicated shared command used shared_vvc_cmd
signal target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant proc_call : in string;
constant msg : in string;
constant command_type : in t_immediate_or_queued;
constant operation : in t_operation
);
-------------------------------------------
-- set_general_target_and_command_fields
-------------------------------------------
-- Sets target index and channel, and updates shared_vvc_cmd
procedure set_general_target_and_command_fields ( -- VVC dedicated shared command used shared_vvc_cmd
signal target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant proc_call : in string;
constant msg : in string;
constant command_type : in t_immediate_or_queued;
constant operation : in t_operation
);
-------------------------------------------
-- acknowledge_cmd
-------------------------------------------
-- Drives global_vvc_ack signal (to '1') for 1 delta cycle, then sets it back to 'Z'.
procedure acknowledge_cmd (
signal vvc_ack : inout std_logic;
constant command_idx : in natural
);
end package td_target_support_pkg;
package body td_target_support_pkg is
function resolved ( input_vector : t_vvc_target_record_drivers) return t_vvc_target_record_unresolved is
-- if none of the drives want to drive the target return value of first driver (which we need to drive at least the target name)
constant C_LINE_LENGTH_MAX : natural := 100; -- VVC idx list string length
variable v_result : t_vvc_target_record_unresolved := input_vector(input_vector'low);
variable v_cnt : integer := 0;
variable v_instance_string : string(1 to C_LINE_LENGTH_MAX) := (others => NUL);
variable v_line : line;
variable v_width : integer := 0;
begin
if input_vector'length = 1 then
return input_vector(input_vector'low);
else
for i in input_vector'range loop
-- The VVC is used if instance_idx is not -1 (which is the default value)
if input_vector(i).vvc_instance_idx /= -1 then
-- count the number of sequencer trying to access the VVC
v_cnt := v_cnt + 1;
v_result := input_vector(i);
-- generating string with all instance_idx for report in case of failure
write(v_line, string'(" "));
write(v_line, input_vector(i).vvc_instance_idx);
-- Ensure there is room for the last item and dots
v_width := v_line'length;
if v_width > (C_LINE_LENGTH_MAX-15) then
write(v_line, string'("..."));
exit;
end if;
end if;
end loop;
if v_width > 0 then
v_instance_string(1 to v_width) := v_line.all;
end if;
deallocate(v_line);
check_value(v_cnt < 2, TB_FAILURE, "Arbitration mechanism failed. Check VVC " & to_string(v_result.vvc_name) & " implementation and semaphore handling. Crashing instances with numbers " & v_instance_string(1 to v_width), C_SCOPE, ID_NEVER);
return v_result;
end if;
end resolved;
function to_string(
value : t_vvc_target_record;
vvc_instance : integer := -1;
vvc_channel : t_channel:= NA
) return string is
variable v_instance : integer;
variable v_channel : t_channel;
begin
if vvc_instance = -1 then
v_instance := value.vvc_instance_idx;
else
v_instance := vvc_instance;
end if;
if vvc_channel = NA then
v_channel := value.vvc_channel;
else
v_channel := vvc_channel;
end if;
if v_channel = NA then
return to_string(value.vvc_name) & "," & to_string(v_instance);
else
return to_string(value.vvc_name) & "," & to_string(v_instance) & "," & to_string(v_channel);
end if;
end;
function set_vvc_target_defaults (
constant vvc_name : in string
) return t_vvc_target_record is
variable v_rec : t_vvc_target_record := C_VVC_TARGET_RECORD_DEFAULT;
begin
v_rec.vvc_name := (others => NUL);
v_rec.vvc_name(1 to vvc_name'length) := vvc_name;
return v_rec;
end function;
procedure set_general_target_and_command_fields (
signal target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant proc_call : in string;
constant msg : in string;
constant command_type : in t_immediate_or_queued;
constant operation : in t_operation
) is
begin
-- As shared_vvc_cmd is a shared variable we have to get exclusive access to it. Therefor we have to lock the protected_semaphore here.
-- It is unlocked again in await_cmd_from_sequencer after it is copied localy or in send_command_to_vvc if no VVC acknowledges the command.
-- It is guaranteed that no time delay occurs, only delta cycle delay.
await_semaphore_in_delta_cycles(protected_semaphore);
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
target.vvc_instance_idx <= vvc_instance_idx;
target.vvc_channel <= vvc_channel;
shared_vvc_cmd.proc_call := pad_string(proc_call, NUL, shared_vvc_cmd.proc_call'length);
shared_vvc_cmd.msg := (others => NUL); -- default empty
shared_vvc_cmd.msg(1 to msg'length) := msg;
shared_vvc_cmd.command_type := command_type;
shared_vvc_cmd.operation := operation;
end procedure;
procedure set_general_target_and_command_fields (
signal target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant proc_call : in string;
constant msg : in string;
constant command_type : in t_immediate_or_queued;
constant operation : in t_operation
) is
begin
set_general_target_and_command_fields(target, vvc_instance_idx, NA, proc_call, msg, command_type, operation);
end procedure;
impure function format_command_idx(
command : t_vvc_cmd_record
) return string is
begin
return format_command_idx(command.cmd_idx);
end;
procedure send_command_to_vvc(
signal vvc_target : inout t_vvc_target_record;
constant timeout : in time := std.env.resolution_limit
) is
constant C_SCOPE : string := C_TB_SCOPE_DEFAULT & "(uvvm)";
constant C_CMD_INFO : string := "uvvm cmd " & format_command_idx(shared_cmd_idx+1) & ": ";
variable v_ack_cmd_idx : integer := -1;
variable v_start_time : time;
variable v_local_vvc_cmd : t_vvc_cmd_record;
variable v_local_cmd_idx : integer;
variable v_was_multicast : boolean := false;
begin
check_value((shared_uvvm_state /= IDLE), TB_FAILURE, "UVVM will not work without uvvm_vvc_framework.ti_uvvm_engine instantiated in the test harness", C_SCOPE, ID_NEVER);
-- increment shared_cmd_inx. It is protected by the protected_semaphore and only one sequencer can access the variable at a time.
shared_cmd_idx := shared_cmd_idx + 1;
shared_vvc_cmd.cmd_idx := shared_cmd_idx;
if global_show_msg_for_uvvm_cmd then
log(ID_UVVM_SEND_CMD, to_string(shared_vvc_cmd.proc_call) & ": " & add_msg_delimiter(to_string(shared_vvc_cmd.msg)) & "."
& format_command_idx(shared_cmd_idx), C_SCOPE);
else
log(ID_UVVM_SEND_CMD, to_string(shared_vvc_cmd.proc_call)
& format_command_idx(shared_cmd_idx), C_SCOPE);
end if;
wait for 0 ns;
if (vvc_target.vvc_instance_idx = C_VVCT_ALL_INSTANCES) then
await_semaphore_in_delta_cycles(protected_multicast_semaphore);
if global_vvc_busy /= 'L' then
wait until global_vvc_busy = 'L';
end if;
v_was_multicast := true;
end if;
v_start_time := now;
-- semaphore "protected_semaphore" gets released after "wait for 0 ns" in await_cmd_from_sequencer
-- Before the semaphore is released copy shared_vvc_cmd to local variable, so that the shared_vvc_cmd can be used by other VVCs.
v_local_vvc_cmd := shared_vvc_cmd;
-- copy the shared_cmd_idx as it can be changed during this function after the semaphore is released
v_local_cmd_idx := shared_cmd_idx;
-- trigger the target -> vvc continues in await_cmd_from_sequencer
vvc_target.trigger <= '1';
wait for 0 ns;
-- the default value of vvc_target drives trigger to 'L' again
vvc_target <= set_vvc_target_defaults(vvc_target.vvc_name);
while v_ack_cmd_idx /= v_local_cmd_idx loop
wait until global_vvc_ack = '1' for ((v_start_time + timeout) - now);
v_ack_cmd_idx := protected_acknowledge_index.get_index;
if not (global_vvc_ack'event) then
tb_error("Time out for " & C_CMD_INFO & " '" & to_string(v_local_vvc_cmd.proc_call) & "' while waiting for acknowledge from VVC", C_SCOPE);
-- lock the sequencer for 5 delta cycles as it can take so long to get every VVC in normal mode again
wait for 0 ns;
wait for 0 ns;
wait for 0 ns;
wait for 0 ns;
wait for 0 ns;
-- release the semaphore as no VVC can do this
release_semaphore(protected_semaphore);
return;
end if;
end loop;
if (v_was_multicast = true) then
release_semaphore(protected_multicast_semaphore);
end if;
log(ID_UVVM_CMD_ACK, "ACK received. " & format_command_idx(v_local_cmd_idx), C_SCOPE);
-- clean up and prepare for next
wait for 0 ns; -- wait for executor to stop driving global_vvc_ack
end procedure;
procedure acknowledge_cmd (
signal vvc_ack : inout std_logic;
constant command_idx : in natural
) is
begin
-- Drive ack signal for 1 delta cycle only one command index can be acknowledged simultaneously.
while(protected_acknowledge_index.set_index(command_idx) = false) loop
-- if it can't set the acknowledge_index wait for one delta cycle and try again
wait for 0 ns;
end loop;
vvc_ack <= '1';
wait until vvc_ack = '1';
vvc_ack <= 'Z';
wait for 0 ns;
protected_acknowledge_index.release_index;
end procedure;
end package body td_target_support_pkg;
|
mit
|
AndyMcC0/UVVM_All
|
bitvis_vip_axistream/src/axistream_vvc.vhd
|
1
|
21985
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.axistream_bfm_pkg.all;
use work.vvc_methods_pkg.all; -- shared_axistream_vvc_config
use work.vvc_cmd_pkg.all;
use work.td_target_support_pkg.all;
use work.td_vvc_entity_support_pkg.all;
use work.td_cmd_queue_pkg.all;
use work.td_result_queue_pkg.all;
--========================================================================================================================
entity axistream_vvc is
generic (
-- When true: This VVC is an AXI4 Stream master. Data is output from BFM.
-- When false: This VVC is an AXI4 Stream slave. Data is input to BFM.
GC_VVC_IS_MASTER : boolean;
GC_DATA_WIDTH : integer;
GC_USER_WIDTH : integer := 1;
-- (Note: STRB_WIDTH = DATA_WIDTH/8)
GC_ID_WIDTH : integer := 1;
GC_DEST_WIDTH : integer := 1;
GC_INSTANCE_IDX : natural;
GC_PACKETINFO_QUEUE_COUNT_MAX : natural := 1; -- Number of PacketInfo Queues, normally one per source VVC
GC_AXISTREAM_BFM_CONFIG : t_axistream_bfm_config := C_AXISTREAM_BFM_CONFIG_DEFAULT;
GC_CMD_QUEUE_COUNT_MAX : natural := 1000;
GC_CMD_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := warning;
GC_RESULT_QUEUE_COUNT_MAX : natural := 1000;
GC_RESULT_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING
);
port (
clk : in std_logic;
axistream_vvc_if : inout t_axistream_if := init_axistream_if_signals(GC_VVC_IS_MASTER, GC_DATA_WIDTH, GC_USER_WIDTH, GC_ID_WIDTH, GC_DEST_WIDTH)
);
begin
-- Check the interface widths to assure that the interface was correctly set up
assert (axistream_vvc_if.tdata'length = GC_DATA_WIDTH) report "axistream_vvc_if.data'length =/ GC_DATA_WIDTH" severity failure;
end entity axistream_vvc;
--========================================================================================================================
--========================================================================================================================
architecture behave of axistream_vvc is
constant C_SCOPE : string := C_VVC_NAME & "," & to_string(GC_INSTANCE_IDX);
constant C_VVC_LABELS : t_vvc_labels := assign_vvc_labels(C_SCOPE, C_VVC_NAME, GC_INSTANCE_IDX, NA);
signal executor_is_busy : boolean := false;
signal queue_is_increasing : boolean := false;
signal last_cmd_idx_executed : natural := 0;
signal terminate_current_cmd : t_flag_record;
-- Instantiation of the element dedicated Queue
shared variable command_queue : work.td_cmd_queue_pkg.t_generic_queue;
shared variable result_queue : work.td_result_queue_pkg.t_generic_queue;
alias vvc_config : t_vvc_config is shared_axistream_vvc_config(GC_INSTANCE_IDX);
alias vvc_status : t_vvc_status is shared_axistream_vvc_status(GC_INSTANCE_IDX);
alias transaction_info : t_transaction_info is shared_axistream_transaction_info(GC_INSTANCE_IDX);
begin
--========================================================================================================================
-- Constructor
-- - Set up the defaults and show constructor if enabled
--========================================================================================================================
work.td_vvc_entity_support_pkg.vvc_constructor(C_SCOPE, GC_INSTANCE_IDX, vvc_config, command_queue, result_queue, GC_AXISTREAM_BFM_CONFIG,
GC_CMD_QUEUE_COUNT_MAX, GC_CMD_QUEUE_COUNT_THRESHOLD, GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
GC_RESULT_QUEUE_COUNT_MAX, GC_RESULT_QUEUE_COUNT_THRESHOLD, GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY);
--========================================================================================================================
--========================================================================================================================
-- Command interpreter
-- - Interpret, decode and acknowledge commands from the central sequencer
--========================================================================================================================
cmd_interpreter : process
variable v_cmd_has_been_acked : boolean; -- Indicates if acknowledge_cmd() has been called for the current shared_vvc_cmd
variable v_local_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
begin
-- 0. Initialize the process prior to first command
work.td_vvc_entity_support_pkg.initialize_interpreter(terminate_current_cmd, global_awaiting_completion);
-- initialise shared_vvc_last_received_cmd_idx for channel and instance
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := 0;
-- Then for every single command from the sequencer
loop -- basically as long as new commands are received
-- 1. wait until command targeted at this VVC. Must match VVC name, instance and channel (if applicable)
-- releases global semaphore
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.await_cmd_from_sequencer(C_VVC_LABELS, vvc_config, THIS_VVCT, VVC_BROADCAST, global_vvc_busy, global_vvc_ack, shared_vvc_cmd, v_local_vvc_cmd);
v_cmd_has_been_acked := false; -- Clear flag
-- update shared_vvc_last_received_cmd_idx with received command index
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := v_local_vvc_cmd.cmd_idx;
-- 2a. Put command on the queue if intended for the executor
-------------------------------------------------------------------------
if v_local_vvc_cmd.command_type = QUEUED then
work.td_vvc_entity_support_pkg.put_command_on_queue(v_local_vvc_cmd, command_queue, vvc_status, queue_is_increasing);
-- 2b. Otherwise command is intended for immediate response
-------------------------------------------------------------------------
elsif v_local_vvc_cmd.command_type = IMMEDIATE then
case v_local_vvc_cmd.operation is
when AWAIT_COMPLETION =>
work.td_vvc_entity_support_pkg.interpreter_await_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed);
when AWAIT_ANY_COMPLETION =>
if not v_local_vvc_cmd.gen_boolean then
-- Called with lastness = NOT_LAST: Acknowledge immediately to let the sequencer continue
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
v_cmd_has_been_acked := true;
end if;
work.td_vvc_entity_support_pkg.interpreter_await_any_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed, global_awaiting_completion);
when DISABLE_LOG_MSG =>
uvvm_util.methods_pkg.disable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE);
when ENABLE_LOG_MSG =>
uvvm_util.methods_pkg.enable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE);
when FLUSH_COMMAND_QUEUE =>
work.td_vvc_entity_support_pkg.interpreter_flush_command_queue(v_local_vvc_cmd, command_queue, vvc_config, vvc_status, C_VVC_LABELS);
when TERMINATE_CURRENT_COMMAND =>
work.td_vvc_entity_support_pkg.interpreter_terminate_current_command(v_local_vvc_cmd, vvc_config, C_VVC_LABELS, terminate_current_cmd);
when FETCH_RESULT =>
work.td_vvc_entity_support_pkg.interpreter_fetch_result(result_queue, v_local_vvc_cmd, vvc_config, C_VVC_LABELS, last_cmd_idx_executed, shared_vvc_response);
when others =>
tb_error("Unsupported command received for IMMEDIATE execution: '" & to_string(v_local_vvc_cmd.operation) & "'", C_SCOPE);
end case;
else
tb_error("command_type is not IMMEDIATE or QUEUED", C_SCOPE);
end if;
-- 3. Acknowledge command after running or queuing the command
-------------------------------------------------------------------------
if not v_cmd_has_been_acked then
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
end if;
end loop;
end process;
--========================================================================================================================
--========================================================================================================================
-- Command executor
-- - Fetch and execute the commands
--========================================================================================================================
cmd_executor : process
variable v_cmd : t_vvc_cmd_record;
variable v_result : t_vvc_result; -- See vvc_cmd_pkg
variable v_timestamp_start_of_current_bfm_access : time := 0 ns;
variable v_timestamp_start_of_last_bfm_access : time := 0 ns;
variable v_timestamp_end_of_last_bfm_access : time := 0 ns;
variable v_command_is_bfm_access : boolean;
begin
-- 0. Initialize the process prior to first command
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.initialize_executor(terminate_current_cmd);
loop
-- 1. Set defaults, fetch command and log
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.fetch_command_and_prepare_executor(v_cmd, command_queue, vvc_config, vvc_status, queue_is_increasing, executor_is_busy, C_VVC_LABELS);
-- Reset the transaction info for waveview
--transaction_info := C_TRANSACTION_INFO_DEFAULT;
transaction_info.operation := v_cmd.operation;
transaction_info.msg := pad_string(to_string(v_cmd.msg), ' ', transaction_info.msg'length);
-- Check if command is a BFM access
if v_cmd.operation = TRANSMIT or v_cmd.operation = RECEIVE or v_cmd.operation = EXPECT then
v_command_is_bfm_access := true;
else
v_command_is_bfm_access := false;
end if;
-- Insert delay if needed
work.td_vvc_entity_support_pkg.insert_inter_bfm_delay_if_requested(vvc_config => vvc_config,
command_is_bfm_access => v_command_is_bfm_access,
timestamp_start_of_last_bfm_access => v_timestamp_start_of_last_bfm_access,
timestamp_end_of_last_bfm_access => v_timestamp_end_of_last_bfm_access);
if v_command_is_bfm_access then
v_timestamp_start_of_current_bfm_access := now;
end if;
log(ID_BFM, "Running : " & to_string(v_cmd.proc_call) & " " & format_command_idx(v_cmd) & ".", C_SCOPE, vvc_config.msg_id_panel);
-- 2. Execute the fetched command
-------------------------------------------------------------------------
case v_cmd.operation is -- Only operations in the dedicated record are relevant
-- VVC dedicated operations
--===================================
when TRANSMIT =>
check_value(GC_VVC_IS_MASTER, true, TB_ERROR, "Sanity check: Method call only makes sense for master (source) VVC", C_SCOPE, ID_NEVER);
-- Put in queue so that the monitor VVC knows what to expect
-- Needed when the sink is in Monitor Mode, as an alternative to calling lbusExpect() for each packet
transaction_info.numPacketsSent := transaction_info.numPacketsSent + 1;
-- Call the corresponding procedure in the BFM package.
axistream_transmit(
data_array => v_cmd.data_array(0 to v_cmd.data_array_length-1),
user_array => v_cmd.user_array(0 to v_cmd.user_array_length-1),
strb_array => v_cmd.strb_array(0 to v_cmd.strb_array_length-1),
id_array => v_cmd.id_array(0 to v_cmd.id_array_length-1),
dest_array => v_cmd.dest_array(0 to v_cmd.dest_array_length-1),
msg => format_msg(v_cmd),
clk => clk,
-- Using the non-record version to avoid fatal error in Modelsim: (SIGSEGV) Bad handle or reference
axistream_if_tdata => axistream_vvc_if.tdata,
axistream_if_tkeep => axistream_vvc_if.tkeep,
axistream_if_tuser => axistream_vvc_if.tuser,
axistream_if_tstrb => axistream_vvc_if.tstrb,
axistream_if_tid => axistream_vvc_if.tid,
axistream_if_tdest => axistream_vvc_if.tdest,
axistream_if_tvalid => axistream_vvc_if.tvalid,
axistream_if_tlast => axistream_vvc_if.tlast,
axistream_if_tready => axistream_vvc_if.tready,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
when RECEIVE =>
axistream_receive(data_array => v_result.data_array,
data_length => v_result.data_length,
user_array => v_result.user_array,
strb_array => v_result.strb_array,
id_array => v_result.id_array,
dest_array => v_result.dest_array,
msg => format_msg(v_cmd),
clk => clk,
-- Using the non-record version to avoid fatal error in Questa: (SIGSEGV) Bad handle or reference
axistream_if_tdata => axistream_vvc_if.tdata,
axistream_if_tkeep => axistream_vvc_if.tkeep,
axistream_if_tuser => axistream_vvc_if.tuser,
axistream_if_tstrb => axistream_vvc_if.tstrb,
axistream_if_tid => axistream_vvc_if.tid,
axistream_if_tdest => axistream_vvc_if.tdest,
axistream_if_tvalid => axistream_vvc_if.tvalid,
axistream_if_tlast => axistream_vvc_if.tlast,
axistream_if_tready => axistream_vvc_if.tready,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
-- Store the result
work.td_vvc_entity_support_pkg.store_result( result_queue => result_queue,
cmd_idx => v_cmd.cmd_idx,
result => v_result );
when EXPECT =>
-- Call the corresponding procedure in the BFM package.
axistream_expect(
exp_data_array => v_cmd.data_array(0 to v_cmd.data_array_length-1),
exp_user_array => v_cmd.user_array(0 to v_cmd.user_array_length-1),
exp_strb_array => v_cmd.strb_array(0 to v_cmd.strb_array_length-1),
exp_id_array => v_cmd.id_array(0 to v_cmd.id_array_length-1),
exp_dest_array => v_cmd.dest_array(0 to v_cmd.dest_array_length-1),
msg => format_msg(v_cmd),
clk => clk,
-- Using the non-record version to avoid fatal error in Questa: (SIGSEGV) Bad handle or reference
axistream_if_tdata => axistream_vvc_if.tdata,
axistream_if_tkeep => axistream_vvc_if.tkeep,
axistream_if_tuser => axistream_vvc_if.tuser,
axistream_if_tstrb => axistream_vvc_if.tstrb,
axistream_if_tid => axistream_vvc_if.tid,
axistream_if_tdest => axistream_vvc_if.tdest,
axistream_if_tvalid => axistream_vvc_if.tvalid,
axistream_if_tlast => axistream_vvc_if.tlast,
axistream_if_tready => axistream_vvc_if.tready,
alert_level => v_cmd.alert_level,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
-- UVVM common operations
--===================================
when INSERT_DELAY =>
log(ID_INSERTED_DELAY, "Running: " & to_string(v_cmd.proc_call) & " " & format_command_idx(v_cmd), C_SCOPE, vvc_config.msg_id_panel);
if v_cmd.gen_integer_array(0) = -1 then
-- Delay specified using time
wait until terminate_current_cmd.is_active = '1' for v_cmd.delay;
else
-- Delay specified using integer
wait until terminate_current_cmd.is_active = '1' for v_cmd.gen_integer_array(0) * vvc_config.bfm_config.clock_period;
end if;
when others =>
tb_error("Unsupported local command received for execution: '" & to_string(v_cmd.operation) & "'", C_SCOPE);
end case;
if v_command_is_bfm_access then
v_timestamp_end_of_last_bfm_access := now;
v_timestamp_start_of_last_bfm_access := v_timestamp_start_of_current_bfm_access;
if ((vvc_config.inter_bfm_delay.delay_type = TIME_START2START) and
((now - v_timestamp_start_of_current_bfm_access) > vvc_config.inter_bfm_delay.delay_in_time)) then
alert(vvc_config.inter_bfm_delay.inter_bfm_delay_violation_severity, "BFM access exceeded specified start-to-start inter-bfm delay, " &
to_string(vvc_config.inter_bfm_delay.delay_in_time) & ".", C_SCOPE);
end if;
end if;
-- Reset terminate flag if any occurred
if (terminate_current_cmd.is_active = '1') then
log(ID_CMD_EXECUTOR, "Termination request received", C_SCOPE, vvc_config.msg_id_panel);
uvvm_vvc_framework.ti_vvc_framework_support_pkg.reset_flag(terminate_current_cmd);
end if;
last_cmd_idx_executed <= v_cmd.cmd_idx;
-- Reset the transaction info for waveview
transaction_info := C_TRANSACTION_INFO_DEFAULT;
end loop;
end process;
--========================================================================================================================
--========================================================================================================================
-- Command termination handler
-- - Handles the termination request record (sets and resets terminate flag on request)
--========================================================================================================================
cmd_terminator : uvvm_vvc_framework.ti_vvc_framework_support_pkg.flag_handler(terminate_current_cmd); -- flag: is_active, set, reset
--========================================================================================================================
end behave;
|
mit
|
AndyMcC0/UVVM_All
|
bitvis_vip_spi/src/spi_vvc.vhd
|
1
|
27075
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.spi_bfm_pkg.all;
use work.vvc_methods_pkg.all;
use work.vvc_cmd_pkg.all;
use work.td_vvc_framework_common_methods_pkg.all;
use work.td_target_support_pkg.all;
use work.td_vvc_entity_support_pkg.all;
use work.td_cmd_queue_pkg.all;
use work.td_result_queue_pkg.all;
--=================================================================================================
entity spi_vvc is
generic (
GC_DATA_WIDTH : integer := 8;
GC_INSTANCE_IDX : natural := 1; -- Instance index for this SPI_VVCT instance
GC_MASTER_MODE : boolean := true;
GC_SPI_CONFIG : t_spi_bfm_config := C_SPI_BFM_CONFIG_DEFAULT; -- Behavior specification for BFM
GC_CMD_QUEUE_COUNT_MAX : natural := 1000;
GC_CMD_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING;
GC_RESULT_QUEUE_COUNT_MAX : natural := 1000;
GC_RESULT_QUEUE_COUNT_THRESHOLD : natural := 950;
GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY : t_alert_level := WARNING
);
port (
spi_vvc_if : inout t_spi_if := init_spi_if_signals(GC_SPI_CONFIG, GC_MASTER_MODE)
);
end entity spi_vvc;
--=================================================================================================
--=================================================================================================
architecture behave of spi_vvc is
constant C_SCOPE : string := C_VVC_NAME & "," & to_string(GC_INSTANCE_IDX);
constant C_VVC_LABELS : t_vvc_labels := assign_vvc_labels(C_SCOPE, C_VVC_NAME, GC_INSTANCE_IDX, NA);
signal executor_is_busy : boolean := false;
signal queue_is_increasing : boolean := false;
signal last_cmd_idx_executed : natural := 0;
signal terminate_current_cmd : t_flag_record;
-- Instantiation of the element dedicated Queue
shared variable command_queue : work.td_cmd_queue_pkg.t_generic_queue;
shared variable result_queue : work.td_result_queue_pkg.t_generic_queue;
alias vvc_config : t_vvc_config is shared_spi_vvc_config(GC_INSTANCE_IDX);
alias vvc_status : t_vvc_status is shared_spi_vvc_status(GC_INSTANCE_IDX);
alias transaction_info : t_transaction_info is shared_spi_transaction_info(GC_INSTANCE_IDX);
begin
--===============================================================================================
-- Constructor
-- - Set up the defaults and show constructor if enabled
--===============================================================================================
work.td_vvc_entity_support_pkg.vvc_constructor(C_SCOPE, GC_INSTANCE_IDX, vvc_config, command_queue, result_queue, GC_SPI_CONFIG,
GC_CMD_QUEUE_COUNT_MAX, GC_CMD_QUEUE_COUNT_THRESHOLD, GC_CMD_QUEUE_COUNT_THRESHOLD_SEVERITY,
GC_RESULT_QUEUE_COUNT_MAX, GC_RESULT_QUEUE_COUNT_THRESHOLD, GC_RESULT_QUEUE_COUNT_THRESHOLD_SEVERITY);
--===============================================================================================
--===============================================================================================
-- Command interpreter
-- - Interpret, decode and acknowledge commands from the central sequencer
--===============================================================================================
cmd_interpreter : process
variable v_cmd_has_been_acked : boolean; -- Indicates if acknowledge_cmd() has been called for the current shared_vvc_cmd
variable v_local_vvc_cmd : t_vvc_cmd_record := C_VVC_CMD_DEFAULT;
begin
-- 0. Initialize the process prior to first command
work.td_vvc_entity_support_pkg.initialize_interpreter(terminate_current_cmd, global_awaiting_completion);
-- initialise shared_vvc_last_received_cmd_idx for channel and instance
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := 0;
-- Then for every single command from the sequencer
loop -- basically as long as new commands are received
-- 1. wait until command targeted at this VVC. Must match VVC name, instance and channel (if applicable)
-- releases global semaphore
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.await_cmd_from_sequencer(C_VVC_LABELS, vvc_config, THIS_VVCT, VVC_BROADCAST, global_vvc_busy, global_vvc_ack, shared_vvc_cmd, v_local_vvc_cmd);
v_cmd_has_been_acked := false; -- Clear flag
-- update shared_vvc_last_received_cmd_idx with received command index
shared_vvc_last_received_cmd_idx(NA, GC_INSTANCE_IDX) := v_local_vvc_cmd.cmd_idx;
-- 2a. Put command on the queue if intended for the executor
-------------------------------------------------------------------------
if v_local_vvc_cmd.command_type = QUEUED then
work.td_vvc_entity_support_pkg.put_command_on_queue(v_local_vvc_cmd, command_queue, vvc_status, queue_is_increasing);
-- 2b. Otherwise command is intended for immediate response
-------------------------------------------------------------------------
elsif v_local_vvc_cmd.command_type = IMMEDIATE then
case v_local_vvc_cmd.operation is
when AWAIT_COMPLETION =>
work.td_vvc_entity_support_pkg.interpreter_await_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed);
when AWAIT_ANY_COMPLETION =>
if not v_local_vvc_cmd.gen_boolean then
-- Called with lastness = NOT_LAST: Acknowledge immediately to let the sequencer continue
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
v_cmd_has_been_acked := true;
end if;
work.td_vvc_entity_support_pkg.interpreter_await_any_completion(v_local_vvc_cmd, command_queue, vvc_config, executor_is_busy, C_VVC_LABELS, last_cmd_idx_executed, global_awaiting_completion);
when DISABLE_LOG_MSG =>
uvvm_util.methods_pkg.disable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE);
when ENABLE_LOG_MSG =>
uvvm_util.methods_pkg.enable_log_msg(v_local_vvc_cmd.msg_id, vvc_config.msg_id_panel, to_string(v_local_vvc_cmd.msg) & format_command_idx(v_local_vvc_cmd), C_SCOPE);
when FLUSH_COMMAND_QUEUE =>
work.td_vvc_entity_support_pkg.interpreter_flush_command_queue(v_local_vvc_cmd, command_queue, vvc_config, vvc_status, C_VVC_LABELS);
when TERMINATE_CURRENT_COMMAND =>
work.td_vvc_entity_support_pkg.interpreter_terminate_current_command(v_local_vvc_cmd, vvc_config, C_VVC_LABELS, terminate_current_cmd);
when FETCH_RESULT =>
work.td_vvc_entity_support_pkg.interpreter_fetch_result(result_queue, v_local_vvc_cmd, vvc_config, C_VVC_LABELS, last_cmd_idx_executed, shared_vvc_response);
when others =>
tb_error("Unsupported command received for IMMEDIATE execution: '" & to_string(v_local_vvc_cmd.operation) & "'", C_SCOPE);
end case;
else
tb_error("command_type is not IMMEDIATE or QUEUED", C_SCOPE);
end if;
-- 3. Acknowledge command after runing or queuing the command
-------------------------------------------------------------------------
if not v_cmd_has_been_acked then
--uvvm_vvc_framework.ti_vvc_framework_support_pkg.acknowledge_cmd(global_vvc_ack);
work.td_target_support_pkg.acknowledge_cmd(global_vvc_ack,v_local_vvc_cmd.cmd_idx);
end if;
end loop;
end process;
--===============================================================================================
--===============================================================================================
-- Command executor
-- - Fetch and execute the commands
--===============================================================================================
cmd_executor : process
variable v_cmd : t_vvc_cmd_record;
variable v_result : t_vvc_result; -- See vvc_cmd_pkg
variable v_timestamp_start_of_current_bfm_access : time := 0 ns;
variable v_timestamp_start_of_last_bfm_access : time := 0 ns;
variable v_timestamp_end_of_last_bfm_access : time := 0 ns;
variable v_command_is_bfm_access : boolean;
variable v_normalised_data : std_logic_vector(GC_DATA_WIDTH-1 downto 0) := (others => '0');
begin
-- 0. Initialize the process prior to first command
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.initialize_executor(terminate_current_cmd);
loop
-- 1. Set defaults, fetch command and log
-------------------------------------------------------------------------
work.td_vvc_entity_support_pkg.fetch_command_and_prepare_executor(v_cmd, command_queue, vvc_config, vvc_status, queue_is_increasing, executor_is_busy, C_VVC_LABELS);
-- Set the transaction info for waveview
transaction_info := C_TRANSACTION_INFO_DEFAULT;
transaction_info.operation := v_cmd.operation;
transaction_info.msg := pad_string(to_string(v_cmd.msg), ' ', transaction_info.msg'length);
-- Check if command is a BFM access
if v_cmd.operation = MASTER_TRANSMIT_AND_RECEIVE or
v_cmd.operation = MASTER_TRANSMIT_AND_CHECK or
v_cmd.operation = MASTER_TRANSMIT_ONLY or
v_cmd.operation = MASTER_RECEIVE_ONLY or
v_cmd.operation = MASTER_CHECK_ONLY or
v_cmd.operation = SLAVE_TRANSMIT_AND_RECEIVE or
v_cmd.operation = SLAVE_TRANSMIT_AND_CHECK or
v_cmd.operation = SLAVE_TRANSMIT_ONLY or
v_cmd.operation = SLAVE_RECEIVE_ONLY or
v_cmd.operation = SLAVE_CHECK_ONLY
then
v_command_is_bfm_access := true;
else
v_command_is_bfm_access := false;
end if;
-- Insert delay if needed
work.td_vvc_entity_support_pkg.insert_inter_bfm_delay_if_requested(vvc_config => vvc_config,
command_is_bfm_access => v_command_is_bfm_access,
timestamp_start_of_last_bfm_access => v_timestamp_start_of_last_bfm_access,
timestamp_end_of_last_bfm_access => v_timestamp_end_of_last_bfm_access,
scope => C_SCOPE);
if v_command_is_bfm_access then
v_timestamp_start_of_current_bfm_access := now;
end if;
log(ID_BFM, "Running : " & to_string(v_cmd.proc_call) & " " & format_command_idx(v_cmd) & ".", C_SCOPE, vvc_config.msg_id_panel);
-- 2. Execute the fetched command
-------------------------------------------------------------------------
case v_cmd.operation is -- Only operations in the dedicated record are relevant
-- VVC dedicated operations
--===================================
when MASTER_TRANSMIT_AND_RECEIVE =>
transaction_info.tx_data(GC_DATA_WIDTH-1 downto 0) := v_cmd.data(GC_DATA_WIDTH-1 downto 0);
-- Normalise data
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", "spi_master_transmit_and_receive() called with to wide data. " & v_cmd.msg);
if GC_MASTER_MODE then
spi_master_transmit_and_receive(tx_data => v_normalised_data,
rx_data => v_result,
msg => format_msg(v_cmd),
spi_if => spi_vvc_if,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
-- Store the result
work.td_vvc_entity_support_pkg.store_result( result_queue => result_queue,
cmd_idx => v_cmd.cmd_idx,
result => v_result );
else -- attempted master transmit and receive when in slave mode
alert(error, "Master transmit and receive called when VVC is in slave mode.", C_SCOPE);
end if;
when MASTER_TRANSMIT_AND_CHECK =>
transaction_info.tx_data(GC_DATA_WIDTH-1 downto 0) := v_cmd.data(GC_DATA_WIDTH-1 downto 0);
-- Normalise data
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", "spi_master_transmit_and_check() called with to wide data. " & v_cmd.msg);
if GC_MASTER_MODE then
spi_master_transmit_and_check(tx_data => v_normalised_data,
data_exp => v_cmd.data_exp(GC_DATA_WIDTH-1 downto 0),
msg => format_msg(v_cmd),
spi_if => spi_vvc_if,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
else -- attempted master transmit and receive when in slave mode
alert(error, "Master transmit and check called when VVC is in slave mode.", C_SCOPE);
end if;
when MASTER_TRANSMIT_ONLY =>
transaction_info.tx_data(GC_DATA_WIDTH-1 downto 0) := v_cmd.data(GC_DATA_WIDTH-1 downto 0);
-- Normalise data
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", "spi_master_transmit() called with to wide data. " & v_cmd.msg);
if GC_MASTER_MODE then -- master transmit
-- Call the corresponding procedure in the BFM package.
spi_master_transmit(tx_data => v_normalised_data,
msg => format_msg(v_cmd),
spi_if => spi_vvc_if,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
else -- attempted master transmit when in slave mode
alert(error, "Master transmit called when VVC is in slave mode.", C_SCOPE);
end if;
when MASTER_RECEIVE_ONLY =>
if GC_MASTER_MODE then -- master receive
-- Call the corresponding procedure in the BFM package.
spi_master_receive(rx_data => v_result(GC_DATA_WIDTH-1 downto 0),
msg => format_msg(v_cmd),
spi_if => spi_vvc_if,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
-- Store the result
work.td_vvc_entity_support_pkg.store_result(result_queue => result_queue,
cmd_idx => v_cmd.cmd_idx,
result => v_result);
else -- attempted master receive when in slave mode
alert(error, "Master receive called when VVC is in slave mode.", C_SCOPE);
end if;
when MASTER_CHECK_ONLY =>
-- Normalise data
v_normalised_data := normalize_and_check(v_cmd.data_exp, v_normalised_data, ALLOW_WIDER_NARROWER, "data_exp", "shared_vvc_cmd.data_exp", "spi_master_check() called with to wide data. " & v_cmd.msg);
if GC_MASTER_MODE then -- master check
-- Call the corresponding procedure in the BFM package.
spi_master_check(data_exp => v_normalised_data,
msg => format_msg(v_cmd),
spi_if => spi_vvc_if,
alert_level => v_cmd.alert_level,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
else -- attempted master check when in slave mode
alert(error, "Master check called when VVC is in slave mode.", C_SCOPE);
end if;
when SLAVE_TRANSMIT_AND_RECEIVE =>
transaction_info.tx_data(GC_DATA_WIDTH-1 downto 0) := v_cmd.data(GC_DATA_WIDTH-1 downto 0);
-- Normalise data
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", "spi_slave_transmit_and_receive() called with to wide data. " & v_cmd.msg);
if not GC_MASTER_MODE then
spi_slave_transmit_and_receive(tx_data => v_normalised_data,
rx_data => v_result,
msg => format_msg(v_cmd),
spi_if => spi_vvc_if,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
-- Store the result
work.td_vvc_entity_support_pkg.store_result( result_queue => result_queue,
cmd_idx => v_cmd.cmd_idx,
result => v_result );
else -- attempted slave transmit when in master mode
alert(note, "Slave transmit and receive called when VVC is in master mode.", C_SCOPE);
end if;
when SLAVE_TRANSMIT_AND_CHECK =>
transaction_info.tx_data(GC_DATA_WIDTH-1 downto 0) := v_cmd.data(GC_DATA_WIDTH-1 downto 0);
-- Normalise data
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", "spi_slave_transmit_and_check() called with to wide data. " & v_cmd.msg);
if not GC_MASTER_MODE then
spi_slave_transmit_and_check(tx_data => v_normalised_data,
data_exp => v_cmd.data_exp(GC_DATA_WIDTH-1 downto 0),
msg => format_msg(v_cmd),
spi_if => spi_vvc_if,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
else -- attempted slave transmit when in master mode
alert(error, "Slave transmit and check called when VVC is in master mode.", C_SCOPE);
end if;
when SLAVE_TRANSMIT_ONLY =>
transaction_info.tx_data(GC_DATA_WIDTH-1 downto 0) := v_cmd.data(GC_DATA_WIDTH-1 downto 0);
-- Normalise data
v_normalised_data := normalize_and_check(v_cmd.data, v_normalised_data, ALLOW_WIDER_NARROWER, "data", "shared_vvc_cmd.data", "spi_slave_transmit() called with to wide data. " & v_cmd.msg);
if not GC_MASTER_MODE then -- slave transmit
-- Call the corresponding procedure in the BFM package.
spi_slave_transmit(tx_data => v_normalised_data,
msg => format_msg(v_cmd),
spi_if => spi_vvc_if,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
else -- attempted slave transmit when in master mode
alert(error, "Slave transmit called when VVC is in master mode.", C_SCOPE);
end if;
when SLAVE_RECEIVE_ONLY =>
if not GC_MASTER_MODE then -- slave receive
-- Call the corresponding procedure in the BFM package.
spi_slave_receive(rx_data => v_result(GC_DATA_WIDTH-1 downto 0),
msg => format_msg(v_cmd),
spi_if => spi_vvc_if,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
-- Store the result
work.td_vvc_entity_support_pkg.store_result(result_queue => result_queue,
cmd_idx => v_cmd.cmd_idx,
result => v_result);
else -- attempted slave receive when in master mode
alert(error, "Slave receive called when VVC is in master mode.", C_SCOPE);
end if;
when SLAVE_CHECK_ONLY =>
-- Normalise data
v_normalised_data := normalize_and_check(v_cmd.data_exp, v_normalised_data, ALLOW_WIDER_NARROWER, "data_exp", "shared_vvc_cmd.data_exp", "spi_slave_check() called with to wide data. " & v_cmd.msg);
if not GC_MASTER_MODE then -- slave check
-- Call the corresponding procedure in the BFM package.
spi_slave_check(data_exp => v_normalised_data,
msg => format_msg(v_cmd),
spi_if => spi_vvc_if,
alert_level => v_cmd.alert_level,
scope => C_SCOPE,
msg_id_panel => vvc_config.msg_id_panel,
config => vvc_config.bfm_config);
else -- attempted slave check when in master mode
alert(error, "Slave check called when VVC is in master mode.", C_SCOPE);
end if;
-- UVVM common operations
--===================================
when INSERT_DELAY =>
log(ID_INSERTED_DELAY, "Running: " & to_string(v_cmd.proc_call) & " " & format_command_idx(v_cmd), C_SCOPE, vvc_config.msg_id_panel);
if v_cmd.gen_integer_array(0) = -1 then
-- Delay specified using time
wait for v_cmd.delay;
else
-- Delay specified using integer
wait for v_cmd.gen_integer_array(0) * vvc_config.bfm_config.spi_bit_time;
end if;
when others =>
tb_error("Unsupported local command received for execution: '" & to_string(v_cmd.operation) & "'", C_SCOPE);
end case;
if v_command_is_bfm_access then
v_timestamp_end_of_last_bfm_access := now;
v_timestamp_start_of_last_bfm_access := v_timestamp_start_of_current_bfm_access;
if ((vvc_config.inter_bfm_delay.delay_type = TIME_START2START) and
((now - v_timestamp_start_of_current_bfm_access) > vvc_config.inter_bfm_delay.delay_in_time)) then
alert(vvc_config.inter_bfm_delay.inter_bfm_delay_violation_severity, "BFM access exceeded specified start-to-start inter-bfm delay, " &
to_string(vvc_config.inter_bfm_delay.delay_in_time) & ".", C_SCOPE);
end if;
end if;
-- Reset terminate flag if any occurred
if (terminate_current_cmd.is_active = '1') then
log(ID_CMD_EXECUTOR, "Termination request received", C_SCOPE, vvc_config.msg_id_panel);
uvvm_vvc_framework.ti_vvc_framework_support_pkg.reset_flag(terminate_current_cmd);
end if;
last_cmd_idx_executed <= v_cmd.cmd_idx;
-- Reset the transaction info for waveview
transaction_info := C_TRANSACTION_INFO_DEFAULT;
end loop;
end process;
--========================================================================================================================
--===============================================================================================
-- Command termination handler
-- - Handles the termination request record (sets and resets terminate flag on request)
--===============================================================================================
cmd_terminator : uvvm_vvc_framework.ti_vvc_framework_support_pkg.flag_handler(terminate_current_cmd); -- flag: is_active, set, reset
--===============================================================================================
end behave;
|
mit
|
AndyMcC0/UVVM_All
|
bitvis_uart/src/uart_pkg.vhd
|
3
|
3191
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package uart_pkg is
function find_num_hits(
vector : std_logic_vector;
pattern : std_logic)
return integer;
function find_most_repeated_bit(
vector : std_logic_vector)
return std_logic;
function transient_error(
vector : std_logic_vector;
limit : integer)
return boolean;
function f_log2 (x : positive)
return natural;
function odd_parity (
signal data : std_logic_vector(7 downto 0))
return std_logic;
end package uart_pkg;
package body uart_pkg is
function find_num_hits(
vector : std_logic_vector;
pattern : std_logic)
return integer is
variable hitcount : natural := 0;
begin
for i in 0 to vector'length-1 loop
if (vector(i) = pattern) then
hitcount := hitcount+1;
end if;
end loop;
return hitcount;
end function;
function find_most_repeated_bit(
vector : std_logic_vector)
return std_logic is
begin
if (find_num_hits(vector,'1') >
find_num_hits(vector,'0')) then
return '1';
else
return '0';
end if;
end function;
function transient_error(
vector : std_logic_vector;
limit : integer)
return boolean is
begin
if ((find_num_hits(vector,'1') < limit) and
(find_num_hits(vector,'0') < limit)) then
return true;
else
return false;
end if;
end function;
function f_log2 (x : positive)
return natural is
variable i : natural;
begin
i := 0;
while (2**i < x) and i < 31 loop
i := i + 1;
end loop;
return i;
end function;
function odd_parity (
signal data : std_logic_vector(7 downto 0))
return std_logic is
variable odd : std_logic;
begin
odd := '1';
for i in data'range loop
odd := odd xor data(i);
end loop;
return odd;
end odd_parity;
end package body uart_pkg;
|
mit
|
Wynjones1/gbvhdl
|
synth/clock_gen.vhd
|
4
|
1024
|
library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
entity clk_gen is
generic( CLOCK_SPEED : integer := 50_000_000;
REQUIRED_HZ : integer := 1);
port( clk : in std_logic;
reset : in std_logic;
clk_out : out std_logic);
end;
architecture rtl of clk_gen is
constant COUNT_MAX : integer := CLOCK_SPEED / (REQUIRED_HZ * 2);
signal count : integer range 0 to COUNT_MAX - 1 := 0;
signal clk_s : std_logic;
begin
process(clk, reset)
begin
if reset = '1' then
count <= 0;
clk_s <= '0';
elsif rising_edge(clk) then
if count = COUNT_MAX - 1 then
count <= 0;
if clk_s = '1' then
clk_s <= '0';
else
clk_s <= '1';
end if;
else
count <= count + 1;
end if;
end if;
end process;
clk_out <= clk_s;
end architecture;
|
mit
|
elainemielas/CVUT_THESIS
|
Spartan-3E/switch_controller.vhd
|
1
|
1507
|
----------------------------------------------------------------------------------
-- Company: FIT CTU
-- Engineer: Elena Filipenkova
--
-- Create Date: 12:57:00 05/08/2015
-- Design Name: FPGA deska rizena procesorem
-- Module Name: switch_controller - Behavioral
-- Target Devices: Spartan-3E Starter Kit
-- Revision 0.01 - File Created
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity switch_controller is
generic(
rf_addr_w : integer := 5;
reg_width : integer := 32
);
port(
clk : in std_logic;
reset : in std_logic;
sw0 : in std_logic;
sw1 : in std_logic;
sw2 : in std_logic;
sw3 : in std_logic;
rf_data : in std_logic_vector(reg_width - 1 downto 0);
rf_addr : out std_logic_vector(rf_addr_w - 1 downto 0);
led : out std_logic_vector(3 downto 0)
);
end switch_controller;
architecture Behavioral of switch_controller is
begin
rf_addr <= "01010";
process(clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
led(3 downto 0) <= "0000";
else
if rf_data(3) = '1' then
led(0) <= sw0;
else
led(0) <= '0';
end if;
if rf_data(7) = '1' then
led(1) <= sw1;
else
led(1) <= '0';
end if;
if rf_data(11) = '1' then
led(2) <= sw2;
else
led(2) <= '0';
end if;
if rf_data(15) = '1' then
led(3) <= sw3;
else
led(3) <= '0';
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
wltr/cern-fgclite
|
nanofip_fpga/src/rtl/nanofip/wf_fd_receiver.vhd
|
1
|
14438
|
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- wf_fd_receiver |
-- |
---------------------------------------------------------------------------------------------------
-- File wf_fd_receiver.vhd |
-- |
-- Description The unit groups the main actions that regard FIELDRIVE data reception. |
-- It instantiates the units: |
-- |
-- o wf_rx_deserializer: for the formation of bytes of data to be provided to the: |
-- o wf_engine_control unit, for the contents of ID_DAT frames |
-- o wf_cons_bytes_processor unit, for the contents of consumed|
-- RP_DAT frames |
-- |
-- o wf_rx_osc : for the clock recovery |
-- |
-- o wf_rx_deglitcher : for the filtering of the input FD_RXD |
-- |
-- |
-- _________________________ _________________________ |
-- | | | | |
-- | wf_Consumption | | wf_engine_control | |
-- |_________________________| |_________________________| |
-- /\ /\ |
-- ___________________________________________________________ |
-- | wf_fd_revceiver | |
-- | _________ | |
-- | _______________________________________ | | | |
-- | | | | | | |
-- | | wf_rx_deserializer | | wf_rx | | |
-- | | | < | _osc | | |
-- | |_______________________________________| | | | |
-- | /\ |_________| | |
-- | _______________________________________ | |
-- | | | | |
-- | | wf_rx_deglitcher | | |
-- | |_______________________________________| | |
-- | | |
-- |___________________________________________________________| |
-- /\ |
-- ___________________________________________________________________ |
-- 0_____________________________FIELDBUS______________________________O |
-- |
-- |
-- Authors Pablo Alvarez Sanchez ([email protected]) |
-- Evangelia Gousiou ([email protected]) |
-- Date 15/02/2011 |
-- Version v0.01 |
-- Depends on wf_reset_unit |
-- wf_engine_control |
---------------- |
-- Last changes |
-- 02/2011 v0.01 EG First version |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for wf_fd_receiver
--=================================================================================================
entity wf_fd_receiver is port(
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; -- 40 MHZ clock
-- nanoFIP WorldFIP Settings
rate_i : in std_logic_vector (1 downto 0); -- WorldFIP bit rate
-- nanoFIP FIELDRIVE
fd_rxd_a_i : in std_logic; -- receiver data
-- Signal from the wf_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
-- Signal from the wf_engine_control unit
rx_rst_i : in std_logic; -- reset during production or
-- reset pulse when during reception a frame is rejected
-- by the engine_control (example: ID_DAT > 8 bytes,
-- RP_DAT > 133 bytes, wrong ID_DAT CTRL/ VAR/ SUBS bytes)
-- OUTPUTS
-- Signals to the wf_engine_control and wf_consumption
rx_byte_o : out std_logic_vector (7 downto 0); -- retrieved data byte
rx_byte_ready_p_o : out std_logic; -- pulse indicating a new retrieved data byte
rx_fss_crc_fes_ok_p_o : out std_logic; -- indication of a frame (ID_DAT or RP_DAT) with
-- correct FSS, FES & CRC; pulse upon FES detection
rx_crc_wrong_p_o : out std_logic; -- indication of a frame (ID_DAT or RP_DAT) with
-- wrong CRC; pulse upon FES detection
-- Signals to the wf_engine_control
rx_fss_received_p_o : out std_logic);-- pulse upon FSS detection (ID/ RP_DAT)
end entity wf_fd_receiver;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture struc of wf_fd_receiver is
signal s_rx_osc_rst, s_adjac_bits_window, s_signif_edge_window : std_logic;
signal s_sample_bit_p, s_sample_manch_bit_p : std_logic;
signal s_fd_rxd_filt, s_rxd_filt_edge_p : std_logic;
signal s_fd_rxd_filt_f_edge_p, s_fd_rxd_filt_r_edge_p : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- Deglitcher --
---------------------------------------------------------------------------------------------------
FIELDRIVE_Receiver_Deglitcher: wf_rx_deglitcher
port map(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
fd_rxd_a_i => fd_rxd_a_i,
-----------------------------------------------------------------
fd_rxd_filt_o => s_fd_rxd_filt,
fd_rxd_filt_edge_p_o => s_rxd_filt_edge_p,
fd_rxd_filt_f_edge_p_o => s_fd_rxd_filt_f_edge_p);
-----------------------------------------------------------------
s_fd_rxd_filt_r_edge_p <= s_rxd_filt_edge_p and (not s_fd_rxd_filt_f_edge_p);
---------------------------------------------------------------------------------------------------
-- Oscillator --
---------------------------------------------------------------------------------------------------
FIELDRIVE_Receiver_Oscillator: wf_rx_osc
port map(
uclk_i => uclk_i,
rate_i => rate_i,
nfip_rst_i => nfip_rst_i,
fd_rxd_edge_p_i => s_rxd_filt_edge_p,
rx_osc_rst_i => s_rx_osc_rst,
-----------------------------------------------------------------
rx_manch_clk_p_o => s_sample_manch_bit_p,
rx_bit_clk_p_o => s_sample_bit_p,
rx_signif_edge_window_o => s_signif_edge_window,
rx_adjac_bits_window_o => s_adjac_bits_window);
-----------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- Deserializer --
---------------------------------------------------------------------------------------------------
FIELDRIVE_Receiver_Deserializer: wf_rx_deserializer
port map(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
rx_rst_i => rx_rst_i,
sample_bit_p_i => s_sample_bit_p,
sample_manch_bit_p_i => s_sample_manch_bit_p,
signif_edge_window_i => s_signif_edge_window,
adjac_bits_window_i => s_adjac_bits_window,
fd_rxd_f_edge_p_i => s_fd_rxd_filt_f_edge_p,
fd_rxd_r_edge_p_i => s_fd_rxd_filt_r_edge_p,
fd_rxd_i => s_fd_rxd_filt,
-----------------------------------------------------------------
byte_ready_p_o => rx_byte_ready_p_o,
byte_o => rx_byte_o,
fss_crc_fes_ok_p_o => rx_fss_crc_fes_ok_p_o,
rx_osc_rst_o => s_rx_osc_rst,
fss_received_p_o => rx_fss_received_p_o,
crc_wrong_p_o => rx_crc_wrong_p_o);
-----------------------------------------------------------------
end architecture struc;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
|
mit
|
wltr/cern-fgclite
|
nanofip_fpga/src/rtl/nanofip/wf_tx_osc.vhd
|
1
|
12737
|
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- wf_tx_osc |
-- |
---------------------------------------------------------------------------------------------------
-- File wf_tx_osc.vhd |
-- |
-- Description Generation of the clock signals needed for the FIELDRIVE transmission. |
-- |
-- The unit generates the nanoFIP FIELDRIVE output FD_TXCK (line driver half bit |
-- clock) and the nanoFIP internal signal tx_sched_p_buff: |
-- |
-- uclk : _|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-|_|-| |
-- FD_TXCK : _____|--------...--------|________...________|--------...--- |
-- tx_sched_p_buff(3): 0 0 0 1 0 0 0 1 |
-- tx_sched_p_buff(2): 0 0 1 0 0 0 1 0 |
-- tx_sched_p_buff(1): 0 1 0 0 0 1 0 0 |
-- tx_sched_p_buff(0): 1 0 0 0 1 0 0 0 |
-- |
-- Authors Pablo Alvarez Sanchez ([email protected]) |
-- Evangelia Gousiou ([email protected]) |
-- Date 14/02/2011 |
-- Version v0.04 |
-- Depends on wf_reset_unit |
---------------- |
-- Last changes |
-- 08/2009 v0.01 PS Entity Ports added, start of architecture content |
-- 07/2010 v0.02 EG tx counter changed from 20 bits signed, to 11 bits unsigned; |
-- c_TX_SCHED_BUFF_LGTH got 1 bit more |
-- 12/2010 v0.03 EG code cleaned-up |
-- 01/2011 v0.04 EG wf_tx_osc as different unit; use of wf_incr_counter;added tx_osc_rst_p_i
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for wf_tx_osc
--=================================================================================================
entity wf_tx_osc is
port (
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; -- 40 MHz clock
rate_i : in std_logic_vector (1 downto 0); -- WorldFIP bit rate
-- Signal from the wf_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
-- Signals from the wf_engine_control
tx_osc_rst_p_i : in std_logic; -- transmitter timeout
-- OUTPUTS
-- nanoFIP FIELDRIVE output
tx_clk_o : out std_logic; -- line driver half bit clock
-- Signal to the wf_tx_serializer unit
tx_sched_p_buff_o : out std_logic_vector (c_TX_SCHED_BUFF_LGTH -1 downto 0));
-- buffer of pulses used for the scheduling
-- of the actions of the wf_tx_serializer
end entity wf_tx_osc;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of wf_tx_osc is
-- transmission periods counter
signal s_period_c, s_period : unsigned (c_PERIODS_COUNTER_LGTH -1 downto 0);
signal s_one_forth_period : unsigned (c_PERIODS_COUNTER_LGTH -1 downto 0);
signal s_period_c_is_full, s_period_c_reinit : std_logic;
-- clocks
signal s_tx_clk_d1, s_tx_clk, s_tx_clk_p : std_logic;
signal s_tx_sched_p_buff : std_logic_vector (c_TX_SCHED_BUFF_LGTH-1 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- Periods Counter --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_period <= c_BIT_RATE_UCLK_TICKS(to_integer(unsigned(rate_i)));-- # uclk ticks for a
-- transmission period
s_one_forth_period <= s_period srl 2; -- 1/4 s_period
s_period_c_is_full <= '1' when s_period_c = s_period -1 else '0'; -- counter full
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of a wf_incr_counter counting transmission periods.
tx_periods_count: wf_incr_counter
generic map(g_counter_lgth => c_PERIODS_COUNTER_LGTH)
port map(
uclk_i => uclk_i,
counter_reinit_i => s_period_c_reinit,
counter_incr_i => '1',
counter_is_full_o => open,
------------------------------------------
counter_o => s_period_c);
------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- counter reinitialized : if the nfip_rst_i is active or
-- if the tx_osc_rst_p_i is active or
-- if it fills up
s_period_c_reinit <= nfip_rst_i or tx_osc_rst_p_i or s_period_c_is_full;
---------------------------------------------------------------------------------------------------
-- Clocks Construction --
---------------------------------------------------------------------------------------------------
-- Concurrent signals assignments and a synchronous process that use
-- the s_period_c to construct the tx_clk_o clock and the buffer of pulses tx_sched_p_buff_o.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Creation of the clock for the transmitter with period: 1/2 transmission period
s_tx_clk <= '1' when ((s_period_c < s_one_forth_period) or
((s_period_c > (2*s_one_forth_period)-1) and
(s_period_c < 3*s_one_forth_period)))
else '0';
-- transm. period : _|-----------|___________|--
-- tx_counter : 0 1/4 1/2 3/4 1
-- s_tx_clk : _|-----|_____|-----|_____|--
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Edge detector for s_tx_clk
s_tx_clk_p <= s_tx_clk and (not s_tx_clk_d1);
-- s_tx_clk : _|-----|_____|-----|_____
-- tx_clk_o/ s_tx_clk_d1: ___|-----|_____|-----|___
-- not s_tx_clk_d1 : ---|_____|-----|_____|---
-- s_tx_clk_p : _|-|___|-|___|-|___|-|___
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
clk_Signals_Construction: process (uclk_i)
begin
if rising_edge (uclk_i) then
if (nfip_rst_i = '1') or (tx_osc_rst_p_i = '1') then
s_tx_sched_p_buff <= (others => '0');
s_tx_clk_d1 <= '0';
else
s_tx_clk_d1 <= s_tx_clk;
s_tx_sched_p_buff <= s_tx_sched_p_buff (s_tx_sched_p_buff'left-1 downto 0) & s_tx_clk_p;
-- buffering of the s_tx_clk_p pulses
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Output signals
tx_clk_o <= s_tx_clk_d1;
tx_sched_p_buff_o <= s_tx_sched_p_buff;
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
|
mit
|
wltr/cern-fgclite
|
critical_fpga/src/rtl/cf/xf.vhd
|
1
|
8861
|
-------------------------------------------------------------------------------
--! @file xf.vhd
--! @author Johannes Walter <[email protected]>
--! @copyright CERN TE-EPC-CCE
--! @date 2014-07-08
--! @brief Auxiliary FPGA communication.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.xf_pkg.all;
use work.nf_pkg.all;
--! @brief Entity declaration of xf
--! @details
--! This component handles the NanoFIP communication and provides a
--! synchronization mechanism with the field-bus cycle.
entity xf is
port (
--! @name Clock and resets
--! @{
--! System clock
clk_i : in std_ulogic;
--! Asynchronous active-low reset
rst_asy_n_i : in std_ulogic;
--! Synchronous active-high reset
rst_syn_i : in std_ulogic;
--! @}
--! @name Auxiliary FPGA interface
--! @{
--! Inputs
xf_i : in xf_in_t;
--! Outputs
xf_o : out xf_out_t;
--! @}
--! @name Internal interface
--! @{
--! Millisecond strobe indicating start of cycle
ms_0_strobe_i : in std_ulogic;
--! Millisecond strobe indicating start of second millisecond
ms_1_strobe_i : in std_ulogic;
--! Commands
command_i : in nf_command_t;
--! @}
--! @name Auxiliary FPGA data
--! @{
--! DIM analogue data
dim_o : out std_ulogic_vector(19 downto 0);
--! DIM analogue data enable
dim_en_o : out std_ulogic;
--! DIM trigger number
dim_trig_num_o : out std_ulogic_vector(3 downto 0);
--! DIM latched trigger
dim_trig_lat_o : out std_ulogic;
--! DIM unlatched trigger
dim_trig_unl_o : out std_ulogic;
--! Backplane type
backplane_type_o : out std_ulogic_vector(7 downto 0);
--! Backplane type enable
backplane_type_en_o : out std_ulogic;
--! XF and PF versions
version_xfpf_o : out std_ulogic_vector(7 downto 0);
--! XF and PF versions enable
version_xfpf_en_o : out std_ulogic;
--! Single-event upset (SEU) count
seu_count_o : out std_ulogic_vector(7 downto 0);
--! Single-event upset (SEU) count enable
seu_count_en_o : out std_ulogic;
--! 1-wire scan busy
ow_scan_busy_o : out std_ulogic;
--! @}
--! @name DIM data
--! @{
--! Address
dim_addr_i : in std_ulogic_vector(6 downto 0);
--! Read enable
dim_rd_en_i : in std_ulogic;
--! Data output
dim_data_o : out std_ulogic_vector(15 downto 0);
--! Data output enable
dim_data_en_o : out std_ulogic;
--! @}
--! @name One-wire data
--! @{
--! Address
ow_addr_i : in std_ulogic_vector(5 downto 0);
--! Read enable
ow_rd_en_i : in std_ulogic;
--! Data output
ow_data_o : out std_ulogic_vector(79 downto 0);
--! Data output enable
ow_data_en_o : out std_ulogic);
--! @}
end entity xf;
--! RTL implementation of xf
architecture rtl of xf is
---------------------------------------------------------------------------
--! @name Internal Registers
---------------------------------------------------------------------------
--! @{
signal ow_scan_busy : std_ulogic;
signal dim_trigger : std_ulogic;
signal dim_reset : std_ulogic;
signal ow_scan : std_ulogic;
signal ow_bus_select : std_ulogic_vector(2 downto 0);
--! @}
---------------------------------------------------------------------------
--! @name Internal Wires
---------------------------------------------------------------------------
--! @{
signal xf_rx_data_0 : std_ulogic_vector(41 downto 0);
signal xf_rx_data_en_0 : std_ulogic;
signal xf_rx_error_0 : std_ulogic;
signal xf_rx_data_1 : std_ulogic_vector(83 downto 0);
signal xf_rx_data_en_1 : std_ulogic;
signal xf_rx_error_1 : std_ulogic;
signal dim_addr : std_ulogic_vector(6 downto 0);
signal ow_addr : std_ulogic_vector(5 downto 0);
--! @}
begin -- architecture rtl
---------------------------------------------------------------------------
-- Outputs
---------------------------------------------------------------------------
xf_o.dim_trig <= dim_trigger;
xf_o.dim_rst <= dim_reset;
xf_o.ow_trig <= ow_scan;
xf_o.ow_bus_select <= ow_bus_select;
backplane_type_o <= "00" & xf_rx_data_0(13 downto 8);
backplane_type_en_o <= xf_rx_data_en_0;
version_xfpf_o <= xf_rx_data_0(7 downto 0);
version_xfpf_en_o <= xf_rx_data_en_0;
seu_count_o <= xf_rx_data_0(21 downto 14);
seu_count_en_o <= xf_rx_data_en_0 when dim_addr = "0000000" else '0';
ow_scan_busy_o <= ow_scan_busy;
dim_o <= xf_rx_data_0(41 downto 22);
dim_en_o <= xf_rx_data_en_0 and xf_rx_data_0(36); -- only save analogue values
dim_trig_num_o <= xf_rx_data_0(41 downto 38);
dim_trig_lat_o <= xf_rx_data_en_0 when (xf_rx_data_0(37) = '1' and xf_rx_data_0(36 downto 34) = "010") else '0';
dim_trig_unl_o <= xf_rx_data_en_0 when (xf_rx_data_0(37) = '1' and xf_rx_data_0(36) = '1') else '0';
---------------------------------------------------------------------------
-- Signal Assignments
---------------------------------------------------------------------------
dim_addr <= xf_rx_data_0(41 downto 38) & xf_rx_data_0(36 downto 34);
ow_addr <= "00" & xf_rx_data_1(83 downto 80);
---------------------------------------------------------------------------
-- Instances
---------------------------------------------------------------------------
--! 1st 3-wire serial receiver from XF
xf_rx_inst_0 : entity work.serial_3wire_rx
generic map (
data_width_g => 42)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
rx_frame_i => xf_i.rx_frame(0),
rx_bit_en_i => xf_i.rx_bit_en(0),
rx_i => xf_i.rx(0),
data_o => xf_rx_data_0,
data_en_o => xf_rx_data_en_0,
error_o => xf_rx_error_0);
--! 2nd 3-wire serial receiver from XF
xf_rx_inst_1 : entity work.serial_3wire_rx
generic map (
data_width_g => 84)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
rx_frame_i => xf_i.rx_frame(1),
rx_bit_en_i => xf_i.rx_bit_en(1),
rx_i => xf_i.rx(1),
data_o => xf_rx_data_1,
data_en_o => xf_rx_data_en_1,
error_o => xf_rx_error_1);
--! DIM pages
dim_page_inst : entity work.two_port_ram_tmr
generic map (
depth_g => 128,
width_g => 16)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
wr_addr_i => dim_addr,
wr_en_i => xf_rx_data_en_0,
wr_data_i => xf_rx_data_0(37 downto 22),
wr_done_o => open,
wr_busy_o => open,
rd_addr_i => dim_addr_i,
rd_en_i => dim_rd_en_i,
rd_data_o => dim_data_o,
rd_data_en_o => dim_data_en_o,
rd_busy_o => open);
--! One-wire pages
ow_page_inst : entity work.two_port_ram_tmr
generic map (
depth_g => 64,
width_g => 80)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
wr_addr_i => ow_addr,
wr_en_i => xf_rx_data_en_1,
wr_data_i => xf_rx_data_1(79 downto 0),
wr_done_o => open,
wr_busy_o => open,
rd_addr_i => ow_addr_i,
rd_en_i => ow_rd_en_i,
rd_data_o => ow_data_o,
rd_data_en_o => ow_data_en_o,
rd_busy_o => open);
---------------------------------------------------------------------------
-- Registers
---------------------------------------------------------------------------
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
dim_trigger <= '0';
ow_scan_busy <= '0';
dim_reset <= '0';
ow_scan <= '0';
ow_bus_select <= (others => '0');
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
else
if ms_0_strobe_i = '1' then
dim_reset <= command_i.dim_reset;
ow_scan <= command_i.ow_scan;
ow_bus_select <= command_i.ow_bus_select;
end if;
if ms_0_strobe_i = '1' then
dim_trigger <= '1';
elsif ms_1_strobe_i = '1' then
dim_trigger <= '0';
end if;
if command_i.ow_scan = '1' then
ow_scan_busy <= '1';
elsif xf_rx_data_en_1 = '1' then
ow_scan_busy <= '0';
end if;
end if;
end if;
end process regs;
end architecture rtl;
|
mit
|
dtysky/LD3320_AXI
|
src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_gen_generic_cstr.vhd
|
2
|
136312
|
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`protect end_protected
|
mit
|
dtysky/LD3320_AXI
|
src/VOICE_ROM_INIT/blk_mem_gen_v8_2/hdl/blk_mem_gen_ecc_encoder.vhd
|
2
|
20893
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13728)
`protect data_block
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`protect end_protected
|
mit
|
dtysky/LD3320_AXI
|
src/LIST/blk_mem_gen_v8_2/hdl/blk_mem_gen_ecc_encoder.vhd
|
2
|
20893
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13728)
`protect data_block
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`protect end_protected
|
mit
|
dtysky/LD3320_AXI
|
src/LIST/LIST_funcsim.vhdl
|
1
|
47409
|
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.2 (win64) Build 928826 Thu Jun 5 18:21:07 MDT 2014
-- Date : Wed Sep 10 03:38:08 2014
-- Host : Dtysky running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- d:/spira_heaven/0-myworks/ld3320_axi/ld3320_axi_1.0/src/LIST/LIST_funcsim.vhdl
-- Design : LIST
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity LIST_blk_mem_gen_prim_wrapper is
port (
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
clkb : in STD_LOGIC;
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of LIST_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end LIST_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of LIST_blk_mem_gen_prim_wrapper is
signal \n_0_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_10_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_11_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_12_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_13_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_16_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_17_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_18_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_19_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_1_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_20_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_21_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_24_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_25_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_26_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_27_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_28_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_29_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_2_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_32_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_33_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_34_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_35_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_3_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_4_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_5_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_8_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_9_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "SDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 0,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(13) => '0',
ADDRARDADDR(12 downto 5) => addrb(7 downto 0),
ADDRARDADDR(4) => '0',
ADDRARDADDR(3) => '0',
ADDRARDADDR(2) => '0',
ADDRARDADDR(1) => '0',
ADDRARDADDR(0) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12 downto 5) => addra(7 downto 0),
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CLKARDCLK => clkb,
CLKBWRCLK => clka,
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9 downto 8) => dina(3 downto 2),
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9 downto 8) => dina(7 downto 6),
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1 downto 0) => dina(5 downto 4),
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(15) => \n_0_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(14) => \n_1_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(13) => \n_2_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(12) => \n_3_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(11) => \n_4_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(10) => \n_5_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(9 downto 8) => doutb(3 downto 2),
DOADO(7) => \n_8_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(6) => \n_9_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(5) => \n_10_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(4) => \n_11_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(3) => \n_12_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(2) => \n_13_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(1 downto 0) => doutb(1 downto 0),
DOBDO(15) => \n_16_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(14) => \n_17_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(13) => \n_18_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(12) => \n_19_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(11) => \n_20_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(10) => \n_21_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(9 downto 8) => doutb(7 downto 6),
DOBDO(7) => \n_24_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(6) => \n_25_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(5) => \n_26_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(4) => \n_27_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(3) => \n_28_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(2) => \n_29_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(1 downto 0) => doutb(5 downto 4),
DOPADOP(1) => \n_32_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOPADOP(0) => \n_33_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOPBDOP(1) => \n_34_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOPBDOP(0) => \n_35_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
ENARDEN => '1',
ENBWREN => wea(0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(3) => '1',
WEBWE(2) => '1',
WEBWE(1) => '1',
WEBWE(0) => '1'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity LIST_blk_mem_gen_prim_width is
port (
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
clkb : in STD_LOGIC;
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of LIST_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end LIST_blk_mem_gen_prim_width;
architecture STRUCTURE of LIST_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.LIST_blk_mem_gen_prim_wrapper
port map (
addra(7 downto 0) => addra(7 downto 0),
addrb(7 downto 0) => addrb(7 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity LIST_blk_mem_gen_generic_cstr is
port (
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
clkb : in STD_LOGIC;
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of LIST_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end LIST_blk_mem_gen_generic_cstr;
architecture STRUCTURE of LIST_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.LIST_blk_mem_gen_prim_width
port map (
addra(7 downto 0) => addra(7 downto 0),
addrb(7 downto 0) => addrb(7 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity LIST_blk_mem_gen_top is
port (
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
clkb : in STD_LOGIC;
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of LIST_blk_mem_gen_top : entity is "blk_mem_gen_top";
end LIST_blk_mem_gen_top;
architecture STRUCTURE of LIST_blk_mem_gen_top is
begin
\valid.cstr\: entity work.LIST_blk_mem_gen_generic_cstr
port map (
addra(7 downto 0) => addra(7 downto 0),
addrb(7 downto 0) => addrb(7 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity LIST_blk_mem_gen_v8_2_synth is
port (
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
clkb : in STD_LOGIC;
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of LIST_blk_mem_gen_v8_2_synth : entity is "blk_mem_gen_v8_2_synth";
end LIST_blk_mem_gen_v8_2_synth;
architecture STRUCTURE of LIST_blk_mem_gen_v8_2_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.LIST_blk_mem_gen_top
port map (
addra(7 downto 0) => addra(7 downto 0),
addrb(7 downto 0) => addrb(7 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \LIST_blk_mem_gen_v8_2__parameterized0\ is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
douta : out STD_LOGIC_VECTOR ( 7 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 7 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 7 downto 0 );
sleep : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is "blk_mem_gen_v8_2";
attribute C_FAMILY : string;
attribute C_FAMILY of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is "zynq";
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is "zynq";
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is "./";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is "NONE";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 4;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 9;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is "no_coe_file_loaded";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is "LIST.mem";
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is "CE";
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 8;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 8;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 256;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 256;
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 8;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is "CE";
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 8;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 8;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 256;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 256;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 8;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is "ALL";
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is "1";
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is "Estimated Power for IP : 2.68455 mW";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of \LIST_blk_mem_gen_v8_2__parameterized0\ : entity is "yes";
end \LIST_blk_mem_gen_v8_2__parameterized0\;
architecture STRUCTURE of \LIST_blk_mem_gen_v8_2__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
douta(7) <= \<const0>\;
douta(6) <= \<const0>\;
douta(5) <= \<const0>\;
douta(4) <= \<const0>\;
douta(3) <= \<const0>\;
douta(2) <= \<const0>\;
douta(1) <= \<const0>\;
douta(0) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.LIST_blk_mem_gen_v8_2_synth
port map (
addra(7 downto 0) => addra(7 downto 0),
addrb(7 downto 0) => addrb(7 downto 0),
clka => clka,
clkb => clkb,
dina(7 downto 0) => dina(7 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity LIST is
port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 7 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
clkb : in STD_LOGIC;
addrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of LIST : entity is true;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of LIST : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of LIST : entity is "blk_mem_gen_v8_2,Vivado 2014.2";
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of LIST : entity is "LIST,blk_mem_gen_v8_2,{}";
attribute core_generation_info : string;
attribute core_generation_info of LIST : entity is "LIST,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=1,x_ipLanguage=VERILOG,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=1,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=LIST.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=256,C_READ_DEPTH_A=256,C_ADDRA_WIDTH=8,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=256,C_READ_DEPTH_B=256,C_ADDRB_WIDTH=8,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=0,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 2.68455 mW}";
end LIST;
architecture STRUCTURE of LIST is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_douta_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 8;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 8;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "0";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 2.68455 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "LIST.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 1;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 256;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 256;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 8;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 8;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 256;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 256;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 8;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 8;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of U0 : label is std.standard.true;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.\LIST_blk_mem_gen_v8_2__parameterized0\
port map (
addra(7 downto 0) => addra(7 downto 0),
addrb(7 downto 0) => addrb(7 downto 0),
clka => clka,
clkb => clkb,
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
dina(7 downto 0) => dina(7 downto 0),
dinb(7) => '0',
dinb(6) => '0',
dinb(5) => '0',
dinb(4) => '0',
dinb(3) => '0',
dinb(2) => '0',
dinb(1) => '0',
dinb(0) => '0',
douta(7 downto 0) => NLW_U0_douta_UNCONNECTED(7 downto 0),
doutb(7 downto 0) => doutb(7 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(7 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(7 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rstb => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31) => '0',
s_axi_araddr(30) => '0',
s_axi_araddr(29) => '0',
s_axi_araddr(28) => '0',
s_axi_araddr(27) => '0',
s_axi_araddr(26) => '0',
s_axi_araddr(25) => '0',
s_axi_araddr(24) => '0',
s_axi_araddr(23) => '0',
s_axi_araddr(22) => '0',
s_axi_araddr(21) => '0',
s_axi_araddr(20) => '0',
s_axi_araddr(19) => '0',
s_axi_araddr(18) => '0',
s_axi_araddr(17) => '0',
s_axi_araddr(16) => '0',
s_axi_araddr(15) => '0',
s_axi_araddr(14) => '0',
s_axi_araddr(13) => '0',
s_axi_araddr(12) => '0',
s_axi_araddr(11) => '0',
s_axi_araddr(10) => '0',
s_axi_araddr(9) => '0',
s_axi_araddr(8) => '0',
s_axi_araddr(7) => '0',
s_axi_araddr(6) => '0',
s_axi_araddr(5) => '0',
s_axi_araddr(4) => '0',
s_axi_araddr(3) => '0',
s_axi_araddr(2) => '0',
s_axi_araddr(1) => '0',
s_axi_araddr(0) => '0',
s_axi_arburst(1) => '0',
s_axi_arburst(0) => '0',
s_axi_arid(3) => '0',
s_axi_arid(2) => '0',
s_axi_arid(1) => '0',
s_axi_arid(0) => '0',
s_axi_arlen(7) => '0',
s_axi_arlen(6) => '0',
s_axi_arlen(5) => '0',
s_axi_arlen(4) => '0',
s_axi_arlen(3) => '0',
s_axi_arlen(2) => '0',
s_axi_arlen(1) => '0',
s_axi_arlen(0) => '0',
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2) => '0',
s_axi_arsize(1) => '0',
s_axi_arsize(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31) => '0',
s_axi_awaddr(30) => '0',
s_axi_awaddr(29) => '0',
s_axi_awaddr(28) => '0',
s_axi_awaddr(27) => '0',
s_axi_awaddr(26) => '0',
s_axi_awaddr(25) => '0',
s_axi_awaddr(24) => '0',
s_axi_awaddr(23) => '0',
s_axi_awaddr(22) => '0',
s_axi_awaddr(21) => '0',
s_axi_awaddr(20) => '0',
s_axi_awaddr(19) => '0',
s_axi_awaddr(18) => '0',
s_axi_awaddr(17) => '0',
s_axi_awaddr(16) => '0',
s_axi_awaddr(15) => '0',
s_axi_awaddr(14) => '0',
s_axi_awaddr(13) => '0',
s_axi_awaddr(12) => '0',
s_axi_awaddr(11) => '0',
s_axi_awaddr(10) => '0',
s_axi_awaddr(9) => '0',
s_axi_awaddr(8) => '0',
s_axi_awaddr(7) => '0',
s_axi_awaddr(6) => '0',
s_axi_awaddr(5) => '0',
s_axi_awaddr(4) => '0',
s_axi_awaddr(3) => '0',
s_axi_awaddr(2) => '0',
s_axi_awaddr(1) => '0',
s_axi_awaddr(0) => '0',
s_axi_awburst(1) => '0',
s_axi_awburst(0) => '0',
s_axi_awid(3) => '0',
s_axi_awid(2) => '0',
s_axi_awid(1) => '0',
s_axi_awid(0) => '0',
s_axi_awlen(7) => '0',
s_axi_awlen(6) => '0',
s_axi_awlen(5) => '0',
s_axi_awlen(4) => '0',
s_axi_awlen(3) => '0',
s_axi_awlen(2) => '0',
s_axi_awlen(1) => '0',
s_axi_awlen(0) => '0',
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2) => '0',
s_axi_awsize(1) => '0',
s_axi_awsize(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(7 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(7 downto 0),
s_axi_rdata(7 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(7 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(7) => '0',
s_axi_wdata(6) => '0',
s_axi_wdata(5) => '0',
s_axi_wdata(4) => '0',
s_axi_wdata(3) => '0',
s_axi_wdata(2) => '0',
s_axi_wdata(1) => '0',
s_axi_wdata(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
|
mit
|
wltr/cern-fgclite
|
nanofip_fpga/src/rtl/nanofip/wf_dualram_512x8_clka_rd_clkb_wr.vhd
|
1
|
8330
|
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- wf_dualram_512x8_clka_rd_clkb_wr |
-- |
---------------------------------------------------------------------------------------------------
-- File wf_dualram_512x8_clka_rd_clkb_wr.vhd |
-- |
-- Description The unit adds a layer over the dual port 512x8 memory, by disabling writing from |
-- one side and reading from the other. Finally from port A only reading is possible |
-- and from port B only writing. |
-- Commented in the unit is the memory triplication. Precision RadTol makes the |
-- triplication automatically; in Synplify the comments have to be removed. With the |
-- triplication each incoming byte is written at the same position in the three |
-- memories, whereas each outgoing one is the outcome of a majority voter. |
-- |
-- |
-- Authors Pablo Alvarez Sanchez ([email protected]) |
-- Evangelia Gousiou ([email protected]) |
-- Date 10/12/2010 |
-- Version v0.02 |
-- Depends on dualram_512x8.vhd |
---------------- |
-- Last changes |
-- 12/2010 v0.02 EG code cleaned-up+commented |
-- 11/2011 v0.03 EG removed generics! addr+data lgth already defined at the |
-- dualram_512x8 |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for wf_dualram_512x8_clka_rd_clkb_wr
--=================================================================================================
entity wf_dualram_512x8_clka_rd_clkb_wr is port(
-- INPUTS
-- Inputs concerning port A
clk_porta_i : in std_logic;
addr_porta_i : in std_logic_vector (8 downto 0);
-- Inputs concerning port B
clk_portb_i : in std_logic;
addr_portb_i : in std_logic_vector (8 downto 0);
data_portb_i : in std_logic_vector (7 downto 0);
write_en_portb_i : in std_logic;
-- OUTPUT
-- Output concerning port A
data_porta_o : out std_logic_vector (7 downto 0));
end wf_dualram_512x8_clka_rd_clkb_wr;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture syn of wf_dualram_512x8_clka_rd_clkb_wr is
signal s_one, s_rwB : std_logic;
signal s_zeros : std_logic_vector (7 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
s_one <= '1';
s_zeros <= (others => '0');
s_rwB <= not write_en_portb_i;
---------------------------------------------------------------------------------------------------
-- Port A used for reading only, port B for writing only.
-- for triplication: G_memory_triplication: for I in 0 to 2 generate
DualRam : dualram_512x8
port map(
DINA => s_zeros,
ADDRA => addr_porta_i,
RWA => s_one,
CLKA => clk_porta_i,
DINB => data_portb_i,
ADDRB => addr_portb_i,
RWB => s_rwB,
CLKB => clk_portb_i,
RESETn => s_one,
DOUTA => data_porta_o, -- for triplication: s_data_o_A_array(I)
DOUTB => open);
-- end generate;
---------------------------------------------------------------------------------------------------
-- for triplication: Combinatorial Majority_Voter
-- for triplication: Majority_Voter: data_porta_o <= (s_data_o_A_array(0) and s_data_o_A_array(1)) or
-- (s_data_o_A_array(1) and s_data_o_A_array(2)) or
-- (s_data_o_A_array(2) and s_data_o_A_array(0));
end syn;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
|
mit
|
wltr/cern-fgclite
|
nanofip_fpga/src/rtl/nanofip/wf_jtag_controller.vhd
|
1
|
26343
|
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- wf_jtag_controller |
-- |
---------------------------------------------------------------------------------------------------
-- File wf_jtag_controller.vhd |
-- |
-- Description After the reception and validation of a consumed var_4 RP_DAT frame, the unit |
-- is responsible for driving the "nanoFIP, User Interface, JTAG Controller" signals |
-- JC_TCK, JC_TMS, JC_TDI and for sampling the JC_TDO input. |
-- |
-- o JC_TCK is a 5 MHz clock generated by the 40 MHz uclk; a cycle is created for |
-- every JC_TMS/ JC_TDI pair. |
-- |
-- o JC_TMS and JC_TDI are being retreived from the JC_consumed memory and are |
-- put to the corresponding outputs on each falling edge of the JC_TCK. |
-- |
-- o The first and second data bytes of the JC_consumed memory do not contain |
-- JC_TMS/ JC_TDI bits, but are used to indicate, in big endian order, the |
-- amount of JC_TMS and JC_TDI bits that have to be output. |
-- |
-- o the JC_TDO input is sampled on the rising edge of JC_TCK; only the last |
-- sampled JC_TDO bit is significant. It is registered and sent to the |
-- wf_production unit for it to be delivered in the next produced var_5 frame. |
-- |
-- |
-- Authors Pablo Alvarez Sanchez ([email protected]) |
-- Evangelia Gousiou ([email protected]) |
-- Date 09/2011 |
-- Version v0.02 |
-- Depends on wf_reset_unit |
-- wf_consumption |
---------------- |
-- Last changes |
-- 07/07/2011 v0.01 EG First version |
-- 09/2011 v0.02 EG added counter for counting the outgoing TMS/TDI bits; combinatorial |
-- was too heavy; changed a bit state machine to include counter |
-- put session_timedout in the synchronous FSM process |
-- 11/2011 v0.021 EG timeout counter has different size (constant added) |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for wf_jtag_controller
--=================================================================================================
entity wf_jtag_controller is port(
-- INPUTS
-- nanoFIP User Interface, General signal
uclk_i : in std_logic; -- 40 MHz clock
-- nanoFIP User Interface, JTAG Controller signal
jc_tdo_i : in std_logic; -- JTAG TDO input
-- Signal from the wf_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
-- Signals from the wf_consumption unit
jc_start_p_i : in std_logic; -- pulse upon validation of a var_4 RP_DAT frame
jc_mem_data_i : in std_logic_vector (7 downto 0); -- byte retreived from the JC_consumed memory
-- OUTPUTS
-- nanoFIP User Interface, JTAG Controller signals
jc_tms_o : out std_logic; -- JTAG TMS output
jc_tdi_o : out std_logic; -- JTAG TDI output
jc_tck_o : out std_logic; -- JTAG TCK output
-- Signal to the wf_production unit
jc_tdo_byte_o : out std_logic_vector (7 downto 0); -- byte containing the TDO sample for the next var_5
-- Signal to the wf_consumption unit
jc_mem_adr_rd_o : out std_logic_vector (8 downto 0));-- address of byte to be retreived from the JC_cons memory
end entity wf_jtag_controller;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of wf_jtag_controller is
-- FSM
type jc_st_t is (IDLE, GET_BYTE, PLAY_BYTE, SET_ADDR);
signal jc_st, nx_jc_st : jc_st_t;
signal s_idle, s_play_byte, s_set_addr : std_logic;
signal s_not_play_byte : std_logic;
signal s_session_timedout : std_logic;
-- bytes counter
signal s_bytes_c, s_bytes_c_d1 : unsigned (6 downto 0);
-- retrieval of the number of TMS/ TDI bits that have to be delivered
signal s_frame_bits_lsb, s_frame_bits_msb : std_logic_vector (7 downto 0);
signal s_frame_bits : unsigned (15 downto 0);
-- number of TMS/ TDI bits delivered so far
signal s_bits_so_far : unsigned (15 downto 0);
-- TCK generation
signal s_tck, s_tck_c_is_full : std_logic;
signal s_tck_r_edge_p, s_tck_f_edge_p : std_logic;
signal s_tck_c, s_tck_period, s_tck_four_periods : unsigned (c_FOUR_JC_TCK_C_LGTH-1 downto 0);
signal s_tck_half_period, s_tck_quarter_period : unsigned (c_FOUR_JC_TCK_C_LGTH-1 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- FSM --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- JTAG Controller FSM: the state machine is divided in three parts (a clocked process
-- to store the current state, a combinatorial process to manage state transitions and finally a
-- combinatorial process to manage the output signals), which are the three processes that follow.
-- After the reception of a var_4 RP_DAT frame the FSM starts retrieving one by one bytes from
-- the JC_consumed memory. The first two bytes concatenated in big endian encoding indicate the
-- total amount of TMS/ TDI bits that have to be retrieved and output.
-- The rest of the bytes contain the TMS/ TDI bits.
-- The FSM goes back to IDLE if the counter that counts the amount the bits that have been output
-- reaches the total amount.
-- To add a robust layer of protection to the FSM, we have implemented a counter, dependent only on
-- the system clock, that from any state can bring the FSM back to IDLE. A frame with the maximum
-- number of TMS/ TDI bits needs: 122 bytes * ((4 * JC_TCK) + 2 uclk) seconds to be treated.
-- For a 5 MHz JC_TCK clock this is 103.7 us. We use a counter of c_JC_TIMEOUT_C_LGTH = 13 bits
-- which means that the FSM is reset if 204.8 us have passed since it has left the IDLE state.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Synchronous process JC_FSM_Sync: storage of the current state of the FSM
JC_FSM_Sync: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' or s_session_timedout = '1' then
jc_st <= IDLE;
else
jc_st <= nx_jc_st;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process JC_FSM_Comb_State_Transitions: Definition of the state
-- transitions of the FSM.
JC_FSM_Comb_State_Transitions: process (jc_st, s_bytes_c, s_frame_bits,s_bits_so_far, jc_start_p_i,
s_tck_c_is_full, s_tck_r_edge_p, s_tck_f_edge_p)
begin
case jc_st is
when IDLE =>
if jc_start_p_i = '1' then -- consumed var_4 frame validated
nx_jc_st <= SET_ADDR;
else
nx_jc_st <= IDLE;
end if;
when SET_ADDR =>
nx_jc_st <= GET_BYTE; -- 1 uclk cycle for the setting of the memory
-- address; byte available at the next cycle
when GET_BYTE =>
if s_bytes_c < 2 then -- 2 first bytes: amount of JC_TMS & JC_TDI bits
nx_jc_st <= SET_ADDR;
else -- the rest of the bytes have to be "played"
nx_jc_st <= PLAY_BYTE;
end if;
when PLAY_BYTE =>
if s_frame_bits <= 0 or s_frame_bits > c_MAX_FRAME_BITS then
nx_jc_st <= IDLE; -- outside expected limits
elsif s_frame_bits > s_bits_so_far then -- still available bits to go..
if s_tck_c_is_full = '1' then-- byte completed; a new one has
nx_jc_st <= SET_ADDR; -- to be retrieved
else -- byte being output
nx_jc_st <= PLAY_BYTE;
end if;
else -- last bit
if s_tck_r_edge_p = '1' or s_tck_f_edge_p = '1' then
nx_jc_st <= IDLE; -- wait until the completion of a JC_TCK cycle
else
nx_jc_st <= PLAY_BYTE;
end if;
end if;
when OTHERS =>
nx_jc_st <= IDLE;
end case;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process JC_FSM_Comb_Output_Signals: Definition of the output signals of the FSM.
JC_FSM_Comb_Output_Signals: process (jc_st)
begin
case jc_st is
when IDLE =>
-----------------------------
s_idle <= '1';
-----------------------------
s_set_addr <= '0';
s_play_byte <= '0';
when SET_ADDR =>
s_idle <= '0';
-----------------------------
s_set_addr <= '1';
-----------------------------
s_play_byte <= '0';
when GET_BYTE =>
s_idle <= '0';
s_set_addr <= '0';
s_play_byte <= '0';
when PLAY_BYTE =>
s_idle <= '0';
s_set_addr <= '0';
-----------------------------
s_play_byte <= '1';
-----------------------------
when OTHERS =>
-----------------------------
s_idle <= '1';
-----------------------------
s_set_addr <= '0';
s_play_byte <= '0';
end case;
end process;
---------------------------------------------------------------------------------------------------
-- JC_TCK generation --
---------------------------------------------------------------------------------------------------
-- Instantiation of a wf_incr_counter used for the generation of the JC_TCK output clock.
-- The counter is filled up after having counted 4 JC_TCK periods; this corresponds to the amount
-- of periods needed for outputting a full JC_TMS/ JC_TDI byte.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
JC_TCK_periods_counter: wf_incr_counter
generic map(g_counter_lgth => c_FOUR_JC_TCK_C_LGTH)
port map(
uclk_i => uclk_i,
counter_reinit_i => s_not_play_byte,
counter_incr_i => s_play_byte,
counter_is_full_o => s_tck_c_is_full,
------------------------------------------
counter_o => s_tck_c);
------------------------------------------
s_not_play_byte <= not s_play_byte;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
JC_TCK_Construction: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_tck <= '1';
else
if s_tck_f_edge_p = '1' or s_tck_r_edge_p = '1' then
s_tck <= not s_tck;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_tck_four_periods <= (others => '1'); -- # uclk ticks for 4 JC_TCK periods i.e delivery of 1 byte
s_tck_period <= (s_tck_four_periods srl 2)+1; -- # uclk ticks for 1 JC_TCK period
s_tck_half_period <= (s_tck_four_periods srl 3)+1; -- # uclk ticks for 1/2 JC_TCK period
s_tck_quarter_period <= (s_tck_four_periods srl 4)+1; -- # uclk ticks for 1/4 JC_TCK period
-- s_tck_four_periods : >------------------------<
-- s_tck_period : >-----<
-- s_tck_half_period : >--<
-- s_tck_quarter_period: >-<
-- s_tck : -|__|--|__|--|__|--|__|-
s_tck_f_edge_p <= '1' when (s_tck_c = s_tck_quarter_period) or
(s_tck_c = (2*s_tck_half_period) +s_tck_quarter_period) or
(s_tck_c = (4*s_tck_half_period) +s_tck_quarter_period) or
(s_tck_c = (6*s_tck_half_period) +s_tck_quarter_period) else '0';
s_tck_r_edge_p <= '1' when (s_tck_c = s_tck_half_period+s_tck_quarter_period) or
(s_tck_c = (3*s_tck_half_period) +s_tck_quarter_period) or
(s_tck_c = (5*s_tck_half_period) +s_tck_quarter_period) or
(s_tck_c = (7*s_tck_half_period) +s_tck_quarter_period) else '0';
jc_tck_o <= s_tck;
---------------------------------------------------------------------------------------------------
-- Bytes counter --
---------------------------------------------------------------------------------------------------
-- Instantiation of a wf_incr_counter for the counting of the bytes that are being retreived from
-- the JC_cons memory.
JC_bytes_counter: wf_incr_counter
generic map(g_counter_lgth => 7)
port map(
uclk_i => uclk_i,
counter_reinit_i => s_idle,
counter_incr_i => s_set_addr,
counter_is_full_o => open,
------------------------------------------
counter_o => s_bytes_c);
------------------------------------------
jc_mem_adr_rd_o <= std_logic_vector (resize((s_bytes_c + 2), jc_mem_adr_rd_o'length));
-- "+2" is bc the first 2 bytes in the memory (PDU_TYPE and LGTH) are not read
---------------------------------------------------------------------------------------------------
-- Delivered bits counter --
---------------------------------------------------------------------------------------------------
-- Creation of a counter counting the number of TMS and TDI bits that have been output.
-- The output of this counter, s_bits_so_far, could have been derived from the s_bytes_c with some
-- combinatorial logic, but then the timing performance was prohibiting.
JC_bits_counter: process (uclk_i)
begin
if rising_edge (uclk_i) then
if s_idle = '1' then
s_bits_so_far <= (others => '0');
elsif s_tck_f_edge_p = '1' then
s_bits_so_far <= s_bits_so_far + 2; -- 1 TMS + 1 TDI bits
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- Frame bits retrieval --
---------------------------------------------------------------------------------------------------
-- Construction of the 16 bits word that indicates the amount of TMS/ TDI bits that have to be
-- played from this frame. The word is the result of the big endian concatenation of the 1st and
-- 2nd data bytes from the memory.
Bits_Number_retrieval: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_bytes_c_d1 <= (others => '0');
s_frame_bits_msb <= (others => '0');
s_frame_bits_lsb <= (others => '0');
else
s_bytes_c_d1 <= s_bytes_c;
if s_set_addr = '1' and s_bytes_c_d1 = 0 then
s_frame_bits_msb <= jc_mem_data_i;
end if;
if s_set_addr = '1' and s_bytes_c_d1 = 1 then
s_frame_bits_lsb <= jc_mem_data_i;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
s_frame_bits <= unsigned (s_frame_bits_msb) & unsigned (s_frame_bits_lsb);
---------------------------------------------------------------------------------------------------
-- TMS and TDI player --
---------------------------------------------------------------------------------------------------
-- Delivery of the jc_tms_o and jc_tdi_o bits on the falling edge of the jc_tck_o clock.
-- At the "PLAY_BYTE" state of the FSM the incoming jc_mem_data_i byte is decomposed to 4 TMS and
-- 4 TDI bits; a pair of TMS/ TDI bits is output on every TCK falling edge.
JC_TMS_TDI_player: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
jc_tms_o <= '0';
jc_tdi_o <= '0';
elsif s_tck_f_edge_p = '1' then
if s_tck_c < (s_tck_period) then -- 1st JC_TMS/ JC_TDI pair
jc_tms_o <= jc_mem_data_i(7);
jc_tdi_o <= jc_mem_data_i(6);
elsif s_tck_c < (s_tck_period sll 1) then -- 2nd JC_TMS/ JC_TDI pair
jc_tms_o <= jc_mem_data_i(5);
jc_tdi_o <= jc_mem_data_i(4);
elsif s_tck_c < ((s_tck_period sll 1)+s_tck_period) then -- 3rd JC_TMS/ JC_TDI pair
jc_tms_o <= jc_mem_data_i(3);
jc_tdi_o <= jc_mem_data_i(2);
else
jc_tms_o <= jc_mem_data_i(1); -- 4th JC_TMS/ JC_TDI pair
jc_tdi_o <= jc_mem_data_i(0);
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- TDO sampler --
---------------------------------------------------------------------------------------------------
-- Sampling of the jc_tdo_i input on the rising edge of the jc_tck_o clock. Only the last sampled
-- bit is significant and is delivered.
-- Note: on the side of the target TAP, the jc_tdo should be provided on the falling edge of jc_tck;
-- a falling jc_tck edge comes many uclk cycles before a rising one, which is nanoFIP's sampling
-- moment for jc_tdo; therefore on the rising edges, jc_tdo is not expected to be metastable.
-- That is why we have decided not to synchronize the jc_tdo input.
JC_TDO_sampling: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
jc_tdo_byte_o <= (others => '0');
elsif s_tck_r_edge_p = '1' then
jc_tdo_byte_o <= "0000000" & jc_tdo_i;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- Independent Timeout Counter --
---------------------------------------------------------------------------------------------------
-- Instantiation of a wf_decr_counter relying only on the system clock, as an additional
-- way to go back to IDLE state, in case any other logic is being stuck. The timeout is 204.8 us.
Session_Timeout_Counter: wf_decr_counter
generic map(g_counter_lgth => c_JC_TIMEOUT_C_LGTH)
port map(
uclk_i => uclk_i,
counter_rst_i => nfip_rst_i,
counter_top_i => (others => '1'),
counter_load_i => s_idle,
counter_decr_i => '1', -- on each uclk tick
counter_o => open,
---------------------------------------------------
counter_is_zero_o => s_session_timedout);
---------------------------------------------------
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
|
mit
|
dtysky/LD3320_AXI
|
hdl/LD3320_AXI_v1_0_S00_AXI.vhd
|
1
|
22043
|
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
entity LD3320_AXI_v1_0_S00_AXI is
generic (
-- Users to add parameters here
constant Cmd_Start:std_logic_vector(31 downto 0):=x"00000001";
constant Cmd_Rqu:std_logic_vector(31 downto 0):=x"00000002";
constant Re_Success:std_logic_vector(7 downto 0):=x"01";
constant Re_Fail:std_logic_vector(7 downto 0):=x"02";
constant Re_Wait:std_logic_vector(7 downto 0):=x"03";
constant Ram_Init:std_logic_vector(7 downto 0):=x"01";
constant Ram_List:std_logic_vector(7 downto 0):=x"02";
constant Ram_Stop:std_logic_vector(7 downto 0):=x"03";
constant Ram_Re_Yes:std_logic_vector(7 downto 0):=x"01";
constant Ram_Re_No:std_logic_vector(7 downto 0):=x"02";
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 4
);
port (
-- Users to add ports here
inclk,inclk_n:in std_logic;
clk_voice:out std_logic;
n_wr,n_cs,n_rd,n_rst:out std_logic:='1';
n_int:in std_logic:='0';
add_en:out std_logic:='0';
data_voice:inout std_logic_vector(7 downto 0);
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end LD3320_AXI_v1_0_S00_AXI;
architecture arch_imp of LD3320_AXI_v1_0_S00_AXI is
component VOICE is
port
(
start:in std_logic;
inclk,inclk_n:in std_logic;
init_clk:in std_logic;
init_wea:in std_logic_vector(0 downto 0);
init_addr:in std_logic_vector(5 downto 0);
init_din:in std_logic_vector(15 downto 0);
list_clk:in std_logic;
list_wea:in std_logic_vector(0 downto 0);
list_addr:in std_logic_vector(7 downto 0);
list_din:in std_logic_vector(7 downto 0);
clk_voice:out std_logic;
n_wr,n_cs,n_rd,n_rst:out std_logic:='1';
n_int:in std_logic:='0';
add_en:out std_logic:='0';
data_voice:inout std_logic_vector(7 downto 0);
voice_result:out std_logic_vector(7 downto 0):=x"00";
reco_rqu:in std_logic:='0';
reco_fin:out std_logic:='0';
voice_state:out std_logic_vector(7 downto 0):=x"00";
voice_ram:out std_logic_vector(15 downto 0):=x"0000"
);
end component;
signal inclk_s,inclk_n_s:std_logic;
signal voice_start:std_logic:='0';
signal voice_result:std_logic_vector(7 downto 0);
signal voice_rqu:std_logic;
signal voice_fin:std_logic;
signal init_clk:std_logic;
signal init_wea:std_logic_vector(0 downto 0);
signal init_addr:std_logic_vector(5 downto 0);
signal init_din:std_logic_vector(15 downto 0);
signal list_clk:std_logic;
signal list_wea:std_logic_vector(0 downto 0);
signal list_addr:std_logic_vector(7 downto 0);
signal list_din:std_logic_vector(7 downto 0);
signal voice_state:std_logic_vector(7 downto 0):=x"00";
signal voice_ram:std_logic_vector(15 downto 0):=x"0000";
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
-- Example-specific design signals
-- local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
-- ADDR_LSB is used for addressing 32/64 bit registers/memories
-- ADDR_LSB = 2 for 32 bits (n downto 2)
-- ADDR_LSB = 3 for 64 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 1;
------------------------------------------------
---- Signals for user logic register space example
--------------------------------------------------
---- Number of Slave Registers 4
signal slv_reg0 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg0_last :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg1 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg2_last :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg3 :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal slv_reg_rden : std_logic;
signal slv_reg_wren : std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal byte_index : integer;
begin
-- I/O Connections assignments
inclk_s<=inclk;
inclk_n_s<=inclk_n;
list_clk<=inclk_n_s;
init_clk<=inclk_n_s;
VOICEX:VOICE
port map
(
start=>voice_start,
inclk=>inclk_s,
inclk_n=>inclk_n_s,
clk_voice=>clk_voice,
n_wr=>n_wr,
n_cs=>n_cs,
n_rd=>n_rd,
n_rst=>n_rst,
n_int=>n_int,
add_en=>add_en,
data_voice=>data_voice,
init_clk=>init_clk,
init_wea=>init_wea,
init_addr=>init_addr,
init_din=>init_din,
list_clk=>list_clk,
list_wea=>list_wea,
list_addr=>list_addr,
list_din=>list_din,
voice_result=>voice_result,
reco_rqu=>voice_rqu,
reco_fin=>voice_fin,
voice_state=>voice_state,
voice_ram=>voice_ram
);
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
slv_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVALID ;
process (S_AXI_ACLK)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
slv_reg0 <= (others => '0');
slv_reg2 <= (others => '0');
else
loc_addr := axi_awaddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
if (slv_reg_wren = '1') then
case loc_addr is
when b"00" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 0
slv_reg0(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when b"10" =>
for byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) loop
if ( S_AXI_WSTRB(byte_index) = '1' ) then
-- Respective byte enables are asserted as per write strobes
-- slave registor 2
slv_reg2(byte_index*8+7 downto byte_index*8) <= S_AXI_WDATA(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others =>
slv_reg0 <= slv_reg0;
slv_reg2 <= slv_reg2;
end case;
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
slv_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
process (slv_reg0, slv_reg1, slv_reg2, slv_reg3, axi_araddr, S_AXI_ARESETN, slv_reg_rden)
variable loc_addr :std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
begin
if S_AXI_ARESETN = '0' then
reg_data_out <= (others => '1');
else
-- Address decoding for reading registers
loc_addr := axi_araddr(ADDR_LSB + OPT_MEM_ADDR_BITS downto ADDR_LSB);
case loc_addr is
when b"00" =>
reg_data_out <= slv_reg0;
when b"01" =>
reg_data_out <= slv_reg1;
when b"10" =>
reg_data_out <= slv_reg2;
when b"11" =>
reg_data_out <= slv_reg3;
when others =>
reg_data_out <= (others => '0');
end case;
end if;
end process;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (slv_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
-- Add user logic here
ram_wr:process(inclk_s)
variable con_wr:integer range 0 to 3:=0;
begin
if rising_edge(inclk_s) then
slv_reg2_last<=slv_reg2;
if slv_reg2 /= slv_reg2_last then
case slv_reg2(31 downto 24) is
when Ram_Init=>
init_wea<="1";
init_addr<=slv_reg2(21 downto 16);
init_din<=slv_reg2(15 downto 0);
con_wr:=0;
when Ram_List=>
list_wea<="1";
list_addr<=slv_reg2(23 downto 16);
list_din<=slv_reg2(7 downto 0);
con_wr:=0;
when Ram_Stop=>
init_wea<="0";
list_wea<="0";
con_wr:=0;
when others=>
init_wea<=init_wea;
init_addr<=init_addr;
init_din<=init_din;
list_wea<=list_wea;
list_addr<=list_addr;
list_din<=list_din;
end case;
else
case slv_reg2(31 downto 24) is
when Ram_Init=>
if con_wr=3 then
init_wea<="0";
slv_reg3<=slv_reg2;
slv_reg3(31 downto 24)<=Ram_Re_Yes;
else
con_wr:=con_wr+1;
slv_reg3<=slv_reg2;
slv_reg3(31 downto 24)<=Ram_Re_No;
end if;
when Ram_List=>
if con_wr=3 then
list_wea<="0";
slv_reg3<=slv_reg2;
slv_reg3(31 downto 24)<=Ram_Re_Yes;
else
con_wr:=con_wr+1;
slv_reg3<=slv_reg2;
slv_reg3(31 downto 24)<=Ram_Re_No;
end if;
when others=>
init_wea<=init_wea;
init_addr<=init_addr;
init_din<=init_din;
list_wea<=list_wea;
list_addr<=list_addr;
list_din<=list_din;
slv_reg3<=slv_reg2;
slv_reg3(31 downto 24)<=x"ff";
end case;
end if;
end if;
end process;
Cmd:process(inclk_s)
begin
if rising_edge(inclk_s) then
slv_reg0_last<=slv_reg0;
if slv_reg0 /= slv_reg0_last then
slv_reg1(15 downto 8)<=Re_Wait;
case slv_reg0 is
when Cmd_Start=>
voice_start<='1';
when Cmd_Rqu=>
voice_Rqu<='1';
when others=>
voice_start<=voice_start;
voice_Rqu<=voice_Rqu;
end case;
else
slv_reg1(7 downto 0)<=voice_result;
slv_reg1(31 downto 24)<=voice_ram(15 downto 8);
slv_reg1(23 downto 16)<=voice_state;
case voice_fin is
when '1'=>
voice_Rqu<='0';
case voice_result is
when x"FD"=>
slv_reg1(15 downto 8)<=Re_Fail;
when others=>
slv_reg1(15 downto 8)<=Re_Success;
end case;
when others=>
voice_Rqu<=voice_Rqu;
end case;
end if;
end if;
end process;
-- User logic ends
end arch_imp;
|
mit
|
wltr/cern-fgclite
|
nanofip_fpga/src/rtl/nanofip/wf_rx_deglitcher.vhd
|
1
|
10214
|
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- wf_rx_deglitcher |
-- |
---------------------------------------------------------------------------------------------------
-- File wf_rx_deglitcher.vhd |
-- |
-- Description The unit applies a glitch filter to the nanoFIP FIELDRIVE input FD_RXD. |
-- It is capable of cleaning glitches up to c_DEGLITCH_THRESHOLD uclk ticks long. |
-- |
-- Authors Pablo Alvarez Sanchez ([email protected]) |
-- Evangelia Gousiou ([email protected]) |
-- Date 14/02/2011 |
-- Version v0.03 |
-- Depends on wf_reset_unit |
---------------- |
-- Last changes |
-- 07/08/2009 v0.01 PAS Entity Ports added, start of architecture content |
-- 23/08/2010 v0.02 EG code cleaned-up+commented |
-- 14/02/2011 v0.03 EG complete change, no dependency on osc; |
-- fd_rxd deglitched right at reception |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for wf_rx_deglitcher
--=================================================================================================
entity wf_rx_deglitcher is port(
-- INPUTS
-- nanoFIP User Interface general signal
uclk_i : in std_logic; -- 40 MHz clock
-- Signal from the wf_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
-- nanoFIP FIELDRIVE (synchronized with uclk)
fd_rxd_a_i : in std_logic; -- receiver data
-- OUTPUTS
-- Signals to the wf_rx_deserializer unit
fd_rxd_filt_o : out std_logic; -- filtered output signal
fd_rxd_filt_edge_p_o : out std_logic; -- indicates an edge on the filtered signal
fd_rxd_filt_f_edge_p_o : out std_logic);-- indicates a falling edge on the filtered signal
end wf_rx_deglitcher;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of wf_rx_deglitcher is
signal s_fd_rxd_synch : std_logic_vector (1 downto 0);
signal s_fd_rxd_filt, s_fd_rxd_filt_d1 : std_logic;
signal s_fd_rxd_filt_r_edge_p, s_fd_rxd_filt_f_edge_p : std_logic;
signal s_filt_c : unsigned (3 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- FD_RXD synchronization --
---------------------------------------------------------------------------------------------------
-- Synchronous process FD_RXD_synchronizer: Synchronization of the nanoFIP FIELDRIVE input
-- FD_RXD to the uclk, using a set of 2 registers.
FD_RXD_synchronizer: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_fd_rxd_synch <= (others => '0');
else
s_fd_rxd_synch <= s_fd_rxd_synch(0) & fd_rxd_a_i;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- Deglitching --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- Synchronous process FD_RXD_deglitcher: the output signal s_fd_rxd_filt is updated only
-- after the accumulation of a sufficient (c_DEGLITCH_THRESHOLD + 1) amount of identical bits.
-- The signal is therefore cleaned of any glitches up to c_DEGLITCH_THRESHOLD uclk ticks long.
FD_RXD_deglitcher: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_filt_c <= to_unsigned (c_DEGLITCH_THRESHOLD, s_filt_c'length) srl 1;-- middle value
s_fd_rxd_filt <= '0';
s_fd_rxd_filt_d1 <= '0';
else
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
if s_fd_rxd_synch(1) = '0' then -- arrival of a '0'
if s_filt_c /= 0 then -- counter updated
s_filt_c <= s_filt_c - 1;
else
s_fd_rxd_filt <= '0'; -- output updated
end if; -- if counter = 0
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
elsif s_fd_rxd_synch(1) = '1' then -- arrival of a '1'
if s_filt_c /= c_DEGLITCH_THRESHOLD then
s_filt_c <= s_filt_c + 1; -- counter updated
else
s_fd_rxd_filt <= '1'; -- output updated
end if; -- if counter = c_DEGLITCH_THRESHOLD
end if;
s_fd_rxd_filt_d1 <= s_fd_rxd_filt; -- used for the edges detection
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -
-- Concurrent signal assignments
s_fd_rxd_filt_r_edge_p <= (not s_fd_rxd_filt_d1) and s_fd_rxd_filt; -- pulse upon detection
-- of a falling edge
s_fd_rxd_filt_f_edge_p <= s_fd_rxd_filt_d1 and (not s_fd_rxd_filt); -- pulse upon detection
-- of a rising edge
fd_rxd_filt_edge_p_o <= s_fd_rxd_filt_f_edge_p or s_fd_rxd_filt_r_edge_p;
fd_rxd_filt_f_edge_p_o <= s_fd_rxd_filt_f_edge_p;
fd_rxd_filt_o <= s_fd_rxd_filt;
end rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
|
mit
|
dtysky/LD3320_AXI
|
hdl/VOICE.vhd
|
1
|
16919
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity VOICE is
port
(
start:in std_logic;
inclk,inclk_n:in std_logic;
init_clk:in std_logic;
init_wea:in std_logic_vector(0 downto 0);
init_addr:in std_logic_vector(5 downto 0);
init_din:in std_logic_vector(15 downto 0);
list_clk:in std_logic;
list_wea:in std_logic_vector(0 downto 0);
list_addr:in std_logic_vector(7 downto 0);
list_din:in std_logic_vector(7 downto 0);
clk_voice:out std_logic;
n_wr,n_cs,n_rd,n_rst:out std_logic:='1';
n_int:in std_logic:='0';
add_en:out std_logic:='0';
data_voice:inout std_logic_vector(7 downto 0);
voice_result:out std_logic_vector(7 downto 0):=x"00";
reco_rqu:in std_logic:='0';
reco_fin:out std_logic:='0';
voice_state:out std_logic_vector(7 downto 0):=x"00";
voice_ram:out std_logic_vector(15 downto 0):=x"0000"
);
end entity;
architecture voicex of VOICE is
component VOICE_ROM_INIT is
PORT
(
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
end component;
component LIST is
PORT
(
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN std_logic_vector(7 downto 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN std_logic_vector(7 downto 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
end component;
component VOICE_DELAY is
port
(
clk:in std_logic;
start:in std_logic:='0';
total:in std_logic_vector(7 downto 0);
finish:out std_logic:='1'
);
end component;
-------------------æ¶éã?0MHz---------------------
signal clk_self,clk_out:std_logic;
-----------------------å¤ä½------------------------
signal reset:std_logic:='0';
--------------------åå§åROM----------------------
signal rom_init_addr:std_logic_vector(5 downto 0):="000000";
signal rom_init_data:std_logic_vector(15 downto 0);
signal rom_en:std_logic:='1';
---------------------å表ROM-----------------------
signal rom_list_addr:std_logic_vector(7 downto 0):=x"00";
signal rom_list_data:std_logic_vector(7 downto 0);
-----------------------延æ¶------------------------
signal delay_start,delay_finish:std_logic:='0';
signal delay_total:std_logic_vector(7 downto 0);
----------------------é
ç½®ç¶æ?----------------------
signal init_done,list_done,all_wait,all_done,all_done_last:std_logic:='0';
----------------------è¯å«ç¶æ?----------------------
signal reco_allow,reco_allow_last,reco_start:std_logic:='0';
signal reco_rqu_last:std_logic:='0';
signal n_int_last:std_logic:='1';
signal add_en_s:std_logic:='1';
begin
voice_state(1)<=start;
voice_state(0)<=reco_rqu;
clk_voice<=inclk_n;
VOICE_ROM_INITX:voice_rom_init
port map
(
clka=>init_clk,
wea=>init_wea,
addra=>init_addr,
dina=>init_din,
clkb=>clk_out,
addrb=>rom_init_addr,
doutb=>rom_init_data
);
VOICE_ROM_LIST:list
port map
(
clka=>list_clk,
wea=>list_wea,
addra=>list_addr,
dina=>list_din,
clkb=>clk_out,
addrb=>rom_list_addr,
doutb=>rom_list_data
);
VOICE_DLLAYX:voice_delay port map(clk=>clk_self,start=>delay_start,finish=>delay_finish,total=>delay_total);
clk_self<=inclk;
clk_out<=inclk_n;
add_en<=add_en_s;
rom_en<='1';
process(clk_self,reset)
variable con_reset:integer range 0 to 127:=0;
variable con_init_start:integer range 0 to 2047:=0;
variable con:integer range 0 to 5:=0;
variable con_total:integer range 0 to 26:=0;
variable con_type:integer range 0 to 31:=0;
variable con_init_fin_start:integer range 0 to 3:=0;
begin
if clk_self'event and clk_self='1' then
voice_state(7)<='1';
--------------------å¤ä½-----------------------
if con_reset=127 then
reset<='1';
end if;
if reset='1' then
con_reset:=0;
reset<='0';
reco_fin<='0';
init_done<='0';
list_done<='0';
all_wait<='0';
all_done<='0';
reco_allow<='0';
rom_init_addr<="000000";
rom_list_addr<="00000000";
con_init_start:=0;
end if;
---------------------åå§å?---------------------
if start='1' then
if con_init_start=2047 then
con_init_start:=2047;
else
con_init_start:=con_init_start+1;
con:=0;
con_type:=0;
con_total:=0;
con_init_fin_start:=0;
end if;
end if;
if con_init_start=500 then
n_rst<='0';
elsif con_init_start=1000 then
n_rst<='1';
elsif con_init_start=1500 then
n_cs<='0';
elsif con_init_start=2000 then
n_cs<='1';
delay_start<='1';
delay_total<=x"5F";
end if;
--------------------åå§å?--------------------
if con_init_start=2047 and init_done='0' and delay_finish='1' then
voice_state(6)<='1';
if con=5 then
con:=0;
elsif con=0 then
if con_total=26 then
init_done<='1';
con:=0;
con_type:=0;
con_total:=0;
else
con:=con+1;
end if;
else
con:=con+1;
end if;
-------------------------------------------------------
if con_total=0 or con_total=2 then
if con=1 then
delay_start<='0';
if con_type=0 then
add_en_s<='1';
data_voice<=x"06";
else
add_en_s<='0';
data_voice<="ZZZZZZZZ";
end if;
elsif con=2 then
n_cs<='0';
elsif con=3 then
if con_type=0 then
n_wr<='0';
else
n_rd<='0';
end if;
elsif con=4 then
if add_en_s='0' then
delay_total<=x"0A";
delay_start<='1';
end if;
if con_type=0 then
n_wr<='1';
else
n_rd<='1';
end if;
elsif con=5 then
n_cs<='1';
if con_type=1 then
con_type:=0;
con_total:=con_total+1;
else
con_type:=con_type+1;
end if;
end if;
-------------------------------------------------------
else
if con=1 then
delay_start<='0';
if con_type=0 then
add_en_s<='1';
data_voice<=rom_init_data(15 downto 8);
else
add_en_s<='0';
data_voice<=rom_init_data(7 downto 0);
rom_init_addr<=rom_init_addr+1;
end if;
elsif con=2 then
n_cs<='0';
elsif con=3 then
n_wr<='0';
elsif con=4 then
n_wr<='1';
delay_total<=x"0A";
delay_start<='1';
elsif con=5 then
n_cs<='1';
if con_type=1 then
con_type:=0;
con_total:=con_total+1;
else
con_type:=con_type+1;
end if;
end if;
end if;
end if;
-------------------å¾
è¯å«å表åå
?---------------
if init_done='1' and list_done='0' and delay_finish='1' then
voice_state(5)<='1';
if con=0 then
delay_start<='0';
con:=con+1;
elsif con=1 then
if con_type=0 then
add_en_s<='1';
data_voice<=x"B2";
con:=con+1;
elsif con_type=10 then
add_en_s<='0';
data_voice<="ZZZZZZZZ";
con:=con+1;
elsif con_type=1 then
if rom_list_data=x"FF" then
con_type:=20;
--list_done<='1';
delay_total<=x"5F";
delay_start<='1';
con:=0;
--con_type:=0;
else
add_en_s<='1';
data_voice<=x"C1";
con:=con+1;
con_type:=2;
end if;
elsif con_type=20 then
add_en_s<='1';
data_voice<=x"BF";
con:=con+1;
elsif con_type=21 then
add_en_s<='0';
data_voice<="ZZZZZZZZ";
con:=con+1;
elsif con_type=2 then
add_en_s<='0';
data_voice<=rom_list_data;
con:=con+1;
con_type:=12;
elsif con_type=12 then
add_en_s<='1';
data_voice<=x"C3";
con:=con+1;
con_type:=13;
elsif con_type=13 then
add_en_s<='0';
data_voice<=x"00";
con:=con+1;
con_type:=14;
elsif con_type=14 then
add_en_s<='1';
data_voice<=x"08";
con:=con+1;
con_type:=15;
elsif con_type=15 then
add_en_s<='0';
data_voice<=x"04";
con:=con+1;
con_type:=16;
elsif con_type=16 then
add_en_s<='1';
data_voice<=x"08";
con:=con+1;
con_type:=17;
elsif con_type=17 then
add_en_s<='0';
data_voice<=x"00";
con:=con+1;
con_type:=3;
elsif con_type=3 then
add_en_s<='1';
data_voice<=x"05";
con:=con+1;
con_type:=11;
rom_list_addr<=rom_list_addr+1;
elsif con_type=4 then
add_en_s<='1';
data_voice<=x"B9";
con:=con+1;
con_type:=5;
rom_list_addr<=rom_list_addr+1;
elsif con_type=5 then
add_en_s<='0';
data_voice<=rom_list_data;
con:=con+1;
con_type:=6;
elsif con_type=6 then
add_en_s<='1';
data_voice<=x"B2";
con:=con+1;
con_type:=7;
elsif con_type=7 then
add_en_s<='0';
data_voice<=x"FF";
con:=con+1;
con_type:=8;
elsif con_type=8 then
add_en_s<='1';
data_voice<=x"37";
con:=con+1;
con_type:=9;
elsif con_type=9 then
add_en_s<='0';
data_voice<=x"04";
con:=con+1;
con_type:=0;
rom_list_addr<=rom_list_addr+1;
elsif con_type=11 then
if rom_list_data=x"FF" then
con_type:=4;
con:=0;
else
add_en_s<='0';
data_voice<=rom_list_data;
rom_list_addr<=rom_list_addr+1;
con:=con+1;
end if;
end if;
elsif con=2 then
n_cs<='0';
con:=con+1;
elsif con=3 then
con:=con+1;
if con_type=10 or con_type=21 then
n_rd<='0';
else
n_wr<='0';
end if;
elsif con=4 then
con:=con+1;
if add_en_s='0' and con_type/=11 then
delay_total<=x"01";
delay_start<='1';
end if;
if con_type=21 or con_type=10 then
n_rd<='1';
else
n_wr<='1';
end if;
elsif con=5 then
n_cs<='1';
con:=0;
if con_type=10 then
voice_ram(15 downto 8)<=data_voice;
voice_ram(5 downto 0)<=rom_init_addr;
if data_voice=x"21" then
con_type:=1;
else
delay_total<=x"0A";
delay_start<='1';
con_type:=0;
con_reset:=con_reset+1;
end if;
elsif con_type=0 then
con_type:=10;
elsif con_type=20 then
con_type:=21;
elsif con_type=21 then
if data_voice=x"31" then
con_type:=0;
list_done<='1';
con:=0;
con_type:=0;
else
reset<='1';
end if;
end if;
end if;
end if;
-------------------------è¯å«åå¤------------------------
reco_rqu_last<=reco_rqu;
if reco_rqu_last='0' and reco_rqu='1' then
reco_start<='1';
end if;
if list_done='1' and all_wait='0' and reco_start='1' and delay_finish='1' then
voice_state(4)<='1';
if con_init_fin_start=3 then
con_init_fin_start:=3;
else
rom_init_addr<="100000";
con_init_fin_start:=con_init_fin_start+1;
end if;
if con_init_fin_start=3 then
if con=5 then
con:=0;
elsif con=0 then
if con_total=5 then
all_wait<='1';
reco_start<='0';
con:=0;
con_type:=0;
con_total:=0;
con_reset:=0;
elsif con_total=0 then
con:=con+1;
else
con:=con+1;
end if;
else
con:=con+1;
end if;
if con=0 then
delay_start<='0';
elsif con=1 then
if con_type=0 then
add_en_s<='1';
data_voice<=rom_init_data(15 downto 8);
else
add_en_s<='0';
data_voice<=rom_init_data(7 downto 0);
rom_init_addr<=rom_init_addr+1;
end if;
elsif con=2 then
n_cs<='0';
elsif con=3 then
n_wr<='0';
elsif con=4 then
n_wr<='1';
if add_en_s='0' then
delay_total<=x"01";
delay_start<='1';
end if;
elsif con=5 then
n_cs<='1';
if con_type=1 then
con_type:=0;
con_total:=con_total+1;
else
con_type:=con_type+1;
end if;
end if;
end if;
end if;
---------------------------è¯å«--------------------------
if all_wait='1' and delay_finish='1' then
voice_state(3)<='1';
if con=5 then
con:=0;
elsif con=0 then
if con_total=7 then
con_total:=0;
con_type:=0;
con:=0;
all_wait<='0';
all_done<='1';
else
con:=con+1;
end if;
else
con:=con+1;
end if;
if con=0 then
delay_start<='0';
elsif con=1 then
if con_type=0 then
add_en_s<='1';
if con_total=0 then
data_voice<=x"B2";
elsif con_total=3 then
data_voice<=x"BF";
else
data_voice<=rom_init_data(15 downto 8);
end if;
else
add_en_s<='0';
if con_total=0 or con_total=3 then
data_voice<="ZZZZZZZZ";
else
data_voice<=rom_init_data(7 downto 0);
rom_init_addr<=rom_init_addr+1;
end if;
end if;
elsif con=2 then
n_cs<='0';
elsif con=3 then
if (con_total=0 or con_total=3) and con_type=1 then
n_rd<='0';
else
n_wr<='0';
end if;
elsif con=4 then
if (con_total=0 or con_total=3) and con_type=1 then
n_rd<='1';
else
n_wr<='1';
end if;
if add_en_s='0' then
if con_total=2 then
delay_total<=x"05";
else
delay_total<=x"01";
end if;
delay_start<='1';
end if;
elsif con=5 then
n_cs<='1';
if con_total=0 and con_type=1 then
if data_voice=x"21" then
con_total:=con_total+1;
else
con_reset:=con_reset+1;
con_total:=0;
end if;
elsif con_total=3 and con_type=1 then
if data_voice=x"31" then
con_total:=con_total+1;
else
reco_fin<='1';
data_voice<=x"FF";
reset<='1';
end if;
elsif con_type=1 then
con_total:=con_total+1;
end if;
if con_type=1 then
con_type:=0;
else
con_type:=con_type+1;
end if;
end if;
end if;
-----------------------è¯å«ç»æ---------------------
if all_done='1' and delay_finish='1' then
n_int_last<=n_int;
if n_int_last='1' and n_int='0' then
reco_allow<='1';
end if;
end if;
reco_allow_last<=reco_allow;
if reco_allow_last='1' and reco_allow='0' then
reco_fin<='0';
end if;
if reco_allow='1' then
voice_state(2)<='1';
if con=5 then
con:=0;
else
con:=con+1;
end if;
if con=0 then
if con_total=6 then
reco_allow<='0';
all_done<='0';
con:=0;
con_type:=0;
con_total:=0;
end if;
elsif con=1 then
if con_type=0 then
add_en_s<='1';
if con_total=0 then
data_voice<=x"29";
elsif con_total=1 then
data_voice<=x"02";
elsif con_total=2 then
data_voice<=x"BF";
elsif con_total=3 then
data_voice<=x"2B";
elsif con_total=4 then
data_voice<=x"BA";
elsif con_total=5 then
data_voice<=x"C5";
end if;
else
add_en_s<='0';
if con_total<2 then
data_voice<=x"00";
else
data_voice<="ZZZZZZZZ";
end if;
end if;
elsif con=2 then
n_cs<='0';
elsif con=3 then
if con_total>1 and con_type=1 then
n_rd<='0';
else
n_wr<='0';
end if;
elsif con=4 then
if con_total>1 and con_type=1 then
n_rd<='1';
else
n_wr<='1';
end if;
elsif con=5 then
n_cs<='1';
if con_type=1 then
con_type:=0;
if con_total<2 then
con_total:=con_total+1;
elsif con_total=2 and data_voice=x"35" then
con_total:=con_total+1;
elsif con_total=3 and data_voice(3)='0' then
con_total:=con_total+1;
elsif con_total=4 then
if data_voice>x"00" and data_voice<x"05" then
con_total:=con_total+1;
else
voice_result<=x"FD";
reco_allow<='0';
reco_fin<='1';
all_done<='0';
con:=0;
con_type:=0;
con_total:=0;
end if;
elsif con_total=5 then
reco_fin<='1';
voice_result<=data_voice;
con_total:=con_total+1;
else
reset<='1';
end if;
else
con_type:=con_type+1;
end if;
end if;
end if;
end if;
end process;
end voicex;
|
mit
|
wltr/cern-fgclite
|
nanofip_fpga/src/rtl/nanofip/wf_engine_control.vhd
|
1
|
51040
|
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- wf_engine_control |
-- |
---------------------------------------------------------------------------------------------------
-- File wf_engine_control.vhd |
-- |
-- Description The wf_engine_control is following the reception of an incoming ID_DAT frame and |
-- o identifies the variable to be treated |
-- o signals accordingly the wf_production or wf_consumption units. |
-- |
-- Reminder: |
-- |
-- ID_DAT frame structure: |
-- ___________ ______ _______ ______ ___________ _______ |
-- |____FSS____|_CTRL_||__Var__|_SUBS_||____FCS____|__FES__| |
-- |
-- |
-- Produced RP_DAT frame structure: |
-- ___________ ______ _______ ______ _________________ _______ _______ ___________ _______ |
-- |____FSS____|_CTRL_||__PDU__|_LGTH_|__..User-Data..__|_nstat_|__MPS__||____FCS____|__FES__| |
-- |
-- |
-- Consumed RP_DAT frame structure: |
-- ___________ ______ _______ ______ _________________________ _______ ___________ _______ |
-- |____FSS____|_CTRL_||__PDU__|_LGTH_|_____..Applic-Data.._____|__MPS__||____FCS____|__FES__| |
-- |
-- |
-- Turnaround time: Time between the end of the reception of an ID_DAT frame |
-- requesting for a variable to be produced and the starting of the delivery of a |
-- produced RP_DAT frame. |
-- |
-- Silence time : Maximum time that nanoFIP waits for a consumed RP_DAT frame |
-- after the reception of an ID_DAT frame that indicates a variable to be consumed. |
-- |
-- Authors Pablo Alvarez Sanchez ([email protected]) |
-- Evangelia Gousiou ([email protected]) |
-- Date 15/01/2011 |
-- Version v0.06 |
-- Depends on wf_reset_unit |
-- wf_fd_transmitter |
-- wf_fd_receiver |
---------------- |
-- Last changes |
-- 07/2009 v0.01 EB First version |
-- 08/2010 v0.02 EG E0 added as broadcast |
-- PDU,LGTH,CTRL bytes of RP_DAT checked bf VAR1_RDY/var_2_rdy assertion; |
-- if ID_DAT>8 bytes or RP_DAT>133 (bf reception of a FES) go to IDLE; |
-- state CONSUME_WAIT_FSS, for the correct use of the silence time(time |
-- stops counting when an RP_DAT frame has started) |
-- 12/2010 v0.03 EG state machine rewritten moore style; removed check on slone mode |
-- for #bytes>4; in slone no broadcast |
-- 01/2011 v0.04 EG signals named according to their origin; signals var_rdy (1,2,3), |
-- assert_rston_p_o,rst_nfip_and_fd_p_o, nFIP status bits and |
-- rx_byte_ready_p_o removed cleaning-up+commenting |
-- 02/2011 v0.05 EG Independent timeout counter added; time counter 18 digits instead of 15|
-- ID_DAT_FRAME_OK: corrected mistake if rx_fss_crc_fes_ok_p not |
-- activated; rx reset during production (rx_rst_o); |
-- cons_bytes_excess_o added |
-- tx_completed_p_i added (bf for the engine ctrl production was finished |
-- after the delivery of the last data byte (MPS)) |
-- 07/2011 v0.06 EG RST_RX state added |
-- 10/2011 v0.06b EG moved session_timedout in the synchronous FSM process |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for wf_engine_control
--=================================================================================================
entity wf_engine_control is port(
-- INPUTS
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; -- 40 MHz clock
nostat_i : in std_logic; -- if negated, nFIP status is sent
slone_i : in std_logic; -- stand-alone mode
-- nanoFIP WorldFIP Settings
p3_lgth_i : in std_logic_vector (2 downto 0); -- produced var user-data length
rate_i : in std_logic_vector (1 downto 0); -- WorldFIP bit rate
subs_i : in std_logic_vector (7 downto 0); -- subscriber number coding
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signal from the wf_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signal from the wf_fd_transmitter unit
tx_completed_p_i : in std_logic; -- pulse upon termination of a
-- produced RP_DAT transmission
tx_byte_request_p_i : in std_logic; -- used for the counting of the
-- # produced bytes
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signals from the wf_fd_receiver unit
rx_byte_i : in std_logic_vector (7 downto 0); -- deserialized ID_DAT/ RP_DAT byte
rx_byte_ready_p_i : in std_logic; -- indication of a new byte on rx_byte_i
rx_fss_crc_fes_ok_p_i : in std_logic; -- indication of a frame (ID_DAT or RP_DAT) with
-- correct FSS, FES and CRC
rx_crc_wrong_p_i : in std_logic; -- indication of a frame with a wrong CRC
-- pulse upon FES detection
rx_fss_received_p_i : in std_logic; -- pulse upon FSS detection (ID/ RP_DAT)
-------------------------------------------------------------------------------------------------
-- OUTPUTS
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signal to the wf_fd_transmitter unit
tx_start_p_o : out std_logic; -- launches the transmitter
tx_byte_request_accept_p_o : out std_logic; -- answer to tx_byte_request_p_i
tx_last_data_byte_p_o : out std_logic; -- indication of the last data-byte
-- (CRC & FES not included)
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signal to the wf_production unit
prod_data_lgth_o : out std_logic_vector (7 downto 0); -- # bytes of the Conrol & Data
-- fields of a prod RP_DAT frame
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signal to the wf_fd_receiver
rx_rst_o : out std_logic; -- reset during production or
-- reset pulse when during reception a frame is rejected
-- (example: ID_DAT > 8 bytes, RP_DAT > 133 bytes,
-- wrong ID_DAT CTRL, variable, subs bytes)
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signal to the wf_consumption unit
cons_bytes_excess_o : out std_logic; -- indication of a consumed RP_DAT frame with more
-- than 133 bytes
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signals to the wf_production & wf_consumption
prod_byte_index_o : out std_logic_vector (7 downto 0); -- index of the byte being
-- produced
cons_byte_index_o : out std_logic_vector (7 downto 0); -- index of the byte being
-- consumed
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Signals to the wf_production, wf_consumption, wf_reset_unit
var_o : out t_var); -- received variable; takes a value only after a
-- valid ID_DAT frame with SUBS the station's address
end entity wf_engine_control;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of wf_engine_control is
-- FSM
type control_st_t is (IDLE,
ID_DAT_CTRL_BYTE, ID_DAT_VAR_BYTE, ID_DAT_SUBS_BYTE, ID_DAT_FRAME_OK,
CONSUME_WAIT_FSS, CONSUME, RST_RX,
PRODUCE_WAIT_TURNAR_TIME, PRODUCE);
signal control_st, nx_control_st : control_st_t;
signal s_idle_state, s_id_dat_ctrl_byte, s_id_dat_var_byte, s_id_dat_frame_ok : std_logic;
signal s_cons_wait_FSS, s_consuming, s_rst_rx_p : std_logic;
signal s_prod_wait_turnar_time, s_producing : std_logic;
-- variable identification
signal s_var_aux, s_var : t_var;
signal s_var_identified, s_broadcast_var : std_logic;
signal s_prod_or_cons : std_logic_vector (1 downto 0);
-- time counters (turnaround, silence, timeout)
signal s_time_c_top, s_turnaround_time, s_silence_time : unsigned (17 downto 0);
signal s_time_c_load, s_time_c_is_zero : std_logic;
signal s_session_timedout : std_logic;
-- received & produced byte counters
signal s_rx_bytes_c, s_prod_bytes_c : unsigned (7 downto 0);
signal s_prod_bytes_c_rst, s_prod_bytes_c_inc : std_logic;
signal s_rx_bytes_c_rst, s_rx_bytes_c_inc : std_logic;
-- transmitter controls
signal s_tx_start_prod_p, s_tx_byte_request_accept_p, s_tx_byte_request_accept_p_d1 : std_logic;
signal s_tx_byte_request_accept_p_d2, s_tx_last_data_byte_p, s_tx_last_data_byte_p_d : std_logic;
-- length of produced data
signal s_prod_data_lgth : std_logic_vector (7 downto 0);
signal s_prod_data_lgth_match : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- engine_control FSM --
---------------------------------------------------------------------------------------------------
-- Central control FSM: the state machine is divided in three parts (a clocked process
-- to store the current state, a combinatorial process to manage state transitions and finally a
-- combinatorial process to manage the output signals), which are the three processes that follow.
-- The FSM stays in IDLE until the reception of a FSS from the wf_fd_receiver.
-- It continues by checking one by one the bytes of the frame as they arrive:
-- o if the CTRL byte corresponds to an ID_DAT,
-- o if the variable byte corresponds to a defined variable,
-- o if the subscriber byte matches the station's address, or if the variable is a broadcast
-- o and if the frame finishes with a correct CRC and FES.
-- If any of the bytes above has been different than the expected, the FSM resets the wf_fd_receiver
-- and goes back to IDLE.
-- o if the ID_DAT frame has been correct and the received variable is a produced (var_presence,
-- var_identif, var_3, var_5) the FSM stays in the "PRODUCE_WAIT_TURNAR_TIME" state until the
-- expiration of the turnaround time and then jumps to the "PRODUCE" state, waiting for the
-- wf_fd_serializer to finish the transmission; then it goes back to IDLE.
-- o if the received variable is a consumed (var_1, var_2, var_rst, var_4) the FSM stays in the
-- "CONSUME_WAIT_FSS" state until the arrival of a FSS or the expiration of the silence time.
-- After the arrival of the FSS the FSM jumps to the "CONSUME" state, where it stays until the
-- end of the reception of the consumed frame (marked by a FES).
-- Note: In the case of a var_5, it is the wf_consumption unit that signals the start-up of
-- the wf_jtag_controller which will work in parallel and independently from the
-- wf_engine_control; i.e. new frames reception can take place while the
-- wf_jtag_controller is working.
-- To add a robust layer of protection to the FSM, a counter dependent only on the system clock
-- has been implemented, that from any state can bring the FSM back to IDLE. At any bit rate the
-- reception of an ID_DAT frame followed by the reception/ transmission of an RP_DAT should not
-- last more than 41ms. Hence, we have generated a 21 bits (c_SESSION_TIMEOUT_C_LGTH)counter that
-- will reset the machine if more than 52ms (complete 21 bit counter) have passed since it has
-- left this IDLE state.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Synchronous process Engine_Control_FSM_Sync: storage of the current state of the FSM
Engine_Control_FSM_Sync: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' or s_session_timedout = '1' then
control_st <= IDLE;
else
control_st <= nx_control_st;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process Engine_Control_FSM_Comb_State_Transitions: definition of the state
-- transitions of the FSM.
Engine_Control_FSM_Comb_State_Transitions: process (s_time_c_is_zero, s_prod_or_cons,subs_i,
rx_crc_wrong_p_i, rx_fss_crc_fes_ok_p_i,
s_broadcast_var, s_var_identified, rx_byte_i,
rx_byte_ready_p_i, control_st, s_rx_bytes_c,
rx_fss_received_p_i,tx_completed_p_i)
begin
case control_st is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when IDLE =>
if rx_fss_received_p_i = '1' then -- new frame FSS detected
nx_control_st <= ID_DAT_CTRL_BYTE;
else
nx_control_st <= IDLE;
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when ID_DAT_CTRL_BYTE =>
if (rx_byte_ready_p_i = '1') and (rx_byte_i(5 downto 0) = c_ID_DAT_CTRL_BYTE) then
nx_control_st <= ID_DAT_VAR_BYTE; -- check of ID_DAT CTRL byte
elsif rx_byte_ready_p_i = '1' then
nx_control_st <= RST_RX; -- byte different than the expected ID_DAT CTRL
else
nx_control_st <= ID_DAT_CTRL_BYTE; -- ID_DAT CTRL byte being arriving
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when ID_DAT_VAR_BYTE =>
if (rx_byte_ready_p_i = '1') and (s_var_identified = '1') then
nx_control_st <= ID_DAT_SUBS_BYTE; -- check of the ID_DAT variable
elsif rx_byte_ready_p_i = '1' then
nx_control_st <= RST_RX; -- byte not corresponding to an expected variable
else
nx_control_st <= ID_DAT_VAR_BYTE; -- ID_DAT variable byte being arriving
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when ID_DAT_SUBS_BYTE =>
if (rx_byte_ready_p_i = '1') and ((rx_byte_i = subs_i) or (s_broadcast_var = '1')) then
nx_control_st <= ID_DAT_FRAME_OK; -- checking of the ID_DAT subscriber
-- or if it is a broadcast variable
-- note: broadcast consumed vars are only treated in
-- memory mode, but at this moment we do not do this
-- check as the var_rst which is broadcast is treated
-- also in stand-alone mode.
elsif rx_byte_ready_p_i = '1' then -- not the station's address, neither a broadcast var
nx_control_st <= RST_RX;
else
nx_control_st <= ID_DAT_SUBS_BYTE; -- ID_DAT subscriber byte being arriving
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when ID_DAT_FRAME_OK =>
if (rx_fss_crc_fes_ok_p_i = '1') and (s_prod_or_cons = "10") then
nx_control_st <= PRODUCE_WAIT_TURNAR_TIME; -- ID_DAT frame ok! station has to PRODUCE
elsif (rx_fss_crc_fes_ok_p_i = '1') and (s_prod_or_cons = "01") then
nx_control_st <= CONSUME_WAIT_FSS; -- ID_DAT frame ok! station has to CONSUME
elsif (s_rx_bytes_c > 2) then -- 3 bytes after the arrival of the subscriber
nx_control_st <= RST_RX; -- byte, a FES has not been detected
else
nx_control_st <= ID_DAT_FRAME_OK; -- CRC & FES bytes being arriving
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when PRODUCE_WAIT_TURNAR_TIME =>
if s_time_c_is_zero = '1' then -- turnaround time passed
nx_control_st <= PRODUCE;
else
nx_control_st <= PRODUCE_WAIT_TURNAR_TIME; -- waiting for turnaround time to pass
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when CONSUME_WAIT_FSS =>
if rx_fss_received_p_i = '1' then -- FSS of the consumed RP_DAT arrived
nx_control_st <= CONSUME;
elsif s_time_c_is_zero = '1' then -- if the FSS of the consumed RP_DAT frame doesn't
nx_control_st <= RST_RX; -- arrive before the expiration of the silence time,
-- the engine goes back to IDLE
else
nx_control_st <= CONSUME_WAIT_FSS; -- counting silence time
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when CONSUME =>
if (rx_fss_crc_fes_ok_p_i = '1') or -- the cons frame arrived to the end, as expected
(rx_crc_wrong_p_i = '1') then -- FES detected but wrong CRC or wrong # bits
nx_control_st <= IDLE;
elsif (s_rx_bytes_c > c_MAX_FRAME_BYTES) then -- no FES detected after the max number of bytes
nx_control_st <= RST_RX;
else
nx_control_st <= CONSUME; -- consuming bytes
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when PRODUCE =>
if tx_completed_p_i = '1' then -- end of production (including CRC and FES)
nx_control_st <= IDLE;
else
nx_control_st <= PRODUCE; -- producing bytes
end if;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when RST_RX => -- the current reception has finished
-- a reset pulse is sent to the wf_receiver
nx_control_st <= IDLE; -- which will start looking for a new FSS
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when others =>
nx_control_st <= IDLE;
end case;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Combinatorial process Engine_Control_FSM_Comb_Output_Signals : definition of the output
-- signals of the FSM
Engine_Control_FSM_Comb_Output_Signals: process (control_st)
begin
case control_st is
when IDLE =>
---------------------------------
s_idle_state <= '1';
---------------------------------
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0';
s_consuming <= '0';
s_rst_rx_p <= '0';
s_producing <= '0';
when ID_DAT_CTRL_BYTE =>
s_idle_state <= '0';
---------------------------------
s_id_dat_ctrl_byte <= '1';
---------------------------------
s_id_dat_var_byte <= '0';
s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0';
s_consuming <= '0';
s_rst_rx_p <= '0';
s_producing <= '0';
when ID_DAT_VAR_BYTE =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
---------------------------------
s_id_dat_var_byte <= '1';
---------------------------------
s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0';
s_consuming <= '0';
s_rst_rx_p <= '0';
s_producing <= '0';
when ID_DAT_SUBS_BYTE =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0';
s_consuming <= '0';
s_rst_rx_p <= '0';
s_producing <= '0';
when ID_DAT_FRAME_OK =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
---------------------------------
s_id_dat_frame_ok <= '1';
---------------------------------
s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0';
s_consuming <= '0';
s_rst_rx_p <= '0';
s_producing <= '0';
when PRODUCE_WAIT_TURNAR_TIME =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_frame_ok <= '0';
---------------------------------
s_prod_wait_turnar_time <= '1';
---------------------------------
s_cons_wait_FSS <= '0';
s_consuming <= '0';
s_rst_rx_p <= '0';
s_producing <= '0';
when CONSUME_WAIT_FSS =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0';
---------------------------------
s_cons_wait_FSS <= '1';
---------------------------------
s_consuming <= '0';
s_rst_rx_p <= '0';
s_producing <= '0';
when CONSUME =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0';
---------------------------------
s_consuming <= '1';
---------------------------------
s_rst_rx_p <= '0';
s_producing <= '0';
when RST_RX =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0';
s_consuming <= '0';
---------------------------------
s_rst_rx_p <= '1';
---------------------------------
s_producing <= '0';
when PRODUCE =>
s_idle_state <= '0';
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0';
s_consuming <= '0';
s_rst_rx_p <= '0';
---------------------------------
s_producing <= '1';
---------------------------------
when others =>
---------------------------------
s_idle_state <= '1';
---------------------------------
s_id_dat_ctrl_byte <= '0';
s_id_dat_var_byte <= '0';
s_id_dat_frame_ok <= '0';
s_prod_wait_turnar_time <= '0';
s_cons_wait_FSS <= '0';
s_consuming <= '0';
s_rst_rx_p <= '0';
s_producing <= '0';
end case;
end process;
---------------------------------------------------------------------------------------------------
-- Counters for the number of bytes being received or produced --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of the wf_prod_data_lgth_calc unit that calculates the amount of bytes that have
-- to be transmitted when a variable is produced; the CTRL, MPS and nanoFIP_status bytes are
-- included; The FSS, CRC and FES bytes are not included!
Produced_Data_Length_Calculator: wf_prod_data_lgth_calc
port map(
uclk_i => uclk_i,
nfip_rst_i => nfip_rst_i,
slone_i => slone_i,
nostat_i => nostat_i,
p3_lgth_i => p3_lgth_i,
var_i => s_var,
-------------------------------------------------------
prod_data_lgth_o => s_prod_data_lgth);
-------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of a wf_incr_counter for the counting of the number of the bytes that are
-- being produced. The counter is reset at the "PRODUCE_WAIT_TURNAR_TIME" state of the FSM and
-- counts bytes following the "tx_byte_request_p_i" pulse in the "PRODUCE" state.
Prod_Bytes_Counter: wf_incr_counter
generic map(g_counter_lgth => 8)
port map(
uclk_i => uclk_i,
counter_reinit_i => s_prod_bytes_c_rst,
counter_incr_i => s_prod_bytes_c_inc,
counter_is_full_o => open,
-------------------------------------------------------
counter_o => s_prod_bytes_c);
-------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- --
s_prod_bytes_c_rst <= '0' when s_producing = '1' else '1';
s_prod_bytes_c_inc <= tx_byte_request_p_i when s_producing = '1' else '0';
-- when s_prod_data_lgth bytes have been counted,the signal s_prod_data_lgth_match is activated
s_prod_data_lgth_match <= '1' when s_prod_bytes_c = unsigned (s_prod_data_lgth) else '0';
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of a wf_incr_counter for the counting of the number of bytes that are being
-- received. The same counter is used for the bytes of an ID_DAT frame or a consumed RP_DAT
-- frame (hence the name of the counter is s_rx_bytes_c and not s_cons_bytes_c).
-- Regarding an ID_DAT frame: the FSS, CTRL, var and SUBS bytes are being followed by the
-- Engine_Control_FSM; the counter is used for the counting of the bytes from then on and until
-- the arrival of a FES. Therefore, the counter is reset at the "ID_DAT_SUBS_BYTE" state and counts
-- bytes following the "rx_byte_ready_p_i" pulse in the "ID_DAT_FRAME_OK" state.
-- Regarding a RP_DAT frame : the counter is reset at the "CONSUME_WAIT_FSS" state and counts
-- bytes following the "rx_byte_ready_p_i" pulse in the "CONSUME" state.
Rx_Bytes_Counter: wf_incr_counter
generic map(g_counter_lgth => 8)
port map(
uclk_i => uclk_i,
counter_reinit_i => s_rx_bytes_c_rst,
counter_incr_i => s_rx_bytes_c_inc,
counter_is_full_o => open,
-------------------------------------------------------
counter_o => s_rx_bytes_c);
-------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- --
s_rx_bytes_c_rst <= '0' when (s_id_dat_frame_ok = '1') or (s_consuming = '1') else '1';
s_rx_bytes_c_inc <= rx_byte_ready_p_i when (s_id_dat_frame_ok = '1') or (s_consuming = '1') else '0';
---------------------------------------------------------------------------------------------------
-- Independent Timeout Counter --
---------------------------------------------------------------------------------------------------
-- Instantiation of a wf_decr_counter relying only on the system clock as an additional
-- way to go back to IDLE state, in case any other logic is being stuck.
Session_Timeout_Counter: wf_decr_counter
generic map(g_counter_lgth => c_SESSION_TIMEOUT_C_LGTH)
port map(
uclk_i => uclk_i,
counter_rst_i => nfip_rst_i,
counter_top_i => (others => '1'),
counter_load_i => s_idle_state,
counter_decr_i => '1', -- on each uclk tick
counter_o => open,
---------------------------------------------------
counter_is_zero_o => s_session_timedout);
---------------------------------------------------
---------------------------------------------------------------------------------------------------
-- Turnaround & Silence times --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- retrieval of the turnaround and silence times (in equivalent number of uclk ticks) from the
-- c_TIMEOUTS_TABLE declared in the WF_PACKAGE unit.
s_turnaround_time <= to_unsigned((c_TIMEOUTS_TABLE(to_integer(unsigned(rate_i))).turnaround),
s_turnaround_time'length);
s_silence_time <= to_unsigned((c_TIMEOUTS_TABLE(to_integer(unsigned(rate_i))).silence),
s_turnaround_time'length);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Instantiation of a wf_decr_counter for the counting of turnaround and silence times.
-- The same counter is used in both cases. The signal s_time_c_top initializes the counter
-- to either the turnaround or the silence time. If after the correct arrival of an ID_DAT frame
-- the identified variable is a produced one the counter loads to the turnaround time, whereas if
-- it had been a consumed variable it loads to the silence. The counting takes place during the
-- states "PRODUCE_WAIT_TURNAR_TIME" and "CONSUME_WAIT_FSS" respectively.
Turnaround_and_Silence_Time_Counter: wf_decr_counter
generic map(g_counter_lgth => 18)
port map(
uclk_i => uclk_i,
counter_rst_i => nfip_rst_i,
counter_top_i => s_time_c_top,
counter_load_i => s_time_c_load,
counter_decr_i => '1', -- on each uclk tick
counter_o => open,
-------------------------------------------------------
counter_is_zero_o => s_time_c_is_zero);
-------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- --
s_time_c_top <= s_turnaround_time when (s_id_dat_frame_ok = '1' and s_prod_or_cons = "10") else s_silence_time;
s_time_c_load <= '0' when s_prod_wait_turnar_time= '1' or s_cons_wait_FSS = '1' else '1';
---------------------------------------------------------------------------------------------------
-- Identification of the variable received by an ID_DAT frame --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The following process generates the signals:
-- o internal signal s_var_aux that locks to the value of the ID_DAT.Identifier.Variable byte
-- upon its arrival
-- o output signal var_o (or s_var, used also internally by the wf_prod_data_lgth_calc) that
-- locks to the value of the ID_DAT.Identifier.Variable byte at the end of the reception of a
-- valid ID_DAT frame, if the received SUBS byte matches the station's address.
-- For a produced var this takes place at the "PRODUCE_WAIT_TURNAR_TIME" state, and
-- for a consumed at the "CONSUME" state (not in the "consume_wait_silence_time", as at this
-- state there is no knowledge that a consumed RP_DAT frame will indeed arrive!).
-- (the process is very simple but very big as we decided not to use a for loop:s)
ID_DAT_var: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_var_aux <= var_whatever;
s_var <= var_whatever;
s_prod_or_cons <= "00";
s_broadcast_var <= '0';
else
-------------------------------------------------------------------------------------------
if (s_idle_state = '1') or (s_id_dat_ctrl_byte = '1') then -- new frame initializations
s_var_aux <= var_whatever;
s_var <= var_whatever;
s_prod_or_cons <= "00";
s_broadcast_var <= '0';
-------------------------------------------------------------------------------------------
elsif (s_id_dat_var_byte = '1') and (rx_byte_ready_p_i = '1') then -- var byte arrived
case rx_byte_i is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).hexvalue =>
s_var_aux <= var_presence;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).hexvalue =>
s_var_aux <= var_identif;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when c_VARS_ARRAY(c_VAR_1_INDEX).hexvalue =>
s_var_aux <= var_1;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_1_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_1_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when c_VARS_ARRAY(c_VAR_2_INDEX).hexvalue =>
s_var_aux <= var_2;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_2_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_2_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when c_VARS_ARRAY(c_VAR_3_INDEX).hexvalue =>
s_var_aux <= var_3;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_3_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_3_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when c_VARS_ARRAY(c_VAR_RST_INDEX).hexvalue =>
s_var_aux <= var_rst;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_RST_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_RST_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when c_VARS_ARRAY(c_VAR_4_INDEX).hexvalue =>
s_var_aux <= var_4;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_4_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_4_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when c_VARS_ARRAY(c_VAR_5_INDEX).hexvalue =>
s_var_aux <= var_5;
s_prod_or_cons <= c_VARS_ARRAY(c_VAR_5_INDEX).prod_or_cons;
s_broadcast_var <= c_VARS_ARRAY(c_VAR_5_INDEX).broadcast;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
when others =>
s_var_aux <= var_whatever;
s_prod_or_cons <= "00";
s_broadcast_var <= '0';
end case;
-------------------------------------------------------------------------------------------
elsif (s_prod_wait_turnar_time = '1') or (s_consuming = '1') then -- ID_DAT OK!
s_var <= s_var_aux;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Concurrent signal assignment (used by the FSM)
s_var_identified <= '1' when rx_byte_i = c_VARS_ARRAY(c_VAR_PRESENCE_INDEX).hexvalue or
rx_byte_i = c_VARS_ARRAY(c_VAR_IDENTIF_INDEX).hexvalue or
rx_byte_i = c_VARS_ARRAY(c_VAR_RST_INDEX).hexvalue or
rx_byte_i = c_VARS_ARRAY(c_VAR_1_INDEX).hexvalue or
rx_byte_i = c_VARS_ARRAY(c_VAR_2_INDEX).hexvalue or
rx_byte_i = c_VARS_ARRAY(c_VAR_3_INDEX).hexvalue or
rx_byte_i = c_VARS_ARRAY(c_VAR_4_INDEX).hexvalue or
rx_byte_i = c_VARS_ARRAY(c_VAR_5_INDEX).hexvalue else '0';
---------------------------------------------------------------------------------------------------
-- Signals Registration --
---------------------------------------------------------------------------------------------------
process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
tx_last_data_byte_p_o <= '0';
s_tx_last_data_byte_p_d <= '0';
s_tx_byte_request_accept_p_d1 <= '0';
s_tx_byte_request_accept_p_d2 <= '0';
s_tx_start_prod_p <= '0';
else
s_tx_last_data_byte_p_d <= s_tx_last_data_byte_p;
tx_last_data_byte_p_o <= s_tx_last_data_byte_p_d;
s_tx_byte_request_accept_p_d1 <= s_tx_byte_request_accept_p;
s_tx_byte_request_accept_p_d2 <= s_tx_byte_request_accept_p_d1;
s_tx_start_prod_p <= (s_prod_wait_turnar_time and s_time_c_is_zero);
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- --
s_tx_byte_request_accept_p <= s_producing and (tx_byte_request_p_i or s_tx_start_prod_p);
s_tx_last_data_byte_p <= s_producing and s_prod_data_lgth_match and tx_byte_request_p_i;
---------------------------------------------------------------------------------------------------
-- Concurrent Signal Assignments --
---------------------------------------------------------------------------------------------------
-- variable received by a valid ID_DAT frame that concerns this station
var_o <= s_var;
-- number of bytes for the CTRL & Data fields of a produced RP_DAT frame
prod_data_lgth_o <= s_prod_data_lgth;
-- response to wf_tx_serializer request for a byte
tx_byte_request_accept_p_o <= s_tx_byte_request_accept_p_d2;
-- index of the byte being produced/ consumed
prod_byte_index_o <= std_logic_vector (s_prod_bytes_c);
cons_byte_index_o <= std_logic_vector (s_rx_bytes_c);
-- The wf_fd_receiver receives a 1 uclk long reset pulse if during the reception of an ID or an
-- RP_DAT the engine control FSM has to go back to IDLE.
-- This may happen if : any of the CTRL, variable, subs bytes of an ID_DAT frame are wrong or
-- an ID_DAT is lasting more than 8 bytes or
-- an RP_DAT is lasting more than 133 bytes or
-- the silence times expires
-- the engine control FSM times out
-- After this reset, the receiver will discard any frame being received and will restart looking
-- for the FSS of a new one.
-- The wf_fd_receiver also stays reset during a production session.
rx_rst_o <= '1' when (s_rst_rx_p = '1') or
(s_prod_wait_turnar_time = '1') or (s_producing = '1') else '0';
-- indication of a consumed RP_DAT frame with more than 133 bytes
cons_bytes_excess_o <= '1' when (s_consuming = '1') and (s_rx_bytes_c > c_MAX_FRAME_BYTES) else '0';
-- production starts after the expiration of the turnaround time
tx_start_p_o <= s_tx_start_prod_p;
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
|
mit
|
wltr/cern-fgclite
|
critical_fpga/src/rtl/cf_top.vhd
|
1
|
14885
|
-------------------------------------------------------------------------------
--! @file cf_top.vhd
--! @author Johannes Walter <[email protected]>
--! @copyright CERN TE-EPC-CCE
--! @date 2014-05-06
--! @brief FGClite Critical FPGA (CF) top-level.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.ab_pkg.all;
use work.nf_pkg.all;
use work.xf_pkg.all;
use work.sram_pkg.all;
--! @brief Entity declaration of cf_top
--! @details
--! The top-level component for the Critical FPGA implementation.
entity cf_top is
port (
--! @name Clock and resets
--! @{
--! System clock
clk_i : in std_ulogic;
--! Power-on reset
po_rst_i : inout std_logic;
--! Push-button reset
pb_rst_n_i : in std_ulogic;
--! NF reset
nf_rst_n_i : in std_ulogic;
--! @}
--! @name LEDs
--! @{
--! Red LEDs
leds_red_n_o : out std_ulogic_vector(5 downto 0);
--! Green LEDs
leds_green_n_o : out std_ulogic_vector(5 downto 0);
--! Test LEDs
leds_test_n_i : in std_ulogic;
--! @}
--! @name Power converter interface
--! @{
--! Power converter commands
conv_cmd_o : out std_ulogic_vector(7 downto 0);
--! Power converter status
conv_stat_i : in std_ulogic_vector(15 downto 0);
--! @}
--! @name External SRAM interface
--! @{
--! Address
sram_addr_o : out std_ulogic_vector(19 downto 0);
--! Control signals (CS2, OE, LB, UB, BYTE, CS1, WE)
sram_ctrl_o : out std_ulogic_vector(6 downto 0);
--! Data bus
sram_data_io : inout std_logic_vector(15 downto 0);
--! @}
--! @name Optical interface
--! @{
--! Optical input
optical_i : in std_ulogic_vector(1 downto 0);
--! @}
--! @name Analogue board interface
--! @{
--! Stop temperature control
ab_temp_stop_o : out std_ulogic;
--! Power control
ab_pwr_on_n_o : out std_ulogic;
--! @}
--! @name Analogue board calibration multiplexer (only one can be active)
--! @{
--! Set calibration source to DAC
ab_cal_dac_o : out std_ulogic;
--! Set calibration source to GND
ab_cal_offset_o : out std_ulogic;
--! Set calibration source to +VREF
ab_cal_vref_p_o : out std_ulogic;
--! Set calibration source to -VREF
ab_cal_vref_n_o : out std_ulogic;
--! @}
--! @name Analogue board DAC interface
--! @{
--! DAC data
ab_dac_din_o : out std_ulogic;
--! DAC clock
ab_dac_sclk_o : out std_ulogic;
--! DAC chip-select
ab_dac_cs_o : out std_ulogic;
--! @}
--! @name Analogue board ADC V_MEAS
--! @{
--! ADC V_MEAS bit streams M1 and M0
ab_adc_vs_i : in std_ulogic_vector(1 downto 0);
--! ADC V_MEAS bit stream clock
ab_adc_vs_clk_i : in std_ulogic;
--! ADC V_MEAS reset (active-low)
ab_adc_vs_rst_n_o : out std_ulogic;
--! Calibrate ADC V_MEAS
ab_sw_in_vs_o : out std_ulogic;
--! @}
--! @name Analogue board ADC I_A
--! @{
--! ADC I_A bit streams M1 and M0
ab_adc_a_i : in std_ulogic_vector(1 downto 0);
--! ADC I_A bit stream clock
ab_adc_a_clk_i : in std_ulogic;
--! ADC I_A reset (active-low)
ab_adc_a_rst_n_o : out std_ulogic;
--! Calibrate ADC I_A
ab_sw_in_a_o : out std_ulogic;
--! @}
--! @name Analogue board ADC I_B
--! @{
--! ADC I_B bit streams M1 and M0
ab_adc_b_i : in std_ulogic_vector(1 downto 0);
--! ADC I_B bit stream clock
ab_adc_b_clk_i : in std_ulogic;
--! ADC I_B reset (active-low)
ab_adc_b_rst_n_o : out std_ulogic;
--! Calibrate ADC I_B
ab_sw_in_b_o : out std_ulogic;
--! @}
--! @name Interlocks
--! @{
--! Interlock inputs
interlock_i : in std_ulogic_vector(1 downto 0);
--! Interlock outputs
interlock_o : out std_ulogic_vector(1 downto 0);
--! @}
--! @name PF interface
--! @{
--! Send power cycle request to PF
pf_req_n_o : out std_ulogic;
--! Enable power down on PF
pf_pwr_dwn_en_o : out std_ulogic;
--! Failure flag from PF
pf_pwr_flr_i : in std_ulogic;
--! Power down signal from PF
pf_pwr_dwn_i : in std_ulogic;
--! @}
--! @name NF interface
--! @{
--! NF received FGClite CMD 0
nf_cmd_0_i : in std_ulogic;
--! NF transmitter ready
nf_tx_rdy_i : in std_ulogic;
--! NanoFIP status byte - bit 5
nf_r_fcser_i : in std_ulogic;
--! NanoFIP status byte - bit 4
nf_r_tler_i : in std_ulogic;
--! NanoFIP status byte - bit 2
nf_u_cacer_i : in std_ulogic;
--! NanoFIP status byte - bit 3
nf_u_pacer_i : in std_ulogic;
--! @}
--! @name 3-wire serial receiver from NF
--! @{
--! Frame
nf_rx_frame_i : in std_ulogic;
--! Bit enable
nf_rx_bit_en_i : in std_ulogic;
--! Data
nf_rx_i : in std_ulogic;
--! @}
--! @name 3-wire serial transmitter to NF
--! @{
--! Frame
nf_tx_frame_o : out std_ulogic;
--! Bit enable
nf_tx_bit_en_o : out std_ulogic;
--! Data
nf_tx_o : out std_ulogic;
--! @}
--! @name 2 x 3-wire serial receiver from XF
--! @{
--! Frame
xf_rx_frame_i : in std_ulogic_vector(1 downto 0);
--! Bit enable
xf_rx_bit_en_i : in std_ulogic_vector(1 downto 0);
--! Data
xf_rx_i : in std_ulogic_vector(1 downto 0);
--! @}
--! @name Control signals to XF
--! @{
--! Trigger DIM bus readout
xf_dim_trig_o : out std_ulogic;
--! Reset all DIMs on bus
xf_dim_rst_o : out std_ulogic;
--! Trigger 1-wire bus readout
xf_ow_trig_o : out std_ulogic;
--! 1-wire bus select
xf_ow_bus_sel_o : out std_ulogic_vector(2 downto 0);
--! @}
--! @name Auxiliary interface (UART to diagnostics connector)
--! @{
--! Input
aux_i : in std_ulogic;
--! Output
aux_o : out std_ulogic;
--! @}
--! @name Debugging
--! @{
--! Serial receiver
debug_rx_i : in std_ulogic;
--! Serial transmitter
debug_tx_o : out std_ulogic;
--! Debugging probe
debug_probe_o : out std_ulogic);
--! @}
end entity cf_top;
--! RTL implementation of cf_top
architecture rtl of cf_top is
---------------------------------------------------------------------------
--! @name Internal Wires
---------------------------------------------------------------------------
--! @{
-- Safe reset generation
signal po_rst_n : std_ulogic;
signal pb_rst_n : std_ulogic;
signal nf_rst_n : std_ulogic;
signal rst_n : std_ulogic;
-- Input synchronization and glitch filter
signal leds_test_n_syn : std_ulogic;
signal conv_stat_syn : std_ulogic_vector(15 downto 0);
signal optical_syn : std_ulogic_vector(1 downto 0);
signal interlock_syn : std_ulogic_vector(1 downto 0);
signal pf_pwr_flr_syn : std_ulogic;
signal pf_pwr_dwn_syn : std_ulogic;
signal aux_syn : std_ulogic;
signal debug_rx_syn : std_ulogic;
-- External SRAM interface
signal sram_in : sram_in_t;
signal sram_out : sram_out_t;
-- Analogue board interface
signal ab_in : ab_in_t;
signal ab_out : ab_out_t;
-- NanoFIP interface
signal nf_in : nf_in_t;
signal nf_out : nf_out_t;
-- Auxiliary FPGA interface
signal xf_in : xf_in_t;
signal xf_out : xf_out_t;
--! @}
begin -- architecture rtl
---------------------------------------------------------------------------
-- Outputs
---------------------------------------------------------------------------
-- External SRAM interface
sram_data_io <= std_logic_vector(sram_out.data) when sram_out.we_n = '0' else (others => 'Z');
sram_addr_o <= sram_out.addr;
sram_ctrl_o(0) <= sram_out.we_n;
sram_ctrl_o(1) <= sram_out.cs1_n;
sram_ctrl_o(2) <= sram_out.byte_n;
sram_ctrl_o(3) <= sram_out.ue_n;
sram_ctrl_o(4) <= sram_out.le_n;
sram_ctrl_o(5) <= sram_out.oe_n;
sram_ctrl_o(6) <= sram_out.cs2;
-- Analogue board interface
ab_temp_stop_o <= ab_out.temp_stop;
ab_pwr_on_n_o <= ab_out.pwr_on_n;
ab_cal_dac_o <= ab_out.cal_dac;
ab_cal_offset_o <= ab_out.cal_offset;
ab_cal_vref_p_o <= ab_out.cal_vref_p;
ab_cal_vref_n_o <= ab_out.cal_vref_n;
ab_dac_din_o <= ab_out.dac_din;
ab_dac_sclk_o <= ab_out.dac_sclk;
ab_dac_cs_o <= ab_out.dac_cs;
ab_adc_vs_rst_n_o <= ab_out.adc_vs_rst_n;
ab_sw_in_vs_o <= ab_out.sw_in_vs;
ab_adc_a_rst_n_o <= ab_out.adc_a_rst_n;
ab_sw_in_a_o <= ab_out.sw_in_a;
ab_adc_b_rst_n_o <= ab_out.adc_b_rst_n;
ab_sw_in_b_o <= ab_out.sw_in_b;
-- NanoFIP interface
nf_tx_frame_o <= nf_out.tx_frame;
nf_tx_bit_en_o <= nf_out.tx_bit_en;
nf_tx_o <= nf_out.tx;
-- Auxiliary FPGA interface
xf_dim_trig_o <= xf_out.dim_trig;
xf_dim_rst_o <= xf_out.dim_rst;
xf_ow_trig_o <= xf_out.ow_trig;
xf_ow_bus_sel_o <= xf_out.ow_bus_select;
---------------------------------------------------------------------------
-- Signal Assignments
---------------------------------------------------------------------------
-- Safe reset generation
rst_n <= po_rst_n and pb_rst_n and nf_rst_n;
---------------------------------------------------------------------------
-- Instances
---------------------------------------------------------------------------
--! Power-on reset generation for Microsemi devices
po_reset_inst : entity work.microsemi_reset_generator
generic map (
num_delay_g => 4,
active_g => '0')
port map (
clk_i => clk_i,
rst_asy_io => po_rst_i,
rst_o => po_rst_n);
--! Safe push-button reset generation
pb_reset_inst : entity work.reset_generator
generic map (
num_delay_g => 4,
active_g => '0')
port map (
clk_i => clk_i,
rst_asy_i => pb_rst_n_i,
rst_o => pb_rst_n);
--! Safe NF reset generation
nf_reset_inst : entity work.reset_generator
generic map (
num_delay_g => 4,
active_g => '0')
port map (
clk_i => clk_i,
rst_asy_i => nf_rst_n_i,
rst_o => nf_rst_n);
--! Input synchronization and glitch filter for power converter status
ext_inputs_inst_0 : entity work.external_inputs
generic map (
init_value_g => '0',
num_inputs_g => conv_stat_i'length)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_n,
rst_syn_i => '0',
sig_i => conv_stat_i,
sig_o => conv_stat_syn);
--! Input synchronization and glitch filter for SRAM data
ext_inputs_inst_1 : entity work.external_inputs
generic map (
init_value_g => '0',
num_inputs_g => sram_data_io'length)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_n,
rst_syn_i => '0',
sig_i => std_ulogic_vector(sram_data_io),
sig_o => sram_in.data);
--! Input synchronization and glitch filter for all other inputs
ext_inputs_inst_2 : entity work.external_inputs
generic map (
init_value_g => '0',
num_inputs_g => 33)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_n,
rst_syn_i => '0',
sig_i(0) => leds_test_n_i,
sig_i(1) => optical_i(0),
sig_i(2) => optical_i(1),
sig_i(3) => ab_adc_vs_i(0),
sig_i(4) => ab_adc_vs_i(1),
sig_i(5) => ab_adc_vs_clk_i,
sig_i(6) => ab_adc_a_i(0),
sig_i(7) => ab_adc_a_i(1),
sig_i(8) => ab_adc_a_clk_i,
sig_i(9) => ab_adc_b_i(0),
sig_i(10) => ab_adc_b_i(1),
sig_i(11) => ab_adc_b_clk_i,
sig_i(12) => interlock_i(0),
sig_i(13) => interlock_i(1),
sig_i(14) => pf_pwr_flr_i,
sig_i(15) => pf_pwr_dwn_i,
sig_i(16) => nf_cmd_0_i,
sig_i(17) => nf_tx_rdy_i,
sig_i(18) => nf_r_fcser_i,
sig_i(19) => nf_r_tler_i,
sig_i(20) => nf_u_cacer_i,
sig_i(21) => nf_u_pacer_i,
sig_i(22) => nf_rx_frame_i,
sig_i(23) => nf_rx_bit_en_i,
sig_i(24) => nf_rx_i,
sig_i(25) => xf_rx_frame_i(0),
sig_i(26) => xf_rx_frame_i(1),
sig_i(27) => xf_rx_bit_en_i(0),
sig_i(28) => xf_rx_bit_en_i(1),
sig_i(29) => xf_rx_i(0),
sig_i(30) => xf_rx_i(1),
sig_i(31) => aux_i,
sig_i(32) => debug_rx_i,
sig_o(0) => leds_test_n_syn,
sig_o(1) => optical_syn(0),
sig_o(2) => optical_syn(1),
sig_o(3) => ab_in.adc_vs(0),
sig_o(4) => ab_in.adc_vs(1),
sig_o(5) => ab_in.adc_vs_clk,
sig_o(6) => ab_in.adc_a(0),
sig_o(7) => ab_in.adc_a(1),
sig_o(8) => ab_in.adc_a_clk,
sig_o(9) => ab_in.adc_b(0),
sig_o(10) => ab_in.adc_b(1),
sig_o(11) => ab_in.adc_b_clk,
sig_o(12) => interlock_syn(0),
sig_o(13) => interlock_syn(1),
sig_o(14) => pf_pwr_flr_syn,
sig_o(15) => pf_pwr_dwn_syn,
sig_o(16) => nf_in.cmd_0,
sig_o(17) => nf_in.tx_rdy,
sig_o(18) => nf_in.r_fcser,
sig_o(19) => nf_in.r_tler,
sig_o(20) => nf_in.u_cacer,
sig_o(21) => nf_in.u_pacer,
sig_o(22) => nf_in.rx_frame,
sig_o(23) => nf_in.rx_bit_en,
sig_o(24) => nf_in.rx,
sig_o(25) => xf_in.rx_frame(0),
sig_o(26) => xf_in.rx_frame(1),
sig_o(27) => xf_in.rx_bit_en(0),
sig_o(28) => xf_in.rx_bit_en(1),
sig_o(29) => xf_in.rx(0),
sig_o(30) => xf_in.rx(1),
sig_o(31) => aux_syn,
sig_o(32) => debug_rx_syn);
--! CF core component
cf_inst : entity work.cf
port map (
clk_i => clk_i,
rst_asy_n_i => rst_n,
rst_syn_i => '0',
leds_red_n_o => leds_red_n_o,
leds_green_n_o => leds_green_n_o,
leds_test_n_i => leds_test_n_syn,
conv_cmd_o => conv_cmd_o,
conv_stat_i => conv_stat_syn,
sram_i => sram_in,
sram_o => sram_out,
optical_i => optical_syn,
ab_i => ab_in,
ab_o => ab_out,
interlock_i => interlock_syn,
interlock_o => interlock_o,
pf_req_n_o => pf_req_n_o,
pf_pwr_dwn_en_o => pf_pwr_dwn_en_o,
pf_pwr_flr_i => pf_pwr_flr_syn,
pf_pwr_dwn_i => pf_pwr_dwn_syn,
nf_i => nf_in,
nf_o => nf_out,
xf_i => xf_in,
xf_o => xf_out,
aux_i => aux_syn,
aux_o => aux_o,
debug_rx_i => debug_rx_syn,
debug_tx_o => debug_tx_o,
debug_probe_o => debug_probe_o);
end architecture rtl;
|
mit
|
wltr/cern-fgclite
|
nanofip_fpga/src/rtl/nanofip/wf_crc.vhd
|
1
|
10402
|
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- wf_crc |
-- |
---------------------------------------------------------------------------------------------------
-- File wf_crc.vhd |
-- |
-- Description The unit creates the modules for: |
-- o the generation of the CRC of serial data, |
-- o the verification of an incoming CRC syndrome. |
-- The unit is instantiated in both the wf_fd_transmitter, for the generation of the |
-- FCS field of produced RP_DAT frames, and the wf_fd_receiver for the validation of |
-- of an incoming ID_DAT or consumed RP_DAT frame. |
-- |
-- Authors Pablo Alvarez Sanchez ([email protected]) |
-- Date 23/02/2011 |
-- Version v0.04 |
-- Depends on wf_reset_unit |
-- wf_rx_deserializer |
-- wf_tx_serializer |
---------------- |
-- Last changes |
-- 07/08/2009 v0.02 PAS Entity Ports added, start of architecture content |
-- 08/2010 v0.03 EG Data_FCS_select and crc_ready_p_o signals removed, |
-- variable v_q_check_mask replaced with a signal, |
-- code cleaned-up+commented |
-- 02/2011 v0.04 EG s_q_check_mask was not in Syndrome_Verification sensitivity list! |
-- xor replaced with if(Syndrome_Verification); processes rewritten; |
-- delay on data_bit_ready_p_i removed. |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for wf_crc
--=================================================================================================
entity wf_crc is port(
-- INPUTS
-- nanoFIP User Interface, General signals
uclk_i : in std_logic; -- 40 MHz clock
-- Signal from the wf_reset_unit
nfip_rst_i : in std_logic; -- nanoFIP internal reset
-- Signals from the wf_rx_deserializer/ wf_tx_serializer units
data_bit_i : in std_logic; -- incoming data bit stream
data_bit_ready_p_i : in std_logic; -- indicates the sampling moment of data_bit_i
start_crc_p_i : in std_logic; -- beginning of the CRC calculation
-- OUTPUTS
-- Signal to the wf_rx_deserializer unit
crc_ok_p_o : out std_logic; -- signals a correct received CRC syndrome
-- Signal to the wf_tx_serializer unit
crc_o : out std_logic_vector (c_CRC_POLY_LGTH-1 downto 0)); -- calculated CRC
end entity wf_crc;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of wf_crc is
signal s_q, s_q_nx : std_logic_vector (c_CRC_POLY_LGTH - 1 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- CRC Calculation --
---------------------------------------------------------------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- The Gen_16_bit_Register_and_Interconnections generator, follows the scheme of figure A.1
-- of the Annex A 61158-4-7 IEC:2007 and constructs a register of 16 master-slave flip-flops which
-- are interconnected as a linear feedback shift register.
Generate_16_bit_Register_and_Interconnections:
s_q_nx(0) <= data_bit_i xor s_q(s_q'left);
G: for I in 1 to c_CRC_GENER_POLY'left generate
s_q_nx(I) <= s_q(I-1) xor (c_CRC_GENER_POLY(I) and (data_bit_i xor s_q(s_q'left)));
end generate;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Synchronous process CRC_calculation: the process "moves" the shift register described
-- above, for the calculation of the CRC.
CRC_calculation: process (uclk_i)
begin
if rising_edge (uclk_i) then
if nfip_rst_i = '1' then
s_q <= (others => '0');
else
if start_crc_p_i = '1' then
s_q <= (others => '1'); -- register initialization
-- (initially preset, according to the Annex)
elsif data_bit_ready_p_i = '1' then -- new bit to be considered for the CRC calculation
s_q <= s_q_nx; -- data propagation
end if;
end if;
end if;
end process;
-- -- -- -- --
crc_o <= not s_q;
---------------------------------------------------------------------------------------------------
-- CRC Verification --
---------------------------------------------------------------------------------------------------
-- During reception, the CRC is being calculated as data is arriving (same as in the transmission)
-- and at the same time it is being compared to the predefined c_CRC_VERIF_POLY. When the CRC
-- calculated from the received data matches the c_CRC_VERIF_POLY, it is implied that a correct CRC
-- word has been received for the preceded data and the signal crc_ok_p_o gives a 1 uclk-wide pulse.
crc_ok_p_o <= data_bit_ready_p_i when s_q = not c_CRC_VERIF_POLY else '0';
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
|
mit
|
marceloboeira/vhdl-examples
|
004-clock-divider/source.vhd
|
1
|
704
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clock_div is
Port ( clock_50m : in STD_LOGIC;
reset : in STD_LOGIC;
led : out STD_LOGIC);
end clock_div;
architecture Behavioral of clock_div is
signal counter : integer range 0 to 25000 := 0;
signal led_tmp : STD_LOGIC := '0';
begin
process (clock_50m, reset)
begin
if reset='1' then
led <= '0'; -- '0' -> Binary
counter <= 0; -- 0 -> Decimal
elsif (clock_50m'event and clock_50m='1') then
if (counter < 25000) then
counter <= counter + 1;
else
counter <= 0;
led_tmp <= not led_tmp;
end if;
end if;
end process;
led <= led_tmp;
end Behavioral;
|
mit
|
jdryg/tis100cpu
|
reg.vhd
|
1
|
569
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity reg is
Generic(WIDTH: integer := 8);
Port (
I_clk : in STD_LOGIC;
I_reset : in STD_LOGIC;
I_dataIn : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
O_dataOut : out STD_LOGIC_VECTOR (WIDTH-1 downto 0));
end reg;
architecture Behavioral of reg is
begin
process (I_clk) begin
if (rising_edge(I_clk)) then
if(I_reset = '1') then
O_dataOut <= (others => '0');
else
O_dataOut <= I_dataIn;
end if;
end if;
end process;
end Behavioral;
|
mit
|
Abeergit/UART
|
UART_RX.vhd
|
1
|
3595
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity uart_rx is
generic ( DBIT : integer := 8; --Anzahl Datenbits
SB_TICK : integer := 16; --Anzahl ticks für Stopbit
PARITY_EN: std_logic := '1' );
port (clk : in std_logic; --clock
reset : in std_logic; --reset
rx : in std_logic; --empfangenes bit
s_tick : in std_logic; --sample tick, für (16x baudrate)
rx_done_tick : out std_logic; --tick welches angibt, dass die Uebertragung abgeschlossen ist
framing_error_tick: out std_logic;
dout : out std_logic_vector (7 downto 0); --die aufgenommenen Bits in paralleler Form
parity_error : out std_logic);
end uart_rx;
architecture main of uart_rx is
type state_type is (idle, start, data, parity, stop);
signal parity_bit, parity_rx : std_logic;
signal state_reg, state_next : state_type; --Status Register
signal s_reg, s_next : unsigned (3 downto 0); --sample register
signal n_reg, n_next : unsigned (3 downto 0); --Anzahl empfangener Datenbits
signal b_reg, b_next : std_logic_vector (7 downto 0); --Datenwort
begin
process(clk,reset)
begin
if (rising_edge(clk) and clk='1') then
if reset = '1' then
state_reg <= idle;
s_reg <= (others=>'0');
n_reg <= (others=>'0');
b_reg <= (others=>'0');
elsif reset = '0' then
state_reg <= state_next;
s_reg <= s_next;
n_reg <= n_next;
b_reg <= b_next;
end if;
end if;
end process;
process(state_reg, s_reg, n_reg, b_reg, s_tick, rx)
begin
state_next <= state_reg;
s_next <= s_reg;
n_next <= n_reg;
b_next <= b_reg;
rx_done_tick <= '0';
framing_error_tick <= '0';
case state_reg is
when idle =>
if (rx='0') then
state_next <= start;
s_next <= (others => '0');
end if;
when start =>
if (s_tick = '1') then
if (s_reg = 7) then
state_next <= data;
s_next <= (others => '0');
n_next <= (others => '0');
else
s_next <= s_reg + 1;
end if;
end if;
when data =>
if (s_tick = '1') then
if (s_reg = 15) then
s_next <= (others => '0');
b_next <= rx & b_reg(7 downto 1);
if n_reg=(DBIT-1) then
if PARITY_EN = '1' then
state_next <= parity;
elsif PARITY_EN = '0' then
state_next <= stop;
end if;
else
n_next <= n_reg + 1;
end if;
else
s_next <= s_reg + 1;
end if;
end if;
when parity =>
parity_bit <= (b_reg(0) xor b_reg(1)) xor (b_reg(2) xor b_reg(3)) xor (b_reg(4) xor b_reg(5)) xor (b_reg(6) xor b_reg(7)); --even parity
if (s_tick = '1') then
if s_reg = 15 then
s_next <= (others => '0');
parity_rx <= rx;
parity_error <= rx xor parity_bit;
state_next <= stop;
else
s_next <= s_reg + 1;
end if;
end if;
when stop =>
if (s_tick = '1') then
if (s_reg = SB_TICK - 1) then
rx_done_tick <= '1';
if (rx = '1') then
state_next <= idle;
else
framing_error_tick <= '1';
if (rx = '1') then
state_next <= idle;
end if;
end if;
else
s_next <= s_reg + 1;
if (rx = '0') then
framing_error_tick <= '1';
end if;
end if;
end if;
end case;
end process;
dout <= b_reg;
end main;
|
mit
|
CyAScott/CIS4930.DatapathSynthesisTool
|
docs/sample2/c_register.vhd
|
1
|
752
|
library IEEE;
use ieee.std_logic_1164.all;
entity c_register is
generic
(
width : integer := 4
);
port
(
input : in std_logic_vector((width - 1) downto 0);
wr : in std_logic;
clear : in std_logic;
clock : in std_logic;
output : out std_logic_vector((width - 1) downto 0)
);
end c_register;
architecture behavior of c_register is
begin
process (clock, clear, input, wr)
variable interim_val : std_logic_vector((width - 1) downto 0);
begin
if (clear = '1' and clear'event) then
for i in width - 1 downto 0 loop
interim_val(i) := '0';
end loop;
elsif (wr = '1' and clock = '1' and (clock'event or input'event or wr'event)) then
interim_val := input;
end if;
output <= interim_val;
end process;
end behavior;
|
mit
|
jdryg/tis100cpu
|
cpu_1x3.vhd
|
1
|
6784
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity cpu_1x3 is
generic (
PROGRAM_00 : string := "input.prg";
PROGRAM_01 : string := "passthrough.prg";
PROGRAM_02 : string := "output.prg");
port (
I_clk : in std_logic;
I_reset : in std_logic);
end cpu_1x3;
architecture Behavioral of cpu_1x3 is
component ben is
Generic (PROGRAM_FILENAME : string);
Port ( I_clk, I_reset : in STD_LOGIC;
I_puw_dataValid : in STD_LOGIC;
I_pdw_dataValid : in STD_LOGIC;
I_plw_dataValid : in STD_LOGIC;
I_prw_dataValid : in STD_LOGIC;
I_pur_dataValid : in STD_LOGIC;
I_pdr_dataValid : in STD_LOGIC;
I_plr_dataValid : in STD_LOGIC;
I_prr_dataValid : in STD_LOGIC;
I_pur_data : in STD_LOGIC_VECTOR (15 downto 0);
I_pdr_data : in STD_LOGIC_VECTOR (15 downto 0);
I_plr_data : in STD_LOGIC_VECTOR (15 downto 0);
I_prr_data : in STD_LOGIC_VECTOR (15 downto 0);
O_puw_writeEnable : out STD_LOGIC;
O_pdw_writeEnable : out STD_LOGIC;
O_plw_writeEnable : out STD_LOGIC;
O_prw_writeEnable : out STD_LOGIC;
O_puw_data : out STD_LOGIC_VECTOR (15 downto 0);
O_pdw_data : out STD_LOGIC_VECTOR (15 downto 0);
O_plw_data : out STD_LOGIC_VECTOR (15 downto 0);
O_prw_data : out STD_LOGIC_VECTOR (15 downto 0);
O_pur_readEnable : out STD_LOGIC;
O_pdr_readEnable : out STD_LOGIC;
O_plr_readEnable : out STD_LOGIC;
O_prr_readEnable : out STD_LOGIC);
end component;
component node_port is
generic (WIDTH: integer := 8);
port ( I_clk : in STD_LOGIC;
I_reset : in STD_LOGIC;
I_writeEnable: in STD_LOGIC;
I_readEnable: in STD_LOGIC;
I_dataIn : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
O_dataOut : out STD_LOGIC_VECTOR (WIDTH-1 downto 0);
O_dataOutValid : out STD_LOGIC); -- TODO: Check if this is actually needed. We can reset the O_dataOut(0) to Z or U instead.
end component;
signal inputWriteMainRead_writeEnable : STD_LOGIC := '0';
signal inputWriteMainRead_readEnable : STD_LOGIC := '0';
signal input_dataOut : STD_LOGIC_VECTOR (15 downto 0) := X"0000";
signal main_dataIn : STD_LOGIC_VECTOR (15 downto 0) := X"0000";
signal main_dataInValid : STD_LOGIC := '0';
signal mainWriteOutputRead_writeEnable : STD_LOGIC := '0';
signal mainWriteOutputRead_readEnable : STD_LOGIC := '0';
signal main_dataOut : STD_LOGIC_VECTOR (15 downto 0) := X"0000";
signal output_dataIn : STD_LOGIC_VECTOR (15 downto 0) := X"0000";
signal output_dataInValid : STD_LOGIC := '0';
begin
inputWriteMainRead : node_port
generic map(WIDTH => 16)
port map(
I_clk => I_clk,
I_reset => I_reset,
I_writeEnable => inputWriteMainRead_writeEnable,
I_readEnable => inputWriteMainRead_readEnable,
I_dataIn => input_dataOut,
O_dataOut => main_dataIn,
O_dataOutValid => main_dataInValid);
mainWriteOutputRead: node_port
generic map(WIDTH => 16)
port map(
I_clk => I_clk,
I_reset => I_reset,
I_writeEnable => mainWriteOutputRead_writeEnable,
I_readEnable => mainWriteOutputRead_readEnable,
I_dataIn => main_dataOut,
O_dataOut => output_dataIn,
O_dataOutValid => output_dataInValid);
-- Input BEN
inputBEN: ben
generic map(PROGRAM_FILENAME => PROGRAM_00)
port map(
I_clk => I_clk,
I_reset => I_reset,
-- Read
-- Input BENs should not read anything
I_pur_dataValid => '0',
I_pdr_dataValid => '0',
I_plr_dataValid => '0',
I_prr_dataValid => '0',
I_pur_data => X"0000",
I_pdr_data => X"0000",
I_plr_data => X"0000",
I_prr_data => X"0000",
O_pur_readEnable => open,
O_pdr_readEnable => open,
O_plr_readEnable => open,
O_prr_readEnable => open,
-- Write
I_puw_dataValid => '0',
I_pdw_dataValid => main_dataInValid,
I_plw_dataValid => '0',
I_prw_dataValid => '0',
O_puw_writeEnable => open,
O_pdw_writeEnable => inputWriteMainRead_writeEnable,
O_plw_writeEnable => open,
O_prw_writeEnable => open,
O_puw_data => open,
O_pdw_data => input_dataOut,
O_plw_data => open,
O_prw_data => open);
-- Main BEN
mainBEN: ben
generic map(PROGRAM_FILENAME => PROGRAM_01)
port map(
I_clk => I_clk,
I_reset => I_reset,
-- Read
I_pur_dataValid => main_dataInValid,
I_pdr_dataValid => '0',
I_plr_dataValid => '0',
I_prr_dataValid => '0',
I_pur_data => main_dataIn,
I_pdr_data => X"0000",
I_plr_data => X"0000",
I_prr_data => X"0000",
O_pur_readEnable => inputWriteMainRead_readEnable,
O_pdr_readEnable => open,
O_plr_readEnable => open,
O_prr_readEnable => open,
-- Write
I_puw_dataValid => '0', -- Don't write to input BENs
I_pdw_dataValid => output_dataInValid,
I_plw_dataValid => '0', -- No left BEN
I_prw_dataValid => '0', -- No right BEN
O_puw_writeEnable => open, -- Don't write to input BENs
O_pdw_writeEnable => mainWriteOutputRead_writeEnable,
O_plw_writeEnable => open, -- No left BEN
O_prw_writeEnable => open, -- No right BEN
O_puw_data => open, -- Don't write to input BENs
O_pdw_data => main_dataOut,
O_plw_data => open, -- No left BEN
O_prw_data => open); -- No right BEN
-- Output BEN
outputBEN: ben
generic map(PROGRAM_FILENAME => PROGRAM_02)
port map(
I_clk => I_clk,
I_reset => I_reset,
-- Read
I_pur_dataValid => output_dataInValid,
I_pdr_dataValid => '0',
I_plr_dataValid => '0',
I_prr_dataValid => '0',
I_pur_data => output_dataIn,
I_pdr_data => X"0000",
I_plr_data => X"0000",
I_prr_data => X"0000",
O_pur_readEnable => mainWriteOutputRead_readEnable,
O_pdr_readEnable => open,
O_plr_readEnable => open,
O_prr_readEnable => open,
-- Write
-- Output BENs should not write anything
I_puw_dataValid => '0',
I_pdw_dataValid => '0',
I_plw_dataValid => '0',
I_prw_dataValid => '0',
O_puw_writeEnable => open,
O_pdw_writeEnable => open,
O_plw_writeEnable => open,
O_prw_writeEnable => open,
O_puw_data => open,
O_pdw_data => open,
O_plw_data => open,
O_prw_data => open);
end Behavioral;
|
mit
|
marceloboeira/vhdl-examples
|
008-state-machine-calculator/_example/teste_display_e_botao.vhd
|
1
|
1652
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:01:32 06/10/2013
-- Design Name:
-- Module Name: teste_display_e_botao - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
entity teste_display_e_botao is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
botao : in STD_LOGIC;
saida_8segmentos : out STD_LOGIC_VECTOR (7 downto 0);
disp_sel_o : out STD_LOGIC_VECTOR (3 downto 0);
led : out STD_LOGIC);
end teste_display_e_botao;
architecture Behavioral of teste_display_e_botao is
signal entrada_disp, display_s : STD_LOGIC_VECTOR (15 downto 0);
signal clk1s, botao_DB : std_logic :='0';
signal cnt : integer range 0 to 9999;
begin
meu_proj : entity work.meu_projeto
Port map ( clock => clock,
reset => reset,
botao => botao_DB,
saida => entrada_disp,
led => led) ;
debouce_n1 :entity work.debounce
port map ( clock => clock,
entrada => botao,
saida_DB => botao_DB
);
display : entity work.modulo_display
Port map( clock => clock,
reset => reset,
entrada_s => entrada_disp,
saida_8segmentos => saida_8segmentos,
disp_sel_o => disp_sel_o
);
end Behavioral;
|
mit
|
marceloboeira/vhdl-examples
|
006-ULA/lib/or.vhd
|
1
|
312
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity OR_PROCESS is
Port (A : in STD_LOGIC_VECTOR (7 downto 0);
B : in STD_LOGIC_VECTOR (7 downto 0);
O : out STD_LOGIC_VECTOR (7 downto 0));
end OR_PROCESS;
architecture Behavioral of OR_PROCESS is
begin
O <= A or B;
end Behavioral;
|
mit
|
jdryg/tis100cpu
|
register_file.vhd
|
1
|
1900
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity register_file is
generic (WIDTH : integer := 8);
port ( I_clk : in STD_LOGIC;
I_swp : in STD_LOGIC;
I_enableWrite : in STD_LOGIC;
I_srcAID : in STD_LOGIC_VECTOR (1 downto 0);
I_srcBID : in STD_LOGIC_VECTOR (1 downto 0);
I_dstID : in STD_LOGIC_VECTOR (1 downto 0);
I_dstData : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
O_srcAData : out STD_LOGIC_VECTOR (WIDTH-1 downto 0);
O_srcBData : out STD_LOGIC_VECTOR (WIDTH-1 downto 0));
end register_file;
architecture Behavioral of register_file is
-- 4 registers (NIL, ACC, BAK, TMP)
type regstype is array (0 to 3) of STD_LOGIC_VECTOR (WIDTH-1 downto 0);
type regindextype is array (0 to 3) of integer range 0 to 3;
signal regID: regindextype := (0, 1, 2, 3);
signal regs: regstype := (X"0000", X"0000", X"0000", X"0000");
begin
-- Write reg on rising edge of the clock.
process(I_clk) begin
if(rising_edge(I_clk)) then
if(I_swp = '1') then
regID(1) <= 3 - regID(1);
regID(2) <= 3 - regID(2);
end if;
if(I_enableWrite = '1') then
regs(regID(to_integer(unsigned(I_dstID)))) <= I_dstData;
end if;
end if;
end process;
-- Read 2 regs
process(I_clk, I_srcAID, I_srcBID) begin
-- Check for the special NIL register in order to make sure we always read 0,
-- independent of the value actually written to this register.
if(I_srcAID = "00") then
O_srcAData <= (others => '0');
else
O_srcAData <= regs(regID(to_integer(unsigned(I_srcAID))));
end if;
if(I_srcBID = "00") then
O_srcBData <= (others => '0');
else
O_srcBData <= regs(regID(to_integer(unsigned(I_srcBID))));
end if;
end process;
end Behavioral;
|
mit
|
CyAScott/CIS4930.DatapathSynthesisTool
|
src/components/gen_AND_bit.vhd
|
1
|
506
|
library ieee;
use ieee.std_logic_1164.all;
entity gen_AND_bit is
generic
(
width : integer := 4
);
port
(
input : std_logic_vector(width - 1 downto 0);
output : out std_logic
);
end gen_AND_bit;
architecture Behavior of gen_AND_bit is
begin
P0 : process (input)
variable result : std_logic;
begin
result := '1';
L1 : for n in width - 1 downto 0 loop
if input(n) = '0' then
result := '0';
exit L1;
end if;
end loop L1;
output <= result;
end process P0;
end Behavior;
|
mit
|
CyAScott/CIS4930.DatapathSynthesisTool
|
src/components/c_adder.vhd
|
1
|
1914
|
library ieee;
use ieee.std_logic_1164.all;
library WORK;
use WORK.all;
entity c_adder is
generic
(
width : integer := 4
);
port
(
input1, input2 : in std_logic_vector((width - 1) downto 0);
output : out std_logic_vector(width downto 0)
);
end c_adder;
architecture behavior of c_adder is
begin
P0 : process (input1, input2)
variable carry : std_logic := '0';
variable overflow : std_logic := '0';
variable temp : std_logic_vector(width downto 0);
begin
for i in 0 to width - 1 loop
if input1(i) = '0' and input2(i) = '0' and carry = '0' then
temp(i) := '0';
carry := '0';
elsif input1(i) = '0' and input2(i) = '0' and carry = '1' then
temp(i) := '1';
carry := '0';
elsif input1(i) = '0' and input2(i) = '1' and carry = '0' then
temp(i) := '1';
carry := '0';
elsif input1(i) = '0' and input2(i) = '1' and carry = '1' then
temp(i) := '0';
carry := '1';
elsif input1(i) = '1' and input2(i) = '0' and carry = '0' then
temp(i) := '1';
carry := '0';
elsif input1(i) = '1' and input2(i) = '0' and carry = '1' then
temp(i) := '0';
carry := '1';
elsif input1(i) = '1' and input2(i) = '1' and carry = '0' then
temp(i) := '0';
carry := '1';
elsif input1(i) = '1' and input2(i) = '1' and carry = '1' then
temp(i) := '1';
carry := '1';
end if;
end loop;
temp(width) := carry;
carry := '0';
output <= temp;
if ((input1(width - 1) = '0') and (input2(width - 1) = '0') and (temp(width) = '1')) then
overflow := '1';
elsif ((input1(width - 1) = '1') and (input2(width - 1) = '1') and (temp(width) = '0')) then
overflow := '1';
elsif ((input1(width - 1) = '0') and (input2(width - 1) = '1') and (temp(width) = '1')) then
overflow := '1';
elsif ((input1(width - 1) = '1') and (input2(width - 1) = '0') and (temp(width) = '0')) then
overflow := '1';
end if;
end process;
end behavior;
|
mit
|
CyAScott/CIS4930.DatapathSynthesisTool
|
src/components/test_ram.vhd
|
1
|
1938
|
library IEEE;
use IEEE.std_logic_1164.all;
use Std.Textio.all;
use IEEE.std_logic_textio.all;
entity test_ram is
end test_ram;
architecture test_ram of test_ram is
component Ram
generic (width : INTEGER := 16;
ram_select : INTEGER := 4);
port (input1 : in std_logic_Vector((width - 1) downto 0);
input2 : in std_logic_Vector((ram_select - 1) downto 0);
Wr, Rd, CLOCK : in std_logic;
output : out std_logic_Vector(width - 1 downto 0)) ;
end component;
for all : Ram use entity WORK.Ram(behavior);
signal input1 : std_logic_Vector(3 downto 0);
signal input2 : std_logic_Vector(3 downto 0);
signal Wr, Rd, Clk : std_logic;
signal output : std_logic_Vector(3 downto 0);
begin
UUT : Ram
generic map(4,4)
port map(input1, input2, Wr, rd, Clk, output);
test_process : process
begin
Clk <= '1';
wr <= '1';
rd <= '0';
input1 <= "1111";
input2 <= "0000";
wait for 100 ns;
Clk <= '0';
wait for 100 ns;
Clk <= '1';
wr <= '1';
rd <= '0';
input1 <= "1110";
input2 <= "0001";
wait for 100 ns;
Clk <= '0';
wait for 100 ns;
Clk <= '1';
wr <= '1';
rd <= '0';
input1 <= "1101";
input2 <= "0010";
wait for 100 ns;
Clk <= '0';
wait for 100 ns;
Clk <= '1';
wr <= '0';
rd <= '1';
input2 <= "0000";
wait for 100 ns;
Clk <= '0';
wait for 100 ns;
Clk <= '1';
wr <= '0';
rd <= '1';
input2 <= "0001";
wait for 100 ns;
Clk <= '0';
wait for 100 ns;
Clk <= '1';
wr <= '0';
rd <= '1';
input2 <= "0010";
wait for 100 ns;
Clk <= '0';
wait for 100 ns;
wait;
end process;
monitor_process : process
variable outline : line;
file outfile : text is out "ram.out";
begin
write(outline, input1);
write(outline, string'(" : "));
write(outline, input2);
write(outline, string'(" : "));
write(outline, rd);
write(outline, string'(" : "));
write(outline, wr);
write(outline, string'(" : "));
write(outline, output);
writeline(outfile, outline);
wait until not rd'quiet;
end process;
end test_ram;
|
mit
|
CyAScott/CIS4930.DatapathSynthesisTool
|
src/components/test_register.vhd
|
1
|
1900
|
use Std.Textio.all;
library IEEE;
use ieee.std_logic_1164.ALL;
entity test_c_register is end;
architecture test_c_register of test_c_register is
component c_register
generic (width : INTEGER := 4);
port (input : in std_logic_vector((width - 1) downto 0);
WR: in std_logic;
clear : in std_logic;
clock : in std_logic;
output : out std_logic_vector((width -1) downto 0));
end component;
for all : c_register use entity work.c_register(behavior);
signal INPUT : std_logic_vector(3 downto 0);
signal CLEAR : std_logic ;
SIGNAL clock : std_logic;
signal OUTPUT : std_logic_vector(3 downto 0);
signal WR : std_logic;
begin
creg1 : c_register generic map(4)
port map( input, WR, clear, clock , output);
test_process : process
begin
----------- check clear ----------------
CLEAR <= '1';
WR <= '0' ;
clock <= '1';
input <= "1101";
wait for 10 ns;
clock <= '0';
wait for 10 ns;
CLEAR <= '0';
WR <= '1';
input <= "0111";
clock <= '1';
wait for 10 ns;
clock <= '0';
wait for 10 ns;
input <= "0101";
clock <= '1';
wait for 10 ns;
clock <= '0';
wait for 10 ns;
WR <= '0';
input <= "0011";
clock <= '1';
wait for 10 ns;
clock <= '0';
wait for 10 ns;
clock <= '1';
wait for 10 ns;
clock <= '0';
wait for 10 ns;
wait;
end process test_process ;
end test_c_register;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
|
mit
|
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