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justingallagher/fpga-trace
|
hls/triangle_intersect/tri_intersect/impl/vhdl/tri_intersect_fadd_32ns_32ns_32_9_full_dsp.vhd
|
4
|
3391
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.1
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity tri_intersect_fadd_32ns_32ns_32_9_full_dsp is
generic (
ID : integer := 15;
NUM_STAGE : integer := 9;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of tri_intersect_fadd_32ns_32ns_32_9_full_dsp is
--------------------- Component ---------------------
component tri_intersect_ap_fadd_7_full_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
tri_intersect_ap_fadd_7_full_dsp_32_u : component tri_intersect_ap_fadd_7_full_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
mit
|
justingallagher/fpga-trace
|
design/raytracer_design.srcs/sources_1/bd/triangle_intersect/hdl/triangle_intersect_wrapper.vhd
|
1
|
3551
|
--Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015
--Date : Sun May 08 18:17:54 2016
--Host : Win10Desktop running 64-bit major release (build 9200)
--Command : generate_target triangle_intersect_wrapper.bd
--Design : triangle_intersect_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity triangle_intersect_wrapper is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC
);
end triangle_intersect_wrapper;
architecture STRUCTURE of triangle_intersect_wrapper is
component triangle_intersect is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC
);
end component triangle_intersect;
begin
triangle_intersect_i: component triangle_intersect
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb
);
end STRUCTURE;
|
mit
|
justingallagher/fpga-trace
|
hls/triangle_intersect/tri_intersect/impl/ip/tmp.srcs/sources_1/ip/tri_intersect_ap_fdiv_28_no_dsp_32/xbip_dsp48_addsub_v3_0/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd
|
9
|
86039
|
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`protect end_protected
|
mit
|
justingallagher/fpga-trace
|
hls/triangle_intersect/tri_intersect/impl/ip/tmp.srcs/sources_1/ip/tri_intersect_ap_fmul_3_max_dsp_32/axi_utils_v2_0/hdl/axi_utils_v2_0_vh_rfs.vhd
|
9
|
291505
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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LUc7zZygoA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 214048)
`protect data_block
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3fG8B1EiBvxYq0wnug==
`protect end_protected
|
mit
|
justingallagher/fpga-trace
|
hls/triangle_intersect/tri_intersect/impl/vhdl/project.srcs/sources_1/ip/tri_intersect_ap_fdiv_28_no_dsp_32/axi_utils_v2_0/hdl/axi_utils_v2_0_vh_rfs.vhd
|
9
|
291505
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 214048)
`protect data_block
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`protect end_protected
|
mit
|
justingallagher/fpga-trace
|
design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/950a27d1/hdl/src/vhdl/axi_sg_updt_sm.vhd
|
5
|
41952
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_sm.vhd
-- Description: This entity manages updating of descriptors.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_sm is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_SG_CH1_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to fetch
C_SG_CH1_FIRST_UPDATE_WORD : integer range 0 to 15 := 0;
-- Starting update word offset
C_SG_CH2_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to fetch
C_SG_CH2_FIRST_UPDATE_WORD : integer range 0 to 15 := 0
-- Starting update word offset
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
ftch_error : in std_logic ; --
--
-- Channel 1 Control and Status --
ch1_updt_queue_empty : in std_logic ; --
ch1_updt_curdesc_wren : in std_logic ; --
ch1_updt_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_updt_ioc : in std_logic ; --
ch1_dma_interr : in std_logic ; --
ch1_dma_slverr : in std_logic ; --
ch1_dma_decerr : in std_logic ; --
ch1_updt_active : out std_logic ; --
ch1_updt_idle : out std_logic ; --
ch1_updt_interr_set : out std_logic ; --
ch1_updt_slverr_set : out std_logic ; --
ch1_updt_decerr_set : out std_logic ; --
ch1_dma_interr_set : out std_logic ; --
ch1_dma_slverr_set : out std_logic ; --
ch1_dma_decerr_set : out std_logic ; --
ch1_updt_ioc_irq_set : out std_logic ; --
ch1_updt_done : out std_logic ; --
--
-- Channel 2 Control and Status --
ch2_updt_queue_empty : in std_logic ; --
-- ch2_updt_curdesc_wren : in std_logic ; --
-- ch2_updt_curdesc : in std_logic_vector --
-- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_updt_ioc : in std_logic ; --
ch2_dma_interr : in std_logic ; --
ch2_dma_slverr : in std_logic ; --
ch2_dma_decerr : in std_logic ; --
ch2_updt_active : out std_logic ; --
ch2_updt_idle : out std_logic ; --
ch2_updt_interr_set : out std_logic ; --
ch2_updt_slverr_set : out std_logic ; --
ch2_updt_decerr_set : out std_logic ; --
ch2_dma_interr_set : out std_logic ; --
ch2_dma_slverr_set : out std_logic ; --
ch2_dma_decerr_set : out std_logic ; --
ch2_updt_ioc_irq_set : out std_logic ; --
ch2_updt_done : out std_logic ; --
--
-- DataMover Command --
updt_cmnd_wr : out std_logic ; --
updt_cmnd_data : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH --
+CMD_BASE_WIDTH)-1 downto 0) ; --
-- DataMover Status --
updt_done : in std_logic ; --
updt_error : in std_logic ; --
updt_interr : in std_logic ; --
updt_slverr : in std_logic ; --
updt_decerr : in std_logic ; --
updt_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) --
);
end axi_sg_updt_sm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
attribute mark_debug : string;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- DataMover Commmand TAG
constant UPDATE_CMD_TAG : std_logic_vector(3 downto 0) := (others => '0');
-- DataMover Command Type
-- Always set to INCR type
constant UPDATE_CMD_TYPE : std_logic := '1';
-- DataMover Cmnd Reserved Bits
constant UPDATE_MSB_IGNORED : std_logic_vector(7 downto 0) := (others => '0');
-- DataMover Cmnd Reserved Bits
constant UPDATE_LSB_IGNORED : std_logic_vector(15 downto 0) := (others => '0');
-- DataMover Cmnd Bytes to Xfer for Channel 1
constant UPDATE_CH1_CMD_BTT : std_logic_vector(SG_BTT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_SG_CH1_WORDS_TO_UPDATE*4),SG_BTT_WIDTH));
-- DataMover Cmnd Bytes to Xfer for Channel 2
constant UPDATE_CH2_CMD_BTT : std_logic_vector(SG_BTT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_SG_CH2_WORDS_TO_UPDATE*4),SG_BTT_WIDTH));
-- DataMover Cmnd Reserved Bits
constant UPDATE_CMD_RSVD : std_logic_vector(
DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_SG_ADDR_WIDTH downto
DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_SG_ADDR_WIDTH)
:= (others => '0');
-- DataMover Cmnd Address Offset for channel 1
constant UPDATE_CH1_ADDR_OFFSET : integer := C_SG_CH1_FIRST_UPDATE_WORD*4;
-- DataMover Cmnd Address Offset for channel 2
constant UPDATE_CH2_ADDR_OFFSET : integer := C_SG_CH2_FIRST_UPDATE_WORD*4;
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
type SG_UPDATE_STATE_TYPE is (
IDLE,
GET_UPDATE_PNTR,
UPDATE_DESCRIPTOR,
UPDATE_STATUS,
UPDATE_ERROR
);
signal updt_cs : SG_UPDATE_STATE_TYPE;
signal updt_ns : SG_UPDATE_STATE_TYPE;
-- State Machine Signals
signal ch1_active_set : std_logic := '0';
signal ch2_active_set : std_logic := '0';
signal write_cmnd_cmb : std_logic := '0';
signal ch1_updt_sm_idle : std_logic := '0';
signal ch2_updt_sm_idle : std_logic := '0';
-- Misc Signals
signal ch1_active_i : std_logic := '0';
signal service_ch1 : std_logic := '0';
signal ch2_active_i : std_logic := '0';
signal service_ch2 : std_logic := '0';
attribute mark_debug of ch1_active_i: signal is "true";
attribute mark_debug of ch2_active_i: signal is "true";
signal update_address : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal update_cmd_btt : std_logic_vector
(SG_BTT_WIDTH-1 downto 0) := (others => '0');
signal update_tag : std_logic_vector (3 downto 0);
signal updt_ioc_irq_set : std_logic := '0';
signal ch1_interr_catch : std_logic := '0';
signal ch2_interr_catch : std_logic := '0';
signal ch1_decerr_catch : std_logic := '0';
signal ch2_decerr_catch : std_logic := '0';
signal ch1_slverr_catch : std_logic := '0';
signal ch2_slverr_catch : std_logic := '0';
signal updt_cmnd_data_int : std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH --
+CMD_BASE_WIDTH)-1 downto 0) ; --
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ch1_updt_active <= ch1_active_i;
ch2_updt_active <= ch2_active_i;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch State Machine
-------------------------------------------------------------------------------
SG_UPDT_MACHINE : process(updt_cs,
ch1_active_i,
ch2_active_i,
service_ch1,
service_ch2,
ch1_updt_curdesc_wren,
-- ch2_updt_curdesc_wren,
updt_error,
updt_done)
begin
-- Default signal assignment
ch1_active_set <= '0';
ch2_active_set <= '0';
write_cmnd_cmb <= '0';
ch1_updt_sm_idle <= '0';
ch2_updt_sm_idle <= '0';
updt_ns <= updt_cs;
case updt_cs is
-------------------------------------------------------------------
when IDLE =>
ch1_updt_sm_idle <= not service_ch1;
ch2_updt_sm_idle <= not service_ch2;
-- error during update - therefore shut down
if(updt_error = '1')then
updt_ns <= UPDATE_ERROR;
-- If channel 1 is running and not idle and queue is not full
-- then fetch descriptor for channel 1
elsif(service_ch1 = '1')then
ch1_active_set <= '1';
updt_ns <= GET_UPDATE_PNTR;
-- If channel 2 is running and not idle and queue is not full
-- then fetch descriptor for channel 2
elsif(service_ch2 = '1')then
ch2_active_set <= '1';
updt_ns <= GET_UPDATE_PNTR;
else
updt_ns <= IDLE;
end if;
when GET_UPDATE_PNTR =>
if(ch1_updt_curdesc_wren = '1')then
updt_ns <= UPDATE_DESCRIPTOR;
else
updt_ns <= GET_UPDATE_PNTR;
end if;
-- if(ch1_updt_curdesc_wren = '1' or ch2_updt_curdesc_wren = '1')then
-- updt_ns <= UPDATE_DESCRIPTOR;
-- else
-- updt_ns <= GET_UPDATE_PNTR;
-- end if;
-------------------------------------------------------------------
when UPDATE_DESCRIPTOR =>
-- error during update - therefore shut down
if(updt_error = '1')then
-- coverage off
updt_ns <= UPDATE_ERROR;
-- coverage on
-- write command
else
ch1_updt_sm_idle <= not ch1_active_i and not service_ch1;
ch2_updt_sm_idle <= not ch2_active_i and not service_ch2;
write_cmnd_cmb <= '1';
updt_ns <= UPDATE_STATUS;
end if;
-------------------------------------------------------------------
when UPDATE_STATUS =>
ch1_updt_sm_idle <= not ch1_active_i and not service_ch1;
ch2_updt_sm_idle <= not ch2_active_i and not service_ch2;
-- error during update - therefore shut down
if(updt_error = '1')then
-- coverage off
updt_ns <= UPDATE_ERROR;
-- coverage on
-- wait until done with update
elsif(updt_done = '1')then
-- If just finished fethcing for channel 2 then...
if(ch2_active_i = '1')then
-- If ready, update descriptor for channel 1
if(service_ch1 = '1')then
ch1_active_set <= '1';
updt_ns <= GET_UPDATE_PNTR;
-- Otherwise return to IDLE
else
updt_ns <= IDLE;
end if;
-- If just finished fethcing for channel 1 then...
elsif(ch1_active_i = '1')then
-- If ready, update descriptor for channel 2
if(service_ch2 = '1')then
ch2_active_set <= '1';
updt_ns <= GET_UPDATE_PNTR;
-- Otherwise return to IDLE
else
updt_ns <= IDLE;
end if;
else
-- coverage off
updt_ns <= IDLE;
-- coverage on
end if;
else
updt_ns <= UPDATE_STATUS;
end if;
-------------------------------------------------------------------
when UPDATE_ERROR =>
ch1_updt_sm_idle <= '1';
ch2_updt_sm_idle <= '1';
updt_ns <= UPDATE_ERROR;
-------------------------------------------------------------------
-- coverage off
when others =>
updt_ns <= IDLE;
-- coverage on
end case;
end process SG_UPDT_MACHINE;
-------------------------------------------------------------------------------
-- Register states of state machine
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_cs <= IDLE;
else
updt_cs <= updt_ns;
end if;
end if;
end process REGISTER_STATE;
-------------------------------------------------------------------------------
-- Channel included therefore generate fetch logic
-------------------------------------------------------------------------------
GEN_CH1_UPDATE : if C_INCLUDE_CH1 = 1 generate
begin
-------------------------------------------------------------------------------
-- Active channel flag. Indicates which channel is active.
-- 0 = channel active
-- 1 = channel active
-------------------------------------------------------------------------------
CH1_ACTIVE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_active_i <= '0';
elsif(ch1_active_i = '1' and updt_done = '1')then
ch1_active_i <= '0';
elsif(ch1_active_set = '1')then
ch1_active_i <= '1';
end if;
end if;
end process CH1_ACTIVE_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 ready to be serviced?
-------------------------------------------------------------------------------
service_ch1 <= '1' when ch1_updt_queue_empty = '0' -- Queue not empty
and ftch_error = '0' -- No SG Fetch Error
else '0';
-------------------------------------------------------------------------------
-- Channel 1 Interrupt On Complete
-------------------------------------------------------------------------------
CH1_INTR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_ioc_irq_set <= '0';
-- Set interrupt on Done and Descriptor IOC set
elsif(updt_done = '1' and ch1_updt_ioc = '1')then
ch1_updt_ioc_irq_set <= '1';
else
ch1_updt_ioc_irq_set <= '0';
end if;
end if;
end process CH1_INTR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Internal Error
-------------------------------------------------------------------------------
CH1_INTERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_dma_interr_set <= '0';
-- Set internal error on desc updt Done and Internal Error
elsif(updt_done = '1' and ch1_dma_interr = '1')then
ch1_dma_interr_set <= '1';
end if;
end if;
end process CH1_INTERR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Slave Error
-------------------------------------------------------------------------------
CH1_SLVERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_dma_slverr_set <= '0';
-- Set slave error on desc updt Done and Slave Error
elsif(updt_done = '1' and ch1_dma_slverr = '1')then
ch1_dma_slverr_set <= '1';
end if;
end if;
end process CH1_SLVERR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Decode Error
-------------------------------------------------------------------------------
CH1_DECERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_dma_decerr_set <= '0';
-- Set decode error on desc updt Done and Decode Error
elsif(updt_done = '1' and ch1_dma_decerr = '1')then
ch1_dma_decerr_set <= '1';
end if;
end if;
end process CH1_DECERR_PROCESS;
-------------------------------------------------------------------------------
-- Log Fetch Errors
-------------------------------------------------------------------------------
-- Log Slave Errors reported during descriptor update
SLV_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_slverr_set <= '0';
elsif(ch1_active_i = '1' and updt_slverr = '1')then
ch1_updt_slverr_set <= '1';
end if;
end if;
end process SLV_SET_PROCESS;
-- Log Internal Errors reported during descriptor update
INT_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_interr_set <= '0';
elsif(ch1_active_i = '1' and updt_interr = '1')then
-- coverage off
ch1_updt_interr_set <= '1';
-- coverage on
end if;
end if;
end process INT_SET_PROCESS;
-- Log Decode Errors reported during descriptor update
DEC_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_decerr_set <= '0';
elsif(ch1_active_i = '1' and updt_decerr = '1')then
ch1_updt_decerr_set <= '1';
end if;
end if;
end process DEC_SET_PROCESS;
-- Indicate update is idle if state machine is idle and update queue is empty
IDLE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_error = '1' or ftch_error = '1')then
ch1_updt_idle <= '1';
elsif(service_ch1 = '1')then
ch1_updt_idle <= '0';
elsif(service_ch1 = '0' and ch1_updt_sm_idle = '1')then
ch1_updt_idle <= '1';
end if;
end if;
end process IDLE_PROCESS;
---------------------------------------------------------------------------
-- Indicate update is done to allow fetch of next descriptor
-- This is needed to prevent a partial descriptor being fetched
-- and then axi read is throttled for extended periods until the
-- remainder of the descriptor is fetched.
--
-- Note: Only used when fetch queue not inluded otherwise
-- tools optimize out this process
---------------------------------------------------------------------------
REG_CH1_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_done <= '0';
elsif(updt_done = '1' and ch1_active_i = '1')then
ch1_updt_done <= '1';
else
ch1_updt_done <= '0';
end if;
end if;
end process REG_CH1_DONE;
end generate GEN_CH1_UPDATE;
-------------------------------------------------------------------------------
-- Channel excluded therefore do not generate fetch logic
-------------------------------------------------------------------------------
GEN_NO_CH1_UPDATE : if C_INCLUDE_CH1 = 0 generate
begin
service_ch1 <= '0';
ch1_active_i <= '0';
ch1_updt_idle <= '0';
ch1_updt_interr_set <= '0';
ch1_updt_slverr_set <= '0';
ch1_updt_decerr_set <= '0';
ch1_dma_interr_set <= '0';
ch1_dma_slverr_set <= '0';
ch1_dma_decerr_set <= '0';
ch1_updt_ioc_irq_set <= '0';
ch1_updt_done <= '0';
end generate GEN_NO_CH1_UPDATE;
-------------------------------------------------------------------------------
-- Channel included therefore generate fetch logic
-------------------------------------------------------------------------------
GEN_CH2_UPDATE : if C_INCLUDE_CH2 = 1 generate
begin
-------------------------------------------------------------------------------
-- Active channel flag. Indicates which channel is active.
-- 0 = channel active
-- 1 = channel active
-------------------------------------------------------------------------------
CH2_ACTIVE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_active_i <= '0';
elsif(ch2_active_i = '1' and updt_done = '1')then
ch2_active_i <= '0';
elsif(ch2_active_set = '1')then
ch2_active_i <= '1';
end if;
end if;
end process CH2_ACTIVE_PROCESS;
-------------------------------------------------------------------------------
-- Channel 2 ready to be serviced?
-------------------------------------------------------------------------------
service_ch2 <= '1' when ch2_updt_queue_empty = '0' -- Queue not empty
and ftch_error = '0' -- No SG Fetch Error
else '0';
-------------------------------------------------------------------------------
-- Channel 2 Interrupt On Complete
-------------------------------------------------------------------------------
CH2_INTR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_ioc_irq_set <= '0';
-- Set interrupt on Done and Descriptor IOC set
elsif(updt_done = '1' and ch2_updt_ioc = '1')then
ch2_updt_ioc_irq_set <= '1';
else
ch2_updt_ioc_irq_set <= '0';
end if;
end if;
end process CH2_INTR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Internal Error
-------------------------------------------------------------------------------
CH2_INTERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_dma_interr_set <= '0';
-- Set internal error on desc updt Done and Internal Error
elsif(updt_done = '1' and ch2_dma_interr = '1')then
ch2_dma_interr_set <= '1';
end if;
end if;
end process CH2_INTERR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Slave Error
-------------------------------------------------------------------------------
CH2_SLVERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_dma_slverr_set <= '0';
-- Set slave error on desc updt Done and Slave Error
elsif(updt_done = '1' and ch2_dma_slverr = '1')then
ch2_dma_slverr_set <= '1';
end if;
end if;
end process CH2_SLVERR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Decode Error
-------------------------------------------------------------------------------
CH2_DECERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_dma_decerr_set <= '0';
-- Set decode error on desc updt Done and Decode Error
elsif(updt_done = '1' and ch2_dma_decerr = '1')then
ch2_dma_decerr_set <= '1';
end if;
end if;
end process CH2_DECERR_PROCESS;
-------------------------------------------------------------------------------
-- Log Fetch Errors
-------------------------------------------------------------------------------
-- Log Slave Errors reported during descriptor update
SLV_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_slverr_set <= '0';
elsif(ch2_active_i = '1' and updt_slverr = '1')then
ch2_updt_slverr_set <= '1';
end if;
end if;
end process SLV_SET_PROCESS;
-- Log Internal Errors reported during descriptor update
INT_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_interr_set <= '0';
elsif(ch2_active_i = '1' and updt_interr = '1')then
-- coverage off
ch2_updt_interr_set <= '1';
-- coverage on
end if;
end if;
end process INT_SET_PROCESS;
-- Log Decode Errors reported during descriptor update
DEC_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_decerr_set <= '0';
elsif(ch2_active_i = '1' and updt_decerr = '1')then
ch2_updt_decerr_set <= '1';
end if;
end if;
end process DEC_SET_PROCESS;
-- Indicate update is idle if state machine is idle and update queue is empty
IDLE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_error = '1' or ftch_error = '1')then
ch2_updt_idle <= '1';
elsif(service_ch2 = '1')then
ch2_updt_idle <= '0';
elsif(service_ch2 = '0' and ch2_updt_sm_idle = '1')then
ch2_updt_idle <= '1';
end if;
end if;
end process IDLE_PROCESS;
---------------------------------------------------------------------------
-- Indicate update is done to allow fetch of next descriptor
-- This is needed to prevent a partial descriptor being fetched
-- and then axi read is throttled for extended periods until the
-- remainder of the descriptor is fetched.
--
-- Note: Only used when fetch queue not inluded otherwise
-- tools optimize out this process
---------------------------------------------------------------------------
REG_CH2_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_done <= '0';
elsif(updt_done = '1' and ch2_active_i = '1')then
ch2_updt_done <= '1';
else
ch2_updt_done <= '0';
end if;
end if;
end process REG_CH2_DONE;
end generate GEN_CH2_UPDATE;
-------------------------------------------------------------------------------
-- Channel excluded therefore do not generate fetch logic
-------------------------------------------------------------------------------
GEN_NO_CH2_UPDATE : if C_INCLUDE_CH2 = 0 generate
begin
service_ch2 <= '0';
ch2_active_i <= '0';
ch2_updt_idle <= '0';
ch2_updt_interr_set <= '0';
ch2_updt_slverr_set <= '0';
ch2_updt_decerr_set <= '0';
ch2_dma_interr_set <= '0';
ch2_dma_slverr_set <= '0';
ch2_dma_decerr_set <= '0';
ch2_updt_ioc_irq_set <= '0';
ch2_updt_done <= '0';
end generate GEN_NO_CH2_UPDATE;
---------------------------------------------------------------------------
-- Register Current Update Address. Address captured from channel port
-- or queue by axi_sg_updt_queue
---------------------------------------------------------------------------
REG_UPDATE_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
update_address (C_M_AXI_SG_ADDR_WIDTH-1 downto 4) <= (others => '0');
-- update_tag <= "0000";
-- Channel 1 descriptor update pointer
elsif(ch1_updt_curdesc_wren = '1')then
update_address (C_M_AXI_SG_ADDR_WIDTH-1 downto 4) <= std_logic_vector(unsigned(ch1_updt_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto 4))
+ 1);
-- update_tag <= "0001";
-- -- Channel 2 descriptor update pointer
-- elsif(ch2_updt_curdesc_wren = '1')then
-- update_address (C_M_AXI_SG_ADDR_WIDTH-1 downto 4) <= std_logic_vector(unsigned(ch2_updt_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto 4))
-- + 1);
-- update_tag <= "0000";
end if;
end if;
end process REG_UPDATE_ADDRESS;
update_tag <= "0000" when ch2_active_i = '1' else
"0001";
--REG_UPDATE_ADDRESS : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- update_address (C_M_AXI_SG_ADDR_WIDTH-1 downto 4) <= (others => '0');
-- update_tag <= "0000";
-- -- Channel 1 descriptor update pointer
-- elsif(ch1_updt_curdesc_wren = '1')then
-- update_address (C_M_AXI_SG_ADDR_WIDTH-1 downto 4) <= std_logic_vector(unsigned(ch1_updt_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto 4))
-- + 1);
-- update_tag <= "0001";
-- -- Channel 2 descriptor update pointer
-- elsif(ch2_updt_curdesc_wren = '1')then
-- update_address (C_M_AXI_SG_ADDR_WIDTH-1 downto 4) <= std_logic_vector(unsigned(ch2_updt_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto 4))
-- + 1);
-- update_tag <= "0000";
-- end if;
-- end if;
-- end process REG_UPDATE_ADDRESS;
update_address (3 downto 0) <= "1100";
-- Assigne Bytes to Transfer (BTT)
update_cmd_btt <= UPDATE_CH1_CMD_BTT when ch1_active_i = '1'
else UPDATE_CH2_CMD_BTT;
updt_cmnd_data <= updt_cmnd_data_int;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- When command by sm, drive command to updt_cmdsts_if
--GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- updt_cmnd_wr <= '0';
-- updt_cmnd_data_int <= (others => '0');
-- -- Fetch SM issued a command write
-- elsif(write_cmnd_cmb = '1')then
updt_cmnd_wr <= write_cmnd_cmb; --'1';
updt_cmnd_data_int <= UPDATE_CMD_RSVD
& update_tag --UPDATE_CMD_TAG
& update_address
& UPDATE_MSB_IGNORED
& UPDATE_CMD_TYPE
& UPDATE_LSB_IGNORED
& update_cmd_btt;
-- else
-- updt_cmnd_wr <= '0';
-- end if;
-- end if;
-- end process GEN_DATAMOVER_CMND;
-------------------------------------------------------------------------------
-- Capture and hold fetch address in case an error occurs
-------------------------------------------------------------------------------
LOG_ERROR_ADDR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_error_addr (C_M_AXI_SG_ADDR_WIDTH-1 downto SG_ADDR_LSB) <= (others => '0');
elsif(write_cmnd_cmb = '1')then
updt_error_addr (C_M_AXI_SG_ADDR_WIDTH-1 downto SG_ADDR_LSB) <= update_address(C_M_AXI_SG_ADDR_WIDTH-1 downto SG_ADDR_LSB);
end if;
end if;
end process LOG_ERROR_ADDR;
updt_error_addr (5 downto 0) <= "000000";
end implementation;
|
mit
|
justingallagher/fpga-trace
|
hls/triangle_intersect/tri_intersect/impl/vhdl/project.srcs/sources_1/ip/tri_intersect_ap_fadd_7_full_dsp_32/synth/tri_intersect_ap_fadd_7_full_dsp_32.vhd
|
1
|
12685
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_0;
USE floating_point_v7_0.floating_point_v7_0;
ENTITY tri_intersect_ap_fadd_7_full_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END tri_intersect_ap_fadd_7_full_dsp_32;
ARCHITECTURE tri_intersect_ap_fadd_7_full_dsp_32_arch OF tri_intersect_ap_fadd_7_full_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tri_intersect_ap_fadd_7_full_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_0 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF tri_intersect_ap_fadd_7_full_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_0,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF tri_intersect_ap_fadd_7_full_dsp_32_arch : ARCHITECTURE IS "tri_intersect_ap_fadd_7_full_dsp_32,floating_point_v7_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF tri_intersect_ap_fadd_7_full_dsp_32_arch: ARCHITECTURE IS "tri_intersect_ap_fadd_7_full_dsp_32,floating_point_v7_0,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.0,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=1,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=7,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_0
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 1,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 7,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END tri_intersect_ap_fadd_7_full_dsp_32_arch;
|
mit
|
justingallagher/fpga-trace
|
hls/triangle_intersect/tri_intersect/impl/ip/tmp.srcs/sources_1/ip/tri_intersect_ap_fadd_7_full_dsp_32/xbip_bram18k_v3_0/hdl/xbip_bram18k_v3_0.vhd
|
13
|
8791
|
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`protect end_protected
|
mit
|
justingallagher/fpga-trace
|
hls/triangle_intersect/tri_intersect/impl/ip/tmp.srcs/sources_1/ip/tri_intersect_ap_fmul_3_max_dsp_32/xbip_bram18k_v3_0/hdl/xbip_bram18k_v3_0.vhd
|
13
|
8791
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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GZc9q/N3Ew==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4768)
`protect data_block
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`protect end_protected
|
mit
|
justingallagher/fpga-trace
|
design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/950a27d1/hdl/src/vhdl/axi_sg_intrpt.vhd
|
4
|
28207
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_intrpt.vhd
-- Description: This entity handles interrupt coalescing
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.clog2;
use lib_pkg_v1_0.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg_intrpt is
generic(
C_INCLUDE_CH1 : integer range 0 to 1 := 1 ;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_INCLUDE_CH2 : integer range 0 to 1 := 1 ;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_INCLUDE_DLYTMR : integer range 0 to 1 := 1 ;
-- Include/Exclude interrupt delay timer
-- 0 = Exclude Delay timer
-- 1 = Include Delay timer
C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125
-- Interrupt Delay Timer resolution in usec
);
port (
-- Secondary Clock and Reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
ch1_irqthresh_decr : in std_logic ;-- CR567661 --
ch1_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch1_dlyirq_dsble : in std_logic ; --
ch1_irqdelay_wren : in std_logic ; --
ch1_irqdelay : in std_logic_vector(7 downto 0) ; --
ch1_irqthresh_wren : in std_logic ; --
ch1_irqthresh : in std_logic_vector(7 downto 0) ; --
ch1_packet_sof : in std_logic ; --
ch1_packet_eof : in std_logic ; --
ch1_ioc_irq_set : out std_logic ; --
ch1_dly_irq_set : out std_logic ; --
ch1_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch1_irqthresh_status : out std_logic_vector(7 downto 0) ; --
--
ch2_irqthresh_decr : in std_logic ;-- CR567661 --
ch2_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch2_dlyirq_dsble : in std_logic ; --
ch2_irqdelay_wren : in std_logic ; --
ch2_irqdelay : in std_logic_vector(7 downto 0) ; --
ch2_irqthresh_wren : in std_logic ; --
ch2_irqthresh : in std_logic_vector(7 downto 0) ; --
ch2_packet_sof : in std_logic ; --
ch2_packet_eof : in std_logic ; --
ch2_ioc_irq_set : out std_logic ; --
ch2_dly_irq_set : out std_logic ; --
ch2_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch2_irqthresh_status : out std_logic_vector(7 downto 0) --
);
end axi_sg_intrpt;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_intrpt is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Delay interrupt fast counter width
constant FAST_COUNT_WIDTH : integer := clog2(C_DLYTMR_RESOLUTION+1);
-- Delay interrupt fast counter terminal count
constant FAST_COUNT_TC : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_DLYTMR_RESOLUTION-1),FAST_COUNT_WIDTH));
-- Delay interrupt fast counter zero value
constant ZERO_FAST_COUNT : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0)
:= (others => '0');
constant ZERO_VALUE : std_logic_vector(7 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ch1_thresh_count : std_logic_vector(7 downto 0) := ONE_THRESHOLD;
signal ch1_dly_irq_set_i : std_logic := '0';
signal ch1_ioc_irq_set_i : std_logic := '0';
signal ch1_delay_count : std_logic_vector(7 downto 0) := (others => '0');
signal ch1_delay_cnt_en : std_logic := '0';
signal ch1_dly_fast_cnt : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0) := (others => '0');
signal ch1_dly_fast_incr : std_logic := '0';
signal ch1_delay_zero : std_logic := '0';
signal ch1_delay_tc : std_logic := '0';
signal ch1_disable_delay : std_logic := '0';
signal ch2_thresh_count : std_logic_vector(7 downto 0) := ONE_THRESHOLD;
signal ch2_dly_irq_set_i : std_logic := '0';
signal ch2_ioc_irq_set_i : std_logic := '0';
signal ch2_delay_count : std_logic_vector(7 downto 0) := (others => '0');
signal ch2_delay_cnt_en : std_logic := '0';
signal ch2_dly_fast_cnt : std_logic_vector(FAST_COUNT_WIDTH-1 downto 0) := (others => '0');
signal ch2_dly_fast_incr : std_logic := '0';
signal ch2_delay_zero : std_logic := '0';
signal ch2_delay_tc : std_logic := '0';
signal ch2_disable_delay : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Transmit channel included therefore generate transmit interrupt logic
GEN_INCLUDE_MM2S : if C_INCLUDE_CH1 = 1 generate
begin
REG_THRESH_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_thresh_count <= ONE_THRESHOLD;
ch1_ioc_irq_set_i <= '0';
-- New Threshold set by CPU OR delay interrupt event occured.
-- CR572013 - added ability to disable threshold count reset on delay timeout
-- elsif(ch1_irqthresh_wren = '1' or ch1_dly_irq_set_i = '1') then
elsif( (ch1_irqthresh_wren = '1')
or (ch1_dly_irq_set_i = '1' and ch1_irqthresh_rstdsbl = '0')) then
ch1_thresh_count <= ch1_irqthresh;
ch1_ioc_irq_set_i <= '0';
-- IOC event then...
elsif(ch1_irqthresh_decr = '1')then --CR567661
-- Threshold at zero, reload threshold and drive ioc
-- interrupt.
if(ch1_thresh_count = ONE_THRESHOLD)then
ch1_thresh_count <= ch1_irqthresh;
ch1_ioc_irq_set_i <= '1';
else
ch1_thresh_count <= std_logic_vector(unsigned(ch1_thresh_count(7 downto 0)) - 1);
ch1_ioc_irq_set_i <= '0';
end if;
else
ch1_thresh_count <= ch1_thresh_count;
ch1_ioc_irq_set_i <= '0';
end if;
end if;
end process REG_THRESH_COUNT;
-- Pass current threshold count out to DMASR
ch1_irqthresh_status <= ch1_thresh_count;
ch1_ioc_irq_set <= ch1_ioc_irq_set_i;
---------------------------------------------------------------------------
-- Generate Delay Interrupt Timers
---------------------------------------------------------------------------
GEN_CH1_DELAY_INTERRUPT : if C_INCLUDE_DLYTMR = 1 generate
begin
GEN_CH1_FAST_COUNTER : if C_DLYTMR_RESOLUTION /= 1 generate
begin
---------------------------------------------------------------------------
-- Delay interrupt high resolution timer
---------------------------------------------------------------------------
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_dly_fast_cnt <= FAST_COUNT_TC;
ch1_dly_fast_incr <= '0';
elsif(ch1_dly_fast_cnt = ZERO_FAST_COUNT)then
ch1_dly_fast_cnt <= FAST_COUNT_TC;
ch1_dly_fast_incr <= '1';
else
ch1_dly_fast_cnt <= std_logic_vector(unsigned(ch1_dly_fast_cnt(FAST_COUNT_WIDTH-1 downto 0)) - 1);
ch1_dly_fast_incr <= '0';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH1_FAST_COUNTER;
GEN_CH1_NO_FAST_COUNTER : if C_DLYTMR_RESOLUTION = 1 generate
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_dly_fast_incr <= '0';
else
ch1_dly_fast_incr <= '1';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH1_NO_FAST_COUNTER;
-- DMACR Delay value set to zero - disable delay interrupt
ch1_delay_zero <= '1' when ch1_irqdelay = ZERO_DELAY
else '0';
-- Delay Terminal Count reached (i.e. Delay count = DMACR delay value)
ch1_delay_tc <= '1' when ch1_delay_count = ch1_irqdelay
and ch1_delay_zero = '0'
and ch1_packet_sof = '0'
else '0';
-- 1 clock earlier delay counter disable to prevent count
-- increment on TC hit.
ch1_disable_delay <= '1' when ch1_delay_zero = '1'
or ch1_dlyirq_dsble = '1'
or ch1_dly_irq_set_i = '1'
else '0';
---------------------------------------------------------------------------
-- Delay interrupt low resolution timer
---------------------------------------------------------------------------
REG_DELAY_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 need to reset on SOF now due to CR change
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1' or ch1_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch1_delay_cnt_en = '0' or ch1_disable_delay = '1'
or ch1_packet_sof = '1' or ch1_irqdelay_wren = '1')then
ch1_delay_count <= (others => '0');
ch1_dly_irq_set_i <= '0';
elsif(ch1_dly_fast_incr = '1' and ch1_delay_tc = '1')then
ch1_delay_count <= (others => '0');
ch1_dly_irq_set_i <= '1';
elsif(ch1_dly_fast_incr = '1')then
ch1_delay_count <= std_logic_vector(unsigned(ch1_delay_count(7 downto 0)) + 1);
ch1_dly_irq_set_i <= '0';
else
ch1_delay_count <= ch1_delay_count;
ch1_dly_irq_set_i <= '0';
end if;
end if;
end process REG_DELAY_COUNT;
-- Pass current delay count to DMASR
ch1_irqdelay_status <= ch1_delay_count;
ch1_dly_irq_set <= ch1_dly_irq_set_i;
-- Enable control for delay counter
REG_DELAY_CNT_ENABLE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch1_disable_delay = '1')then
ch1_delay_cnt_en <= '0';
-- CR565366 simulatenous sof/eof which occurs for small packets causes delay timer
-- to not enable
-- elsif(ch1_packet_sof = '1')then
-- stop counting if already counting and receive an sof and
-- not end of another packet
elsif(ch1_delay_cnt_en = '1' and ch1_packet_sof = '1'
and ch1_packet_eof = '0')then
ch1_delay_cnt_en <= '0';
elsif(ch1_packet_eof = '1')then
ch1_delay_cnt_en <= '1';
end if;
end if;
end process REG_DELAY_CNT_ENABLE;
end generate GEN_CH1_DELAY_INTERRUPT;
---------------------------------------------------------------------------
-- Delay interrupt NOT included
---------------------------------------------------------------------------
GEN_NO_CH1_DELAY_INTR : if C_INCLUDE_DLYTMR = 0 generate
begin
ch1_dly_irq_set <= '0';
ch1_dly_irq_set_i <= '0';
ch1_irqdelay_status <= (others => '0');
end generate GEN_NO_CH1_DELAY_INTR;
end generate GEN_INCLUDE_MM2S;
-- Receive channel included therefore generate receive interrupt logic
GEN_INCLUDE_S2MM : if C_INCLUDE_CH2 = 1 generate
begin
REG_THRESH_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_thresh_count <= ONE_THRESHOLD;
ch2_ioc_irq_set_i <= '0';
-- New Threshold set by CPU OR delay interrupt event occured.
-- CR572013 - added ability to disable threshold count reset on delay timeout
-- elsif(ch2_irqthresh_wren = '1' or ch2_dly_irq_set_i = '1') then
elsif( (ch2_irqthresh_wren = '1')
or (ch2_dly_irq_set_i = '1' and ch2_irqthresh_rstdsbl = '0')) then
ch2_thresh_count <= ch2_irqthresh;
ch2_ioc_irq_set_i <= '0';
-- IOC event then...
elsif(ch2_irqthresh_decr = '1')then --CR567661
-- Threshold at zero, reload threshold and drive ioc
-- interrupt.
if(ch2_thresh_count = ONE_THRESHOLD)then
ch2_thresh_count <= ch2_irqthresh;
ch2_ioc_irq_set_i <= '1';
else
ch2_thresh_count <= std_logic_vector(unsigned(ch2_thresh_count(7 downto 0)) - 1);
ch2_ioc_irq_set_i <= '0';
end if;
else
ch2_thresh_count <= ch2_thresh_count;
ch2_ioc_irq_set_i <= '0';
end if;
end if;
end process REG_THRESH_COUNT;
-- Pass current threshold count out to DMASR
ch2_irqthresh_status <= ch2_thresh_count;
ch2_ioc_irq_set <= ch2_ioc_irq_set_i;
---------------------------------------------------------------------------
-- Generate Delay Interrupt Timers
---------------------------------------------------------------------------
GEN_CH2_DELAY_INTERRUPT : if C_INCLUDE_DLYTMR = 1 generate
begin
---------------------------------------------------------------------------
-- Delay interrupt high resolution timer
---------------------------------------------------------------------------
GEN_CH2_FAST_COUNTER : if C_DLYTMR_RESOLUTION /= 1 generate
begin
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_dly_fast_cnt <= FAST_COUNT_TC;
ch2_dly_fast_incr <= '0';
elsif(ch2_dly_fast_cnt = ZERO_FAST_COUNT)then
ch2_dly_fast_cnt <= FAST_COUNT_TC;
ch2_dly_fast_incr <= '1';
else
ch2_dly_fast_cnt <= std_logic_vector(unsigned(ch2_dly_fast_cnt(FAST_COUNT_WIDTH-1 downto 0)) - 1);
ch2_dly_fast_incr <= '0';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH2_FAST_COUNTER;
GEN_CH2_NO_FAST_COUNTER : if C_DLYTMR_RESOLUTION = 1 generate
REG_DLY_FAST_CNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 - need to reset on sof due to chanes for CR
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_dly_fast_incr <= '0';
else
ch2_dly_fast_incr <= '1';
end if;
end if;
end process REG_DLY_FAST_CNT;
end generate GEN_CH2_NO_FAST_COUNTER;
-- DMACR Delay value set to zero - disable delay interrupt
ch2_delay_zero <= '1' when ch2_irqdelay = ZERO_DELAY
else '0';
-- Delay Terminal Count reached (i.e. Delay count = DMACR delay value)
ch2_delay_tc <= '1' when ch2_delay_count = ch2_irqdelay
and ch2_delay_zero = '0'
and ch2_packet_sof = '0'
else '0';
-- 1 clock earlier delay counter disable to prevent count
-- increment on TC hit.
ch2_disable_delay <= '1' when ch2_delay_zero = '1'
or ch2_dlyirq_dsble = '1'
or ch2_dly_irq_set_i = '1'
else '0';
---------------------------------------------------------------------------
-- Delay interrupt low resolution timer
---------------------------------------------------------------------------
REG_DELAY_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- CR565366 need to reset on SOF now due to CR change
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1')then
-- CR570398 - need to reset delay timer each time a new delay value is written.
-- if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1' or ch2_packet_sof = '1')then
if(m_axi_sg_aresetn = '0' or ch2_delay_cnt_en = '0' or ch2_disable_delay = '1'
or ch2_packet_sof = '1' or ch2_irqdelay_wren = '1')then
ch2_delay_count <= (others => '0');
ch2_dly_irq_set_i <= '0';
elsif(ch2_dly_fast_incr = '1' and ch2_delay_tc = '1')then
ch2_delay_count <= (others => '0');
ch2_dly_irq_set_i <= '1';
elsif(ch2_dly_fast_incr = '1')then
ch2_delay_count <= std_logic_vector(unsigned(ch2_delay_count(7 downto 0)) + 1);
ch2_dly_irq_set_i <= '0';
else
ch2_delay_count <= ch2_delay_count;
ch2_dly_irq_set_i <= '0';
end if;
end if;
end process REG_DELAY_COUNT;
-- Pass current delay count to DMASR
ch2_irqdelay_status <= ch2_delay_count;
ch2_dly_irq_set <= ch2_dly_irq_set_i;
-- Enable control for delay counter
REG_DELAY_CNT_ENABLE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_disable_delay = '1')then
ch2_delay_cnt_en <= '0';
-- CR565366 simulatenous sof/eof which occurs for small packets causes delay timer
-- to not enable
-- elsif(ch2_packet_sof = '1')then
-- stop counting if already counting and receive an sof and
-- not end of another packet
elsif(ch2_delay_cnt_en = '1' and ch2_packet_sof = '1'
and ch2_packet_eof = '0')then
ch2_delay_cnt_en <= '0';
elsif(ch2_packet_eof = '1')then
ch2_delay_cnt_en <= '1';
end if;
end if;
end process REG_DELAY_CNT_ENABLE;
end generate GEN_CH2_DELAY_INTERRUPT;
---------------------------------------------------------------------------
-- Delay interrupt NOT included
---------------------------------------------------------------------------
GEN_NO_CH2_DELAY_INTR : if C_INCLUDE_DLYTMR = 0 generate
begin
ch2_dly_irq_set <= '0';
ch2_dly_irq_set_i <= '0';
ch2_irqdelay_status <= (others => '0');
end generate GEN_NO_CH2_DELAY_INTR;
end generate GEN_INCLUDE_S2MM;
-- Transmit channel not included therefore associated outputs to zero
GEN_EXCLUDE_MM2S : if C_INCLUDE_CH1 = 0 generate
begin
ch1_ioc_irq_set <= '0';
ch1_dly_irq_set <= '0';
ch1_irqdelay_status <= (others => '0');
ch1_irqthresh_status <= (others => '0');
end generate GEN_EXCLUDE_MM2S;
-- Receive channel not included therefore associated outputs to zero
GEN_EXCLUDE_S2MM : if C_INCLUDE_CH2 = 0 generate
begin
ch2_ioc_irq_set <= '0';
ch2_dly_irq_set <= '0';
ch2_irqdelay_status <= (others => '0');
ch2_irqthresh_status <= (others => '0');
end generate GEN_EXCLUDE_S2MM;
end implementation;
|
mit
|
justingallagher/fpga-trace
|
design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/f4229bb6/hdl/src/vhdl/axi_datamover_indet_btt.vhd
|
6
|
60696
|
-------------------------------------------------------------------------------
-- axi_datamover_indet_btt.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_indet_btt.vhd
--
-- Description:
-- This file implements the DataMover S2MM Indeterminate BTT support module.
-- This Module keeps track of the incoming data stream and generates a transfer
-- descriptor for each AXI MMap Burst worth of data loaded in the Data FIFO.
-- This information is stored in a separate FIFO that the Predictive Transfer
-- Calculator fetches sequentially as it is generating commands for the AXI MMap
-- bus.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library lib_pkg_v1_0;
Use lib_pkg_v1_0.lib_pkg.clog2;
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_sfifo_autord;
use axi_datamover_v5_1.axi_datamover_skid_buf;
Use axi_datamover_v5_1.axi_datamover_stbs_set;
Use axi_datamover_v5_1.axi_datamover_stbs_set_nodre;
-------------------------------------------------------------------------------
entity axi_datamover_indet_btt is
generic (
C_SF_FIFO_DEPTH : integer range 128 to 8192 := 128;
-- Sets the depth of the Data FIFO
C_IBTT_XFER_BYTES_WIDTH : Integer range 1 to 14 := 8;
-- Sets the width of the sf2pcc_xfer_bytes port
C_STRT_OFFSET_WIDTH : Integer range 1 to 7 := 2;
-- Sets the bit width of the starting address offset port
-- This should be set to log2(C_MMAP_DWIDTH/C_STREAM_DWIDTH)
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates what is set as the allowed max burst length for AXI4
-- transfers
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the width of the AXI4 MMap data path
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Indicates the width of the stream data path
C_ENABLE_SKID_BUF : string := "11111";
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_DRE : Integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA Family
);
port (
-- Clock input --------------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
-----------------------------------------------------------
-- Write Data Controller I/O ----------------------------------------------------------
--
ibtt2wdc_stbs_asserted : Out std_logic_vector(7 downto 0); --
-- Indicates the number of asserted WSTRB bits for the --
-- associated output stream data beat --
--
ibtt2wdc_eop : Out std_logic; --
-- Write End of Packet flag output to Write Data Controller --
--
ibtt2wdc_tdata : Out std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- Write DATA output to Write Data Controller --
--
ibtt2wdc_tstrb : Out std_logic_vector((C_MMAP_DWIDTH/8)-1 downto 0); --
-- Write DATA output to Write Data Controller --
--
ibtt2wdc_tlast : Out std_logic; --
-- Write LAST output to Write Data Controller --
--
ibtt2wdc_tvalid : Out std_logic; --
-- Write VALID output to Write Data Controller --
--
wdc2ibtt_tready : In std_logic; --
-- Write READY input from Write Data Controller --
---------------------------------------------------------------------------------------
-- DRE Stream In ----------------------------------------------------------------------
--
dre2ibtt_tvalid : In std_logic; --
-- DRE Stream VALID Output --
--
ibtt2dre_tready : Out Std_logic; --
-- DRE Stream READY input --
--
dre2ibtt_tdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- DRE Stream DATA input --
--
dre2ibtt_tstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- DRE Stream STRB input --
--
dre2ibtt_tlast : In std_logic; --
-- DRE Xfer LAST input --
--
dre2ibtt_eop : In std_logic; --
-- DRE Stream end of Stream packet flag --
--------------------------------------------------------------------------------------
-- Starting Address Offset Input -------------------------------------------------
--
dre2ibtt_strt_addr_offset : In std_logic_vector(C_STRT_OFFSET_WIDTH-1 downto 0); --
-- Used by Packing logic to set the initial data slice position for the --
-- packing operation. Packing is only needed if the MMap and Stream Data --
-- widths do not match. This input is sampled on the first valid DRE Stream In --
-- input databeat of a packet. --
-- --
-----------------------------------------------------------------------------------
-- Store and Forward Command Calculator Interface ---------------------------------------
--
sf2pcc_xfer_valid : Out std_logic; --
-- Indicates that at least 1 xfer descriptor entry is in in the XFER_DESCR_FIFO --
--
pcc2sf_xfer_ready : in std_logic; --
-- Indicates that a full burst of data has been loaded into the data FIFO --
--
--
sf2pcc_cmd_cmplt : Out std_logic; --
-- Indicates that this is the final xfer for an associated command loaded --
-- into the Realigner by the IBTTCC interface --
--
--
sf2pcc_packet_eop : Out std_logic; --
-- Indicates the end of a Stream Packet corresponds to the pending --
-- xfer data described by this xfer descriptor --
--
sf2pcc_xfer_bytes : Out std_logic_vector(C_IBTT_XFER_BYTES_WIDTH-1 downto 0) --
-- This byte count is used by the IBTTCC for setting up the spawned child --
-- commands. The IBTTCC must use this count to generate the appropriate --
-- LEN value to put out on the AXI4 Write Addr Channel and the WSTRB on the AXI4 --
-- Write Data Channel. --
-----------------------------------------------------------------------------------------
);
end entity axi_datamover_indet_btt;
architecture implementation of axi_datamover_indet_btt is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Functions
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_cntr_width
--
-- Function Description:
-- This function calculates the needed counter bit width from the
-- number of count sates needed (input).
--
-------------------------------------------------------------------
function funct_get_cntr_width (num_cnt_values : integer) return integer is
Variable temp_cnt_width : Integer := 0;
begin
if (num_cnt_values <= 2) then
temp_cnt_width := 1;
elsif (num_cnt_values <= 4) then
temp_cnt_width := 2;
elsif (num_cnt_values <= 8) then
temp_cnt_width := 3;
elsif (num_cnt_values <= 16) then
temp_cnt_width := 4;
elsif (num_cnt_values <= 32) then
temp_cnt_width := 5;
elsif (num_cnt_values <= 64) then
temp_cnt_width := 6;
elsif (num_cnt_values <= 128) then
temp_cnt_width := 7;
else
temp_cnt_width := 8;
end if;
Return (temp_cnt_width);
end function funct_get_cntr_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_rnd2pwr_of_2
--
-- Function Description:
-- Rounds the input value up to the nearest power of 2 between
-- 4 and 32. THis is used for sizing the SRL based XD FIFO.
--
-------------------------------------------------------------------
function funct_rnd2pwr_of_2 (input_value : integer) return integer is
Variable temp_pwr2 : Integer := 128;
begin
if (input_value <= 4) then
temp_pwr2 := 4;
elsif (input_value <= 8) then
temp_pwr2 := 8;
elsif (input_value <= 16) then
temp_pwr2 := 16;
else
temp_pwr2 := 32;
end if;
Return (temp_pwr2);
end function funct_rnd2pwr_of_2;
-------------------------------------------------------------------
-- Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BITS_PER_BYTE : integer := 8;
Constant MMAP2STRM_WIDTH_RATO : integer := C_MMAP_DWIDTH/C_STREAM_DWIDTH;
Constant STRM_WSTB_WIDTH : integer := C_STREAM_DWIDTH/BITS_PER_BYTE;
Constant MMAP_WSTB_WIDTH : integer := C_MMAP_DWIDTH/BITS_PER_BYTE;
Constant STRM_STRBS_ASSERTED_WIDTH : integer := clog2(STRM_WSTB_WIDTH)+1;
-- Constant DATA_FIFO_DFACTOR : integer := 4; -- set buffer to 4 times the Max allowed Burst Length
-- Constant DATA_FIFO_DEPTH : integer := C_MAX_BURST_LEN*DATA_FIFO_DFACTOR;
Constant DATA_FIFO_DEPTH : integer := C_SF_FIFO_DEPTH;
Constant DATA_FIFO_WIDTH : integer := C_MMAP_DWIDTH+MMAP_WSTB_WIDTH*C_ENABLE_S2MM_TKEEP+2;
-- Constant DATA_FIFO_WIDTH : integer := C_MMAP_DWIDTH+STRB_CNTR_WIDTH+2;
Constant DATA_FIFO_CNT_WIDTH : integer := clog2(DATA_FIFO_DEPTH)+1;
Constant BURST_CNTR_WIDTH : integer := clog2(C_MAX_BURST_LEN);
Constant MAX_BURST_DBEATS : Unsigned(BURST_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(C_MAX_BURST_LEN-1, BURST_CNTR_WIDTH);
Constant DBC_ONE : Unsigned(BURST_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, BURST_CNTR_WIDTH);
Constant BYTE_CNTR_WIDTH : integer := C_IBTT_XFER_BYTES_WIDTH;
Constant BYTES_PER_MMAP_DBEAT : integer := C_MMAP_DWIDTH/BITS_PER_BYTE;
Constant BYTES_PER_STRM_DBEAT : integer := C_STREAM_DWIDTH/BITS_PER_BYTE;
--Constant MAX_BYTE_CNT : integer := C_MAX_BURST_LEN*BYTES_PER_DBEAT;
--Constant NUM_STRB_BITS : integer := BYTES_PER_DBEAT;
Constant BCNTR_ONE : Unsigned(BYTE_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, BYTE_CNTR_WIDTH);
--Constant XD_FIFO_DEPTH : integer := 16;
Constant XD_FIFO_DEPTH : integer := funct_rnd2pwr_of_2(DATA_FIFO_DEPTH/C_MAX_BURST_LEN);
Constant XD_FIFO_CNT_WIDTH : integer := clog2(XD_FIFO_DEPTH)+1;
Constant XD_FIFO_WIDTH : integer := BYTE_CNTR_WIDTH+2;
Constant MMAP_STBS_ASSERTED_WIDTH : integer := 8;
Constant SKIDBUF2WDC_DWIDTH : integer := C_MMAP_DWIDTH + MMAP_STBS_ASSERTED_WIDTH;
Constant SKIDBUF2WDC_STRB_WIDTH : integer := SKIDBUF2WDC_DWIDTH/BITS_PER_BYTE;
--Constant NUM_ZEROS_WIDTH : integer := MMAP_STBS_ASSERTED_WIDTH;
Constant STRB_CNTR_WIDTH : integer := MMAP_STBS_ASSERTED_WIDTH;
-- Signals
signal sig_wdc2ibtt_tready : std_logic := '0';
signal sig_ibtt2wdc_tvalid : std_logic := '0';
signal sig_ibtt2wdc_tdata : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_tstrb : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_tlast : std_logic := '0';
signal sig_ibtt2wdc_eop : std_logic := '0';
signal sig_push_data_fifo : std_logic := '0';
signal sig_pop_data_fifo : std_logic := '0';
signal sig_data_fifo_data_in : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_data_out : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_dvalid : std_logic := '0';
signal sig_data_fifo_full : std_logic := '0';
signal sig_data_fifo_rd_cnt : std_logic_vector(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_wr_cnt : std_logic_vector(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_push_xd_fifo : std_logic := '0';
signal sig_pop_xd_fifo : std_logic := '0';
signal sig_xd_fifo_data_in : std_logic_vector(XD_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_xd_fifo_data_out : std_logic_vector(XD_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_xd_fifo_dvalid : std_logic := '0';
signal sig_xd_fifo_full : std_logic := '0';
signal sig_tmp : std_logic := '0';
signal sig_strm_in_ready : std_logic := '0';
signal sig_good_strm_dbeat : std_logic := '0';
signal sig_good_tlast_dbeat : std_logic := '0';
signal sig_dre2ibtt_tlast_reg : std_logic := '0';
signal sig_dre2ibtt_eop_reg : std_logic := '0';
signal sig_burst_dbeat_cntr : Unsigned(BURST_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_dbeat_cntr : std_logic := '0';
signal sig_clr_dbeat_cntr : std_logic := '0';
signal sig_clr_dbc_reg : std_logic := '0';
signal sig_dbc_max : std_logic := '0';
signal sig_pcc2ibtt_xfer_ready : std_logic := '0';
signal sig_byte_cntr : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_byte_cntr_incr_value : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_byte_cntr : std_logic := '0';
signal sig_incr_byte_cntr : std_logic := '0';
signal sig_clr_byte_cntr : std_logic := '0';
signal sig_fifo_tstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
signal sig_num_ls_zeros : integer range 0 to STRM_WSTB_WIDTH := 0;
signal sig_ls_assert_found : std_logic := '0';
signal sig_num_ms_zeros : integer range 0 to STRM_WSTB_WIDTH := 0;
signal sig_ms_assert_found : std_logic := '0';
-- signal sig_num_zeros : unsigned(NUM_ZEROS_WIDTH-1 downto 0) := (others => '0');
-- signal sig_num_ones : unsigned(NUM_ZEROS_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs2sfcc_asserted : std_logic_vector(MMAP_STBS_ASSERTED_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs2wdc_asserted : std_logic_vector(MMAP_STBS_ASSERTED_WIDTH-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_stbs_asserted : std_logic_vector(MMAP_STBS_ASSERTED_WIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_in_tready : std_logic := '0';
signal sig_skidbuf_in_tvalid : std_logic := '0';
signal sig_skidbuf_in_tdata : std_logic_vector(SKIDBUF2WDC_DWIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_in_tstrb : std_logic_vector(SKIDBUF2WDC_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_in_tlast : std_logic := '0';
signal sig_skidbuf_in_eop : std_logic := '0';
signal sig_skidbuf_out_tready : std_logic := '0';
signal sig_skidbuf_out_tvalid : std_logic := '0';
signal sig_skidbuf_out_tdata : std_logic_vector(SKIDBUF2WDC_DWIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_out_tstrb : std_logic_vector(SKIDBUF2WDC_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_out_tlast : std_logic := '0';
signal sig_skidbuf_out_eop : std_logic := '0';
signal sig_enable_dbcntr : std_logic := '0';
signal sig_good_fifo_write : std_logic := '0';
begin --(architecture implementation)
-- Write Data Controller I/O
sig_wdc2ibtt_tready <= wdc2ibtt_tready ;
ibtt2wdc_tvalid <= sig_ibtt2wdc_tvalid ;
ibtt2wdc_tdata <= sig_ibtt2wdc_tdata ;
ibtt2wdc_tstrb <= sig_ibtt2wdc_tstrb ;
ibtt2wdc_tlast <= sig_ibtt2wdc_tlast ;
ibtt2wdc_eop <= sig_ibtt2wdc_eop ;
ibtt2wdc_stbs_asserted <= sig_ibtt2wdc_stbs_asserted;
-- PCC I/O
sf2pcc_xfer_valid <= sig_xd_fifo_dvalid;
sig_pcc2ibtt_xfer_ready <= pcc2sf_xfer_ready;
sf2pcc_packet_eop <= sig_xd_fifo_data_out(BYTE_CNTR_WIDTH+1);
sf2pcc_cmd_cmplt <= sig_xd_fifo_data_out(BYTE_CNTR_WIDTH);
sf2pcc_xfer_bytes <= sig_xd_fifo_data_out(BYTE_CNTR_WIDTH-1 downto 0);
-- DRE Stream In
ibtt2dre_tready <= sig_strm_in_ready;
-- sig_strm_in_ready <= not(sig_xd_fifo_full) and
-- not(sig_data_fifo_full);
sig_good_strm_dbeat <= dre2ibtt_tvalid and
sig_strm_in_ready;
sig_good_tlast_dbeat <= sig_good_strm_dbeat and
dre2ibtt_tlast;
-- Burst Packet Counter Logic -------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_DBC_STUFF
--
-- Process Description:
-- Just a register for data beat counter signals.
--
-------------------------------------------------------------
REG_DBC_STUFF : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_dre2ibtt_tlast_reg <= '0';
sig_dre2ibtt_eop_reg <= '0';
sig_clr_dbc_reg <= '0';
else
sig_dre2ibtt_tlast_reg <= dre2ibtt_tlast;
sig_dre2ibtt_eop_reg <= dre2ibtt_eop;
sig_clr_dbc_reg <= sig_clr_dbeat_cntr;
end if;
end if;
end process REG_DBC_STUFF;
-- sig_clr_dbc_reg <= sig_clr_dbeat_cntr;
-- Increment the dataBeat counter on a data fifo wide
-- load condition. If packer logic is enabled, this will
-- only occur when a full fifo data width has been collected
-- from the Stream input.
sig_incr_dbeat_cntr <= sig_good_strm_dbeat and
sig_enable_dbcntr;
-- Check to see if a max burst len of databeats have been
-- loaded into the FIFO
sig_dbc_max <= '1'
when (sig_burst_dbeat_cntr = MAX_BURST_DBEATS)
Else '0';
-- Start the counter over at a max burst len boundary or at
-- the end of the packet.
sig_clr_dbeat_cntr <= '1'
when (sig_dbc_max = '1' and
sig_good_strm_dbeat = '1' and
sig_enable_dbcntr = '1') or
(sig_good_tlast_dbeat = '1' and
sig_enable_dbcntr = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DBC_CMTR
--
-- Process Description:
-- The Databeat Counter keeps track of how many databeats have
-- been loaded into the Data FIFO. When a max burst worth of
-- databeats have been loaded (or a TLAST encountered), the
-- XD FIFO can be loaded with a transfer data set to be sent
-- to the IBTTCC.
--
-------------------------------------------------------------
IMP_DBC_CMTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_dbeat_cntr = '1') then
sig_burst_dbeat_cntr <= (others => '0');
elsif (sig_incr_dbeat_cntr = '1') then
sig_burst_dbeat_cntr <= sig_burst_dbeat_cntr + DBC_ONE;
else
null; -- hold current value
end if;
end if;
end process IMP_DBC_CMTR;
----- Byte Counter Logic -----------------------------------------------
sig_clr_byte_cntr <= sig_clr_dbc_reg and
not(sig_good_strm_dbeat);
sig_ld_byte_cntr <= sig_clr_dbc_reg and
sig_good_strm_dbeat;
sig_incr_byte_cntr <= sig_good_strm_dbeat;
sig_byte_cntr_incr_value <= RESIZE(UNSIGNED(sig_stbs2sfcc_asserted), BYTE_CNTR_WIDTH);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BYTE_CMTR
--
-- Process Description:
-- Keeps a running byte count per burst packet loaded into the
-- xfer FIFO. It is based on the strobes set on the incoming
-- Stream dbeat.
--
-------------------------------------------------------------
IMP_BYTE_CMTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_byte_cntr = '1') then
sig_byte_cntr <= (others => '0');
elsif (sig_ld_byte_cntr = '1') then
sig_byte_cntr <= sig_byte_cntr_incr_value;
elsif (sig_incr_byte_cntr = '1') then
sig_byte_cntr <= sig_byte_cntr + sig_byte_cntr_incr_value;
else
null; -- hold current value
end if;
end if;
end process IMP_BYTE_CMTR;
------------------------------------------------------------
-- Instance: I_IBTTCC_STBS_SET
--
-- Description:
-- Instance of the asserted strobe counter for the IBTTCC
-- interface.
--
------------------------------------------------------------
SAME_WIDTH_NO_DRE : if (C_ENABLE_DRE = 0 and (C_STREAM_DWIDTH = C_MMAP_DWIDTH)) generate
begin
I_IBTTCC_STBS_SET : entity axi_datamover_v5_1.axi_datamover_stbs_set_nodre
generic map (
C_STROBE_WIDTH => STRM_WSTB_WIDTH
)
port map (
tstrb_in => dre2ibtt_tstrb,
num_stbs_asserted => sig_stbs2sfcc_asserted -- 8 bit wide slv
);
end generate SAME_WIDTH_NO_DRE;
DIFF_WIDTH_OR_DRE : if (C_ENABLE_DRE /= 0 or (C_STREAM_DWIDTH /= C_MMAP_DWIDTH)) generate
begin
I_IBTTCC_STBS_SET : entity axi_datamover_v5_1.axi_datamover_stbs_set
generic map (
C_STROBE_WIDTH => STRM_WSTB_WIDTH
)
port map (
tstrb_in => dre2ibtt_tstrb,
num_stbs_asserted => sig_stbs2sfcc_asserted -- 8 bit wide slv
);
end generate DIFF_WIDTH_OR_DRE;
----- Xfer Descriptor FIFO Logic -----------------------------------------------
sig_push_xd_fifo <= sig_clr_dbc_reg ;
sig_pop_xd_fifo <= sig_pcc2ibtt_xfer_ready and
sig_xd_fifo_dvalid ;
sig_xd_fifo_data_in <= sig_dre2ibtt_eop_reg & -- (TLAST for the input Stream)
sig_dre2ibtt_tlast_reg & -- (TLAST for the IBTTCC command)
std_logic_vector(sig_byte_cntr); -- Number of bytes in this xfer
------------------------------------------------------------
-- Instance: I_XD_FIFO
--
-- Description:
-- Implement the Transfer Desciptor (XD) FIFO. This FIFO holds
-- the individual child command xfer descriptors used by the
-- IBTTCC to generate the commands sent to the Address Cntlr and
-- the Data Cntlr.
--
------------------------------------------------------------
I_XD_FIFO : entity axi_datamover_v5_1.axi_datamover_sfifo_autord
generic map (
C_DWIDTH => XD_FIFO_WIDTH ,
C_DEPTH => XD_FIFO_DEPTH ,
C_DATA_CNT_WIDTH => XD_FIFO_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => 0 ,
C_NEED_ALMOST_FULL => 1 ,
C_USE_BLKMEM => 0 ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => mmap_reset ,
SFIFO_Clk => primary_aclk ,
SFIFO_Wr_en => sig_push_xd_fifo ,
SFIFO_Din => sig_xd_fifo_data_in ,
SFIFO_Rd_en => sig_pop_xd_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_xd_fifo_dvalid ,
SFIFO_Dout => sig_xd_fifo_data_out ,
SFIFO_Full => sig_xd_fifo_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => sig_tmp ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => open ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => open ,
SFIFO_Rd_ack => open
);
----------------------------------------------------------------
-- Packing Logic ------------------------------------------
----------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_PACKING
--
-- If Generate Description:
-- Omits any packing logic in the Store and Forward module.
-- The Stream and MMap data widths are the same.
--
------------------------------------------------------------
OMIT_PACKING : if (C_MMAP_DWIDTH = C_STREAM_DWIDTH) generate
begin
-- The data beat counter is always enabled when the packer
-- is omitted.
sig_enable_dbcntr <= '1';
sig_good_fifo_write <= sig_good_strm_dbeat;
sig_strm_in_ready <= not(sig_xd_fifo_full) and
not(sig_data_fifo_full) and
not (sig_tmp);
GEN_S2MM_TKEEP_ENABLE5 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Concatonate the Stream inputs into the single FIFO data
-- word input value
sig_data_fifo_data_in <= dre2ibtt_eop & -- end of packet marker
dre2ibtt_tlast & -- Tlast marker
dre2ibtt_tstrb & -- TSTRB Value
dre2ibtt_tdata; -- data value
end generate GEN_S2MM_TKEEP_ENABLE5;
GEN_S2MM_TKEEP_DISABLE5 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Concatonate the Stream inputs into the single FIFO data
-- word input value
sig_data_fifo_data_in <= dre2ibtt_eop & -- end of packet marker
dre2ibtt_tlast & -- Tlast marker
--dre2ibtt_tstrb & -- TSTRB Value
dre2ibtt_tdata; -- data value
end generate GEN_S2MM_TKEEP_DISABLE5;
end generate OMIT_PACKING;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_PACKING
--
-- If Generate Description:
-- Includes packing logic in the IBTT Store and Forward
-- module. The MMap Data bus is wider than the Stream width.
--
------------------------------------------------------------
INCLUDE_PACKING : if (C_MMAP_DWIDTH > C_STREAM_DWIDTH) generate
Constant TLAST_WIDTH : integer := 1; -- bit
Constant EOP_WIDTH : integer := 1; -- bit
Constant DATA_SLICE_WIDTH : integer := C_STREAM_DWIDTH;
Constant STRB_SLICE_WIDTH : integer := STRM_WSTB_WIDTH;
Constant FLAG_SLICE_WIDTH : integer := TLAST_WIDTH +
EOP_WIDTH;
Constant OFFSET_CNTR_WIDTH : integer := funct_get_cntr_width(MMAP2STRM_WIDTH_RATO);
Constant OFFSET_CNT_ONE : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, OFFSET_CNTR_WIDTH);
Constant OFFSET_CNT_MAX : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(MMAP2STRM_WIDTH_RATO-1, OFFSET_CNTR_WIDTH);
-- Types -----------------------------------------------------------------------------
type lsig_data_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(DATA_SLICE_WIDTH-1 downto 0);
type lsig_strb_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(STRB_SLICE_WIDTH-1 downto 0);
type lsig_flag_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(FLAG_SLICE_WIDTH-1 downto 0);
-- local signals
signal lsig_data_slice_reg : lsig_data_slice_type;
signal lsig_strb_slice_reg : lsig_strb_slice_type;
signal lsig_flag_slice_reg : lsig_flag_slice_type;
signal lsig_reg_segment : std_logic_vector(DATA_SLICE_WIDTH-1 downto 0) := (others => '0');
signal lsig_segment_ld : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_segment_clr : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_0ffset_to_to_use : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_0ffset_cntr : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_ld_offset : std_logic := '0';
signal lsig_incr_offset : std_logic := '0';
signal lsig_offset_cntr_eq_max : std_logic := '0';
signal lsig_combined_data : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0');
signal lsig_combined_strb : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
signal lsig_tlast_or : std_logic := '0';
signal lsig_eop_or : std_logic := '0';
signal lsig_partial_tlast_or : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_partial_eop_or : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_packer_full : std_logic := '0';
signal lsig_packer_empty : std_logic := '0';
signal lsig_set_packer_full : std_logic := '0';
signal lsig_good_push2fifo : std_logic := '0';
signal lsig_first_dbeat : std_logic := '0';
begin
-- Generate the stream ready
sig_strm_in_ready <= not(sig_xd_fifo_full) and
not(sig_tmp) and
(not(lsig_packer_full) or
lsig_good_push2fifo) ;
-- Enable the Data Beat counter when the packer is
-- going full
sig_enable_dbcntr <= lsig_set_packer_full;
-- Assign the flag indicating that a fifo write is going
-- to occur at the next rising clock edge.
sig_good_fifo_write <= lsig_good_push2fifo;
GEN_S2MM_TKEEP_ENABLE6 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Format the composite FIFO input data word
sig_data_fifo_data_in <= lsig_eop_or & -- MS Bit
lsig_tlast_or &
lsig_combined_strb &
lsig_combined_data ; -- LS Bits
end generate GEN_S2MM_TKEEP_ENABLE6;
GEN_S2MM_TKEEP_DISABLE6 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Format the composite FIFO input data word
sig_data_fifo_data_in <= lsig_eop_or & -- MS Bit
lsig_tlast_or &
--lsig_combined_strb &
lsig_combined_data ; -- LS Bits
end generate GEN_S2MM_TKEEP_DISABLE6;
-- Generate a flag indicating a write to the DataFIFO
-- is going to complete
lsig_good_push2fifo <= lsig_packer_full and
not(sig_data_fifo_full);
-- Generate the control that loads the starting address
-- offset for the next input packet
lsig_ld_offset <= lsig_first_dbeat and
sig_good_strm_dbeat;
-- Generate the control for incrementing the offset counter
lsig_incr_offset <= sig_good_strm_dbeat;
-- Generate a flag indicating the packer input register
-- array is full or has loaded the last data beat of
-- the input paket
lsig_set_packer_full <= sig_good_strm_dbeat and
(dre2ibtt_tlast or
lsig_offset_cntr_eq_max);
-- Check to see if the offset counter has reached its max
-- value
lsig_offset_cntr_eq_max <= '1'
--when (lsig_0ffset_cntr = OFFSET_CNT_MAX)
when (lsig_0ffset_to_to_use = OFFSET_CNT_MAX)
Else '0';
-- Mux between the input start offset and the offset counter
-- output to use for the packer slice load control.
lsig_0ffset_to_to_use <= UNSIGNED(dre2ibtt_strt_addr_offset)
when (lsig_first_dbeat = '1')
Else lsig_0ffset_cntr;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_OFFSET_LD_MARKER
--
-- Process Description:
-- Implements the flop indicating the first databeat of
-- an input data packet.
--
-------------------------------------------------------------
IMP_OFFSET_LD_MARKER : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_first_dbeat <= '1';
elsif (sig_good_strm_dbeat = '1' and
dre2ibtt_tlast = '0') then
lsig_first_dbeat <= '0';
Elsif (sig_good_strm_dbeat = '1' and
dre2ibtt_tlast = '1') Then
lsig_first_dbeat <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_OFFSET_LD_MARKER;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_OFFSET_CNTR
--
-- Process Description:
-- Implements the address offset counter that is used to
-- steer the data loads into the packer register slices.
-- Note that the counter has to be loaded with the starting
-- offset plus one to sync up with the data input.
-------------------------------------------------------------
IMP_OFFSET_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_0ffset_cntr <= (others => '0');
Elsif (lsig_ld_offset = '1') Then
lsig_0ffset_cntr <= UNSIGNED(dre2ibtt_strt_addr_offset) + OFFSET_CNT_ONE;
elsif (lsig_incr_offset = '1') then
lsig_0ffset_cntr <= lsig_0ffset_cntr + OFFSET_CNT_ONE;
else
null; -- Hold Current State
end if;
end if;
end process IMP_OFFSET_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PACK_REG_FULL
--
-- Process Description:
-- Implements the Packer Register full/empty flags
--
-------------------------------------------------------------
IMP_PACK_REG_FULL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_packer_full <= '0';
lsig_packer_empty <= '1';
Elsif (lsig_set_packer_full = '1' and
lsig_packer_full = '0') Then
lsig_packer_full <= '1';
lsig_packer_empty <= '0';
elsif (lsig_set_packer_full = '0' and
lsig_good_push2fifo = '1') then
lsig_packer_full <= '0';
lsig_packer_empty <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_PACK_REG_FULL;
------------------------------------------------------------
-- For Generate
--
-- Label: DO_REG_SLICES
--
-- For Generate Description:
--
-- Implements the Packng Register Slices
--
--
------------------------------------------------------------
DO_REG_SLICES : for slice_index in 0 to MMAP2STRM_WIDTH_RATO-1 generate
begin
-- generate the register load enable for each slice segment based
-- on the address offset count value
lsig_segment_ld(slice_index) <= '1'
when (sig_good_strm_dbeat = '1' and
TO_INTEGER(lsig_0ffset_to_to_use) = slice_index)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DATA_SLICE
--
-- Process Description:
-- Implement a data register slice abd Strobe register slice
-- for the packer (upsizer).
--
-------------------------------------------------------------
IMP_DATA_SLICE : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_data_slice_reg(slice_index) <= (others => '0');
lsig_strb_slice_reg(slice_index) <= (others => '0');
elsif (lsig_segment_ld(slice_index) = '1') then
lsig_data_slice_reg(slice_index) <= dre2ibtt_tdata;
lsig_strb_slice_reg(slice_index) <= dre2ibtt_tstrb;
-- optional clear of slice reg
elsif (lsig_segment_ld(slice_index) = '0' and
lsig_good_push2fifo = '1') then
lsig_data_slice_reg(slice_index) <= (others => '0');
lsig_strb_slice_reg(slice_index) <= (others => '0');
else
null; -- Hold Current State
end if;
end if;
end process IMP_DATA_SLICE;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FLAG_SLICE
--
-- Process Description:
-- Implement a flag register slice for the packer.
--
-------------------------------------------------------------
IMP_FLAG_SLICE : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_flag_slice_reg(slice_index) <= (others => '0');
elsif (lsig_segment_ld(slice_index) = '1') then
lsig_flag_slice_reg(slice_index) <= dre2ibtt_tlast & -- bit 1
dre2ibtt_eop; -- bit 0
elsif (lsig_segment_ld(slice_index) = '0' and
lsig_good_push2fifo = '1') then
lsig_flag_slice_reg(slice_index) <= (others => '0');
else
null; -- Hold Current State
end if;
end if;
end process IMP_FLAG_SLICE;
end generate DO_REG_SLICES;
-- Do the OR functions of the Flags -------------------------------------
lsig_tlast_or <= lsig_partial_tlast_or(MMAP2STRM_WIDTH_RATO-1) ;
lsig_eop_or <= lsig_partial_eop_or(MMAP2STRM_WIDTH_RATO-1);
lsig_partial_tlast_or(0) <= lsig_flag_slice_reg(0)(1);
lsig_partial_eop_or(0) <= lsig_flag_slice_reg(0)(0);
------------------------------------------------------------
-- For Generate
--
-- Label: DO_FLAG_OR
--
-- For Generate Description:
-- Implement the OR of the TLAST and EOP Error flags.
--
--
--
------------------------------------------------------------
DO_FLAG_OR : for slice_index in 1 to MMAP2STRM_WIDTH_RATO-1 generate
begin
lsig_partial_tlast_or(slice_index) <= lsig_partial_tlast_or(slice_index-1) or
--lsig_partial_tlast_or(slice_index);
lsig_flag_slice_reg(slice_index)(1);
lsig_partial_eop_or(slice_index) <= lsig_partial_eop_or(slice_index-1) or
--lsig_partial_eop_or(slice_index);
lsig_flag_slice_reg(slice_index)(0);
end generate DO_FLAG_OR;
------------------------------------------------------------
-- For Generate
--
-- Label: DO_DATA_COMBINER
--
-- For Generate Description:
-- Combines the Data Slice register and Strobe slice register
-- outputs into a single data and single strobe vector used for
-- input data to the Data FIFO.
--
--
------------------------------------------------------------
DO_DATA_COMBINER : for slice_index in 1 to MMAP2STRM_WIDTH_RATO generate
begin
lsig_combined_data((slice_index*DATA_SLICE_WIDTH)-1 downto
(slice_index-1)*DATA_SLICE_WIDTH) <=
lsig_data_slice_reg(slice_index-1);
lsig_combined_strb((slice_index*STRB_SLICE_WIDTH)-1 downto
(slice_index-1)*STRB_SLICE_WIDTH) <=
lsig_strb_slice_reg(slice_index-1);
end generate DO_DATA_COMBINER;
end generate INCLUDE_PACKING;
-- Data FIFO Logic ------------------------------------------
--sig_push_data_fifo <= sig_good_strm_dbeat;
sig_push_data_fifo <= sig_good_fifo_write;
sig_pop_data_fifo <= sig_skidbuf_in_tready and
sig_data_fifo_dvalid;
-- -- Concatonate the Stream inputs into the single FIFO data in value
-- sig_data_fifo_data_in <= dre2ibtt_eop & -- end of packet marker
-- dre2ibtt_tlast &
-- dre2ibtt_tstrb &
-- dre2ibtt_tdata;
------------------------------------------------------------
-- Instance: I_DATA_FIFO
--
-- Description:
-- Implements the Store and Forward data FIFO
--
------------------------------------------------------------
I_DATA_FIFO : entity axi_datamover_v5_1.axi_datamover_sfifo_autord
generic map (
C_DWIDTH => DATA_FIFO_WIDTH ,
C_DEPTH => DATA_FIFO_DEPTH ,
C_DATA_CNT_WIDTH => DATA_FIFO_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => 0 ,
C_NEED_ALMOST_FULL => 0 ,
C_USE_BLKMEM => 1 ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => mmap_reset ,
SFIFO_Clk => primary_aclk ,
SFIFO_Wr_en => sig_push_data_fifo ,
SFIFO_Din => sig_data_fifo_data_in ,
SFIFO_Rd_en => sig_pop_data_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_data_fifo_dvalid ,
SFIFO_Dout => sig_data_fifo_data_out ,
SFIFO_Full => sig_data_fifo_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => open ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => sig_data_fifo_rd_cnt ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => sig_data_fifo_wr_cnt ,
SFIFO_Rd_ack => open
);
-------------------------------------------------------------------------
---------------- Asserted TSTRB calculation logic ---------------------
-------------------------------------------------------------------------
GEN_S2MM_TKEEP_ENABLE7 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Rip the write strobe value from the FIFO output data
sig_fifo_tstrb_out <= sig_data_fifo_data_out(DATA_FIFO_WIDTH-3 downto
C_MMAP_DWIDTH);
end generate GEN_S2MM_TKEEP_ENABLE7;
GEN_S2MM_TKEEP_DISBALE7 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
sig_fifo_tstrb_out <= (others => '1');
end generate GEN_S2MM_TKEEP_DISBALE7;
------------------------------------------------------------
-- Instance: I_WDC_STBS_SET
--
-- Description:
-- Instance of the asserted strobe counter for the WDC
-- interface.
--
------------------------------------------------------------
SAME_WIDTH_NO_DRE_WDC : if (C_ENABLE_DRE = 0 and (C_STREAM_DWIDTH = C_MMAP_DWIDTH)) generate
begin
I_WDC_STBS_SET : entity axi_datamover_v5_1.axi_datamover_stbs_set_nodre
generic map (
C_STROBE_WIDTH => MMAP_WSTB_WIDTH
)
port map (
tstrb_in => sig_fifo_tstrb_out,
num_stbs_asserted => sig_stbs2wdc_asserted
);
end generate SAME_WIDTH_NO_DRE_WDC;
DIFF_WIDTH_OR_DRE_WDC : if (C_ENABLE_DRE /= 0 or (C_STREAM_DWIDTH /= C_MMAP_DWIDTH)) generate
begin
I_WDC_STBS_SET : entity axi_datamover_v5_1.axi_datamover_stbs_set
generic map (
C_STROBE_WIDTH => MMAP_WSTB_WIDTH
)
port map (
tstrb_in => sig_fifo_tstrb_out,
num_stbs_asserted => sig_stbs2wdc_asserted
);
end generate DIFF_WIDTH_OR_DRE_WDC;
-------------------------------------------------------------------------
------- Isolation Skid Buffer Logic (needed for Fmax timing) -----------
-------------------------------------------------------------------------
-- Skid Buffer output assignments -----------
sig_skidbuf_out_tready <= sig_wdc2ibtt_tready;
sig_ibtt2wdc_tvalid <= sig_skidbuf_out_tvalid;
sig_ibtt2wdc_tdata <= sig_skidbuf_out_tdata(C_MMAP_DWIDTH-1 downto 0) ;
sig_ibtt2wdc_tstrb <= sig_skidbuf_out_tstrb(MMAP_WSTB_WIDTH-1 downto 0) ;
sig_ibtt2wdc_tlast <= sig_skidbuf_out_tlast ;
-- Rip the EOP marker from the MS bit of the skid output strobes
sig_ibtt2wdc_eop <= sig_skidbuf_out_tstrb(MMAP_WSTB_WIDTH) ;
-- Rip the upper 8 bits of the skid output data for the strobes asserted value
sig_ibtt2wdc_stbs_asserted <= sig_skidbuf_out_tdata(SKIDBUF2WDC_DWIDTH-1 downto
C_MMAP_DWIDTH);
-- Skid Buffer input assignments -----------
sig_skidbuf_in_tvalid <= sig_data_fifo_dvalid;
sig_skidbuf_in_eop <= sig_data_fifo_data_out(DATA_FIFO_WIDTH-1);
sig_skidbuf_in_tlast <= sig_data_fifo_data_out(DATA_FIFO_WIDTH-2);
-- Steal the extra input strobe bit and use it for the EOP marker
---- sig_skidbuf_in_tstrb <= sig_skidbuf_in_eop &
---- sig_data_fifo_data_out(DATA_FIFO_WIDTH-3 downto
---- C_MMAP_DWIDTH);
----
sig_skidbuf_in_tstrb <= sig_skidbuf_in_eop &
sig_fifo_tstrb_out;
-- Insert the Strobes Asserted count in the extra (MS) data byte
-- for the skid buffer
sig_skidbuf_in_tdata <= sig_stbs2wdc_asserted &
sig_data_fifo_data_out(C_MMAP_DWIDTH-1 downto 0);
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(2) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_INDET_BTT_SKID_BUF
--
-- Description:
-- Instance for the Store and Forward isolation Skid Buffer
-- which is required to achieve Fmax timing. Note that this
-- skid buffer is 1 byte wider than the stream data width to
-- allow for the asserted strobes count to be passed through
-- it. The EOP marker is inserted in the extra strobe slot.
--
------------------------------------------------------------
I_INDET_BTT_SKID_BUF : entity axi_datamover_v5_1.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => SKIDBUF2WDC_DWIDTH
)
port map (
-- System Ports
aclk => primary_aclk ,
arst => mmap_reset ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => LOGIC_LOW ,
-- Slave Side (Stream Data Input)
s_valid => sig_skidbuf_in_tvalid ,
s_ready => sig_skidbuf_in_tready ,
s_data => sig_skidbuf_in_tdata ,
s_strb => sig_skidbuf_in_tstrb ,
s_last => sig_skidbuf_in_tlast ,
-- Master Side (Stream Data Output
m_valid => sig_skidbuf_out_tvalid ,
m_ready => sig_skidbuf_out_tready ,
m_data => sig_skidbuf_out_tdata ,
m_strb => sig_skidbuf_out_tstrb ,
m_last => sig_skidbuf_out_tlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(2) = '0' generate
begin
sig_skidbuf_out_tvalid <= sig_skidbuf_in_tvalid;
sig_skidbuf_in_tready <= sig_skidbuf_out_tready ;
sig_skidbuf_out_tdata <= sig_skidbuf_in_tdata ;
sig_skidbuf_out_tstrb <= sig_skidbuf_in_tstrb ;
sig_skidbuf_out_tlast <= sig_skidbuf_in_tlast ;
end generate DISABLE_AXIS_SKID;
end implementation;
|
mit
|
justingallagher/fpga-trace
|
design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/950a27d1/hdl/src/vhdl/axi_sg_ftch_mngr.vhd
|
4
|
25954
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_mngr.vhd
-- Description: This entity manages fetching of descriptors.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_mngr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control and Status --
ch1_run_stop : in std_logic ; --
ch1_desc_flush : in std_logic ; --
ch1_updt_done : in std_logic ; --
ch1_ftch_idle : out std_logic ; --
ch1_ftch_active : out std_logic ; --
ch1_ftch_interr_set : out std_logic ; --
ch1_ftch_slverr_set : out std_logic ; --
ch1_ftch_decerr_set : out std_logic ; --
ch1_ftch_err_early : out std_logic ; --
ch1_ftch_stale_desc : out std_logic ; --
ch1_tailpntr_enabled : in std_logic ; --
ch1_taildesc_wren : in std_logic ; --
ch1_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_nxtdesc_wren : in std_logic ; --
ch1_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_ftch_queue_empty : in std_logic ; --
ch1_ftch_queue_full : in std_logic ; --
ch1_ftch_pause : in std_logic ; --
--
-- Channel 2 Control and Status --
ch2_run_stop : in std_logic ; --
ch2_updt_done : in std_logic ; --
ch2_desc_flush : in std_logic ; --
ch2_ftch_idle : out std_logic ; --
ch2_ftch_active : out std_logic ; --
ch2_ftch_interr_set : out std_logic ; --
ch2_ftch_slverr_set : out std_logic ; --
ch2_ftch_decerr_set : out std_logic ; --
ch2_ftch_err_early : out std_logic ; --
ch2_ftch_stale_desc : out std_logic ; --
ch2_tailpntr_enabled : in std_logic ; --
ch2_taildesc_wren : in std_logic ; --
ch2_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_nxtdesc_wren : in std_logic ; --
ch2_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_ftch_queue_empty : in std_logic ; --
ch2_ftch_queue_full : in std_logic ; --
ch2_ftch_pause : in std_logic ; --
ch2_eof_detected : in std_logic ;
tail_updt : in std_logic ;
tail_updt_latch : out std_logic ;
ch2_sg_idle : out std_logic ;
--
nxtdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- Read response for detecting slverr, decerr early --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_rvalid : in std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_ftch_cmd_tvalid : out std_logic ; --
s_axis_ftch_cmd_tready : in std_logic ; --
s_axis_ftch_cmd_tdata : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_ftch_sts_tvalid : in std_logic ; --
m_axis_ftch_sts_tready : out std_logic ; --
m_axis_ftch_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_ftch_sts_tkeep : in std_logic_vector(0 downto 0) ; --
mm2s_err : in std_logic ; --
--
--
ftch_cmnd_wr : out std_logic ; --
ftch_cmnd_data : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
ftch_stale_desc : in std_logic ; --
updt_error : in std_logic ; --
ftch_error : out std_logic ; --
ftch_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
bd_eq : out std_logic
);
end axi_sg_ftch_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ftch_cmnd_wr_i : std_logic := '0';
signal ftch_cmnd_data_i : std_logic_vector
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0)
:= (others => '0');
signal ch1_sg_idle : std_logic := '0';
signal ch1_fetch_address : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal ch2_sg_idle_int : std_logic := '0';
signal ch2_fetch_address : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal ftch_done : std_logic := '0';
signal ftch_error_i : std_logic := '0';
signal ftch_interr : std_logic := '0';
signal ftch_slverr : std_logic := '0';
signal ftch_decerr : std_logic := '0';
signal ftch_error_early : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ftch_cmnd_wr <= ftch_cmnd_wr_i;
ftch_cmnd_data <= ftch_cmnd_data_i;
ftch_error <= ftch_error_i;
ch2_sg_idle <= ch2_sg_idle_int;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch State Machine
-------------------------------------------------------------------------------
I_FTCH_SG : entity axi_sg_v4_1.axi_sg_ftch_sm
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_SG_CH1_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_SG_FTCH_DESC2QUEUE => C_SG_FTCH_DESC2QUEUE ,
C_SG_CH1_ENBL_STALE_ERROR => C_SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_ENBL_STALE_ERROR => C_SG_CH2_ENBL_STALE_ERROR
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
updt_error => updt_error ,
-- Channel 1 Control and Status
ch1_run_stop => ch1_run_stop ,
ch1_updt_done => ch1_updt_done ,
ch1_desc_flush => ch1_desc_flush ,
ch1_sg_idle => ch1_sg_idle ,
ch1_tailpntr_enabled => ch1_tailpntr_enabled ,
ch1_ftch_queue_empty => ch1_ftch_queue_empty ,
ch1_ftch_queue_full => ch1_ftch_queue_full ,
ch1_fetch_address => ch1_fetch_address ,
ch1_ftch_active => ch1_ftch_active ,
ch1_ftch_idle => ch1_ftch_idle ,
ch1_ftch_interr_set => ch1_ftch_interr_set ,
ch1_ftch_slverr_set => ch1_ftch_slverr_set ,
ch1_ftch_decerr_set => ch1_ftch_decerr_set ,
ch1_ftch_err_early => ch1_ftch_err_early ,
ch1_ftch_stale_desc => ch1_ftch_stale_desc ,
ch1_ftch_pause => ch1_ftch_pause ,
-- Channel 2 Control and Status
ch2_run_stop => ch2_run_stop ,
ch2_updt_done => ch2_updt_done ,
ch2_desc_flush => ch2_desc_flush ,
ch2_sg_idle => ch2_sg_idle_int ,
ch2_tailpntr_enabled => ch2_tailpntr_enabled ,
ch2_ftch_queue_empty => ch2_ftch_queue_empty ,
ch2_ftch_queue_full => ch2_ftch_queue_full ,
ch2_fetch_address => ch2_fetch_address ,
ch2_ftch_active => ch2_ftch_active ,
ch2_ftch_idle => ch2_ftch_idle ,
ch2_ftch_interr_set => ch2_ftch_interr_set ,
ch2_ftch_slverr_set => ch2_ftch_slverr_set ,
ch2_ftch_decerr_set => ch2_ftch_decerr_set ,
ch2_ftch_err_early => ch2_ftch_err_early ,
ch2_ftch_stale_desc => ch2_ftch_stale_desc ,
ch2_ftch_pause => ch2_ftch_pause ,
-- Transfer Request
ftch_cmnd_wr => ftch_cmnd_wr_i ,
ftch_cmnd_data => ftch_cmnd_data_i ,
-- Transfer Status
ftch_done => ftch_done ,
ftch_error => ftch_error_i ,
ftch_interr => ftch_interr ,
ftch_slverr => ftch_slverr ,
ftch_decerr => ftch_decerr ,
ftch_stale_desc => ftch_stale_desc ,
ftch_error_addr => ftch_error_addr ,
ftch_error_early => ftch_error_early
);
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Pointer Manager
-------------------------------------------------------------------------------
I_FTCH_PNTR_MNGR : entity axi_sg_v4_1.axi_sg_ftch_pntr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
nxtdesc => nxtdesc ,
-------------------------------
-- CHANNEL 1
-------------------------------
ch1_run_stop => ch1_run_stop ,
ch1_desc_flush => ch1_desc_flush ,--CR568950
-- CURDESC update on run/stop assertion (from ftch_sm)
ch1_curdesc => ch1_curdesc ,
-- TAILDESC update on CPU write (from axi_dma_reg_module)
ch1_tailpntr_enabled => ch1_tailpntr_enabled ,
ch1_taildesc_wren => ch1_taildesc_wren ,
ch1_taildesc => ch1_taildesc ,
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if)
ch1_nxtdesc_wren => ch1_nxtdesc_wren ,
-- Current address of descriptor to fetch
ch1_fetch_address => ch1_fetch_address ,
ch1_sg_idle => ch1_sg_idle ,
-------------------------------
-- CHANNEL 2
-------------------------------
ch2_run_stop => ch2_run_stop ,
ch2_desc_flush => ch2_desc_flush ,--CR568950
ch2_eof_detected => ch2_eof_detected ,
-- CURDESC update on run/stop assertion (from ftch_sm)
ch2_curdesc => ch2_curdesc ,
-- TAILDESC update on CPU write (from axi_dma_reg_module)
ch2_tailpntr_enabled => ch2_tailpntr_enabled ,
ch2_taildesc_wren => ch2_taildesc_wren ,
ch2_taildesc => ch2_taildesc ,
tail_updt_latch => tail_updt_latch ,
tail_updt => tail_updt ,
ch2_updt_done => ch2_updt_done ,
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if)
ch2_nxtdesc_wren => ch2_nxtdesc_wren ,
-- Current address of descriptor to fetch
ch2_fetch_address => ch2_fetch_address ,
ch2_sg_idle => ch2_sg_idle_int ,
bd_eq => bd_eq
);
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Command / Status Interface
-------------------------------------------------------------------------------
I_FTCH_CMDSTS_IF : entity axi_sg_v4_1.axi_sg_ftch_cmdsts_if
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Fetch command write interface from fetch sm
ftch_cmnd_wr => ftch_cmnd_wr_i ,
ftch_cmnd_data => ftch_cmnd_data_i ,
-- Read response for detecting slverr, decerr early
m_axi_sg_rresp => m_axi_sg_rresp ,
m_axi_sg_rvalid => m_axi_sg_rvalid ,
-- User Command Interface Ports (AXI Stream)
s_axis_ftch_cmd_tvalid => s_axis_ftch_cmd_tvalid ,
s_axis_ftch_cmd_tready => s_axis_ftch_cmd_tready ,
s_axis_ftch_cmd_tdata => s_axis_ftch_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_ftch_sts_tvalid => m_axis_ftch_sts_tvalid ,
m_axis_ftch_sts_tready => m_axis_ftch_sts_tready ,
m_axis_ftch_sts_tdata => m_axis_ftch_sts_tdata ,
m_axis_ftch_sts_tkeep => m_axis_ftch_sts_tkeep ,
-- Scatter Gather Fetch Status
mm2s_err => mm2s_err ,
ftch_done => ftch_done ,
ftch_error => ftch_error_i ,
ftch_interr => ftch_interr ,
ftch_slverr => ftch_slverr ,
ftch_decerr => ftch_decerr ,
ftch_error_early => ftch_error_early
);
end implementation;
|
mit
|
justingallagher/fpga-trace
|
design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/f4229bb6/hdl/src/vhdl/axi_datamover_s2mm_omit_wrap.vhd
|
18
|
17501
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_omit_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_omit_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Omit Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_omit_wrap is
generic (
C_INCLUDE_S2MM : Integer range 0 to 2 := 0;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Lite S2MM functionality
C_S2MM_AWID : Integer range 0 to 255 := 9;
-- Specifies the constant value to output on
-- the ARID output port
C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_S2MM_MDATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S2MM_SDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 0;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if Store and Forward is enabled
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- S2MM Primary Clock and reset inputs -----------------------
s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- S2MM Halt request input control ---------------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- S2MM Error discrete output --------------------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional S2MM Command/Status Clock and Reset Inputs -------
-- Only used if C_S2MM_STSCMD_IS_ASYNC = 1 --
s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -----------------------------------------------------
s2mm_cmd_wvalid : in std_logic; --
s2mm_cmd_wready : out std_logic; --
s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); --
--------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) --------------------------------------------------------
s2mm_sts_wvalid : out std_logic; --
s2mm_sts_wready : in std_logic; --
s2mm_sts_wdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
s2mm_sts_wstrb : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
s2mm_sts_wlast : out std_logic; --
----------------------------------------------------------------------------------------------------
-- Address posting controls -----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
---------------------------------------------------------------------
-- S2MM AXI Address Channel I/O --------------------------------------
s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -----------
-- s2mm__awlock : out std_logic_vector(2 downto 0); --
-- s2mm__awcache : out std_logic_vector(4 downto 0); --
-- s2mm__awqos : out std_logic_vector(3 downto 0); --
-- s2mm__awregion : out std_logic_vector(3 downto 0); --
-----------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O ----------------------------------------------
s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); --
s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); --
s2mm_wlast : Out std_logic; --
s2mm_wvalid : Out std_logic; --
s2mm_wready : In std_logic; --
---------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O ------------------------------------------
s2mm_bresp : In std_logic_vector(1 downto 0); --
s2mm_bvalid : In std_logic; --
s2mm_bready : Out std_logic; --
---------------------------------------------------------------------------------------
-- S2MM AXI Master Stream Channel I/O ------------------------------------------------
s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); --
s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); --
s2mm_strm_wlast : In std_logic; --
s2mm_strm_wvalid : In std_logic; --
s2mm_strm_wready : Out std_logic; --
---------------------------------------------------------------------------------------
-- Testing Support I/O -----------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
----------------------------------------------------------------
);
end entity axi_datamover_s2mm_omit_wrap;
architecture implementation of axi_datamover_s2mm_omit_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
begin --(architecture implementation)
-- Just tie off output ports
s2mm_dbg_data <= X"CAFE0000" ; -- 32 bit Constant indicating S2MM OMIT type
s2mm_addr_req_posted <= '0' ;
s2mm_wr_xfer_cmplt <= '0' ;
s2mm_ld_nxt_len <= '0' ;
s2mm_wr_len <= (others => '0');
s2mm_halt_cmplt <= s2mm_halt ;
s2mm_err <= '0' ;
s2mm_cmd_wready <= '0' ;
s2mm_sts_wvalid <= '0' ;
s2mm_sts_wdata <= (others => '0');
s2mm_sts_wstrb <= (others => '0');
s2mm_sts_wlast <= '0' ;
s2mm_awid <= (others => '0');
s2mm_awaddr <= (others => '0');
s2mm_awlen <= (others => '0');
s2mm_awsize <= (others => '0');
s2mm_awburst <= (others => '0');
s2mm_awprot <= (others => '0');
s2mm_awcache <= (others => '0');
s2mm_awuser <= (others => '0');
s2mm_awvalid <= '0' ;
s2mm_wdata <= (others => '0');
s2mm_wstrb <= (others => '0');
s2mm_wlast <= '0' ;
s2mm_wvalid <= '0' ;
s2mm_bready <= '0' ;
s2mm_strm_wready <= '0' ;
-- Input ports are ignored
end implementation;
|
mit
|
hhuang25/uwaterloo_ece224
|
Lab1Good/sdram_pll.vhd
|
4
|
16139
|
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: sdram_pll.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 10.1 Build 197 01/19/2011 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY sdram_pll IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC
);
END sdram_pll;
ARCHITECTURE SYN OF sdram_pll IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire5_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire5 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING
);
PORT (
clk : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire5_bv(0 DOWNTO 0) <= "0";
sub_wire5 <= To_stdlogicvector(sub_wire5_bv);
sub_wire2 <= sub_wire0(1);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
c1 <= sub_wire2;
sub_wire3 <= inclk0;
sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;
altpll_component : altpll
GENERIC MAP (
clk0_divide_by => 1,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "-3000",
clk1_divide_by => 1,
clk1_duty_cycle => 50,
clk1_multiply_by => 1,
clk1_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone II",
lpm_hint => "CBX_MODULE_PREFIX=sdram_pll",
lpm_type => "altpll",
operation_mode => "NORMAL",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED"
)
PORT MAP (
inclk => sub_wire4,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "50.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "-3.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "sdram_pll.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "-3000"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL sdram_pll_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
mit
|
justingallagher/fpga-trace
|
design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/f4229bb6/hdl/src/vhdl/axi_datamover_rd_sf.vhd
|
6
|
75578
|
-------------------------------------------------------------------------------
-- axi_datamover_rd_sf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_rd_sf.vhd
--
-- Description:
-- This file implements the AXI DataMover Read (MM2S) Store and Forward module.
-- The design utilizes the AXI DataMover's new address pipelining
-- control function. The design is such that predictive address
-- pipelining can be supported on the AXI Read Bus without over-commiting
-- the internal Data FIFO and potentially throttling the Read Data Channel
-- if the Data FIFO goes full.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.all;
use lib_pkg_v1_0.lib_pkg.clog2;
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_sfifo_autord;
use axi_datamover_v5_1.axi_datamover_fifo;
-------------------------------------------------------------------------------
entity axi_datamover_rd_sf is
generic (
C_SF_FIFO_DEPTH : Integer range 128 to 8192 := 512;
-- Sets the desired depth of the internal Data FIFO.
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates the max burst length being used by the external
-- AXI4 Master for each AXI4 transfer request.
C_DRE_IS_USED : Integer range 0 to 1 := 0;
-- Indicates if the external Master is utilizing a DRE on
-- the stream input to this module.
C_DRE_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 1;
-- Specifies the depth of the internal dre control queue fifo
C_DRE_ALIGN_WIDTH : Integer range 1 to 3 := 2;
-- Sets the width of the DRE alignment control ports
C_MMAP_DWIDTH : Integer range 32 to 1024 := 64;
-- Sets the AXI4 Memory Mapped Bus Data Width
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the Stream Data Width for the Input and Output
-- Data streams.
C_STRT_SF_OFFSET_WIDTH : Integer range 1 to 7 := 2;
-- Sets the bit width of the starting address offset port
-- This should be set to log2(C_MMAP_DWIDTH/C_STREAM_DWIDTH)
C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1;
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input DRE command
C_FAMILY : String := "virtex7"
-- Indicates the target FPGA Family.
);
port (
-- Clock and Reset inputs --------------------------------------------
--
aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
reset : in std_logic; --
-- Reset used for the internal syncronization logic --
----------------------------------------------------------------------
-- DataMover Read Side Address Pipelining Control Interface ----------
--
ok_to_post_rd_addr : Out Std_logic; --
-- Indicates that the transfer token pool has at least --
-- one token available to borrow --
--
rd_addr_posted : In std_logic; --
-- Indication that a read address has been posted to AXI4 --
--
rd_xfer_cmplt : In std_logic; --
-- Indicates that the Datamover has completed a Read Data --
-- transfer on the AXI4 --
----------------------------------------------------------------------
-- Read Side Stream In from DataMover MM2S Read Data Controller ----------------------
--
sf2sin_tready : Out Std_logic; --
-- DRE Stream READY input --
--
sin2sf_tvalid : In std_logic; --
-- DRE Stream VALID Output --
--
sin2sf_tdata : In std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- DRE Stream DATA input --
--
sin2sf_tkeep : In std_logic_vector((C_MMAP_DWIDTH/8)-1 downto 0); --
-- DRE Stream STRB input --
--
sin2sf_tlast : In std_logic; --
-- DRE Xfer LAST input --
--------------------------------------------------------------------------------------
-- RDC Store and Forward Supplimental Controls ---------------------
-- These are time aligned and qualified with the RDC Stream Input --
--
data2sf_cmd_cmplt : In std_logic; --
data2sf_dre_flush : In std_logic; --
--------------------------------------------------------------------
-- DRE Control Interface from the Command Calculator -----------------------------
--
dre2mstr_cmd_ready : Out std_logic ; --
-- Indication from the DRE that the command is being --
-- accepted from the Command Calculator --
--
mstr2dre_cmd_valid : In std_logic; --
-- The next command valid indication to the DRE --
-- from the Command Calculator --
--
mstr2dre_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2dre_dre_src_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the DRE --
--
mstr2dre_dre_dest_align : In std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the DRE --
--
-- mstr2dre_btt : In std_logic_vector(C_BTT_USED-1 downto 0); --
-- -- The bytes to transfer value for the input command --
--
mstr2dre_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2dre_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
-- mstr2dre_cmd_cmplt : In std_logic; --
-- -- The last tranfer command of a sequence of transfers --
-- -- spawned from a single parent command --
--
mstr2dre_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2dre_strt_offset : In std_logic_vector(C_STRT_SF_OFFSET_WIDTH-1 downto 0);--
-- Outputs the starting offset of a transfer. This is used with Store --
-- and Forward Packer/Unpacker logic --
-----------------------------------------------------------------------------------
-- MM2S DRE Control -------------------------------------------------------------
--
sf2dre_new_align : Out std_logic; --
-- Active high signal indicating new DRE aligment required --
--
sf2dre_use_autodest : Out std_logic; --
-- Active high signal indicating to the DRE to use an auto- --
-- calculated desination alignment based on the last transfer --
--
sf2dre_src_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the byte lane of the first valid data byte --
-- being sent to the DRE --
--
sf2dre_dest_align : Out std_logic_vector(C_DRE_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the desired byte lane of the first valid data byte --
-- to be output by the DRE --
--
sf2dre_flush : Out std_logic; --
-- Active high signal indicating to the DRE to flush the current --
-- contents to the output register in preparation of a new alignment --
-- that will be comming on the next transfer input --
---------------------------------------------------------------------------------
-- Stream Out -----------------------------------------------------------------------
--
sout2sf_tready : In std_logic; --
-- Write READY input from the Stream Master --
--
sf2sout_tvalid : Out std_logic; --
-- Write VALID output to the Stream Master --
--
sf2sout_tdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- Write DATA output to the Stream Master --
--
sf2sout_tkeep : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- Write DATA output to the Stream Master --
--
sf2sout_tlast : Out std_logic --
-- Write LAST output to the Stream Master --
--------------------------------------------------------------------------------------
);
end entity axi_datamover_rd_sf;
architecture implementation of axi_datamover_rd_sf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Functions ---------------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_fifo_cnt_width
--
-- Function Description:
-- simple function to set the width of the data fifo read
-- and write count outputs.
-------------------------------------------------------------------
function funct_get_fifo_cnt_width (fifo_depth : integer)
return integer is
Variable temp_width : integer := 8;
begin
if (fifo_depth = 1) then
temp_width := 1;
elsif (fifo_depth = 2) then
temp_width := 2;
elsif (fifo_depth <= 4) then
temp_width := 3;
elsif (fifo_depth <= 8) then
temp_width := 4;
elsif (fifo_depth <= 16) then
temp_width := 5;
elsif (fifo_depth <= 32) then
temp_width := 6;
elsif (fifo_depth <= 64) then
temp_width := 7;
elsif (fifo_depth <= 128) then
temp_width := 8;
elsif (fifo_depth <= 256) then
temp_width := 9;
elsif (fifo_depth <= 512) then
temp_width := 10;
elsif (fifo_depth <= 1024) then
temp_width := 11;
elsif (fifo_depth <= 2048) then
temp_width := 12;
elsif (fifo_depth <= 4096) then
temp_width := 13;
else -- assume 8192 depth
temp_width := 14;
end if;
Return (temp_width);
end function funct_get_fifo_cnt_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_wrcnt_lsrip
--
-- Function Description:
-- Calculates the ls index of the upper slice of the data fifo
-- write count needed to repesent one max burst worth of data
-- present in the fifo.
--
-------------------------------------------------------------------
function funct_get_wrcnt_lsrip (max_burst_dbeats : integer) return integer is
Variable temp_ls_index : Integer := 0;
begin
if (max_burst_dbeats <= 2) then
temp_ls_index := 1;
elsif (max_burst_dbeats <= 4) then
temp_ls_index := 2;
elsif (max_burst_dbeats <= 8) then
temp_ls_index := 3;
elsif (max_burst_dbeats <= 16) then
temp_ls_index := 4;
elsif (max_burst_dbeats <= 32) then
temp_ls_index := 5;
elsif (max_burst_dbeats <= 64) then
temp_ls_index := 6;
elsif (max_burst_dbeats <= 128) then
temp_ls_index := 7;
else
temp_ls_index := 8;
end if;
Return (temp_ls_index);
end function funct_get_wrcnt_lsrip;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_stall_thresh
--
-- Function Description:
-- Calculates the Stall threshold for the input side of the Data
-- FIFO. If DRE is being used by the DataMover, then the threshold
-- must be reduced to account for the potential of an extra write
-- databeat per request (DRE alignment dependent).
--
-------------------------------------------------------------------
function funct_get_stall_thresh (dre_is_used : integer;
max_xfer_length : integer;
data_fifo_depth : integer;
pipeline_delay_clks : integer;
fifo_settling_clks : integer) return integer is
Constant DRE_PIPE_DELAY : integer := 2; -- clks
Variable var_num_max_xfers_allowed : Integer := 0;
Variable var_dre_dbeat_overhead : Integer := 0;
Variable var_delay_fudge_factor : Integer := 0;
Variable var_thresh_headroom : Integer := 0;
Variable var_stall_thresh : Integer := 0;
begin
var_num_max_xfers_allowed := data_fifo_depth/max_xfer_length;
var_dre_dbeat_overhead := var_num_max_xfers_allowed * dre_is_used;
var_delay_fudge_factor := (dre_is_used * DRE_PIPE_DELAY) +
pipeline_delay_clks +
fifo_settling_clks;
var_thresh_headroom := max_xfer_length +
var_dre_dbeat_overhead +
var_delay_fudge_factor;
-- Scale the result to be in max transfer length increments
var_stall_thresh := (data_fifo_depth - var_thresh_headroom)/max_xfer_length;
Return (var_stall_thresh);
end function funct_get_stall_thresh;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_size_drecntl_fifo
--
-- Function Description:
-- Assures that the DRE control fifo depth is at least 4 deep else it
-- is equal to the number of max burst transfers that can fit in the
-- Store and Forward Data FIFO.
--
-------------------------------------------------------------------
function funct_size_drecntl_fifo (sf_fifo_depth : integer;
max_burst_length : integer) return integer is
Constant NEEDED_FIFO_DEPTH : integer := sf_fifo_depth/max_burst_length;
Variable temp_fifo_depth : Integer := 4;
begin
If (NEEDED_FIFO_DEPTH < 4) Then
temp_fifo_depth := 4;
Else
temp_fifo_depth := NEEDED_FIFO_DEPTH;
End if;
Return (temp_fifo_depth);
end function funct_size_drecntl_fifo;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_cntr_width
--
-- Function Description:
-- Detirmine the width needed for the address offset counter used
-- for the data fifo mux selects.
--
-------------------------------------------------------------------
function funct_get_cntr_width (num_count_states : integer) return integer is
Variable lvar_temp_width : Integer := 1;
begin
if (num_count_states <= 2) then
lvar_temp_width := 1;
elsif (num_count_states <= 4) then
lvar_temp_width := 2;
elsif (num_count_states <= 8) then
lvar_temp_width := 3;
elsif (num_count_states <= 16) then
lvar_temp_width := 4;
elsif (num_count_states <= 32) then
lvar_temp_width := 5;
elsif (num_count_states <= 64) then
lvar_temp_width := 6;
Else -- 128 cnt states
lvar_temp_width := 7;
end if;
Return (lvar_temp_width);
end function funct_get_cntr_width;
-- Constants ---------------------------------------------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BLK_MEM_FIFO : integer := 1;
Constant SRL_FIFO : integer := 0;
Constant NOT_NEEDED : integer := 0;
Constant MMAP_TKEEP_WIDTH : integer := C_MMAP_DWIDTH/8; -- bits
Constant TLAST_WIDTH : integer := 1; -- bits
Constant CMPLT_WIDTH : integer := 1; -- bits
Constant DRE_FLUSH_WIDTH : integer := 1; -- bits
Constant DATA_FIFO_DEPTH : integer := C_SF_FIFO_DEPTH;
Constant DATA_FIFO_CNT_WIDTH : integer := funct_get_fifo_cnt_width(DATA_FIFO_DEPTH);
Constant DF_WRCNT_RIP_LS_INDEX : integer := funct_get_wrcnt_lsrip(C_MAX_BURST_LEN);
Constant DATA_FIFO_WIDTH : integer := C_MMAP_DWIDTH +
MMAP_TKEEP_WIDTH*C_ENABLE_MM2S_TKEEP +
TLAST_WIDTH +
CMPLT_WIDTH +
DRE_FLUSH_WIDTH;
Constant DATA_OUT_LSB_INDEX : integer := 0;
Constant DATA_OUT_MSB_INDEX : integer := C_MMAP_DWIDTH-1;
Constant TKEEP_OUT_LSB_INDEX : integer := DATA_OUT_MSB_INDEX+1;
Constant TKEEP_OUT_MSB_INDEX : integer := (TKEEP_OUT_LSB_INDEX+MMAP_TKEEP_WIDTH*C_ENABLE_MM2S_TKEEP)-1*C_ENABLE_MM2S_TKEEP;
Constant TLAST_OUT_INDEX : integer := TKEEP_OUT_MSB_INDEX+1*C_ENABLE_MM2S_TKEEP;
Constant CMPLT_OUT_INDEX : integer := TLAST_OUT_INDEX+1;
Constant DRE_FLUSH_OUT_INDEX : integer := CMPLT_OUT_INDEX+1;
Constant TOKEN_POOL_SIZE : integer := C_SF_FIFO_DEPTH / C_MAX_BURST_LEN;
Constant TOKEN_CNTR_WIDTH : integer := clog2(TOKEN_POOL_SIZE)+1;
Constant TOKEN_CNT_ZERO : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, TOKEN_CNTR_WIDTH);
Constant TOKEN_CNT_ONE : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, TOKEN_CNTR_WIDTH);
Constant TOKEN_CNT_MAX : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(TOKEN_POOL_SIZE, TOKEN_CNTR_WIDTH);
Constant THRESH_COMPARE_WIDTH : integer := TOKEN_CNTR_WIDTH+2;
Constant RD_PATH_PIPE_DEPTH : integer := 2; -- clocks excluding DRE
Constant WRCNT_SETTLING_TIME : integer := 2; -- data fifo push or pop settling clocks
Constant DRE_COMPENSATION : integer := 0; -- DRE does not contribute since it is on
-- the output side of the Store and Forward
Constant RD_ADDR_POST_STALL_THRESH : integer :=
funct_get_stall_thresh(DRE_COMPENSATION ,
C_MAX_BURST_LEN ,
C_SF_FIFO_DEPTH ,
RD_PATH_PIPE_DEPTH ,
WRCNT_SETTLING_TIME);
Constant RD_ADDR_POST_STALL_THRESH_US : Unsigned(THRESH_COMPARE_WIDTH-1 downto 0) :=
TO_UNSIGNED(RD_ADDR_POST_STALL_THRESH ,
THRESH_COMPARE_WIDTH);
Constant UNCOM_WRCNT_1 : Unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, DATA_FIFO_CNT_WIDTH);
Constant UNCOM_WRCNT_0 : Unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) :=
TO_UNSIGNED(0, DATA_FIFO_CNT_WIDTH);
Constant USE_SYNC_FIFO : integer := 0;
Constant SRL_FIFO_PRIM : integer := 2;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SRC_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH;
Constant DEST_ALIGN_WIDTH : integer := C_DRE_ALIGN_WIDTH;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant SF_OFFSET_WIDTH : integer := C_STRT_SF_OFFSET_WIDTH;
-- Signals ---------------------------------------------------------------------------
signal sig_good_sin_strm_dbeat : std_logic := '0';
signal sig_strm_sin_ready : std_logic := '0';
signal sig_good_sout_strm_dbeat : std_logic := '0';
signal sig_sout2sf_tready : std_logic := '0';
signal sig_sf2sout_tvalid : std_logic := '0';
signal sig_sf2sout_tdata : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_sf2sout_tkeep : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_sf2sout_tlast : std_logic := '0';
signal sig_sf2dre_flush : std_logic := '0';
signal sig_push_data_fifo : std_logic := '0';
signal sig_pop_data_fifo : std_logic := '0';
signal sig_data_fifo_full : std_logic := '0';
signal sig_data_fifo_data_in : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_dvalid : std_logic := '0';
signal sig_data_fifo_data_out : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_wr_cnt : std_logic_vector(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_cnt_unsgnd : unsigned(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_wrcnt_mblen_slice : unsigned(DATA_FIFO_CNT_WIDTH-1 downto
DF_WRCNT_RIP_LS_INDEX) := (others => '0');
signal sig_ok_to_post_rd_addr : std_logic := '0';
signal sig_rd_addr_posted : std_logic := '0';
signal sig_rd_xfer_cmplt : std_logic := '0';
signal sig_taking_last_token : std_logic := '0';
signal sig_stall_rd_addr_posts : std_logic := '0';
signal sig_incr_token_cntr : std_logic := '0';
signal sig_decr_token_cntr : std_logic := '0';
signal sig_token_eq_max : std_logic := '0';
signal sig_token_eq_zero : std_logic := '0';
signal sig_token_eq_one : std_logic := '0';
signal sig_token_cntr : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_tokens_commited : Unsigned(TOKEN_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_commit_plus_actual : unsigned(THRESH_COMPARE_WIDTH-1 downto 0) := (others => '0');
signal sig_cntl_fifo_has_data : std_logic := '0';
signal sig_get_cntl_fifo_data : std_logic := '0';
signal sig_curr_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_src_align_reg : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_dest_align_reg : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_curr_drr_reg : std_logic := '0';
signal sig_curr_eof_reg : std_logic := '0';
signal sig_curr_calc_error_reg : std_logic := '0';
signal sig_curr_strt_offset_reg : std_logic_vector(SF_OFFSET_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_dre_cntl_reg : std_logic := '0';
signal sig_dfifo_data_out : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0');
signal sig_dfifo_tkeep_out : std_logic_vector(MMAP_TKEEP_WIDTH-1 downto 0) := (others => '0');
signal sig_dfifo_tlast_out : std_logic := '0';
signal sig_dfifo_cmd_cmplt_out : std_logic := '0';
signal sig_dfifo_dre_flush_out : std_logic := '0';
begin --(architecture implementation)
-- Read Side (MM2S) Control Flags port connections
ok_to_post_rd_addr <= sig_ok_to_post_rd_addr ;
sig_rd_addr_posted <= rd_addr_posted ;
sig_rd_xfer_cmplt <= rd_xfer_cmplt ;
-- Output Stream Port connections
sig_sout2sf_tready <= sout2sf_tready ;
sf2sout_tvalid <= sig_sf2sout_tvalid ;
sf2sout_tdata <= sig_sf2sout_tdata ;
--sf2sout_tkeep <= sig_sf2sout_tkeep ;
sf2sout_tlast <= sig_sf2sout_tlast and
sig_sf2sout_tvalid ;
GEN_MM2S_TKEEP_ENABLE4 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
sf2sout_tkeep <= sig_sf2sout_tkeep ;
end generate GEN_MM2S_TKEEP_ENABLE4;
GEN_MM2S_TKEEP_DISABLE4 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
sf2sout_tkeep <= (others => '1');
end generate GEN_MM2S_TKEEP_DISABLE4;
-- Input Stream port connections
sf2sin_tready <= sig_strm_sin_ready;
sig_strm_sin_ready <= not(sig_data_fifo_full); -- Throttle if Read Side Data fifo goes full.
-- This should never happen if read address
-- posting control is working properly.
-- Stream transfer qualifiers
sig_good_sin_strm_dbeat <= sin2sf_tvalid and
sig_strm_sin_ready;
sig_good_sout_strm_dbeat <= sig_sf2sout_tvalid and
sig_sout2sf_tready;
----------------------------------------------------------------
-- Unpacking Logic ------------------------------------------
----------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_UNPACKING
--
-- If Generate Description:
-- Omits any unpacking logic in the Store and Forward module.
-- The Stream and MMap data widths are the same. The Data FIFO
-- output can be connected directly to the stream outputs.
--
------------------------------------------------------------
OMIT_UNPACKING : if (C_MMAP_DWIDTH = C_STREAM_DWIDTH) generate
signal lsig_cmd_loaded : std_logic := '0';
signal lsig_ld_cmd : std_logic := '0';
signal lsig_cmd_cmplt_dbeat : std_logic := '0';
signal lsig_cmd_cmplt : std_logic := '0';
begin
-- Data FIFO Output to the stream attachments
sig_sf2sout_tvalid <= sig_data_fifo_dvalid and
lsig_cmd_loaded ;
sig_sf2sout_tdata <= sig_dfifo_data_out ;
sig_sf2sout_tkeep <= sig_dfifo_tkeep_out ;
sig_sf2sout_tlast <= sig_dfifo_tlast_out ;
sig_sf2dre_flush <= sig_dfifo_dre_flush_out ;
-- Control for reading the Data FIFO
sig_pop_data_fifo <= lsig_cmd_loaded and
sig_sout2sf_tready and
sig_data_fifo_dvalid;
-- Control for reading the Command/Offset FIFO
sig_get_cntl_fifo_data <= lsig_ld_cmd ;
-- Control for loading the DRE Control Reg
sig_ld_dre_cntl_reg <= lsig_ld_cmd ;
lsig_cmd_cmplt_dbeat <= sig_dfifo_cmd_cmplt_out and
lsig_cmd_loaded and
sig_data_fifo_dvalid and
sig_sout2sf_tready ;
-- Generate the control that loads the DRE
lsig_ld_cmd <= (sig_cntl_fifo_has_data and -- startup or gap case
not(lsig_cmd_loaded)) or
(sig_cntl_fifo_has_data and -- back to back commands
lsig_cmd_cmplt_dbeat);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_LOADED
--
-- Process Description:
-- Implements the flop indicating a command from the cmd fifo
-- has been loaded into the DRE Output Register.
--
-------------------------------------------------------------
IMP_CMD_LOADED : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_cmd_loaded <= '0';
Elsif (lsig_ld_cmd = '1' ) Then
lsig_cmd_loaded <= '1';
elsif (sig_cntl_fifo_has_data = '0' and -- No more commands queued and
lsig_cmd_cmplt_dbeat = '1') then
lsig_cmd_loaded <= '0';
else
null; -- Hold Current State
end if;
end if;
end process IMP_CMD_LOADED;
end generate OMIT_UNPACKING;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_UNPACKING
--
-- If Generate Description:
-- Includes unpacking logic in the Store and Forward module.
-- The MMap Data bus is wider than the Stream width.
--
------------------------------------------------------------
INCLUDE_UNPACKING : if (C_MMAP_DWIDTH > C_STREAM_DWIDTH) generate
Constant MMAP2STRM_WIDTH_RATO : integer := C_MMAP_DWIDTH/C_STREAM_DWIDTH;
Constant DATA_SLICE_WIDTH : integer := C_STREAM_DWIDTH;
Constant TKEEP_SLICE_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant FLAG_SLICE_WIDTH : integer := TLAST_WIDTH;
Constant OFFSET_CNTR_WIDTH : integer := funct_get_cntr_width(MMAP2STRM_WIDTH_RATO);
Constant OFFSET_CNT_ONE : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, OFFSET_CNTR_WIDTH);
Constant OFFSET_CNT_MAX : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(MMAP2STRM_WIDTH_RATO-1, OFFSET_CNTR_WIDTH);
-- Types -----------------------------------------------------------------------------
type lsig_data_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(DATA_SLICE_WIDTH-1 downto 0);
type lsig_tkeep_slice_type is array(MMAP2STRM_WIDTH_RATO downto 0) of
std_logic_vector(TKEEP_SLICE_WIDTH-1 downto 0);
type lsig_flag_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(FLAG_SLICE_WIDTH-1 downto 0);
-- local signals
signal lsig_0ffset_cntr : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_ld_offset : std_logic := '0';
signal lsig_incr_offset : std_logic := '0';
signal lsig_offset_cntr_eq_max : std_logic := '0';
signal lsig_fifo_data_out_wide : lsig_data_slice_type;
signal lsig_fifo_tkeep_out_wide : lsig_tkeep_slice_type;
signal lsig_mux_sel : integer range 0 to MMAP2STRM_WIDTH_RATO-1;
signal lsig_data_mux_out : std_logic_vector(DATA_SLICE_WIDTH-1 downto 0) ;
signal lsig_tkeep_mux_out : std_logic_vector(TKEEP_SLICE_WIDTH-1 downto 0);
signal lsig_tlast_out : std_logic := '0';
signal lsig_dre_flush_out : std_logic := '0';
signal lsig_this_fifo_wrd_done : std_logic := '0';
signal lsig_cmd_loaded : std_logic := '0';
signal lsig_cmd_cmplt_dbeat : std_logic := '0';
signal lsig_cmd_cmplt : std_logic := '0';
signal lsig_next_slice_tkeep_0 : std_logic := '0';
begin
sig_sf2sout_tvalid <= sig_data_fifo_dvalid and
lsig_cmd_loaded ;
sig_sf2sout_tdata <= lsig_data_mux_out ;
sig_sf2sout_tkeep <= lsig_tkeep_mux_out(TKEEP_SLICE_WIDTH-1 downto 0);
sig_sf2sout_tlast <= lsig_tlast_out ;
sig_sf2dre_flush <= lsig_dre_flush_out ;
-- Control for reading the Data FIFO
sig_pop_data_fifo <= lsig_this_fifo_wrd_done and
lsig_cmd_loaded and
sig_sout2sf_tready and
sig_data_fifo_dvalid;
-- Control for reading the Command/Offset FIFO
sig_get_cntl_fifo_data <= lsig_ld_offset;
-- Control for loading the DRE Control Reg
sig_ld_dre_cntl_reg <= lsig_ld_offset ;
lsig_next_slice_tkeep_0 <= lsig_fifo_tkeep_out_wide(lsig_mux_sel+1)(0);
-- Detirmine if a Command Complete condition exists
lsig_cmd_cmplt <= '1'
when (sig_dfifo_cmd_cmplt_out = '1' and
lsig_next_slice_tkeep_0 = '0')
Else '0';
-- Detirmine if a TLAST condition exists
-- From the RDC via the Data FIFO
lsig_tlast_out <= '1'
when (sig_dfifo_tlast_out = '1' and
lsig_next_slice_tkeep_0 = '0')
Else '0';
-- Detimine if a DRE Flush condition exists
-- From the RDC via the Data FIFO
lsig_dre_flush_out <= '1'
when (sig_dfifo_dre_flush_out = '1' and
lsig_next_slice_tkeep_0 = '0')
Else '0';
lsig_cmd_cmplt_dbeat <= lsig_cmd_cmplt and
lsig_cmd_loaded and
sig_data_fifo_dvalid and
sig_sout2sf_tready ;
-- Check to see if the FIFO output word is finished. This occurs
-- when the offset counter is at max value or the tlast from the
-- fifo is set and the LS TKEED of the next MS Slice is zero.
lsig_this_fifo_wrd_done <= '1'
When (lsig_offset_cntr_eq_max = '1' or
(lsig_cmd_cmplt_dbeat = '1' and
lsig_next_slice_tkeep_0 = '0'))
Else '0';
-- Generate the control that loads the starting address
-- offset for the next input packet
lsig_ld_offset <= (sig_cntl_fifo_has_data and -- startup or gap case
not(lsig_cmd_loaded)) or
(sig_cntl_fifo_has_data and -- back to back commands
lsig_cmd_cmplt_dbeat);
-- Generate the control for incrementing the offset counter
lsig_incr_offset <= sig_good_sout_strm_dbeat;
-- Check to see if the offset counter has reached its max
-- value
lsig_offset_cntr_eq_max <= '1'
when (lsig_0ffset_cntr = OFFSET_CNT_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CMD_LOADED
--
-- Process Description:
-- Implements the flop indicating a command from the cmd fifo
-- has been loaded into the unpacker control logic.
--
-------------------------------------------------------------
IMP_CMD_LOADED : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_cmd_loaded <= '0';
Elsif (lsig_ld_offset = '1' ) Then
lsig_cmd_loaded <= '1';
elsif (sig_cntl_fifo_has_data = '0' and -- No more commands queued
lsig_cmd_cmplt_dbeat = '1') then
lsig_cmd_loaded <= '0';
else
null; -- Hold Current State
end if;
end if;
end process IMP_CMD_LOADED;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_OFFSET_CNTR
--
-- Process Description:
-- Implements the address offset counter that is used to
-- generate the data and tkeep mux selects.
-- Note that the counter has to be loaded with the starting
-- offset plus one to sync up with the data input.
-------------------------------------------------------------
IMP_OFFSET_CNTR : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
lsig_0ffset_cntr <= (others => '0');
Elsif (lsig_ld_offset = '1') Then
lsig_0ffset_cntr <= UNSIGNED(sig_curr_strt_offset_reg);
elsif (lsig_incr_offset = '1') then
lsig_0ffset_cntr <= lsig_0ffset_cntr + OFFSET_CNT_ONE;
else
null; -- Hold Current State
end if;
end if;
end process IMP_OFFSET_CNTR;
------------------------------------------------------------
-- For Generate
--
-- Label: DO_DATA_CONVERTER
--
-- For Generate Description:
-- This ForGen converts the FIFO output data and tkeep from a single
-- std logic vector type to a vector of slices.
--
------------------------------------------------------------
DO_DATA_CONVERTER : for slice_index in 1 to MMAP2STRM_WIDTH_RATO generate
begin
lsig_fifo_data_out_wide(slice_index-1) <=
sig_dfifo_data_out((slice_index*DATA_SLICE_WIDTH)-1 downto
(slice_index-1)*DATA_SLICE_WIDTH);
lsig_fifo_tkeep_out_wide(slice_index-1) <=
sig_dfifo_tkeep_out((slice_index*TKEEP_SLICE_WIDTH)-1 downto
(slice_index-1)*TKEEP_SLICE_WIDTH);
end generate DO_DATA_CONVERTER;
-- Assign the extra tkeep slice to all zeros to allow for detection
-- of the data word done when the ls tkeep bit of the next tkeep
-- slice is zero and the offset count is pointing to the last slice
-- position.
lsig_fifo_tkeep_out_wide(MMAP2STRM_WIDTH_RATO) <= (others => '0');
-- Mux the appropriate data and tkeep slice to the stream output
lsig_mux_sel <= TO_INTEGER(lsig_0ffset_cntr);
lsig_data_mux_out <= lsig_fifo_data_out_wide(lsig_mux_sel) ;
lsig_tkeep_mux_out(TKEEP_SLICE_WIDTH-1 downto 0) <= lsig_fifo_tkeep_out_wide(lsig_mux_sel);
end generate INCLUDE_UNPACKING;
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_DRE_CNTL
--
-- If Generate Description:
-- This IfGen is used to omit the DRE control logic and
-- minimize the Control FIFO when MM2S DRE is not included
-- in the MM2S.
--
------------------------------------------------------------
OMIT_DRE_CNTL : if (C_DRE_IS_USED = 0) generate
-- Constant Declarations ------------------------------------------------------------------
Constant USE_SYNC_FIFO : integer := 0;
Constant SRL_FIFO_PRIM : integer := 2;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant SF_OFFSET_WIDTH : integer := C_STRT_SF_OFFSET_WIDTH;
Constant SF_OFFSET_FIFO_DEPTH : integer := funct_size_drecntl_fifo(C_DRE_CNTL_FIFO_DEPTH,
C_MAX_BURST_LEN);
Constant SF_OFFSET_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
CALC_ERR_WIDTH + -- Calc error flag
SF_OFFSET_WIDTH; -- Store and Forward Offset
Constant TAG_STRT_INDEX : integer := 0;
Constant DRR_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant SF_OFFSET_STRT_INDEX : integer := CALC_ERR_STRT_INDEX+CALC_ERR_WIDTH;
-- Signal Declarations --------------------------------------------------------------------
signal sig_offset_fifo_data_in : std_logic_vector(SF_OFFSET_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_offset_fifo_data_out : std_logic_vector(SF_OFFSET_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_offset_fifo_wr_valid : std_logic := '0';
signal sig_offset_fifo_wr_ready : std_logic := '0';
signal sig_offset_fifo_rd_valid : std_logic := '0';
signal sig_offset_fifo_rd_ready : std_logic := '0';
begin
-- PCC DRE Command interface handshake
dre2mstr_cmd_ready <= sig_offset_fifo_wr_ready ;
sig_offset_fifo_wr_valid <= mstr2dre_cmd_valid ;
-- No DRE so no controls
sf2dre_new_align <= '0';
sf2dre_use_autodest <= '0';
sf2dre_src_align <= (others => '0');
sf2dre_dest_align <= (others => '0');
sf2dre_flush <= '0';
-- No DRE so no alignment values
sig_curr_src_align_reg <= (others => '0');
sig_curr_dest_align_reg <= (others => '0');
-- Format the input data word for the Offset FIFO Queue
sig_offset_fifo_data_in <= mstr2dre_strt_offset & -- MS field
mstr2dre_calc_error &
mstr2dre_eof &
mstr2dre_drr &
mstr2dre_tag; -- LS Field
sig_cntl_fifo_has_data <= sig_offset_fifo_rd_valid ;
sig_offset_fifo_rd_ready <= sig_get_cntl_fifo_data ;
-- Rip the output fifo data word
sig_curr_tag_reg <= sig_offset_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto TAG_STRT_INDEX);
sig_curr_drr_reg <= sig_offset_fifo_data_out(DRR_STRT_INDEX);
sig_curr_eof_reg <= sig_offset_fifo_data_out(EOF_STRT_INDEX);
sig_curr_calc_error_reg <= sig_offset_fifo_data_out(CALC_ERR_STRT_INDEX);
sig_curr_strt_offset_reg <= sig_offset_fifo_data_out((SF_OFFSET_STRT_INDEX+SF_OFFSET_WIDTH)-1 downto
SF_OFFSET_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DRE_CNTL_FIFO
--
-- Description:
-- Instance for the Offset Control FIFO. This is still needed
-- by the unpacker logic to get the starting offset at the
-- begining of an input packet coming out of the Store and
-- Forward data FIFO.
--
------------------------------------------------------------
I_DRE_CNTL_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo
generic map (
C_DWIDTH => SF_OFFSET_FIFO_WIDTH ,
C_DEPTH => SF_OFFSET_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => SRL_FIFO_PRIM ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => reset ,
fifo_wr_clk => aclk ,
-- Write Side
fifo_wr_tvalid => sig_offset_fifo_wr_valid ,
fifo_wr_tready => sig_offset_fifo_wr_ready ,
fifo_wr_tdata => sig_offset_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => aclk ,
fifo_async_rd_clk => reset ,
-- Read Side
fifo_rd_tvalid => sig_offset_fifo_rd_valid ,
fifo_rd_tready => sig_offset_fifo_rd_ready ,
fifo_rd_tdata => sig_offset_fifo_data_out ,
fifo_rd_empty => open
);
end generate OMIT_DRE_CNTL;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_DRE_CNTL
--
-- If Generate Description:
-- This IfGen is used to include the DRE control logic and
-- Control FIFO when MM2S DRE is included in the MM2S.
--
--
------------------------------------------------------------
INCLUDE_DRE_CNTL : if (C_DRE_IS_USED = 1) generate
-- Constant Declarations
Constant DRECNTL_FIFO_DEPTH : integer := funct_size_drecntl_fifo(C_DRE_CNTL_FIFO_DEPTH,
C_MAX_BURST_LEN);
Constant DRECNTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SRC_ALIGN_WIDTH + -- Source align field width
DEST_ALIGN_WIDTH + -- Dest align field width
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
CALC_ERR_WIDTH + -- Calc error flag
SF_OFFSET_WIDTH; -- Store and Forward Offset
Constant TAG_STRT_INDEX : integer := 0;
Constant SRC_ALIGN_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant DEST_ALIGN_STRT_INDEX : integer := SRC_ALIGN_STRT_INDEX + SRC_ALIGN_WIDTH;
Constant DRR_STRT_INDEX : integer := DEST_ALIGN_STRT_INDEX + DEST_ALIGN_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant SF_OFFSET_STRT_INDEX : integer := CALC_ERR_STRT_INDEX+CALC_ERR_WIDTH;
signal sig_cmd_fifo_data_in : std_logic_vector(DRECNTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_fifo_data_out : std_logic_vector(DRECNTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_dre_align_ready : std_logic := '0';
signal sig_dre_align_valid_reg : std_logic := '0';
signal sig_dre_use_autodest_reg : std_logic := '0';
signal sig_dre_src_align_reg : std_logic_vector(SRC_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_dest_align_reg : std_logic_vector(DEST_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_dre_flush_reg : std_logic := '0';
begin
-- Assign the DRE Control Outputs
sf2dre_new_align <= sig_dre_align_valid_reg;
sf2dre_use_autodest <= sig_dre_use_autodest_reg;
sf2dre_src_align <= sig_dre_src_align_reg;
sf2dre_dest_align <= sig_dre_dest_align_reg;
sf2dre_flush <= sig_sf2dre_flush; -- from RDC via data FIFO
-- PCC DRE Command interface handshake
dre2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_wr_cmd_valid <= mstr2dre_cmd_valid ;
-- Format the input data word for the DRE Control FIFO Queue
sig_cmd_fifo_data_in <= mstr2dre_strt_offset &
mstr2dre_calc_error &
mstr2dre_eof &
mstr2dre_drr &
mstr2dre_dre_dest_align &
mstr2dre_dre_src_align &
mstr2dre_tag;
-- Formulate the DRE Control FIFO Read signaling
sig_cntl_fifo_has_data <= sig_fifo_rd_cmd_valid ;
sig_fifo_rd_cmd_ready <= sig_get_cntl_fifo_data ;
-- Rip the output fifo data word
sig_curr_tag_reg <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto TAG_STRT_INDEX);
sig_curr_src_align_reg <= sig_cmd_fifo_data_out((SRC_ALIGN_STRT_INDEX+SRC_ALIGN_WIDTH)-1 downto
SRC_ALIGN_STRT_INDEX);
sig_curr_dest_align_reg <= sig_cmd_fifo_data_out((DEST_ALIGN_STRT_INDEX+DEST_ALIGN_WIDTH)-1 downto
DEST_ALIGN_STRT_INDEX);
sig_curr_drr_reg <= sig_cmd_fifo_data_out(DRR_STRT_INDEX);
sig_curr_eof_reg <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_curr_calc_error_reg <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
sig_curr_strt_offset_reg <= sig_cmd_fifo_data_out((SF_OFFSET_STRT_INDEX+SF_OFFSET_WIDTH)-1 downto
SF_OFFSET_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DRE_CNTL_FIFO
--
-- Description:
-- Instance for the DRE Control FIFO
--
------------------------------------------------------------
I_DRE_CNTL_FIFO : entity axi_datamover_v5_1.axi_datamover_fifo
generic map (
C_DWIDTH => DRECNTL_FIFO_WIDTH ,
C_DEPTH => DRECNTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => SRL_FIFO_PRIM ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => reset ,
fifo_wr_clk => aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => aclk ,
fifo_async_rd_clk => reset ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => open
);
-------------------------------------------------------------------------
-- DRE Control Register
-------------------------------------------------------------------------
-- The DRE will auto-flush on a received TLAST so a commanded Flush
-- is not needed.
sig_dre_flush_reg <= '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CNTL_REG
--
-- Process Description:
-- Implements the DRE alignment Output Register.
--
-------------------------------------------------------------
IMP_CNTL_REG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
sig_dre_use_autodest_reg <= '0' ;
sig_dre_src_align_reg <= (others => '0') ;
sig_dre_dest_align_reg <= (others => '0') ;
Elsif (sig_ld_dre_cntl_reg = '1' ) Then
sig_dre_use_autodest_reg <= not(sig_curr_drr_reg) ;
sig_dre_src_align_reg <= sig_curr_src_align_reg ;
sig_dre_dest_align_reg <= sig_curr_dest_align_reg ;
Elsif (sig_good_sout_strm_dbeat = '1') Then
sig_dre_use_autodest_reg <= '0' ;
sig_dre_src_align_reg <= (others => '0') ;
sig_dre_dest_align_reg <= (others => '0') ;
else
null; -- Hold Current State
end if;
end if;
end process IMP_CNTL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DRE_CNTL_VALID_REG
--
-- Process Description:
-- Implements the DRE Alignment valid Register.
--
-------------------------------------------------------------
IMP_DRE_CNTL_VALID_REG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1') then
sig_dre_align_valid_reg <= '0' ;
Elsif (sig_ld_dre_cntl_reg = '1' ) Then
sig_dre_align_valid_reg <= '1' ;
Elsif (sig_good_sout_strm_dbeat = '1') Then
sig_dre_align_valid_reg <= '0' ;
else
null; -- Hold Current State
end if;
end if;
end process IMP_DRE_CNTL_VALID_REG;
end generate INCLUDE_DRE_CNTL;
----------------------------------------------------------------
-- Token Counter Logic
-- Predicting fifo space availability at some point in the
-- future is based on managing a virtual pool of transfer tokens.
-- A token represents 1 max length burst worth of space in the
-- Data FIFO.
----------------------------------------------------------------
-- calculate how many tokens are commited to pending transfers
sig_tokens_commited <= TOKEN_CNT_MAX - sig_token_cntr;
-- Decrement the token counter when a token is
-- borrowed
sig_decr_token_cntr <= '1'
when (sig_rd_addr_posted = '1' and
sig_token_eq_zero = '0')
else '0';
-- Increment the token counter when a
-- token is returned.
sig_incr_token_cntr <= '1'
when (sig_rd_xfer_cmplt = '1' and
sig_token_eq_max = '0')
else '0';
-- Detect when the xfer token count is at max value
sig_token_eq_max <= '1'
when (sig_token_cntr = TOKEN_CNT_MAX)
Else '0';
-- Detect when the xfer token count is at one
sig_token_eq_one <= '1'
when (sig_token_cntr = TOKEN_CNT_ONE)
Else '0';
-- Detect when the xfer token count is at zero
sig_token_eq_zero <= '1'
when (sig_token_cntr = TOKEN_CNT_ZERO)
Else '0';
-- Look ahead to see if the xfer token pool is going empty
sig_taking_last_token <= '1'
When (sig_token_eq_one = '1' and
sig_rd_addr_posted = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TOKEN_CNTR
--
-- Process Description:
-- Implements the Token counter
--
-------------------------------------------------------------
IMP_TOKEN_CNTR : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1' ) then
sig_token_cntr <= TOKEN_CNT_MAX;
elsif (sig_incr_token_cntr = '1' and
sig_decr_token_cntr = '0') then
sig_token_cntr <= sig_token_cntr + TOKEN_CNT_ONE;
elsif (sig_incr_token_cntr = '0' and
sig_decr_token_cntr = '1') then
sig_token_cntr <= sig_token_cntr - TOKEN_CNT_ONE;
else
null; -- hold current value
end if;
end if;
end process IMP_TOKEN_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TOKEN_AVAIL_FLAG
--
-- Process Description:
-- Implements the flag indicating that the AXI Read Master
-- can post a read address request on the AXI4 bus.
--
-- Read address posting can occur if:
--
-- - The write side LEN fifo is not empty.
-- - The commited plus actual Data FIFO space is less than
-- the stall threshold (a max length read burst can fit
-- in the data FIFO without overflow).
-- - The max allowed commited read count has not been reached.
--
-- The flag is cleared after each address has been posted to
-- ensure a second unauthorized post does not occur.
-------------------------------------------------------------
IMP_TOKEN_AVAIL_FLAG : process (aclk)
begin
if (aclk'event and aclk = '1') then
if (reset = '1' or
sig_rd_addr_posted = '1') then
sig_ok_to_post_rd_addr <= '0';
else
sig_ok_to_post_rd_addr <= not(sig_stall_rd_addr_posts) and -- the commited Data FIFO space is approaching full
not(sig_token_eq_zero) and -- max allowed pending reads has not been reached
not(sig_taking_last_token); -- the max allowed pending reads is about to be reached
end if;
end if;
end process IMP_TOKEN_AVAIL_FLAG;
----------------------------------------------------------------
-- Data FIFO Logic ------------------------------------------
----------------------------------------------------------------
GEN_MM2S_TKEEP_ENABLE3 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
-- FIFO Output ripping to components
sig_dfifo_data_out <= sig_data_fifo_data_out(DATA_OUT_MSB_INDEX downto
DATA_OUT_LSB_INDEX);
sig_dfifo_tkeep_out <= sig_data_fifo_data_out(TKEEP_OUT_MSB_INDEX downto
TKEEP_OUT_LSB_INDEX);
sig_dfifo_tlast_out <= sig_data_fifo_data_out(TLAST_OUT_INDEX) ;
sig_dfifo_cmd_cmplt_out <= sig_data_fifo_data_out(CMPLT_OUT_INDEX) ;
sig_dfifo_dre_flush_out <= sig_data_fifo_data_out(DRE_FLUSH_OUT_INDEX) ;
end generate GEN_MM2S_TKEEP_ENABLE3;
GEN_MM2S_TKEEP_DISABLE3 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
-- FIFO Output ripping to components
sig_dfifo_data_out <= sig_data_fifo_data_out(DATA_OUT_MSB_INDEX downto
DATA_OUT_LSB_INDEX);
sig_dfifo_tkeep_out <= (others => '1');
sig_dfifo_tlast_out <= sig_data_fifo_data_out(TLAST_OUT_INDEX) ;
sig_dfifo_cmd_cmplt_out <= sig_data_fifo_data_out(CMPLT_OUT_INDEX) ;
sig_dfifo_dre_flush_out <= sig_data_fifo_data_out(DRE_FLUSH_OUT_INDEX) ;
end generate GEN_MM2S_TKEEP_DISABLE3;
-- Stall Threshold calculations
sig_fifo_wr_cnt_unsgnd <= UNSIGNED(sig_data_fifo_wr_cnt);
sig_wrcnt_mblen_slice <= sig_fifo_wr_cnt_unsgnd(DATA_FIFO_CNT_WIDTH-1 downto
DF_WRCNT_RIP_LS_INDEX);
sig_commit_plus_actual <= RESIZE(sig_tokens_commited, THRESH_COMPARE_WIDTH) +
RESIZE(sig_wrcnt_mblen_slice, THRESH_COMPARE_WIDTH);
-- Compare the commited read space plus the actual used space against the
-- stall threshold. Assert the read address posting stall flag if the
-- threshold is met or exceeded.
sig_stall_rd_addr_posts <= '1'
when (sig_commit_plus_actual > RD_ADDR_POST_STALL_THRESH_US)
Else '0';
-- FIFO Rd/WR Controls
sig_push_data_fifo <= sig_good_sin_strm_dbeat;
-- sig_pop_data_fifo <= sig_sout2sf_tready and
-- sig_data_fifo_dvalid;
GEN_MM2S_TKEEP_ENABLE2 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
-- Concatonate the Stream inputs into the single FIFO data in value
sig_data_fifo_data_in <= data2sf_dre_flush & -- ms Field
data2sf_cmd_cmplt &
sin2sf_tlast &
sin2sf_tkeep &
sin2sf_tdata; -- ls field
end generate GEN_MM2S_TKEEP_ENABLE2;
GEN_MM2S_TKEEP_DISABLE2 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
-- Concatonate the Stream inputs into the single FIFO data in value
sig_data_fifo_data_in <= data2sf_dre_flush & -- ms Field
data2sf_cmd_cmplt &
sin2sf_tlast &
--sin2sf_tkeep &
sin2sf_tdata; -- ls field
end generate GEN_MM2S_TKEEP_DISABLE2;
------------------------------------------------------------
-- Instance: I_DATA_FIFO
--
-- Description:
-- Implements the Store and Forward data FIFO (synchronous)
--
------------------------------------------------------------
I_DATA_FIFO : entity axi_datamover_v5_1.axi_datamover_sfifo_autord
generic map (
C_DWIDTH => DATA_FIFO_WIDTH ,
C_DEPTH => DATA_FIFO_DEPTH ,
C_DATA_CNT_WIDTH => DATA_FIFO_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => NOT_NEEDED ,
C_NEED_ALMOST_FULL => NOT_NEEDED ,
C_USE_BLKMEM => BLK_MEM_FIFO ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => reset ,
SFIFO_Clk => aclk ,
SFIFO_Wr_en => sig_push_data_fifo ,
SFIFO_Din => sig_data_fifo_data_in ,
SFIFO_Rd_en => sig_pop_data_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_data_fifo_dvalid ,
SFIFO_Dout => sig_data_fifo_data_out ,
SFIFO_Full => sig_data_fifo_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => open ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => open ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => sig_data_fifo_wr_cnt ,
SFIFO_Rd_ack => open
);
end implementation;
|
mit
|
justingallagher/fpga-trace
|
design/raytracer_design.srcs/sources_1/bd/triangle_intersect/ip/triangle_intersect_tri_intersect_0_1/synth/triangle_intersect_tri_intersect_0_1.vhd
|
1
|
8024
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:hls:tri_intersect:1.0
-- IP Revision: 1605081815
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY triangle_intersect_tri_intersect_0_1 IS
PORT (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
ins_TVALID : IN STD_LOGIC;
ins_TREADY : OUT STD_LOGIC;
ins_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ins_TDEST : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ins_TKEEP : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ins_TSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ins_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ins_TLAST : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ins_TID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
outs_TVALID : OUT STD_LOGIC;
outs_TREADY : IN STD_LOGIC;
outs_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
outs_TDEST : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outs_TKEEP : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
outs_TSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
outs_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outs_TLAST : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outs_TID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END triangle_intersect_tri_intersect_0_1;
ARCHITECTURE triangle_intersect_tri_intersect_0_1_arch OF triangle_intersect_tri_intersect_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF triangle_intersect_tri_intersect_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT tri_intersect IS
PORT (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
ins_TVALID : IN STD_LOGIC;
ins_TREADY : OUT STD_LOGIC;
ins_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
ins_TDEST : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ins_TKEEP : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ins_TSTRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
ins_TUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ins_TLAST : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ins_TID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
outs_TVALID : OUT STD_LOGIC;
outs_TREADY : IN STD_LOGIC;
outs_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
outs_TDEST : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outs_TKEEP : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
outs_TSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
outs_TUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outs_TLAST : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
outs_TID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT tri_intersect;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF triangle_intersect_tri_intersect_0_1_arch: ARCHITECTURE IS "tri_intersect,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF triangle_intersect_tri_intersect_0_1_arch : ARCHITECTURE IS "triangle_intersect_tri_intersect_0_1,tri_intersect,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF triangle_intersect_tri_intersect_0_1_arch: ARCHITECTURE IS "triangle_intersect_tri_intersect_0_1,tri_intersect,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=hls,x_ipName=tri_intersect,x_ipVersion=1.0,x_ipCoreRevision=1605081815,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF ap_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 ap_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF ap_rst_n: SIGNAL IS "xilinx.com:signal:reset:1.0 ap_rst_n RST";
ATTRIBUTE X_INTERFACE_INFO OF ins_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 ins TVALID";
ATTRIBUTE X_INTERFACE_INFO OF ins_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 ins TREADY";
ATTRIBUTE X_INTERFACE_INFO OF ins_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 ins TDATA";
ATTRIBUTE X_INTERFACE_INFO OF ins_TDEST: SIGNAL IS "xilinx.com:interface:axis:1.0 ins TDEST";
ATTRIBUTE X_INTERFACE_INFO OF ins_TKEEP: SIGNAL IS "xilinx.com:interface:axis:1.0 ins TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF ins_TSTRB: SIGNAL IS "xilinx.com:interface:axis:1.0 ins TSTRB";
ATTRIBUTE X_INTERFACE_INFO OF ins_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 ins TUSER";
ATTRIBUTE X_INTERFACE_INFO OF ins_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 ins TLAST";
ATTRIBUTE X_INTERFACE_INFO OF ins_TID: SIGNAL IS "xilinx.com:interface:axis:1.0 ins TID";
ATTRIBUTE X_INTERFACE_INFO OF outs_TVALID: SIGNAL IS "xilinx.com:interface:axis:1.0 outs TVALID";
ATTRIBUTE X_INTERFACE_INFO OF outs_TREADY: SIGNAL IS "xilinx.com:interface:axis:1.0 outs TREADY";
ATTRIBUTE X_INTERFACE_INFO OF outs_TDATA: SIGNAL IS "xilinx.com:interface:axis:1.0 outs TDATA";
ATTRIBUTE X_INTERFACE_INFO OF outs_TDEST: SIGNAL IS "xilinx.com:interface:axis:1.0 outs TDEST";
ATTRIBUTE X_INTERFACE_INFO OF outs_TKEEP: SIGNAL IS "xilinx.com:interface:axis:1.0 outs TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF outs_TSTRB: SIGNAL IS "xilinx.com:interface:axis:1.0 outs TSTRB";
ATTRIBUTE X_INTERFACE_INFO OF outs_TUSER: SIGNAL IS "xilinx.com:interface:axis:1.0 outs TUSER";
ATTRIBUTE X_INTERFACE_INFO OF outs_TLAST: SIGNAL IS "xilinx.com:interface:axis:1.0 outs TLAST";
ATTRIBUTE X_INTERFACE_INFO OF outs_TID: SIGNAL IS "xilinx.com:interface:axis:1.0 outs TID";
BEGIN
U0 : tri_intersect
PORT MAP (
ap_clk => ap_clk,
ap_rst_n => ap_rst_n,
ins_TVALID => ins_TVALID,
ins_TREADY => ins_TREADY,
ins_TDATA => ins_TDATA,
ins_TDEST => ins_TDEST,
ins_TKEEP => ins_TKEEP,
ins_TSTRB => ins_TSTRB,
ins_TUSER => ins_TUSER,
ins_TLAST => ins_TLAST,
ins_TID => ins_TID,
outs_TVALID => outs_TVALID,
outs_TREADY => outs_TREADY,
outs_TDATA => outs_TDATA,
outs_TDEST => outs_TDEST,
outs_TKEEP => outs_TKEEP,
outs_TSTRB => outs_TSTRB,
outs_TUSER => outs_TUSER,
outs_TLAST => outs_TLAST,
outs_TID => outs_TID
);
END triangle_intersect_tri_intersect_0_1_arch;
|
mit
|
dhesant/elec4320
|
Lab2/ipcore_dir/bram_decoder/simulation/bmg_stim_gen.vhd
|
1
|
12323
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (12 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(12 DOWNTO 0):= hex_to_std_logic_vector("0",13);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (21 downto 0) of std_logic_vector(12 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(12 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(0,
1,
"bram_decoder.mif",
DEFAULT_DATA,
13,
22);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>22 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(4 DOWNTO 0) <= READ_ADDR(4 DOWNTO 0);
ADDRA <= READ_ADDR_INT AFTER 50 ns;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 22 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
END ARCHITECTURE;
|
mit
|
dhesant/elec4320
|
Lab2/ipcore_dir/bram_decoder/simulation/bmg_tb_synth.vhd
|
1
|
6178
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_tb_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_TB IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE BMG_TB_ARCH OF BMG_TB IS
COMPONENT bram_decoder_top
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ADDRA: STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(12 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC;
SIGNAL RESET_SYNC_R2 : STD_LOGIC;
SIGNAL RESET_SYNC_R3 : STD_LOGIC;
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
clk_buf: bufg
PORT map(
i => CLK_IN,
o => clk_in_i
);
CLKA <= clk_in_i;
RSTA <= RESET_IN;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => CLK_IN,
RST => RSTA,
ADDRA => ADDRA,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDRA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
BMG_PORT: bram_decoder_top PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
|
mit
|
justingallagher/fpga-trace
|
design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/f4229bb6/hdl/src/vhdl/axi_datamover_scc.vhd
|
18
|
47911
|
-------------------------------------------------------------------------------
-- axi_datamover_scc.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_scc.vhd
--
-- Description:
-- This file implements the DataMover Lite Master Simple Command Calculator (SCC).
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_scc is
generic (
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS address bus used for
-- Muxing/Demuxing data to/from a wider AXI4 data bus
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the width of the AXi Address Channel
C_STREAM_DWIDTH : Integer range 8 to 64 := 32;
-- Sets the width of the Native Data width that
-- is being supported by the PCC
C_MAX_BURST_LEN : Integer range 2 to 64 := 16;
-- Indicates the max allowed burst length to use for
-- AXI4 transfer calculations
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command port
C_MICRO_DMA : integer range 0 to 1 := 0;
C_TAG_WIDTH : Integer range 1 to 8 := 4
-- Sets the width of the Tag field in the input command
);
port (
-- Clock and Reset inputs -------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
---------------------------------------------------------------
-- Command Input Interface ---------------------------------------------------------
--
cmd2mstr_command : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cache2mstr_command : in std_logic_vector(7 downto 0); --
-- The next command value available from the Command FIFO/Register --
--
cmd2mstr_cmd_valid : in std_logic; --
-- Handshake bit indicating if the Command FIFO/Register has at leasdt 1 entry --
--
mst2cmd_cmd_ready : out std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
------------------------------------------------------------------------------------
-- Address Channel Controller Interface --------------------------------------------
--
mstr2addr_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : out std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
--
mstr2addr_size : out std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : out std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_user : out std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cmd_cmplt : out std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calcualtion error --
--
mstr2addr_cmd_valid : out std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : In std_logic; --
-- Indication from the Address Channel Controller that the --
-- command is being accepted --
------------------------------------------------------------------------------------
-- Data Channel Controller Interface ----------------------------------------------
--
mstr2data_tag : out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : out std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the data transfer --
--
mstr2data_last_strb : out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the data transfer --
--
mstr2data_sof : out std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : out std_logic; --
-- The endiing tranfer of a sequence of parent transfer commands --
--
mstr2data_calc_error : out std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : out std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : out std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : In std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
--
calc_error : Out std_logic --
-- Indication from the Command Calculator that a calculation --
-- error has occured. --
------------------------------------------------------------------------------------
);
end entity axi_datamover_scc;
architecture implementation of axi_datamover_scc is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_slice_width
--
-- Function Description:
-- Calculates the bits to rip from the Command BTT field to calculate
-- the LEN value output to the AXI Address Channel.
--
-------------------------------------------------------------------
function funct_get_slice_width (max_burst_len : integer) return integer is
Variable temp_slice_width : Integer := 0;
begin
case max_burst_len is
when 64 =>
temp_slice_width := 7;
when 32 =>
temp_slice_width := 6;
when 16 =>
temp_slice_width := 5;
when 8 =>
temp_slice_width := 4;
when 4 =>
temp_slice_width := 3;
when others => -- assume 16 dbeats is max LEN
temp_slice_width := 2;
end case;
Return (temp_slice_width);
end function funct_get_slice_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_btt_ls_unused (transfer_width : integer) return integer is
Variable temp_btt_ls_unused : Integer := 0; -- 8-bit stream
begin
case transfer_width is
when 64 =>
temp_btt_ls_unused := 3;
when 32 =>
temp_btt_ls_unused := 2;
when 16 =>
temp_btt_ls_unused := 1;
when others => -- assume 8-bit transfers
temp_btt_ls_unused := 0;
end case;
Return (temp_btt_ls_unused);
end function funct_get_btt_ls_unused;
-- Constant Declarations ----------------------------------------
Constant BASE_CMD_WIDTH : integer := 32; -- Bit Width of Command LS (no address)
Constant CMD_TYPE_INDEX : integer := 23;
Constant CMD_ADDR_LS_INDEX : integer := BASE_CMD_WIDTH;
Constant CMD_EOF_INDEX : integer := BASE_CMD_WIDTH-2;
Constant CMD_ADDR_MS_INDEX : integer := (C_ADDR_WIDTH+BASE_CMD_WIDTH)-1;
Constant CMD_TAG_WIDTH : integer := C_TAG_WIDTH;
Constant CMD_TAG_LS_INDEX : integer := C_ADDR_WIDTH+BASE_CMD_WIDTH;
Constant CMD_TAG_MS_INDEX : integer := (CMD_TAG_LS_INDEX+CMD_TAG_WIDTH)-1;
Constant AXI_BURST_FIXED : std_logic_vector(1 downto 0) := "00";
Constant AXI_BURST_INCR : std_logic_vector(1 downto 0) := "01";
Constant AXI_BURST_WRAP : std_logic_vector(1 downto 0) := "10";
Constant AXI_BURST_RESVD : std_logic_vector(1 downto 0) := "11";
Constant AXI_SIZE_1BYTE : std_logic_vector(2 downto 0) := "000";
Constant AXI_SIZE_2BYTE : std_logic_vector(2 downto 0) := "001";
Constant AXI_SIZE_4BYTE : std_logic_vector(2 downto 0) := "010";
Constant AXI_SIZE_8BYTE : std_logic_vector(2 downto 0) := "011";
Constant AXI_SIZE_16BYTE : std_logic_vector(2 downto 0) := "100";
Constant AXI_SIZE_32BYTE : std_logic_vector(2 downto 0) := "101";
Constant AXI_SIZE_64BYTE : std_logic_vector(2 downto 0) := "110";
Constant AXI_SIZE_128BYTE : std_logic_vector(2 downto 0) := "111";
Constant BTT_SLICE_SIZE : integer := funct_get_slice_width(C_MAX_BURST_LEN);
Constant MAX_BURST_LEN_US : unsigned(BTT_SLICE_SIZE-1 downto 0) :=
TO_UNSIGNED(C_MAX_BURST_LEN-1, BTT_SLICE_SIZE);
Constant BTT_LS_UNUSED_WIDTH : integer := funct_get_btt_ls_unused(C_STREAM_DWIDTH);
Constant CMD_BTT_WIDTH : integer := BTT_SLICE_SIZE+BTT_LS_UNUSED_WIDTH;
Constant CMD_BTT_LS_INDEX : integer := 0;
Constant CMD_BTT_MS_INDEX : integer := CMD_BTT_WIDTH-1;
Constant BTT_ZEROS : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
Constant BTT_RESIDUE_ZEROS : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
Constant BTT_SLICE_ONE : unsigned(BTT_SLICE_SIZE-1 downto 0) := TO_UNSIGNED(1, BTT_SLICE_SIZE);
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8; -- Number of bytes in the Stream
Constant LEN_WIDTH : integer := 8;
-- Type Declarations --------------------------------------------
type SCC_SM_STATE_TYPE is (
INIT,
POP_RECOVER,
GET_NXT_CMD,
CHK_AND_CALC,
PUSH_TO_AXI,
ERROR_TRAP
);
-- Signal Declarations --------------------------------------------
signal sm_scc_state : SCC_SM_STATE_TYPE := INIT;
signal sm_scc_state_ns : SCC_SM_STATE_TYPE := INIT;
signal sm_pop_input_cmd : std_logic := '0';
signal sm_pop_input_cmd_ns : std_logic := '0';
signal sm_set_push2axi : std_logic := '0';
signal sm_set_push2axi_ns : std_logic := '0';
signal sm_set_error : std_logic := '0';
signal sm_set_error_ns : std_logic := '0';
Signal sm_scc_sm_ready : std_logic := '0';
Signal sm_scc_sm_ready_ns : std_logic := '0';
signal sig_cmd2data_valid : std_logic := '0';
signal sig_clr_cmd2data_valid : std_logic := '0';
signal sig_cmd2addr_valid : std_logic := '0';
signal sig_clr_cmd2addr_valid : std_logic := '0';
signal sig_addr_data_rdy_pending : std_logic := '0';
signal sig_cmd_btt_slice : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_load_input_cmd : std_logic := '0';
signal sig_cmd_reg_empty : std_logic := '0';
signal sig_cmd_reg_full : std_logic := '0';
signal sig_cmd_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_btt_reg : std_logic_vector(CMD_BTT_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_type_reg : std_logic := '0';
signal sig_cmd_burst_reg : std_logic_vector (1 downto 0) := "00";
signal sig_cmd_tag_reg : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_data_rdy4cmd : std_logic := '0';
signal sig_btt_raw : std_logic := '0';
signal sig_btt_is_zero : std_logic := '0';
signal sig_btt_is_zero_reg : std_logic := '0';
signal sig_next_tag : std_logic_vector(CMD_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_next_len : std_logic_vector(LEN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_next_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_next_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_strt_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_next_end_strb : std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0) := (others => '0');
signal sig_input_eof_reg : std_logic;
begin --(architecture implementation)
-- Assign calculation error output
calc_error <= sm_set_error;
-- Assign the ready output to the Command FIFO
mst2cmd_cmd_ready <= sig_cmd_reg_empty and sm_scc_sm_ready;
-- Assign the Address Channel Controller Qualifiers
mstr2addr_tag <= sig_next_tag ;
mstr2addr_addr <= sig_next_addr ;
mstr2addr_len <= sig_next_len ;
mstr2addr_size <= sig_next_size ;
mstr2addr_burst <= sig_cmd_burst_reg;
mstr2addr_cache <= sig_next_cache;
mstr2addr_user <= sig_next_user;
mstr2addr_cmd_valid <= sig_cmd2addr_valid;
mstr2addr_calc_error <= sm_set_error ;
mstr2addr_cmd_cmplt <= '1' ; -- Lite mode is always 1
-- Assign the Data Channel Controller Qualifiers
mstr2data_tag <= sig_next_tag ;
mstr2data_saddr_lsb <= sig_cmd_addr_reg(C_SEL_ADDR_WIDTH-1 downto 0);
mstr2data_len <= sig_next_len ;
mstr2data_strt_strb <= sig_next_strt_strb;
mstr2data_last_strb <= sig_next_end_strb;
mstr2data_sof <= '1'; -- Lite mode is always 1 cmd
mstr2data_eof <= sig_input_eof_reg; -- Lite mode is always 1 cmd
mstr2data_cmd_cmplt <= '1'; -- Lite mode is always 1 cmd
mstr2data_cmd_valid <= sig_cmd2data_valid;
mstr2data_calc_error <= sm_set_error;
-- Internal logic ------------------------------
sig_addr_data_rdy_pending <= sig_cmd2addr_valid or
sig_cmd2data_valid;
sig_clr_cmd2data_valid <= sig_cmd2data_valid and data2mstr_cmd_ready;
sig_clr_cmd2addr_valid <= sig_cmd2addr_valid and addr2mstr_cmd_ready;
sig_load_input_cmd <= cmd2mstr_cmd_valid and
sig_cmd_reg_empty and
sm_scc_sm_ready;
sig_next_tag <= sig_cmd_tag_reg;
sig_next_addr <= sig_cmd_addr_reg;
sig_addr_data_rdy4cmd <= addr2mstr_cmd_ready and data2mstr_cmd_ready;
sig_cmd_btt_slice <= cmd2mstr_command(CMD_BTT_MS_INDEX downto CMD_BTT_LS_INDEX);
sig_btt_is_zero <= '1'
when (sig_cmd_btt_slice = BTT_ZEROS)
Else '0';
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_NO_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH = 0) generate
-- signals
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
sig_next_len <= STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto 0));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value,
-- otheriwse subtract 1 from the BTT ripped value
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1;
end generate GEN_NO_RESIDUE_BITS;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_HAS_RESIDUE_BITS
--
-- If Generate Description:
--
--
--
------------------------------------------------------------
GEN_HAS_RESIDUE_BITS : if (BTT_LS_UNUSED_WIDTH > 0) generate
-- signals
signal sig_btt_len_residue : unsigned(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_len_btt_slice : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len_btt_slice_minus_1 : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
signal sig_len2use : unsigned(BTT_SLICE_SIZE-1 downto 0) := (others => '0');
begin
-- LEN Calculation logic ------------------------------------------
sig_next_len <= STD_LOGIC_VECTOR(RESIZE(sig_len2use, LEN_WIDTH));
sig_len_btt_slice <= UNSIGNED(sig_cmd_btt_reg(CMD_BTT_MS_INDEX downto BTT_LS_UNUSED_WIDTH));
sig_len_btt_slice_minus_1 <= sig_len_btt_slice-BTT_SLICE_ONE
when sig_btt_is_zero_reg = '0'
else (others => '0'); -- clip at zero
sig_btt_len_residue <= UNSIGNED(sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0));
-- If most significant bit of BTT set then limit to
-- Max Burst Len, else rip it from the BTT value
-- However if residue bits are zeroes then subtract
-- 1 from the BTT ripped value
sig_len2use <= MAX_BURST_LEN_US
When (sig_cmd_btt_reg(CMD_BTT_MS_INDEX) = '1')
Else sig_len_btt_slice_minus_1
when (sig_btt_len_residue = BTT_RESIDUE_ZEROS)
Else sig_len_btt_slice;
end generate GEN_HAS_RESIDUE_BITS;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_INPUT_CMD
--
-- Process Description:
-- Implements the input command holding registers
--
-------------------------------------------------------------
REG_INPUT_CMD : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sm_pop_input_cmd = '1') then
sig_cmd_btt_reg <= (others => '0');
sig_cmd_type_reg <= '0';
sig_cmd_addr_reg <= (others => '0');
sig_cmd_tag_reg <= (others => '0');
sig_btt_is_zero_reg <= '0';
sig_cmd_reg_empty <= '1';
sig_cmd_reg_full <= '0';
sig_input_eof_reg <= '0';
sig_cmd_burst_reg <= "00";
elsif (sig_load_input_cmd = '1') then
sig_cmd_btt_reg <= sig_cmd_btt_slice;
sig_cmd_type_reg <= cmd2mstr_command(CMD_TYPE_INDEX);
sig_cmd_addr_reg <= cmd2mstr_command(CMD_ADDR_MS_INDEX downto CMD_ADDR_LS_INDEX);
sig_cmd_tag_reg <= cmd2mstr_command(CMD_TAG_MS_INDEX downto CMD_TAG_LS_INDEX);
sig_btt_is_zero_reg <= sig_btt_is_zero;
sig_cmd_reg_empty <= '0';
sig_cmd_reg_full <= '1';
sig_cmd_burst_reg <= sig_next_burst;
if (C_MICRO_DMA = 1) then
sig_input_eof_reg <= cmd2mstr_command(CMD_EOF_INDEX);
else
sig_input_eof_reg <= '1';
end if;
else
null; -- Hold current State
end if;
end if;
end process REG_INPUT_CMD;
-- Only Incrementing Burst type supported (per Interface_X guidelines)
sig_next_burst <= AXI_BURST_INCR when (cmd2mstr_command(CMD_TYPE_INDEX) = '1') else
AXI_BURST_FIXED;
sig_next_user <= cache2mstr_command (7 downto 4);
sig_next_cache <= cache2mstr_command (3 downto 0);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_64
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 64-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_64 : if (C_STREAM_DWIDTH = 64) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_8BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 3;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0');
-- note 1 extra bit implied
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_8bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 64 bits wide and 8 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_8bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "0001" =>
sig_last_strb <= "00000001";
when "0010" =>
sig_last_strb <= "00000011";
when "0011" =>
sig_last_strb <= "00000111";
when "0100" =>
sig_last_strb <= "00001111";
when "0101" =>
sig_last_strb <= "00011111";
when "0110" =>
sig_last_strb <= "00111111";
when "0111" =>
sig_last_strb <= "01111111";
when others =>
sig_last_strb <= "11111111";
end case;
end process IMP_LAST_STRB_8bit;
end generate GEN_LEN_SDWIDTH_64;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_32
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 32-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_32 : if (C_STREAM_DWIDTH = 32) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_4BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 2;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_4bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 32 bits wide and 4 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_4bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "001" =>
sig_last_strb <= "0001";
when "010" =>
sig_last_strb <= "0011";
when "011" =>
sig_last_strb <= "0111";
when others =>
sig_last_strb <= "1111";
end case;
end process IMP_LAST_STRB_4bit;
end generate GEN_LEN_SDWIDTH_32;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_16
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 16-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_16 : if (C_STREAM_DWIDTH = 16) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_2BYTE;
Constant RESIDUE_BIT_WIDTH : integer := 1;
-- local signals
signal sig_last_strb2use : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0) := (others => '0');
Signal sig_btt_ms_bit_value : std_logic := '0';
signal sig_btt_len_residue_composite : std_logic_vector(RESIDUE_BIT_WIDTH downto 0) := (others => '0'); -- 1 extra bit
signal lsig_btt_len_residue : std_logic_vector(BTT_LS_UNUSED_WIDTH-1 downto 0) := (others => '0');
begin
-- Assign the Address Channel Controller Size Qualifier Value
sig_next_size <= AXI_SIZE2USE;
-- Assign the Strobe Values
sig_next_strt_strb <= (others => '1'); -- always aligned on first databeat for LITE DataMover
sig_next_end_strb <= sig_last_strb;
-- Local calculations ------------------------------
lsig_btt_len_residue <= sig_cmd_btt_reg(BTT_LS_UNUSED_WIDTH-1 downto 0);
sig_btt_ms_bit_value <= sig_cmd_btt_reg(CMD_BTT_MS_INDEX);
sig_btt_len_residue_composite <= sig_btt_ms_bit_value &
lsig_btt_len_residue;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: IMP_LAST_STRB_2bit
--
-- Process Description:
-- Generates the Strobe values for the LAST databeat of the
-- Burst to MMap when the Stream is 16 bits wide and 2 strobe
-- bits are required.
--
-------------------------------------------------------------
IMP_LAST_STRB_2bit : process (sig_btt_len_residue_composite)
begin
case sig_btt_len_residue_composite is
when "01" =>
sig_last_strb <= "01";
when others =>
sig_last_strb <= "11";
end case;
end process IMP_LAST_STRB_2bit;
end generate GEN_LEN_SDWIDTH_16;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LEN_SDWIDTH_8
--
-- If Generate Description:
-- This IfGen implements the AXI LEN qualifier calculation
-- and the Stream data channel start/end STRB value.
--
-- This IfGen is for the 8-bit Stream data Width case.
--
------------------------------------------------------------
GEN_LEN_SDWIDTH_8 : if (C_STREAM_DWIDTH = 8) generate
-- Local Constants
Constant AXI_SIZE2USE : std_logic_vector(2 downto 0) := AXI_SIZE_1BYTE;
begin
-- Assign the Address Channel Controller Qualifiers
sig_next_size <= AXI_SIZE2USE;
-- Assign the Data Channel Controller Qualifiers
sig_next_strt_strb <= (others => '1');
sig_next_end_strb <= (others => '1');
end generate GEN_LEN_SDWIDTH_8;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2DATA_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Ready control
-- to the Data Controller Module.
--
-------------------------------------------------------------
CMD2DATA_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_cmd2data_valid = '1') then
sig_cmd2data_valid <= '0';
elsif (sm_set_push2axi_ns = '1') then
sig_cmd2data_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2DATA_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: CMD2ADDR_VALID_FLOP
--
-- Process Description:
-- Implements the set/reset flop for the Command Ready control
-- to the Address Controller Module.
--
-------------------------------------------------------------
CMD2ADDR_VALID_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_cmd2addr_valid = '1') then
sig_cmd2addr_valid <= '0';
elsif (sm_set_push2axi_ns = '1') then
sig_cmd2addr_valid <= '1';
else
null; -- hold current state
end if;
end if;
end process CMD2ADDR_VALID_FLOP;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: SCC_SM_COMB
--
-- Process Description:
-- Implements combinational portion of state machine
--
-------------------------------------------------------------
SCC_SM_COMB : process (sm_scc_state,
cmd2mstr_cmd_valid,
sig_addr_data_rdy_pending,
sig_cmd_reg_full,
sig_btt_is_zero_reg
)
begin
-- Set default State machine outputs
sm_pop_input_cmd_ns <= '0';
sm_set_push2axi_ns <= '0';
sm_scc_state_ns <= sm_scc_state;
sm_set_error_ns <= '0';
sm_scc_sm_ready_ns <= '1';
case sm_scc_state is
----------------------------------------------------
when INIT =>
-- if (sig_addr_data_rdy4cmd = '1') then
if (cmd2mstr_cmd_valid = '1') then -- wait for first cmd valid after reset
sm_scc_state_ns <= GET_NXT_CMD; -- jump to get command
else
sm_scc_sm_ready_ns <= '0';
sm_scc_state_ns <= INIT; -- Stay in Init
End if;
----------------------------------------------------
when POP_RECOVER =>
sm_scc_state_ns <= GET_NXT_CMD; -- jump to next state
----------------------------------------------------
when GET_NXT_CMD =>
if (sig_cmd_reg_full = '1') then
sm_scc_state_ns <= CHK_AND_CALC; -- jump to next state
else
sm_scc_state_ns <= GET_NXT_CMD; -- stay in this state
end if;
----------------------------------------------------
when CHK_AND_CALC =>
sm_set_push2axi_ns <= '1'; -- Push the command to ADDR and DATA
if (sig_btt_is_zero_reg = '1') then
sm_scc_state_ns <= ERROR_TRAP; -- jump to error trap
sm_set_error_ns <= '1'; -- Set internal error flag
else
sm_scc_state_ns <= PUSH_TO_AXI;
end if;
----------------------------------------------------
when PUSH_TO_AXI =>
if (sig_addr_data_rdy_pending = '1') then
sm_scc_state_ns <= PUSH_TO_AXI; -- stay in this state
-- until both Addr and Data have taken commands
else
sm_pop_input_cmd_ns <= '1';
sm_scc_state_ns <= POP_RECOVER; -- jump back to fetch new cmd input
end if;
----------------------------------------------------
when ERROR_TRAP =>
sm_scc_state_ns <= ERROR_TRAP; -- stay in this state
sm_set_error_ns <= '1';
----------------------------------------------------
when others =>
sm_scc_state_ns <= INIT; -- error so always jump to init state
end case;
end process SCC_SM_COMB;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SCC_SM_REG
--
-- Process Description:
-- Implements registered portion of state machine
--
-------------------------------------------------------------
SCC_SM_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sm_scc_state <= INIT;
sm_pop_input_cmd <= '0' ;
sm_set_push2axi <= '0' ;
sm_set_error <= '0' ;
sm_scc_sm_ready <= '0' ;
else
sm_scc_state <= sm_scc_state_ns ;
sm_pop_input_cmd <= sm_pop_input_cmd_ns ;
sm_set_push2axi <= sm_set_push2axi_ns ;
sm_set_error <= sm_set_error_ns ;
sm_scc_sm_ready <= sm_scc_sm_ready_ns ;
end if;
end if;
end process SCC_SM_REG;
end implementation;
|
mit
|
justingallagher/fpga-trace
|
hls/triangle_intersect/tri_intersect/impl/ip/tmp.srcs/sources_1/ip/tri_intersect_ap_fsub_7_full_dsp_32/xbip_dsp48_wrapper_v3_0/hdl/xbip_dsp48_wrapper_v3_0_vh_rfs.vhd
|
9
|
142019
|
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 103392)
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`protect end_protected
|
mit
|
justingallagher/fpga-trace
|
hls/triangle_intersect/tri_intersect/impl/vhdl/project.srcs/sources_1/ip/tri_intersect_ap_fsub_7_full_dsp_32/mult_gen_v12_0/hdl/mult_gen_v12_0.vhd
|
13
|
9504
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5296)
`protect data_block
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`protect end_protected
|
mit
|
justingallagher/fpga-trace
|
hls/triangle_intersect/tri_intersect/impl/ip/tmp.srcs/sources_1/ip/tri_intersect_ap_fadd_7_full_dsp_32/xbip_utils_v3_0/hdl/xbip_utils_v3_0_vh_rfs.vhd
|
13
|
153715
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 112048)
`protect data_block
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`protect end_protected
|
mit
|
justingallagher/fpga-trace
|
hls/triangle_intersect/tri_intersect/impl/vhdl/project.srcs/sources_1/ip/tri_intersect_ap_fdiv_28_no_dsp_32/xbip_bram18k_v3_0/hdl/xbip_bram18k_v3_0_vh_rfs.vhd
|
13
|
96005
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 69328)
`protect data_block
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`protect end_protected
|
mit
|
justingallagher/fpga-trace
|
design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/0728269d/hdl/src/vhdl/axi_dma_s2mm_sts_mngr.vhd
|
3
|
11859
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_sts_mngr.vhd
-- Description: This entity mangages 'halt' and 'idle' status for the S2MM
-- channel
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_sts_mngr is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- system state --
s2mm_run_stop : in std_logic ; --
s2mm_ftch_idle : in std_logic ; --
s2mm_updt_idle : in std_logic ; --
s2mm_cmnd_idle : in std_logic ; --
s2mm_sts_idle : in std_logic ; --
--
-- stop and halt control/status --
s2mm_stop : in std_logic ; --
s2mm_halt_cmplt : in std_logic ; --
--
-- system control --
s2mm_all_idle : out std_logic ; --
s2mm_halted_clr : out std_logic ; --
s2mm_halted_set : out std_logic ; --
s2mm_idle_set : out std_logic ; --
s2mm_idle_clr : out std_logic --
);
end axi_dma_s2mm_sts_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_sts_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal all_is_idle : std_logic := '0';
signal all_is_idle_d1 : std_logic := '0';
signal all_is_idle_re : std_logic := '0';
signal all_is_idle_fe : std_logic := '0';
signal s2mm_datamover_idle : std_logic := '0';
signal s2mm_halt_cmpt_d1_cdc_tig : std_logic := '0';
signal s2mm_halt_cmpt_cdc_d2 : std_logic := '0';
signal s2mm_halt_cmpt_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF s2mm_halt_cmpt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_halt_cmpt_cdc_d2 : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- all is idle when all is idle
all_is_idle <= s2mm_ftch_idle
and s2mm_updt_idle
and s2mm_cmnd_idle
and s2mm_sts_idle;
s2mm_all_idle <= all_is_idle;
-------------------------------------------------------------------------------
-- For data mover halting look at halt complete to determine when halt
-- is done and datamover has completly halted. If datamover not being
-- halted then can ignore flag thus simply flag as idle.
-------------------------------------------------------------------------------
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Double register to secondary clock domain. This is sufficient
-- because halt_cmplt will remain asserted until detected in
-- reset module in secondary clock domain.
REG_TO_SECONDARY : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_halt_cmplt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s2mm_halt_cmpt_cdc_d2,
scndry_vect_out => open
);
-- REG_TO_SECONDARY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
---- if(m_axi_sg_aresetn = '0')then
---- s2mm_halt_cmpt_d1_cdc_tig <= '0';
---- s2mm_halt_cmpt_d2 <= '0';
---- else
-- s2mm_halt_cmpt_d1_cdc_tig <= s2mm_halt_cmplt;
-- s2mm_halt_cmpt_cdc_d2 <= s2mm_halt_cmpt_d1_cdc_tig;
---- end if;
-- end if;
-- end process REG_TO_SECONDARY;
s2mm_halt_cmpt_d2 <= s2mm_halt_cmpt_cdc_d2;
end generate GEN_FOR_ASYNC;
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- No clock crossing required therefore simple pass through
s2mm_halt_cmpt_d2 <= s2mm_halt_cmplt;
end generate GEN_FOR_SYNC;
s2mm_datamover_idle <= '1' when (s2mm_stop = '1' and s2mm_halt_cmpt_d2 = '1')
or (s2mm_stop = '0')
else '0';
-------------------------------------------------------------------------------
-- Set halt bit if run/stop cleared and all processes are idle
-------------------------------------------------------------------------------
HALT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_halted_set <= '0';
elsif(s2mm_run_stop = '0' and all_is_idle = '1' and s2mm_datamover_idle = '1')then
s2mm_halted_set <= '1';
else
s2mm_halted_set <= '0';
end if;
end if;
end process HALT_PROCESS;
-------------------------------------------------------------------------------
-- Clear halt bit if run/stop is set and SG engine begins to fetch descriptors
-------------------------------------------------------------------------------
NOT_HALTED_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_halted_clr <= '0';
elsif(s2mm_run_stop = '1')then
s2mm_halted_clr <= '1';
else
s2mm_halted_clr <= '0';
end if;
end if;
end process NOT_HALTED_PROCESS;
-------------------------------------------------------------------------------
-- Register ALL is Idle to create rising and falling edges on idle flag
-------------------------------------------------------------------------------
IDLE_REG_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
all_is_idle_d1 <= '0';
else
all_is_idle_d1 <= all_is_idle;
end if;
end if;
end process IDLE_REG_PROCESS;
all_is_idle_re <= all_is_idle and not all_is_idle_d1;
all_is_idle_fe <= not all_is_idle and all_is_idle_d1;
-- Set or Clear IDLE bit in DMASR
s2mm_idle_set <= all_is_idle_re and s2mm_run_stop;
s2mm_idle_clr <= all_is_idle_fe;
end implementation;
|
mit
|
justingallagher/fpga-trace
|
design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_dma_v7_1/0728269d/hdl/src/vhdl/axi_dma_cmd_split.vhd
|
1
|
22804
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
entity axi_dma_cmd_split is
generic (
C_ADDR_WIDTH : integer range 32 to 64 := 32;
C_DM_STATUS_WIDTH : integer range 8 to 32 := 8;
C_INCLUDE_S2MM : integer range 0 to 1 := 0
);
port (
clock : in std_logic;
sgresetn : in std_logic;
clock_sec : in std_logic;
aresetn : in std_logic;
-- command coming from _MNGR
s_axis_cmd_tvalid : in std_logic;
s_axis_cmd_tready : out std_logic;
s_axis_cmd_tdata : in std_logic_vector ((C_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0);
-- split command to DM
s_axis_cmd_tvalid_s : out std_logic;
s_axis_cmd_tready_s : in std_logic;
s_axis_cmd_tdata_s : out std_logic_vector ((C_ADDR_WIDTH+CMD_BASE_WIDTH+8)-1 downto 0);
-- Tvalid from Datamover
tvalid_from_datamover : in std_logic;
status_in : in std_logic_vector (C_DM_STATUS_WIDTH-1 downto 0);
tvalid_unsplit : out std_logic;
status_out : out std_logic_vector (C_DM_STATUS_WIDTH-1 downto 0);
-- Tlast of stream data from Datamover
tlast_stream_data : in std_logic;
tready_stream_data : in std_logic;
tlast_unsplit : out std_logic;
tlast_unsplit_user : out std_logic
);
end entity axi_dma_cmd_split;
architecture implementation of axi_dma_cmd_split is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
type SPLIT_MM2S_STATE_TYPE is (
IDLE,
SEND,
SPLIT
);
signal mm2s_cs : SPLIT_MM2S_STATE_TYPE;
signal mm2s_ns : SPLIT_MM2S_STATE_TYPE;
signal mm2s_cmd : std_logic_vector (C_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46-1 downto 0);
signal command_ns : std_logic_vector (C_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH-1 downto 0);
signal command : std_logic_vector (C_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH-1 downto 0);
signal cache_info : std_logic_vector (31 downto 0);
signal vsize_data : std_logic_vector (22 downto 0);
signal vsize_data_int : std_logic_vector (22 downto 0);
signal vsize : std_logic_vector (22 downto 0);
signal counter : std_logic_vector (22 downto 0);
signal counter_tlast : std_logic_vector (22 downto 0);
signal split_cmd : std_logic_vector (31+(C_ADDR_WIDTH-32) downto 0);
signal stride_data : std_logic_vector (22 downto 0);
signal vsize_over : std_logic;
signal cmd_proc_cdc_from : std_logic;
signal cmd_proc_cdc_to : std_logic;
signal cmd_proc_cdc : std_logic;
signal cmd_proc_ns : std_logic;
ATTRIBUTE async_reg : STRING;
-- ATTRIBUTE async_reg OF cmd_proc_cdc_to : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF cmd_proc_cdc : SIGNAL IS "true";
signal cmd_out : std_logic;
signal cmd_out_ns : std_logic;
signal split_out : std_logic;
signal split_out_ns : std_logic;
signal command_valid : std_logic;
signal command_valid_ns : std_logic;
signal command_ready : std_logic;
signal reset_lock : std_logic;
signal reset_lock_tlast : std_logic;
signal tvalid_unsplit_int : std_logic;
signal tlast_stream_data_int : std_logic;
signal ready_for_next_cmd : std_logic;
signal ready_for_next_cmd_tlast : std_logic;
signal ready_for_next_cmd_tlast_cdc_from : std_logic;
signal ready_for_next_cmd_tlast_cdc_to : std_logic;
signal ready_for_next_cmd_tlast_cdc : std_logic;
-- ATTRIBUTE async_reg OF ready_for_next_cmd_tlast_cdc_to : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF ready_for_next_cmd_tlast_cdc : SIGNAL IS "true";
signal tmp1, tmp2, tmp3, tmp4 : std_logic;
signal tlast_int : std_logic;
signal eof_bit : std_logic;
signal eof_bit_cdc_from : std_logic;
signal eof_bit_cdc_to : std_logic;
signal eof_bit_cdc : std_logic;
signal eof_set : std_logic;
signal over_ns, over : std_logic;
signal cmd_in : std_logic;
signal status_out_int : std_logic_vector (C_DM_STATUS_WIDTH-1 downto 0);
begin
s_axis_cmd_tvalid_s <= command_valid;
command_ready <= s_axis_cmd_tready_s;
s_axis_cmd_tdata_s <= command (103+(C_ADDR_WIDTH-32) downto 96+(C_ADDR_WIDTH-32)) & command (71+(C_ADDR_WIDTH-32) downto 0);
REGISTER_STATE_MM2S : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
mm2s_cs <= IDLE;
cmd_proc_cdc_from <= '0';
cmd_out <= '0';
command <= (others => '0');
command_valid <= '0';
split_out <= '0';
over <= '0';
else
mm2s_cs <= mm2s_ns;
cmd_proc_cdc_from <= cmd_proc_ns;
cmd_out <= cmd_out_ns;
command <= command_ns;
command_valid <= command_valid_ns;
split_out <= split_out_ns;
over <= over_ns;
end if;
end if;
end process REGISTER_STATE_MM2S;
-- grab the MM2S command coming from MM2S_mngr
REGISTER_MM2S_CMD : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
mm2s_cmd <= (others => '0');
s_axis_cmd_tready <= '0';
cache_info <= (others => '0');
vsize_data <= (others => '0');
vsize_data_int <= (others => '0');
stride_data <= (others => '0');
eof_bit_cdc_from <= '0';
cmd_in <= '0';
elsif (s_axis_cmd_tvalid = '1' and ready_for_next_cmd = '1' and cmd_proc_cdc_from = '0' and ready_for_next_cmd_tlast_cdc = '1') then -- when there is no processing being done, means it is ready to accept
mm2s_cmd <= s_axis_cmd_tdata;
s_axis_cmd_tready <= '1';
cache_info <= s_axis_cmd_tdata (149+(C_ADDR_WIDTH-32) downto 118+(C_ADDR_WIDTH-32));
vsize_data <= s_axis_cmd_tdata (117+(C_ADDR_WIDTH-32) downto 95+(C_ADDR_WIDTH-32));
vsize_data_int <= s_axis_cmd_tdata (117+(C_ADDR_WIDTH-32) downto 95+(C_ADDR_WIDTH-32)) - '1';
stride_data <= s_axis_cmd_tdata (94+(C_ADDR_WIDTH-32) downto 72+(C_ADDR_WIDTH-32));
eof_bit_cdc_from <= s_axis_cmd_tdata (30);
cmd_in <= '1';
else
mm2s_cmd <= mm2s_cmd; --split_cmd;
vsize_data <= vsize_data;
vsize_data_int <= vsize_data_int;
stride_data <= stride_data;
cache_info <= cache_info;
s_axis_cmd_tready <= '0';
eof_bit_cdc_from <= eof_bit_cdc_from;
cmd_in <= '0';
end if;
end if;
end process REGISTER_MM2S_CMD;
REGISTER_DECR_VSIZE : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
vsize <= "00000000000000000000000";
elsif (command_valid = '1' and command_ready = '1' and (vsize < vsize_data_int)) then -- sending a cmd out to DM
vsize <= vsize + '1';
elsif (cmd_proc_cdc_from = '0') then -- idle or when all cmd are sent to DM
vsize <= "00000000000000000000000";
else
vsize <= vsize;
end if;
end if;
end process REGISTER_DECR_VSIZE;
vsize_over <= '1' when (vsize = vsize_data_int) else '0';
-- eof_set <= eof_bit when (vsize = vsize_data_int) else '0';
REGISTER_SPLIT : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
split_cmd <= (others => '0');
elsif (s_axis_cmd_tvalid = '1' and cmd_proc_cdc_from = '0' and ready_for_next_cmd = '1' and ready_for_next_cmd_tlast_cdc = '1') then
split_cmd <= s_axis_cmd_tdata (63+(C_ADDR_WIDTH-32) downto 32); -- capture the ba when a new cmd arrives
elsif (split_out = '1') then -- add stride to previous ba
split_cmd <= split_cmd + stride_data;
else
split_cmd <= split_cmd;
end if;
end if;
end process REGISTER_SPLIT;
MM2S_MACHINE : process(mm2s_cs,
s_axis_cmd_tvalid,
cmd_proc_cdc_from,
vsize_over, command_ready,
cache_info, mm2s_cmd,
split_cmd, eof_set,
cmd_in, command
)
begin
over_ns <= '0';
cmd_proc_ns <= '0'; -- ready to receive new command
split_out_ns <= '0';
command_valid_ns <= '0';
mm2s_ns <= mm2s_cs;
command_ns <= command;
-- Default signal assignment
case mm2s_cs is
-------------------------------------------------------------------
when IDLE =>
command_ns <= cache_info & mm2s_cmd (72+(C_ADDR_WIDTH-32) downto 65+(C_ADDR_WIDTH-32)) & split_cmd & mm2s_cmd (31) & eof_set & mm2s_cmd (29 downto 0); -- buf length remains the same
-- command_ns <= cache_info & mm2s_cmd (72 downto 65) & split_cmd & mm2s_cmd (31 downto 0); -- buf length remains the same
if (cmd_in = '1' and cmd_proc_cdc_from = '0') then
cmd_proc_ns <= '1'; -- new command has come in and i need to start processing
mm2s_ns <= SEND;
over_ns <= '0';
split_out_ns <= '1';
command_valid_ns <= '1';
else
mm2s_ns <= IDLE;
over_ns <= '0';
cmd_proc_ns <= '0'; -- ready to receive new command
split_out_ns <= '0';
command_valid_ns <= '0';
end if;
-------------------------------------------------------------------
when SEND =>
cmd_out_ns <= '1';
command_ns <= command;
if (vsize_over = '1' and command_ready = '1') then
mm2s_ns <= IDLE;
cmd_proc_ns <= '1';
command_valid_ns <= '0';
split_out_ns <= '0';
over_ns <= '1';
elsif (command_ready = '0') then --(command_valid = '1' and command_ready = '0') then
mm2s_ns <= SEND;
command_valid_ns <= '1';
cmd_proc_ns <= '1';
split_out_ns <= '0';
over_ns <= '0';
else
mm2s_ns <= SPLIT;
command_valid_ns <= '0';
cmd_proc_ns <= '1';
over_ns <= '0';
split_out_ns <= '0';
end if;
-------------------------------------------------------------------
when SPLIT =>
cmd_proc_ns <= '1';
mm2s_ns <= SEND;
command_ns <= cache_info & mm2s_cmd (72+(C_ADDR_WIDTH-32) downto 65+(C_ADDR_WIDTH-32)) & split_cmd & mm2s_cmd (31) & eof_set & mm2s_cmd (29 downto 0); -- buf length remains the same
-- command_ns <= cache_info & mm2s_cmd (72 downto 65) & split_cmd & mm2s_cmd (31 downto 0); -- buf length remains the same
cmd_out_ns <= '0';
split_out_ns <= '1';
command_valid_ns <= '1';
-------------------------------------------------------------------
-- coverage off
when others =>
mm2s_ns <= IDLE;
-- coverage on
end case;
end process MM2S_MACHINE;
SWALLOW_TVALID : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
counter <= (others => '0');
-- tvalid_unsplit_int <= '0';
reset_lock <= '1';
ready_for_next_cmd <= '0';
elsif (vsize_data_int = "00000000000000000000000") then
-- tvalid_unsplit_int <= '0';
ready_for_next_cmd <= '1';
reset_lock <= '0';
elsif ((tvalid_from_datamover = '1') and (counter < vsize_data_int)) then
counter <= counter + '1';
-- tvalid_unsplit_int <= '0';
ready_for_next_cmd <= '0';
reset_lock <= '0';
elsif ((counter = vsize_data_int) and (reset_lock = '0') and (tvalid_from_datamover = '1')) then
counter <= (others => '0');
-- tvalid_unsplit_int <= '1';
ready_for_next_cmd <= '1';
else
counter <= counter;
-- tvalid_unsplit_int <= '0';
if (cmd_proc_cdc_from = '1') then
ready_for_next_cmd <= '0';
else
ready_for_next_cmd <= ready_for_next_cmd;
end if;
end if;
end if;
end process SWALLOW_TVALID;
tvalid_unsplit_int <= tvalid_from_datamover when (counter = vsize_data_int) else '0'; --tvalid_unsplit_int;
SWALLOW_TDATA : process(clock)
begin
if(clock'EVENT and clock = '1')then
if (sgresetn = '0' or cmd_in = '1') then
tvalid_unsplit <= '0';
status_out_int <= (others => '0');
else
tvalid_unsplit <= tvalid_unsplit_int;
if (tvalid_from_datamover = '1') then
status_out_int (C_DM_STATUS_WIDTH-2 downto 0) <= status_in (C_DM_STATUS_WIDTH-2 downto 0) or status_out_int (C_DM_STATUS_WIDTH-2 downto 0);
else
status_out_int <= status_out_int;
end if;
if (tvalid_unsplit_int = '1') then
status_out_int (C_DM_STATUS_WIDTH-1) <= status_in (C_DM_STATUS_WIDTH-1);
end if;
end if;
end if;
end process SWALLOW_TDATA;
status_out <= status_out_int;
SWALLOW_TLAST_GEN : if C_INCLUDE_S2MM = 0 generate
begin
eof_set <= '1'; --eof_bit when (vsize = vsize_data_int) else '0';
CDC_CMD_PROC1 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => cmd_proc_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => clock_sec,
scndry_resetn => '0',
scndry_out => cmd_proc_cdc,
scndry_vect_out => open
);
CDC_CMD_PROC2 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => eof_bit_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => clock_sec,
scndry_resetn => '0',
scndry_out => eof_bit_cdc,
scndry_vect_out => open
);
CDC_CMD_PROC : process (clock_sec)
begin
if (clock_sec'EVENT and clock_sec = '1') then
if (aresetn = '0') then
-- cmd_proc_cdc_to <= '0';
-- cmd_proc_cdc <= '0';
-- eof_bit_cdc_to <= '0';
-- eof_bit_cdc <= '0';
ready_for_next_cmd_tlast_cdc_from <= '0';
else
-- cmd_proc_cdc_to <= cmd_proc_cdc_from;
-- cmd_proc_cdc <= cmd_proc_cdc_to;
-- eof_bit_cdc_to <= eof_bit_cdc_from;
-- eof_bit_cdc <= eof_bit_cdc_to;
ready_for_next_cmd_tlast_cdc_from <= ready_for_next_cmd_tlast;
end if;
end if;
end process CDC_CMD_PROC;
CDC_CMDTLAST_PROC : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => ready_for_next_cmd_tlast_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => clock,
scndry_resetn => '0',
scndry_out => ready_for_next_cmd_tlast_cdc,
scndry_vect_out => open
);
--CDC_CMDTLAST_PROC : process (clock)
-- begin
-- if (clock'EVENT and clock = '1') then
-- if (sgresetn = '0') then
-- ready_for_next_cmd_tlast_cdc_to <= '0';
-- ready_for_next_cmd_tlast_cdc <= '0';
-- else
-- ready_for_next_cmd_tlast_cdc_to <= ready_for_next_cmd_tlast_cdc_from;
-- ready_for_next_cmd_tlast_cdc <= ready_for_next_cmd_tlast_cdc_to;
-- end if;
-- end if;
--end process CDC_CMDTLAST_PROC;
SWALLOW_TLAST : process(clock_sec)
begin
if(clock_sec'EVENT and clock_sec = '1')then
if(aresetn = '0')then
counter_tlast <= (others => '0');
tlast_stream_data_int <= '0';
reset_lock_tlast <= '1';
ready_for_next_cmd_tlast <= '1';
elsif ((tlast_stream_data = '1' and tready_stream_data = '1') and vsize_data_int = "00000000000000000000000") then
tlast_stream_data_int <= '0';
ready_for_next_cmd_tlast <= '1';
reset_lock_tlast <= '0';
elsif ((tlast_stream_data = '1' and tready_stream_data = '1') and (counter_tlast < vsize_data_int)) then
counter_tlast <= counter_tlast + '1';
tlast_stream_data_int <= '0';
ready_for_next_cmd_tlast <= '0';
reset_lock_tlast <= '0';
elsif ((counter_tlast = vsize_data_int) and (reset_lock_tlast = '0') and (tlast_stream_data = '1' and tready_stream_data = '1')) then
counter_tlast <= (others => '0');
tlast_stream_data_int <= '1';
ready_for_next_cmd_tlast <= '1';
else
counter_tlast <= counter_tlast;
tlast_stream_data_int <= '0';
if (cmd_proc_cdc = '1') then
ready_for_next_cmd_tlast <= '0';
else
ready_for_next_cmd_tlast <= ready_for_next_cmd_tlast;
end if;
end if;
end if;
end process SWALLOW_TLAST;
tlast_unsplit <= tlast_stream_data when (counter_tlast = vsize_data_int and eof_bit_cdc = '1') else '0';
tlast_unsplit_user <= tlast_stream_data when (counter_tlast = vsize_data_int) else '0';
-- tlast_unsplit <= tlast_stream_data; -- when (counter_tlast = vsize_data_int) else '0';
end generate SWALLOW_TLAST_GEN;
SWALLOW_TLAST_GEN_S2MM : if C_INCLUDE_S2MM = 1 generate
begin
eof_set <= eof_bit_cdc_from;
ready_for_next_cmd_tlast_cdc <= '1';
end generate SWALLOW_TLAST_GEN_S2MM;
end implementation;
|
mit
|
justingallagher/fpga-trace
|
hls/triangle_intersect/tri_intersect/impl/ip/tmp.srcs/sources_1/ip/tri_intersect_ap_fdiv_28_no_dsp_32/xbip_dsp48_addsub_v3_0/hdl/xbip_dsp48_addsub_v3_0.vhd
|
9
|
10258
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5856)
`protect data_block
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`protect end_protected
|
mit
|
justingallagher/fpga-trace
|
hls/triangle_intersect/tri_intersect/impl/ip/hdl/vhdl/tri_intersect_fsub_32ns_32ns_32_9_full_dsp.vhd
|
4
|
3390
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.1
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity tri_intersect_fsub_32ns_32ns_32_9_full_dsp is
generic (
ID : integer := 0;
NUM_STAGE : integer := 9;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of tri_intersect_fsub_32ns_32ns_32_9_full_dsp is
--------------------- Component ---------------------
component tri_intersect_ap_fsub_7_full_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
tri_intersect_ap_fsub_7_full_dsp_32_u : component tri_intersect_ap_fsub_7_full_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= (din0_WIDTH-1 downto 0 => '0') when ((din0_buf1 = ( din0_WIDTH-1 downto 0 => 'X')) or (din0_buf1 = ( din0_WIDTH-1 downto 0 => 'U'))) else din0_buf1;
b_tvalid <= '1';
b_tdata <= (din1_WIDTH-1 downto 0 => '0') when ((din1_buf1 = ( din1_WIDTH-1 downto 0 => 'X')) or (din1_buf1 = ( din1_WIDTH-1 downto 0 => 'U'))) else din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
|
mit
|
justingallagher/fpga-trace
|
design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/950a27d1/hdl/src/vhdl/axi_sg_updt_cmdsts_if.vhd
|
5
|
12100
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_cmdsts_if.vhd
-- Description: This entity is the descriptor update command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_cmdsts_if is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Update command write interface from fetch sm --
updt_cmnd_wr : in std_logic ; --
updt_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_updt_cmd_tvalid : out std_logic ; --
s_axis_updt_cmd_tready : in std_logic ; --
s_axis_updt_cmd_tdata : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_updt_sts_tvalid : in std_logic ; --
m_axis_updt_sts_tready : out std_logic ; --
m_axis_updt_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_updt_sts_tkeep : in std_logic_vector(0 downto 0) ; --
--
-- Scatter Gather Fetch Status --
s2mm_err : in std_logic ; --
updt_done : out std_logic ; --
updt_error : out std_logic ; --
updt_interr : out std_logic ; --
updt_slverr : out std_logic ; --
updt_decerr : out std_logic --
);
end axi_sg_updt_cmdsts_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_cmdsts_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal updt_slverr_i : std_logic := '0';
signal updt_decerr_i : std_logic := '0';
signal updt_interr_i : std_logic := '0';
signal s2mm_error : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
updt_slverr <= updt_slverr_i;
updt_decerr <= updt_decerr_i;
updt_interr <= updt_interr_i;
-------------------------------------------------------------------------------
-- DataMover Command Interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When command by fetch sm, drive descriptor update command to data mover.
-- Hold until data mover indicates ready.
-------------------------------------------------------------------------------
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_updt_cmd_tvalid <= '0';
-- s_axis_updt_cmd_tdata <= (others => '0');
elsif(updt_cmnd_wr = '1')then
s_axis_updt_cmd_tvalid <= '1';
-- s_axis_updt_cmd_tdata <= updt_cmnd_data;
elsif(s_axis_updt_cmd_tready = '1')then
s_axis_updt_cmd_tvalid <= '0';
-- s_axis_updt_cmd_tdata <= (others => '0');
end if;
end if;
end process GEN_DATAMOVER_CMND;
s_axis_updt_cmd_tdata <= updt_cmnd_data;
-------------------------------------------------------------------------------
-- DataMover Status Interface
-------------------------------------------------------------------------------
-- Drive ready low during reset to indicate not ready
REG_STS_READY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
m_axis_updt_sts_tready <= '0';
else
m_axis_updt_sts_tready <= '1';
end if;
end if;
end process REG_STS_READY;
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_slverr_i <= '0';
updt_decerr_i <= '0';
updt_interr_i <= '0';
-- Status valid, therefore capture status
elsif(m_axis_updt_sts_tvalid = '1')then
updt_slverr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
updt_decerr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_DECERR_BIT);
updt_interr_i <= m_axis_updt_sts_tdata(DATAMOVER_STS_INTERR_BIT);
-- Only assert when valid
else
updt_slverr_i <= '0';
updt_decerr_i <= '0';
updt_interr_i <= '0';
end if;
end if;
end process DATAMOVER_STS;
-------------------------------------------------------------------------------
-- Transfer Done
-------------------------------------------------------------------------------
XFER_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_done <= '0';
-- Status valid, therefore capture status
elsif(m_axis_updt_sts_tvalid = '1')then
updt_done <= m_axis_updt_sts_tdata(DATAMOVER_STS_CMDDONE_BIT)
or m_axis_updt_sts_tdata(DATAMOVER_STS_SLVERR_BIT)
or m_axis_updt_sts_tdata(DATAMOVER_STS_DECERR_BIT)
or m_axis_updt_sts_tdata(DATAMOVER_STS_INTERR_BIT);
-- Only assert when valid
else
updt_done <= '0';
end if;
end if;
end process XFER_DONE;
-------------------------------------------------------------------------------
-- Register global error from data mover.
-------------------------------------------------------------------------------
s2mm_error <= updt_slverr_i or updt_decerr_i or updt_interr_i;
-- Log errors into a global error output
UPDATE_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_error <= '0';
elsif(s2mm_error = '1')then
updt_error <= '1';
end if;
end if;
end process UPDATE_ERROR_PROCESS;
end implementation;
|
mit
|
justingallagher/fpga-trace
|
design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/950a27d1/hdl/src/vhdl/axi_sg_skid_buf.vhd
|
13
|
18142
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_skid_buf.vhd
--
-- Description:
-- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_sg_skid_buf is
generic (
C_WDATA_WIDTH : INTEGER := 32
-- Width of the Stream Data bus (in bits)
);
port (
-- Clock and Reset Inputs ---------------------------------------------
aclk : In std_logic ; --
arst : In std_logic ; --
-----------------------------------------------------------------------
-- Shutdown control (assert for 1 clk pulse) --------------------------
--
skid_stop : In std_logic ; --
-----------------------------------------------------------------------
-- Slave Side (Stream Data Input) -------------------------------------
s_valid : In std_logic ; --
s_ready : Out std_logic ; --
s_data : In std_logic_vector(C_WDATA_WIDTH-1 downto 0); --
s_strb : In std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); --
s_last : In std_logic ; --
-----------------------------------------------------------------------
-- Master Side (Stream Data Output ------------------------------------
m_valid : Out std_logic ; --
m_ready : In std_logic ; --
m_data : Out std_logic_vector(C_WDATA_WIDTH-1 downto 0); --
m_strb : Out std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); --
m_last : Out std_logic --
-----------------------------------------------------------------------
);
end entity axi_sg_skid_buf;
architecture implementation of axi_sg_skid_buf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Signals decalrations -------------------------
Signal sig_reset_reg : std_logic := '0';
signal sig_spcl_s_ready_set : std_logic := '0';
signal sig_data_skid_reg : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_reg : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_reg : std_logic := '0';
signal sig_skid_reg_en : std_logic := '0';
signal sig_data_skid_mux_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_mux_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_mux_out : std_logic := '0';
signal sig_skid_mux_sel : std_logic := '0';
signal sig_data_reg_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_reg_out : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_reg_out : std_logic := '0';
signal sig_data_reg_out_en : std_logic := '0';
signal sig_m_valid_out : std_logic := '0';
signal sig_m_valid_dup : std_logic := '0';
signal sig_m_valid_comb : std_logic := '0';
signal sig_s_ready_out : std_logic := '0';
signal sig_s_ready_dup : std_logic := '0';
signal sig_s_ready_comb : std_logic := '0';
signal sig_stop_request : std_logic := '0';
signal sig_stopped : std_logic := '0';
signal sig_sready_stop : std_logic := '0';
signal sig_sready_early_stop : std_logic := '0';
signal sig_sready_stop_set : std_logic := '0';
signal sig_sready_stop_reg : std_logic := '0';
signal sig_mvalid_stop_reg : std_logic := '0';
signal sig_mvalid_stop : std_logic := '0';
signal sig_mvalid_early_stop : std_logic := '0';
signal sig_mvalid_stop_set : std_logic := '0';
signal sig_slast_with_stop : std_logic := '0';
signal sig_sstrb_stop_mask : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_sstrb_with_stop : std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0) := (others => '0');
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no";
begin --(architecture implementation)
m_valid <= sig_m_valid_out;
s_ready <= sig_s_ready_out;
m_strb <= sig_strb_reg_out;
m_last <= sig_last_reg_out;
m_data <= sig_data_reg_out;
-- Special shutdown logic version od Slast.
-- A halt request forces a tlast through the skig buffer
sig_slast_with_stop <= s_last or sig_stop_request;
sig_sstrb_with_stop <= s_strb or sig_sstrb_stop_mask;
-- Assign the special s_ready FLOP set signal
sig_spcl_s_ready_set <= sig_reset_reg;
-- Generate the ouput register load enable control
sig_data_reg_out_en <= m_ready or not(sig_m_valid_dup);
-- Generate the skid input register load enable control
sig_skid_reg_en <= sig_s_ready_dup;
-- Generate the skid mux select control
sig_skid_mux_sel <= not(sig_s_ready_dup);
-- Skid Mux
sig_data_skid_mux_out <= sig_data_skid_reg
When (sig_skid_mux_sel = '1')
Else s_data;
sig_strb_skid_mux_out <= sig_strb_skid_reg
When (sig_skid_mux_sel = '1')
Else sig_sstrb_with_stop;
sig_last_skid_mux_out <= sig_last_skid_reg
When (sig_skid_mux_sel = '1')
Else sig_slast_with_stop;
-- m_valid combinational logic
sig_m_valid_comb <= s_valid or
(sig_m_valid_dup and
(not(sig_s_ready_dup) or
not(m_ready)));
-- s_ready combinational logic
sig_s_ready_comb <= m_ready or
(sig_s_ready_dup and
(not(sig_m_valid_dup) or
not(s_valid)));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_THE_RST
--
-- Process Description:
-- Register input reset
--
-------------------------------------------------------------
REG_THE_RST : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
sig_reset_reg <= ARST;
end if;
end process REG_THE_RST;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: S_READY_FLOP
--
-- Process Description:
-- Registers s_ready handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
S_READY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_sready_stop = '1' or
sig_sready_early_stop = '1') then -- Special stop condition
sig_s_ready_out <= '0';
sig_s_ready_dup <= '0';
Elsif (sig_spcl_s_ready_set = '1') Then
sig_s_ready_out <= '1';
sig_s_ready_dup <= '1';
else
sig_s_ready_out <= sig_s_ready_comb;
sig_s_ready_dup <= sig_s_ready_comb;
end if;
end if;
end process S_READY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: M_VALID_FLOP
--
-- Process Description:
-- Registers m_valid handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
M_VALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_spcl_s_ready_set = '1' or -- Fix from AXI DMA
sig_mvalid_stop = '1' or
sig_mvalid_stop_set = '1') then -- Special stop condition
sig_m_valid_out <= '0';
sig_m_valid_dup <= '0';
else
sig_m_valid_out <= sig_m_valid_comb;
sig_m_valid_dup <= sig_m_valid_comb;
end if;
end if;
end process M_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_REG
--
-- Process Description:
-- This process implements the output registers for the
-- Skid Buffer Data signals
--
-------------------------------------------------------------
SKID_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_data_skid_reg <= (others => '0');
sig_strb_skid_reg <= (others => '0');
sig_last_skid_reg <= '0';
elsif (sig_skid_reg_en = '1') then
sig_data_skid_reg <= s_data;
sig_strb_skid_reg <= sig_sstrb_with_stop;
sig_last_skid_reg <= sig_slast_with_stop;
else
null; -- hold current state
end if;
end if;
end process SKID_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_REG
--
-- Process Description:
-- This process implements the output registers for the
-- Skid Buffer Data signals
--
-------------------------------------------------------------
OUTPUT_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_mvalid_stop_reg = '1') then
sig_data_reg_out <= (others => '0');
sig_strb_reg_out <= (others => '0');
sig_last_reg_out <= '0';
elsif (sig_data_reg_out_en = '1') then
sig_data_reg_out <= sig_data_skid_mux_out;
sig_strb_reg_out <= sig_strb_skid_mux_out;
sig_last_reg_out <= sig_last_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_REG;
-------- Special Stop Logic --------------------------------------
sig_sready_stop <= sig_sready_stop_reg;
sig_sready_early_stop <= skid_stop; -- deassert S_READY immediately
sig_sready_stop_set <= sig_sready_early_stop;
sig_mvalid_stop <= sig_mvalid_stop_reg;
sig_mvalid_early_stop <= sig_m_valid_dup and
m_ready and
skid_stop;
sig_mvalid_stop_set <= sig_mvalid_early_stop or
(sig_stop_request and
not(sig_m_valid_dup)) or
(sig_m_valid_dup and
m_ready and
sig_stop_request);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_STOP_REQ_FLOP
--
-- Process Description:
-- This process implements the Stop request flop. It is a
-- sample and hold register that can only be cleared by reset.
--
-------------------------------------------------------------
IMP_STOP_REQ_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_stop_request <= '0';
sig_sstrb_stop_mask <= (others => '0');
elsif (skid_stop = '1') then
sig_stop_request <= '1';
sig_sstrb_stop_mask <= (others => '1');
else
null; -- hold current state
end if;
end if;
end process IMP_STOP_REQ_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_SREADY_FLOP
--
-- Process Description:
-- This process implements the flag to clear the s_ready
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_SREADY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_sready_stop_reg <= '0';
elsif (sig_sready_stop_set = '1') then
sig_sready_stop_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_SREADY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_CLR_MVALID_FLOP
--
-- Process Description:
-- This process implements the flag to clear the m_valid
-- flop at a stop condition.
--
-------------------------------------------------------------
IMP_CLR_MVALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_mvalid_stop_reg <= '0';
elsif (sig_mvalid_stop_set = '1') then
sig_mvalid_stop_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_CLR_MVALID_FLOP;
end implementation;
|
mit
|
justingallagher/fpga-trace
|
hls/triangle_intersect/tri_intersect/impl/ip/tmp.srcs/sources_1/ip/tri_intersect_ap_fsub_7_full_dsp_32/xbip_pipe_v3_0/hdl/xbip_pipe_v3_0.vhd
|
13
|
7774
|
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`protect end_protected
|
mit
|
justingallagher/fpga-trace
|
design/raytracer_design.srcs/sources_1/ipshared/xilinx.com/axi_sg_v4_1/950a27d1/hdl/src/vhdl/axi_sg_ftch_pntr.vhd
|
4
|
22217
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_pntr.vhd
-- Description: This entity manages descriptor pointers and determine scatter
-- gather idle mode.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_pntr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_INCLUDE_CH1 : integer range 0 to 1 := 1 ;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
nxtdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
------------------------------- --
-- CHANNEL 1 --
------------------------------- --
ch1_run_stop : in std_logic ; --
ch1_desc_flush : in std_logic ; --CR568950 --
--
-- CURDESC update to fetch pointer on run/stop assertion --
ch1_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- TAILDESC update on CPU write (from axi_dma_reg_module) --
ch1_tailpntr_enabled : in std_logic ; --
ch1_taildesc_wren : in std_logic ; --
ch1_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if) --
ch1_nxtdesc_wren : in std_logic ; --
--
-- Current address of descriptor to fetch --
ch1_fetch_address : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_sg_idle : out std_logic ; --
--
------------------------------- --
-- CHANNEL 2 --
------------------------------- --
ch2_run_stop : in std_logic ; --
ch2_desc_flush : in std_logic ;--CR568950 --
ch2_eof_detected : in std_logic ; --
--
-- CURDESC update to fetch pointer on run/stop assertion --
ch2_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- TAILDESC update on CPU write (from axi_dma_reg_module) --
ch2_tailpntr_enabled : in std_logic ; --
ch2_taildesc_wren : in std_logic ; --
ch2_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
tail_updt : in std_logic;
tail_updt_latch : out std_logic;
ch2_updt_done : in std_logic;
--
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if) --
ch2_nxtdesc_wren : in std_logic ; --
--
-- Current address of descriptor to fetch --
ch2_fetch_address : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_sg_idle : out std_logic ; --
bd_eq : out std_logic
);
end axi_sg_ftch_pntr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_pntr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
attribute mark_debug : string;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ch1_run_stop_d1 : std_logic := '0';
signal ch1_run_stop_re : std_logic := '0';
signal ch1_use_crntdesc : std_logic := '0';
signal ch1_fetch_address_i : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal ch2_run_stop_d1 : std_logic := '0';
signal ch2_run_stop_re : std_logic := '0';
signal ch2_use_crntdesc : std_logic := '0';
signal ch2_fetch_address_i : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal first : std_logic;
signal eof_latch : std_logic;
signal ch2_sg_idle_int : std_logic;
attribute mark_debug of ch1_fetch_address_i : signal is "true";
attribute mark_debug of ch2_fetch_address_i : signal is "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Channel 1 is included therefore generate pointer logic
GEN_PNTR_FOR_CH1 : if C_INCLUDE_CH1 = 1 generate
begin
GEN_RUNSTOP_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_run_stop_d1 <= '0';
else
ch1_run_stop_d1 <= ch1_run_stop;
end if;
end if;
end process GEN_RUNSTOP_RE;
ch1_run_stop_re <= ch1_run_stop and not ch1_run_stop_d1;
---------------------------------------------------------------------------
-- At setting of run/stop need to use current descriptor pointer therefor
-- flag for use
---------------------------------------------------------------------------
GEN_INIT_PNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch1_nxtdesc_wren = '1')then
ch1_use_crntdesc <= '0';
elsif(ch1_run_stop_re = '1')then
ch1_use_crntdesc <= '1';
end if;
end if;
end process GEN_INIT_PNTR;
---------------------------------------------------------------------------
-- Register Current Fetch Address. During start (run/stop asserts) reg
-- curdesc pointer from register module. Once running use nxtdesc pointer.
---------------------------------------------------------------------------
REG_FETCH_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_fetch_address_i <= (others => '0');
-- On initial tail pointer write use current desc pointer
elsif(ch1_use_crntdesc = '1' and ch1_nxtdesc_wren = '0')then
ch1_fetch_address_i <= ch1_curdesc;
-- On desriptor fetch capture next pointer
elsif(ch1_nxtdesc_wren = '1')then
ch1_fetch_address_i <= nxtdesc;
end if;
end if;
end process REG_FETCH_ADDRESS;
-- Pass address out of module
-- Addresses are always 16 word 32-bit aligned
ch1_fetch_address <= ch1_fetch_address_i (C_M_AXI_SG_ADDR_WIDTH-1 downto 6) & "000000";
---------------------------------------------------------------------------
-- Compair tail descriptor pointer to scatter gather engine current
-- descriptor pointer. Set idle if matched. Only check if DMA engine
-- is running and current descriptor is in process of being fetched. This
-- forces at least 1 descriptor fetch before checking for IDLE condition.
---------------------------------------------------------------------------
COMPARE_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- SG is IDLE on reset and on stop.
--CR568950 - reset idlag on descriptor flush
--if(m_axi_sg_aresetn = '0' or ch1_run_stop = '0')then
if(m_axi_sg_aresetn = '0' or ch1_run_stop = '0' or ch1_desc_flush = '1')then
ch1_sg_idle <= '1';
-- taildesc_wren must be in this 'if' to force a minimum
-- of 1 clock of sg_idle = '0'.
elsif(ch1_taildesc_wren = '1' or ch1_tailpntr_enabled = '0')then
ch1_sg_idle <= '0';
-- Descriptor at fetch_address is being fetched (wren=1)
-- therefore safe to check if tail matches the fetch address
elsif(ch1_nxtdesc_wren = '1'
and ch1_taildesc = ch1_fetch_address_i)then
ch1_sg_idle <= '1';
end if;
end if;
end process COMPARE_ADDRESS;
end generate GEN_PNTR_FOR_CH1;
-- Channel 1 is NOT included therefore tie off pointer logic
GEN_NO_PNTR_FOR_CH1 : if C_INCLUDE_CH1 = 0 generate
begin
ch1_fetch_address <= (others =>'0');
ch1_sg_idle <= '0';
end generate GEN_NO_PNTR_FOR_CH1;
-- Channel 2 is included therefore generate pointer logic
GEN_PNTR_FOR_CH2 : if C_INCLUDE_CH2 = 1 generate
begin
---------------------------------------------------------------------------
-- Create clock delay of run_stop in order to generate a rising edge pulse
---------------------------------------------------------------------------
GEN_RUNSTOP_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_run_stop_d1 <= '0';
else
ch2_run_stop_d1 <= ch2_run_stop;
end if;
end if;
end process GEN_RUNSTOP_RE;
ch2_run_stop_re <= ch2_run_stop and not ch2_run_stop_d1;
---------------------------------------------------------------------------
-- At setting of run/stop need to use current descriptor pointer therefor
-- flag for use
---------------------------------------------------------------------------
GEN_INIT_PNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_nxtdesc_wren = '1')then
ch2_use_crntdesc <= '0';
elsif(ch2_run_stop_re = '1')then
ch2_use_crntdesc <= '1';
end if;
end if;
end process GEN_INIT_PNTR;
---------------------------------------------------------------------------
-- Register Current Fetch Address. During start (run/stop asserts) reg
-- curdesc pointer from register module. Once running use nxtdesc pointer.
---------------------------------------------------------------------------
REG_FETCH_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_fetch_address_i <= (others => '0');
-- On initial tail pointer write use current desc pointer
elsif((ch2_use_crntdesc = '1' and ch2_nxtdesc_wren = '0'))then
ch2_fetch_address_i <= ch2_curdesc;
-- On descirptor fetch capture next pointer
elsif(ch2_nxtdesc_wren = '1')then
ch2_fetch_address_i <= nxtdesc;
end if;
end if;
end process REG_FETCH_ADDRESS;
-- Pass address out of module
-- Addresses are always 16 word 32-bit aligned
ch2_fetch_address <= ch2_fetch_address_i (C_M_AXI_SG_ADDR_WIDTH-1 downto 6) & "000000";
---------------------------------------------------------------------------
-- Compair tail descriptor pointer to scatter gather engine current
-- descriptor pointer. Set idle if matched. Only check if DMA engine
-- is running and current descriptor is in process of being fetched. This
-- forces at least 1 descriptor fetch before checking for IDLE condition.
---------------------------------------------------------------------------
COMPARE_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- SG is IDLE on reset and on stop.
--CR568950 - reset idlag on descriptor flush
--if(m_axi_sg_aresetn = '0' or ch2_run_stop = '0')then
if(m_axi_sg_aresetn = '0' or ch2_run_stop = '0' or ch2_desc_flush = '1' or ch2_eof_detected = '1')then
ch2_sg_idle <= '1';
ch2_sg_idle_int <= '1';
-- taildesc_wren must be in this 'if' to force a minimum
-- of 1 clock of sg_idle = '0'.
elsif(ch2_taildesc_wren = '1' or ch2_tailpntr_enabled = '0')then
ch2_sg_idle <= '0';
ch2_sg_idle_int <= '0';
-- Descriptor at fetch_address is being fetched (wren=1)
-- therefore safe to check if tail matches the fetch address
elsif(ch2_nxtdesc_wren = '1'
and ch2_taildesc = ch2_fetch_address_i)then
ch2_sg_idle <= '1';
ch2_sg_idle_int <= '1';
end if;
end if;
end process COMPARE_ADDRESS;
-- Needed for multi channel
EOF_LATCH_PROC : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_taildesc_wren = '1' or eof_latch = '1')then -- nned to have some reset condition here
eof_latch <= '0';
elsif (ch2_sg_idle_int = '1' and ch2_updt_done = '1') then
eof_latch <= '1';
end if;
end if;
end process EOF_LATCH_PROC;
TAILUPDT_LATCH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or eof_latch = '1')then -- nned to have some reset condition here
tail_updt_latch <= '0';
first <= '0';
elsif (tail_updt = '1') then
tail_updt_latch <= '0';
elsif(ch2_taildesc_wren = '1' and first = '0')then
first <= '1';
elsif(ch2_taildesc_wren = '1' and first = '1')then
tail_updt_latch <= '1';
end if;
end if;
end process TAILUPDT_LATCH;
EQUAL_BD : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_run_stop = '0' or ch2_desc_flush = '1')then
bd_eq <= '0';
elsif(ch2_taildesc_wren = '1' or ch2_tailpntr_enabled = '0')then
bd_eq <= '0';
elsif(ch2_nxtdesc_wren = '1'
and ch2_taildesc = ch2_fetch_address_i)then
bd_eq <= '1';
end if;
end if;
end process EQUAL_BD;
end generate GEN_PNTR_FOR_CH2;
-- Channel 2 is NOT included therefore tie off pointer logic
GEN_NO_PNTR_FOR_CH2 : if C_INCLUDE_CH2 = 0 generate
begin
ch2_fetch_address <= (others =>'0');
ch2_sg_idle <= '0';
tail_updt_latch <= '0';
bd_eq <= '0';
end generate GEN_NO_PNTR_FOR_CH2;
end implementation;
|
mit
|
justingallagher/fpga-trace
|
hls/triangle_intersect/tri_intersect/impl/ip/tmp.srcs/sources_1/ip/tri_intersect_ap_fdiv_28_no_dsp_32/sim/tri_intersect_ap_fdiv_28_no_dsp_32.vhd
|
1
|
10720
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_0;
USE floating_point_v7_0.floating_point_v7_0;
ENTITY tri_intersect_ap_fdiv_28_no_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END tri_intersect_ap_fdiv_28_no_dsp_32;
ARCHITECTURE tri_intersect_ap_fdiv_28_no_dsp_32_arch OF tri_intersect_ap_fdiv_28_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tri_intersect_ap_fdiv_28_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_0 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_0
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 1,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 28,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END tri_intersect_ap_fdiv_28_no_dsp_32_arch;
|
mit
|
justingallagher/fpga-trace
|
hls/triangle_intersect/tri_intersect/impl/ip/hdl/ip/tri_intersect_ap_fsub_7_full_dsp_32.vhd
|
3
|
12691
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_0;
USE floating_point_v7_0.floating_point_v7_0;
ENTITY tri_intersect_ap_fsub_7_full_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END tri_intersect_ap_fsub_7_full_dsp_32;
ARCHITECTURE tri_intersect_ap_fsub_7_full_dsp_32_arch OF tri_intersect_ap_fsub_7_full_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tri_intersect_ap_fsub_7_full_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_0 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF tri_intersect_ap_fsub_7_full_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_0,Vivado 2015.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF tri_intersect_ap_fsub_7_full_dsp_32_arch : ARCHITECTURE IS "tri_intersect_ap_fsub_7_full_dsp_32,floating_point_v7_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF tri_intersect_ap_fsub_7_full_dsp_32_arch: ARCHITECTURE IS "tri_intersect_ap_fsub_7_full_dsp_32,floating_point_v7_0,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.0,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=1,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=7,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_0
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 1,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 7,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END tri_intersect_ap_fsub_7_full_dsp_32_arch;
|
mit
|
herenvarno/dlx
|
dlx_vhd/src/a.b-DataPath.core/a.b.a-Alu.core/a.b.a.a-Adder.core/a.b.a.a.0-AdderSumGenerator.vhd
|
1
|
1674
|
--------------------------------------------------------------------------------
-- FILE: AdderSumGenerator
-- DESC: The sum generator part of a Adder, typically used in P4 Adder
--
-- Author:
-- Create: 2015-05-27
-- Update: 2015-05-27
-- Status: TESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.Consts.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity AdderSumGenerator is
generic (
DATA_SIZE : integer := C_SYS_DATA_SIZE;
SPARSITY : integer := C_ADD_SPARSITY
);
port (
a, b: in std_logic_vector(DATA_SIZE-1 downto 0);
cin: in std_logic_vector(DATA_SIZE/SPARSITY-1 downto 0);
sum: out std_logic_vector(DATA_SIZE-1 downto 0)
);
end AdderSumGenerator;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture adder_sum_generator_arch of AdderSumGenerator is
component AdderCarrySelect is
generic(
DATA_SIZE : integer := C_SYS_DATA_SIZE
);
port(
a, b: in std_logic_vector(DATA_SIZE-1 downto 0);
sel: in std_logic;
sum: out std_logic_vector(DATA_SIZE-1 downto 0)
);
end component;
begin
GE0: for i in 0 to DATA_SIZE/SPARSITY-1 generate
begin
ACSi: AdderCarrySelect
generic map(SPARSITY)
port map(a((i+1)*SPARSITY-1 downto i*SPARSITY), b((i+1)*SPARSITY-1 downto i*SPARSITY), cin(i), sum((i+1)*SPARSITY-1 downto i*SPARSITY));
end generate;
end adder_sum_generator_arch;
|
mit
|
jakubcabal/pipemania-fpga-game
|
source/comp/memory/mem_hub_tb.vhd
|
1
|
4418
|
--------------------------------------------------------------------------------
-- PROJECT: PIPE MANIA - GAME FOR FPGA
--------------------------------------------------------------------------------
-- NAME: MEM_HUB_TB
-- AUTHORS: Jakub Cabal <[email protected]>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://github.com/jakubcabal/pipemania-fpga-game
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MEM_HUB_TB is
end MEM_HUB_TB;
architecture behavior of MEM_HUB_TB is
-- CLK and RST
signal CLK : std_logic := '0';
signal RST : std_logic := '0';
-- Memory signals
signal sig_we_hub : std_logic;
signal sig_addr_hub : std_logic_vector(8 downto 0);
signal sig_dout_hub : std_logic_vector(31 downto 0);
signal sig_din_hub : std_logic_vector(31 downto 0);
-- MEM_HUB signals
signal hub_we_a : std_logic;
signal hub_en_a : std_logic;
signal hub_addr_a : std_logic_vector(8 downto 0);
signal hub_din_a : std_logic_vector(31 downto 0);
signal hub_dout_a : std_logic_vector(31 downto 0);
signal hub_ack_a : std_logic;
signal hub_we_b : std_logic;
signal hub_en_b : std_logic;
signal hub_addr_b : std_logic_vector(8 downto 0);
signal hub_din_b : std_logic_vector(31 downto 0);
signal hub_dout_b : std_logic_vector(31 downto 0);
signal hub_ack_b : std_logic;
-- Clock period definitions
constant CLK_period : time := 10 ns;
begin
uut : entity work.MEM_HUB
port map (
CLK => CLK,
RST => RST,
-- Port A
EN_A => hub_en_a,
WE_A => hub_we_a,
ADDR_A => hub_addr_a,
DIN_A => hub_din_a,
DOUT_A => hub_dout_a,
ACK_A => hub_ack_a,
-- Port B
EN_B => hub_en_b,
WE_B => hub_we_b,
ADDR_B => hub_addr_b,
DIN_B => hub_din_b,
DOUT_B => hub_dout_b,
ACK_B => hub_ack_b,
-- Port to memory
WE => sig_we_hub,
ADDR => sig_addr_hub,
DIN => sig_din_hub,
DOUT => sig_dout_hub
);
mem : entity work.BRAM_SYNC_TDP
port map (
-- Port A
CLK => CLK,
WE_A => sig_we_hub,
ADDR_A => sig_addr_hub,
DATAIN_A => sig_din_hub,
DATAOUT_A => sig_dout_hub,
-- Port B
WE_A => '0',
ADDR_A => (others => '0'),
DATAIN_A => (others => '0'),
DATAOUT_A => open
);
clk_process : process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
sim_proc : process
begin
wait for 100 ns;
wait until rising_edge(CLK);
hub_en_a <= '1';
hub_we_a <= '1';
hub_addr_a <= "000000001";
hub_din_a <= "11111111110000001111111111000000";
wait until rising_edge(CLK);
hub_en_a <= '1';
hub_we_a <= '1';
hub_addr_a <= "000000010";
hub_din_a <= "11111111111111111111111111111111";
wait until rising_edge(CLK);
hub_en_a <= '1';
hub_we_a <= '1';
hub_addr_a <= "000000011";
hub_din_a <= "00000001111111111100000000011111";
wait until rising_edge(CLK);
hub_en_a <= '1';
hub_we_a <= '0';
hub_addr_a <= "000000001";
hub_din_a <= "00000000000000000000000000000000";
wait until rising_edge(CLK);
hub_en_a <= '0';
hub_we_a <= '0';
hub_addr_a <= (others => '0');
wait until rising_edge(CLK);
hub_en_a <= '1';
hub_we_a <= '0';
hub_addr_a <= (others => '0');
wait until rising_edge(CLK);
hub_en_a <= '1';
hub_we_a <= '0';
hub_addr_a <= "000000001";
wait until rising_edge(CLK);
hub_en_a <= '1';
hub_we_a <= '0';
hub_addr_a <= "000000010";
wait until rising_edge(CLK);
hub_en_a <= '1';
hub_we_a <= '0';
hub_addr_a <= "000000011";
wait until rising_edge(CLK);
hub_en_a <= '0';
hub_we_a <= '0';
hub_addr_a <= (others => '0');
wait;
end process;
end;
|
mit
|
herenvarno/dlx
|
dlx_syn/postsyn/Dlx_opd.vhdl
|
2
|
3457984
| null |
mit
|
herenvarno/dlx
|
dlx_vhd/src/a.a-ControlUnit.core/a.a.a-CwGenerator.vhd
|
1
|
10864
|
--------------------------------------------------------------------------------
-- FILE: CwGenerator
-- DESC: Generate Control Word
--
-- Author:
-- Create: 2015-05-30
-- Update: 2015-09-02
-- Status: TESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Consts.all;
use work.Funcs.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity CwGenerator is
generic (
DATA_SIZE : integer := C_SYS_DATA_SIZE; -- Data Size
OPCD_SIZE : integer := C_SYS_OPCD_SIZE; -- Op Code Size
FUNC_SIZE : integer := C_SYS_FUNC_SIZE; -- Func Field Size for R-Type Ops
CWRD_SIZE : integer := C_SYS_CWRD_SIZE; -- Control Word Size
CALU_SIZE : integer := C_CTR_CALU_SIZE -- ALU Op Code Word Size
);
port (
clk : in std_logic;
rst : in std_logic;
opcd : in std_logic_vector(OPCD_SIZE-1 downto 0):=(others=>'0');
func : in std_logic_vector(FUNC_SIZE-1 downto 0):=(others=>'0');
stall_flag : in std_logic_vector(4 downto 0):=(others=>'0');
taken : in std_logic;
cw : out std_logic_vector(CWRD_SIZE-1 downto 0):=(others=>'0');
calu : out std_logic_vector(CALU_SIZE-1 downto 0):=(others=>'0')
);
end CwGenerator;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture cw_generator_arch of CwGenerator is
constant PIPELINE_STAGE: integer := 5;
--constant UCODE_MEM_SIZE : integer := 2**OPCD_SIZE;
constant UCODE_MEM_SIZE : integer := 69;
constant RELOC_MEM_SIZE : integer := 64;
type ucode_mem_t is array (0 to UCODE_MEM_SIZE-1) of std_logic_vector(CWRD_SIZE-1 downto 0);
type reloc_mem_t is array (0 to RELOC_MEM_SIZE-1) of std_logic_vector(OPCD_SIZE+1 downto 0); -- Mul by 4, since each instruction need 4 stages, IF stage do not count.
signal stall1 : std_logic;
signal stall2 : std_logic;
signal stall3 : std_logic;
signal stall4 : std_logic;
signal stall5 : std_logic;
signal reloc_mem : reloc_mem_t := (
x"01", -- 0x00 R
x"01", -- 0x01 F
x"05", -- 0x02 J
x"09", -- 0x03 JAL
x"0d", -- 0x04 BEQZ
x"0d", -- 0x05 BNEZ
x"00", -- 0x06 UNUSED
x"00", -- 0x07 UNUSED
x"11", -- 0x08 ADDI
x"41", -- 0x09 ADDUI
x"11", -- 0x0a SUBI
x"41", -- 0x0b SUBUI
x"41", -- 0x0c ANDI
x"41", -- 0x0d ORI
x"41", -- 0x0e XORI
x"11", -- 0x0f LHI
x"00", -- 0x10 UNUSED
x"00", -- 0x11 UNUSED
x"15", -- 0x12 JR
x"19", -- 0x13 JALR
x"41", -- 0x14 SLLI
x"1d", -- 0x15 NOP
x"41", -- 0x16 SRLI
x"41", -- 0x17 SRAI
x"11", -- 0x18 SEQI
x"11", -- 0x19 SNEI
x"11", -- 0x1a SLTI
x"11", -- 0x1b SGTI
x"11", -- 0x1c SLEI
x"11", -- 0x1d SGEI
x"00", -- 0x1e UNUSED
x"00", -- 0x1f UNUSED
x"21", -- 0x20 LB
x"25", -- 0x21 LH
x"00", -- 0x22 UNUSED
x"29", -- 0x23 LW
x"2d", -- 0x24 LBU
x"31", -- 0x25 LHU
x"00", -- 0x26 UNUSED
x"00", -- 0x27 UNUSED
x"35", -- 0x28 SB
x"39", -- 0x29 SH
x"00", -- 0x2a UNUSED
x"3d", -- 0x2b SW
x"00", -- 0x2c UNUSED
x"00", -- 0x2d UNUSED
x"00", -- 0x2e UNUSED
x"00", -- 0x2f UNUSED
x"00", -- 0x30 UNUSED
x"00", -- 0x31 UNUSED
x"00", -- 0x32 UNUSED
x"00", -- 0x33 UNUSED
x"00", -- 0x34 UNUSED
x"00", -- 0x35 UNUSED
x"00", -- 0x36 UNUSED
x"00", -- 0x37 UNUSED
x"00", -- 0x38 UNUSED
x"00", -- 0x39 UNUSED
x"41", -- 0x3a SLTUI
x"41", -- 0x3b SGTUI
x"41", -- 0x3c SLEUI
x"41", -- 0x3d SGEUI
x"00", -- 0x3e UNUSED
x"00" -- 0x3f UNUSED
);
signal ucode_mem : ucode_mem_t := (
"00000000000000000000", -- 0x00 RESET
"00000000000001000000", -- 0x01 R [ID]
"00000000011000000000", -- R [EXE]
"01100000000000000000", -- R [MEM]
"10000000000000000000", -- R [WB]
"00000000000001000110", -- 0x05 J
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000001010110", -- 0x09 JAL
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000001100000", -- 0x0d BEQZ/BENZ
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000001100000", -- 0x11 ADDI/...
"00000000011010000000",
"01100000000000000000",
"10000000000000000000",
"00000000000001001010", -- 0x15 JR
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000001001010", -- 0x19 JALR
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000000000000", -- 0x1d NOP
"00000000000000000000",
"00000000000000000000",
"00000000000000000000",
"00000000000001000000", -- 0x21 LB
"00000000011110000000",
"01111010100000000000",
"10000000000000000000",
"00000000000001000000", -- 0x25 LH
"00000000011110000000",
"01111001100000000000",
"10000000000000000000",
"00000000000001000000", -- 0x29 LW
"00000000011110000000",
"01111000000000000000",
"10000000000000000000",
"00000000000001000000", -- 0x2d LBU
"00000000011110000000",
"01111010000000000000",
"10000000000000000000",
"00000000000001000000", -- 0x31 LHU
"00000000011110000000",
"01111001000000000000",
"10000000000000000000",
"00000000000001000000", -- 0x35 SB
"00000000010010000000",
"01000110000000000000",
"00000000000000000000",
"00000000000001000000", -- 0x39 SH
"00000000010010000000",
"01000101000000000000",
"00000000000000000000",
"00000000000001000000", -- 0x3d SW
"00000000010010000000",
"01000100000000000000",
"00000000000000000000",
"00000000000001000000", -- 0x41 ADDUI/...
"00000000011010000000",
"01100000000000000000",
"10000000000000000000"
);
signal cw1 : std_logic_vector(CWRD_SIZE-1 downto 0):=(CW_S1_LATCH=>'1', others=>'0');
signal cw2 : std_logic_vector(CWRD_SIZE-1 downto 0);
signal cw3 : std_logic_vector(CWRD_SIZE-1 downto 0);
signal cw4 : std_logic_vector(CWRD_SIZE-1 downto 0);
signal cw5 : std_logic_vector(CWRD_SIZE-1 downto 0);
signal cw_temp : std_logic_vector(CWRD_SIZE-1 downto 0);
signal cw_mask : std_logic_vector(CWRD_SIZE-1 downto 0);
signal upc2 : integer range 0 to 131072:=0;
signal upc3 : integer range 0 to 131072:=0;
signal upc4 : integer range 0 to 131072:=0;
signal upc5 : integer range 0 to 131072:=0;
signal i_count : integer range 0 to PIPELINE_STAGE;
signal relc : std_logic_vector(OPCD_SIZE+1 downto 0);
signal calu2 : std_logic_vector(CALU_SIZE-1 downto 0);
signal taken_flag: std_logic_vector(CWRD_SIZE-1 downto 0);
begin
cw1 <= (CW_S1_LATCH=>'1', others=>'0');
cw2 <= ucode_mem(upc2);
cw3 <= ucode_mem(upc3);
cw4 <= ucode_mem(upc4);
cw5 <= ucode_mem(upc5);
stall1 <= stall_flag(4);
stall2 <= stall_flag(3);
stall3 <= stall_flag(2);
stall4 <= stall_flag(1);
stall5 <= stall_flag(0);
cw_mask(CW_S1_LATCH downto 0) <= (others=> (not stall1));
cw_mask(CW_S2_LATCH downto CW_S1_LATCH+1) <= (others=> (not stall2));
cw_mask(CW_S3_LATCH downto CW_S2_LATCH+1) <= (others=> (not stall3));
cw_mask(CW_S4_LATCH downto CW_S3_LATCH+1) <= (others=> (not stall4));
cw_mask(CWRD_SIZE-1 downto CW_S4_LATCH+1) <= (others=> (not stall5));
taken_flag <= (CW_S2_JUMP => taken, others=>'0');
cw_temp <= (cw1 or cw2 or cw3 or cw4 or cw5 or taken_flag);
cw <= cw_temp and cw_mask;
relc <= reloc_mem(to_integer(unsigned(opcd)));
P_CALU: process (opcd, func)
begin
calu2 <= (others => '0');
if (opcd = OPCD_R) then
if (func=FUNC_ADD) or (func=FUNC_ADDU) then -- ADD
calu2 <= OP_ADD;
elsif (func=FUNC_AND) then -- AND
calu2 <= OP_AND;
elsif (func=FUNC_OR) then -- OR
calu2 <= OP_OR;
elsif (func=FUNC_XOR) then -- AND
calu2 <= OP_XOR;
elsif (func=FUNC_SLL) then -- SLL
calu2 <= OP_SLL;
elsif (func=FUNC_SRL) then -- SRL
calu2 <= OP_SRL;
elsif (func=FUNC_SRA) then -- SRA
calu2 <= OP_SRA;
elsif (func=FUNC_SUB) or (func=FUNC_SUBU) then -- SUB
calu2 <= OP_SUB;
elsif (func = FUNC_SGT) then -- SGT
calu2 <= OP_SGT;
elsif (func = FUNC_SGE) then -- SGE
calu2 <= OP_SGE;
elsif (func = FUNC_SLT) then -- SLT
calu2 <= OP_SLT;
elsif (func = FUNC_SLE) then -- SLE
calu2 <= OP_SLE;
elsif (func = FUNC_SGTU) then -- SGTU
calu2 <= OP_SGTU;
elsif (func = FUNC_SGEU) then -- SGEU
calu2 <= OP_SGEU;
elsif (func = FUNC_SLTU) then -- SLTU
calu2 <= OP_SLTU;
elsif (func = FUNC_SLEU) then -- SLEU
calu2 <= OP_SLEU;
elsif (func = FUNC_SEQ) then -- SEQ
calu2 <= OP_SEQ;
elsif (func = FUNC_SNE) then -- SNE
calu2 <= OP_SNE;
else
calu2 <= OP_ADD;
end if;
elsif (opcd=OPCD_F) then
if (func=FUNC_MULTU) then -- MULTU
calu2 <= OP_MULTU;
elsif (func=FUNC_MULT) then -- MULT
calu2 <= OP_MULT;
elsif (func=FUNC_DIVU) then -- DIVU
calu2 <= OP_DIVU;
elsif (func=FUNC_DIV) then -- DIV
calu2 <= OP_DIV;
elsif (func=FUNC_SQRT) then -- SQRT
calu2 <= OP_SQRT;
end if;
elsif (opcd=OPCD_ADDI) or (opcd=OPCD_ADDUI) then -- ADD
calu2 <= OP_ADD;
elsif (opcd=OPCD_SUBI) or (opcd=OPCD_SUBUI) then -- SUB
calu2 <= OP_SUB;
elsif opcd=OPCD_ANDI then -- AND
calu2 <= OP_AND;
elsif opcd=OPCD_ORI then -- OR
calu2 <= OP_OR;
elsif opcd=OPCD_XORI then -- XOR
calu2 <= OP_XOR;
elsif opcd=OPCD_SLLI then -- SLL
calu2 <= OP_SLL;
elsif opcd=OPCD_SRLI then -- SRL
calu2 <= OP_SRL;
elsif opcd=OPCD_SRAI then -- SRA
calu2 <= OP_SRA;
elsif opcd=OPCD_SEQI then -- SEQ
calu2 <= OP_SEQ;
elsif opcd=OPCD_SNEI then -- SNE
calu2 <= OP_SNE;
elsif opcd=OPCD_SLTI then -- SLT
calu2 <= OP_SLT;
elsif opcd=OPCD_SGTI then -- SGT
calu2 <= OP_SGT;
elsif opcd=OPCD_SLEI then -- SLE
calu2 <= OP_SLE;
elsif opcd=OPCD_SGEI then -- SGE
calu2 <= OP_SGE;
elsif opcd=OPCD_SLTUI then -- SLTU
calu2 <= OP_SLTU;
elsif opcd=OPCD_SGTUI then -- SGTU
calu2 <= OP_SGTU;
elsif opcd=OPCD_SLEUI then -- SLEU
calu2 <= OP_SLEU;
elsif opcd=OPCD_SGEUI then -- SGEU
calu2 <= OP_SGEU;
else
calu2 <= OP_ADD;
end if;
end process;
upc2 <= to_integer(unsigned(relc)) when (stall2='0') else 0 when (rst='0');
P_CW: process (clk, rst)
begin
if rst = '0' then
-- upc2 <= 0;
upc3 <= 0;
upc4 <= 0;
upc5 <= 0;
elsif clk'event and clk = '1' then
-- if stall2='0' then
-- upc2 <= to_integer(unsigned(relc));
-- end if;
if (upc2 /= 0) and (stall3='0') then
upc3 <= upc2+1;
calu <= calu2;
end if;
if (upc3 /= 0) and (stall4='0') then
upc4 <= upc3+1;
end if;
if (upc4 /= 0) and (stall5='0') then
upc5 <= upc4+1;
end if;
end if;
end process;
end cw_generator_arch;
|
mit
|
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors-
|
DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/plasma/mlite_pack/mlite_pack.vhd
|
2
|
21630
|
---------------------------------------------------------------------
-- TITLE: Plasma Misc. Package
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/15/01
-- FILENAME: mlite_pack.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Data types, constants, and add functions needed for the Plasma CPU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package mlite_pack is
constant ZERO : std_logic_vector(31 downto 0) :=
"00000000000000000000000000000000";
constant ONES : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
--make HIGH_Z equal to ZERO if compiler complains
constant HIGH_Z : std_logic_vector(31 downto 0) :=
"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
subtype alu_function_type is std_logic_vector(3 downto 0);
constant ALU_NOTHING : alu_function_type := "0000";
constant ALU_ADD : alu_function_type := "0001";
constant ALU_SUBTRACT : alu_function_type := "0010";
constant ALU_LESS_THAN : alu_function_type := "0011";
constant ALU_LESS_THAN_SIGNED : alu_function_type := "0100";
constant ALU_OR : alu_function_type := "0101";
constant ALU_AND : alu_function_type := "0110";
constant ALU_XOR : alu_function_type := "0111";
constant ALU_NOR : alu_function_type := "1000";
subtype shift_function_type is std_logic_vector(1 downto 0);
constant SHIFT_NOTHING : shift_function_type := "00";
constant SHIFT_LEFT_UNSIGNED : shift_function_type := "01";
constant SHIFT_RIGHT_SIGNED : shift_function_type := "11";
constant SHIFT_RIGHT_UNSIGNED : shift_function_type := "10";
subtype mult_function_type is std_logic_vector(3 downto 0);
constant MULT_NOTHING : mult_function_type := "0000";
constant MULT_READ_LO : mult_function_type := "0001";
constant MULT_READ_HI : mult_function_type := "0010";
constant MULT_WRITE_LO : mult_function_type := "0011";
constant MULT_WRITE_HI : mult_function_type := "0100";
constant MULT_MULT : mult_function_type := "0101";
constant MULT_SIGNED_MULT : mult_function_type := "0110";
constant MULT_DIVIDE : mult_function_type := "0111";
constant MULT_SIGNED_DIVIDE : mult_function_type := "1000";
subtype a_source_type is std_logic_vector(1 downto 0);
constant A_FROM_REG_SOURCE : a_source_type := "00";
constant A_FROM_IMM10_6 : a_source_type := "01";
constant A_FROM_PC : a_source_type := "10";
subtype b_source_type is std_logic_vector(1 downto 0);
constant B_FROM_REG_TARGET : b_source_type := "00";
constant B_FROM_IMM : b_source_type := "01";
constant B_FROM_SIGNED_IMM : b_source_type := "10";
constant B_FROM_IMMX4 : b_source_type := "11";
subtype c_source_type is std_logic_vector(2 downto 0);
constant C_FROM_NULL : c_source_type := "000";
constant C_FROM_ALU : c_source_type := "001";
constant C_FROM_SHIFT : c_source_type := "001"; --same as alu
constant C_FROM_MULT : c_source_type := "001"; --same as alu
constant C_FROM_MEMORY : c_source_type := "010";
constant C_FROM_PC : c_source_type := "011";
constant C_FROM_PC_PLUS4 : c_source_type := "100";
constant C_FROM_IMM_SHIFT16: c_source_type := "101";
constant C_FROM_REG_SOURCEN: c_source_type := "110";
subtype pc_source_type is std_logic_vector(1 downto 0);
constant FROM_INC4 : pc_source_type := "00";
constant FROM_OPCODE25_0 : pc_source_type := "01";
constant FROM_BRANCH : pc_source_type := "10";
constant FROM_LBRANCH : pc_source_type := "11";
subtype branch_function_type is std_logic_vector(2 downto 0);
constant BRANCH_LTZ : branch_function_type := "000";
constant BRANCH_LEZ : branch_function_type := "001";
constant BRANCH_EQ : branch_function_type := "010";
constant BRANCH_NE : branch_function_type := "011";
constant BRANCH_GEZ : branch_function_type := "100";
constant BRANCH_GTZ : branch_function_type := "101";
constant BRANCH_YES : branch_function_type := "110";
constant BRANCH_NO : branch_function_type := "111";
-- mode(32=1,16=2,8=3), signed, write
subtype mem_source_type is std_logic_vector(3 downto 0);
constant MEM_FETCH : mem_source_type := "0000";
constant MEM_READ32 : mem_source_type := "0100";
constant MEM_WRITE32 : mem_source_type := "0101";
constant MEM_READ16 : mem_source_type := "1000";
constant MEM_READ16S : mem_source_type := "1010";
constant MEM_WRITE16 : mem_source_type := "1001";
constant MEM_READ8 : mem_source_type := "1100";
constant MEM_READ8S : mem_source_type := "1110";
constant MEM_WRITE8 : mem_source_type := "1101";
function bv_adder(a : in std_logic_vector;
b : in std_logic_vector;
do_add: in std_logic) return std_logic_vector;
function bv_negate(a : in std_logic_vector) return std_logic_vector;
function bv_increment(a : in std_logic_vector(31 downto 2)
) return std_logic_vector;
function bv_inc(a : in std_logic_vector
) return std_logic_vector;
-- For Altera
COMPONENT lpm_ram_dp
GENERIC (
lpm_width : NATURAL;
lpm_widthad : NATURAL;
rden_used : STRING;
intended_device_family : STRING;
lpm_indata : STRING;
lpm_wraddress_control : STRING;
lpm_rdaddress_control : STRING;
lpm_outdata : STRING;
use_eab : STRING;
lpm_type : STRING);
PORT (
wren : IN STD_LOGIC ;
wrclock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (lpm_widthad-1 DOWNTO 0);
wraddress : IN STD_LOGIC_VECTOR (lpm_widthad-1 DOWNTO 0));
END COMPONENT;
-- For Altera
component LPM_RAM_DQ
generic (
LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_ADDRESS_CONTROL: string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := "LPM_RAM_DQ";
USE_EAB : string := "OFF";
INTENDED_DEVICE_FAMILY : string := "UNUSED";
LPM_HINT : string := "UNUSED");
port (
DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
ADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
INCLOCK : in std_logic := '0';
OUTCLOCK : in std_logic := '0';
WE : in std_logic;
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
-- For Xilinx
component RAM16X1D
-- synthesis translate_off
generic (INIT : bit_vector := X"16");
-- synthesis translate_on
port (DPO : out STD_ULOGIC;
SPO : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
D : in STD_ULOGIC;
DPRA0 : in STD_ULOGIC;
DPRA1 : in STD_ULOGIC;
DPRA2 : in STD_ULOGIC;
DPRA3 : in STD_ULOGIC;
WCLK : in STD_ULOGIC;
WE : in STD_ULOGIC);
end component;
component pc_next
port(clk : in std_logic;
reset_in : in std_logic;
pc_new : in std_logic_vector(31 downto 2);
take_branch : in std_logic;
pause_in : in std_logic;
opcode25_0 : in std_logic_vector(25 downto 0);
pc_source : in pc_source_type;
pc_future : out std_logic_vector(31 downto 2);
pc_current : out std_logic_vector(31 downto 2);
pc_plus4 : out std_logic_vector(31 downto 2));
end component;
component mem_ctrl
port(clk : in std_logic;
reset_in : in std_logic;
pause_in : in std_logic;
nullify_op : in std_logic;
address_pc : in std_logic_vector(31 downto 2);
opcode_out : out std_logic_vector(31 downto 0);
address_in : in std_logic_vector(31 downto 0);
mem_source : in mem_source_type;
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
pause_out : out std_logic;
address_next : out std_logic_vector(31 downto 2);
byte_we_next : out std_logic_vector(3 downto 0);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0));
end component;
component control
port(opcode : in std_logic_vector(31 downto 0);
intr_signal : in std_logic;
rs_index : out std_logic_vector(5 downto 0);
rt_index : out std_logic_vector(5 downto 0);
rd_index : out std_logic_vector(5 downto 0);
imm_out : out std_logic_vector(15 downto 0);
alu_func : out alu_function_type;
shift_func : out shift_function_type;
mult_func : out mult_function_type;
branch_func : out branch_function_type;
a_source_out : out a_source_type;
b_source_out : out b_source_type;
c_source_out : out c_source_type;
pc_source_out: out pc_source_type;
mem_source_out:out mem_source_type;
exception_out: out std_logic);
end component;
component reg_bank
generic(memory_type : string := "ALTERA_LPM");
port(clk : in std_logic;
reset_in : in std_logic;
pause : in std_logic;
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
rd_index : in std_logic_vector(5 downto 0);
reg_source_out : out std_logic_vector(31 downto 0);
reg_target_out : out std_logic_vector(31 downto 0);
reg_dest_new : in std_logic_vector(31 downto 0);
intr_enable : out std_logic);
end component;
component bus_mux
port(imm_in : in std_logic_vector(15 downto 0);
reg_source : in std_logic_vector(31 downto 0);
a_mux : in a_source_type;
a_out : out std_logic_vector(31 downto 0);
reg_target : in std_logic_vector(31 downto 0);
b_mux : in b_source_type;
b_out : out std_logic_vector(31 downto 0);
c_bus : in std_logic_vector(31 downto 0);
c_memory : in std_logic_vector(31 downto 0);
c_pc : in std_logic_vector(31 downto 2);
c_pc_plus4 : in std_logic_vector(31 downto 2);
c_mux : in c_source_type;
reg_dest_out : out std_logic_vector(31 downto 0);
branch_func : in branch_function_type;
take_branch : out std_logic);
end component;
component alu
generic(alu_type : string := "DEFAULT");
port(a_in : in std_logic_vector(31 downto 0);
b_in : in std_logic_vector(31 downto 0);
alu_function : in alu_function_type;
c_alu : out std_logic_vector(31 downto 0));
end component;
component shifter
generic(shifter_type : string := "DEFAULT" );
port(value : in std_logic_vector(31 downto 0);
shift_amount : in std_logic_vector(4 downto 0);
shift_func : in shift_function_type;
c_shift : out std_logic_vector(31 downto 0));
end component;
component mult
generic(mult_type : string := "DEFAULT");
port(clk : in std_logic;
reset_in : in std_logic;
a, b : in std_logic_vector(31 downto 0);
mult_func : in mult_function_type;
c_mult : out std_logic_vector(31 downto 0);
pause_out : out std_logic);
end component;
component pipeline
port(clk : in std_logic;
reset : in std_logic;
a_bus : in std_logic_vector(31 downto 0);
a_busD : out std_logic_vector(31 downto 0);
b_bus : in std_logic_vector(31 downto 0);
b_busD : out std_logic_vector(31 downto 0);
alu_func : in alu_function_type;
alu_funcD : out alu_function_type;
shift_func : in shift_function_type;
shift_funcD : out shift_function_type;
mult_func : in mult_function_type;
mult_funcD : out mult_function_type;
reg_dest : in std_logic_vector(31 downto 0);
reg_destD : out std_logic_vector(31 downto 0);
rd_index : in std_logic_vector(5 downto 0);
rd_indexD : out std_logic_vector(5 downto 0);
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
pc_source : in pc_source_type;
mem_source : in mem_source_type;
a_source : in a_source_type;
b_source : in b_source_type;
c_source : in c_source_type;
c_bus : in std_logic_vector(31 downto 0);
pause_any : in std_logic;
pause_pipeline : out std_logic);
end component;
component mlite_cpu
generic(memory_type : string := "ALTERA_LPM"; --ALTERA_LPM, or DUAL_PORT_
mult_type : string := "DEFAULT";
shifter_type : string := "DEFAULT";
alu_type : string := "DEFAULT";
pipeline_stages : natural := 2); --2 or 3
port(clk : in std_logic;
reset_in : in std_logic;
intr_in : in std_logic;
address_next : out std_logic_vector(31 downto 2); --for synch ram
byte_we_next : out std_logic_vector(3 downto 0);
opcode_test_out : out std_logic_vector(31 downto 0);
pc_future_test_out : out std_logic_vector(31 downto 2);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0);
mem_pause : in std_logic);
end component;
component ram
generic(memory_type : string := "DEFAULT");
port(clk : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end component; --ram
component uart
generic(log_file : string := "UNUSED");
port(clk : in std_logic;
reset : in std_logic;
enable_read : in std_logic;
enable_write : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
uart_read : in std_logic;
uart_write : out std_logic;
busy_write : out std_logic;
data_avail : out std_logic);
end component; --uart
component eth_dma
port(clk : in std_logic; --25 MHz
reset : in std_logic;
enable_eth : in std_logic;
select_eth : in std_logic;
rec_isr : out std_logic;
send_isr : out std_logic;
address : out std_logic_vector(31 downto 2); --to DDR
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
pause_in : in std_logic;
mem_address : in std_logic_vector(31 downto 2); --from CPU
mem_byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
pause_out : out std_logic;
E_RX_CLK : in std_logic; --2.5 MHz receive
E_RX_DV : in std_logic; --data valid
E_RXD : in std_logic_vector(3 downto 0); --receive nibble
E_TX_CLK : in std_logic; --2.5 MHz transmit
E_TX_EN : out std_logic; --transmit enable
E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble
end component; --eth_dma
component plasma
generic(memory_type : string := "XILINX_X16"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED";
ethernet : std_logic := '0');
port(clk : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
mem_pause_in : in std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0));
end component; --plasma
component ddr_ctrl
port(clk : in std_logic;
clk_2x : in std_logic;
reset_in : in std_logic;
address : in std_logic_vector(25 downto 2);
byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
data_r : out std_logic_vector(31 downto 0);
active : in std_logic;
pause : out std_logic;
SD_CK_P : out std_logic; --clock_positive
SD_CK_N : out std_logic; --clock_negative
SD_CKE : out std_logic; --clock_enable
SD_BA : out std_logic_vector(1 downto 0); --bank_address
SD_A : out std_logic_vector(12 downto 0); --address(row or col)
SD_CS : out std_logic; --chip_select
SD_RAS : out std_logic; --row_address_strobe
SD_CAS : out std_logic; --column_address_strobe
SD_WE : out std_logic; --write_enable
SD_DQ : inout std_logic_vector(15 downto 0); --data
SD_UDM : out std_logic; --upper_byte_enable
SD_UDQS : inout std_logic; --upper_data_strobe
SD_LDM : out std_logic; --low_byte_enable
SD_LDQS : inout std_logic); --low_data_strobe
end component; --ddr
end; --package mlite_pack
package body mlite_pack is
function bv_adder(a : in std_logic_vector;
b : in std_logic_vector;
do_add: in std_logic) return std_logic_vector is
variable carry_in : std_logic;
variable bb : std_logic_vector(a'length-1 downto 0);
variable result : std_logic_vector(a'length downto 0);
begin
if do_add = '1' then
bb := b;
carry_in := '0';
else
bb := not b;
carry_in := '1';
end if;
for index in 0 to a'length-1 loop
result(index) := a(index) xor bb(index) xor carry_in;
carry_in := (carry_in and (a(index) or bb(index))) or
(a(index) and bb(index));
end loop;
result(a'length) := carry_in xnor do_add;
return result;
end; --function
function bv_negate(a : in std_logic_vector) return std_logic_vector is
variable carry_in : std_logic;
variable not_a : std_logic_vector(a'length-1 downto 0);
variable result : std_logic_vector(a'length-1 downto 0);
begin
not_a := not a;
carry_in := '1';
for index in a'reverse_range loop
result(index) := not_a(index) xor carry_in;
carry_in := carry_in and not_a(index);
end loop;
return result;
end; --function
function bv_increment(a : in std_logic_vector(31 downto 2)
) return std_logic_vector is
variable carry_in : std_logic;
variable result : std_logic_vector(31 downto 2);
begin
carry_in := '1';
for index in 2 to 31 loop
result(index) := a(index) xor carry_in;
carry_in := a(index) and carry_in;
end loop;
return result;
end; --function
function bv_inc(a : in std_logic_vector
) return std_logic_vector is
variable carry_in : std_logic;
variable result : std_logic_vector(a'length-1 downto 0);
begin
carry_in := '1';
for index in 0 to a'length-1 loop
result(index) := a(index) xor carry_in;
carry_in := a(index) and carry_in;
end loop;
return result;
end; --function
end; --package body
|
mit
|
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors-
|
DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/to_send/ngnp_added_monitor/ngnp/src/tmp/mb_lite/decode.vhd
|
3
|
17812
|
----------------------------------------------------------------------------------------------
--
-- Input file : decode.vhd
-- Design name : decode
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : This combined register file and decoder uses three Dual Port
-- read after write Random Access Memory components. Every clock
-- cycle three data values can be read (ra, rb and rd) and one value
-- can be stored.
--
----------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
LIBRARY work;
USE work.config_Pkg.ALL;
USE work.core_Pkg.ALL;
USE work.std_Pkg.ALL;
ENTITY decode IS GENERIC
(
G_INTERRUPT : boolean := CFG_INTERRUPT;
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
G_USE_BARREL : boolean := CFG_USE_BARREL;
G_DEBUG : boolean := CFG_DEBUG
);
PORT
(
decode_o : OUT decode_out_type;
gprf_o : OUT gprf_out_type;
decode_i : IN decode_in_type;
ena_i : IN std_ulogic;
rst_i : IN std_ulogic;
clk_i : IN std_ulogic
);
END decode;
ARCHITECTURE arch OF decode IS
TYPE decode_reg_type IS RECORD
instruction : std_ulogic_vector(CFG_IMEM_WIDTH - 1 DOWNTO 0);
program_counter : std_ulogic_vector(CFG_IMEM_SIZE - 1 DOWNTO 0);
immediate : std_ulogic_vector(15 DOWNTO 0);
is_immediate : std_ulogic;
msr_interrupt_enable : std_ulogic;
interrupt : std_ulogic;
delay_interrupt : std_ulogic;
END RECORD;
SIGNAL r, rin : decode_out_type;
SIGNAL reg, regin : decode_reg_type;
SIGNAL wb_dat_d : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
BEGIN
decode_o.imm <= r.imm;
decode_o.ctrl_ex <= r.ctrl_ex;
decode_o.ctrl_mem <= r.ctrl_mem;
decode_o.ctrl_wb <= r.ctrl_wb;
decode_o.reg_a <= r.reg_a;
decode_o.reg_b <= r.reg_b;
decode_o.hazard <= r.hazard;
decode_o.program_counter <= r.program_counter;
decode_o.fwd_dec_result <= r.fwd_dec_result;
decode_o.fwd_dec <= r.fwd_dec;
decode_comb: PROCESS(decode_i,decode_i.ctrl_wb,
decode_i.ctrl_mem_wb,
decode_i.ctrl_mem_wb.transfer_size,
r,r.ctrl_ex,r.ctrl_mem,
r.ctrl_mem.transfer_size,r.ctrl_wb,
r.fwd_dec,reg)
VARIABLE v : decode_out_type;
VARIABLE v_reg : decode_reg_type;
VARIABLE opcode : std_ulogic_vector(5 DOWNTO 0);
VARIABLE instruction : std_ulogic_vector(CFG_IMEM_WIDTH - 1 DOWNTO 0);
VARIABLE program_counter : std_ulogic_vector(CFG_IMEM_SIZE - 1 DOWNTO 0);
VARIABLE mem_result : std_ulogic_vector(CFG_DMEM_WIDTH - 1 DOWNTO 0);
BEGIN
v := r;
v_reg := reg;
-- Default register values (NOP)
v_reg.immediate := (OTHERS => '0');
v_reg.is_immediate := '0';
v_reg.program_counter := decode_i.program_counter;
v_reg.instruction := decode_i.instruction;
IF decode_i.ctrl_mem_wb.mem_read = '1' THEN
mem_result := align_mem_load(decode_i.mem_result, decode_i.ctrl_mem_wb.transfer_size, decode_i.alu_result(1 DOWNTO 0));
ELSE
mem_result := decode_i.alu_result;
END IF;
wb_dat_d <= mem_result;
IF G_INTERRUPT = true THEN
v_reg.delay_interrupt := '0';
END IF;
IF CFG_REG_FWD_WB = true THEN
v.fwd_dec_result := mem_result;
v.fwd_dec := decode_i.ctrl_wb;
ELSE
v.fwd_dec_result := (OTHERS => '0');
v.fwd_dec.reg_d := (OTHERS => '0');
v.fwd_dec.reg_write := '0';
END IF;
IF (NOT decode_i.flush_id AND r.ctrl_mem.mem_read AND (compare(decode_i.instruction(20 DOWNTO 16), r.ctrl_wb.reg_d) OR compare(decode_i.instruction(15 DOWNTO 11), r.ctrl_wb.reg_d))) = '1' THEN
-- A hazard occurred on register a or b
-- set current instruction and program counter to 0
instruction := (OTHERS => '0');
program_counter := (OTHERS => '0');
v.hazard := '1';
ELSIF CFG_MEM_FWD_WB = false AND (NOT decode_i.flush_id AND r.ctrl_mem.mem_read AND compare(decode_i.instruction(25 DOWNTO 21), r.ctrl_wb.reg_d)) = '1' THEN
-- A hazard occurred on register d
-- set current instruction and program counter to 0
instruction := (OTHERS => '0');
program_counter := (OTHERS => '0');
v.hazard := '1';
ELSIF r.hazard = '1' THEN
-- Recover from hazard. Insert latched instruction
instruction := reg.instruction;
program_counter := reg.program_counter;
v.hazard := '0';
ELSE
instruction := decode_i.instruction;
program_counter := decode_i.program_counter;
v.hazard := '0';
END IF;
v.program_counter := program_counter;
opcode := instruction(31 DOWNTO 26);
v.ctrl_wb.reg_d := instruction(25 DOWNTO 21);
v.reg_a := instruction(20 DOWNTO 16);
v.reg_b := instruction(15 DOWNTO 11);
-- SET IMM value
IF reg.is_immediate = '1' THEN
v.imm := reg.immediate & instruction(15 DOWNTO 0);
ELSE
v.imm := sign_extend(instruction(15 DOWNTO 0), instruction(15), 32);
END IF;
-- Register if an interrupt occurs
IF G_INTERRUPT = true THEN
IF v_reg.msr_interrupt_enable = '1' AND decode_i.interrupt = '1' THEN
v_reg.interrupt := '1';
v_reg.msr_interrupt_enable := '0';
END IF;
END IF;
v.ctrl_ex.alu_op := ALU_ADD;
v.ctrl_ex.alu_src_a := ALU_SRC_REGA;
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
v.ctrl_ex.operation := '0';
v.ctrl_ex.carry := CARRY_ZERO;
v.ctrl_ex.carry_keep := CARRY_NOT_KEEP;
v.ctrl_ex.delay := '0';
v.ctrl_ex.branch_cond := NOP;
v.ctrl_mem.mem_write := '0';
v.ctrl_mem.transfer_size := WORD;
v.ctrl_mem.mem_read := '0';
v.ctrl_wb.reg_write := '0';
IF G_INTERRUPT = true AND (v_reg.interrupt = '1' AND reg.delay_interrupt = '0' AND decode_i.flush_id = '0' AND v.hazard = '0' AND r.ctrl_ex.delay = '0' AND reg.is_immediate = '0') THEN
-- IF an interrupt occured
-- AND the current instruction is not a branch or return instruction,
-- AND the current instruction is not in a delay slot,
-- AND this is instruction is not preceded by an IMM instruction, than handle the interrupt.
v_reg.msr_interrupt_enable := '0';
v_reg.interrupt := '0';
v.reg_a := (OTHERS => '0');
v.reg_b := (OTHERS => '0');
v.imm := X"00000010";
v.ctrl_wb.reg_d := "01110";
v.ctrl_ex.branch_cond := BNC;
v.ctrl_ex.alu_src_a := ALU_SRC_ZERO;
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
v.ctrl_wb.reg_write := '1';
ELSIF (decode_i.flush_id OR v.hazard) = '1' THEN
-- clearing these registers is not necessary, but facilitates debugging.
-- On the other hand performance improves when disabled.
IF G_DEBUG = true THEN
v.program_counter := (OTHERS => '0');
v.ctrl_wb.reg_d := (OTHERS => '0');
v.reg_a := (OTHERS => '0');
v.reg_b := (OTHERS => '0');
v.imm := (OTHERS => '0');
END IF;
ELSIF is_zero(opcode(5 DOWNTO 4)) = '1' THEN
-- ADD, SUBTRACT OR COMPARE
-- Alu operation
v.ctrl_ex.alu_op := ALU_ADD;
-- Source operand A
IF opcode(0) = '1' THEN
v.ctrl_ex.alu_src_a := ALU_SRC_NOT_REGA;
ELSE
v.ctrl_ex.alu_src_a := ALU_SRC_REGA;
END IF;
-- Source operand B
IF opcode(3) = '1' THEN
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
ELSE
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
END IF;
IF (compare(opcode, "000101") AND instruction(1)) = '1' THEN
v.ctrl_ex.operation := '1';
END IF;
-- Carry
CASE opcode(1 DOWNTO 0) IS
WHEN "00" => v.ctrl_ex.carry := CARRY_ZERO;
WHEN "01" => v.ctrl_ex.carry := CARRY_ONE;
WHEN OTHERS => v.ctrl_ex.carry := CARRY_ALU;
END CASE;
-- Carry keep
IF opcode(2) = '1' THEN
v.ctrl_ex.carry_keep := CARRY_KEEP;
ELSE
v.ctrl_ex.carry_keep := CARRY_NOT_KEEP;
END IF;
-- Flag writeback if reg_d != 0
v.ctrl_wb.reg_write := is_not_zero(v.ctrl_wb.reg_d);
ELSIF (compare(opcode(5 DOWNTO 2), "1000") OR compare(opcode(5 DOWNTO 2), "1010")) = '1' THEN
-- OR, AND, XOR, ANDN
-- ORI, ANDI, XORI, ANDNI
CASE opcode(1 DOWNTO 0) IS
WHEN "00" => v.ctrl_ex.alu_op := ALU_OR;
WHEN "10" => v.ctrl_ex.alu_op := ALU_XOR;
WHEN OTHERS => v.ctrl_ex.alu_op := ALU_AND;
END CASE;
IF opcode(3) = '1' AND compare(opcode(1 DOWNTO 0), "11") = '1' THEN
v.ctrl_ex.alu_src_b := ALU_SRC_NOT_IMM;
ELSIF opcode(3) = '1' THEN
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
ELSIF opcode(3) = '0' AND compare(opcode(1 DOWNTO 0), "11") = '1' THEN
v.ctrl_ex.alu_src_b := ALU_SRC_NOT_REGB;
ELSE
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
END IF;
-- Flag writeback if reg_d != 0
v.ctrl_wb.reg_write := is_not_zero(v.ctrl_wb.reg_d);
ELSIF compare(opcode, "101100") = '1' THEN
-- IMM instruction
v_reg.immediate := instruction(15 DOWNTO 0);
v_reg.is_immediate := '1';
ELSIF compare(opcode, "100100") = '1' THEN
-- SHIFT, SIGN EXTEND
IF compare(instruction(6 DOWNTO 5), "11") = '1' THEN
IF instruction(0) = '1' THEN
v.ctrl_ex.alu_op:= ALU_SEXT16;
ELSE
v.ctrl_ex.alu_op:= ALU_SEXT8;
END IF;
ELSE
v.ctrl_ex.alu_op:= ALU_SHIFT;
CASE instruction(6 DOWNTO 5) IS
WHEN "10" => v.ctrl_ex.carry := CARRY_ZERO;
WHEN "01" => v.ctrl_ex.carry := CARRY_ALU;
WHEN OTHERS => v.ctrl_ex.carry := CARRY_ARITH;
END CASE;
END IF;
-- Flag writeback if reg_d != 0
v.ctrl_wb.reg_write := is_not_zero(v.ctrl_wb.reg_d);
ELSIF (compare(opcode, "100110") OR compare(opcode, "101110")) = '1' THEN
-- BRANCH UNCONDITIONAL
v.ctrl_ex.branch_cond := BNC;
IF opcode(3) = '1' THEN
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
ELSE
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
END IF;
-- WRITE THE RESULT ALSO TO REGISTER D
IF v.reg_a(2) = '1' THEN
-- Flag writeback if reg_d != 0
v.ctrl_wb.reg_write := is_not_zero(v.ctrl_wb.reg_d);
END IF;
IF v.reg_a(3) = '1' THEN
v.ctrl_ex.alu_src_a := ALU_SRC_ZERO;
ELSE
v.ctrl_ex.alu_src_a := ALU_SRC_PC;
END IF;
IF G_INTERRUPT = true THEN
v_reg.delay_interrupt := '1';
END IF;
v.ctrl_ex.delay := v.reg_a(4);
ELSIF (compare(opcode, "100111") OR compare(opcode, "101111")) = '1' THEN
-- BRANCH CONDITIONAL
v.ctrl_ex.alu_op := ALU_ADD;
v.ctrl_ex.alu_src_a := ALU_SRC_PC;
IF opcode(3) = '1' THEN
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
ELSE
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
END IF;
CASE v.ctrl_wb.reg_d(2 DOWNTO 0) IS
WHEN "000" => v.ctrl_ex.branch_cond := BEQ;
WHEN "001" => v.ctrl_ex.branch_cond := BNE;
WHEN "010" => v.ctrl_ex.branch_cond := BLT;
WHEN "011" => v.ctrl_ex.branch_cond := BLE;
WHEN "100" => v.ctrl_ex.branch_cond := BGT;
WHEN OTHERS => v.ctrl_ex.branch_cond := BGE;
END CASE;
IF G_INTERRUPT = true THEN
v_reg.delay_interrupt := '1';
END IF;
v.ctrl_ex.delay := v.ctrl_wb.reg_d(4);
ELSIF compare(opcode, "101101") = '1' THEN
-- RETURN
v.ctrl_ex.branch_cond := BNC;
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
v.ctrl_ex.delay := '1';
IF G_INTERRUPT = true THEN
IF v.ctrl_wb.reg_d(0) = '1' THEN
v_reg.msr_interrupt_enable := '1';
END IF;
v_reg.delay_interrupt := '1';
END IF;
ELSIF compare(opcode(5 DOWNTO 4), "11") = '1' THEN
-- SW, LW
v.ctrl_ex.alu_op := ALU_ADD;
v.ctrl_ex.alu_src_a := ALU_SRC_REGA;
IF opcode(3) = '1' THEN
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
ELSE
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
END IF;
v.ctrl_ex.carry := CARRY_ZERO;
IF opcode(2) = '1' THEN
-- Store
v.ctrl_mem.mem_write := '1';
v.ctrl_mem.mem_read := '0';
v.ctrl_wb.reg_write := '0';
ELSE
-- Load
v.ctrl_mem.mem_write := '0';
v.ctrl_mem.mem_read := '1';
v.ctrl_wb.reg_write := is_not_zero(v.ctrl_wb.reg_d);
END IF;
CASE opcode(1 DOWNTO 0) IS
WHEN "00" => v.ctrl_mem.transfer_size := BYTE;
WHEN "01" => v.ctrl_mem.transfer_size := HALFWORD;
WHEN OTHERS => v.ctrl_mem.transfer_size := WORD;
END CASE;
v.ctrl_ex.delay := '0';
ELSIF G_USE_HW_MUL = true AND (compare(opcode, "010000") OR compare(opcode, "011000")) = '1' THEN
v.ctrl_ex.alu_op := ALU_MUL;
IF opcode(3) = '1' THEN
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
ELSE
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
END IF;
v.ctrl_wb.reg_write := is_not_zero(v.ctrl_wb.reg_d);
ELSIF G_USE_BARREL = true AND (compare(opcode, "010001") OR compare(opcode, "011001")) = '1' THEN
v.ctrl_ex.alu_op := ALU_BS;
IF opcode(3) = '1' THEN
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
ELSE
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
END IF;
v.ctrl_wb.reg_write := is_not_zero(v.ctrl_wb.reg_d);
ELSE
-- UNKNOWN OPCODE
NULL;
END IF;
rin <= v;
regin <= v_reg;
END PROCESS;
decode_seq: PROCESS(clk_i)
PROCEDURE proc_reset_decode IS
BEGIN
r.reg_a <= (OTHERS => '0');
r.reg_b <= (OTHERS => '0');
r.imm <= (OTHERS => '0');
r.program_counter <= (OTHERS => '0');
r.hazard <= '0';
r.ctrl_ex.alu_op <= ALU_ADD;
r.ctrl_ex.alu_src_a <= ALU_SRC_REGA;
r.ctrl_ex.alu_src_b <= ALU_SRC_REGB;
r.ctrl_ex.operation <= '0';
r.ctrl_ex.carry <= CARRY_ZERO;
r.ctrl_ex.carry_keep <= CARRY_NOT_KEEP;
r.ctrl_ex.delay <= '0';
r.ctrl_ex.branch_cond <= NOP;
r.ctrl_mem.mem_write <= '0';
r.ctrl_mem.transfer_size <= WORD;
r.ctrl_mem.mem_read <= '0';
r.ctrl_wb.reg_d <= (OTHERS => '0');
r.ctrl_wb.reg_write <= '0';
r.fwd_dec_result <= (OTHERS => '0');
r.fwd_dec.reg_d <= (OTHERS => '0');
r.fwd_dec.reg_write <= '0';
reg.instruction <= (OTHERS => '0');
reg.program_counter <= (OTHERS => '0');
reg.immediate <= (OTHERS => '0');
reg.is_immediate <= '0';
reg.msr_interrupt_enable <= '1';
reg.interrupt <= '0';
reg.delay_interrupt <= '0';
END PROCEDURE proc_reset_decode;
BEGIN
IF rising_edge(clk_i) THEN
IF rst_i = '1' THEN
proc_reset_decode;
ELSIF ena_i = '1' THEN
r <= rin;
reg <= regin;
END IF;
END IF;
END PROCESS;
gprf0 : gprf PORT MAP
(
gprf_o => gprf_o,
gprf_i.adr_a_i => rin.reg_a,
gprf_i.adr_b_i => rin.reg_b,
gprf_i.adr_d_i => rin.ctrl_wb.reg_d,
gprf_i.dat_w_i => wb_dat_d,
gprf_i.adr_w_i => decode_i.ctrl_wb.reg_d,
gprf_i.wre_i => decode_i.ctrl_wb.reg_write,
ena_i => ena_i,
clk_i => clk_i
);
END arch;
|
mit
|
nczempin/NICNAC16
|
ipcore_dir/ROM01/simulation/bmg_tb_pkg.vhd
|
101
|
6006
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_tb_pkg.vhd
--
-- Description:
-- BMG Testbench Package files
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE :STRING)
RETURN STRING;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE :STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER;
END BMG_TB_PKG;
PACKAGE BODY BMG_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER IS
VARIABLE DIV : INTEGER;
BEGIN
DIV := DATA_VALUE/DIVISOR;
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
DIV := DIV+1;
END IF;
RETURN DIV;
END DIVROUNDUP;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE : STD_LOGIC)
RETURN STD_LOGIC IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER IS
VARIABLE RETVAL : INTEGER := 0;
BEGIN
IF CONDITION=FALSE THEN
RETVAL:=FALSE_CASE;
ELSE
RETVAL:=TRUE_CASE;
END IF;
RETURN RETVAL;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE : STRING)
RETURN STRING IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
-------------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER IS
VARIABLE WIDTH : INTEGER := 0;
VARIABLE CNT : INTEGER := 1;
BEGIN
IF (DATA_VALUE <= 1) THEN
WIDTH := 1;
ELSE
WHILE (CNT < DATA_VALUE) LOOP
WIDTH := WIDTH + 1;
CNT := CNT *2;
END LOOP;
END IF;
RETURN WIDTH;
END LOG2ROUNDUP;
END BMG_TB_PKG;
|
mit
|
herenvarno/dlx
|
dlx_vhd/src/a.b-DataPath.core/a.b.a-Alu.core/a.b.a.b-Shifter.vhd
|
1
|
2119
|
--------------------------------------------------------------------------------
-- FILE: Shifter
-- DESC: Shift A by B bits
--
-- Author:
-- Create: 2015-05-25
-- Update: 2015-05-27
-- Status: TESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Consts.all;
use work.Funcs.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity Shifter is
generic (
DATA_SIZE : integer := C_SYS_DATA_SIZE
);
port (
l_r : in std_logic; -- LEFT/RIGHT
l_a : in std_logic; -- LOGIC/ARITHMETIC
s_r : in std_logic; -- SHIFT/ROTATE
a : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
b : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
o : out std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0')
);
end Shifter;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture shifter_arch of Shifter is
constant B_SIZE : integer := MyLog2Ceil(DATA_SIZE);
begin
P0: process (a, b, l_r, l_a, s_r) is
begin
if s_r = '1' then
if l_r = '1' then
o <= to_StdLogicVector((to_bitvector(a)) ror (to_integer(unsigned(b(B_SIZE-1 downto 0)))));
else
o <= to_StdLogicVector((to_bitvector(a)) rol (to_integer(unsigned(b(B_SIZE-1 downto 0)))));
end if;
else
if l_r = '1' then
if l_a = '1' then
o <= to_StdLogicVector((to_bitvector(a)) sra (to_integer(unsigned(b(B_SIZE-1 downto 0)))));
else
o <= to_StdLogicVector((to_bitvector(a)) srl (to_integer(unsigned(b(B_SIZE-1 downto 0)))));
end if;
else
if l_a = '1' then
o <= to_StdLogicVector((to_bitvector(a)) sla (to_integer(unsigned(b(B_SIZE-1 downto 0)))));
else
o <= to_StdLogicVector((to_bitvector(a)) sll (to_integer(unsigned(b(B_SIZE-1 downto 0)))));
end if;
end if;
end if;
end process;
end shifter_arch;
|
mit
|
herenvarno/dlx
|
dlx_vhd/tb/old_tb/a.b.c-tbRegisterFile.vhd
|
1
|
2481
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Consts.all;
use work.Funcs.all;
entity tbRegisterFile is
end tbRegisterFile;
architecture tb_register_file_arch of tbRegisterFile is
signal clk: std_logic := '0';
signal rst: std_logic;
signal en: std_logic;
signal rd1_en: std_logic;
signal rd2_en: std_logic;
signal wr_en: std_logic;
signal rd1_addr: std_logic_vector(4 downto 0);
signal rd2_addr: std_logic_vector(4 downto 0);
signal wr_addr: std_logic_vector(4 downto 0);
signal d_out1: std_logic_vector(31 downto 0);
signal d_out2: std_logic_vector(31 downto 0);
signal d_in: std_logic_vector(31 downto 0);
component RegisterFile is
generic(
DATA_SIZE : integer := C_SYS_DATA_SIZE;
REG_NUM : integer := C_REG_NUM
);
port(
clk : in std_logic; -- clock
rst : in std_logic; -- reset
en : in std_logic; -- enable
rd1_en : in std_logic; -- read port 1
rd2_en : in std_logic; -- read port 2
wr_en : in std_logic; -- write port
rd1_addr: in std_logic_vector(MyLog2Ceil(REG_NUM)-1 downto 0); -- address of read port 1
rd2_addr: in std_logic_vector(MyLog2Ceil(REG_NUM)-1 downto 0); -- address of read port 2
wr_addr : in std_logic_vector(MyLog2Ceil(REG_NUM)-1 downto 0); -- address of write port
d_out1 : out std_logic_vector(DATA_SIZE-1 downto 0); -- data out 1 bus
d_out2 : out std_logic_vector(DATA_SIZE-1 downto 0); -- data out 2 bus
d_in : in std_logic_vector(DATA_SIZE-1 downto 0) -- data in bus
);
end component;
begin
RG:RegisterFile
generic map(32, 32)
port map (clk, rst, en, rd1_en, rd2_en, wr_en, rd1_addr, rd2_addr, wr_addr, d_out1, d_out2, d_in);
rst <= '0','1' after 5 ns;
en <= '0','1' after 3 ns;
wr_en <= '0','1' after 6 ns, '0' after 7 ns, '1' after 10 ns, '0' after 20 ns;
rd1_en <= '1','0' after 5 ns, '1' after 13 ns, '0' after 20 ns;
rd2_en <= '0','1' after 17 ns;
wr_addr <= "10110", "01000" after 9 ns, "00000" after 19 ns;
rd1_addr <="10110", "01000" after 9 ns, "00000" after 19 ns;
rd2_addr <= "11100", "01000" after 9 ns;
d_in<=(others => '0'),(others => '1') after 8 ns;
PCLOCK : process(clk)
begin
clk <= not(clk) after 0.5 ns;
end process;
end tb_register_file_arch;
configuration tb_register_file_cfg of tbRegisterFile is
for tb_register_file_arch
end for;
end tb_register_file_cfg;
|
mit
|
jakubcabal/pipemania-fpga-game
|
source/comp/game/random_decoder_fifo.vhd
|
1
|
6406
|
--------------------------------------------------------------------------------
-- PROJECT: PIPE MANIA - GAME FOR FPGA
--------------------------------------------------------------------------------
-- NAME: RANDOM_DECODER_FIFO
-- AUTHORS: Vojtěch Jeřábek <[email protected]>
-- LICENSE: The MIT License, please read LICENSE file
-- WEBSITE: https://github.com/jakubcabal/pipemania-fpga-game
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity RANDOM_DECODER_FIFO is
Port(
CLK : in std_logic;
RST : in std_logic;
GENERATE_NEW : in std_logic; -- enable generate one random component
GENERATE_FIVE : in std_logic; -- enable generate five random components
KOMP0 : out std_logic_vector(5 downto 0); -- nejnovejci trubka
KOMP1 : out std_logic_vector(5 downto 0); -- ||
KOMP2 : out std_logic_vector(5 downto 0); -- posouva se dolu
KOMP3 : out std_logic_vector(5 downto 0); -- \/
KOMP4 : out std_logic_vector(5 downto 0) -- nejstarsi trubka, vklada se do hraciho pole
);
end RANDOM_DECODER_FIFO;
architecture Behavioral of RANDOM_DECODER_FIFO is
signal generate_random : std_logic;
signal generate_random_1 : std_logic;
signal generate_random_2 : std_logic;
signal fifo_move : std_logic;
signal generate_random_five : unsigned(11 downto 0);
signal fifo_input : std_logic_vector(3 downto 0);
signal komp0_sig : std_logic_vector(5 downto 0);
signal komp1_sig : std_logic_vector(5 downto 0);
signal komp2_sig : std_logic_vector(5 downto 0);
signal komp3_sig : std_logic_vector(5 downto 0);
signal komp4_sig : std_logic_vector(5 downto 0);
signal komp_sig : std_logic_vector(5 downto 0);
begin
--------------------------------------------------------------------------------
-- vygenerovani 5-ti nahodnych komponent za sebou
process (CLK, RST)
begin
if (RST = '1') then
generate_random_five <= (others=>'0');
generate_random_1 <='0';
elsif(rising_edge(CLK)) then
if (GENERATE_FIVE='1') then
generate_random_five <= "000000000001";
generate_random_1<='0';
else
if (generate_random_five=4096) then
generate_random_five <= (others=>'0');
generate_random_1<='0';
elsif (generate_random_five=0) then
generate_random_1<='0';
generate_random_five <= (others=>'0');
elsif (generate_random_five=237) then
generate_random_1<='1';
generate_random_five <= generate_random_five + 1;
elsif (generate_random_five=1638) then
generate_random_1<='1';
generate_random_five <= generate_random_five + 1;
elsif (generate_random_five=2484) then
generate_random_1<='1';
generate_random_five <= generate_random_five + 1;
elsif (generate_random_five=3186) then
generate_random_1<='1';
generate_random_five <= generate_random_five + 1;
elsif (generate_random_five=4001) then
generate_random_1<='1';
generate_random_five <= generate_random_five + 1;
else
generate_random_1<='0';
generate_random_five <= generate_random_five + 1;
end if;
end if;
end if;
end process;
--------------------------------------------------------------------------------
-- vygenerovani 1 nahodne komponenty
process (CLK, RST)
begin
if (RST = '1') then
generate_random_2 <= '0';
elsif (rising_edge(CLK)) then
if (GENERATE_NEW = '1') then
generate_random_2 <= '1';
else
generate_random_2 <= '0';
end if;
end if;
end process;
--------------------------------------------------------------------------------
-- vygenerovani prirazeni nahodneho cila na KOMP0_sig a posuv ostatnich. KOPM4_sig zanika
process (CLK, RST)
begin
if (RST = '1') then
komp0_sig <= (others=>'0');
komp1_sig <= (others=>'0');
komp2_sig <= (others=>'0');
komp3_sig <= (others=>'0');
komp4_sig <= (others=>'0');
elsif (rising_edge(CLK)) then
if (fifo_move = '1') then
komp0_sig <= komp_sig;
komp1_sig <= komp0_sig;
komp2_sig <= komp1_sig;
komp3_sig <= komp2_sig;
komp4_sig <= komp3_sig;
end if;
end if;
end process;
KOMP0 <= komp0_sig;
KOMP1 <= komp1_sig;
KOMP2 <= komp2_sig;
KOMP3 <= komp3_sig;
KOMP4 <= komp4_sig;
--------------------------------------------------------------------------------
-- prepocet kombinacni logiky nahodneho cisla
with fifo_input select
komp_sig <= "000001" when "0000",
"000001" when "0001",
"010001" when "0010",
"010001" when "0011", --rovne trubky
"000010" when "0100",
"010010" when "0101",
"100010" when "0110",
"110010" when "0111", --zahla trubka
"000011" when "1000",
"000011" when "1001", --kriz, je 2x kvuli lepsi cetnosti
"111111" when "1111",
"000000" when others;
--------------------------------------------------------------------------------
-- instancovani komponenty RANDOM_GENERATOR
random_generator_i: entity work.RANDOM_GENERATOR
generic map (
Number_of_options => 10,
Flip_Flops => 4
)
port map (
CLK => CLK,
RST => RST,
RANDOM_PULSE => generate_random,
RANDOM_OUT => fifo_input,
ENABLE_OUT => fifo_move
);
generate_random <= generate_random_1 OR generate_random_2;
end Behavioral;
|
mit
|
beltagymohamed/FLOATING-POINT-MULTIPLIER-USING-FPGA
|
Multiplier/Project/VHDL/device.vhd
|
1
|
1405
|
library ieee;
use ieee.std_logic_1164.all;
entity device is
port (a,b: in std_logic_vector(31 downto 0);
clk,en,rst: in std_logic;
c: out std_logic_vector(31 downto 0);
done: out std_logic
);
end device;
architecture arch_device_1 of device is
component datapath is
port (a,b: in std_logic_vector(31 downto 0);
clk,rst: in std_logic;
en: in std_logic_vector(1 downto 0);
c: out std_logic_vector(31 downto 0);
done,m47: out std_logic
);
end component;
component exceptions
port (in1: in std_logic_vector(31 downto 0);
in2: in std_logic_vector(31 downto 0);
int_mul: in std_logic_vector(31 downto 0);
enable: in std_logic;
m_in47:in std_logic;
exp_out: out std_logic_vector(31 downto 0)
);
end component;
component control
port (clk,rst,en: in std_logic;
done_m: in std_logic;
done:out std_logic;
en_mul: out std_logic_vector(1 downto 0)
);
end component;
signal done_s : std_logic ;
signal res: std_logic_vector(31 downto 0);
signal m47: std_logic;
signal en_m:std_logic_vector(1 downto 0);
signal d: std_logic;
begin
done<=d;
dp: datapath port map(a=>a,b=>b,clk=>clk,rst=>rst,en=>en_m,c=>res,done=>done_s,m47=>m47);
ex:exceptions port map(in1=>a,in2=>b,int_mul=>res,enable=>d,m_in47=>m47,exp_out=>c);
ctrl: control port map(clk=>clk,rst=>rst,en=>en,done_m=>done_s,done=>d,en_mul=>en_m);
end arch_device_1;
|
mit
|
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors-
|
DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/plasma/shifter.vhd
|
16
|
3063
|
---------------------------------------------------------------------
-- TITLE: Shifter Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- Matthias Gruenewald
-- DATE CREATED: 2/2/01
-- FILENAME: shifter.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the 32-bit shifter unit.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity shifter is
generic(shifter_type : string := "DEFAULT");
port(value : in std_logic_vector(31 downto 0);
shift_amount : in std_logic_vector(4 downto 0);
shift_func : in shift_function_type;
c_shift : out std_logic_vector(31 downto 0));
end; --entity shifter
architecture logic of shifter is
-- type shift_function_type is (
-- shift_nothing, shift_left_unsigned,
-- shift_right_signed, shift_right_unsigned);
signal shift1L, shift2L, shift4L, shift8L, shift16L : std_logic_vector(31 downto 0);
signal shift1R, shift2R, shift4R, shift8R, shift16R : std_logic_vector(31 downto 0);
signal fills : std_logic_vector(31 downto 16);
begin
fills <= "1111111111111111" when shift_func = SHIFT_RIGHT_SIGNED
and value(31) = '1'
else "0000000000000000";
shift1L <= value(30 downto 0) & '0' when shift_amount(0) = '1' else value;
shift2L <= shift1L(29 downto 0) & "00" when shift_amount(1) = '1' else shift1L;
shift4L <= shift2L(27 downto 0) & "0000" when shift_amount(2) = '1' else shift2L;
shift8L <= shift4L(23 downto 0) & "00000000" when shift_amount(3) = '1' else shift4L;
shift16L <= shift8L(15 downto 0) & ZERO(15 downto 0) when shift_amount(4) = '1' else shift8L;
shift1R <= fills(31) & value(31 downto 1) when shift_amount(0) = '1' else value;
shift2R <= fills(31 downto 30) & shift1R(31 downto 2) when shift_amount(1) = '1' else shift1R;
shift4R <= fills(31 downto 28) & shift2R(31 downto 4) when shift_amount(2) = '1' else shift2R;
shift8R <= fills(31 downto 24) & shift4R(31 downto 8) when shift_amount(3) = '1' else shift4R;
shift16R <= fills(31 downto 16) & shift8R(31 downto 16) when shift_amount(4) = '1' else shift8R;
GENERIC_SHIFTER: if shifter_type = "DEFAULT" generate
c_shift <= shift16L when shift_func = SHIFT_LEFT_UNSIGNED else
shift16R when shift_func = SHIFT_RIGHT_UNSIGNED or
shift_func = SHIFT_RIGHT_SIGNED else
ZERO;
end generate;
AREA_OPTIMIZED_SHIFTER: if shifter_type /= "DEFAULT" generate
c_shift <= shift16L when shift_func = SHIFT_LEFT_UNSIGNED else (others => 'Z');
c_shift <= shift16R when shift_func = SHIFT_RIGHT_UNSIGNED or
shift_func = SHIFT_RIGHT_SIGNED else (others => 'Z');
c_shift <= ZERO when shift_func = SHIFT_NOTHING else (others => 'Z');
end generate;
end; --architecture logic
|
mit
|
herenvarno/dlx
|
dlx_vhd/src/a.b-DataPath.core/a.b.a-Alu.vhd
|
1
|
5350
|
--------------------------------------------------------------------------------
-- FILE: Alu
-- DESC: ALU with multiple functions:
-- ADD/SUB/CMP
-- SHIFT
-- AND/OR/XOR
--
-- Author:
-- Create: 2015-05-25
-- Update: 2015-05-27
-- Status: TESTED
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Encode of FUNCTION (f) signal:
-- 00000 -- [ADD] Addition, or NOP
-- 00001 -- [AND]
-- 00010 -- [OR]
-- 00011 -- [XOR]
-- 00100 -- [SLL] Logic Shift LEFT
-- 00101 -- [SRL] Logic Shift RIGHT
-- 00110 -- NOT USED
-- 00111 -- [SRA] Arithmetic Shift RIGHT
-- 01000 -- [MULTU] Unsigned Multiply -- IN MUL MODULE
-- 01001 -- [MULT] Multiply -- IN MUL MODULE
-- 01010 -- [DIVU] Unsigned Division -- IN DIV MODULE
-- 01011 -- [DIV] Division -- IN DIV MODULE
-- 01100 -- [SQRT] Square root -- IN DIV MODULE
-- 01101 -- NOT USED
-- 01110 -- NOT USED
-- 01111 -- NOT USED
-- 10000 -- [SUB] Substraction
-- 10001 -- [SGT] SET If GREAT, For SIGNED
-- 10010 -- [SGE] SET If GREAT AND EQUAL, For SIGNED
-- 10011 -- [SLT] SET If LESS, For SIGNED
-- 10100 -- [SLE] SET If LESS AND EQUAL, For SIGNED
-- 10101 -- [SGTU] SET If GREAT, For UNSIGNED
-- 10110 -- [SGEU] SET If GREAT AND EQUAL, For UNSIGNED
-- 10111 -- [SLTU] SET If LESS, For UNSIGNED
-- 11000 -- [SLEU] SET If LESS AND EQUAL, For UNSIGNED
-- 11001 -- [SEQ] SET If EQUAL
-- 11010 -- [SNE] SET If NOT EQUAL
-- 11011 -- NOT USED
-- 11100 -- NOT USED
-- 11101 -- NOT USED
-- 11110 -- NOT USED
-- 11111 -- NOT USED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Consts.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity Alu is
generic (
DATA_SIZE : integer := C_SYS_DATA_SIZE
);
port (
f : in std_logic_vector(4 downto 0):=(others=>'0'); -- Function
a : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0'); -- Data A
b : in std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0'); -- Data B
o : out std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0') -- Data Out
);
end Alu;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture alu_arch of Alu is
component Adder is
generic(
DATA_SIZE : integer := C_SYS_DATA_SIZE
);
port(
cin : in std_logic;
a, b : in std_logic_vector(DATA_SIZE-1 downto 0);
s : out std_logic_vector(DATA_SIZE-1 downto 0);
cout : out std_logic
);
end component;
component Shifter is
generic (
DATA_SIZE : integer := C_SYS_DATA_SIZE
);
port (
l_r : in std_logic; -- LEFT/RIGHT
l_a : in std_logic; -- LOGIC/ARITHMETIC
s_r : in std_logic; -- SHIFT/ROTATE
a : in std_logic_vector(DATA_SIZE-1 downto 0);
b : in std_logic_vector(DATA_SIZE-1 downto 0);
o : out std_logic_vector(DATA_SIZE-1 downto 0)
);
end component;
constant FUNC_SIZE : integer := 5;
constant FUNC_NUM : integer := 2**FUNC_SIZE;
signal b_new : std_logic_vector(DATA_SIZE-1 downto 0);
signal as_arr: std_logic_vector(DATA_SIZE-1 downto 0);
signal ado : std_logic_vector(DATA_SIZE-1 downto 0); -- adder output
signal sho : std_logic_vector(DATA_SIZE-1 downto 0); -- shifter output
signal c_f, o_f, s_f, z_f, b_f : std_logic := '0'; -- Flags of ADDER outputs: Carry, Overflow, Sign, Zero, Borrow
type OutMem_t is array (FUNC_NUM-1 downto 0) of std_logic_vector(DATA_SIZE-1 downto 0);
signal outputs : OutMem_t;
signal zeros : std_logic_vector(DATA_SIZE-1 downto 0):=(others=>'0');
begin
as_arr <= (others=>f(FUNC_SIZE-1));
b_new <= b xor as_arr;
ADD0: Adder
generic map (DATA_SIZE)
port map (f(FUNC_SIZE-1), a, b_new, ado, c_f);
SHF0: Shifter
generic map (DATA_SIZE)
port map (f(0), f(1), '0', a, b, sho);
-- CAUTION: the concept of CF is different from the CF in 8086 structure, a
-- BF is needed to determin the Borrow Bit of a substraction.
b_f <= not c_f;
s_f <= ado(DATA_SIZE-1);
o_f <= (not (a(DATA_SIZE-1) xor b_new(DATA_SIZE-1))) and (a(DATA_SIZE-1) xor s_f);
P0: process(ado)
begin
if ado = zeros then
z_f <= '1';
else
z_f <= '0';
end if;
end process;
outputs(0) <= ado;
outputs(1) <= a and b;
outputs(2) <= a or b;
outputs(3) <= a xor b;
outputs(4) <= sho;
outputs(5) <= sho;
outputs(7) <= sho;
outputs(16) <= ado;
outputs(17) <= (0 => (not z_f) and (not (s_f xor o_f)), others => '0'); -- ZF=0 & SF=OF
outputs(18) <= (0 => (not (s_f xor o_f)), others => '0'); -- SF=OF
outputs(19) <= (0 => (s_f xor o_f), others => '0'); -- SF!=OF
outputs(20) <= (0 => (z_f or (s_f xor o_f)), others => '0'); -- ZF=1 | SF!=OF
outputs(21) <= (0 => ((not b_f) and (not z_f)), others => '0'); -- BF=0 & ZF=0
outputs(22) <= (0 => (not b_f), others => '0'); -- BF=0
outputs(23) <= (0 => b_f, others => '0'); -- BF=1
outputs(24) <= (0 => (b_f or z_f), others => '0'); -- BF=1 | ZF=1
outputs(25) <= (0 => z_f, others => '0'); -- ZF=1
outputs(26) <= (0 => (not z_f), others => '0'); -- ZF=0
o <= outputs(to_integer(unsigned(f)));
end alu_arch;
|
mit
|
shkkgs/DE4-multicore-network-processor-with-multiple-hardware-monitors-
|
DE4_network_processor_4cores_6monitors_release/projects/DE4_Reference_Router_with_DMA/src/sources_ngnp_multicore/src/tmp/mb_lite/fetch.vhd
|
3
|
2196
|
----------------------------------------------------------------------------------------------
--
-- Input file : fetch.vhd
-- Design name : fetch
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Instruction Fetch Stage inserts instruction into the pipeline. It
-- uses a single port Random Access Memory component which holds
-- the instructions. The next instruction is computed in the decode
-- stage.
--
----------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
LIBRARY work;
USE work.config_Pkg.ALL;
USE work.core_Pkg.ALL;
USE work.std_Pkg.ALL;
ENTITY fetch IS PORT
(
fetch_o : OUT fetch_out_type;
imem_adr_o : OUT std_ulogic_vector(CFG_IMEM_SIZE - 1 DOWNTO 0);
imem_ena_o : OUT std_ulogic;
fetch_i : IN fetch_in_type;
rst_i : IN std_ulogic;
ena_i : IN std_ulogic;
clk_i : IN std_ulogic
);
END fetch;
ARCHITECTURE arch OF fetch IS
SIGNAL r, rin : fetch_out_type;
BEGIN
fetch_o.program_counter <= r.program_counter;
imem_adr_o <= rin.program_counter;
imem_ena_o <= ena_i;
fetch_comb: PROCESS(fetch_i, r, rst_i)
VARIABLE v : fetch_out_type;
BEGIN
v := r;
IF fetch_i.hazard = '1' THEN
v.program_counter := r.program_counter;
ELSIF fetch_i.branch = '1' THEN
v.program_counter := fetch_i.branch_target;
ELSE
v.program_counter := increment(r.program_counter(CFG_IMEM_SIZE - 1 DOWNTO 2)) & "00";
END IF;
rin <= v;
END PROCESS;
fetch_seq: PROCESS(clk_i)
BEGIN
IF rising_edge(clk_i) THEN
IF rst_i = '1' THEN
r.program_counter <= (OTHERS => '0');
ELSIF ena_i = '1' THEN
r <= rin;
END IF;
END IF;
END PROCESS;
END arch;
|
mit
|
KPU-RISC/KPU
|
VHDL/Neg8Bit.vhd
|
1
|
1675
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07/15/2015 09:30:43 PM
-- Design Name:
-- Module Name: Neg8Bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Neg8Bit is
Port
(
Input : in BIT_VECTOR(7 downto 0); -- 8-bit input value
Output : out BIT_VECTOR(7 downto 0) -- 8-bit output value
);
end Neg8Bit;
architecture Behavioral of Neg8Bit is
component RippleCarryAdder8Bit is
Port
(
InputA : in BIT_VECTOR(7 downto 0); -- 1st 8-bit input value
InputB : in BIT_VECTOR(7 downto 0); -- 2nd 8-bit input value
Cin : in BIT; -- Carry-in flag
Output : out BIT_VECTOR(7 downto 0); -- 8-bit output value
Cout : out BIT -- Carry-out flag
);
end component RippleCarryAdder8Bit;
signal NegatedInput : BIT_VECTOR(7 downto 0);
signal CarryADD : BIT;
begin
NegatedInput <= not(Input);
ADD_Impl: RippleCarryAdder8Bit port map (NegatedInput, "00000001", '0', Output, CarryADD);
end Behavioral;
|
mit
|
gustavogarciautp/Procesador
|
Entrega 3/OMUXT.vhd
|
3
|
434
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity OMUXT is
Port ( Crs2 : in STD_LOGIC_VECTOR (31 downto 0);
SEUimm: in STD_LOGIC_VECTOR (31 downto 0);
i : in STD_LOGIC;
oper2 : out STD_LOGIC_VECTOR (31 downto 0));
end OMUXT;
architecture Behavioral of OMUXT is
begin
process(Crs2,SEUimm,i)
begin
if i='0' then
Oper2<=Crs2;
else
Oper2<=SEUimm;
end if;
end process;
end Behavioral;
|
mit
|
KPU-RISC/KPU
|
VHDL/SAR8Bit.vhd
|
1
|
1353
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07/17/2015 02:58:32 PM
-- Design Name:
-- Module Name: SAR8Bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SAR8Bit is
Port
(
Input : in BIT_VECTOR(7 downto 0); -- 8-bit input value
Output : out BIT_VECTOR(7 downto 0); -- 8-bit output value
Cout : out BIT -- Carry-out flag
);
end SAR8Bit;
architecture Behavioral of SAR8Bit is
begin
Cout <= Input(0);
Output(0) <= Input(1);
Output(1) <= Input(2);
Output(2) <= Input(3);
Output(3) <= Input(4);
Output(4) <= Input(5);
Output(5) <= Input(6);
Output(6) <= Input(7);
Output(7) <= Input(7);
end Behavioral;
|
mit
|
jeffmagina/ECE368
|
Lab2/VGA Part 2/clk25MHz.vhd
|
1
|
2032
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Pixel CLK
-- Project Name: VGA
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Pixel Clock
-- Output a 25Mhz clock for a vga controller
-- 50 Mhz to 25 Mhz
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity CLK_25MHZ is
port(CLK_IN: in std_logic;
CLK_OUT: inout std_logic);
end CLK_25MHZ;
architecture Behavioral of CLK_25MHZ is
component CLKDLL
generic (CLKDV_DIVIDE : real := 2.0;
DUTY_CYCLE_CORRECTION : Boolean := TRUE;
STARTUP_WAIT : boolean := FALSE);
port(CLK0 : out STD_ULOGIC;
CLK180 : out STD_ULOGIC;
CLK270 : out STD_ULOGIC;
CLK2X : out STD_ULOGIC;
CLK90 : out STD_ULOGIC;
CLKDV : out STD_ULOGIC;
LOCKED : out STD_ULOGIC;
CLKFB : in STD_ULOGIC;
CLKIN : in STD_ULOGIC;
RST : in STD_ULOGIC);
end component;
attribute CLKDV_DIVIDE : real;
attribute DUTY_CYCLE_CORRECTION : boolean;
attribute STARTUP_WAIT : boolean;
signal CLK_D: std_logic;
begin
CLKDLL_inst : CLKDLL
port map (
CLK0 => open, -- 0 degree DLL CLK ouptput
CLK180 => open, -- 180 degree DLL CLK output
CLK270 => open, -- 270 degree DLL CLK output
CLK2X => CLK_D, -- 2X DLL CLK output
CLK90 => open, -- 90 degree DLL CLK output
CLKDV => CLK_OUT, -- Divided DLL CLK out (CLKDV_DIVIDE)
LOCKED => open, -- DLL LOCK status output
CLKFB => CLK_D, -- DLL clock feedback
CLKIN => CLK_IN, -- Clock input (from IBUFG, BUFG or DLL)
RST => '0' -- DLL asynchronous reset input
);
end Behavioral;
|
mit
|
KPU-RISC/KPU
|
VHDL/MOV8.vhd
|
1
|
1858
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07/17/2015 05:17:03 PM
-- Design Name:
-- Module Name: MOV8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MOV8 is
Port
(
InputA : in BIT_VECTOR(7 downto 0); -- 1st 8-bit input value
InputB : in BIT_VECTOR(7 downto 0); -- 2nd 8-bit input value
Output : out BIT_VECTOR(7 downto 0) -- 8-bit output value
);
end MOV8;
architecture Behavioral of MOV8 is
component SHL8Bit is
Port
(
Input : in BIT_VECTOR(7 downto 0); -- 8-bit input value
Output : out BIT_VECTOR(7 downto 0); -- 8-bit output value
Cout : out BIT -- Carry-out flag
);
end component SHL8Bit;
signal OutputSHL1 : BIT_VECTOR(7 downto 0);
signal OutputSHL2 : BIT_VECTOR(7 downto 0);
signal OutputSHL3 : BIT_VECTOR(7 downto 0);
signal OutputSHL4 : BIT_VECTOR(7 downto 0);
begin
-- Shift InputA 4 bits to the left
SHL_Impl1: SHL8Bit port map(InputA, OutputSHL1);
SHL_Impl2: SHL8Bit port map(OutputSHL1, OutputSHL2);
SHL_Impl3: SHL8Bit port map(OutputSHL2, OutputSHL3);
SHL_Impl4: SHL8Bit port map(OutputSHL3, OutputSHL4);
Output <= OutputSHL4 or InputB;
end Behavioral;
|
mit
|
jeffmagina/ECE368
|
Lab2/VGA Part 2/blinker.vhd
|
4
|
1406
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: BLINKER
-- Project Name: VGA Toplevel
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Simulate a BLINKER by inverting the
-- font for 1/2 second.
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BLINKER is
Port ( CLK : in STD_LOGIC;
ADDR_B : in STD_LOGIC_VECTOR (11 downto 0);
CURSOR_ADR : in STD_LOGIC_VECTOR (11 downto 0);
OUTPUT : out STD_LOGIC_VECTOR (7 downto 0);
FONT_ROM : in STD_LOGIC_VECTOR (7 downto 0));
end BLINKER;
architecture Behavioral of BLINKER is
signal sel : std_logic;
signal out1 : std_logic_vector(7 downto 0):="11111111";
begin
with sel select
OUTPUT<=out1 when '1',
FONT_ROM when others;
sel<='1' when ADDR_B=CURSOR_ADR else '0';
process(CLK)
variable count : integer;
begin
if CLK'event and CLK='1' then
count:=count+1;
if count=12500000 then
out1<=FONT_ROM;
elsif count=25000000 then
out1<="11111111";
count:=0;
end if;
end if;
end process;
end Behavioral;
|
mit
|
gustavogarciautp/Procesador
|
Entrega 2/RF_tb.vhd
|
1
|
2902
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY RF_tb IS
END RF_tb;
ARCHITECTURE behavior OF RF_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT RF
PORT(
rs1 : IN std_logic_vector(5 downto 0);
rs2 : IN std_logic_vector(5 downto 0);
rd : IN std_logic_vector(5 downto 0);
DWR : IN std_logic_vector(31 downto 0);
rst : IN std_logic;
Crs1 : OUT std_logic_vector(31 downto 0);
Crs2 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal rs1 : std_logic_vector(5 downto 0) := (others => '0');
signal rs2 : std_logic_vector(5 downto 0) := (others => '0');
signal rd : std_logic_vector(5 downto 0) := (others => '0');
signal DWR : std_logic_vector(31 downto 0) := (others => '0');
signal rst : std_logic := '0';
--Outputs
signal Crs1 : std_logic_vector(31 downto 0);
signal Crs2 : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: RF PORT MAP (
rs1 => rs1,
rs2 => rs2,
rd => rd,
DWR => DWR,
rst => rst,
Crs1 => Crs1,
Crs2 => Crs2
);
-- Stimulus process
stim_proc: process
begin
rst<='1';
wait for 20 ns;
rst<='0';
rs1<=(others=>'0');
rs2<="000101";
rd<="000001";
DWR<="00000000000000000000000000000101";
wait for 40 ns;
rs1<=(others=>'0');
rs2<="111000";
rd<="010000";
DWR<="11111111111111111111111111111000";
wait for 40 ns;
rs1<=(others=>'0');
rs2<="000100";
rd<="010001";
DWR<="00000000000000000000000000000100";
wait for 40 ns;
rs1<="000001";
rs2<="000010";
rd<="011000";
DWR<="00000000000000000000000000010100";
wait for 40 ns;
rs1<="010001";
rs2<="000001";
rd<="011001";
DWR<="00000000000000000000000000000010";
wait for 40 ns;
rs1<=(others=>'0');
rs2<=(others=>'0');
rd<=(others=>'0');
DWR<="00000000000000000000000000000000";
wait for 40 ns;
rs1<="000001";
rs2<="000011";
rd<="100000";
DWR<="00000000000000000000000000001000";
wait for 40 ns;
rs1<=(others=>'0');
rs2<=(others=>'0');
rd<=(others=>'0');
DWR<="00000000000000000000000000000000";
wait for 40 ns;
rs1<=(others=>'0');
rs2<="000100";
rd<=(others=>'0');
DWR<="11111111111111111111111111111100";
wait for 40 ns;
rs1<=(others=>'0');
rs2<="000001";
rd<="000010";
DWR<="00000000000000000000000000000101";
wait for 40 ns;
rs1<=(others=>'0');
rs2<="010000";
rd<="001000";
DWR<="11111111111111111111111111111000";
wait for 40 ns;
rst<='1';
rs1<="000001";
rs2<="000010";
rd<="001101";
DWR<="00000000000000000000000000001100";
wait;
end process;
END;
|
mit
|
KPU-RISC/KPU
|
VHDL/FlipFlop1Bit2WayInput.vhd
|
1
|
1868
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/28/2015 07:11:32 PM
-- Design Name:
-- Module Name: FlipFlop1Bit2WayInput - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity FlipFlop1Bit2WayInput is
Port
(
Load1 : in BIT; -- Load Line #1
Load2 : in BIT; -- Load Line #2
Sel : in BIT; -- Select Line
Input1 : in BIT; -- Input Data #1
Input2 : in BIT; -- Input Data #2
Output : out BIT; -- Output Data
State : out BIT -- Current state of the Flip Flop
);
end FlipFlop1Bit2WayInput;
architecture Behavioral of FlipFlop1Bit2WayInput is
signal Nand1 : BIT;
signal Nand2 : BIT;
signal Not1 : BIT;
signal F1 : BIT;
signal F2 : BIT;
signal Load: BIT;
signal Input: BIT;
begin
-- We accept input from 2 inputs
Load <= Load1 or Load2;
Input <= Input1 or Input2;
Nand1 <= not(Load and Input);
Not1 <= not Input;
Nand2 <= not(Not1 and Load);
F1 <= not (F2 and Nand1);
F2 <= not (Nand2 and F1) after 1 ns;
-- Return the internal state for debugging/monitoring purposes
State <= F1;
Output <= F1 and Sel;
end Behavioral;
|
mit
|
gustavogarciautp/Procesador
|
Entrega 3/SEU.vhd
|
3
|
389
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SEU is
Port ( imm13 : in STD_LOGIC_VECTOR (12 downto 0);
SEUimm : out STD_LOGIC_VECTOR (31 downto 0));
end SEU;
architecture Behavioral of SEU is
begin
process(imm13)
begin
if imm13(12)='1' then
SEUimm<="1111111111111111111"&imm13;
else
SEUimm<="0000000000000000000"&imm13;
end if;
end process;
end Behavioral;
|
mit
|
jeffmagina/ECE368
|
Project1/WRITE_BACK/write_back.vhd
|
1
|
1809
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:43:03 03/25/2015
-- Design Name:
-- Module Name: write_back - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Use ieee.std_logic_unsigned.all;
Use ieee.std_logic_arith.all;
entity write_back is
Port( CLK : IN STD_LOGIC;
DATA_WE : IN STD_LOGIC;
FPU_IN : IN STD_LOGIC_VECTOR (15 downto 0);
REG_A : IN STD_LOGIC_VECTOR (15 downto 0);
D_OUT_SEL : IN STD_LOGIC;
WB_OUT : OUT STD_LOGIC_VECTOR (15 downto 0)
);
end write_back;
architecture Structural of write_back is
signal s_Reg_Out, s_Reg_A_Out, s_Data_Mem_Out, s_MUX_WB_OUT : STD_LOGIC_VECTOR (15 downto 0);
signal InvCLK : STD_LOGIC;
begin
InvCLK <= not CLK;
U0: entity work.Register_RE_16
Port Map( CLK => CLK,
ENB => '1',
D => FPU_IN,
Q => s_Reg_Out
);
U1: entity work.Register_RE_16
Port Map( CLK => CLK,
ENB => '1',
D => REG_A,
Q => s_Reg_A_Out
);
U2: entity work.Data_MEM
Port Map( CLKA => InvCLK,
WEA(0) => DATA_WE,
ADDRA => s_Reg_Out(7 downto 0), -- (7 DOWNTO 0)
DINA => s_Reg_A_Out, -- (15 DOWNTO 0)
CLKB => CLK,
ADDRB => FPU_IN(7 downto 0), -- (7 DOWNTO 0)
DOUTB => s_Data_Mem_Out);
U3: entity work.mux2to1
Port Map( SEL => D_OUT_SEL,
DATA_0 => s_Data_Mem_Out,
DATA_1 => s_Reg_Out,
OUTPUT => WB_OUT
);
end Structural;
|
mit
|
gustavogarciautp/Procesador
|
Entrega 1/PC_tb.vhd
|
1
|
1799
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY PC_tb IS
END PC_tb;
ARCHITECTURE behavior OF PC_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT PC
PORT(
rst : IN std_logic;
dataIn : IN std_logic_vector(31 downto 0);
CLK : IN std_logic;
DataOut : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal rst : std_logic := '0';
signal dataIn : std_logic_vector(31 downto 0) := (others => '0');
signal CLK : std_logic := '0';
--Outputs
signal DataOut : std_logic_vector(31 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: PC PORT MAP (
rst => rst,
dataIn => dataIn,
CLK => CLK,
DataOut => DataOut
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for 20 ns;
CLK <= '1';
wait for 20 ns;
end process;
stim_proc: process
begin
rst<='1';
wait for 20 ns;
rst<='0';
dataIn<="00100010001000100010001000100010";
wait for 40 ns;
dataIn<="00000000000000000000000000000011";
wait for 80 ns;
rst<='1';
dataIn<="00100010001000100010001000100010";
wait for 40 ns;
dataIn<="00000000000000000000000000000011";
wait for 80 ns;
rst<='0';
dataIn<="11100010001000100010001111100010";
wait for 40 ns;
dataIn<="00000000000000111111100001111111";
wait for 40 ns;
dataIn<="01010010100101001100100100010010";
wait for 40 ns;
dataIn<="01011110100001011110100001101000";
wait for 20 ns;
dataIn<="00000000000000000000000000111010";
wait;
end process;
END;
|
mit
|
gustavogarciautp/Procesador
|
Entrega 3/SEUdisp22.vhd
|
1
|
421
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SEUdisp22 is
Port ( disp22 : in STD_LOGIC_VECTOR (21 downto 0);
SEUdisp22 : out STD_LOGIC_VECTOR (31 downto 0));
end SEUdisp22;
architecture Behavioral of SEUdisp22 is
begin
process(disp22)
begin
if disp22(21)='1' then
SEUdisp22<="1111111111"&disp22;
else
SEUdisp22<="0000000000"&disp22;
end if;
end process;
end Behavioral;
|
mit
|
KPU-RISC/KPU
|
VHDL/Decoder4To16.vhd
|
1
|
2407
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07/14/2015 04:50:10 PM
-- Design Name:
-- Module Name: Decoder4To16 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Decoder4To16 is
Port
(
F : in BIT_VECTOR(3 downto 0); -- 4-Bit Function Code (Input)
X : out BIT_VECTOR(15 downto 0) -- 16-Bit State (Output)
);
end Decoder4To16;
architecture Behavioral of Decoder4To16 is
begin
-- 0000
X(0) <= not(F(0)) and not(F(1)) and not (F(2)) and not(F(3)) after 1 ns;
-- 0001
X(1) <= F(0) and not (F(1)) and not (F(2)) and not(F(3)) after 1 ns;
-- 0010
X(2) <= not(F(0)) and F(1) and not (F(2)) and not(F(3)) after 1 ns;
-- 0011
X(3) <= F(0) and F(1) and not (F(2)) and not(F(3)) after 1 ns;
-- 0100
X(4) <= not(F(0)) and not(F(1)) and F(2) and not(F(3)) after 1 ns;
-- 0101
X(5) <= F(0) and not(F(1)) and F(2) and not(F(3)) after 1 ns;
-- 0110
X(6) <= not(F(0)) and F(1) and F(2) and not(F(3)) after 1 ns;
-- 0111
X(7) <= F(0) and F(1) and F(2) and not(F(3)) after 1 ns;
-- 1000
X(8) <= not(F(0)) and not(F(1)) and not(F(2)) and F(3) after 1 ns;
-- 1001
X(9) <= F(0) and not(F(1)) and not(F(2)) and F(3) after 1 ns;
-- 1010
X(10) <= not(F(0)) and F(1) and not(F(2)) and F(3) after 1 ns;
-- 1011
X(11) <= F(0) and F(1) and not(F(2)) and F(3) after 1 ns;
-- 1100
X(12) <= not(F(0)) and not(F(1)) and F(2) and F(3) after 1 ns;
-- 1101
X(13) <= F(0) and not(F(1)) and F(2) and F(3) after 1 ns;
-- 1110
X(14) <= not(F(0)) and F(1) and F(2) and F(3) after 1 ns;
-- 1111
X(15) <= F(0) and F(1) and F(2) and F(3) after 1 ns;
end Behavioral;
|
mit
|
popas90/vhdl-parser
|
assets/entity.vhd
|
1
|
434
|
ENTITY ALU IS
generic(
Depth : natural := 2;
Overflow : boolean
);
port (
A : in std_logic_vector(7 downto 0); --! ALU A input 8-bit from AC
B : in std_logic_vector(7 downto 0); --! ALU B input 8-bit from B-register
S : out std_logic_vector(Depth-1 downto 0); --! ALU output 8-bit to W-bus
Su : in std_logic; --! Low Add, High Sub
Eu : in std_logic); --! Active low enable ALU (tri-state)
END ALU ;
|
mit
|
jeffmagina/ECE368
|
Lab2/RISC Machine SSEG/alu_mux.vhd
|
4
|
2168
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_MUX
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Mux unit
-- Output what ALU operation requested
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU_Mux is
Port ( OP : in STD_LOGIC_VECTOR (3 downto 0);
ARITH : in STD_LOGIC_VECTOR (7 downto 0);
LOGIC : in STD_LOGIC_VECTOR (7 downto 0);
SHIFT : in STD_LOGIC_VECTOR (7 downto 0);
MEMORY : in STD_LOGIC_VECTOR (7 downto 0);
CCR_ARITH : in STD_LOGIC_VECTOR (3 downto 0);
CCR_LOGIC : in STD_LOGIC_VECTOR (3 downto 0);
ALU_OUT : out STD_LOGIC_VECTOR (7 downto 0);
CCR_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end ALU_Mux;
architecture Combinational of ALU_Mux is
begin
with OP select
ALU_OUT <=
ARITH when "0000", -- ADD
ARITH when "0001", -- SUB
LOGIC when "0010", -- AND
LOGIC when "0011", -- OR
LOGIC when "0100", -- CMP
ARITH when "0101", -- ADDI
LOGIC when "0110", -- ANDI
SHIFT when "0111", -- SL
SHIFT when "1000", -- SR
MEMORY when "1001", -- LW
MEMORY when OTHERS; -- SW
with OP select
CCR_OUT <=
CCR_ARITH when "0000", -- ADD
CCR_ARITH when "0001", -- SUB
CCR_LOGIC when "0010", -- AND
CCR_LOGIC when "0011", -- OR
CCR_LOGIC when "0100", -- CMP
CCR_ARITH when "0101", -- ADDI
CCR_LOGIC when "0110", -- ANDI
"0000" when OTHERS; -- All flags cleared for other LOGIC operations
end Combinational;
|
mit
|
jeffmagina/ECE368
|
Project1/OPERAND_ACCESS/op_access.vhd
|
1
|
4233
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:38:02 03/25/2015
-- Design Name:
-- Module Name: op_access - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity op_access is
Port( CLK : IN STD_LOGIC;
OPCODE_IN : IN STD_LOGIC_VECTOR (3 downto 0);
REG_A : IN STD_LOGIC_VECTOR (3 downto 0);
IMMEDIATE : IN STD_LOGIC_VECTOR (7 downto 0);
W_ADDR : IN STD_LOGIC_VECTOR (3 downto 0);
OP1_MUX_SEL : IN STD_LOGIC_VECTOR(1 downto 0);
OP2_MUX_SEL : IN STD_LOGIC_VECTOR(1 downto 0);
BANK_R_W : IN STD_LOGIC;
BANK_ENB : IN STD_LOGIC;
BANK_DATA : IN STD_LOGIC_VECTOR(15 downto 0);
DEC_REG_ADDR : OUT STD_LOGIC_VECTOR (3 downto 0);
OPCODE_OUT : OUT STD_LOGIC_VECTOR (3 downto 0);
EX_FWD_IN : IN STD_LOGIC_VECTOR(15 downto 0);
EX_FWD_ADDR : IN STD_LOGIC_VECTOR (3 downto 0);
WB_FWD_IN : IN STD_LOGIC_VECTOR(15 downto 0);
WB_FWD_ADDR : IN STD_LOGIC_VECTOR (3 downto 0);
OP1_OUT : OUT STD_LOGIC_VECTOR (15 downto 0);
OP2_OUT : OUT STD_LOGIC_VECTOR (15 downto 0)
);
end op_access;
architecture Structural of op_access is
signal REG_BANK_A_OUT, REG_BANK_B_OUT, IMM_DATA, REG_A_IN, REG_B_IN, REG_B : STD_LOGIC_VECTOR (15 downto 0);
signal OPCODE_DEL_OUT, write_address, EX_FWD_ADDR_REG, WB_FWD_ADDR_REG : STD_LOGIC_VECTOR (3 downto 0);
signal DETECT_SEL1, DETECT_SEL2 : STD_LOGIC_VECTOR(1 downto 0);
begin
IMM_DATA <= x"00" & IMMEDIATE;
REG_B <= X"000" & IMMEDIATE(3 downto 0);
RegBank: entity work.register_bank
Port Map( CLK => CLK,
ADDR_A => REG_A,
ADDR_B => IMMEDIATE(7 downto 4),
W_ADDR => write_address,
R_W => BANK_R_W,
ENB => BANK_ENB,
DATA_IN => BANK_DATA,
REG_A => REG_BANK_A_OUT,
REG_B => REG_BANK_B_OUT);
OPCODE: entity work.Register_FE_4
Port Map( CLK => CLK,
D => OPCODE_IN,
ENB => '1',
Q => OPCODE_OUT);
REGA: entity work.Register_FE_4
Port Map( CLK => CLK,
D => REG_A,
ENB => '1',
Q => DEC_REG_ADDR);
-- OPCODEDEL: entity work.Register_FE_4
-- Port Map( CLK => CLK,
-- D => OPCODE_DEL_OUT,
-- ENB => '1',
-- Q => OPCODE_OUT);
FWD_DETECT1: entity work.Forwarding_unit
PORT MAP( OPA_REG => REG_A,
EX_FWD_REG => EX_FWD_ADDR_REG,
WB_FWD_REG => WB_FWD_ADDR_REG,
FWD_SEL => OP1_MUX_SEL,
FWD_MUX_SEL => DETECT_SEL1);
OP1_MUX: entity work.MUX4to1
PORT MAP( SEL => DETECT_SEL1,
DATA_0 => REG_BANK_A_OUT,
DATA_1 => x"0000",
DATA_2 => WB_FWD_IN,
DATA_3 => EX_FWD_IN,
OUTPUT => REG_A_IN);
OP1: entity work.Register_FE_16
Port Map( CLK => CLK,
D => REG_A_IN,
ENB => '1',
Q => OP1_OUT);
FWD_DETECT2: entity work.Forwarding_unit
PORT MAP( OPA_REG => IMMEDIATE(3 downto 0),
EX_FWD_REG => EX_FWD_ADDR_REG,
WB_FWD_REG => WB_FWD_ADDR_REG,
FWD_SEL => OP2_MUX_SEL,
FWD_MUX_SEL => DETECT_SEL2);
OP2_MUX: entity work.mux4to1
Port Map( SEL => DETECT_SEL2,
DATA_0 => REG_BANK_B_OUT,
DATA_1 => IMM_DATA,
DATA_2 => WB_FWD_IN,
DATA_3 => EX_FWD_IN,
OUTPUT => REG_B_IN);
OP2: entity work.Register_FE_16
Port Map( CLK => CLK,
D => REG_B_IN,
ENB => '1',
Q => OP2_OUT);
U5: entity work.Register_RE_4
Port Map( CLK => CLK,
ENB => '1',
D => W_ADDR,
Q => write_address);
U6: entity work.Register_RE_4
Port Map( CLK => CLK,
ENB => '1',
D => EX_FWD_ADDR,
Q => EX_FWD_ADDR_REG);
U7: entity work.Register_RE_4
Port Map( CLK => CLK,
ENB => '1',
D => WB_FWD_ADDR,
Q => WB_FWD_ADDR_REG);
end Structural;
|
mit
|
jeffmagina/ECE368
|
Lab1/Button/debounce.vhd
|
2
|
2029
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Debouncer
-- Project Name: Button Controller
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Debouncer
-- Debounce Input Signal
-- Input is fed through two flip flops
-- If both flip flops(2 cycles) have a high then
-- the counter will increment till it goes to
-- the necessary wait time.
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_unsigned.all;
entity debounce is
Generic ( wait_time : INTEGER := 20);
-- Wait_time is a fixed time to wait to validate a debounce signal
-- Wait time is based on the Nexys 50 MHZ Clock
-- XX : (2^xx + 2)/CLK
-- 21 : 41.9ms | (2^21 + 2)/50E6
-- 20 : 21.0ms | (2^20 + 2)/50E6
-- 19 : 10.5ms | (2^19 + 2)/50E6
-- 18 : 5.2ms | (2^18 + 2)/50E6
Port ( CLK : in STD_LOGIC;
EN : in STD_LOGIC;
INPUT : in STD_LOGIC;
OUTPUT : out STD_LOGIC);
end debounce;
architecture Logic of debounce is
signal D_STATE : STD_LOGIC_VECTOR (1 downto 0);
signal D_SET : STD_LOGIC;
signal Count : STD_LOGIC_VECTOR( wait_time downto 0) := (others => '0');
begin
D_SET <= D_STATE(0) xor D_STATE(1);
--Check what the deboune states are
-- *if their is a change in state then D_SET will be set to a high
input_monitor: process (EN, CLK)
begin
if (CLK'event and CLK = '1' and EN = '1') then
D_STATE(0) <= INPUT;
D_STATE(1) <= D_STATE(0);
if(D_SET = '1') then
Count <= (others => '0');
elsif(Count(wait_time) = '0') then
Count <= Count + 1;
else
OUTPUT <= D_STATE(1);
end if;
end if;
end process;
end Logic;
|
mit
|
jeffmagina/ECE368
|
Lab1/ALUwithInput/alu_arithmetic_unit.vhd
|
3
|
1602
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Arithmetic_Unit
-- Project Name: OurALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Artithmetic Unit
-- Operations - Add, Sub, Addi
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Arith_Unit is
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
B : in STD_LOGIC_VECTOR (7 downto 0);
OP : in STD_LOGIC_VECTOR (2 downto 0);
CCR : out STD_LOGIC_VECTOR (3 downto 0);
RESULT : out STD_LOGIC_VECTOR (7 downto 0));
end Arith_Unit;
architecture Combinational of Arith_Unit is
signal a1, b1 : STD_LOGIC_VECTOR (8 downto 0) := (OTHERS => '0');
signal arith : STD_LOGIC_VECTOR (8 downto 0) := (OTHERS => '0');
begin
-- Give extra bit to accound for carry,overflow,negative
a1 <= '0' & A;
b1 <= '0' & B;
with OP select
arith <=
a1 + b1 when "000", -- ADD
a1 - b1 when "001", -- SUB
a1 + b1 when "101", -- ADDI
a1 + b1 when OTHERS;
CCR(3) <= arith(7); -- Negative
CCR(2) <= '1' when arith(7 downto 0) = x"0000" else '0'; -- Zero
CCR(1) <= arith(8) xor arith(7); -- Overflow
CCR(0) <= arith(8); --Carry
RESULT <= arith(7 downto 0);
end Combinational;
|
mit
|
kaott/16-bit-risc
|
vhdl/mux2x16.vhd
|
4
|
382
|
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity mux2x16 is
port(S : in std_logic;
X,Y : in std_logic_vector(15 downto 0);
O : out std_logic_vector(15 downto 0));
end mux2x16;
architecture Logic of mux2x16 is
begin
with S select O <= X when '0',
Y when '1',
"XXXXXXXXXXXXXXXX" when others;
end Logic;
|
mit
|
gustavogarciautp/Procesador
|
Entrega 1/InstructionMemory_tb.vhd
|
1
|
1372
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY InstructionMemory_tb IS
END InstructionMemory_tb;
ARCHITECTURE behavior OF InstructionMemory_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT InstructionMemory
PORT(
Address : IN std_logic_vector(5 downto 0);
rst: IN std_logic;
Instruction : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Address : std_logic_vector(5 downto 0) := (others => '0');
signal rst: std_logic:= '0';
--Outputs
signal Instruction : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: InstructionMemory PORT MAP (
Address => Address,
rst =>rst,
Instruction => Instruction
);
-- Stimulus process
stim_proc: process
begin
rst<='0';
Address<=(others=>'0');
wait for 20 ns;
Address<="000001";
wait for 40 ns;
Address<="000010";
wait for 40 ns;
Address<="000011";
wait for 40 ns;
Address<="000100";
wait for 40 ns;
Address<="000101";
wait for 40 ns;
Address<="000110";
wait for 40 ns;
Address<="000111";
wait for 40 ns;
rst<='1';
Address<="000001";
wait for 40 ns;
Address<="000100";
wait;
end process;
END;
|
mit
|
gustavogarciautp/Procesador
|
Entrega 2/CU.vhd
|
1
|
1771
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity CU is
Port ( OP : in STD_LOGIC_VECTOR (1 downto 0);
OP3 : in STD_LOGIC_VECTOR (5 downto 0);
ALUOP : out STD_LOGIC_VECTOR (5 downto 0));
end CU;
architecture Behavioral of CU is
begin
process(OP,OP3)
begin
case OP is
when "10"=>
case OP3 is --Instrucciones aritmetico logicas
when "000001"=>ALUOP<="000000"; --0. AND
when "000101"=>ALUOP<="000001"; --1. ANDN
when "000010"=>ALUOP<="000010"; --2. OR
when "000110"=>ALUOP<="000011"; --3. ORN
when "000011"=>ALUOP<="000100"; --4. XOR
when "000111"=>ALUOP<="000101"; --5. XNOR
when "000000"=>ALUOP<="000110"; --6. ADD
when "000100"=>ALUOP<="000111"; --7. SUB
when "100101"=>ALUOP<="001000"; --8. SLL
when "100110"=>ALUOP<="001001"; --9. SRL
when "100111"=>ALUOP<="001010"; --10. SRA
when "010001"=>ALUOP<="001011"; --11. ANDcc
when "010101"=>ALUOP<="001100"; --12. ANDNcc
when "010010"=>ALUOP<="001101"; --13. ORcc
when "010110"=>ALUOP<="001110"; --14. ORNcc
when "010011"=>ALUOP<="001111"; --15. XORcc
when "010111"=>ALUOP<="010000"; --16. XNORcc
when "010000"=>ALUOP<="010001"; --17. ADDcc
when "001000"=>ALUOP<="010010"; --18. ADDX
when "011000"=>ALUOP<="010011"; --19. ADDXcc
when "010100"=>ALUOP<="010100"; --20. SUBcc
when "001100"=>ALUOP<="010101"; --21. SUBX
when "011100"=>ALUOP<="010110"; --22. SUBXcc
when "111100"=>ALUOP<="010111"; --23. SAVE
when "111101"=>ALUOP<="011000"; --24. RESTORE
when others=> ALUOP<="111111"; --Instrucciones artimetico logicas no definidas
end case;
when others=>ALUOP<="111111"; --Otras instrucciones aun no definidas
end case;
end process;
end Behavioral;
|
mit
|
KPU-RISC/KPU
|
VHDL/RCL8Bit.vhd
|
1
|
1411
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 07/17/2015 12:51:34 PM
-- Design Name:
-- Module Name: RCL8Bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RCL8Bit is
Port
(
Input : in BIT_VECTOR(7 downto 0); -- 8-bit input value
Cin : in BIT; -- Carry-in flag
Output : out BIT_VECTOR(7 downto 0); -- 8-bit output value
Cout : out BIT -- Carry-out flag
);
end RCL8Bit;
architecture Behavioral of RCL8Bit is
begin
Cout <= Input(7);
Output(0) <= Cin;
Output(1) <= Input(0);
Output(2) <= Input(1);
Output(3) <= Input(2);
Output(4) <= Input(3);
Output(5) <= Input(4);
Output(6) <= Input(5);
Output(7) <= Input(6);
end Behavioral;
|
mit
|
gustavogarciautp/Procesador
|
Entrega 2/PSRModifier_tb.vhd
|
2
|
3138
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY PSRModifier_tb IS
END PSRModifier_tb;
ARCHITECTURE behavior OF PSRModifier_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT PSRModifier
PORT(
ALUOP : IN std_logic_vector(5 downto 0);
Oper2 : IN std_logic_vector(31 downto 0);
Oper1 : IN std_logic_vector(31 downto 0);
ALURESULT : IN std_logic_vector(31 downto 0);
NZVC : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal ALUOP : std_logic_vector(5 downto 0) := (others => '0');
signal Oper2 : std_logic_vector(31 downto 0) := (others => '0');
signal Oper1 : std_logic_vector(31 downto 0) := (others => '0');
signal ALURESULT : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal NZVC : std_logic_vector(3 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: PSRModifier PORT MAP (
ALUOP => ALUOP,
Oper2 => Oper2,
Oper1 => Oper1,
ALURESULT => ALURESULT,
NZVC => NZVC
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
Oper1<="00000000000000000000000000001111";
Oper2<="00000000000000000000000000010000";
ALUOP<="001011"; --ANDcc
ALURESULT<="00000000000000000000000000000000";
wait for 20 ns;
Oper1<="00000000001111111000000000011111";
Oper2<="00000000000000000000000000000000";
ALUOP<="001100"; --ANDNcc
ALURESULT<="00000000000111111100000000001111";
wait for 20 ns;
Oper1<="11100000000000000000000000000000";
Oper2<="00111111111111111111111111100000";
ALUOP<="001101"; --ORcc
ALURESULT<="11111111111111111111111111100000";
wait for 20 ns;
Oper1<="00000000000000011111100000000000";
Oper2<="00000000000000000000000011111111";
ALUOP<="001110"; --ORNcc
ALURESULT<="11111111111111111111111100000000";
wait for 20 ns;
Oper1<="10000000000000000000000000001111";
Oper2<="00000000000000000000000000010000";
ALUOP<="001111"; --XORcc
ALURESULT<="10000000000000000000000000011111";
wait for 20 ns;
Oper1<="00000111111111100000000000000000";
Oper2<="11111000000000011111111111111111";
ALUOP<="010000"; --XNORcc
ALURESULT<="00000000000000000000000000000000";
wait for 20 ns;
Oper1<="10000000000000000000000000001111";
Oper2<="10000000000000000000000000010000";
ALUOP<="010001"; --ADDcc
ALURESULT<="00000000000000000000000000011111";
wait for 20 ns;
Oper1<="11000000000000000000000000001111";
Oper2<="11000000000000000000000000010000";
ALUOP<="010011"; --ADDXcc
ALURESULT<="10000000000000000000000000011111";
wait for 20 ns;
Oper1<="10000000000000000000000000001111";
Oper2<="01111000000000000000000000000000";
ALUOP<="010100"; --SUBcc
ALURESULT<="00001000000000000000000000001111";
wait for 20 ns;
Oper1<="00000000000000000000000000001111";
Oper2<="10000000000000000000000000010000";
ALUOP<="010110"; --SUBXcc
ALURESULT<="01111111111111111111111111111111";
wait for 20 ns;
wait;
end process;
END;
|
mit
|
jeffmagina/ECE368
|
Lab2/VGA Part 2/vga_toplevel.vhd
|
4
|
4057
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: VGA Toplevel
-- Project Name: VGA Toplevel
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Toplevel of the VGA Unit
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;
entity VGA_TOPLEVEL is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
--SW : in STD_LOGIC_VECTOR (7 downto 0);
PS2_CLK : inout STD_LOGIC;
PS2_DATA : inout STD_LOGIC;
ASCII_D : out STD_LOGIC_VECTOR (7 downto 0); -- Debug ASCII
HSYNC : out STD_LOGIC;
VSYNC : out STD_LOGIC;
VGARED : out STD_LOGIC_VECTOR (2 downto 0);
VGAGRN : out STD_LOGIC_VECTOR (2 downto 0);
VGABLU : out STD_LOGIC_VECTOR (1 downto 0));
end VGA_TOPLEVEL;
architecture Structural of VGA_TOPLEVEL is
signal ASCII : STD_LOGIC_VECTOR(7 downto 0):= (OTHERS => '0');
signal ASCII_RD : STD_LOGIC := '0';
signal ASCII_WE : STD_LOGIC := '0';
signal PCLK : STD_LOGIC;
signal vcount : STD_LOGIC_VECTOR(9 downto 0):= (OTHERS => '0');
signal hcount : STD_LOGIC_VECTOR(9 downto 0):= (OTHERS => '0');
signal blank : STD_LOGIC := '0';
signal MUX8to1_OUT : STD_LOGIC := '0';
signal BLINKER_OUTPUT : STD_LOGIC_VECTOR(7 downto 0):= (OTHERS => '0');
signal ADDR_A : STD_LOGIC_VECTOR(11 downto 0):= (OTHERS => '0');
signal ADDR_B : STD_LOGIC_VECTOR(11 downto 0):= (OTHERS => '0');
signal ADDR_W : STD_LOGIC_VECTOR(10 downto 0):= (OTHERS => '0');
signal DOUT_B : STD_LOGIC_VECTOR(7 downto 0):= (OTHERS => '0');
signal FR_DATA: STD_LOGIC_VECTOR(7 downto 0):= (OTHERS => '0');
signal ADDR_C : STD_LOGIC_VECTOR(12 downto 0):= (OTHERS => '0');
begin
ASCII_D<= ASCII;
ADDR_C <= vcount(8 downto 4)*X"50" + hcount(9 downto 3);
ADDR_B <= ADDR_C(11 downto 0);
ADDR_W <= DOUT_B(6 downto 0) & vcount(3 downto 0);
U1: entity work.CLK_25MHZ
port map( CLK_IN => CLK,
CLK_OUT => PCLK);
U2: entity work.vga_controller
port map( RST => RST,
PIXEL_CLK => PCLK,
HS => HSYNC,
VS => VSYNC,
HCOUNT => hcount,
VCOUNT => vcount,
BLANK => blank);
U3: entity work.RGB
port map( VALUE => MUX8to1_OUT,
BLANK => blank,
RED => VGARED,
GRN => VGAGRN,
BLU => VGABLU);
U4: entity work.MUX8to1
port map( SEL => hcount(2 downto 0),
DATA => BLINKER_OUTPUT,
OUTPUT => MUX8to1_OUT);
U5: entity work.FONT_ROM
port map( CLK => CLK,
ADDR => ADDR_W,
DATA => FR_DATA);
U6: entity work.BLINKER
port map( CLK => CLK,
ADDR_B => ADDR_B,
CURSOR_ADR => ADDR_A,
OUTPUT => BLINKER_OUTPUT,
FONT_ROM => FR_DATA);
U7: entity work.VGA_BUFFER_RAM
port map( CLKA => ASCII_RD,
WEA(0)=> ASCII_WE,
ADDRA => ADDR_A, -- (11 DOWNTO 0)
DINA => ASCII, -- (7 DOWNTO 0)
CLKB => CLK,
ADDRB => ADDR_B, -- (11 DOWNTO 0)
DOUTB => DOUT_B); -- (7 DOWNTO 0)
U8: entity work.KEYBOARD_CONTROLLER
port map( CLK => CLK,
RST => RST,
PS2_CLK => PS2_CLK,
PS2_DATA => PS2_DATA,
ASCII_OUT=> ASCII,
ASCII_RD => ASCII_RD,
ASCII_WE => ASCII_WE);
U9: entity work.CURSOR
port map( ASCII_CODE => ASCII,
ASCII_RD => ASCII_RD,
ASCII_WE => ASCII_WE,
CURSOR_ADDR => ADDR_A);
end Structural;
|
mit
|
gustavogarciautp/Procesador
|
Entrega 3/ALU_tb.vhd
|
1
|
7200
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ALU_tb IS
END ALU_tb;
ARCHITECTURE behavior OF ALU_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ALU
PORT(
Oper1 : IN std_logic_vector(31 downto 0);
Oper2 : IN std_logic_vector(31 downto 0);
ALUOP : IN std_logic_vector(5 downto 0);
C: IN std_logic;
ALURESULT : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Oper1 : std_logic_vector(31 downto 0) := (others => '0');
signal Oper2 : std_logic_vector(31 downto 0) := (others => '0');
signal ALUOP : std_logic_vector(5 downto 0) := (others => '0');
signal C : std_logic:='0';
--Outputs
signal ALURESULT : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ALU PORT MAP (
Oper1 => Oper1,
Oper2 => Oper2,
ALUOP => ALUOP,
C => C,
ALURESULT => ALURESULT
);
-- Stimulus process
stim_proc: process
begin
C<='1';
------------------SUB-------------------------------
ALUOP<="000111";
-- 5 - 28
Oper1<="00000000000000000000000000000101"; -- +5
Oper2<="00000000000000000000000000011100"; -- +28
wait for 20 ns;
-- 32 - 20
Oper1<="00000000000000000000000000100000";-- +32
Oper2<="00000000000000000000000000010100";-- +20
wait for 20 ns;
-- -45 - (+33)
Oper1<="11111111111111111111111111010011";-- -45
Oper2<="00000000000000000000000000100001";-- +33
wait for 20 ns;
-- -45 - (+63)
Oper1<="11111111111111111111111111010011";-- -45
Oper2<="00000000000000000000000000111111";-- +63
wait for 20 ns;
-- -45 - (-33)
Oper1<="11111111111111111111111111010011";-- -45
Oper2<="11111111111111111111111111011111";-- -33
wait for 20 ns;
-- -45 - (-63)
Oper1<="11111111111111111111111111010011";-- -45
Oper2<="11111111111111111111111111000001";-- -63
wait for 20 ns;
-- 45 - (-63)
Oper1<="00000000000000000000000000101101";-- 45
Oper2<="11111111111111111111111111000001";-- -63
wait for 20 ns;
-- 45 - (-33)
Oper1<="00000000000000000000000000101101";-- 45
Oper2<="11111111111111111111111111011111";-- -33
wait for 20 ns;
----------------SUMA----------------
ALUOP<="000110";-- 75 + 25
Oper1<="00000000000000000000000001001011";-- 75
Oper2<="00000000000000000000000000011001";-- 25
wait for 20 ns;
-- 75 + (-25)
Oper1<="00000000000000000000000001001011";-- 75
Oper2<="11111111111111111111111111100111";-- -25
wait for 20 ns;
-- 75 + (-100)
Oper1<="00000000000000000000000001001011";-- 75
Oper2<="11111111111111111111111110011100";-- -100
wait for 20 ns;
-- -75 + 25
Oper1<="11111111111111111111111110110101";-- -75
Oper2<="00000000000000000000000000011001";-- 25
wait for 20 ns;
-- -75 + 100
Oper1<="11111111111111111111111110110101";-- -75
Oper2<="00000000000000000000000001100100";-- +100
wait for 20 ns;
-- -75 + (-25)
Oper1<="11111111111111111111111110110101";-- -75
Oper2<="11111111111111111111111111100111";-- -25
wait for 20 ns;
-- -75 + (-100)
Oper1<="11111111111111111111111110110101";-- -75
Oper2<="11111111111111111111111110011100";-- -100
wait for 20 ns;
-------------------OR--------------------
ALUOP<="000010";
Oper1<="11111111111111111100011110110101";
Oper2<="00000011101010001001010000001100";
wait for 20 ns;
-----------------orn---------------------
ALUOP<="000011";
wait for 20 ns;
-----------------xor-------------------
ALUOP<="000100";
wait for 20 ns;
-----------------xnor-------------------
ALUOP<="000101";
wait for 20 ns;
-----------------and-------------------
ALUOP<="000000";
wait for 20 ns;
-----------------andn-------------------
ALUOP<="000001";
wait for 20 ns;
------------------------Instrucciones aritmetico logicas no definidas-----------------------
-----------------SLL------------------
ALUOP<="001000";
Oper1<="00000000000000011110001110011011";
Oper2<="00000000000000000000000000000011";
wait for 20 ns;
-----------------SRL-------------------
ALUOP<="001001";
Oper1<="11111000000000011110001110011011";
Oper2<="00000000000000000000000000000011";
wait for 20 ns;
-----------------SRA----------------------
ALUOP<="001010";
Oper1<="11111000000000011110001110011011";
Oper2<="00000000000000000000000000000011";
wait for 20 ns;
-----------------ANDcc---------------------
ALUOP<="001011";
Oper1<="00000111111000000010010000000111";
Oper2<="00000111111111000000000000000011";
wait for 20 ns;
-----------------ANDNcc--------------------
ALUOP<="001100";
Oper1<="00000000111111111000000010100000";
Oper2<="00001111111100000000000000000011";
wait for 20 ns;
-----------------ORcc----------------------
ALUOP<="001101";
Oper1<="00000001111111111100000000000000";
Oper2<="11111000000000111111110000000000";
wait for 20 ns;
-----------------ORNcc---------------------
ALUOP<="001110";
Oper1<="00000011111111100000011111000000";
Oper2<="00000000001111111111111100000000";
wait for 20 ns;
-----------------XORcc---------------------
ALUOP<="001111";
Oper1<="00001000100000000111111111100000";
Oper2<="00000001111110000110000011000000";
wait for 20 ns;
-----------------XNORcc--------------------
ALUOP<="010000";
Oper1<="00000001111111111100000000000111";
Oper2<="11110000001111100000110001000000";
wait for 20 ns;
-----------------ADDcc---------------------
ALUOP<="010001";
Oper1<="00000000000000000000000001101000";
Oper2<="00000000000000000000000000000101";
wait for 20 ns;
-----------------ADDX----------------------
ALUOP<="010010";
Oper1<="00000000000000100101010000000000";
Oper2<="00000000000000000000000100000011";
wait for 20 ns;
-----------------ADDXcc--------------------
ALUOP<="010011";
Oper1<="00000000000000000000000000101010";
Oper2<="00000000000000000000000000001101";
wait for 20 ns;
-----------------SUBcc---------------------
ALUOP<="010100";
Oper1<="00000000000000000000000100000000";
Oper2<="00000000000000000000000000010000";
wait for 20 ns;
-----------------SUBX----------------------
ALUOP<="010101";
Oper1<="00000000000000000000000000001111";
Oper2<="00000000000000000000000000001011";
wait for 20 ns;
-----------------SUBXcc--------------------
ALUOP<="010110";
Oper1<="00000000000000000000000100011011";
Oper2<="00000000000000000000000000000011";
wait for 20 ns;
-----------------SAVE----------------------
ALUOP<="010111";
Oper1<="00000000000000000000000000011011";
Oper2<="00000000000000000000000000001100";
wait for 20 ns;
-----------------RESTORE-------------------
ALUOP<="011000";
Oper1<="00000000000000000000000000010000";
Oper2<="00000000000000000000000000000111";
wait for 20 ns;
---------------Instrucciones no definidas--------------------------
ALUOP<="111111";
Oper1<="00000000000000011110001110011011";
Oper2<="00000000000000000000000011111111";
wait;
end process;
END;
|
mit
|
jeffmagina/ECE368
|
Lab1/ALUwithInput/load_store_unit.vhd
|
3
|
1320
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Logic_Unit
-- Project Name: OurALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Load/Store Unit
-- Operations - Load/Store to a register
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Load_Store_Unit is
Port ( CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR (7 downto 0);
IMMED : in STD_LOGIC_VECTOR (7 downto 0);
OP : in STD_LOGIC_VECTOR (3 downto 0);
RESULT : out STD_LOGIC_VECTOR (7 downto 0));
end Load_Store_Unit;
architecture Behavioral of Load_Store_Unit is
signal reg : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal w_en : std_logic := '0';-- '1' = write, '0' = read
begin
w_en <= '1' when OP="1010" else '0';
process(CLK)
begin
if (CLK'event and CLK='1') then
if (w_en = '1') then
reg <= A;
end if;
end if;
end process;
RESULT <= reg;
end Behavioral;
|
mit
|
jeffmagina/ECE368
|
Lab2/Keyboard/keycode_to_ascii.vhd
|
4
|
6904
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Keycode to Ascii
-- Project Name: Keyboard Controller
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Keycode to ascii
---------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity KEYCODE_TO_ASCII is
port(
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
KEYCODE : in STD_LOGIC_VECTOR(7 downto 0);
VALID_SIGNAL : in STD_LOGIC;
-- Output
COMPLETE: out STD_LOGIC; -- Hit Key sucessfully
ASCII : out STD_LOGIC_VECTOR(7 downto 0)--;
--KEYBOARD_OUT : out STD_LOGIC_VECTOR(7 downto 0);
--WRITE_KEYBOARD: out STD_LOGIC;
);
end KEYCODE_TO_ASCII;
architecture dataflow of KEYCODE_TO_ASCII is
type StateType is (init, idle, READ_BREAKCODE, READ_EXTENDED, READ_KEYCODE,SEND_COMPLETE);--,SEND_CAPS);
signal STATE : StateType := init;
signal ASCII_LOWER : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal ASCII_UPPER : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
shared variable Shift_Key : boolean := false;
shared variable Caps_Lock : boolean := false;
shared variable Extended : boolean := false;
begin
with KEYCODE select
ASCII_LOWER <=
-- Alphabet
x"61" when x"1C", -- a
x"62" when x"32", -- b
x"63" when x"21", -- c
x"64" when x"23", -- d
x"65" when x"24", -- e
x"66" when x"2B", -- f
x"67" when x"34", -- g
x"68" when x"33", -- h
x"69" when x"43", -- i
x"6A" when x"3B", -- j
x"6B" when x"42", -- k
x"6C" when x"4B", -- l
x"6D" when x"3A", -- m
x"6E" when x"31", -- n
x"6F" when x"44", -- o
x"70" when x"4D", -- p
x"71" when x"15", -- q
x"72" when x"2D", -- r
x"73" when x"1B", -- s
x"74" when x"2C", -- t
x"75" when x"3C", -- u
x"76" when x"2A", -- v
x"77" when x"1D", -- w
x"78" when x"22", -- x
x"79" when x"35", -- y
x"7A" when x"1A", -- z
--Top Row
x"60" when x"0E", -- `
x"31" when x"16", -- 1
x"32" when x"1E", -- 2
x"33" when x"26", -- 3
x"34" when x"25", -- 4
x"35" when x"2E", -- 5
x"36" when x"36", -- 6
x"37" when x"3D", -- 7
x"38" when x"3E", -- 8
x"39" when x"46", -- 9
x"30" when x"45", -- 0
x"2D" when x"4E", -- -
x"3D" when x"55", -- =
--Enter Corner
x"5B" when x"54", -- [
x"5D" when x"5B", -- ]
x"5C" when x"5D", -- \
x"3B" when x"4C", -- ;
x"27" when x"52", -- '
x"2C" when x"41", -- ,
x"2E" when x"49", -- .
x"2F" when x"4A", -- /
--Function Keys -- Based on the IBM PC Codes
x"1B" when x"76", -- Esc (Escape)
x"3B" when x"05", -- F1
x"3C" when x"06", -- F2
x"3D" when x"04", -- F3
x"3E" when x"0C", -- F4
x"3F" when x"03", -- F5
x"40" when x"0B", -- F6
x"41" when x"83", -- F7
x"42" when x"0A", -- F8
x"43" when x"01", -- F9
x"44" when x"09", -- F10
x"85" when x"78", -- F11
x"86" when x"07", -- F12
x"09" when x"0D", -- Tab (Horizontal Tab)
x"0D" when x"5A", -- Enter (Carriage Return)
--special characters -- taking up unneaded ascii codes for simplicity
x"05" when x"58", -- Caps Lock
x"06" when x"14", -- Ctrl
x"07" when x"11", -- Alt
x"08" when x"66", -- Back Space
x"20" when x"29", -- Space
--Direction Keys -- taking up unneaded ascii codes for simplicity
x"01" when x"75", -- Up
x"02" when x"72", -- Down
x"03" when x"6B", -- Left
x"04" when x"74", -- Right
--Unknown input
x"00" when OTHERS; -- Null
with KEYCODE select
ASCII_UPPER <=
-- Alphabet
x"41" when x"1C", -- A
x"42" when x"32", -- B
x"43" when x"21", -- C
x"44" when x"23", -- D
x"45" when x"24", -- E
x"46" when x"2B", -- F
x"47" when x"34", -- G
x"48" when x"33", -- H
x"49" when x"43", -- I
x"4A" when x"3B", -- J
x"4B" when x"42", -- K
x"4C" when x"4B", -- L
x"4D" when x"3A", -- M
x"4E" when x"31", -- N
x"4F" when x"44", -- O
x"50" when x"4D", -- P
x"51" when x"15", -- Q
x"52" when x"2D", -- R
x"53" when x"1B", -- S
x"54" when x"2C", -- T
x"55" when x"3C", -- U
x"56" when x"2A", -- V
x"57" when x"1D", -- W
x"58" when x"22", -- X
x"59" when x"35", -- Y
x"5A" when x"1A", -- Z
-- Special Upper case Characters (top left to bottom right)
-- Top Row
x"7E" when x"0E", -- ~
x"21" when x"16", -- !
x"40" when x"1E", -- @
x"23" when x"26", -- #
x"24" when x"25", -- $
x"25" when x"2E", -- %
x"5E" when x"36", -- ^
x"26" when x"3D", -- &
x"2A" when x"3E", -- *
x"28" when x"46", -- (
x"29" when x"45", -- )
x"5F" when x"4E", -- _
x"2B" when x"55", -- +
-- Enter Corner
x"7B" when x"54", -- {
x"7D" when x"5B", -- }
x"7C" when x"5D", -- |
x"3A" when x"4C", -- :
x"22" when x"52", -- "
x"3C" when x"41", -- <
x"3E" when x"49", -- >
x"3F" when x"4A", -- ?
-- Unknown Key
x"00" when OTHERS; -- Null
PROCESS (KEYCODE,CLK, RST)
BEGIN
if (RST = '1') then
STATE <= init;
elsif (CLK'event and CLK= '0' ) then
case STATE is
when init =>
ascii <= (OTHERS => '0');
COMPLETE <= '0';
state <= idle;
when idle =>
COMPLETE <= '0';
if VALID_SIGNAL= '1' then
Extended := false;
if keycode=x"E0" then
state <= READ_EXTENDED;
-- A Key was pressed
elsif keycode=x"F0" then
state <= READ_KEYCODE;
else
-- No break code yet
state <= idle;
end if;
-- Shift Key was press (on)
if (keycode=x"12" or keycode=x"59") then
Shift_Key := true;
end if;
end if;
when READ_EXTENDED =>
if VALID_SIGNAL= '1' then
Extended := true;
if keycode=x"F0" then
state <= READ_KEYCODE;
else
state <= idle;
end if;
end if;
when READ_BREAKCODE =>
if VALID_SIGNAL= '1' then
if keycode=x"F0" then
state <= READ_KEYCODE;
else
state <= idle;
end if;
end if;
when READ_KEYCODE =>
if VALID_SIGNAL= '1' then
-- Shift Key was released (off)
if (keycode=x"12" or keycode=x"59") then
Shift_Key := false;
elsif (keycode=x"58") then
if (Caps_Lock = false) then
Caps_Lock := true;
else
Caps_Lock := false;
end if;
--state <= SEND_CAPS;
else
if (Shift_Key = true or Caps_Lock = true) then
ascii <= ASCII_UPPER;
else
ascii <= ASCII_LOWER;
end if;
end if;
state <= SEND_COMPLETE;
end if;
when SEND_COMPLETE =>
COMPLETE <= '1';
state <= idle;
--when SEND_CAPS =>
when OTHERS =>
state <= idle;
end case;
end if;
end process;
end architecture dataflow;
|
mit
|
gustavogarciautp/Procesador
|
Entrega 3/ALU.vhd
|
1
|
2164
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity ALU is
Port ( Oper1 : in STD_LOGIC_VECTOR (31 downto 0);
Oper2 : in STD_LOGIC_VECTOR (31 downto 0);
ALUOP : in STD_LOGIC_VECTOR (5 downto 0);
C: in STD_LOGIC;
ALURESULT : out STD_LOGIC_VECTOR (31 downto 0));
end ALU;
architecture Behavioral of ALU is
begin
process(Oper1,Oper2,ALUOP,C)
begin
case ALUOP is
when "000000"=>
ALURESULT<=Oper1 and Oper2;--AND
when "000001"=>
ALURESULT<=Oper1 and not Oper2;--ANDN
when "000010"=>
ALURESULT<=Oper1 or Oper2;--OR
when "000011"=>
ALURESULT<=Oper1 or not Oper2;--ORN
when "000100"=>
ALURESULT<=Oper1 xor Oper2;--XOR
when "000101"=>
ALURESULT<=Oper1 xnor Oper2;--XNOR
when "000110"=>
ALURESULT<=Oper1+Oper2;--ADD
when "000111"=>
ALURESULT<=Oper1-Oper2;--SUB
when "001000"=> --SLL
ALURESULT<=std_logic_vector(unsigned(Oper1) sll conv_integer(oper2(4 downto 0)));
when "001001"=> --SRL
ALURESULT<=std_logic_vector(unsigned(Oper1) srl conv_integer(oper2(4 downto 0)));
when "001010"=> --SRA
ALURESULT<=To_StdLogicVector(to_bitvector(Oper1) sra conv_integer(oper2(4 downto 0)));
when "001011"=>
ALURESULT<=Oper1 and Oper2;--ANDcc
when "001100"=>
ALURESULT<=Oper1 and not Oper2;--ANDNcc
when "001101"=>
ALURESULT<=Oper1 or Oper2;--ORcc
when "001110"=>
ALURESULT<=Oper1 or not Oper2;--ORNcc
when "001111"=>
ALURESULT<=Oper1 xor Oper2;--XORcc
when "010000"=>
ALURESULT<=Oper1 xnor Oper2;--XNORcc
when "010001"=>
ALURESULT<=Oper1+Oper2;--ADDcc
when "010010"=> --ADDX
ALURESULT<=Oper1+Oper2+C;
when "010011"=> --ADDXcc
ALURESULT<=Oper1+Oper2+C;
when "010100"=>
ALURESULT<=Oper1-Oper2;--SUBcc
when "010101"=> --SUBX
ALURESULT<=Oper1-Oper2-C;
when "010110"=> --SUBXcc
ALURESULT<=Oper1-Oper2-C;
when "010111"=> --SAVE
ALURESULT<=Oper1+Oper2;
when "011000"=> --RESTORE
ALURESULT<=Oper1+Oper2;
when others=>--"111111" Instrucciones no definidas
ALURESULT<=(others=>'0');
end case;
end process;
end Behavioral;
|
mit
|
KPU-RISC/KPU
|
VHDL/CPU8Bit.vhd
|
1
|
39284
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 05/20/2015 10:41:46 PM
-- Design Name:
-- Module Name: CPU8Bit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity CPU8Bit is
port
(
Clock : in BIT;
Start : in BIT;
Reset : in BIT;
Load_RAM : in BIT;
Select_RAM : in BIT;
Address_RAM : in BIT_VECTOR(15 downto 0);
Input_RAM : in BIT_VECTOR(7 downto 0);
PC : in BIT_VECTOR(15 downto 0);
Load_PC : in BIT;
InputPort_A : in BIT_VECTOR(7 downto 0);
InputPort_B : in BIT_VECTOR(7 downto 0);
OutputPort_C : out BIT_VECTOR(7 downto 0);
OutputPort_D : out BIT_VECTOR(7 downto 0);
Instruction : out BIT_VECTOR(7 downto 0)
);
end CPU8Bit;
architecture Behavioral of CPU8Bit is
component Counter4Bit is
port
(
Clock : in BIT;
Reset : in BIT;
Output: out STD_LOGIC_VECTOR(3 downto 0)
);
end component Counter4Bit;
component Decoder3to8 is
Port
(
F : in BIT_VECTOR(2 downto 0); -- 3-Bit Function Code (Input)
X : out BIT_VECTOR(7 downto 0); -- 8-Bit State (Output)
Started: in BIT -- Is the CPU already running?
);
end component Decoder3to8;
component RAM_Wrapper is
port
(
Clock: IN BIT;
Load: IN BIT;
Sel: IN BIT; -- Requests the data from the RAM
Ret: IN BIT; -- Returns the data from the RAM and places it onto the data bus
Address: IN BIT_VECTOR(15 DOWNTO 0);
Input: IN BIT_VECTOR(7 DOWNTO 0);
Output: OUT BIT_VECTOR(7 DOWNTO 0)
);
end component RAM_Wrapper;
component Register8Bit is
Port
(
Load : in BIT; -- Load Line
Sel : in BIT; -- Select Line
Input : in BIT_VECTOR(7 downto 0); -- 8-bit input value
Output : out BIT_VECTOR(7 downto 0); -- 8-bit output value
State : out BIT_VECTOR(7 downto 0) -- Current state of the Flip Flop
);
end component Register8Bit;
component Register8Bit2WayOutput is
Port
(
Load : in BIT; -- Load Line
Sel1 : in BIT; -- Select Line #1
Sel2 : in BIT; -- Select Line #2
Input : in BIT_VECTOR(7 downto 0); -- 8-bit input value
Output1 : out BIT_VECTOR(7 downto 0); -- 8-bit output value #1
Output2 : out BIT_VECTOR(7 downto 0); -- 8-bit output value #2
State : out BIT_VECTOR(7 downto 0) -- Current state of the Flip Flop
);
end component Register8Bit2WayOutput;
component Register8Bit2WayInput is
Port
(
Load1 : in BIT; -- Load Line #1
Load2 : in BIT; -- Load Line #2
Sel : in BIT; -- Select Line
Input1 : in BIT_VECTOR(7 downto 0); -- 8-bit input value #1
Input2 : in BIT_VECTOR(7 downto 0); -- 8-bit input value #2
Output : out BIT_VECTOR(7 downto 0); -- 8-bit output value
State : out BIT_VECTOR(7 downto 0) -- Current state of the Flip Flop
);
end component Register8Bit2WayInput;
component Register16Bit is
Port
(
Load : in BIT; -- Load Line
Sel : in BIT; -- Select Line
Input : in BIT_VECTOR(15 downto 0); -- 16-bit input value
Output : out BIT_VECTOR(15 downto 0); -- 16-bit output value
State : out BIT_VECTOR(15 downto 0) -- Current state of the Flip Flop
);
end component Register16Bit;
component RegisterExtended16Bit is
Port
(
Load_8Bit_L: in BIT; -- Load Line #1 (bits 0 - 7)
Load_8Bit_H: in BIT; -- Load Line #2 (bits 8 - 15)
Load_16Bit: in BIT; -- Load Line #3 (bits 0 - 15)
Select_8Bit_L: in BIT; -- Select Line #1 (bits 0 - 7)
Select_8Bit_H: in BIT; -- Select Line #2 (bits 8 - 15)
Select_16Bit: in BIT; -- Select Line #3 (bits 0 - 15)
Input_8Bit_L: in BIT_VECTOR(7 downto 0); -- 8-bit input value (bits 0 - 7)
Input_8Bit_H: in BIT_VECTOR(7 downto 0); -- 8-bit input value (bits 8 - 15)
Input_16Bit: in BIT_VECTOR(15 downto 0); -- 16-bit input value (bits 0 - 15)
Output_8Bit_L: out BIT_VECTOR(7 downto 0); -- 8-bit output value (bits 0 - 7)
Output_8Bit_H: out BIT_VECTOR(7 downto 0); -- 8-bit output value (bits 8 - 15)
Output_16Bit: out BIT_VECTOR(15 downto 0); -- 16-bit output value (bits 0 - 15)
State_8Bit_L: out BIT_VECTOR(7 downto 0); -- Current state of the Flip Flop (bits 0 - 7)
State_8Bit_H: out BIT_VECTOR(7 downto 0); -- Current state of the Flip Flop (bits 8 - 15)
State_16Bit: out BIT_VECTOR(15 downto 0) -- Current state of the Flip Flop (bits 0 - 15)
);
end component RegisterExtended16Bit;
component Increment8Bit is
Port
(
Input : in BIT_VECTOR(7 downto 0); -- 8-bit input value
Cin : in BIT; -- Carry-in flag
Output : out BIT_VECTOR(7 downto 0); -- 8-bit output value
Cout : out BIT -- Carry-out flag
);
end component Increment8Bit;
component Increment16Bit is
Port
(
Input : in BIT_VECTOR(15 downto 0); -- 16-bit input value
Cin : in BIT; -- Carry-in flag
Output : out BIT_VECTOR(15 downto 0); -- 16-bit output value
Cout : out BIT -- Carry-out flag
);
end component Increment16Bit;
component InstructionDecoder is
port
(
TimingSignals : in BIT_VECTOR(7 downto 0); -- The 8 different timing states
Instruction : in BIT_VECTOR(7 downto 0); -- The instruction to execute
Flags : in BIT_VECTOR(7 downto 0); -- Content of the FLAGS register - needed for conditional jumps
-- ==============================================================
-- The various control lines of the CPU which go low/high
-- depending on the timing state and the instruction to execute:
-- ==============================================================
Load_PC : out BIT;
Select_PC : out BIT;
Load_SRAM: out BIT;
Select_SRAM: out BIT;
Return_SRAM: out BIT;
Load_INC: out BIT;
Select_INC: out BIT;
Load_INSTR: out BIT;
Select_INSTR_To_DataBus: out BIT;
Select_INSTR_To_ALU: out BIT;
Load_A_From_DataBus: out BIT;
Select_A_To_ALU: out BIT;
Load_B_From_DataBus: out BIT;
Select_B_To_ALU: out BIT;
Load_C_From_DataBus: out BIT;
Load_InternalA_From_DataBus: out BIT;
Select_InternalA_To_DataBus: out BIT;
Load_Flags: out BIT;
Select_A_To_DataBus: out BIT;
Select_B_To_DataBus: out BIT;
Select_C_To_DataBus: out BIT;
Load_D_From_DataBus: out BIT;
Select_D_To_DataBus: out BIT;
Load_E_From_DataBus: out BIT;
Select_E_To_DataBus: out BIT;
Load_F_From_DataBus: out BIT;
Select_F_To_DataBus: out BIT;
Load_G_From_DataBus: out BIT;
Select_G_To_DataBus: out BIT;
Load_H_From_DataBus: out BIT;
Select_H_To_DataBus: out BIT;
load_M_From_AddressBus: out BIT;
select_M_To_AddressBus: out BIT;
load_XL_From_DataBus: out BIT;
load_XH_From_DataBus: out BIT;
load_X_From_AddressBus: out BIT;
select_XL_To_DataBus: out BIT;
select_XH_To_DataBus: out BIT;
select_X_To_AddressBus: out BIT;
Load_J_From_AddressBus: out BIT;
Select_J_To_AddressBus: out BIT;
Load_SP_From_AddressBus: out BIT;
Select_SP_To_AddressBus: out BIT;
Load_BP_From_AddressBus: out BIT;
Select_BP_To_AddressBus: out BIT;
Load_Y_From_AddressBus: out BIT;
Select_Y_To_AddressBus: out BIT;
Load_Z_From_AddressBus: out BIT;
Select_Z_To_AddressBus: out BIT;
Load_Adder16Bit_InputA: out BIT;
Select_Adder16Bit_InputA: out BIT;
Load_Adder16Bit_InputB: out BIT;
Select_Adder16Bit_InputB: out BIT;
Load_Adder16Bit_OutputC: out BIT;
Select_Adder16Bit_OutputC: out BIT;
load_FlagsSaved_From_FlagsRegister: out BIT;
load_FlagsSaved_To_FlagsRegister: out BIT;
Load_FlagsFromDataBus: out BIT;
Select_FlagsToFlagsBus: out BIT;
Load_FlagsFromFlagsBus: out BIT;
Select_FlagsToDataBus: out BIT;
Select_Flags: out BIT;
Select_PortA_To_DataBus: out BIT;
Select_PortB_To_DataBus: out BIT;
Load_PortC_From_DataBus: out BIT;
Load_PortD_From_DataBus: out BIT;
StopCPU: out BIT
);
end component InstructionDecoder;
component ALU8Bit is
Port
(
InputA : in BIT_VECTOR(7 downto 0); -- 1st 8-bit input value
InputB : in BIT_VECTOR(7 downto 0); -- 2nd 8-bit input value
FunctionCode: in BIT_VECTOR(3 downto 0); -- 4-bit function code
CarryIn: in BIT; -- Carry-Bit
Output : out BIT_VECTOR(7 downto 0); -- 8-bit output value
Sign : out BIT; -- Do we have a negative number?
Zero : out BIT; -- Do we have a zero value?
Carry : out BIT; -- Do we have a carry?
Overflow: out BIT -- Do we have an overflow?
);
end component ALU8Bit;
component RippleCarryAdder16Bit is
Port
(
InputA : in BIT_VECTOR(15 downto 0); -- 1st 8-bit input value
InputB : in BIT_VECTOR(15 downto 0); -- 2nd 8-bit input value
Cin : in BIT; -- Carry-in flag
Output : out BIT_VECTOR(15 downto 0); -- 8-bit output value
Cout : out BIT -- Carry-out flag
);
end component RippleCarryAdder16Bit;
-- 4-bit binary counter & Control Lines
signal CounterOutput : STD_LOGIC_VECTOR(3 downto 0);
signal CounterOutputBitVector : BIT_VECTOR(3 downto 0);
signal TimingSignals : BIT_VECTOR(7 downto 0);
-- Signals needed for the RAM memory cell
signal loadRAM: BIT;
signal selectRAM: BIT;
signal returnRAM: BIT;
signal addressRAM: BIT_VECTOR(15 downto 0);
signal inputRAM: BIT_VECTOR(7 downto 0);
signal outputRAM: BIT_VECTOR(7 downto 0);
-- Signals needed for register "A"
signal load_A_From_DataBus : BIT; -- Load Line
signal select_A_To_DataBus : BIT; -- Select Line to Data Bus
signal select_A_To_ALU : BIT; -- Select Line to ALU
signal in_A_From_DataBus : BIT_VECTOR(7 downto 0); -- Input Data
signal out_A_To_DataBus : BIT_VECTOR(7 downto 0); -- Output Data
signal out_A_To_ALU : BIT_VECTOR(7 downto 0); -- Output Data
-- Signals needed for register "B"
signal load_B_From_DataBus : BIT; -- Load Line
signal select_B_To_DataBus : BIT; -- Select Line to Data Bus
signal select_B_To_ALU : BIT; -- Select Line to ALU
signal in_B_From_DataBus : BIT_VECTOR(7 downto 0); -- Input Data
signal out_B_To_DataBus : BIT_VECTOR(7 downto 0); -- Output Data
signal out_B_To_ALU : BIT_VECTOR(7 downto 0); -- Output Data
-- Signals needed for register "C"
signal load_C_From_DataBus : BIT; -- Load Line
signal select_C_To_DataBus : BIT; -- Select Line
signal in_C_From_DataBus : BIT_VECTOR(7 downto 0); -- Input Data
signal out_C_To_DataBus : BIT_VECTOR(7 downto 0); -- Output Data
-- Signals needed for register "D"
signal load_D_From_DataBus : BIT; -- Load Line
signal select_D_To_DataBus : BIT; -- Select Line
signal in_D_From_DataBus : BIT_VECTOR(7 downto 0); -- Input Data
signal out_D_To_DataBus : BIT_VECTOR(7 downto 0); -- Output Data
-- Signals needed for register "E"
signal load_E_From_DataBus : BIT; -- Load Line
signal select_E_To_DataBus : BIT; -- Select Line
signal in_E_From_DataBus : BIT_VECTOR(7 downto 0); -- Input Data
signal out_E_To_DataBus : BIT_VECTOR(7 downto 0); -- Output Data
-- Signals needed for register "F"
signal load_F_From_DataBus : BIT; -- Load Line
signal select_F_To_DataBus : BIT; -- Select Line
signal in_F_From_DataBus : BIT_VECTOR(7 downto 0); -- Input Data
signal out_F_To_DataBus : BIT_VECTOR(7 downto 0); -- Output Data
-- Signals needed for register "G"
signal load_G_From_DataBus : BIT; -- Load Line
signal select_G_To_DataBus : BIT; -- Select Line
signal in_G_From_DataBus : BIT_VECTOR(7 downto 0); -- Input Data
signal out_G_To_DataBus : BIT_VECTOR(7 downto 0); -- Output Data
-- Signals needed for register "H"
signal load_H_From_DataBus : BIT; -- Load Line
signal select_H_To_DataBus : BIT; -- Select Line
signal in_H_From_DataBus : BIT_VECTOR(7 downto 0); -- Input Data
signal out_H_To_DataBus : BIT_VECTOR(7 downto 0); -- Output Data
-- Signals needed for register "Flags"
signal load_Flags : BIT; -- Load Line
signal select_Flags : BIT; -- Select Line
signal in_Flags_From_ALU : BIT_VECTOR(7 downto 0); -- Input Data
signal out_Flags : BIT_VECTOR(7 downto 0); -- Output Data
signal in_Flags : BIT_VECTOR(7 downto 0);
signal state_Flags: BIT_VECTOR(7 downto 0);
-- Signals needed for register "FlagsSaved"
signal load_FlagsSaved_From_FlagsBus: BIT;
signal select_FlagsSaved_To_FlagsBus: BIT;
signal out_FlagsSaved_To_FlagsBus: BIT_VECTOR(7 downto 0);
signal in_FlagsSaved_From_FlagsBus : BIT_VECTOR(7 downto 0);
-- Signals needed for register "FlagsInBuffer"
signal load_FlagsFromDataBus: BIT;
signal select_FlagsToFlagsBus: BIT;
signal in_FlagsFromDataBus: BIT_VECTOR(7 downto 0);
signal out_FlagsToFlagsBus: BIT_VECTOR(7 downto 0);
-- Signals needed for register "FlagsOutBuffer"
signal load_FlagsFromFlagsBus: BIT;
signal select_FlagsToDataBus: BIT;
signal in_FlagsFromFlagsBus: BIT_VECTOR(7 downto 0);
signal out_FlagsToDataBus: BIT_VECTOR(7 downto 0);
-- Signals needed for register "Internal A"
signal load_InternalA_From_DataBus : BIT; -- Load Line
signal select_InternalA_To_DataBus : BIT; -- Select Line
signal in_InternalA_From_DataBus : BIT_VECTOR(7 downto 0); -- Input Data
signal out_InternalA : BIT_VECTOR(7 downto 0); -- Output Data
-- Signals needed for register "Program Counter"
signal l_PC : BIT; -- Load Line
signal select_PC : BIT; -- Select Line
signal in_PC : BIT_VECTOR(15 downto 0); -- Input Data
signal out_PC : BIT_VECTOR(15 downto 0); -- Output Data
-- Signals needed for register "Increment Program Counter"
signal load_INC : BIT; -- Load Line
signal select_INC : BIT; -- Select Line
signal in_INC : BIT_VECTOR(15 downto 0); -- Input Data
signal out_INC : BIT_VECTOR(15 downto 0); -- Output Data
-- Signals needed for 16-bit register "M"
signal load_M_From_AddressBus: BIT;
signal select_M_To_AddressBus: BIT;
signal in_M_From_AddressBus: BIT_VECTOR(15 downto 0);
signal out_M_To_AddressBus: BIT_VECTOR(15 downto 0);
-- Signals needed for 16-bit register "X"
signal load_XL_From_DataBus: BIT;
signal load_XH_From_DataBus: BIT;
signal load_X_From_AddressBus: BIT;
signal select_XL_To_DataBus: BIT;
signal select_XH_To_DataBus: BIT;
signal select_X_To_AddressBus: BIT;
signal in_XL_From_DataBus: BIT_VECTOR(7 downto 0);
signal in_XH_From_DataBus: BIT_VECTOR(7 downto 0);
signal in_X_From_AddressBus: BIT_VECTOR(15 downto 0);
signal out_XL_To_DataBus: BIT_VECTOR(7 downto 0);
signal out_XH_To_DataBus: BIT_VECTOR(7 downto 0);
signal out_X_To_AddressBus: BIT_VECTOR(15 downto 0);
-- Signals needed for register "J"
signal load_J_From_AddressBus: BIT;
signal select_J_To_AddressBus: BIT;
signal in_J_From_AddressBus: BIT_VECTOR(15 downto 0);
signal out_J_To_AddressBus: BIT_VECTOR(15 downto 0);
-- Signals needed for register "SP"
signal load_SP_From_AddressBus: BIT;
signal select_SP_To_AddressBus: BIT;
signal in_SP_From_AddressBus: BIT_VECTOR(15 downto 0);
signal out_SP_To_AddressBus: BIT_VECTOR(15 downto 0);
-- Signals needed for register "BP"
signal load_BP_From_AddressBus: BIT;
signal select_BP_To_AddressBus: BIT;
signal in_BP_From_AddressBus: BIT_VECTOR(15 downto 0);
signal out_BP_To_AddressBus: BIT_VECTOR(15 downto 0);
-- Signals needed for register "Y"
signal load_Y_From_AddressBus: BIT;
signal select_Y_To_AddressBus: BIT;
signal in_Y_From_AddressBus: BIT_VECTOR(15 downto 0);
signal out_Y_To_AddressBus: BIT_VECTOR(15 downto 0);
-- Signals needed for register "Z"
signal load_Z_From_AddressBus: BIT;
signal select_Z_To_AddressBus: BIT;
signal in_Z_From_AddressBus: BIT_VECTOR(15 downto 0);
signal out_Z_To_AddressBus: BIT_VECTOR(15 downto 0);
-- Signals needed for the register "Instruction"
signal load_INSTR : BIT; -- Load Line
signal select_INSTR_To_DataBus : BIT; -- Select Line to Data Bus
signal select_INSTR_To_ALU: BIT; -- Select Line to ALU
signal in_INSTR : BIT_VECTOR(7 downto 0); -- Input Data
signal out_INSTR_To_DataBus : BIT_VECTOR(7 downto 0); -- Output Data to Data Bus
signal out_INSTR_To_ALU : BIT_VECTOR(7 downto 0); -- Output Data to ALU
signal currentInstruction : BIT_VECTOR(7 downto 0); -- The current instruction to be processed
-- Signals needed for the 16-bit Ripple Carry Adder
signal Output_Adder16Bit: BIT_VECTOR(15 downto 0); -- 16-bit output value for the 16-bit adder
-- Signals needed for the register "Adder16Bit_OutputC"
signal load_Adder16Bit_OutputC: BIT;
signal select_Adder16Bit_OutputC: BIT;
signal Output_RegisterAdder16Bit: BIT_VECTOR(15 downto 0);
-- Signals needed for the register "Adder16Bit_InputA"
signal load_Adder16Bit_InputA: BIT;
signal select_Adder16Bit_InputA: BIT;
signal in_Adder16Bit_InputA_From_AddressBus: BIT_VECTOR(15 downto 0);
signal out_Adder16Bit_InputA: BIT_VECTOR(15 downto 0);
-- Signals needed for the register "Adder16Bit_InputB"
signal load_Adder16Bit_InputB: BIT;
signal select_Adder16Bit_InputB: BIT;
signal in_Adder16Bit_InputB_From_AddressBus: BIT_VECTOR(15 downto 0);
signal out_Adder16Bit_InputB: BIT_VECTOR(15 downto 0);
-- Signals needed for Input Port "A"
signal select_PortA_To_DataBus: BIT;
signal out_PortA_To_DataBus: BIT_VECTOR(7 downto 0);
-- Signals needed for Output Port "C"
signal load_PortC_From_DataBus: BIT;
signal in_PortC_FromDataBus: BIT_VECTOR(7 downto 0);
-- Signals needed for Output Port "D"
signal load_PortD_From_DataBus: BIT;
signal in_PortD_FromDataBus: BIT_VECTOR(7 downto 0);
-- Signals needed for Input Port "B"
signal select_PortB_To_DataBus: BIT;
signal out_PortB_To_DataBus: BIT_VECTOR(7 downto 0);
-- 16-bit Address Bus
signal AddressBus : BIT_VECTOR(15 downto 0);
-- 8-bit Data Bus
signal DataBus : BIT_VECTOR(7 downto 0);
-- 8-bit Flags Bus
signal FlagsBus : BIT_VECTOR(7 downto 0);
signal FlagsTemp: BIT_VECTOR(7 downto 0);
-- Incrementer for Program Counter
signal CarryOutIncrementer : BIT;
-- Signals needed to connect the TestBench to the CPU
signal load_SRAM : BIT;
signal select_SRAM : BIT;
signal load_PC1 : BIT;
-- ALU output flags
signal ALU_Sign: BIT := '0';
signal ALU_Zero: BIT := '0';
signal ALU_Carry: BIT := '0';
signal out_ALU: BIT_VECTOR(7 downto 0);
signal stopped: BIT := '0';
-- This line stores the first 5 bits from the Register "Internal A"
signal Truncated_InternalA : BIT_VECTOR(7 downto 0);
begin
-- =============================================================
-- The following section contains the definition of the various
-- components of the CPU
-- =============================================================
-- That's the 4-bit binary counter
Counter: Counter4Bit port map (Clock, Reset, CounterOutput);
CounterOutputBitVector <= TO_BITVECTOR(CounterOutput);
-- The decoder generates the signals along the 8 control lines out from the 4-bit binary counter
Decoder: Decoder3to8 port map(CounterOutputBitVector(2 downto 0), TimingSignals, Start and not stopped);
-- This is our main-memory - 64K
ram: RAM_Wrapper port map(Clock, loadRAM, selectRAM, returnRAM, addressRAM, inputRAM, OutputRAM);
-- Connects the address bus to the SRAM address input
addressRAM <= AddressBus or
Address_RAM;
-- The Instruction Decoder - the brain within the brain.
-- Based on the timing signal and the current instruction the
-- various CPU control lines are going high/low.
instrDecoder: InstructionDecoder port map(TimingSignals,
currentInstruction,
out_Flags,
load_PC1,
select_PC,
load_SRAM,
select_SRAM,
returnRAM,
load_INC,
select_INC,
load_INSTR,
select_INSTR_To_DataBus,
select_INSTR_To_ALU,
load_A_From_DataBus,
select_A_To_ALU,
load_B_From_DataBus,
select_B_To_ALU,
load_C_From_DataBus,
load_InternalA_From_DataBus,
select_InternalA_To_DataBus,
load_Flags,
select_A_To_DataBus,
select_B_To_DataBus,
select_C_To_DataBus,
load_D_From_DataBus,
select_D_To_DataBus,
load_E_From_DataBus,
select_E_To_DataBus,
load_F_From_DataBus,
select_F_To_DataBus,
load_G_From_DataBus,
select_G_To_DataBus,
load_H_From_DataBus,
select_H_To_DataBus,
load_M_From_AddressBus,
select_M_To_AddressBus,
load_XL_From_DataBus,
load_XH_From_DataBus,
load_X_From_AddressBus,
select_XL_To_DataBus,
select_XH_To_DataBus,
select_X_To_AddressBus,
load_J_From_AddressBus,
select_J_To_AddressBus,
load_SP_From_AddressBus,
select_SP_To_AddressBus,
load_BP_From_AddressBus,
select_BP_To_AddressBus,
load_Y_From_AddressBus,
select_Y_To_AddressBus,
load_Z_From_AddressBus,
select_Z_To_AddressBus,
load_Adder16Bit_InputA,
select_Adder16Bit_InputA,
load_Adder16Bit_InputB,
select_Adder16Bit_InputB,
load_Adder16Bit_OutputC,
select_Adder16Bit_OutputC,
load_FlagsSaved_From_FlagsBus,
select_FlagsSaved_To_FlagsBus,
load_FlagsFromDataBus,
select_FlagsToFlagsBus,
load_FlagsFromFlagsBus,
select_FlagsToDataBus,
select_Flags,
select_PortA_To_DataBus,
select_PortB_To_DataBus,
load_PortC_From_DataBus,
load_PortD_From_DataBus,
stopped);
-- 16-bit Register Definitions
rPC: Register16Bit port map(l_PC, select_PC, in_PC, out_PC); -- Register "Program Counter" (PC)
rINC: Register16Bit port map(load_INC, select_INC, in_INC, out_INC); -- Register "Program Counter Increment" (INC)
rJ: Register16Bit port map(load_J_From_AddressBus, select_J_To_AddressBus, in_J_From_AddressBus, out_J_To_AddressBus); -- Register "Jump" - stores the JMP target address
rM: Register16Bit port map(load_M_From_AddressBus, select_M_To_AddressBus, in_M_From_AddressBus, out_M_To_AddressBus); -- Register "M"
rSP: Register16Bit port map(load_SP_From_AddressBus, select_SP_To_AddressBus, in_SP_From_AddressBus, out_SP_To_AddressBus); -- Register "SP"
rBP: Register16Bit port map(load_BP_From_AddressBus, select_BP_To_AddressBus, in_BP_From_AddressBus, out_BP_To_AddressBus); -- Register "BP"
rY: Register16Bit port map(load_Y_From_AddressBus, select_Y_To_AddressBus, in_Y_From_AddressBus, out_Y_To_AddressBus); -- Register "Y"
rZ: Register16Bit port map(load_Z_From_AddressBus, select_Z_To_AddressBus, in_Z_From_AddressBus, out_Z_To_AddressBus); -- Register "Z"
-- 16-bit Ripple Carry Adder
adder16Bit: RippleCarryAdder16Bit port map(out_Adder16Bit_InputA, out_Adder16Bit_InputB, '0', Output_Adder16Bit);
rAdder16Bit_InputA: Register16Bit port map(load_Adder16Bit_InputA, select_Adder16Bit_InputA, in_Adder16Bit_InputA_From_AddressBus, out_Adder16Bit_InputA);
rAdder16Bit_InputB: Register16Bit port map(load_Adder16Bit_InputB, select_Adder16Bit_InputB, in_Adder16Bit_InputB_From_AddressBus, out_Adder16Bit_InputB);
rAdder16Bit_OutputC: Register16Bit port map(load_Adder16Bit_OutputC, select_Adder16Bit_OutputC, Output_Adder16Bit, Output_RegisterAdder16Bit);
-- Incrementer for Program Counter
-- It takes the input from the AddressBus and writes
-- the output into the input of the INC register (=> in_INC)
inc: Increment16Bit port map(AddressBus, '0', in_INC, CarryOutIncrementer);
-- 8-bit Instruction Register
rINSTR: Register8Bit2WayOutput port map(load_INSTR, select_INSTR_To_DataBus, select_INSTR_To_ALU, in_INSTR, out_INSTR_To_DataBus, out_INSTR_To_ALU, currentInstruction);
-- Internal ALU registers
rA: Register8Bit2WayOutput port map(load_A_From_DataBus, select_A_To_DataBus, select_A_To_ALU, in_A_From_DataBus, out_A_To_DataBus, out_A_To_ALU); -- Register "A": Input to ALU
rB: Register8Bit2WayOutput port map(load_B_From_DataBus, select_B_To_DataBus, select_B_To_ALU, in_B_From_DataBus, out_B_To_DataBus, out_B_To_ALU); -- Register "B": Input to ALU
rC: Register8Bit port map(load_C_From_DataBus, select_C_To_DataBus, in_C_From_DataBus, out_C_To_DataBus); -- Register "C": Output from ALU
rInternalA: Register8Bit port map(load_InternalA_From_DataBus, select_InternalA_To_DataBus, in_InternalA_From_DataBus, out_InternalA); -- Register "Internal A" for ALU
-- General purpose 8-bit Register Definitions
rD: Register8Bit port map(load_D_From_DataBus, select_D_To_DataBus, in_D_From_DataBus, out_D_To_DataBus); -- Register "D"
rE: Register8Bit port map(load_E_From_DataBus, select_E_To_DataBus, in_E_From_DataBus, out_E_To_DataBus); -- Register "E"
rF: Register8Bit port map(load_F_From_DataBus, select_F_To_DataBus, in_F_From_DataBus, out_F_To_DataBus); -- Register "F"
rG: Register8Bit port map(load_G_From_DataBus, select_G_To_DataBus, in_G_From_DataBus, out_G_To_DataBus); -- Register "G"
rH: Register8Bit port map(load_H_From_DataBus, select_H_To_DataBus, in_H_From_DataBus, out_H_To_DataBus); -- Register "H"
-- 16-bit Extended Register "X"
-- Consists of the 2 internal 8-bit wide registers "XL" and "XH"
rX: RegisterExtended16Bit port map(load_XL_From_DataBus,
load_XH_From_DataBus,
load_X_From_AddressBus,
select_XL_To_DataBus,
select_XH_To_DataBus,
select_X_To_AddressBus,
in_XL_From_DataBus,
in_XH_From_DataBus,
in_X_From_AddressBus,
out_XL_To_DataBus,
out_XH_To_DataBus,
out_X_To_AddressBus);
-- Input/Output Ports
pA: Register8Bit port map('1', select_PortA_To_DataBus, InputPort_A, out_PortA_To_DataBus); -- Input Port "A"
pB: Register8Bit port map('1', select_PortB_To_DataBus, InputPort_B, out_PortB_To_DataBus); -- Input Port "B"
p_outC: Register8Bit port map(load_PortC_From_DataBus, '1', in_PortC_FromDataBus, OutputPort_C); -- Output Port "C"
p_outD: Register8Bit port map(load_PortD_From_DataBus, '1', in_PortD_FromDataBus, OutputPort_D); -- Output Port "D"
-- Flags related registers
rFlags : Register8Bit port map(load_Flags, select_Flags, in_Flags, out_Flags);
rFlagsSaved : Register8Bit port map(load_FlagsSaved_From_FlagsBus, select_FlagsSaved_To_FlagsBus, in_FlagsSaved_From_FlagsBus, out_FlagsSaved_To_FlagsBus, state_Flags); -- Stores a copy of the Flags register so that we can perform ALU operations without affecting the original content of the Flags register
rFlagsInBuffer : Register8Bit port map(load_FlagsFromDataBus, select_FlagsToFlagsBus, in_FlagsFromDataBus, out_FlagsToFlagsBus); -- Buffers the flags when read from the data bus (needed for the POPF operation)
rFlagsOutBuffer : Register8Bit port map(load_FlagsFromFlagsBus, select_FlagsToDataBus, in_FlagsFromFlagsBus, out_FlagsToDataBus); -- Buffers the flags when written to the data bus (needed for the PUSHF operation)
-- This is our ALU
-- The ALU receives the input from Register A and Register B.
-- The output is written to Register C for further processing.
-- state_Flags(2)
alu: ALU8Bit port map(out_A_To_ALU, out_B_To_ALU, out_INSTR_To_ALU(3 downto 0), state_Flags(2), out_ALU, in_Flags_From_ALU(0), in_Flags_From_ALU(1), in_Flags_From_ALU(2), in_Flags_From_ALU(3));
FlagsTemp(0) <= in_Flags_From_ALU(0);
FlagsTemp(1) <= in_Flags_From_ALU(1);
FlagsTemp(2) <= in_Flags_From_ALU(2);
FlagsTemp(3) <= in_Flags_From_ALU(3);
-- Writes the flags onto the Flags Bus
FlagsBus <= FlagsTemp or
out_Flags or
out_FlagsSaved_To_FlagsBus or
out_FlagsToFlagsBus;
-- Writes the content from the Flags Bus into the Flags register
in_Flags <= FlagsBus;
-- Writes the content from the Flags Bus into the FlagsSaved register
in_FlagsSaved_From_FlagsBus <= FlagsBus;
in_FlagsFromFlagsBus <= FlagsBus;
-- =======================================================================
-- The following section contains the wiring of the individual registers
-- with the Address and Data Bus
-- =======================================================================
-- Connects the Address Bus to the Program Counter register
in_PC <= AddressBus or PC;
-- Connects the 16-bit wide registers to the Address Bus
in_M_From_AddressBus <= AddressBus;
in_X_From_AddressBus <= AddressBus;
in_J_From_AddressBus <= AddressBus;
in_SP_From_AddressBus <= AddressBus;
in_BP_From_AddressBus <= AddressBus;
in_Y_From_AddressBus <= AddressBus;
in_Z_From_AddressBus <= AddressBus;
in_Adder16Bit_InputA_From_AddressBus <= AddressBus;
in_Adder16Bit_InputB_From_AddressBus <= AddressBus;
-- Connects the Program Counter register, the Increment register, and the 16-bit registers to the Address Bus
AddressBus <= out_PC or
out_INC or
out_M_To_AddressBus or
out_X_To_AddressBus or
out_J_To_AddressBus or
out_SP_To_AddressBus or
out_BP_To_AddressBus or
out_Y_To_AddressBus or
out_Z_To_AddressBus or
Output_RegisterAdder16Bit;
-- Connects the general purpose registers and the instruction
-- register to the data bus
in_A_From_DataBus <= DataBus;
in_B_From_DataBus <= DataBus;
in_C_From_DataBus <= DataBus;
in_D_From_DataBus <= DataBus;
in_E_From_DataBus <= DataBus;
in_F_From_DataBus <= DataBus;
in_G_From_DataBus <= DataBus;
in_H_From_DataBus <= DataBus;
in_InternalA_From_DataBus <= DataBus;
in_INSTR <= DataBus;
in_XL_From_DataBus <= DataBus;
in_XH_From_DataBus <= DataBus;
in_FlagsFromDataBus <= DataBus;
in_PortC_FromDataBus <= DataBus;
in_PortD_FromDataBus <= DataBus;
-- Just store the first 4 bits from the Register D.
-- This eliminates the 4 bits from SETAB opcode and the destination register (A or B)
Truncated_InternalA <= out_InternalA and "00001111";
-- Connects the data bus to the general purpose registers, and the
-- SRAM memory output.
-- !!!!IT'S VERY IMPORTANT THAT ONLY *ONE* REGISTER CONCURRENTLY WRITES
-- TO THE DATA BUS!!!!
DataBus <= out_A_To_DataBus or
out_B_To_DataBus or
out_C_To_DataBus or
out_INSTR_To_DataBus or
outputRAM or
Truncated_InternalA or
out_ALU or
out_D_To_DataBus or
out_E_To_DataBus or
out_F_To_DataBus or
out_G_To_DataBus or
out_H_To_DataBus or
out_XL_To_DataBus or
out_XH_To_DataBus or
out_FlagsToDataBus or
out_PortA_To_DataBus or
out_PortB_To_DataBus;
-- =======================================================================
-- The following section contains a few additional connections
-- that are needed to connect the TestBench to the CPU itself.
-- These are the Control Lines that also accept inputs from the TestBench.
-- They just take their input from the Instruction Decoder and ORed with the
-- input from the TestBench.
-- ========================================================================
loadRAM <= load_SRAM or Load_RAM;
inputRAM <= Input_RAM or DataBus;
l_PC <= load_PC1 or Load_PC;
selectRAM <= select_SRAM or Select_RAM;
-- Just provide from the CPU an output value, so that the implementation on the FPGA works
Instruction <= currentInstruction;
end Behavioral;
|
mit
|
rodrigoazs/-7-5-Reed-Solomon
|
code/reedsomolon_decoder.vhd
|
1
|
1889
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Author: R. Azevedo Santos ([email protected])
-- Co-Author: Joao Lucas Magalini Zago
--
-- VHDL Implementation of (7,5) Reed Solomon
-- Course: Information Theory - 2014 - Ohio Northern University
entity ReedSolomonDecoder is
Port ( Clock : in std_logic;
Count7 : in std_logic;
Qs0: in std_logic_vector(2 downto 0);
Dsyn1: out std_logic_vector(2 downto 0);
Dsyn2: out std_logic_vector(2 downto 0));
end ReedSolomonDecoder;
architecture Behavioral of ReedSolomonDecoder is
component flipflop is
Port ( D: in std_logic_vector(2 downto 0);
Clock : in std_logic;
Reset : in std_logic;
Q : out std_logic_vector(2 downto 0));
end component;
component AdderXor is
Port ( a: in std_logic_vector(2 downto 0);
b: in std_logic_vector(2 downto 0);
c: out std_logic_vector(2 downto 0)) ;
end component;
component Mult is
port(uncoded_a, uncoded_b:
in std_logic_vector(2 downto 0);
uncoded_multab: out std_logic_vector(2 downto 0));
end component;
signal alpha3 : std_logic_vector(2 downto 0);
signal alpha4 : std_logic_vector(2 downto 0);
signal D1 : std_logic_vector(2 downto 0);
signal D2 : std_logic_vector(2 downto 0);
signal Q1 : std_logic_vector(2 downto 0);
signal Q2 : std_logic_vector(2 downto 0);
signal C0 : std_logic_vector(2 downto 0);
signal multa1 : std_logic_vector(2 downto 0);
signal multa2 : std_logic_vector(2 downto 0);
begin
alpha3(0) <= '0'; alpha3(1) <= '1'; alpha3(2) <= '1';
alpha4(0) <= '1'; alpha4(1) <= '1'; alpha4(2) <= '0';
add1 : AdderXor port map (multa1, Qs0, C0);
D1 <= C0;
ff1 : flipflop port map (D1,Clock,Count7,Q1);
add2 : AdderXor port map(Q1, multa2, D2);
ff2 : flipflop port map (D2,Clock,Count7,Q2);
mult1 : Mult port map (Q2, alpha3, multa1);
mult2 : Mult port map (Q2, alpha4, multa2);
Dsyn1 <= D1;
Dsyn2 <= D2;
end Behavioral;
|
mit
|
laurivosandi/hdl
|
zynq/src/ov7670_controller/i2c_sender.vhd
|
1
|
5111
|
----------------------------------------------------------------------------------
-- Engineer: <[email protected]
--
-- Description: Send the commands to the OV7670 over an I2C-like interface
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity i2c_sender is
port (
clk : in std_logic;
siod : inout std_logic;
sioc : out std_logic;
taken : out std_logic;
send : in std_logic;
id : in std_logic_vector(7 downto 0);
reg : in std_logic_vector(7 downto 0);
value : in std_logic_vector(7 downto 0)
);
end i2c_sender;
architecture behavioral of i2c_sender is
-- this value gives a 254 cycle pause before the initial frame is sent
signal divider : unsigned (7 downto 0) := "00000001";
signal busy_sr : std_logic_vector(31 downto 0) := (others => '0');
signal data_sr : std_logic_vector(31 downto 0) := (others => '1');
begin
process(busy_sr, data_sr(31))
begin
if busy_sr(11 downto 10) = "10" or
busy_sr(20 downto 19) = "10" or
busy_sr(29 downto 28) = "10" then
siod <= 'Z';
else
siod <= data_sr(31);
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
taken <= '0';
if busy_sr(31) = '0' then
SIOC <= '1';
if send = '1' then
if divider = "00000000" then
data_sr <= "100" & id & '0' & reg & '0' & value & '0' & "01";
busy_sr <= "111" & "111111111" & "111111111" & "111111111" & "11";
taken <= '1';
else
divider <= divider+1; -- this only happens on powerup
end if;
end if;
else
case busy_sr(32-1 downto 32-3) & busy_sr(2 downto 0) is
when "111"&"111" => -- start seq #1
case divider(7 downto 6) is
when "00" => SIOC <= '1';
when "01" => SIOC <= '1';
when "10" => SIOC <= '1';
when others => SIOC <= '1';
end case;
when "111"&"110" => -- start seq #2
case divider(7 downto 6) is
when "00" => SIOC <= '1';
when "01" => SIOC <= '1';
when "10" => SIOC <= '1';
when others => SIOC <= '1';
end case;
when "111"&"100" => -- start seq #3
case divider(7 downto 6) is
when "00" => SIOC <= '0';
when "01" => SIOC <= '0';
when "10" => SIOC <= '0';
when others => SIOC <= '0';
end case;
when "110"&"000" => -- end seq #1
case divider(7 downto 6) is
when "00" => SIOC <= '0';
when "01" => SIOC <= '1';
when "10" => SIOC <= '1';
when others => SIOC <= '1';
end case;
when "100"&"000" => -- end seq #2
case divider(7 downto 6) is
when "00" => SIOC <= '1';
when "01" => SIOC <= '1';
when "10" => SIOC <= '1';
when others => SIOC <= '1';
end case;
when "000"&"000" => -- Idle
case divider(7 downto 6) is
when "00" => SIOC <= '1';
when "01" => SIOC <= '1';
when "10" => SIOC <= '1';
when others => SIOC <= '1';
end case;
when others =>
case divider(7 downto 6) is
when "00" => SIOC <= '0';
when "01" => SIOC <= '1';
when "10" => SIOC <= '1';
when others => SIOC <= '0';
end case;
end case;
if divider = "11111111" then
busy_sr <= busy_sr(32-2 downto 0) & '0';
data_sr <= data_sr(32-2 downto 0) & '1';
divider <= (others => '0');
else
divider <= divider+1;
end if;
end if;
end if;
end process;
end behavioral;
|
mit
|
laurivosandi/hdl
|
arithmetic/src/reciprocal.vhd
|
1
|
1471
|
library ieee;
use ieee.std_logic_1164.all;
entity reciprocal is
port (
b : in std_logic_vector (15 downto 0);
r : out std_logic_vector (15 downto 0)
);
end reciprocal;
architecture behavioral of reciprocal is
begin
-- Note that this is not the most compact solution,
-- but it leaves room for experimentation.
r <= "1100000000000000" when b = "0000000000000000" else
"0110000000000000" when b(15 downto 1) = "000000000000000" else
"0011000000000000" when b(15 downto 2) = "00000000000000" else
"0001100000000000" when b(15 downto 3) = "0000000000000" else
"0000110000000000" when b(15 downto 4) = "000000000000" else
"0000011000000000" when b(15 downto 5) = "00000000000" else
"0000001100000000" when b(15 downto 6) = "0000000000" else
"0000000110000000" when b(15 downto 7) = "000000000" else
"0000000011000000" when b(15 downto 8) = "00000000" else
"0000000001100000" when b(15 downto 9) = "0000000" else
"0000000000110000" when b(15 downto 10) = "000000" else
"0000000000011000" when b(15 downto 11) = "00000" else
"0000000000001100" when b(15 downto 12) = "0000" else
"0000000000000110" when b(15 downto 13) = "000" else
"0000000000000011" when b(15 downto 14) = "00" else
"0000000000000001" when b(15) = '0' else
"0000000000000000";
end behavioral;
|
mit
|
rodrigoazs/-7-5-Reed-Solomon
|
code/read_file.vhd
|
1
|
1412
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-- Author: R. Azevedo Santos ([email protected])
-- Co-Author: Joao Lucas Magalini Zago
--
-- VHDL Implementation of (7,5) Reed Solomon
-- Course: Information Theory - 2014 - Ohio Northern University
entity read_file is
Port (Clock: in std_logic;
Qout: out std_logic_vector(2 downto 0)
);
end read_file;
architecture Behavioral of read_file is
signal bin_value : std_logic_vector(2 downto 0):="000";
begin
process
file file_pointer : text;
variable line_content : string(1 to 15);
variable line_num : line;
variable j, i : integer := 0;
variable char : character:='0';
begin
file_open(file_pointer,"read.txt",READ_MODE);
bin_value <= "UUU";
wait for 1 ps;
while not endfile(file_pointer) loop
readline (file_pointer,line_num);
READ (line_num,line_content);
for j in 1 to 15 loop
i := i + 1;
char := line_content(16-j);
if(char = '0') then
bin_value(i-1) <= '0';
else
bin_value(i-1) <= '1';
end if;
if (i = 3) then
i := 0;
wait for 2 ps;
end if;
end loop;
bin_value <= "UUU";
wait for 4 ps;
end loop;
file_close(file_pointer);
wait;
end process;
Qout <= bin_value;
end Behavioral;
|
mit
|
andrecp/myhdl_simple_uart
|
generated_files/serial_rx.vhd
|
1
|
3727
|
-- File: serial_rx.vhd
-- Generated by MyHDL 0.8
-- Date: Thu Aug 21 10:54:44 2014
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity serial_rx is
port (
sysclk: in std_logic;
reset_n: in std_logic;
half_baud_rate_tick_i: in std_logic;
baud_rate_tick_i: in std_logic;
recieve_i: in std_logic;
data_o: out unsigned(7 downto 0);
ready_o: out std_logic
);
end entity serial_rx;
-- Serial
-- This module implements a reciever serial interface
--
-- Ports:
-- -----
-- sysclk: sysclk input
-- reset_n: reset input
-- half_baud_rate_tick_i: half baud rate tick
-- baud_rate_tick_i: the baud rate
-- n_stop_bits_i: number of stop bits
-- recieve_i: rx
-- data_o: the data output in 1 byte
-- ready_o: indicates data_o is valid
-- -----
architecture MyHDL of serial_rx is
constant n_stop_bits_i: integer := 2;
constant END_OF_BYTE: integer := 7;
type t_enum_t_State_1 is (
ST_WAIT_START_BIT,
ST_GET_DATA_BITS,
ST_GET_STOP_BITS
);
signal data_reg: unsigned(7 downto 0);
signal count_8_bits_reg: unsigned(2 downto 0);
signal data: unsigned(7 downto 0);
signal count_8_bits: unsigned(2 downto 0);
signal ready: std_logic;
signal state: t_enum_t_State_1;
signal count_stop_bits_reg: unsigned(2 downto 0);
signal count_stop_bits: unsigned(2 downto 0);
signal state_reg: t_enum_t_State_1;
signal ready_reg: std_logic;
begin
data_o <= data_reg;
ready_o <= ready_reg;
SERIAL_RX_SEQUENTIAL_PROCESS: process (sysclk, reset_n) is
begin
if (reset_n = '0') then
count_8_bits_reg <= to_unsigned(0, 3);
count_stop_bits_reg <= to_unsigned(0, 3);
ready_reg <= '0';
state_reg <= ST_WAIT_START_BIT;
data_reg <= to_unsigned(0, 8);
elsif rising_edge(sysclk) then
state_reg <= state;
data_reg <= data;
ready_reg <= ready;
count_8_bits_reg <= count_8_bits;
count_stop_bits_reg <= count_stop_bits;
end if;
end process SERIAL_RX_SEQUENTIAL_PROCESS;
SERIAL_RX_COMBINATIONAL_PROCESS: process (count_8_bits_reg, recieve_i, data_reg, baud_rate_tick_i, count_stop_bits_reg, state_reg, ready_reg) is
begin
state <= state_reg;
data <= data_reg;
ready <= ready_reg;
count_8_bits <= count_8_bits_reg;
count_stop_bits <= count_stop_bits_reg;
case state_reg is
when ST_WAIT_START_BIT =>
ready <= '0';
if (baud_rate_tick_i = '1') then
if (recieve_i = '0') then
state <= ST_GET_DATA_BITS;
end if;
end if;
when ST_GET_DATA_BITS =>
if (baud_rate_tick_i = '1') then
data(to_integer(count_8_bits_reg)) <= recieve_i;
if (count_8_bits_reg = END_OF_BYTE) then
count_8_bits <= to_unsigned(0, 3);
state <= ST_GET_STOP_BITS;
else
count_8_bits <= (count_8_bits_reg + 1);
state <= ST_GET_DATA_BITS;
end if;
end if;
when ST_GET_STOP_BITS =>
if (baud_rate_tick_i = '1') then
if (signed(resize(count_stop_bits_reg, 4)) = (n_stop_bits_i - 1)) then
count_stop_bits <= to_unsigned(0, 3);
ready <= '1';
state <= ST_WAIT_START_BIT;
else
count_stop_bits <= (count_stop_bits_reg + 1);
end if;
end if;
when others =>
assert False report "End of Simulation" severity Failure;
end case;
end process SERIAL_RX_COMBINATIONAL_PROCESS;
end architecture MyHDL;
|
mit
|
andrecp/myhdl_simple_uart
|
generated_files/serial_tx.vhd
|
1
|
3557
|
-- File: serial_tx.vhd
-- Generated by MyHDL 0.8
-- Date: Thu Aug 21 10:54:44 2014
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_08.all;
entity serial_tx is
port (
sysclk: in std_logic;
reset_n: in std_logic;
start_i: in std_logic;
data_i: in unsigned(7 downto 0);
baud_rate_tick_i: in std_logic;
transmit_o: out std_logic
);
end entity serial_tx;
-- Serial
-- This module implements a transmitter serial interface
--
-- Ports:
-- -----
-- sysclk: sysclk input
-- reset_n: reset input
-- baud_rate_tick_i: the baud rate
-- start_i: start sending data
-- data_i: the data to send
-- n_stop_bits_i: number of stop bits
-- transmit_o: data output
-- -----
architecture MyHDL of serial_tx is
constant n_stop_bits_i: integer := 2;
constant END_OF_BYTE: integer := 7;
type t_enum_t_State_1 is (
ST_WAIT_START,
ST_SEND_START_BIT,
ST_SEND_DATA,
ST_SEND_STOP_BIT
);
signal transmit_reg: std_logic;
signal count_8_bits: unsigned(2 downto 0);
signal count_8_bits_reg: unsigned(2 downto 0);
signal state: t_enum_t_State_1;
signal transmit: std_logic;
signal count_stop_bits_reg: unsigned(2 downto 0);
signal count_stop_bits: unsigned(2 downto 0);
signal state_reg: t_enum_t_State_1;
begin
transmit_o <= transmit_reg;
SERIAL_TX_SEQUENTIAL_PROCESS: process (sysclk, reset_n) is
begin
if (reset_n = '0') then
count_8_bits_reg <= to_unsigned(0, 3);
count_stop_bits_reg <= to_unsigned(0, 3);
transmit_reg <= '0';
state_reg <= ST_WAIT_START;
elsif rising_edge(sysclk) then
state_reg <= state;
transmit_reg <= transmit;
count_8_bits_reg <= count_8_bits;
count_stop_bits_reg <= count_stop_bits;
end if;
end process SERIAL_TX_SEQUENTIAL_PROCESS;
SERIAL_TX_COMBINATIONAL_PROCESS: process (transmit_reg, start_i, count_8_bits_reg, data_i, baud_rate_tick_i, count_stop_bits_reg, state_reg) is
begin
state <= state_reg;
transmit <= transmit_reg;
count_8_bits <= count_8_bits_reg;
count_stop_bits <= count_stop_bits_reg;
case state_reg is
when ST_WAIT_START =>
transmit <= '1';
if (start_i = '1') then
state <= ST_SEND_START_BIT;
end if;
when ST_SEND_START_BIT =>
transmit <= '0';
if (baud_rate_tick_i = '1') then
state <= ST_SEND_DATA;
end if;
when ST_SEND_DATA =>
transmit <= data_i(to_integer(count_8_bits_reg));
if (baud_rate_tick_i = '1') then
if (count_8_bits_reg = END_OF_BYTE) then
count_8_bits <= to_unsigned(0, 3);
state <= ST_SEND_STOP_BIT;
else
count_8_bits <= (count_8_bits_reg + 1);
state <= ST_SEND_DATA;
end if;
end if;
when ST_SEND_STOP_BIT =>
transmit <= '1';
if (baud_rate_tick_i = '1') then
if (signed(resize(count_stop_bits_reg, 4)) = (n_stop_bits_i - 1)) then
count_stop_bits <= to_unsigned(0, 3);
state <= ST_WAIT_START;
else
count_stop_bits <= (count_stop_bits_reg + 1);
end if;
end if;
when others =>
assert False report "End of Simulation" severity Failure;
end case;
end process SERIAL_TX_COMBINATIONAL_PROCESS;
end architecture MyHDL;
|
mit
|
christop/linguist
|
samples/VHDL/foo.vhd
|
91
|
217
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
mit
|
laurivosandi/hdl
|
arithmetic/src/carry_lookahead_adder.vhd
|
1
|
1002
|
library ieee;
use ieee.std_logic_1164.all;
-- 15-bit carry look-ahead adder
entity carry_lookahead_adder is
port (
a : in std_logic_vector (14 downto 0);
b : in std_logic_vector (14 downto 0);
ci : in std_logic;
s : out std_logic_vector (14 downto 0);
co : out std_logic
);
end carry_lookahead_adder;
architecture behavioral of carry_lookahead_adder is
signal t : std_logic_vector(14 DOWNTO 0);
signal g : std_logic_vector(14 DOWNTO 0);
signal p : std_logic_vector(14 DOWNTO 0);
signal c : std_logic_vector(14 DOWNTO 1);
begin
-- Product stage
g <= a and b;
p <= a or b;
-- Sum stage
t <= a xor b;
-- Carry stage
c(1) <= g(0) or (p(0) and ci);
carry_loop: for i in 1 to 13 generate
c(i+1) <= g(i) or (p(i) and c(i));
end generate;
co <= g(14) or (p(14) and c(14));
s(0) <= t(0) xor ci;
s(14 downto 1) <= t(14 downto 1) xor c(14 downto 1);
end behavioral;
|
mit
|
vhdlnerd/classicHp
|
src/classic_pack.vhd
|
1
|
4130
|
----------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2014 Brian K. Nemetz
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
----------------------------------------------------------------------------------
--
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library ieee; use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ps2_keyboard_pack.all;
use work.rom_pack.all;
package classic_pack is
constant WSIZE : natural := 14; -- Arithmetic register size
constant SSIZE : natural := 12; -- Status word size
subtype bcdDigitType is unsigned(3 downto 0);
type arthRegType is array (natural range 0 to WSIZE-1) of bcdDigitType;
type ramType is array (natural range <>) of arthRegType; -- for models with RAM
constant BCD_DIGIT_ZERO : bcdDigitType := (others => '0');
constant REG_ZEROS : arthRegType := (others => BCD_DIGIT_ZERO);
function vecLen(n : natural) return natural;
--
-- Declare functions and procedure
--
function IIF (signal test : boolean; signal a : std_logic; signal b : std_logic) return std_logic;
function IIF (constant test : boolean; constant a : std_logic_vector; constant b : std_logic_vector) return std_logic_vector;
function IIF (constant test : boolean; constant a : keyLutType; constant b : keyLutType) return keyLutType;
function IIF (constant test : boolean; constant a : RomType; constant b : RomType) return RomType;
end classic_pack;
package body classic_pack is
--
-- Compute the length of a bit vector that can count up to 'n'
-- If you need a counter to count from 0 to 203, you can pass
-- 203 to this function and it will return 8 (i.e. an 8 bit
-- counter is required). 255 will return 8, also and 256 will
-- return 9.
--
function vecLen(n : natural) return natural is
variable t : unsigned(31 downto 0) := to_unsigned(n,32);
begin
for i in t'range loop
if t(i) = '1' then
return i+1;
end if;
end loop;
return 0;
end function vecLen;
function IIF (signal test : boolean; signal a : std_logic; signal b : std_logic) return std_logic is
begin
if test then return a; else return b; end if;
end function IIF;
function IIF (constant test : boolean; constant a : std_logic_vector; constant b : std_logic_vector) return std_logic_vector is
begin
if test then return a; else return b; end if;
end function IIF;
function IIF (constant test : boolean; constant a : keyLutType; constant b : keyLutType) return keyLutType is
begin
if test then return a; else return b; end if;
end function IIF;
function IIF (constant test : boolean; constant a : RomType; constant b : RomType) return RomType is
begin
if test then return a; else return b; end if;
end function IIF;
end classic_pack;
|
mit
|
PalmNote/PalmNote
|
www/lib/ngCordova/demo/www/lib/ace-builds/demo/kitchen-sink/docs/vhdl.vhd
|
472
|
830
|
library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
|
mit
|
vhdlnerd/classicHp
|
src/top_tb.vhd
|
1
|
6708
|
----------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2014 Brian K. Nemetz
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Company:
-- Engineer: Brian Nemetz
--
-- Create Date: 10:56:50 10/16/2012
-- Design Name:
-- Module Name: top_tb.vhd
-- Project Name: classicHp
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: classic
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
--
-- WARNING: I have not used htis test bench in a long time. I'm not sure if its
-- working any longer. BKN 4/1/2014
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY top_tb IS
END top_tb;
ARCHITECTURE behavior OF top_tb IS
-- -- Component Declaration for the Unit Under Test (UUT)
--
-- COMPONENT classic
-- PORT(
-- clk_i : IN std_logic;
-- rst_i : IN std_logic;
-- keycode_i : IN std_logic_vector(7 downto 0);
-- keyvalid_i : IN std_logic;
-- error_o : OUT std_logic;
-- xreg_o : OUT std_logic_vector(55 downto 0);
-- mask_o : OUT std_logic_vector(55 downto 0);
-- update_o : OUT std_logic
-- );
-- END COMPONENT;
--Inputs
signal clk_i : std_logic := '0';
signal rst_i : std_logic := '0';
signal keycode_i : std_logic_vector(7 downto 0) := (others => '0');
signal keyvalid_i : std_logic := '0';
--Outputs
signal error_o : std_logic;
signal xreg_o : std_logic_vector(55 downto 0);
signal mask_o : std_logic_vector(55 downto 0);
signal update_o : std_logic;
signal display : string(1 to 15);
-- Clock period definitions
constant clk_i_period : time := 5 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: entity work.classic(rtl)
PORT MAP (
clk_i => clk_i,
rst_i => rst_i,
keycode_i => keycode_i,
keyvalid_i => keyvalid_i,
error_o => error_o,
xreg_o => xreg_o,
mask_o => mask_o,
update_o => update_o
);
-- Clock process definitions
clk_i_process :process
begin
clk_i <= '0';
wait for clk_i_period/2;
clk_i <= '1';
wait for clk_i_period/2;
end process;
dis_proc : process(clk_i)
function bcd2char(bcd : std_logic_vector(3 downto 0)) return character is
begin
case bcd is
when "0000" => return '0';
when "0001" => return '1';
when "0010" => return '2';
when "0011" => return '3';
when "0100" => return '4';
when "0101" => return '5';
when "0110" => return '6';
when "0111" => return '7';
when "1000" => return '8';
when "1001" => return '9';
when others => return '?';
end case;
end function bcd2char;
variable bcd : std_logic_vector(3 downto 0);
variable mask : std_logic_vector(3 downto 0);
variable n : natural;
variable flag : boolean;
begin
if rising_edge(clk_i) then
n := 15;
flag := false;
for i in 0 to 13 loop
bcd := xreg_o((i+1)*4-1 downto i*4);
mask := mask_o((i+1)*4-1 downto i*4);
if mask = "1001" then
display(n) <= ' ';
n := n - 1;
else
if mask = "0000" and (i=2 or i=13) then
if bcd = "1001" then
display(n) <= '-';
else
display(n) <= ' ';
end if;
n := n - 1;
elsif mask = "0000" then
display(n) <= bcd2char(bcd);
n := n - 1;
else
if flag = false then
display(n) <= '.';
n := n - 1;
end if;
flag := true;
display(n) <= bcd2char(bcd);
n := n - 1;
end if;
end if;
end loop;
end if;
end process dis_proc;
-- Stimulus process
stim_proc: process
begin
keycode_i <= X"00";
keyvalid_i <= '0';
-- hold reset state for 100 ns.
rst_i <= '1';
wait for 30 ns;
rst_i <= '0';
-- wait for clk_i_period*10;
wait for 2 us;
keycode_i <= X"13"; -- 5
wait until rising_edge(clk_i);
keyvalid_i <= '1';
wait until rising_edge(clk_i);
keyvalid_i <= '0';
wait for 4 us;
keycode_i <= "00" & O"76"; -- enter
wait until rising_edge(clk_i);
keyvalid_i <= '1';
wait until rising_edge(clk_i);
keyvalid_i <= '0';
wait for 4 us;
keycode_i <= X"12"; -- 6
wait until rising_edge(clk_i);
keyvalid_i <= '1';
wait until rising_edge(clk_i);
keyvalid_i <= '0';
wait for 4 us;
keycode_i <= "00" & O"26"; -- +
wait until rising_edge(clk_i);
keyvalid_i <= '1';
wait until rising_edge(clk_i);
keyvalid_i <= '0';
-- insert stimulus here
wait;
end process;
END;
|
mit
|
vhdlnerd/classicHp
|
src/classicHp_top.vhd
|
1
|
31092
|
----------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2014 Brian K. Nemetz
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in all
-- copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-- SOFTWARE.
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Brian Nemetz
--
-- Create Date: 08:18:42 10/26/2012
-- Design Name:
-- Module Name: classicHp_top - rtl
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.classic_pack.all;
use work.ps2_keyboard_pack.all;
use work.rom_pack.all;
use work.tm16xxFonts.all;
entity classichp_top is
generic (
UART_TYPE : string := "TX_RX"; -- Should be: "NONE", "TX", "RX", or "TX_RX"
CALC_NAME : string := "HP55" -- Should be: "HP55", "HP45", or "HP35"
);
port ( clk_i : in std_logic;
rst_i : in std_logic;
ps2_clk_i : in std_logic;
ps2_data_i : in std_logic;
uart_rx_i : in std_logic;
dis_clk_o : out std_logic;
dis_data_o : out std_logic;
uart_tx_o : out std_logic;
leds_o : out std_logic_vector (3 downto 0)
);
end classichp_top;
architecture rtl of classichp_top is
-- Configure for the calculator desired:
constant HP35 : boolean := CALC_NAME="HP35";
constant HP45 : boolean := CALC_NAME="HP45";
constant HP55 : boolean := CALC_NAME="HP55";
constant CALC_ROM : RomType := IIF(HP55, ROM_55, IIF(HP45, ROM_45, ROM_35));
constant KEY_LUT : keyLutType := IIF(HP55, KEY_LUT_HP55, IIF(HP45, KEY_LUT_HP45, KEY_LUT_HP35));
-- Configure for UART type desired:
constant UART_TX : boolean := UART_TYPE="TX" or UART_TYPE="TX_RX";
constant UART_RX : boolean := UART_TYPE="RX" or UART_TYPE="TX_RX";
-- constant CLK_FREQ : natural := 7000000; -- sysClk Rate
constant CLK_FREQ : natural := 84000000; -- sysClk Rate
constant CLK_EN_CNT : natural := CLK_FREQ/1000000; -- CLK_EN_CNT is how many sysClk periods in 1us
-- definition for "HP-x5" where x is 3, 4, or 5 (padded out to 14 chars)
constant LED_SIGNON : ledFontRomType := (
LED_SPACE,
LED_MINUS,
LED_MINUS,
LED_SPACE,
LED_H, -- 'H'
LED_P, -- 'P'
LED_DASH, -- '-'
IIF(HP55, LED_5, IIF(HP45, LED_4, LED_3)), -- '3', '4', or '5'
LED_5, -- '5'
LED_SPACE,
LED_MINUS,
LED_MINUS,
LED_SPACE,
LED_SPACE
);
type ledFsmType is (IDLE, START, SEND1, SEND2, SEND3, END1, END2, END3, END4);
type disLedFsmType is (CMD1, CMD2, CMD2W, T0, T1, DIS_CMD1, DIS_CMD2, DIS_EX1,
DIS_EX2, ERROR_D, SIGNON_D, SIGNON_W);
subtype clkEnCntType is natural range 0 to CLK_EN_CNT-1;
type byteArrayType is array (natural range <>) of std_logic_vector(7 downto 0);
subtype idxCntType is natural range 0 to 13;
subtype ledCntType is natural range 0 to 7;
constant DELAY_100MS : natural := 100000
-- synthesis translate_off
- 99996
-- synthesis translate_on
;
constant DELAY_10MS : natural := 10000
-- synthesis translate_off
- 9996
-- synthesis translate_on
;
constant DELAY_5MS : natural := 5000
-- synthesis translate_off
- 4996
-- synthesis translate_on
;
constant DELAY_200US : natural := 200
-- synthesis translate_off
- 198
-- synthesis translate_on
;
constant DELAY_10US : natural := 10
-- synthesis translate_off
- 8
-- synthesis translate_on
;
-- delay for creating real timing of the original HP-55 => 3500 instructions per sec
-- ex: if sysClk is 7MHz: 7Mhz/3500 = 2000
constant DELAY_INST : natural := CLK_FREQ/3500
-- synthesis translate_off
- (CLK_FREQ/3500 - 10)
-- synthesis translate_on
;
subtype delayCntType is natural range 0 to DELAY_5MS-1;
subtype keyCntType is natural range 0 to DELAY_10MS-1;
subtype pCntType is natural range 0 to DELAY_100MS-1;
subtype instCntType is natural range 0 to DELAY_INST-1;
signal sysRst : std_logic;
signal sysRstLow : std_logic;
signal sysClk : std_logic;
signal error : std_logic;
signal status : std_logic_vector(11 downto 0);
signal flagsR : std_logic_vector(11 downto 0);
signal xreg : std_logic_vector(55 downto 0);
signal mask : std_logic_vector(55 downto 0);
signal clkEnR : std_logic;
signal clkEnCntR : clkEnCntType;
signal ledFsmR : ledFsmType;
signal ledSendR : std_logic;
signal ledStartR : std_logic;
signal ledEndR : std_logic;
signal ledDoneR : std_logic;
signal ledClkR : std_logic;
signal ledDataR : std_logic;
signal ledSendDataR : std_logic_vector(7 downto 0);
signal ledBrightR : unsigned(2 downto 0);
signal ledCntR : ledCntType;
signal xregLedR : std_logic_vector(55 downto 0);
signal maskLedR : std_logic_vector(55 downto 0);
signal ps2ClkR : std_logic;
signal ps2ClkRR : std_logic;
signal ps2ClkRRR : std_logic;
signal keyRdyR : std_logic;
signal keyRdyLongR : std_logic;
signal keyRdy : std_logic;
signal keyData : std_logic_vector(7 downto 0);
signal keyDataR : std_logic_vector(7 downto 0);
signal uartKeyRdyR : std_logic;
signal uartKeyDataR : std_logic_vector(7 downto 0);
signal ps2KeyRdy : std_logic;
signal ps2KeyData : std_logic_vector(7 downto 0);
signal disLedFsmR : disLedFsmType;
signal indexLedR : idxCntType;
signal ledFirstR : std_logic;
signal ledExDigit1R : std_logic_vector(7 downto 0);
signal ledExDigit2R : std_logic_vector(7 downto 0);
signal keyCntR : keyCntType;
signal instCntR : instCntType;
signal instEnR : std_logic;
signal realSpeedEnR : std_logic;
signal displayEn : std_logic;
begin
-- test outputs
leds_o(0) <= uart_rx_i;
leds_o(1) <= '0';
leds_o(2) <= clkEnR;
leds_o(3) <= '0';
-- Xilinx DCM primitive is within this component.
-- This is one thing that has to change if targetting a different FPGA.
dcm : entity work.sys_dcm(behavioral)
port map (
CLKIN_IN => clk_i,
RST_IN => rst_i,
CLKFX_OUT => sysClk,
CLKIN_IBUFG_OUT => open,
CLK0_OUT => open,
LOCKED_OUT => sysRstLow
);
sysRst <= not sysRstLow;
hpCore: entity work.classic(rtl)
generic map (
CALC_NAME => CALC_NAME,
ROM => CALC_ROM
)
PORT MAP (
clk_i => sysClk,
rst_i => sysRst,
inst_en_i => instEnR,
flags_i => flagsR,
keycode_i => keyDataR,
keyvalid_i => keyRdyLongR,
display_en_o => displayEn,
error_o => error,
xreg_o => xreg,
mask_o => mask,
status_o => status
);
-- This is the PS/2 interface and will return calculator keycodes (plus a few
-- special codes).
ps2 : entity work.ps2_keyboard(rtl)
generic map (KEY_LUT => KEY_LUT)
port map(
rst_i => sysRst,
clk_i => sysClk, -- needs to be faster than ps2_clk_i
ps2_data_i => ps2_data_i,
ps2_clk_i => ps2_clk_i,
key_rdy_o => ps2KeyRdy, -- one clock cycle pulse, notify a new byte has arrived
key_data_o => ps2KeyData
);
-- choose between UART and PS/2 keyboard input
keyRdy <= ps2KeyRdy or uartKeyRdyR;
keyData <= ps2KeyData when ps2KeyRdy='1' else uartKeyDataR;
-- Create a clock enable pulse every 1us. This is for general timing of
-- slower things.
clk_en : process (sysClk, sysRst)
begin
if sysRst = '1' then
clkEnCntR <= 0;
clkEnR <= '0';
elsif rising_edge(sysClk) then
if clkEnCntR = CLK_EN_CNT-1 then
clkEnR <= '1';
clkEnCntR <= 0;
else
clkEnR <= '0';
clkEnCntR <= clkEnCntR+1;
end if;
end if;
end process clk_en;
-- Create an enable pulse every micro-instruction execution time.
-- For slowing down the core to the same speed as the original HP-55.
inst_en : process (sysClk, sysRst)
begin
if sysRst = '1' then
instCntR <= 0;
instEnR <= '1';
elsif rising_edge(sysClk) then
if realSpeedEnR /= '1' or instCntR = instCntType'high then
instEnR <= '1';
instCntR <= 0;
else
instEnR <= '0';
instCntR <= instCntR+1;
end if;
end if;
end process inst_en;
-- We need to create a stretched key ready signal for the core on each new
-- keyboard input. This is needed since the calculator micro-code is still
-- doing key debouncing. We hold each key active for 10ms -- this should be
-- long enough for the core to "see" the key press (in real or turbo speed
-- mode).
key_stretch : process (sysClk, sysRst)
begin
if sysRst = '1' then
keyCntR <= 0;
keyRdyLongR <= '0';
elsif rising_edge(sysClk) then
if keyRdyLongR = '0' and keyRdyR = '1' then
keyRdyLongR <= '1';
keyCntR <= 0;
end if;
if clkEnR = '1' and keyRdyLongR = '1' then
if keyCntR = keyCntType'high then
keyRdyLongR <= '0';
else
keyCntR <= keyCntR+1;
end if;
end if;
end if;
end process key_stretch;
-- clock process for sync'ing FFs for the PS/2 clock input. This input
-- is async to the internal FPGA clock.
-- (The underlying PS/2 module does not seem to do this.)
clk_proc : process (sysClk, sysRst)
begin
if sysRst = '1' then
ps2ClkR <= '0';
ps2ClkRR <= '0';
ps2ClkRR <= '0';
elsif rising_edge(sysClk) then
ps2ClkR <= ps2_clk_i;
ps2ClkRR <= ps2ClkR;
ps2ClkRRR <= ps2ClkRR;
end if;
end process clk_proc;
-- Handle new key presses.
keypress : process (sysClk, sysRst)
begin
if sysRst = '1' then
keyDataR <= (others => '0');
flagsR <= (others => '0');
keyRdyR <= '0';
realSpeedEnR <= '0';
ledBrightR <= "100";
elsif rising_edge(sysClk) then
if keyRdy = '1' then keyDataR <= keyData; end if;
-- Key codes with the lower three bits set are special keys and are not
-- sent to the calculator core.
if keyRdy = '1' and keyData(2 downto 0) /= "111" then keyRdyR <= '1'; else keyRdyR <= '0'; end if;
if keyRdy = '1' and keyData(2 downto 0) = "111" then
if keyData = x"3F" then
-- change the brighness of the LED display
if ledBrightR = "000" then
ledBrightR <= (others => '1');
else
ledBrightR <= ledBrightR - 1;
end if;
elsif keyData = x"27" then
-- Fast speed
if HP55 then
if flagsR(11) /= '1' then
-- only allow fast speed when not in timer mode
realSpeedEnR <= '0';
end if;
else
realSpeedEnR <= '0';
end if;
elsif keyData = x"1F" then
-- RealSpeed
realSpeedEnR <= '1';
elsif keyData = x"07" and HP55 then
flagsR <= (others => '0'); -- Switch in RUN mode
elsif keyData = x"0F" and HP55 then
flagsR <= (others => '0');
flagsR(3) <= '1'; -- Switch in PROG mode
elsif keyData = x"17" and HP55 then
flagsR <= (others => '0');
flagsR(11) <= '1'; -- Switch in TIMER mode
realSpeedEnR <= '1'; -- need to be in realspeed mode for timer to be correct
end if;
end if;
end if;
end process keypress;
-----------------------------------------
-- Start of the UART driver
-----------------------------------------
UART_YES : if UART_TX or UART_RX generate
begin
RX_YES : if UART_RX generate
constant KEY_PREFIX : std_logic_vector(7 downto 0) := x"0F";
constant CMD_PREFIX : std_logic_vector(7 downto 0) := x"F0";
type fsmType is (IDLE, GET_KEY, GET_CMD);
signal fsmR : fsmType;
signal dataRcv : std_logic_vector(7 downto 0);
signal rxSerial : std_logic;
signal rxDataAv : std_logic;
begin
uut_rx: entity work.uart_rx(rtl)
generic map (
CLK_HZ => CLK_FREQ,
BAUD => 115200
)
port map (
clk_i => sysClk,
rst_i => sysRst,
rx_i => rxSerial,
data_o => dataRcv,
val_o => rxDataAv
);
rxSerial <= uart_rx_i;
rx_fsm : process (sysClk, sysRst)
begin
if sysRst = '1' then
fsmR <= IDLE;
uartKeyRdyR <= '0';
uartKeyDataR <= (others => '0');
elsif rising_edge(sysClk) then
uartKeyRdyR <= '0';
case fsmR is
when IDLE =>
if rxDataAv = '1' and dataRcv = KEY_PREFIX then
-- A keycode is being received
fsmR <= GET_KEY;
elsif rxDataAv = '1' and dataRcv = CMD_PREFIX then
-- A command is being received
fsmR <= GET_CMD;
end if;
when GET_KEY =>
if rxDataAv = '1' then
uartKeyRdyR <= '1';
uartKeyDataR <= dataRcv;
fsmR <= IDLE;
end if;
when GET_CMD =>
if rxDataAv = '1' then
uartKeyRdyR <= '1';
uartKeyDataR <= dataRcv;
fsmR <= IDLE;
end if;
end case;
end if;
end process rx_fsm;
end generate RX_YES;
RX_NO : if not UART_RX generate
begin
uartKeyRdyR <= '0';
uartKeyDataR <= (others => '0');
end generate RX_NO;
TX_YES : if UART_TX generate
constant PREFIX : std_logic_vector(7 downto 0) := x"FA";
constant BYTES : natural := WSIZE/2;
subtype byteCntType is natural range 0 to BYTES-1;
type fsmType is (IDLE, SEND_XREG, SEND_MASK, SEND_FLAGS);
signal fsmR : fsmType;
signal dataSendR : std_logic_vector(7 downto 0);
signal txSerial : std_logic;
signal txEot : std_logic;
signal txRdy : std_logic;
signal txWrEnR : std_logic;
signal cntR : byteCntType;
signal xregR : std_logic_vector(55 downto 0);
signal maskR : std_logic_vector(55 downto 0);
signal dcntR : pCntType;
signal pulseR : std_logic;
signal flags : std_logic_vector(7 downto 0);
begin
uut_tx: entity work.uart_tx(rtl)
generic map (
CLK_HZ => CLK_FREQ,
BAUD => 115200
)
port map (
clk_i => sysClk,
rst_i => sysRst,
data_i => dataSendR,
wr_i => txWrEnR,
tx_o => txSerial,
rdy_o => txRdy
);
uart_tx_o <= txSerial;
timer : process (sysClk, sysRst)
begin
if sysRst = '1' then
dcntR <= 0;
pulseR <= '0';
elsif rising_edge(sysClk) then
pulseR <= '0';
if clkEnR = '1' then
if dcntR = DELAY_100MS-1 then
dcntR <= 0;
pulseR <= '1';
else
dcntR <= dcntR + 1;
end if;
end if;
end if;
end process timer;
flags <= "0001" & realSpeedEnR & flagsR(11) & status(6) & status(4) when HP55 else
"0010" & realSpeedEnR & "00" & status(10) when HP45 else
"0100" & realSpeedEnR & "00" & status(10);
tx_fsm : process (sysClk, sysRst)
begin
if sysRst = '1' then
fsmR <= IDLE;
cntR <= 0;
txWrEnR <= '0';
maskR <= (others => '0');
xregR <= (others => '0');
dataSendR <= (others => '0');
elsif rising_edge(sysClk) then
txWrEnR <= '0';
case fsmR is
when IDLE =>
dataSendR <= PREFIX;
cntR <= 0;
maskR <= mask;
xregR <= xreg;
-- if txRdy = '1' and (maskR /= mask or xregR /= xreg) then
if txRdy = '1' and pulseR = '1' then
maskR <= mask;
xregR <= xreg;
txWrEnR <= '1';
fsmR <= SEND_XREG;
end if;
when SEND_XREG =>
dataSendR <= xregR(xregR'left downto xregR'left-7);
if txRdy = '1' then
txWrEnR <= '1';
xregR <= xregR(xregR'left-8 downto 0) & xregR(xregR'left downto xregR'left-7);
if cntR = BYTES-1 then
cntR <= 0;
fsmR <= SEND_MASK;
else
cntR <= cntR + 1;
end if;
end if;
when SEND_MASK =>
dataSendR <= maskR(maskR'left downto maskR'left-7);
if txRdy = '1' then
txWrEnR <= '1';
maskR <= maskR(maskR'left-8 downto 0) & maskR(maskR'left downto maskR'left-7);
if cntR = BYTES-1 then
fsmR <= SEND_FLAGS;
else
cntR <= cntR + 1;
end if;
end if;
when SEND_FLAGS =>
dataSendR <= flags;
if txRdy = '1' then
txWrEnR <= '1';
fsmR <= IDLE;
end if;
end case;
end if;
end process tx_fsm;
end generate TX_YES;
TX_NO : if not UART_TX generate
begin
end generate TX_NO;
end generate UART_YES;
UART_NO : if not(UART_TX or UART_RX) generate
begin
uart_tx_o <= '1';
uartKeyRdyR <= '0';
uartKeyDataR <= (others => '0');
end generate UART_NO;
-----------------------------------------
-- End of the UART driver
-----------------------------------------
-----------------------------------------
-- Start of the LED Display Module driver
-----------------------------------------
-- The led process is a low level driver for the LED display.
-- It will send one byte to the display.
-- Inputs:
-- ledSendR : pulse high to start sending byte to the display
-- ledStartR : should a start bit be sent first?
-- ledSendDataR : 8-bit data to send to the display
-- Output:
-- ledDoneR : pulses high when data has been sent
--
led : process (sysClk, sysRst)
begin
if sysRst = '1' then
ledFsmR <= IDLE;
ledDoneR <= '0';
ledClkR <= '1';
ledDataR <= '1';
ledCntR <= 0;
elsif rising_edge(sysClk) then
if clkEnR='1' then
ledDoneR <= '0';
case ledFsmR is
when IDLE =>
ledCntR <= 0;
if ledSendR = '1' then
if ledStartR = '1' then
ledFsmR <= START;
else
ledFsmR <= SEND1;
end if;
end if;
when START =>
-- Signal a "start" command: drive ledDataR low while ledClkR is high
-- Note: ledClkR is assumed to be already high
ledDataR <= '0';
ledFsmR <= SEND1;
when SEND1 =>
-- drive clock low (assumes it is high already)
ledClkR <= '0';
ledFsmR <= SEND2;
when SEND2 =>
-- drive data
ledDataR <= ledSendDataR(ledCntR);
ledFsmR <= SEND3;
when SEND3 =>
-- drive clock back high
ledClkR <= '1';
if ledCntR = 7 then
if ledEndR = '1' then
ledFsmR <= END1;
else
ledDoneR <= '1';
ledFsmR <= IDLE;
end if;
else
ledCntR <= ledCntR + 1;
ledFsmR <= SEND1;
end if;
when END1 =>
ledClkR <= '0';
ledFsmR <= END2;
when END2 =>
ledDataR <= '0';
ledFsmR <= END3;
when END3 =>
ledClkR <= '1';
ledFsmR <= END4;
when END4 =>
ledDoneR <= '1';
ledDataR <= '1';
ledFsmR <= IDLE;
end case;
end if;
end if;
end process led;
dis_clk_o <= ledClkR;
dis_data_o <= ledDataR;
-- there are two extra digits on the LED display that are not used to
-- dispaly calculator output. These two extra digits can display additiona
-- info. The first extra digit is not used, yet. The second digit is used
-- to display "shift" key status. The "shift" key status varies for each
-- calculator type.
HP35_DIS : if HP35 generate
-- The HP-35 only shift key to do arc-sin, arc-cos, and arc-tan
-- status bit indicates this.
ledExDigit1R <= LED_SPACE;
fShift : process (sysClk, sysRst)
begin
if sysRst = '1' then
ledExDigit2R <= LED_SPACE;
elsif rising_edge(sysClk) then
if status(10) = '1' then
ledExDigit2R <= LED_A;
else
ledExDigit2R <= LED_SPACE;
end if;
end if;
end process fShift;
end generate HP35_DIS;
HP45_DIS : if HP45 generate
-- The HP-45 has one shift key. Status
-- bit 10 indicates its state.
ledExDigit1R <= LED_SPACE;
fShift : process (sysClk, sysRst)
begin
if sysRst = '1' then
ledExDigit2R <= LED_SPACE;
elsif rising_edge(sysClk) then
if status(10) = '1' then
ledExDigit2R <= LED_F;
else
ledExDigit2R <= LED_SPACE;
end if;
end if;
end process fShift;
end generate HP45_DIS;
HP55_DIS : if HP55 generate
-- The HP-45 has two shift keys. Status bits 4, 6, and 11
-- need to be looked at to determine the shift key states.
ledExDigit1R <= LED_SPACE;
fgShift : process (sysClk, sysRst)
begin
if sysRst = '1' then
ledExDigit2R <= LED_SPACE;
elsif rising_edge(sysClk) then
-- Note: When in timer mode (flagsR(11) is set) status(6)
-- indicates if the timer is stopped (status(6)=1 if timer is stopped)
if status(6) = '1' and flagsR(11) /= '1' then
ledExDigit2R <= LED_F;
elsif status(4) = '1' then
ledExDigit2R <= LED_G;
else
ledExDigit2R <= LED_SPACE;
end if;
ledExDigit2R(7) <= realSpeedEnR;
end if;
end process fgShift;
end generate HP55_DIS;
-- The ledDisplay process is the higher level LED display
-- driver. It displays the current value of the X register,
-- the sign-on message or the error message.
ledDisplay : process (sysClk, sysRst, xregLedR, maskLedR)
variable bcd : std_logic_vector(3 downto 0);
variable dMask: std_logic_vector(3 downto 0);
begin
bcd := xregLedR(55 downto 52);
dMask := maskLedR(55 downto 52);
if sysRst = '1' then
disLedFsmR <= CMD1;
indexLedR <= 0;
ledStartR <= '0';
ledEndR <= '0';
ledSendR <= '0';
ledFirstR <= '1'; -- flag for the first time throught the FSM (for Sign On message)
ledSendDataR<= (others => '0');
maskLedR <= (others => '0');
xregLedR <= (others => '0');
elsif rising_edge(sysClk) then
if clkEnR='1' then
ledSendR <= '0';
case disLedFsmR is
when CMD1 =>
maskLedR <= mask;
xregLedR <= xreg;
indexLedR <= 0;
ledSendDataR <= "01000000"; -- Data Mode: Address Auto + 1
ledSendR <= '1';
ledEndR <= '1';
-- if realSpeedEnR /= '1' or displayEn = '1' then
if ledFirstR = '1' or error = '1' or displayEn = '1' then
ledStartR <= '1';
disLedFsmR <= CMD2;
end if;
when CMD2 =>
if ledDoneR = '1' then
ledSendDataR <= x"C0" or x"00"; -- set address
ledStartR <= '1';
ledSendR <= '1';
ledEndR <= '0';
if ledFirstR = '1' then
disLedFsmR <= SIGNON_D;
elsif error = '1' then
disLedFsmR <= ERROR_D;
else
disLedFsmR <= CMD2W;
end if;
end if;
when SIGNON_D =>
if ledDoneR = '1' then
ledSendDataR <= LED_SIGNON(indexLedR);
ledStartR <= '0';
ledSendR <= '1';
if indexLedR = 13 then
ledEndR <= '0';
disLedFsmR <= DIS_EX1;
else
indexLedR <= indexLedR + 1;
ledEndR <= '0';
end if;
end if;
when ERROR_D =>
if ledDoneR = '1' then
ledSendDataR <= LED_ERROR(indexLedR);
ledStartR <= '0';
ledSendR <= '1';
if indexLedR = 13 then
ledEndR <= '0';
disLedFsmR <= DIS_EX1;
else
indexLedR <= indexLedR + 1;
ledEndR <= '0';
end if;
end if;
when CMD2W =>
if ledDoneR = '1' then
disLedFsmR <= T0;
end if;
when T0 =>
if dMask = "1001" then
ledSendDataR <= LED_SPACE; -- space
else
if indexLedR=11 or indexLedR=0 then -- the two sign positions
if bcd = "1001" then
if dMask = "0000" then
ledSendDataR <= LED_MINUS; -- '-'
else
ledSendDataR <= LED_MINUS or LED_DP; -- '-.'
end if;
else
if dMask = "0000" then
ledSendDataR <= LED_SPACE; -- space
else
ledSendDataR <= LED_0 or LED_DP; -- space
end if;
end if;
elsif dMask = "0000" then
ledSendDataR <= LED_HEX_FONT(to_integer(unsigned(bcd)));
else
ledSendDataR <= LED_HEX_FONT(to_integer(unsigned(bcd))) or LED_DP;
end if;
end if;
ledStartR <= '0';
ledSendR <= '1';
if indexLedR = 13 then
ledEndR <= '0';
disLedFsmR <= DIS_EX1;
else
ledEndR <= '0';
disLedFsmR <= T1;
end if;
when T1 =>
if ledDoneR = '1' then
indexLedR <= indexLedR + 1;
maskLedR <= maskLedR(51 downto 0) & "0000";
xregLedR <= xregLedR(51 downto 0) & "0000";
disLedFsmR <= T0;
end if;
when DIS_EX1 =>
if ledDoneR = '1' then
ledSendDataR <= ledExDigit1R;
ledStartR <= '0';
ledSendR <= '1';
ledEndR <= '0';
disLedFsmR <= DIS_EX2;
end if;
when DIS_EX2 =>
if ledDoneR = '1' then
ledSendDataR <= ledExDigit2R;
ledStartR <= '0';
ledSendR <= '1';
ledEndR <= '1';
disLedFsmR <= DIS_CMD1;
end if;
when DIS_CMD1 =>
if ledDoneR = '1' then
ledSendDataR <= x"80" or x"08" or "00000"&std_logic_vector(ledBrightR); -- Display Command: On & full brighness
ledStartR <= '1';
ledSendR <= '1';
ledEndR <= '1';
disLedFsmR <= DIS_CMD2;
end if;
when DIS_CMD2 =>
if ledDoneR = '1' then
if ledFirstR = '1' then
disLedFsmR <= SIGNON_W;
else
disLedFsmR <= CMD1;
end if;
end if;
when SIGNON_W =>
-- wait for keyboard activity
ledFirstR <= '0'; -- reset first flag
if (ps2ClkRRR='0' and ps2ClkRR = '1') or keyRdyLongR = '1' then
disLedFsmR <= CMD1;
end if;
end case;
end if;
end if;
end process ledDisplay;
-----------------------------------------
-- End of the LED Display Module driver
-----------------------------------------
end rtl;
|
mit
|
Umesh8Joshi/VHDL-programs
|
Transport_delay.vhdl
|
1
|
235
|
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY delay_line IS
PORT ( a : IN std_logic;
PORT (
b : OUT std_logic);
END delay_line;
ARCHITECTURE delay_line OF delay_line IS
BEGIN
b <= TRANSPORT a AFTER 20 ns;
END delay_line;
|
mit
|
jelliotartz/Active-Record-Drill
|
public/ace-builds/demo/kitchen-sink/docs/vhdl.vhd
|
472
|
830
|
library IEEE
user IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COUNT16 is
port (
cOut :out std_logic_vector(15 downto 0); -- counter output
clkEn :in std_logic; -- count enable
clk :in std_logic; -- clock input
rst :in std_logic -- reset input
);
end entity;
architecture count_rtl of COUNT16 is
signal count :std_logic_vector (15 downto 0);
begin
process (clk, rst) begin
if(rst = '1') then
count <= (others=>'0');
elsif(rising_edge(clk)) then
if(clkEn = '1') then
count <= count + 1;
end if;
end if;
end process;
cOut <= count;
end architecture;
|
mit
|
abidrahmank/MyRoughWork
|
vitbi/ACSunit.vhd
|
1
|
3303
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------
entity ACSunit is
port (din : IN std_logic_vector(1 downto 0);-- data input
RESET,CLK:IN std_logic;
outPM1,outPM2,outPM3,outPM4:out std_logic_vector (2 downto 0);-- path metric values
--- dec1,dec2,dec3,dec4:out std_logic
decisions:out std_logic_vector (3 downto 0));--decisions of 4 ACS
end ACSunit;
---------------------------------------------------------------
architecture arch_ACSunit of ACSunit is
component BMU
port (CLK,reset: in std_logic;
din : IN std_logic_vector(1 downto 0);
W,X,Y,Z : OUT std_logic_vector(1 downto 0));
end component;
component ACS
port (PMU,PMD:in std_logic_vector (2 downto 0);
BMU,BMD:in std_logic_vector (1 downto 0);
DECISION:OUT std_logic;
RESET,CLK:IN std_logic;
PM:OUT std_logic_vector (2 downto 0));
end component;
signal PM1,PM2,PM3,PM4:std_logic_vector (2 downto 0);--path metric values
signal pr_PM1,pr_PM2,pr_PM3,pr_PM4:std_logic_vector (2 downto 0);--previous path metric values
signal BM1,BM2,BM3,BM4:std_logic_vector (1 downto 0);--branch metric values
signal reg1,reg2,reg3,reg4:std_logic_vector(2 downto 0);--registers to store pm values
signal dec1,dec2,dec3,dec4:std_logic;
--------------------------------------------------------------------------
begin
bmUnits:BMU port map(CLK,reset,din,BM1,BM2,BM3,BM4); -- calling branch metric units
ACS1:ACS port map(pr_PM1,pr_PM3,BM1,BM4,dec1,RESET,CLK,PM1);-- calling acs units
ACS2:ACS port map(pr_PM1,pr_PM3,BM4,BM1,dec2,RESET,CLK,PM2);
ACS3:ACS port map(pr_PM2,pr_PM4,BM2,BM3,dec3,RESET,CLK,PM3);
ACS4:ACS port map(pr_PM2,pr_PM4,BM3,BM2,dec4,RESET,CLK,PM4);
decisions(0) <= dec1;
decisions(1) <= dec2;
decisions(2) <= dec3;
decisions(3) <= dec4;
process(CLK,RESET,reg1,reg2,reg3,reg4)
begin
if(reset = '1')then
pr_PM1 <= "000";-- resetting the previous path metric
pr_PM2 <= "000";-- values to 000
pr_PM3 <= "000";
pr_PM4 <= "000";
elsif (clk'event and clk = '0')then
pr_PM1 <= reg1; -- reading previous path metric values from
pr_PM2 <= reg2; -- registers and assigning them to corresponding
pr_PM3 <= reg3; -- signals
pr_PM4 <= reg4;
end if;
end process;
process (PM1,PM2,PM3,PM4)
begin
reg1 <= PM1; -- saving path metric values to registers
reg2 <= PM2;
reg3 <= PM3;
reg4 <= PM4;
outPM1 <= PM1; -- taking path metric values to out put ports
outPM2 <= PM2;
outPM3 <= PM3;
outPM4 <= PM4;
end process;
end arch_ACSunit;
|
mit
|
ssabogal/nocturnal
|
noc_dev/noc_dev.srcs/sources_1/bd/sys/ip/sys_router_20_1/sim/sys_router_20_1.vhd
|
1
|
7453
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:router:1.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY sys_router_20_1 IS
PORT (
CLOCK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
L_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VIN : IN STD_LOGIC;
L_RIN : OUT STD_LOGIC;
L_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VOUT : OUT STD_LOGIC;
L_ROUT : IN STD_LOGIC;
S_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_VIN : IN STD_LOGIC;
S_RIN : OUT STD_LOGIC;
S_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_VOUT : OUT STD_LOGIC;
S_ROUT : IN STD_LOGIC;
W_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
W_VIN : IN STD_LOGIC;
W_RIN : OUT STD_LOGIC;
W_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
W_VOUT : OUT STD_LOGIC;
W_ROUT : IN STD_LOGIC
);
END sys_router_20_1;
ARCHITECTURE sys_router_20_1_arch OF sys_router_20_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sys_router_20_1_arch: ARCHITECTURE IS "yes";
COMPONENT router_struct IS
GENERIC (
ADDR_X : INTEGER;
ADDR_Y : INTEGER;
N_INST : BOOLEAN;
S_INST : BOOLEAN;
E_INST : BOOLEAN;
W_INST : BOOLEAN
);
PORT (
CLOCK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
L_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VIN : IN STD_LOGIC;
L_RIN : OUT STD_LOGIC;
L_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VOUT : OUT STD_LOGIC;
L_ROUT : IN STD_LOGIC;
N_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
N_VIN : IN STD_LOGIC;
N_RIN : OUT STD_LOGIC;
N_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
N_VOUT : OUT STD_LOGIC;
N_ROUT : IN STD_LOGIC;
S_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_VIN : IN STD_LOGIC;
S_RIN : OUT STD_LOGIC;
S_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_VOUT : OUT STD_LOGIC;
S_ROUT : IN STD_LOGIC;
E_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
E_VIN : IN STD_LOGIC;
E_RIN : OUT STD_LOGIC;
E_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
E_VOUT : OUT STD_LOGIC;
E_ROUT : IN STD_LOGIC;
W_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
W_VIN : IN STD_LOGIC;
W_RIN : OUT STD_LOGIC;
W_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
W_VOUT : OUT STD_LOGIC;
W_ROUT : IN STD_LOGIC
);
END COMPONENT router_struct;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLOCK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLOCK CLK";
ATTRIBUTE X_INTERFACE_INFO OF RESET: SIGNAL IS "xilinx.com:signal:reset:1.0 RESET RST";
ATTRIBUTE X_INTERFACE_INFO OF L_DIN: SIGNAL IS "xilinx.com:interface:axis:1.0 L_IN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF L_VIN: SIGNAL IS "xilinx.com:interface:axis:1.0 L_IN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF L_RIN: SIGNAL IS "xilinx.com:interface:axis:1.0 L_IN TREADY";
ATTRIBUTE X_INTERFACE_INFO OF L_DOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 L_OUT TDATA";
ATTRIBUTE X_INTERFACE_INFO OF L_VOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 L_OUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF L_ROUT: SIGNAL IS "xilinx.com:interface:axis:1.0 L_OUT TREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_DIN: SIGNAL IS "xilinx.com:interface:axis:1.0 S_IN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_VIN: SIGNAL IS "xilinx.com:interface:axis:1.0 S_IN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_RIN: SIGNAL IS "xilinx.com:interface:axis:1.0 S_IN TREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_DOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 S_OUT TDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_VOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 S_OUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_ROUT: SIGNAL IS "xilinx.com:interface:axis:1.0 S_OUT TREADY";
ATTRIBUTE X_INTERFACE_INFO OF W_DIN: SIGNAL IS "xilinx.com:interface:axis:1.0 W_IN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF W_VIN: SIGNAL IS "xilinx.com:interface:axis:1.0 W_IN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF W_RIN: SIGNAL IS "xilinx.com:interface:axis:1.0 W_IN TREADY";
ATTRIBUTE X_INTERFACE_INFO OF W_DOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 W_OUT TDATA";
ATTRIBUTE X_INTERFACE_INFO OF W_VOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 W_OUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF W_ROUT: SIGNAL IS "xilinx.com:interface:axis:1.0 W_OUT TREADY";
BEGIN
U0 : router_struct
GENERIC MAP (
ADDR_X => 2,
ADDR_Y => 2,
N_INST => false,
S_INST => true,
E_INST => false,
W_INST => true
)
PORT MAP (
CLOCK => CLOCK,
RESET => RESET,
L_DIN => L_DIN,
L_VIN => L_VIN,
L_RIN => L_RIN,
L_DOUT => L_DOUT,
L_VOUT => L_VOUT,
L_ROUT => L_ROUT,
N_DIN => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
N_VIN => '0',
N_ROUT => '0',
S_DIN => S_DIN,
S_VIN => S_VIN,
S_RIN => S_RIN,
S_DOUT => S_DOUT,
S_VOUT => S_VOUT,
S_ROUT => S_ROUT,
E_DIN => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
E_VIN => '0',
E_ROUT => '0',
W_DIN => W_DIN,
W_VIN => W_VIN,
W_RIN => W_RIN,
W_DOUT => W_DOUT,
W_VOUT => W_VOUT,
W_ROUT => W_ROUT
);
END sys_router_20_1_arch;
|
mit
|
jdeblese/clocksync
|
driveseg.vhd
|
1
|
3688
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
package driveseg_comp is
component driveseg
Port(
data : in STD_LOGIC_VECTOR (15 downto 0);
seg_c : out STD_LOGIC_VECTOR (7 downto 0);
seg_a : out std_logic_vector (3 downto 0);
en : in std_logic_vector(3 downto 0);
clk : in std_logic;
rst : in std_logic);
end component;
end package;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.driveseg_comp.all;
entity driveseg is
Port ( data : in STD_LOGIC_VECTOR (15 downto 0);
seg_c : out STD_LOGIC_VECTOR (7 downto 0);
seg_a : out std_logic_vector (3 downto 0);
en : in std_logic_vector(3 downto 0);
clk : in std_logic;
rst : in std_logic);
end driveseg;
architecture Behavioral of driveseg is
signal latch : std_logic_vector(15 downto 0);
signal active : std_logic_vector(3 downto 0);
signal active_new : std_logic_vector(3 downto 0);
signal cathode, cathode_new : std_logic_vector(7 downto 0);
signal divider : unsigned(27 downto 0);
begin
seg_a <= active;
seg_c <= cathode;
process(clk,rst)
variable div,old : std_logic;
begin
if rst = '1' then
latch <= (others => '0');
active <= "1110";
cathode <= (others => '0');
divider <= (others => '0');
old := '0';
elsif rising_edge(clk) then
div := divider(16);
if old = '0' and div = '1' then
active <= active_new;
cathode <= cathode_new;
end if;
latch <= data;
divider <= divider + "1";
old := div;
end if;
end process;
process(en,active,latch,cathode)
variable digit : std_logic_vector(3 downto 0);
variable segen : std_logic;
variable active_next : std_logic_vector(3 downto 0);
variable cathode_next : std_logic_vector(7 downto 0);
begin
active_next := active(2 downto 0) & active(3);
cathode_next := cathode;
-- Turn off dots
cathode_next(7) := '1';
-- Extract the current digit
case active_next is
when "1110" => digit := latch( 3 downto 0);
when "1101" => digit := latch( 7 downto 4);
when "1011" => digit := latch(11 downto 8);
when "0111" => digit := latch(15 downto 12);
when others => digit := "0000";
end case;
-- Check if the current digit is active
segen := (not active_next(3) and en(3)) or (not active_next(2) and en(2)) or (not active_next(1) and en(1)) or (not active_next(0) and en(0));
-- Drive the segment cathode based on the given digit
if segen = '1' then
case digit is
when "0000" => cathode_next(6 downto 0) := "1000000";
when "0001" => cathode_next(6 downto 0) := "1111001";
when "0010" => cathode_next(6 downto 0) := "0100100";
when "0011" => cathode_next(6 downto 0) := "0110000";
when "0100" => cathode_next(6 downto 0) := "0011001";
when "0101" => cathode_next(6 downto 0) := "0010010";
when "0110" => cathode_next(6 downto 0) := "0000010";
when "0111" => cathode_next(6 downto 0) := "1111000";
when "1000" => cathode_next(6 downto 0) := "0000000";
when "1001" => cathode_next(6 downto 0) := "0010000";
when "1010" => cathode_next(6 downto 0) := "0001000";
when "1011" => cathode_next(6 downto 0) := "0000011";
when "1100" => cathode_next(6 downto 0) := "1000110";
when "1101" => cathode_next(6 downto 0) := "0100001";
when "1110" => cathode_next(6 downto 0) := "0000110";
when "1111" => cathode_next(6 downto 0) := "0001110";
when others => cathode_next(6 downto 0) := "0111111";
end case;
else
cathode_next(6 downto 0) := "1111111";
end if;
active_new <= active_next;
cathode_new <= cathode_next;
end process;
end Behavioral;
|
mit
|
ssabogal/nocturnal
|
noc_dev/noc_dev.srcs/sources_1/bd/sys/ip/sys_router_10_1/sim/sys_router_10_1.vhd
|
1
|
8266
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:router:1.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY sys_router_10_1 IS
PORT (
CLOCK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
L_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VIN : IN STD_LOGIC;
L_RIN : OUT STD_LOGIC;
L_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VOUT : OUT STD_LOGIC;
L_ROUT : IN STD_LOGIC;
S_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_VIN : IN STD_LOGIC;
S_RIN : OUT STD_LOGIC;
S_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_VOUT : OUT STD_LOGIC;
S_ROUT : IN STD_LOGIC;
E_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
E_VIN : IN STD_LOGIC;
E_RIN : OUT STD_LOGIC;
E_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
E_VOUT : OUT STD_LOGIC;
E_ROUT : IN STD_LOGIC;
W_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
W_VIN : IN STD_LOGIC;
W_RIN : OUT STD_LOGIC;
W_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
W_VOUT : OUT STD_LOGIC;
W_ROUT : IN STD_LOGIC
);
END sys_router_10_1;
ARCHITECTURE sys_router_10_1_arch OF sys_router_10_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sys_router_10_1_arch: ARCHITECTURE IS "yes";
COMPONENT router_struct IS
GENERIC (
ADDR_X : INTEGER;
ADDR_Y : INTEGER;
N_INST : BOOLEAN;
S_INST : BOOLEAN;
E_INST : BOOLEAN;
W_INST : BOOLEAN
);
PORT (
CLOCK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
L_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VIN : IN STD_LOGIC;
L_RIN : OUT STD_LOGIC;
L_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VOUT : OUT STD_LOGIC;
L_ROUT : IN STD_LOGIC;
N_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
N_VIN : IN STD_LOGIC;
N_RIN : OUT STD_LOGIC;
N_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
N_VOUT : OUT STD_LOGIC;
N_ROUT : IN STD_LOGIC;
S_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_VIN : IN STD_LOGIC;
S_RIN : OUT STD_LOGIC;
S_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_VOUT : OUT STD_LOGIC;
S_ROUT : IN STD_LOGIC;
E_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
E_VIN : IN STD_LOGIC;
E_RIN : OUT STD_LOGIC;
E_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
E_VOUT : OUT STD_LOGIC;
E_ROUT : IN STD_LOGIC;
W_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
W_VIN : IN STD_LOGIC;
W_RIN : OUT STD_LOGIC;
W_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
W_VOUT : OUT STD_LOGIC;
W_ROUT : IN STD_LOGIC
);
END COMPONENT router_struct;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLOCK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLOCK CLK";
ATTRIBUTE X_INTERFACE_INFO OF RESET: SIGNAL IS "xilinx.com:signal:reset:1.0 RESET RST";
ATTRIBUTE X_INTERFACE_INFO OF L_DIN: SIGNAL IS "xilinx.com:interface:axis:1.0 L_IN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF L_VIN: SIGNAL IS "xilinx.com:interface:axis:1.0 L_IN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF L_RIN: SIGNAL IS "xilinx.com:interface:axis:1.0 L_IN TREADY";
ATTRIBUTE X_INTERFACE_INFO OF L_DOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 L_OUT TDATA";
ATTRIBUTE X_INTERFACE_INFO OF L_VOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 L_OUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF L_ROUT: SIGNAL IS "xilinx.com:interface:axis:1.0 L_OUT TREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_DIN: SIGNAL IS "xilinx.com:interface:axis:1.0 S_IN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_VIN: SIGNAL IS "xilinx.com:interface:axis:1.0 S_IN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_RIN: SIGNAL IS "xilinx.com:interface:axis:1.0 S_IN TREADY";
ATTRIBUTE X_INTERFACE_INFO OF S_DOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 S_OUT TDATA";
ATTRIBUTE X_INTERFACE_INFO OF S_VOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 S_OUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF S_ROUT: SIGNAL IS "xilinx.com:interface:axis:1.0 S_OUT TREADY";
ATTRIBUTE X_INTERFACE_INFO OF E_DIN: SIGNAL IS "xilinx.com:interface:axis:1.0 E_IN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF E_VIN: SIGNAL IS "xilinx.com:interface:axis:1.0 E_IN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF E_RIN: SIGNAL IS "xilinx.com:interface:axis:1.0 E_IN TREADY";
ATTRIBUTE X_INTERFACE_INFO OF E_DOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 E_OUT TDATA";
ATTRIBUTE X_INTERFACE_INFO OF E_VOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 E_OUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF E_ROUT: SIGNAL IS "xilinx.com:interface:axis:1.0 E_OUT TREADY";
ATTRIBUTE X_INTERFACE_INFO OF W_DIN: SIGNAL IS "xilinx.com:interface:axis:1.0 W_IN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF W_VIN: SIGNAL IS "xilinx.com:interface:axis:1.0 W_IN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF W_RIN: SIGNAL IS "xilinx.com:interface:axis:1.0 W_IN TREADY";
ATTRIBUTE X_INTERFACE_INFO OF W_DOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 W_OUT TDATA";
ATTRIBUTE X_INTERFACE_INFO OF W_VOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 W_OUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF W_ROUT: SIGNAL IS "xilinx.com:interface:axis:1.0 W_OUT TREADY";
BEGIN
U0 : router_struct
GENERIC MAP (
ADDR_X => 1,
ADDR_Y => 2,
N_INST => false,
S_INST => true,
E_INST => true,
W_INST => true
)
PORT MAP (
CLOCK => CLOCK,
RESET => RESET,
L_DIN => L_DIN,
L_VIN => L_VIN,
L_RIN => L_RIN,
L_DOUT => L_DOUT,
L_VOUT => L_VOUT,
L_ROUT => L_ROUT,
N_DIN => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
N_VIN => '0',
N_ROUT => '0',
S_DIN => S_DIN,
S_VIN => S_VIN,
S_RIN => S_RIN,
S_DOUT => S_DOUT,
S_VOUT => S_VOUT,
S_ROUT => S_ROUT,
E_DIN => E_DIN,
E_VIN => E_VIN,
E_RIN => E_RIN,
E_DOUT => E_DOUT,
E_VOUT => E_VOUT,
E_ROUT => E_ROUT,
W_DIN => W_DIN,
W_VIN => W_VIN,
W_RIN => W_RIN,
W_DOUT => W_DOUT,
W_VOUT => W_VOUT,
W_ROUT => W_ROUT
);
END sys_router_10_1_arch;
|
mit
|
ssabogal/nocturnal
|
ip_repo/router/src/fifo_tb.vhd
|
1
|
1643
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo_tb is
end entity;
architecture testbench of fifo_tb is
component fifo32x1K is
port (
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component;
signal CLOCK : std_logic := '0';
signal RESET : std_logic := '0';
signal DIN : std_logic_vector(31 downto 0) := (others => 'X');
signal VIN : std_logic := '0';
signal RIN : std_logic;
signal DOUT : std_logic_vector(31 downto 0);
signal VOUT : std_logic;
signal ROUT : std_logic := '0';
signal reset_n : std_logic;
begin
UUT: fifo32x1K
port map (
s_aclk => CLOCK,
s_aresetn => reset_n,
s_axis_tdata => DIN,
s_axis_tvalid => VIN,
s_axis_tready => RIN,
m_axis_tdata => DOUT,
m_axis_tvalid => VOUT,
m_axis_tready => ROUT
);
CLOCK <= not CLOCK after 5 ns;
reset_n <= not RESET;
process
begin
RESET <= '1';
wait until rising_edge(CLOCK);
RESET <= '0';
wait until RIN = '1';
wait until rising_edge(CLOCK);
for i in 1 to 8 loop
DIN <= std_logic_vector(to_unsigned(i, 32));
VIN <= '1';
wait until rising_edge(CLOCK);
end loop;
DIN <= (others => 'X');
VIN <= '0';
wait for 50 ns;
for i in 1 to 8 loop
ROUT <= '1';
wait until rising_edge(CLOCK);
end loop;
ROUT <= '0';
wait for 500 ns;
wait;
end process;
end architecture;
|
mit
|
ssabogal/nocturnal
|
noc_dev/noc_dev.srcs/sources_1/bd/sys/ip/sys_router_00_0/sim/sys_router_00_0.vhd
|
1
|
8266
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:router:1.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY sys_router_00_0 IS
PORT (
CLOCK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
L_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VIN : IN STD_LOGIC;
L_RIN : OUT STD_LOGIC;
L_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VOUT : OUT STD_LOGIC;
L_ROUT : IN STD_LOGIC;
N_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
N_VIN : IN STD_LOGIC;
N_RIN : OUT STD_LOGIC;
N_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
N_VOUT : OUT STD_LOGIC;
N_ROUT : IN STD_LOGIC;
E_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
E_VIN : IN STD_LOGIC;
E_RIN : OUT STD_LOGIC;
E_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
E_VOUT : OUT STD_LOGIC;
E_ROUT : IN STD_LOGIC;
W_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
W_VIN : IN STD_LOGIC;
W_RIN : OUT STD_LOGIC;
W_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
W_VOUT : OUT STD_LOGIC;
W_ROUT : IN STD_LOGIC
);
END sys_router_00_0;
ARCHITECTURE sys_router_00_0_arch OF sys_router_00_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sys_router_00_0_arch: ARCHITECTURE IS "yes";
COMPONENT router_struct IS
GENERIC (
ADDR_X : INTEGER;
ADDR_Y : INTEGER;
N_INST : BOOLEAN;
S_INST : BOOLEAN;
E_INST : BOOLEAN;
W_INST : BOOLEAN
);
PORT (
CLOCK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
L_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VIN : IN STD_LOGIC;
L_RIN : OUT STD_LOGIC;
L_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VOUT : OUT STD_LOGIC;
L_ROUT : IN STD_LOGIC;
N_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
N_VIN : IN STD_LOGIC;
N_RIN : OUT STD_LOGIC;
N_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
N_VOUT : OUT STD_LOGIC;
N_ROUT : IN STD_LOGIC;
S_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_VIN : IN STD_LOGIC;
S_RIN : OUT STD_LOGIC;
S_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_VOUT : OUT STD_LOGIC;
S_ROUT : IN STD_LOGIC;
E_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
E_VIN : IN STD_LOGIC;
E_RIN : OUT STD_LOGIC;
E_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
E_VOUT : OUT STD_LOGIC;
E_ROUT : IN STD_LOGIC;
W_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
W_VIN : IN STD_LOGIC;
W_RIN : OUT STD_LOGIC;
W_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
W_VOUT : OUT STD_LOGIC;
W_ROUT : IN STD_LOGIC
);
END COMPONENT router_struct;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLOCK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLOCK CLK";
ATTRIBUTE X_INTERFACE_INFO OF RESET: SIGNAL IS "xilinx.com:signal:reset:1.0 RESET RST";
ATTRIBUTE X_INTERFACE_INFO OF L_DIN: SIGNAL IS "xilinx.com:interface:axis:1.0 L_IN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF L_VIN: SIGNAL IS "xilinx.com:interface:axis:1.0 L_IN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF L_RIN: SIGNAL IS "xilinx.com:interface:axis:1.0 L_IN TREADY";
ATTRIBUTE X_INTERFACE_INFO OF L_DOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 L_OUT TDATA";
ATTRIBUTE X_INTERFACE_INFO OF L_VOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 L_OUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF L_ROUT: SIGNAL IS "xilinx.com:interface:axis:1.0 L_OUT TREADY";
ATTRIBUTE X_INTERFACE_INFO OF N_DIN: SIGNAL IS "xilinx.com:interface:axis:1.0 N_IN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF N_VIN: SIGNAL IS "xilinx.com:interface:axis:1.0 N_IN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF N_RIN: SIGNAL IS "xilinx.com:interface:axis:1.0 N_IN TREADY";
ATTRIBUTE X_INTERFACE_INFO OF N_DOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 N_OUT TDATA";
ATTRIBUTE X_INTERFACE_INFO OF N_VOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 N_OUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF N_ROUT: SIGNAL IS "xilinx.com:interface:axis:1.0 N_OUT TREADY";
ATTRIBUTE X_INTERFACE_INFO OF E_DIN: SIGNAL IS "xilinx.com:interface:axis:1.0 E_IN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF E_VIN: SIGNAL IS "xilinx.com:interface:axis:1.0 E_IN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF E_RIN: SIGNAL IS "xilinx.com:interface:axis:1.0 E_IN TREADY";
ATTRIBUTE X_INTERFACE_INFO OF E_DOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 E_OUT TDATA";
ATTRIBUTE X_INTERFACE_INFO OF E_VOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 E_OUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF E_ROUT: SIGNAL IS "xilinx.com:interface:axis:1.0 E_OUT TREADY";
ATTRIBUTE X_INTERFACE_INFO OF W_DIN: SIGNAL IS "xilinx.com:interface:axis:1.0 W_IN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF W_VIN: SIGNAL IS "xilinx.com:interface:axis:1.0 W_IN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF W_RIN: SIGNAL IS "xilinx.com:interface:axis:1.0 W_IN TREADY";
ATTRIBUTE X_INTERFACE_INFO OF W_DOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 W_OUT TDATA";
ATTRIBUTE X_INTERFACE_INFO OF W_VOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 W_OUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF W_ROUT: SIGNAL IS "xilinx.com:interface:axis:1.0 W_OUT TREADY";
BEGIN
U0 : router_struct
GENERIC MAP (
ADDR_X => 1,
ADDR_Y => 0,
N_INST => true,
S_INST => false,
E_INST => true,
W_INST => true
)
PORT MAP (
CLOCK => CLOCK,
RESET => RESET,
L_DIN => L_DIN,
L_VIN => L_VIN,
L_RIN => L_RIN,
L_DOUT => L_DOUT,
L_VOUT => L_VOUT,
L_ROUT => L_ROUT,
N_DIN => N_DIN,
N_VIN => N_VIN,
N_RIN => N_RIN,
N_DOUT => N_DOUT,
N_VOUT => N_VOUT,
N_ROUT => N_ROUT,
S_DIN => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_VIN => '0',
S_ROUT => '0',
E_DIN => E_DIN,
E_VIN => E_VIN,
E_RIN => E_RIN,
E_DOUT => E_DOUT,
E_VOUT => E_VOUT,
E_ROUT => E_ROUT,
W_DIN => W_DIN,
W_VIN => W_VIN,
W_RIN => W_RIN,
W_DOUT => W_DOUT,
W_VOUT => W_VOUT,
W_ROUT => W_ROUT
);
END sys_router_00_0_arch;
|
mit
|
ssabogal/nocturnal
|
ip_repo/router/src/shift_reg_stub.vhd
|
2
|
2647
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity shift_reg_stub is
port (
CLOCK : in std_logic;
RESET : in std_logic;
DIN : in std_logic_vector(31 downto 0);
VIN : in std_logic;
RIN : out std_logic;
DOUT : out std_logic_vector(31 downto 0);
VOUT : out std_logic;
ROUT : in std_logic;
AX : out std_logic_vector(1 downto 0);
AY : out std_logic_vector(1 downto 0);
SZ : out std_logic_vector(15 downto 0);
VAL3 : out std_logic
);
end entity;
architecture structure of shift_reg_stub is
type shift_reg_t is array(2 downto 0) of std_logic_vector(31 downto 0);
signal shift_reg : shift_reg_t;
signal shift_reg_next : shift_reg_t;
type state_t is (S000, S001, S011, S111);
signal state, state_next : state_t;
begin
DOUT <= shift_reg(2);
AX <= shift_reg(2)(31 downto 30);
AY <= shift_reg(2)(29 downto 28);
SZ <= shift_reg(0)(15 downto 0);
process (CLOCK)
begin
if rising_edge(CLOCK) then
if RESET = '1' then
state <= S000;
else
state <= state_next;
shift_reg(2) <= shift_reg_next(2);
shift_reg(1) <= shift_reg_next(1);
shift_reg(0) <= shift_reg_next(0);
end if;
end if;
end process;
process (state, shift_reg, DIN, VIN, ROUT)
begin
state_next <= state;
RIN <= '0';
VOUT <= '0';
VAL3 <= '0';
shift_reg_next <= shift_reg;
case state is
when S000 =>
if VIN = '1' then
RIN <= '1';
state_next <= S001;
shift_reg_next(2) <= DIN;
end if;
when S001 =>
VOUT <= '1';
if VIN = '1' and ROUT = '1' then
RIN <= '1';
state_next <= S001;
shift_reg_next(2) <= DIN;
elsif VIN = '1' then
RIN <= '1';
state_next <= S011;
shift_reg_next(1) <= DIN;
elsif ROUT = '1' then
state_next <= S000;
end if;
when S011 =>
VOUT <= '1';
if VIN = '1' and ROUT = '1' then
RIN <= '1';
state_next <= S011;
shift_reg_next(2) <= shift_reg(1);
shift_reg_next(1) <= DIN;
elsif VIN = '1' then
RIN <= '1';
state_next <= S111;
shift_reg_next(0) <= DIN;
elsif ROUT = '1' then
shift_reg_next(2) <= shift_reg(1);
state_next <= S001;
end if;
when S111 =>
VAL3 <= '1';
VOUT <= '1';
if VIN = '1' and ROUT = '1' then
RIN <= '1';
state_next <= S111;
shift_reg_next(2) <= shift_reg(1);
shift_reg_next(1) <= shift_reg(0);
shift_reg_next(0) <= DIN;
elsif ROUT = '1' then
shift_reg_next(2) <= shift_reg(1);
shift_reg_next(1) <= shift_reg(0);
state_next <= S011;
end if;
end case;
end process;
end architecture;
|
mit
|
kauecano/eel5105
|
vhds/mux2x1.vhd
|
1
|
481
|
library IEEE;
use IEEE.Std_Logic_1164.all;
entity mux2x1 is
port (x: in std_logic_vector(9 downto 0);--entrada do mux.
y: in std_logic_vector(9 downto 0);--entrada do mux.
s: in std_logic;--entrada de seleção.
m: out std_logic_vector(9 downto 0)--saída do mux que será uma das entradas conforme o valor do bit de seleção.
);
end mux2x1;
architecture mux2x1_estr of mux2x1 is
begin
m <= x when s = '0' else-- abordagem comportamental.
y;
end mux2x1_estr;
|
mit
|
ssabogal/nocturnal
|
noc_dev/noc_dev.srcs/sources_1/bd/sys/ip/sys_axi_nic_10_1/synth/sys_axi_nic_10_1.vhd
|
1
|
9482
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:axi_nic:1.0
-- IP Revision: 11
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY sys_axi_nic_10_1 IS
PORT (
RX_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
RX_VALID : IN STD_LOGIC;
RX_READY : OUT STD_LOGIC;
TX_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TX_VALID : OUT STD_LOGIC;
TX_READY : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC
);
END sys_axi_nic_10_1;
ARCHITECTURE sys_axi_nic_10_1_arch OF sys_axi_nic_10_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sys_axi_nic_10_1_arch: ARCHITECTURE IS "yes";
COMPONENT nic_v1_0 IS
GENERIC (
C_S00_AXI_DATA_WIDTH : INTEGER;
C_S00_AXI_ADDR_WIDTH : INTEGER;
USE_1K_NOT_4K_FIFO_DEPTH : BOOLEAN
);
PORT (
RX_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
RX_VALID : IN STD_LOGIC;
RX_READY : OUT STD_LOGIC;
TX_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TX_VALID : OUT STD_LOGIC;
TX_READY : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC
);
END COMPONENT nic_v1_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF sys_axi_nic_10_1_arch: ARCHITECTURE IS "nic_v1_0,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF sys_axi_nic_10_1_arch : ARCHITECTURE IS "sys_axi_nic_10_1,nic_v1_0,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF RX_DATA: SIGNAL IS "xilinx.com:interface:axis:1.0 RX TDATA";
ATTRIBUTE X_INTERFACE_INFO OF RX_VALID: SIGNAL IS "xilinx.com:interface:axis:1.0 RX TVALID";
ATTRIBUTE X_INTERFACE_INFO OF RX_READY: SIGNAL IS "xilinx.com:interface:axis:1.0 RX TREADY";
ATTRIBUTE X_INTERFACE_INFO OF TX_DATA: SIGNAL IS "xilinx.com:interface:axis:1.0 TX TDATA";
ATTRIBUTE X_INTERFACE_INFO OF TX_VALID: SIGNAL IS "xilinx.com:interface:axis:1.0 TX TVALID";
ATTRIBUTE X_INTERFACE_INFO OF TX_READY: SIGNAL IS "xilinx.com:interface:axis:1.0 TX TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s00_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s00_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi RREADY";
BEGIN
U0 : nic_v1_0
GENERIC MAP (
C_S00_AXI_DATA_WIDTH => 32,
C_S00_AXI_ADDR_WIDTH => 5,
USE_1K_NOT_4K_FIFO_DEPTH => false
)
PORT MAP (
RX_DATA => RX_DATA,
RX_VALID => RX_VALID,
RX_READY => RX_READY,
TX_DATA => TX_DATA,
TX_VALID => TX_VALID,
TX_READY => TX_READY,
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn,
s00_axi_awaddr => s00_axi_awaddr,
s00_axi_awprot => s00_axi_awprot,
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_awready => s00_axi_awready,
s00_axi_wdata => s00_axi_wdata,
s00_axi_wstrb => s00_axi_wstrb,
s00_axi_wvalid => s00_axi_wvalid,
s00_axi_wready => s00_axi_wready,
s00_axi_bresp => s00_axi_bresp,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_araddr => s00_axi_araddr,
s00_axi_arprot => s00_axi_arprot,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_arready => s00_axi_arready,
s00_axi_rdata => s00_axi_rdata,
s00_axi_rresp => s00_axi_rresp,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_rready => s00_axi_rready
);
END sys_axi_nic_10_1_arch;
|
mit
|
kauecano/eel5105
|
vhds/topo.vhd
|
1
|
3817
|
library ieee;
use ieee.std_logic_1164.all;
entity topo is
port (SW: in std_logic_vector(9 downto 0);
KEY: in std_logic_vector(3 downto 0);
CLOCK_50: in std_logic;
HEX5: out std_logic_vector(6 downto 0);
HEX4: out std_logic_vector(6 downto 0);
HEX3: out std_logic_vector(6 downto 0);
HEX2: out std_logic_vector(6 downto 0);
HEX1: out std_logic_vector(6 downto 0);
HEX0: out std_logic_vector(6 downto 0);
LEDR: out std_logic_vector(9 downto 0)
);
end topo;
architecture topo_arch of topo is
signal CONTA_ASC: std_logic_vector(19 DOWNTO 0);
signal AGENDA, PASSWORD, REG: std_logic_vector(19 downto 0);
signal LED_OUT, CONTA_DESC: std_logic_vector(9 downto 0);
signal ESTADOS, SEQ_3, SEQ_2, SEQ_1, SEQ_0: std_logic_vector(4 downto 0);
signal TENTATIVAS, SEL_DISP: std_logic_vector(1 downto 0);
signal C3, C2, C1, C0, CLK1, CLK2: std_logic;
signal BTN3, BTN2, BTN1, BTN0: std_logic;
signal SEL_LED, TESTE_PASS, PASS_CERTO, SALDO: std_logic;
component FSM_control
port (PASS_CERTO, BTN3, BTN0, SALDO, CLOCK_50: in std_logic;
C3, C2, C1, C0, SEL_LED, TESTE_PASS: out std_logic;
SEL_DISP, TENTATIVAS: out std_logic_vector(1 downto 0);
ESTADOS: out std_logic_vector(4 downto 0)
);
end component;
component topo_reg
port (BTN0, C3, C2, C1, C0, CLOCK_50: IN STD_LOGIC;
REG: IN STD_LOGIC_VECTOR(19 downto 0);
SEQ_3, SEQ_2, SEQ_1, SEQ_0 : OUT STD_LOGIC_VECTOR(4 downto 0)
);
end component;
component topo_selec
port (SW: in std_logic_vector(9 downto 0);
AGENDA: in std_logic_vector(19 downto 0);
CONTA_ASC: in std_logic_vector(19 downto 0);
CONTA_DESC: in std_logic_vector(9 downto 0);
SEL_DISP: in std_logic_vector(1 downto 0);
TENTATIVAS: in std_logic_vector(1 downto 0);
SEL_LED: in std_logic;
REG: out std_logic_vector(19 downto 0);
LED_OUT: out std_logic_vector(9 downto 0)
);
end component;
component topo_comparadores
port (SEQ_3, SEQ_2, SEQ_1, SEQ_0 : IN STD_LOGIC_VECTOR(4 downto 0);
CONTA_DES: IN STD_LOGIC_VECTOR(9 downto 0);
TESTE_PASS: IN STD_LOGIC;
PASS_CERTO, SALDO : OUT STD_LOGIC
);
end component;
component ROM
port ( address: in std_logic_vector(3 downto 0);
data: out std_logic_vector(19 downto 0) );
end component;
component ButtonSync
port(
-- Input ports
key0 : in std_logic;
key1 : in std_logic;
key2 : in std_logic;
key3 : in std_logic;
clk : in std_logic;
-- Output ports
btn0 : out std_logic;
btn1 : out std_logic;
btn2 : out std_logic;
btn3 : out std_logic
);
end component;
component decod7seg
port (C: in std_logic_vector(4 downto 0);
F: out std_logic_vector(6 downto 0)
);
end component;
component topo_contador
port (BTN0, SEL_LED, CLOCK_50: in std_logic;
SEL_DISP: in std_logic_vector(1 downto 0);
CONTA_ASC: out std_logic_vector(19 downto 0);
CONTA_DESC: out std_logic_vector(9 downto 0)
);
end component;
begin
HEX5 <= "0000110";
LEDR <= LED_OUT;
L00: FSM_control port map (PASS_CERTO, BTN3, BTN0, SALDO, CLOCK_50, C3, C2, C1, C0, SEL_LED, TESTE_PASS, SEL_DISP, TENTATIVAS, ESTADOS);
L01: topo_reg port map (BTN0, C3, C2, C1, C0, CLOCK_50, REG, SEQ_3, SEQ_2, SEQ_1, SEQ_0);
L02: topo_selec port map (SW, AGENDA, CONTA_ASC, CONTA_DESC, SEL_DISP, TENTATIVAS, SEL_LED, REG, LED_OUT);
L03: topo_comparadores port map (SEQ_3, SEQ_2, SEQ_1, SEQ_0, CONTA_DESC, TESTE_PASS, PASS_CERTO, SALDO);
L04: ROM port map (SW(3 downto 0), AGENDA);
L05: ButtonSync port map (KEY(0), KEY(1), KEY(2), KEY(3), CLOCK_50, BTN0, BTN1, BTN2, BTN3);
L06: decod7seg port map (ESTADOS, HEX4);
L07: decod7seg port map (SEQ_3, HEX3);
L08: decod7seg port map (SEQ_2, HEX2);
L09: decod7seg port map (SEQ_1, HEX1);
L10: decod7seg port map (SEQ_0, HEX0);
L11: topo_contador port map (BTN0, SEL_LED, CLOCK_50, SEL_DISP, CONTA_ASC, CONTA_DESC);
end topo_arch;
|
mit
|
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