repo_name
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HighlandersFRC/fpga
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led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_bram_ctrl_0_0/axi_bram_ctrl_v3_0/hdl/vhdl/wrap_brst.vhd
|
7
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51441
|
-------------------------------------------------------------------------------
-- wrap_brst.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2013] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: wrap_brst.vhd
--
-- Description: Create sub module for logic to generate WRAP burst
-- address for rd_chnl and wr_chnl.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v1_03_a)
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
--
--
--
-------------------------------------------------------------------------------
--
-- History:
--
-- ^^^^^^
-- JLJ 2/2/2011 v1.03a
-- ~~~~~~
-- Migrate to v1.03a.
-- Plus minor code cleanup.
-- ^^^^^^
-- JLJ 2/4/2011 v1.03a
-- ~~~~~~
-- Edit for scalability and support of 512 and 1024-bit data widths.
-- Add axi_bram_ctrl_funcs package inclusion.
-- ^^^^^^
-- JLJ 2/7/2011 v1.03a
-- ~~~~~~
-- Remove axi_bram_ctrl_funcs package use.
-- ^^^^^^
-- JLJ 3/15/2011 v1.03a
-- ~~~~~~
-- Update multiply function on signal, wrap_burst_total_cmb,
-- for timing path improvements. Replace with left shift operation.
-- ^^^^^^
-- JLJ 3/17/2011 v1.03a
-- ~~~~~~
-- Add comments as noted in Spyglass runs. And general code clean-up.
-- ^^^^^^
-- JLJ 3/24/2011 v1.03a
-- ~~~~~~
-- Add specific generate blocks based on C_AXI_DATA_WIDTH to calculate
-- total WRAP burst size for improved FPGA resource utilization.
-- ^^^^^^
-- JLJ 3/30/2011 v1.03a
-- ~~~~~~
-- Clean up code.
-- Re-code wrap_burst_total_cmb process blocks for each data width
-- to improve and catch all false conditions in code coverage analysis.
-- ^^^^^^
--
--
--
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.axi_bram_ctrl_funcs.all;
------------------------------------------------------------------------------
entity wrap_brst is
generic (
C_AXI_ADDR_WIDTH : integer := 32;
-- Width of AXI address bus (in bits)
C_BRAM_ADDR_ADJUST_FACTOR : integer := 32;
-- Adjust BRAM address width based on C_AXI_DATA_WIDTH
C_AXI_DATA_WIDTH : integer := 32
-- Width of AXI data bus (in bits)
);
port (
S_AXI_AClk : in std_logic;
S_AXI_AResetn : in std_logic;
curr_axlen : in std_logic_vector(7 downto 0) := (others => '0');
curr_axsize : in std_logic_vector(2 downto 0) := (others => '0');
curr_narrow_burst : in std_logic;
narrow_bram_addr_inc_re : in std_logic;
bram_addr_ld_en : in std_logic;
bram_addr_ld : in std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
bram_addr_int : in std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
bram_addr_ld_wrap : out std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR)
:= (others => '0');
max_wrap_burst_mod : out std_logic := '0'
);
end entity wrap_brst;
-------------------------------------------------------------------------------
architecture implementation of wrap_brst is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
-- Reset active level (common through core)
constant C_RESET_ACTIVE : std_logic := '0';
-- AXI Size Constants
constant C_AXI_SIZE_1BYTE : std_logic_vector (2 downto 0) := "000"; -- 1 byte
constant C_AXI_SIZE_2BYTE : std_logic_vector (2 downto 0) := "001"; -- 2 bytes
constant C_AXI_SIZE_4BYTE : std_logic_vector (2 downto 0) := "010"; -- 4 bytes = max size for 32-bit BRAM
constant C_AXI_SIZE_8BYTE : std_logic_vector (2 downto 0) := "011"; -- 8 bytes = max size for 64-bit BRAM
constant C_AXI_SIZE_16BYTE : std_logic_vector (2 downto 0) := "100"; -- 16 bytes = max size for 128-bit BRAM
constant C_AXI_SIZE_32BYTE : std_logic_vector (2 downto 0) := "101"; -- 32 bytes = max size for 256-bit BRAM
constant C_AXI_SIZE_64BYTE : std_logic_vector (2 downto 0) := "110"; -- 64 bytes = max size for 512-bit BRAM
constant C_AXI_SIZE_128BYTE : std_logic_vector (2 downto 0) := "111"; -- 128 bytes = max size for 1024-bit BRAM
-- Determine the number of bytes based on the AXI data width.
constant C_AXI_DATA_WIDTH_BYTES : integer := C_AXI_DATA_WIDTH/8;
constant C_AXI_DATA_WIDTH_BYTES_LOG2 : integer := log2(C_AXI_DATA_WIDTH_BYTES);
-- 8d = size of AxLEN vector
constant C_MAX_LSHIFT_SIZE : integer := C_AXI_DATA_WIDTH_BYTES_LOG2 + 8;
-- Constants for WRAP size decoding to simplify integer represenation.
constant C_WRAP_SIZE_2 : std_logic_vector (2 downto 0) := "001";
constant C_WRAP_SIZE_4 : std_logic_vector (2 downto 0) := "010";
constant C_WRAP_SIZE_8 : std_logic_vector (2 downto 0) := "011";
constant C_WRAP_SIZE_16 : std_logic_vector (2 downto 0) := "100";
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
signal max_wrap_burst : std_logic := '0';
signal save_init_bram_addr_ld : std_logic_vector (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1)
:= (others => '0');
-- signal curr_axsize_unsigned : unsigned (2 downto 0) := (others => '0');
-- signal curr_axsize_int : integer := 0;
-- signal curr_axlen_unsigned : unsigned (7 downto 0) := (others => '0');
-- Holds burst length/size total (based on width of BRAM width)
-- Max size = max length of burst (256 beats)
-- signal wrap_burst_total_cmb : integer range 0 to 256 := 1; -- Max 256 (= 32768d / 128 bytes)
-- signal wrap_burst_total : integer range 0 to 256 := 1;
signal wrap_burst_total_cmb : std_logic_vector (2 downto 0) := (others => '0');
signal wrap_burst_total : std_logic_vector (2 downto 0) := (others => '0');
-- signal curr_axlen_unsigned_plus1 : unsigned (7 downto 0) := (others => '0');
-- signal curr_axlen_unsigned_plus1_lshift : unsigned (C_MAX_LSHIFT_SIZE downto 0) := (others => '0'); -- Max = 32768d
-------------------------------------------------------------------------------
-- Architecture Body
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- Modify counter size based on size of current write burst operation
-- For WRAP burst types, the counter value will roll over when the burst
-- boundary is reached.
-- Based on AxSIZE and AxLEN
-- To minimize muxing on initial load of counter value
-- Detect on WRAP burst types, when the max address is reached.
-- When the max address is reached, re-load counter with lower
-- address value.
-- Save initial load address value.
REG_INIT_BRAM_ADDR: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
save_init_bram_addr_ld <= (others => '0');
elsif (bram_addr_ld_en = '1') then
save_init_bram_addr_ld <= bram_addr_ld(C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1);
else
save_init_bram_addr_ld <= save_init_bram_addr_ld;
end if;
end if;
end process REG_INIT_BRAM_ADDR;
---------------------------------------------------------------------------
-- v1.03a
-- Calculate AXI size (integer)
-- curr_axsize_unsigned <= unsigned (curr_axsize);
-- curr_axsize_int <= to_integer (curr_axsize_unsigned);
-- Calculate AXI length (integer)
-- curr_axlen_unsigned <= unsigned (curr_axlen);
-- curr_axlen_unsigned_plus1 <= curr_axlen_unsigned + "00000001";
-- WRAP = size * length (based on BRAM data width in bytes)
--
-- Original multiply function:
-- wrap_burst_total_cmb <= (size_bytes_int * len_int) / C_AXI_DATA_WIDTH_BYTES;
-- For XST, modify integer multiply function to improve timing.
-- Replace multiply of AxLEN * AxSIZE with a left shift function.
-- LEN_LSHIFT: process (curr_axlen_unsigned_plus1, curr_axsize_int)
-- begin
--
-- for i in C_MAX_LSHIFT_SIZE downto 0 loop
--
-- if (i >= curr_axsize_int + 8) then
-- curr_axlen_unsigned_plus1_lshift (i) <= '0';
-- elsif (i >= curr_axsize_int) then
-- curr_axlen_unsigned_plus1_lshift (i) <= curr_axlen_unsigned_plus1 (i - curr_axsize_int);
-- else
-- curr_axlen_unsigned_plus1_lshift (i) <= '0';
-- end if;
--
-- end loop;
--
-- end process LEN_LSHIFT;
-- Final signal assignment for XST & timing improvements.
-- wrap_burst_total_cmb <= to_integer (curr_axlen_unsigned_plus1_lshift) / C_AXI_DATA_WIDTH_BYTES;
---------------------------------------------------------------------------
-- v1.03a
-- For best FPGA resource implementation, hard code the generation of
-- WRAP burst size based on each C_AXI_DATA_WIDTH possibility.
---------------------------------------------------------------------------
-- Generate: GEN_32_WRAP_SIZE
-- Purpose: These wrap size values only apply to 32-bit BRAM.
---------------------------------------------------------------------------
GEN_32_WRAP_SIZE: if C_AXI_DATA_WIDTH = 32 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 4 bytes (full AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 2 bytes (1/2 AXI size)
when C_AXI_SIZE_2BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 1 byte (1/4 AXI size)
when C_AXI_SIZE_1BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_1BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_1BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_32_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_64_WRAP_SIZE
-- Purpose: These wrap size values only apply to 64-bit BRAM.
---------------------------------------------------------------------------
GEN_64_WRAP_SIZE: if C_AXI_DATA_WIDTH = 64 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 8 bytes (full AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 4 bytes (1/2 AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 2 bytes (1/4 AXI size)
when C_AXI_SIZE_2BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 1 byte (1/8 AXI size)
when C_AXI_SIZE_1BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_1BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_64_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_128_WRAP_SIZE
-- Purpose: These wrap size values only apply to 128-bit BRAM.
---------------------------------------------------------------------------
GEN_128_WRAP_SIZE: if C_AXI_DATA_WIDTH = 128 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 16 bytes (full AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 8 bytes (1/2 AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 4 bytes (1/4 AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 2 bytes (1/8 AXI size)
when C_AXI_SIZE_2BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_2BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_128_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_256_WRAP_SIZE
-- Purpose: These wrap size values only apply to 256-bit BRAM.
---------------------------------------------------------------------------
GEN_256_WRAP_SIZE: if C_AXI_DATA_WIDTH = 256 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 32 bytes (full AXI size)
when C_AXI_SIZE_32BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 16 bytes (1/2 AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 8 bytes (1/4 AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 4 bytes (1/8 AXI size)
when C_AXI_SIZE_4BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_4BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_256_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_512_WRAP_SIZE
-- Purpose: These wrap size values only apply to 512-bit BRAM.
---------------------------------------------------------------------------
GEN_512_WRAP_SIZE: if C_AXI_DATA_WIDTH = 512 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 64 bytes (full AXI size)
when C_AXI_SIZE_64BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 32 bytes (1/2 AXI size)
when C_AXI_SIZE_32BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 16 bytes (1/4 AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 8 bytes (1/8 AXI size)
when C_AXI_SIZE_8BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_8BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_512_WRAP_SIZE;
---------------------------------------------------------------------------
-- Generate: GEN_1024_WRAP_SIZE
-- Purpose: These wrap size values only apply to 1024-bit BRAM.
---------------------------------------------------------------------------
GEN_1024_WRAP_SIZE: if C_AXI_DATA_WIDTH = 1024 generate
begin
WRAP_SIZE_CMB: process (curr_axlen, curr_axsize)
begin
-- v1.03a
-- Attempt to re code this to improve conditional coverage checks.
-- Use case statment to replace if/else with no priority enabled.
-- Current size of transaction
case (curr_axsize (2 downto 0)) is
-- 128 bytes (full AXI size)
when C_AXI_SIZE_128BYTE =>
case (curr_axlen (3 downto 0)) is
when "0001" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_16;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 64 bytes (1/2 AXI size)
when C_AXI_SIZE_64BYTE =>
case (curr_axlen (3 downto 0)) is
when "0011" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_8;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 32 bytes (1/4 AXI size)
when C_AXI_SIZE_32BYTE =>
case (curr_axlen (3 downto 0)) is
when "0111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_4;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- 16 bytes (1/8 AXI size)
when C_AXI_SIZE_16BYTE =>
case (curr_axlen (3 downto 0)) is
when "1111" => wrap_burst_total_cmb <= C_WRAP_SIZE_2;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
when others => wrap_burst_total_cmb <= (others => '0');
end case;
-- v1.03 Original HDL
--
--
-- if ((curr_axlen (3 downto 0) = "0001") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) or
-- ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_16BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_2;
--
-- elsif ((curr_axlen (3 downto 0) = "0011") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) or
-- ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_32BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_4;
--
-- elsif ((curr_axlen (3 downto 0) = "0111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) or
-- ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_64BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_8;
--
-- elsif ((curr_axlen (3 downto 0) = "1111") and
-- (curr_axsize (2 downto 0) = C_AXI_SIZE_128BYTE)) then
--
-- wrap_burst_total_cmb <= C_WRAP_SIZE_16;
--
-- else
-- wrap_burst_total_cmb <= (others => '0');
-- end if;
end process WRAP_SIZE_CMB;
end generate GEN_1024_WRAP_SIZE;
---------------------------------------------------------------------------
-- Early decode to determine size of WRAP transfer
-- Goal to break up long timing path to generate max_wrap_burst signal.
REG_WRAP_TOTAL: process (S_AXI_AClk)
begin
if (S_AXI_AClk'event and S_AXI_AClk = '1') then
if (S_AXI_AResetn = C_RESET_ACTIVE) then
wrap_burst_total <= (others => '0');
elsif (bram_addr_ld_en = '1') then
wrap_burst_total <= wrap_burst_total_cmb;
else
wrap_burst_total <= wrap_burst_total;
end if;
end if;
end process REG_WRAP_TOTAL;
---------------------------------------------------------------------------
CHECK_WRAP_MAX : process ( wrap_burst_total,
bram_addr_int,
save_init_bram_addr_ld )
begin
-- Check BRAM address value if max value is reached.
-- Max value is based on burst size/length for operation.
-- Address bits to check vary based on C_S_AXI_DATA_WIDTH and burst size/length.
-- (use signal, wrap_burst_total, based on current WRAP burst size/length/data width).
case wrap_burst_total is
when C_WRAP_SIZE_2 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR) = '1') then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR) <= '0';
when C_WRAP_SIZE_4 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR + 1 downto C_BRAM_ADDR_ADJUST_FACTOR) = "11") then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+2) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+2);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR + 1 downto C_BRAM_ADDR_ADJUST_FACTOR ) <= "00";
when C_WRAP_SIZE_8 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR + 2 downto C_BRAM_ADDR_ADJUST_FACTOR) = "111") then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+3) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+3);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR + 2 downto C_BRAM_ADDR_ADJUST_FACTOR ) <= "000";
when C_WRAP_SIZE_16 =>
if (bram_addr_int (C_BRAM_ADDR_ADJUST_FACTOR + 3 downto C_BRAM_ADDR_ADJUST_FACTOR) = "1111") then
max_wrap_burst <= '1';
else
max_wrap_burst <= '0';
end if;
-- Use saved BRAM load value
bram_addr_ld_wrap (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+4) <=
save_init_bram_addr_ld (C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+4);
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR + 3 downto C_BRAM_ADDR_ADJUST_FACTOR ) <= "0000";
when others =>
max_wrap_burst <= '0';
bram_addr_ld_wrap(C_AXI_ADDR_WIDTH-1 downto C_BRAM_ADDR_ADJUST_FACTOR+1) <= save_init_bram_addr_ld;
-- Reset lower order address bits to zero (to wrap address)
bram_addr_ld_wrap (C_BRAM_ADDR_ADJUST_FACTOR) <= '0';
end case;
end process CHECK_WRAP_MAX;
---------------------------------------------------------------------------
-- Move outside of CHECK_WRAP_MAX process.
-- Account for narrow burst operations.
--
-- Currently max_wrap_burst is getting asserted at the first address beat to BRAM
-- that indicates the maximum WRAP burst boundary. Must wait for the completion of the
-- narrow wrap burst counter to assert max_wrap_burst.
--
-- Indicates when narrow burst address counter hits max (all zeros value)
-- narrow_bram_addr_inc_re
max_wrap_burst_mod <= max_wrap_burst when (curr_narrow_burst = '0') else
(max_wrap_burst and narrow_bram_addr_inc_re);
---------------------------------------------------------------------------
end architecture implementation;
|
mit
|
HighlandersFRC/fpga
|
led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_quad_spi_0_0/proc_common_v4_0/hdl/src/vhdl/or_gate.vhd
|
15
|
9199
|
-------------------------------------------------------------------------------
-- $Id: or_gate.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_gate.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_gate.vhd
-- Version: v1.00a
-- Description: OR gate implementation
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- or_gate.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- History:
-- BLT 2001-05-23 First Version
-- ^^^^^^
-- First version of OPB Bus.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library proc_common_v4_0;
use proc_common_v4_0.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_OR_WIDTH -- Which Xilinx FPGA family to target when
-- syntesizing, affect the RLOC string values
-- C_BUS_WIDTH -- Which Y position the RLOC should start from
--
-- Definition of Ports:
-- A -- Input. Input buses are concatenated together to
-- form input A. Example: to OR buses R, S, and T,
-- assign A <= R & S & T;
-- Y -- Output. Same width as input buses.
--
-------------------------------------------------------------------------------
entity or_gate is
generic (
C_OR_WIDTH : natural range 1 to 32 := 17;
C_BUS_WIDTH : natural range 1 to 64 := 1;
C_USE_LUT_OR : boolean := TRUE
);
port (
A : in std_logic_vector(0 to C_OR_WIDTH*C_BUS_WIDTH-1);
Y : out std_logic_vector(0 to C_BUS_WIDTH-1)
);
end entity or_gate;
architecture imp of or_gate is
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component or_muxcy
generic (
C_NUM_BITS : integer := 8
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end component or_muxcy;
signal test : std_logic_vector(0 to C_BUS_WIDTH-1);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin
USE_LUT_OR_GEN: if C_USE_LUT_OR generate
OR_PROCESS: process( A ) is
variable yi : std_logic_vector(0 to (C_OR_WIDTH));
begin
for j in 0 to C_BUS_WIDTH-1 loop
yi(0) := '0';
for i in 0 to C_OR_WIDTH-1 loop
yi(i+1) := yi(i) or A(i*C_BUS_WIDTH+j);
end loop;
Y(j) <= yi(C_OR_WIDTH);
end loop;
end process OR_PROCESS;
end generate USE_LUT_OR_GEN;
USE_MUXCY_OR_GEN: if not C_USE_LUT_OR generate
BUS_WIDTH_FOR_GEN: for i in 0 to C_BUS_WIDTH-1 generate
signal in_Bus : std_logic_vector(0 to C_OR_WIDTH-1);
begin
ORDER_INPUT_BUS_PROCESS: process( A ) is
begin
for k in 0 to C_OR_WIDTH-1 loop
in_Bus(k) <= A(k*C_BUS_WIDTH+i);
end loop;
end process ORDER_INPUT_BUS_PROCESS;
OR_BITS_I: or_muxcy
generic map (
C_NUM_BITS => C_OR_WIDTH
)
port map (
In_bus => in_Bus, --[in]
Or_out => Y(i) --[out]
);
end generate BUS_WIDTH_FOR_GEN;
end generate USE_MUXCY_OR_GEN;
end architecture imp;
|
mit
|
HighlandersFRC/fpga
|
oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/proc_common_v4_0/hdl/src/vhdl/mux_onehot.vhd
|
15
|
14596
|
-------------------------------------------------------------------------------
-- $Id: mux_onehot.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- mux_onehot - arch and entity
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: mux_onehot.vhd
--
-- Description: Parameterizable multiplexer with one hot select lines
--
--
-------------------------------------------------------------------------------
-- Structure:
-- Multi- use module
--------------------------------------------------------------------------------
-- Author: BLT
-- History:
-- BLT 2/22/01 -- First version
--
-- ALS 3/30/01
-- ^^^^^^
-- Added process to replicate select bus for each of the data buses
-- ~~~~~~
--
-- ALS 4/19/01
-- ^^^^^^
-- Modified assignments of DI and CI to use signals one and zero. VHDL87
-- doesn't support direct assignment of these signals to '0' and '1'.
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Generic definitions:
--
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- There is a separate select line for EACH data bit, leaving it to the
-- user to set fanout on the select lines before using this mux. The select
-- bus into the mux is created by concatenating the one-hot select bus for
-- a single output bit as many times as needed for the data width. Continuing
-- the 4 to 1, 2 bit example from above:
--
-- S = (Sel0Data0,Sel1Data0,Sel2Data0,Sel3Data0,
-- Sel0Data1,Sel1Data1,Sel2Data1,Sel3Data1)
--
-- 4/3/01 ALS - modified the code slightly to have the select bus generated
-- from within this code - input select bus is simply one bit per bus
---------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- UNISIM library is required when Xilinx primitives are instantiated.
library unisim;
use unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- There is a separate select line for EACH data bit, leaving it to the
-- user to set fanout on the select lines before using this mux. The select
-- bus into the mux is created by concatenating the one-hot select bus for
-- a single output bit as many times as needed for the data width. Continuing
-- the 4 to 1, 2 bit example from above:
--
-- S = (Sel0Data0,Sel1Data0,Sel2Data0,Sel3Data0,
-- Sel0Data1,Sel1Data1,Sel2Data1,Sel3Data1)
--
-- 4/3/01 ALS - modified the code slightly to have the select bus generated
-- from within this code - input select bus is simply one bit per bus
--
-- Definition of Ports:
-- input D -- input data bus
-- input S -- input select bus
--
-- output Y -- output bus
-------------------------------------------------------------------------------
entity mux_onehot is
generic( C_DW: integer := 32;
C_NB: integer := 5 );
port(
D: in std_logic_vector(0 to C_DW*C_NB-1);
S: in std_logic_vector(0 to C_NB-1);
Y: out std_logic_vector(0 to C_DW-1));
end mux_onehot;
architecture imp of mux_onehot is
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal Dreord: std_logic_vector(0 to C_DW*((C_NB+1)/2)*2-1);
signal sel: std_logic_vector(0 to C_DW*((C_NB+1)/2)*2-1);
signal lutout: std_logic_vector(0 to (C_DW*(C_NB+1)/2)-1);
signal cyout: std_logic_vector(0 to (C_DW*(C_NB+1)/2)-1);
signal one: std_logic := '1';
signal zero: std_logic := '0';
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- MUXCY used to multiplex busses
component MUXCY
port(
O : out STD_LOGIC;
DI : in STD_LOGIC;
CI : in STD_LOGIC;
S : in STD_LOGIC);
end component;
begin
-- Reorder data buses
REORD: process( D )
variable m,n: integer;
begin
for m in 0 to C_DW-1 loop
for n in 0 to C_NB-1 loop
Dreord( m*C_NB+n) <= D( n*C_DW+m );
end loop;
end loop;
end process REORD;
-------------------------------------------------------------------------------
-- REPSELS_PROCESS
-------------------------------------------------------------------------------
-- The one-hot select bus contains 1-bit for each bus. To more easily
-- parameterize the carry chains and reduce loading on the select bus, these
-- signals are replicated into a bus that replicates the select bits for the
-- data width of the busses
-------------------------------------------------------------------------------
REPSELS_PROCESS : process ( S )
variable i, j : integer;
begin
-- loop through all data bits and busses
for i in 0 to C_DW-1 loop
for j in 0 to C_NB-1 loop
sel(i*C_NB+j) <= S(j);
end loop;
end loop;
end process REPSELS_PROCESS;
-- Handle case for even number of buses
EVEN_GEN: if C_NB rem 2 = 0 and C_NB /= 2 generate
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= not((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
CYMUX_FIRST: MUXCY
port map (CI=> zero,
DI=> one,
S=>lutout(i*(C_NB+1)/2),
O=>cyout(i*(C_NB+1)/2));
NUM_BUSES_GEN: for j in 1 to (C_NB+1)/2-1 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)) or
(Dreord(i*C_NB+j*2+1) and sel(i*C_NB+j*2+1)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
Y(i) <= cyout(i*(C_NB+1)/2+(C_NB+1)/2-1);
end generate;
end generate;
-- Handle case for odd number of buses
ODD_GEN: if C_NB rem 2 /= 0 and C_NB /= 1 generate
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= not((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
CYMUX_FIRST: MUXCY
port map (CI=> zero,
DI=> one,
S=>lutout(i*(C_NB+1)/2),
O=>cyout(i*(C_NB+1)/2));
NUM_BUSES_GEN: for j in 1 to (C_NB+1)/2-2 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)) or
(Dreord(i*C_NB+j*2+1) and sel(i*C_NB+j*2+1)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
ODD_BUS_GEN: for j in (C_NB+1)/2-1 to (C_NB+1)/2-1 generate
lutout(i*(C_NB+1)/2+j) <= not((Dreord(i*C_NB+j*2) and sel(i*C_NB+j*2)));
CARRY_MUX: MUXCY
port map (CI=>cyout(i*(C_NB+1)/2+j-1),
DI=> one,
S=>lutout(i*(C_NB+1)/2+j),
O=>cyout(i*(C_NB+1)/2+j));
end generate;
Y(i) <= cyout(i*(C_NB+1)/2+(C_NB+1)/2-1);
end generate;
end generate;
ONE_GEN: if C_NB = 1 generate
Y <= D;
end generate;
TWO_GEN: if C_NB = 2 generate
DATA_WIDTH_GEN2: for i in 0 to C_DW-1 generate
lutout(i*(C_NB+1)/2) <= ((Dreord(i*C_NB) and sel(i*C_NB)) or
(Dreord(i*C_NB+1) and sel(i*C_NB+1)));
Y(i) <= lutout(i*(C_NB+1)/2);
end generate;
end generate;
end imp;
|
mit
|
HighlandersFRC/fpga
|
led_string_no_gpio/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/fifo_generator_v11_0/fifo_generator_v11_0_defaults.vhd
|
19
|
30145
|
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`protect end_protected
|
mit
|
HighlandersFRC/fpga
|
oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/fifo_generator_v11_0/fifo_generator_v11_0_defaults.vhd
|
19
|
30145
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20576)
`protect data_block
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`protect end_protected
|
mit
|
HighlandersFRC/fpga
|
led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_quad_spi_0_0/fifo_generator_v11_0/ramfifo/wr_status_flags_sshft.vhd
|
19
|
23122
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15376)
`protect data_block
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`protect end_protected
|
mit
|
HighlandersFRC/fpga
|
oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/fifo_generator_v11_0/ramfifo/wr_status_flags_sshft.vhd
|
19
|
23122
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15376)
`protect data_block
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`protect end_protected
|
mit
|
HighlandersFRC/fpga
|
led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_gpio_0_0/fifo_generator_v11_0/ramfifo/wr_status_flags_sshft.vhd
|
19
|
23122
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15376)
`protect data_block
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`protect end_protected
|
mit
|
HighlandersFRC/fpga
|
led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/fifo_generator_v11_0/ramfifo/wr_logic_pkt_fifo.vhd
|
19
|
31831
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 21824)
`protect data_block
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`protect end_protected
|
mit
|
HighlandersFRC/fpga
|
led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_bram_ctrl_0_0/fifo_generator_v11_0/ramfifo/wr_logic_pkt_fifo.vhd
|
19
|
31831
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 21824)
`protect data_block
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`protect end_protected
|
mit
|
HighlandersFRC/fpga
|
led_string_no_gpio/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/fifo_generator_v11_0/ramfifo/wr_logic_pkt_fifo.vhd
|
19
|
31831
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 21824)
`protect data_block
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nx0tWQ4HWHED2eMPaWGYexKavCDQGVXBNT6Ogmko9AOado2qKIebpCBBPlq1P/IGWnk=
`protect end_protected
|
mit
|
HighlandersFRC/fpga
|
lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/pf_adder.vhd
|
15
|
10246
|
-------------------------------------------------------------------------------
-- $Id: pf_adder.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- pf_adder - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_adder.vhd
--
-- Description: Parameterized adder/subtractor for Mauna Loa Packet FIFO
-- vacancy calculation. This design has a combinational
-- output. The carry out is not used by the PFIFO so it has
-- been removed.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_adder.vhd
--
-------------------------------------------------------------------------------
-- Author: D. Thorpe
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:46 $
--
-- History:
-- DET 2001-08-30 First Version
-- - adapted from B Tise MicroBlaze timer counters
--
-- DET 2001-09-11
-- - Added the Rst input to the pf_adder_bit component
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_adder is
generic (
C_REGISTERED_RESULT : Boolean := false;
C_COUNT_WIDTH : integer := 10
);
port (
Clk : in std_logic;
Rst : in std_logic;
--Carry_Out : out std_logic;
Ain : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Bin : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Add_sub_n : in std_logic;
result_out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_adder;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_adder is
component pf_adder_bit is
generic (
C_REGISTERED_RESULT : Boolean
);
port (
Clk : in std_logic;
Rst : In std_logic;
Ain : in std_logic;
Bin : in std_logic;
Add_sub_n : in std_logic;
Carry_In : in std_logic;
Clock_Enable : in std_logic;
Result : out std_logic;
Carry_Out : out std_logic);
end component pf_adder_bit;
-- component FDRE is
-- port (
-- Q : out std_logic;
-- C : in std_logic;
-- CE : in std_logic;
-- D : in std_logic;
-- R : in std_logic
-- );
-- end component FDRE;
--
constant CY_START : integer := 1;
signal alu_cy : std_logic_vector(0 to C_COUNT_WIDTH);
signal iresult_out : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal count_clock_en : std_logic;
--signal carry_active_high : std_logic;
begin -- VHDL_RTL
-----------------------------------------------------------------------------
-- Generate the Counter bits
-----------------------------------------------------------------------------
alu_cy(C_COUNT_WIDTH) <= not(Add_sub_n); -- initial carry-in to adder LSB
count_clock_en <= '1';
I_ADDSUB_GEN : for i in 0 to C_COUNT_WIDTH-1 generate
begin
Counter_Bit_I : pf_adder_bit
Generic map(
C_REGISTERED_RESULT => C_REGISTERED_RESULT
)
port map (
Clk => Clk, -- [in]
Rst => Rst, -- [in]
Ain => Ain(i), -- [in]
Bin => Bin(i), -- [in]
Add_sub_n => Add_sub_n, -- [in]
Carry_In => alu_cy(i+CY_Start), -- [in]
Clock_Enable => count_clock_en, -- [in]
Result => iresult_out(i), -- [out]
Carry_Out => alu_cy(i+(1-CY_Start))); -- [out]
end generate I_ADDSUB_GEN;
-- carry_active_high <= alu_cy(0) xor not(Add_sub_n);
--
--
--
-- I_CARRY_OUT: FDRE
-- port map (
-- Q => Carry_Out, -- [out]
-- C => Clk, -- [in]
-- CE => count_clock_en, -- [in]
-- D => carry_active_high, -- [in]
-- R => Rst -- [in]
-- );
result_out <= iresult_out;
end architecture implementation;
|
mit
|
HighlandersFRC/fpga
|
oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/proc_common_v4_0/hdl/src/vhdl/pf_counter.vhd
|
15
|
9203
|
-------------------------------------------------------------------------------
-- $Id: pf_counter.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- pf_counter - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter.vhd
--
-- Description: Implements 32-bit timer/counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:46 $
--
-- History:
-- D. Thorpe 2001-08-30 First Version
-- - adapted from B Tise MicroBlaze counters
--
-- DET 2001-09-11
-- - Added the Rst input to the pf_counter_bit component
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.pf_counter_bit;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter is
generic (
C_COUNT_WIDTH : integer := 9
);
port (
Clk : in std_logic;
Rst : in std_logic;
Carry_Out : out std_logic;
Load_In : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_counter;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter is
constant CY_START : integer := 1;
signal alu_cy : std_logic_vector(0 to C_COUNT_WIDTH);
signal iCount_Out : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal count_clock_en : std_logic;
signal carry_active_high : std_logic;
begin -- VHDL_RTL
-----------------------------------------------------------------------------
-- Generate the Counter bits
-----------------------------------------------------------------------------
alu_cy(C_COUNT_WIDTH) <= (Count_Down and Count_Load) or
(not Count_Down and not Count_load);
count_clock_en <= Count_Enable or Count_Load;
I_ADDSUB_GEN : for i in 0 to C_COUNT_WIDTH-1 generate
begin
Counter_Bit_I : entity proc_common_v4_0.pf_counter_bit
port map (
Clk => Clk, -- [in]
Rst => Rst, -- [in]
Count_In => iCount_Out(i), -- [in]
Load_In => Load_In(i), -- [in]
Count_Load => Count_Load, -- [in]
Count_Down => Count_Down, -- [in]
Carry_In => alu_cy(i+CY_Start), -- [in]
Clock_Enable => count_clock_en, -- [in]
Result => iCount_Out(i), -- [out]
Carry_Out => alu_cy(i+(1-CY_Start))); -- [out]
end generate I_ADDSUB_GEN;
carry_active_high <= alu_cy(0) xor Count_Down;
I_CARRY_OUT: FDRE
port map (
Q => Carry_Out, -- [out]
C => Clk, -- [in]
CE => count_clock_en, -- [in]
D => carry_active_high, -- [in]
R => Rst -- [in]
);
Count_Out <= iCount_Out;
end architecture implementation;
|
mit
|
HighlandersFRC/fpga
|
lights_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/proc_common_v4_0/hdl/src/vhdl/pf_counter.vhd
|
15
|
9203
|
-------------------------------------------------------------------------------
-- $Id: pf_counter.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- pf_counter - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter.vhd
--
-- Description: Implements 32-bit timer/counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:46 $
--
-- History:
-- D. Thorpe 2001-08-30 First Version
-- - adapted from B Tise MicroBlaze counters
--
-- DET 2001-09-11
-- - Added the Rst input to the pf_counter_bit component
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.pf_counter_bit;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter is
generic (
C_COUNT_WIDTH : integer := 9
);
port (
Clk : in std_logic;
Rst : in std_logic;
Carry_Out : out std_logic;
Load_In : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_counter;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter is
constant CY_START : integer := 1;
signal alu_cy : std_logic_vector(0 to C_COUNT_WIDTH);
signal iCount_Out : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal count_clock_en : std_logic;
signal carry_active_high : std_logic;
begin -- VHDL_RTL
-----------------------------------------------------------------------------
-- Generate the Counter bits
-----------------------------------------------------------------------------
alu_cy(C_COUNT_WIDTH) <= (Count_Down and Count_Load) or
(not Count_Down and not Count_load);
count_clock_en <= Count_Enable or Count_Load;
I_ADDSUB_GEN : for i in 0 to C_COUNT_WIDTH-1 generate
begin
Counter_Bit_I : entity proc_common_v4_0.pf_counter_bit
port map (
Clk => Clk, -- [in]
Rst => Rst, -- [in]
Count_In => iCount_Out(i), -- [in]
Load_In => Load_In(i), -- [in]
Count_Load => Count_Load, -- [in]
Count_Down => Count_Down, -- [in]
Carry_In => alu_cy(i+CY_Start), -- [in]
Clock_Enable => count_clock_en, -- [in]
Result => iCount_Out(i), -- [out]
Carry_Out => alu_cy(i+(1-CY_Start))); -- [out]
end generate I_ADDSUB_GEN;
carry_active_high <= alu_cy(0) xor Count_Down;
I_CARRY_OUT: FDRE
port map (
Q => Carry_Out, -- [out]
C => Clk, -- [in]
CE => count_clock_en, -- [in]
D => carry_active_high, -- [in]
R => Rst -- [in]
);
Count_Out <= iCount_Out;
end architecture implementation;
|
mit
|
HighlandersFRC/fpga
|
led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/proc_common_v4_0/hdl/src/vhdl/pf_counter.vhd
|
15
|
9203
|
-------------------------------------------------------------------------------
-- $Id: pf_counter.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- pf_counter - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: pf_counter.vhd
--
-- Description: Implements 32-bit timer/counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- pf_counter.vhd
--
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:46 $
--
-- History:
-- D. Thorpe 2001-08-30 First Version
-- - adapted from B Tise MicroBlaze counters
--
-- DET 2001-09-11
-- - Added the Rst input to the pf_counter_bit component
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_common_v4_0;
use proc_common_v4_0.pf_counter_bit;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity pf_counter is
generic (
C_COUNT_WIDTH : integer := 9
);
port (
Clk : in std_logic;
Rst : in std_logic;
Carry_Out : out std_logic;
Load_In : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Count_Out : out std_logic_vector(0 to C_COUNT_WIDTH-1)
);
end entity pf_counter;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture implementation of pf_counter is
constant CY_START : integer := 1;
signal alu_cy : std_logic_vector(0 to C_COUNT_WIDTH);
signal iCount_Out : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal count_clock_en : std_logic;
signal carry_active_high : std_logic;
begin -- VHDL_RTL
-----------------------------------------------------------------------------
-- Generate the Counter bits
-----------------------------------------------------------------------------
alu_cy(C_COUNT_WIDTH) <= (Count_Down and Count_Load) or
(not Count_Down and not Count_load);
count_clock_en <= Count_Enable or Count_Load;
I_ADDSUB_GEN : for i in 0 to C_COUNT_WIDTH-1 generate
begin
Counter_Bit_I : entity proc_common_v4_0.pf_counter_bit
port map (
Clk => Clk, -- [in]
Rst => Rst, -- [in]
Count_In => iCount_Out(i), -- [in]
Load_In => Load_In(i), -- [in]
Count_Load => Count_Load, -- [in]
Count_Down => Count_Down, -- [in]
Carry_In => alu_cy(i+CY_Start), -- [in]
Clock_Enable => count_clock_en, -- [in]
Result => iCount_Out(i), -- [out]
Carry_Out => alu_cy(i+(1-CY_Start))); -- [out]
end generate I_ADDSUB_GEN;
carry_active_high <= alu_cy(0) xor Count_Down;
I_CARRY_OUT: FDRE
port map (
Q => Carry_Out, -- [out]
C => Clk, -- [in]
CE => count_clock_en, -- [in]
D => carry_active_high, -- [in]
R => Rst -- [in]
);
Count_Out <= iCount_Out;
end architecture implementation;
|
mit
|
HighlandersFRC/fpga
|
led_string_no_gpio/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/fifo_generator_v11_0/ramfifo/bram_sync_reg.vhd
|
19
|
7904
|
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GPxAxnrSDPM=
`protect end_protected
|
mit
|
HighlandersFRC/fpga
|
oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_9/fifo_generator_v11_0/ramfifo/bram_sync_reg.vhd
|
19
|
7904
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
ISK+8BrzqbDVc2hIh4k9UuGvqsq6yFic71tfszsK7KRf52jFUoK33AosGVUYsGH1pmrUc2NUQcDQ
LseNrcojiQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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4aiU6ycFpLQsNzqRlAw=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4112)
`protect data_block
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GPxAxnrSDPM=
`protect end_protected
|
mit
|
HighlandersFRC/fpga
|
led_string_no_gpio/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_15/blk_mem_gen_v8_1/blk_mem_gen_v8_1_synth_comp.vhd
|
27
|
18409
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
cPZ8vU4rKWICMycnP8ASghxteX0KiiSQpWJpCIK7voNSpkWhaLkY+/QNXKrCWexA6C73eW4MlVqP
U/aYYyUL6A==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
LGoeeEeMUHkj3xBumwl7JSHXwdKJWR3APWiWCdcCy3wVC6g0GScQrp7fjvXp784YBiHqjtsyG69d
mOZ3fy7Gj87kc/h2xvc4Kp6GM/IiHJc0mbPVp01AJelfAExlIEaVGoQkcAXR2aVikeaMxuRKkb9m
THdehu5n5eHx4/tJQjQ=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
aia+xx8RLMhA3IF4tHoW0Vw6LtYVDVgU/c3FBWk9RJ/SaLw9lkXng6eXJGNs7uUJXmkzrbSEXjkp
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PBei/XvAf3p1OvrOrKNUCVdwEg17DQWfBwZyYg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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0Ezm1jX/FmstQisPDpo=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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fj/RQD4+HY8CEDIrJcGjF+Rpk986lOFjZ/hvRA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11888)
`protect data_block
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`protect end_protected
|
mit
|
HighlandersFRC/fpga
|
led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_xbar_0/blk_mem_gen_v8_1/blk_mem_gen_v8_1_synth_comp.vhd
|
27
|
18409
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11888)
`protect data_block
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`protect end_protected
|
mit
|
HighlandersFRC/fpga
|
led_string_no_gpio/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_15/fifo_generator_v11_0/ramfifo/wr_status_flags_ss.vhd
|
19
|
23791
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15872)
`protect data_block
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|
mit
|
HighlandersFRC/fpga
|
led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_gpio_0_0/proc_common_v4_0/hdl/src/vhdl/or_muxcy_f.vhd
|
15
|
12722
|
-------------------------------------------------------------------------------
-- $Id: or_muxcy_f.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- or_muxcy_f
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: or_muxcy_f.vhd
--
-- Description:
-- (Note: It is recommended to use this module sparingly.
-- XST synthesis inferral of reduction-OR functionality
-- has progressed to where a carry-chain implementation
-- will be selected if it has advantages. At the same
-- time, if a rigid carry chain structure is not imposed,
-- XST has more degrees of freedom for optimization.
--
-- This module can be used to get an inferred implementation
-- by specifying C_FAMILY = "nofamily", which is the default
-- value of this Generic. It is equally possible to use
-- a reduction-or function (see or_reduce, below, for an
-- example) instead of this module.
--
-- If however the designer wants without compromise
-- a structural carry-chain implementation, then this
-- module can be used with C_FAMILY set to the target
-- Xilinx FPGA family.
--
-- End of Note.
-- )
--
--
-- Or_out <= or_reduce(In_bus)
--
-- i.e., OR together the bits in In_bus and assign to Or_out.
--
-- The implementation uses a single LUT if possible.
-- Otherwise, if C_FAMILY supports the carry chain concept,
-- it uses a minimal number of LUTs on a carry chain.
-- The native LUT size of C_FAMILY is taken into account.
--
-------------------------------------------------------------------------------
-- Structure: Common use module
-------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 07/06/06 -- First version - derived from or_with_enable_f
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--
entity or_muxcy_f is
generic (
C_NUM_BITS : integer;
C_FAMILY : string := "nofamily"
);
port (
In_bus : in std_logic_vector(0 to C_NUM_BITS-1);
Or_out : out std_logic
);
end or_muxcy_f;
library proc_common_v4_0;
use proc_common_v4_0.family_support.all;
-- Makes visible the function 'supported' and related types,
-- including enumeration literals for the unisim primitives (e.g.
-- the "u_" prefixed identifiers such as u_MUXCY, u_LUT4, etc.).
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
--
architecture implementation of or_muxcy_f is
----------------------------------------------------------------------------
-- Here is determined the largest LUT width supported by the target family.
-- If no LUT is supported, the width is set to a very large number, which,
-- as things are structured, will cause an inferred implementation
-- to be used.
----------------------------------------------------------------------------
constant lut_size : integer
:= native_lut_size(fam_as_string => C_FAMILY,
no_lut_return_val => integer'high);
----------------------------------------------------------------------------
-- Here is determined which structural or inferred implementation to use.
----------------------------------------------------------------------------
constant USE_STRUCTURAL_A : boolean := supported(C_FAMILY, u_MUXCY) and
In_bus'length > lut_size;
-- Structural implementation not needed if the number
-- bits to be ORed will fit into a single LUT.
constant USE_INFERRED : boolean := not USE_STRUCTURAL_A;
----------------------------------------------------------------------------
-- Reduction OR function.
----------------------------------------------------------------------------
function or_reduce (v : std_logic_vector) return std_logic is
variable r : std_logic := '0';
begin
for i in v'range loop
r := r or v(i);
end loop;
return r;
end;
----------------------------------------------------------------------------
-- Min function.
----------------------------------------------------------------------------
function min (a, b: natural) return natural is
begin
if (a>b) then return b; else return a; end if;
end;
----------------------------------------------------------------------------
-- Signal to recast In_bus into a local array whose index bounds and
-- direction are known.
----------------------------------------------------------------------------
signal OB : std_logic_vector(0 to In_bus'length-1);
----------------------------------------------------------------------------
-- Unisim components declared locally for maximum avoidance of default
-- binding and vcomponents version issues.
----------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin
OB <= In_bus;
----------------------------------------------------------------------------
-- Inferred implementation.
----------------------------------------------------------------------------
INFERRED_GEN : if USE_INFERRED generate
begin
Or_out <= or_reduce(OB);
end generate INFERRED_GEN;
----------------------------------------------------------------------------
-- Structural implementation.
----------------------------------------------------------------------------
STRUCTURAL_A_GEN : if USE_STRUCTURAL_A generate
constant NUM_LUTS : positive := ((OB'length + lut_size - 1) / lut_size);
signal cy : std_logic_vector(0 to NUM_LUTS);
begin
--
cy(0) <= '0';
--
GEN : for i in 0 to NUM_LUTS-1 generate
signal lut : std_logic;
begin
lut <= not or_reduce(OB(i*lut_size to
min((i+1)*lut_size-1, OB'right))); -- The min
-- function catches the case where one LUT
-- is partial (i.e., not all inputs are used).
--
I_MUXCY : component MUXCY
port map (O =>cy(NUM_LUTS - i),
CI=>cy(NUM_LUTS - 1 - i),
DI=>'1',
S =>lut);
-- Note on cy handling: As done here, the partial LUT, if any,
-- is placed at the start of the cy chain.
end generate;
--
Or_out <= cy(NUM_LUTS);
--
end generate STRUCTURAL_A_GEN;
end implementation;
|
mit
|
HighlandersFRC/fpga
|
oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_gpio_0_0/fifo_generator_v11_0/ramfifo/dc_ss_fwft.vhd
|
19
|
9156
|
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`protect end_protected
|
mit
|
HighlandersFRC/fpga
|
oled_project/oled_project.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/fifo_generator_v11_0/common/shft_ram.vhd
|
19
|
17157
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10960)
`protect data_block
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`protect end_protected
|
mit
|
HighlandersFRC/fpga
|
led_string_no_gpio/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_auto_pc_15/fifo_generator_v11_0/fifo_generator_v11_0.vhd
|
19
|
89172
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64272)
`protect data_block
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`protect end_protected
|
mit
|
HighlandersFRC/fpga
|
led_string_no_gpio/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/fifo_generator_v11_0/fifo_generator_v11_0.vhd
|
19
|
89172
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64272)
`protect data_block
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RhyseN5T0EQLEIARXK5Ictc0rLqpgTkLSxyGYRNP7ReV
`protect end_protected
|
mit
|
HighlandersFRC/fpga
|
led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_axi_bram_ctrl_0_0/proc_common_v4_0/hdl/src/vhdl/srl_fifo2.vhd
|
15
|
14428
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo2.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo2 - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo2.vhd
--
-- Description: same as srl_fifo except the Addr port has the correct bit
-- ordering, there is a true FIFO_Empty port, and the C_DEPTH
-- generic actually controlls how many elements the fifo will
-- hold (up to 16). includes an assertion statement to check
-- that C_DEPTH is less than or equal to 16. changed
-- C_DATA_BITS to C_DWIDTH and changed it from natural to
-- positive (the width should be 1 or greater, zero width
-- didn't make sense to me!). Changed C_DEPTH from natural
-- to positive (zero elements doesn't make sense).
-- The Addr port in srl_fifo has the bits reversed which
-- made it more difficult to use. C_DEPTH was not used in
-- srl_fifo. Data_Exists is delayed by one clock so it is
-- not usefull for generating an empty flag. FIFO_Empty is
-- generated directly from the address, the same way that
-- FIFO_Full is generated.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo2.vhd
--
-------------------------------------------------------------------------------
-- Author: jam
--
-- History:
-- jam 02/20/02 First Version - modified from original srl_fifo
--
-- DCW 2002-03-12 Structural implementation of synchronous reset for
-- Data_Exists DFF (using FDR)
-- jam 04/12/02 Added C_XON generic for mixed vhdl/verilog sims
--
-- als 2002-04-18 added default for XON generic in SRL16E, FDRE, and FDR
-- component declarations
-- jam 2002-05-01 changed FIFO_Empty output from buffer_Empty, which had a
-- clock delay, to the not of data_Exists_I, which doesn't
-- have any delay
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
library unisim;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; -- conv_std_logic_vector
use unisim.all;
entity srl_fifo2 is
generic (
C_DWIDTH : positive := 8; -- changed to positive
C_DEPTH : positive := 16; -- changed to positive
C_XON : boolean := false -- added for mixed mode sims
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic; -- new port
Data_Exists : out std_logic;
Addr : out std_logic_vector(0 to 3)
);
end entity srl_fifo2;
architecture imp of srl_fifo2 is
-- convert C_DEPTH to a std_logic_vector so FIFO_Full can be generated
-- based on the selected depth rather than fixed at 16
constant DEPTH : std_logic_vector(0 to 3) :=
conv_std_logic_vector(C_DEPTH-1,4);
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
-- component LUT4
-- generic(
-- INIT : bit_vector := X"0000"
-- );
-- port (
-- O : out std_logic;
-- I0 : in std_logic;
-- I1 : in std_logic;
-- I2 : in std_logic;
-- I3 : in std_logic);
-- end component;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDRE;
component FDR is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDR;
signal addr_i : std_logic_vector(0 to 3);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic;
signal data_Exists_I : std_logic;
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to 3);
signal sum_A : std_logic_vector(0 to 3);
signal addr_cy : std_logic_vector(0 to 4);
begin -- architecture IMP
-- C_DEPTH is positive so that ensures the fifo is at least 1 element deep
-- make sure it is not greater than 16 locations deep
-- pragma translate_off
assert C_DEPTH <= 16
report "SRL Fifo's must be 16 or less elements deep"
severity FAILURE;
-- pragma translate_on
-- since srl16 address is 3 downto 0 need to compare individual bits
-- didn't muck with addr_i since the basic addressing works - Addr output
-- is generated correctly below
buffer_Full <= '1' when (addr_i(0) = DEPTH(3) and
addr_i(1) = DEPTH(2) and
addr_i(2) = DEPTH(1) and
addr_i(3) = DEPTH(0)
) else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (addr_i = "0000") else '0';
FIFO_Empty <= not data_Exists_I; -- generate a true empty flag with no delay
-- was buffer_Empty, which had a clock dly
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
Data_Exists_DFF : FDR
port map (
Q => data_Exists_I, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists, -- [in std_logic]
R => Reset); -- [in std_logic]
Data_Exists <= data_Exists_I;
valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
addr_cy(0) <= valid_Write;
Addr_Counters : for I in 0 to 3 generate
hsum_A(I) <= (FIFO_Read xor addr_i(I)) and (FIFO_Write or not buffer_Empty);
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => sum_A(I)); -- [out std_logic]
FDRE_I : FDRE
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_I, -- [in std_logic]
D => sum_A(I), -- [in std_logic]
R => Reset); -- [in std_logic]
end generate Addr_Counters;
FIFO_RAM : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i(0), -- [in std_logic]
A1 => addr_i(1), -- [in std_logic]
A2 => addr_i(2), -- [in std_logic]
A3 => addr_i(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
-------------------------------------------------------------------------------
-- INT_ADDR_PROCESS
-------------------------------------------------------------------------------
-- This process assigns the internal address to the output port
-------------------------------------------------------------------------------
-- modified the process to flip the bits since the address bits from the
-- srl16 are 3 downto 0 and Addr needs to be 0 to 3
INT_ADDR_PROCESS:process (addr_i)
begin -- process
for i in Addr'range
loop
Addr(i) <= addr_i(3 - i); -- flip the bits to account for srl16 addr
end loop;
end process;
end architecture imp;
|
mit
|
HighlandersFRC/fpga
|
led_string/led_string.srcs/sources_1/bd/zynq_1/ip/zynq_1_proc_sys_reset_1_0/proc_common_v4_0/hdl/src/vhdl/srl_fifo2.vhd
|
15
|
14428
|
-------------------------------------------------------------------------------
-- $Id: srl_fifo2.vhd,v 1.1.4.1 2010/09/14 22:35:47 dougt Exp $
-------------------------------------------------------------------------------
-- srl_fifo2 - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo2.vhd
--
-- Description: same as srl_fifo except the Addr port has the correct bit
-- ordering, there is a true FIFO_Empty port, and the C_DEPTH
-- generic actually controlls how many elements the fifo will
-- hold (up to 16). includes an assertion statement to check
-- that C_DEPTH is less than or equal to 16. changed
-- C_DATA_BITS to C_DWIDTH and changed it from natural to
-- positive (the width should be 1 or greater, zero width
-- didn't make sense to me!). Changed C_DEPTH from natural
-- to positive (zero elements doesn't make sense).
-- The Addr port in srl_fifo has the bits reversed which
-- made it more difficult to use. C_DEPTH was not used in
-- srl_fifo. Data_Exists is delayed by one clock so it is
-- not usefull for generating an empty flag. FIFO_Empty is
-- generated directly from the address, the same way that
-- FIFO_Full is generated.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo2.vhd
--
-------------------------------------------------------------------------------
-- Author: jam
--
-- History:
-- jam 02/20/02 First Version - modified from original srl_fifo
--
-- DCW 2002-03-12 Structural implementation of synchronous reset for
-- Data_Exists DFF (using FDR)
-- jam 04/12/02 Added C_XON generic for mixed vhdl/verilog sims
--
-- als 2002-04-18 added default for XON generic in SRL16E, FDRE, and FDR
-- component declarations
-- jam 2002-05-01 changed FIFO_Empty output from buffer_Empty, which had a
-- clock delay, to the not of data_Exists_I, which doesn't
-- have any delay
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
library unisim;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all; -- conv_std_logic_vector
use unisim.all;
entity srl_fifo2 is
generic (
C_DWIDTH : positive := 8; -- changed to positive
C_DEPTH : positive := 16; -- changed to positive
C_XON : boolean := false -- added for mixed mode sims
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic; -- new port
Data_Exists : out std_logic;
Addr : out std_logic_vector(0 to 3)
);
end entity srl_fifo2;
architecture imp of srl_fifo2 is
-- convert C_DEPTH to a std_logic_vector so FIFO_Full can be generated
-- based on the selected depth rather than fixed at 16
constant DEPTH : std_logic_vector(0 to 3) :=
conv_std_logic_vector(C_DEPTH-1,4);
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
-- component LUT4
-- generic(
-- INIT : bit_vector := X"0000"
-- );
-- port (
-- O : out std_logic;
-- I0 : in std_logic;
-- I1 : in std_logic;
-- I2 : in std_logic;
-- I3 : in std_logic);
-- end component;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDRE;
component FDR is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDR;
signal addr_i : std_logic_vector(0 to 3);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic;
signal data_Exists_I : std_logic;
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to 3);
signal sum_A : std_logic_vector(0 to 3);
signal addr_cy : std_logic_vector(0 to 4);
begin -- architecture IMP
-- C_DEPTH is positive so that ensures the fifo is at least 1 element deep
-- make sure it is not greater than 16 locations deep
-- pragma translate_off
assert C_DEPTH <= 16
report "SRL Fifo's must be 16 or less elements deep"
severity FAILURE;
-- pragma translate_on
-- since srl16 address is 3 downto 0 need to compare individual bits
-- didn't muck with addr_i since the basic addressing works - Addr output
-- is generated correctly below
buffer_Full <= '1' when (addr_i(0) = DEPTH(3) and
addr_i(1) = DEPTH(2) and
addr_i(2) = DEPTH(1) and
addr_i(3) = DEPTH(0)
) else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (addr_i = "0000") else '0';
FIFO_Empty <= not data_Exists_I; -- generate a true empty flag with no delay
-- was buffer_Empty, which had a clock dly
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
Data_Exists_DFF : FDR
port map (
Q => data_Exists_I, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists, -- [in std_logic]
R => Reset); -- [in std_logic]
Data_Exists <= data_Exists_I;
valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
addr_cy(0) <= valid_Write;
Addr_Counters : for I in 0 to 3 generate
hsum_A(I) <= (FIFO_Read xor addr_i(I)) and (FIFO_Write or not buffer_Empty);
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => sum_A(I)); -- [out std_logic]
FDRE_I : FDRE
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_I, -- [in std_logic]
D => sum_A(I), -- [in std_logic]
R => Reset); -- [in std_logic]
end generate Addr_Counters;
FIFO_RAM : for I in 0 to C_DWIDTH-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i(0), -- [in std_logic]
A1 => addr_i(1), -- [in std_logic]
A2 => addr_i(2), -- [in std_logic]
A3 => addr_i(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
-------------------------------------------------------------------------------
-- INT_ADDR_PROCESS
-------------------------------------------------------------------------------
-- This process assigns the internal address to the output port
-------------------------------------------------------------------------------
-- modified the process to flip the bits since the address bits from the
-- srl16 are 3 downto 0 and Addr needs to be 0 to 3
INT_ADDR_PROCESS:process (addr_i)
begin -- process
for i in Addr'range
loop
Addr(i) <= addr_i(3 - i); -- flip the bits to account for srl16 addr
end loop;
end process;
end architecture imp;
|
mit
|
pdt/ttask
|
test/modelsim/lib/tbmsgs/src/tbmsgs.vhdl
|
2
|
1716
|
--------------------------------------------------------------------------------
--
-- tbmsgs.vhdl
--
-- Testbench messages
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package tbmsgs is
procedure testcase(
constant desc : in string;
constant count : in natural);
procedure check(
constant good : in boolean;
constant desc : in string);
procedure tested(
constant desc : in string);
procedure testcase_complete;
end;
package body tbmsgs is
shared variable total_tests : natural := 0;
shared variable total_errors : integer := 0;
shared variable completed_tests : natural := 0;
procedure testcase(
constant desc : in string;
constant count : in natural) is
begin
report "|tbmsgs| *** running test case: " & desc;
total_tests := count;
end procedure;
procedure check(
constant good : in boolean;
constant desc : in string) is
begin
if not good then
report "|tbmsgs| ERROR: " & desc;
total_errors := total_errors + 1;
end if;
end procedure;
procedure tested(
constant desc : in string) is
begin
report "|tbmsgs| tested: " & desc;
completed_tests := completed_tests + 1;
end procedure;
procedure testcase_complete is
begin
report "|tbmsgs| tests run: " & integer'image(completed_tests) &
"/" & integer'image(total_tests) & ", errors: " &
integer'image(total_errors);
end procedure;
end;
|
mit
|
IamVNIE/Hardware-Security
|
PUF Lab/Students_PUFS/puf_lab_mos283_ad3572/benes8.vhd
|
2
|
3296
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:34:19 04/24/2017
-- Design Name:
-- Module Name: benes8 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity benes8 is
Port ( a : in STD_LOGIC_VECTOR (7 downto 0);
sel : in STD_LOGIC_VECTOR (19 downto 0);
b : out STD_LOGIC_VECTOR (7 downto 0));
end benes8;
architecture Behavioral of benes8 is
signal a2, a1, ab, b1, b2 : STD_LOGIC_VECTOR (7 downto 0);
component sw2x2
port (
in0: in std_logic;
in1: in std_logic;
out0: out std_logic;
out1: out std_logic;
sel: in std_logic);
end component;
begin
st2a1 : sw2x2 port map(in0 => a(7), in1 => a(3), out0 => a2(7), out1 => a2(3), sel => sel(19) );
st2a2 : sw2x2 port map(in0 => a(6), in1 => a(2), out0 => a2(6), out1 => a2(2), sel => sel(18) );
st2a3 : sw2x2 port map(in0 => a(5), in1 => a(1), out0 => a2(5), out1 => a2(1), sel => sel(17) );
st2a4 : sw2x2 port map(in0 => a(4), in1 => a(0), out0 => a2(4), out1 => a2(0), sel => sel(16) );
st1a1 : sw2x2 port map(in0 => a2(7), in1 => a2(5), out0 => a1(7), out1 => a1(5), sel => sel(15) );
st1a2 : sw2x2 port map(in0 => a2(6), in1 => a2(4), out0 => a1(6), out1 => a1(4), sel => sel(14) );
st1a3 : sw2x2 port map(in0 => a2(3), in1 => a2(1), out0 => a1(3), out1 => a1(1), sel => sel(13) );
st1a4 : sw2x2 port map(in0 => a2(2), in1 => a2(0), out0 => a1(2), out1 => a1(0), sel => sel(12) );
st01 : sw2x2 port map(in0 => a1(7), in1 => a1(6), out0 => ab(7), out1 => ab(6), sel => sel(11) );
st02 : sw2x2 port map(in0 => a1(5), in1 => a1(4), out0 => ab(5), out1 => ab(4), sel => sel(10) );
st03 : sw2x2 port map(in0 => a1(3), in1 => a1(2), out0 => ab(3), out1 => ab(2), sel => sel(9) );
st04 : sw2x2 port map(in0 => a1(1), in1 => a1(0), out0 => ab(1), out1 => ab(0), sel => sel(8) );
st2b1 : sw2x2 port map(in0 => ab(7), in1 => ab(5), out0 => b1(7), out1 => b1(5), sel => sel(7) );
st2b2 : sw2x2 port map(in0 => ab(6), in1 => ab(4), out0 => b1(6), out1 => b1(4), sel => sel(6) );
st2b3 : sw2x2 port map(in0 => ab(3), in1 => ab(1), out0 => b1(3), out1 => b1(1), sel => sel(5) );
st2b4 : sw2x2 port map(in0 => ab(2), in1 => ab(0), out0 => b1(2), out1 => b1(0), sel => sel(4) );
st1b1 : sw2x2 port map(in0 => b1(7), in1 => b1(3), out0 => b(7), out1 => b(3), sel => sel(3) );
st1b2 : sw2x2 port map(in0 => b1(6), in1 => b1(2), out0 => b(6), out1 => b(2), sel => sel(2) );
st1b3 : sw2x2 port map(in0 => b1(5), in1 => b1(1), out0 => b(5), out1 => b(1), sel => sel(1) );
st1b4 : sw2x2 port map(in0 => b1(4), in1 => b1(0), out0 => b(4), out1 => b(0), sel => sel(0) );
end Behavioral;
|
mit
|
capitanov/Stupid_watch
|
src/rtl/game_cores/cl_check.vhd
|
1
|
4399
|
--------------------------------------------------------------------------------
--
-- Title : cl_check.vhd
-- Design : Example
-- Author : Kapitanov
-- Company : InSys
--
-- Version : 1.0
--------------------------------------------------------------------------------
--
-- Description : Game block for square 8x8
--
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity cl_check is
generic(
constant yend : std_logic_vector(4 downto 0); --! Y end area
constant ystart : std_logic_vector(4 downto 0); --! Y start area
constant xend : std_logic_vector(6 downto 0); --! X end area
constant xstart : std_logic_vector(6 downto 0) --! X start area
);
port(
-- system signals:
clk : in std_logic; --! clock
reset : in std_logic; --! system reset
-- vga XoY coordinates:
cnt_yy : in std_logic_vector(2 downto 0); --! counter for Y data
cnt_xx : in std_logic_vector(2 downto 0); --! counter for X data
--data_hide : in std_logic;
display : in std_logic; --! display enable
x_char : in std_logic_vector(9 downto 0); --! X line: 0:79
y_char : in std_logic_vector(8 downto 0); --! Y line: 0:29
-- out color scheme:
rgb : out std_logic_vector(2 downto 0) --! RGB Colour
);
end cl_check;
architecture cl_check of cl_check is
signal data_rom : std_logic_vector(7 downto 0);
signal x_in : std_logic_vector(6 downto 0);
signal y_in : std_logic_vector(4 downto 0);
signal data : std_logic;
signal x_rev : std_logic_vector(2 downto 0);
signal x_del : std_logic_vector(2 downto 0);
signal y_charz : std_logic_vector(3 downto 0);
constant color : std_logic_vector(2 downto 0):="111";
signal comp_yy : std_logic_vector(3 downto 0);
signal comp_xx : std_logic_vector(3 downto 0);
signal data_x, data_y : std_logic;
begin
---------------- stage 1: Get XoY ----------------
y_charz <= y_char(3 downto 0) when rising_edge(clk);
g_rev: for ii in 0 to 2 generate
begin
x_rev(ii) <= not x_char(ii) when rising_edge(clk);
end generate;
x_del <= x_rev when rising_edge(clk);
comp_yy <= '0' & cnt_yy;
comp_xx <= '0' & cnt_xx;
x_in <= x_char(9 downto 3);
y_in <= y_char(8 downto 4);
---------------- stage 2: Convert XY ----------------
pr_select: process(clk, reset) is
begin
if reset = '0' then
data_x <= '0';
data_y <= '0';
elsif rising_edge(clk) then
if display = '1' then
if (x_in = (xstart + comp_xx)) then
data_x <= '1';
else
data_x <= '0';
end if;
if (y_in = (ystart + comp_yy)) then
data_y <= '1';
else
data_y <= '0';
end if;
else
data_x <= '0';
data_y <= '0';
end if;
end if;
end process;
---------------- stage 3: Data ROM ----------------
pr_new_box: process(clk, reset)
begin
if reset = '0' then
data_rom <= x"00";
elsif rising_edge(clk) then
if (data_x = '1' and data_y = '1') then
case y_charz(3 downto 0) is
when x"0" => data_rom <= x"FF";
when x"1" => data_rom <= x"81";
when x"2" => data_rom <= x"81";
when x"3" => data_rom <= x"81";
when x"4" => data_rom <= x"81";
when x"5" => data_rom <= x"81";
when x"6" => data_rom <= x"81";
when x"7" => data_rom <= x"81";
when x"8" => data_rom <= x"81";
when x"9" => data_rom <= x"81";
when x"A" => data_rom <= x"81";
when x"B" => data_rom <= x"81";
when x"C" => data_rom <= x"81";
when x"D" => data_rom <= x"83";
when x"E" => data_rom <= x"87";
when others => data_rom <= x"FF";
end case;
else
data_rom <= x"00";
end if;
end if;
end process;
---------------- stage 4: RGB DATA ----------------
pr_sw_sel: process(clk, reset) is
begin
if reset = '0' then
data <= '0';
elsif rising_edge(clk) then
data <= data_rom(to_integer(unsigned(x_del)));
end if;
end process;
g_rgb: for ii in 0 to 2 generate
begin
rgb(ii) <= data and color(ii);
end generate;
end cl_check;
|
mit
|
laurocruz/snakes_vhdl
|
demo_make_map/demo_make_map.vhd
|
1
|
610
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY snake_lib;
USE snake_lib.snake_pack.all;
ENTITY demo_make_map IS
GENERIC (N : INTEGER := 10;
M : INTEGER := 10;
INITIAL_SIZE : INTEGER := 2);
PORT (clock : IN STD_LOGIC;
reset : IN STD_LOGIC;
eaten : STD_LOGIC;
snake_size : IN INTEGER RANGE 0 TO N*M;
dir : IN STD_LOGIC_VECTOR(1 DOWNTO 0));
END demo_make_map;
ARCHITECTURE Behavior OF demo_make_map IS
SIGNAL snake_body : int_array;
BEGIN
make_map1: make_map PORT MAP (clock, reset, eaten, snake_size, dir, snake_body);
END Behavior;
|
mit
|
kucherenko/jscpd
|
fixtures/vhdl/file2.vhd
|
12226531
|
0
|
mit
|
|
VerkhovtsovPavel/BSUIR_Labs
|
Master/POCP/My_Designs/GPR/src/DPATH.vhd
|
1
|
1698
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library gpr;
use gpr.OneHotGPR.all;
entity DPATH is
port(
EN: in std_logic;
-- operation type
OT: in operation;
-- operand 1
OP1: in operand;
-- operand 2
OP2: in operand;
-- result
RES: out operand;
-- zero flag
ZF: out std_logic
);
end DPATH;
architecture Beh_GPR of DPATH is
signal res_g: operand;
signal res_add: operand;
signal res_sub: operand;
signal res_shift: operand;
signal res_copy: operand;
signal t_zf: std_logic;
Begin
res_add <= CONV_STD_LOGIC_VECTOR(CONV_INTEGER(OP1) + CONV_INTEGER(OP2), 16);
res_sub <= CONV_STD_LOGIC_VECTOR(CONV_INTEGER(OP1) - CONV_INTEGER(OP2), 16);
res_copy <= OP1;
REGA: process (EN, OT, OP1, res_add, res_sub, res_shift, res_copy)
begin
if rising_edge(EN) then
case OT is
when ADD => res_g <= res_add;
when SUBT => res_g <= res_sub;
when SHIFT => res_g <= res_shift;
when COPY => res_g <= res_copy;
when others => null;
end case;
end if;
end process;
FLAGS: process(res_g)
begin
if res_g = (res_g'range => '0') then
t_zf <= '1';
else
t_zf <= '0';
end if;
end process;
GRAY: process(OP1)
begin
for i in 0 to 14 loop
res_shift(i) <= OP1(i) xor OP1(i+1);
end loop;
res_shift(15) <= OP1(15);
end process;
RES <= res_g;
ZF <= t_zf;
End Beh_GPR;
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ipshared/fe7d/hdl/vhdl/nco_AXILiteS_s_axi.vhd
|
2
|
9041
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.1
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity nco_AXILiteS_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 5;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
-- user signals
sine_sample_V :in STD_LOGIC_VECTOR(15 downto 0);
sine_sample_V_ap_vld :in STD_LOGIC;
step_size_V :out STD_LOGIC_VECTOR(15 downto 0));
end entity nco_AXILiteS_s_axi;
--------------------------Address Info-------------------
-- 0x00 : reserved
-- 0x04 : reserved
-- 0x08 : reserved
-- 0x0c : reserved
-- 0x10 : Data signal of sine_sample_V
-- bit 15~0 - sine_sample_V[15:0] (Read)
-- others - reserved
-- 0x14 : Control signal of sine_sample_V
-- bit 0 - sine_sample_V_ap_vld (Read/COR)
-- others - reserved
-- 0x18 : Data signal of step_size_V
-- bit 15~0 - step_size_V[15:0] (Read/Write)
-- others - reserved
-- 0x1c : reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of nco_AXILiteS_s_axi is
constant ADDR_BITS : INTEGER := 5;
constant ADDR_SINE_SAMPLE_V_DATA_0 : INTEGER :=16#10#;
constant ADDR_SINE_SAMPLE_V_CTRL : INTEGER :=16#14#;
constant ADDR_STEP_SIZE_V_DATA_0 : INTEGER :=16#18#;
constant ADDR_STEP_SIZE_V_CTRL : INTEGER :=16#1c#;
type states is (wridle, wrdata, wrresp, rdidle, rddata); -- read and write FSM states
signal wstate, wnext, rstate, rnext: states;
-- Local signal
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_sine_sample_V : UNSIGNED(15 downto 0);
signal int_sine_sample_V_ap_vld : STD_LOGIC;
signal int_step_size_V : UNSIGNED(15 downto 0);
begin
-- axi write
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wridle;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end process;
-- axi read
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdidle;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_SINE_SAMPLE_V_DATA_0 =>
rdata_data <= RESIZE(int_sine_sample_V(15 downto 0), 32);
when ADDR_SINE_SAMPLE_V_CTRL =>
rdata_data <= (0 => int_sine_sample_V_ap_vld, others => '0');
when ADDR_STEP_SIZE_V_DATA_0 =>
rdata_data <= RESIZE(int_step_size_V(15 downto 0), 32);
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end process;
-- internal registers
step_size_V <= STD_LOGIC_VECTOR(int_step_size_V);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_sine_sample_V <= (others => '0');
elsif (ACLK_EN = '1') then
if (sine_sample_V_ap_vld = '1') then
int_sine_sample_V <= UNSIGNED(sine_sample_V); -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_sine_sample_V_ap_vld <= '0';
elsif (ACLK_EN = '1') then
if (sine_sample_V_ap_vld = '1') then
int_sine_sample_V_ap_vld <= '1';
elsif (ar_hs = '1' and raddr = ADDR_SINE_SAMPLE_V_CTRL) then
int_sine_sample_V_ap_vld <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_STEP_SIZE_V_DATA_0) then
int_step_size_V(15 downto 0) <= (UNSIGNED(WDATA(15 downto 0)) and wmask(15 downto 0)) or ((not wmask(15 downto 0)) and int_step_size_V(15 downto 0));
end if;
end if;
end if;
end process;
end architecture behave;
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_1/syn/vhdl/convolve_kernel.vhd
|
4
|
40699
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.3
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convolve_kernel is
generic (
C_S_AXI_CONTROL_ADDR_WIDTH : INTEGER := 4;
C_S_AXI_CONTROL_DATA_WIDTH : INTEGER := 32 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
bufw_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_EN_A : OUT STD_LOGIC;
bufw_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_Clk_A : OUT STD_LOGIC;
bufw_Rst_A : OUT STD_LOGIC;
bufi_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_EN_A : OUT STD_LOGIC;
bufi_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_Clk_A : OUT STD_LOGIC;
bufi_Rst_A : OUT STD_LOGIC;
bufo_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_EN_A : OUT STD_LOGIC;
bufo_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufo_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufo_Clk_A : OUT STD_LOGIC;
bufo_Rst_A : OUT STD_LOGIC;
s_axi_control_AWVALID : IN STD_LOGIC;
s_axi_control_AWREADY : OUT STD_LOGIC;
s_axi_control_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_CONTROL_ADDR_WIDTH-1 downto 0);
s_axi_control_WVALID : IN STD_LOGIC;
s_axi_control_WREADY : OUT STD_LOGIC;
s_axi_control_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_CONTROL_DATA_WIDTH-1 downto 0);
s_axi_control_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_CONTROL_DATA_WIDTH/8-1 downto 0);
s_axi_control_ARVALID : IN STD_LOGIC;
s_axi_control_ARREADY : OUT STD_LOGIC;
s_axi_control_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_CONTROL_ADDR_WIDTH-1 downto 0);
s_axi_control_RVALID : OUT STD_LOGIC;
s_axi_control_RREADY : IN STD_LOGIC;
s_axi_control_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_CONTROL_DATA_WIDTH-1 downto 0);
s_axi_control_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_control_BVALID : OUT STD_LOGIC;
s_axi_control_BREADY : IN STD_LOGIC;
s_axi_control_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
interrupt : OUT STD_LOGIC );
end;
architecture behav of convolve_kernel is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"convolve_kernel,hls_ip_2017_3,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=5.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=4.353000,HLS_SYN_LAT=37942,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=5,HLS_SYN_FF=860,HLS_SYN_LUT=1412}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000000000000001";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000000000000010";
constant ap_ST_fsm_state3 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000000000000100";
constant ap_ST_fsm_state4 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000000000001000";
constant ap_ST_fsm_state5 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000000000010000";
constant ap_ST_fsm_state6 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000000000100000";
constant ap_ST_fsm_state7 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000000001000000";
constant ap_ST_fsm_state8 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000000010000000";
constant ap_ST_fsm_state9 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000000100000000";
constant ap_ST_fsm_state10 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000001000000000";
constant ap_ST_fsm_state11 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000010000000000";
constant ap_ST_fsm_state12 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000100000000000";
constant ap_ST_fsm_state13 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000001000000000000";
constant ap_ST_fsm_state14 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000010000000000000";
constant ap_ST_fsm_state15 : STD_LOGIC_VECTOR (25 downto 0) := "00000000000100000000000000";
constant ap_ST_fsm_state16 : STD_LOGIC_VECTOR (25 downto 0) := "00000000001000000000000000";
constant ap_ST_fsm_state17 : STD_LOGIC_VECTOR (25 downto 0) := "00000000010000000000000000";
constant ap_ST_fsm_state18 : STD_LOGIC_VECTOR (25 downto 0) := "00000000100000000000000000";
constant ap_ST_fsm_state19 : STD_LOGIC_VECTOR (25 downto 0) := "00000001000000000000000000";
constant ap_ST_fsm_state20 : STD_LOGIC_VECTOR (25 downto 0) := "00000010000000000000000000";
constant ap_ST_fsm_state21 : STD_LOGIC_VECTOR (25 downto 0) := "00000100000000000000000000";
constant ap_ST_fsm_state22 : STD_LOGIC_VECTOR (25 downto 0) := "00001000000000000000000000";
constant ap_ST_fsm_state23 : STD_LOGIC_VECTOR (25 downto 0) := "00010000000000000000000000";
constant ap_ST_fsm_state24 : STD_LOGIC_VECTOR (25 downto 0) := "00100000000000000000000000";
constant ap_ST_fsm_state25 : STD_LOGIC_VECTOR (25 downto 0) := "01000000000000000000000000";
constant ap_ST_fsm_state26 : STD_LOGIC_VECTOR (25 downto 0) := "10000000000000000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv32_19 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011001";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv4_F : STD_LOGIC_VECTOR (3 downto 0) := "1111";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv2_3 : STD_LOGIC_VECTOR (1 downto 0) := "11";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv6_2 : STD_LOGIC_VECTOR (5 downto 0) := "000010";
constant ap_const_lv3_5 : STD_LOGIC_VECTOR (2 downto 0) := "101";
constant ap_const_lv3_1 : STD_LOGIC_VECTOR (2 downto 0) := "001";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_rst_n_inv : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (25 downto 0) := "00000000000000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal ap_ready : STD_LOGIC;
signal row_b_cast6_cast_fu_164_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal row_b_cast6_cast_reg_454 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal row_b_cast_fu_168_p1 : STD_LOGIC_VECTOR (2 downto 0);
signal row_b_cast_reg_459 : STD_LOGIC_VECTOR (2 downto 0);
signal row_b_1_fu_178_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal row_b_1_reg_467 : STD_LOGIC_VECTOR (1 downto 0);
signal col_b_cast5_cast_fu_184_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal col_b_cast5_cast_reg_472 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_CS_fsm_state3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state3 : signal is "none";
signal col_b_cast_fu_188_p1 : STD_LOGIC_VECTOR (2 downto 0);
signal col_b_cast_reg_477 : STD_LOGIC_VECTOR (2 downto 0);
signal col_b_1_fu_198_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal col_b_1_reg_485 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_10_cast_fu_226_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_10_cast_reg_490 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_CS_fsm_state4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state4 : signal is "none";
signal tmp_11_fu_230_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_11_reg_495 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_3_fu_235_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_3_reg_501 : STD_LOGIC_VECTOR (0 downto 0);
signal to_b_1_fu_241_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal to_b_1_reg_505 : STD_LOGIC_VECTOR (1 downto 0);
signal bufo_addr_reg_510 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_CS_fsm_state5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state5 : signal is "none";
signal tmp_17_fu_292_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_17_reg_515 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_CS_fsm_state6 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state6 : signal is "none";
signal tmp_19_cast_fu_316_p1 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_19_cast_reg_520 : STD_LOGIC_VECTOR (6 downto 0);
signal ti_b_1_fu_326_p2 : STD_LOGIC_VECTOR (1 downto 0);
signal ti_b_1_reg_528 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_22_fu_357_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_22_reg_533 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_CS_fsm_state7 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state7 : signal is "none";
signal i_1_fu_369_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal i_1_reg_541 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_9_fu_375_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_9_reg_546 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_7_fu_363_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_25_fu_404_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_25_reg_551 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_CS_fsm_state8 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state8 : signal is "none";
signal bufw_addr_reg_556 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_CS_fsm_state9 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state9 : signal is "none";
signal j_1_fu_430_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal j_1_reg_564 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_27_fu_445_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_27_reg_569 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_s_fu_424_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_CS_fsm_state10 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state10 : signal is "none";
signal bufw_load_reg_579 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state11 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state11 : signal is "none";
signal bufi_load_reg_584 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_160_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_4_reg_589 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state16 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state16 : signal is "none";
signal bufo_load_reg_594 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_156_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_6_reg_599 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state25 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state25 : signal is "none";
signal row_b_reg_90 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_1_fu_192_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal col_b_reg_101 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_fu_172_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal to_b_reg_112 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_5_fu_320_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ti_b_reg_123 : STD_LOGIC_VECTOR (1 downto 0);
signal i_reg_134 : STD_LOGIC_VECTOR (2 downto 0);
signal j_reg_145 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_CS_fsm_state26 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state26 : signal is "none";
signal tmp_14_cast_fu_262_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_26_cast_fu_419_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_27_cast_fu_450_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal bufw_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state15 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state15 : signal is "none";
signal bufo_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state17 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state17 : signal is "none";
signal ap_CS_fsm_state12 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state12 : signal is "none";
signal tmp_8_fu_208_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal p_shl1_cast_fu_216_p1 : STD_LOGIC_VECTOR (4 downto 0);
signal to_b_cast4_cast_fu_204_p1 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_10_fu_220_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_12_fu_247_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_13_fu_252_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_14_fu_257_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal ti_b_cast3_cast_fu_267_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_15_fu_271_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_16_fu_280_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_15_cast_fu_276_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal p_shl3_fu_288_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_18_fu_298_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal p_shl2_cast_fu_306_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_19_fu_310_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal i_cast2_fu_332_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_20_fu_336_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_24_fu_345_p1 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_21_fu_341_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal p_shl4_cast_fu_349_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_9_cast_cast_fu_380_p1 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_23_fu_383_p2 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_28_fu_392_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal p_shl5_cast_fu_396_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_23_cast_fu_388_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal j_cast1_cast_fu_410_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_26_fu_414_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_2_fu_436_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_2_cast_cast_fu_441_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (25 downto 0);
component convolve_kernel_fbkb IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component convolve_kernel_fcud IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component convolve_kernel_control_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC );
end component;
begin
convolve_kernel_control_s_axi_U : component convolve_kernel_control_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_CONTROL_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_CONTROL_DATA_WIDTH)
port map (
AWVALID => s_axi_control_AWVALID,
AWREADY => s_axi_control_AWREADY,
AWADDR => s_axi_control_AWADDR,
WVALID => s_axi_control_WVALID,
WREADY => s_axi_control_WREADY,
WDATA => s_axi_control_WDATA,
WSTRB => s_axi_control_WSTRB,
ARVALID => s_axi_control_ARVALID,
ARREADY => s_axi_control_ARREADY,
ARADDR => s_axi_control_ARADDR,
RVALID => s_axi_control_RVALID,
RREADY => s_axi_control_RREADY,
RDATA => s_axi_control_RDATA,
RRESP => s_axi_control_RRESP,
BVALID => s_axi_control_BVALID,
BREADY => s_axi_control_BREADY,
BRESP => s_axi_control_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => ap_const_logic_1,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle);
convolve_kernel_fbkb_U1 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 9,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => bufo_load_reg_594,
din1 => tmp_4_reg_589,
ce => ap_const_logic_1,
dout => grp_fu_156_p2);
convolve_kernel_fcud_U2 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => bufw_load_reg_579,
din1 => bufi_load_reg_584,
ce => ap_const_logic_1,
dout => grp_fu_160_p2);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
col_b_reg_101_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_const_lv1_0 = tmp_fu_172_p2))) then
col_b_reg_101 <= ap_const_lv2_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state5) and (tmp_3_reg_501 = ap_const_lv1_1))) then
col_b_reg_101 <= col_b_1_reg_485;
end if;
end if;
end process;
i_reg_134_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state6) and (ap_const_lv1_0 = tmp_5_fu_320_p2))) then
i_reg_134 <= ap_const_lv3_0;
elsif (((tmp_s_fu_424_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state9))) then
i_reg_134 <= i_1_reg_541;
end if;
end if;
end process;
j_reg_145_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state8)) then
j_reg_145 <= ap_const_lv3_0;
elsif ((ap_const_logic_1 = ap_CS_fsm_state26)) then
j_reg_145 <= j_1_reg_564;
end if;
end if;
end process;
row_b_reg_90_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((tmp_1_fu_192_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
row_b_reg_90 <= row_b_1_reg_467;
elsif (((ap_start = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
row_b_reg_90 <= ap_const_lv2_0;
end if;
end if;
end process;
ti_b_reg_123_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state5) and (tmp_3_reg_501 = ap_const_lv1_0))) then
ti_b_reg_123 <= ap_const_lv2_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state7) and (tmp_7_fu_363_p2 = ap_const_lv1_1))) then
ti_b_reg_123 <= ti_b_1_reg_528;
end if;
end if;
end process;
to_b_reg_112_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state3) and (ap_const_lv1_0 = tmp_1_fu_192_p2))) then
to_b_reg_112 <= ap_const_lv2_0;
elsif (((ap_const_lv1_1 = tmp_5_fu_320_p2) and (ap_const_logic_1 = ap_CS_fsm_state6))) then
to_b_reg_112 <= to_b_1_reg_505;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state11)) then
bufi_load_reg_584 <= bufi_Dout_A;
bufw_load_reg_579 <= bufw_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state5)) then
bufo_addr_reg_510 <= tmp_14_cast_fu_262_p1(5 - 1 downto 0);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state16)) then
bufo_load_reg_594 <= bufo_Dout_A;
tmp_4_reg_589 <= grp_fu_160_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state9)) then
bufw_addr_reg_556 <= tmp_26_cast_fu_419_p1(8 - 1 downto 0);
j_1_reg_564 <= j_1_fu_430_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state3)) then
col_b_1_reg_485 <= col_b_1_fu_198_p2;
col_b_cast5_cast_reg_472(1 downto 0) <= col_b_cast5_cast_fu_184_p1(1 downto 0);
col_b_cast_reg_477(1 downto 0) <= col_b_cast_fu_188_p1(1 downto 0);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state7)) then
i_1_reg_541 <= i_1_fu_369_p2;
tmp_22_reg_533 <= tmp_22_fu_357_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
row_b_1_reg_467 <= row_b_1_fu_178_p2;
row_b_cast6_cast_reg_454(1 downto 0) <= row_b_cast6_cast_fu_164_p1(1 downto 0);
row_b_cast_reg_459(1 downto 0) <= row_b_cast_fu_168_p1(1 downto 0);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state6)) then
ti_b_1_reg_528 <= ti_b_1_fu_326_p2;
tmp_17_reg_515 <= tmp_17_fu_292_p2;
tmp_19_cast_reg_520 <= tmp_19_cast_fu_316_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state4)) then
tmp_10_cast_reg_490 <= tmp_10_cast_fu_226_p1;
tmp_11_reg_495 <= tmp_11_fu_230_p2;
tmp_3_reg_501 <= tmp_3_fu_235_p2;
to_b_1_reg_505 <= to_b_1_fu_241_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state8)) then
tmp_25_reg_551 <= tmp_25_fu_404_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state9) and (ap_const_lv1_0 = tmp_s_fu_424_p2))) then
tmp_27_reg_569 <= tmp_27_fu_445_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_CS_fsm_state25)) then
tmp_6_reg_599 <= grp_fu_156_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state7) and (tmp_7_fu_363_p2 = ap_const_lv1_0))) then
tmp_9_reg_546 <= tmp_9_fu_375_p2;
end if;
end if;
end process;
row_b_cast6_cast_reg_454(5 downto 2) <= "0000";
row_b_cast_reg_459(2) <= '0';
col_b_cast5_cast_reg_472(5 downto 2) <= "0000";
col_b_cast_reg_477(2) <= '0';
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, ap_CS_fsm_state2, ap_CS_fsm_state3, tmp_3_reg_501, ap_CS_fsm_state5, ap_CS_fsm_state6, ap_CS_fsm_state7, tmp_7_fu_363_p2, ap_CS_fsm_state9, tmp_s_fu_424_p2, tmp_1_fu_192_p2, tmp_fu_172_p2, tmp_5_fu_320_p2)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_start = ap_const_logic_1) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((ap_const_lv1_1 = tmp_fu_172_p2) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_state3;
end if;
when ap_ST_fsm_state3 =>
if (((tmp_1_fu_192_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state3))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state4;
end if;
when ap_ST_fsm_state4 =>
ap_NS_fsm <= ap_ST_fsm_state5;
when ap_ST_fsm_state5 =>
if (((ap_const_logic_1 = ap_CS_fsm_state5) and (tmp_3_reg_501 = ap_const_lv1_1))) then
ap_NS_fsm <= ap_ST_fsm_state3;
else
ap_NS_fsm <= ap_ST_fsm_state6;
end if;
when ap_ST_fsm_state6 =>
if (((ap_const_lv1_1 = tmp_5_fu_320_p2) and (ap_const_logic_1 = ap_CS_fsm_state6))) then
ap_NS_fsm <= ap_ST_fsm_state4;
else
ap_NS_fsm <= ap_ST_fsm_state7;
end if;
when ap_ST_fsm_state7 =>
if (((ap_const_logic_1 = ap_CS_fsm_state7) and (tmp_7_fu_363_p2 = ap_const_lv1_1))) then
ap_NS_fsm <= ap_ST_fsm_state6;
else
ap_NS_fsm <= ap_ST_fsm_state8;
end if;
when ap_ST_fsm_state8 =>
ap_NS_fsm <= ap_ST_fsm_state9;
when ap_ST_fsm_state9 =>
if (((tmp_s_fu_424_p2 = ap_const_lv1_1) and (ap_const_logic_1 = ap_CS_fsm_state9))) then
ap_NS_fsm <= ap_ST_fsm_state7;
else
ap_NS_fsm <= ap_ST_fsm_state10;
end if;
when ap_ST_fsm_state10 =>
ap_NS_fsm <= ap_ST_fsm_state11;
when ap_ST_fsm_state11 =>
ap_NS_fsm <= ap_ST_fsm_state12;
when ap_ST_fsm_state12 =>
ap_NS_fsm <= ap_ST_fsm_state13;
when ap_ST_fsm_state13 =>
ap_NS_fsm <= ap_ST_fsm_state14;
when ap_ST_fsm_state14 =>
ap_NS_fsm <= ap_ST_fsm_state15;
when ap_ST_fsm_state15 =>
ap_NS_fsm <= ap_ST_fsm_state16;
when ap_ST_fsm_state16 =>
ap_NS_fsm <= ap_ST_fsm_state17;
when ap_ST_fsm_state17 =>
ap_NS_fsm <= ap_ST_fsm_state18;
when ap_ST_fsm_state18 =>
ap_NS_fsm <= ap_ST_fsm_state19;
when ap_ST_fsm_state19 =>
ap_NS_fsm <= ap_ST_fsm_state20;
when ap_ST_fsm_state20 =>
ap_NS_fsm <= ap_ST_fsm_state21;
when ap_ST_fsm_state21 =>
ap_NS_fsm <= ap_ST_fsm_state22;
when ap_ST_fsm_state22 =>
ap_NS_fsm <= ap_ST_fsm_state23;
when ap_ST_fsm_state23 =>
ap_NS_fsm <= ap_ST_fsm_state24;
when ap_ST_fsm_state24 =>
ap_NS_fsm <= ap_ST_fsm_state25;
when ap_ST_fsm_state25 =>
ap_NS_fsm <= ap_ST_fsm_state26;
when ap_ST_fsm_state26 =>
ap_NS_fsm <= ap_ST_fsm_state9;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXX";
end case;
end process;
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state10 <= ap_CS_fsm(9);
ap_CS_fsm_state11 <= ap_CS_fsm(10);
ap_CS_fsm_state12 <= ap_CS_fsm(11);
ap_CS_fsm_state15 <= ap_CS_fsm(14);
ap_CS_fsm_state16 <= ap_CS_fsm(15);
ap_CS_fsm_state17 <= ap_CS_fsm(16);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_CS_fsm_state25 <= ap_CS_fsm(24);
ap_CS_fsm_state26 <= ap_CS_fsm(25);
ap_CS_fsm_state3 <= ap_CS_fsm(2);
ap_CS_fsm_state4 <= ap_CS_fsm(3);
ap_CS_fsm_state5 <= ap_CS_fsm(4);
ap_CS_fsm_state6 <= ap_CS_fsm(5);
ap_CS_fsm_state7 <= ap_CS_fsm(6);
ap_CS_fsm_state8 <= ap_CS_fsm(7);
ap_CS_fsm_state9 <= ap_CS_fsm(8);
ap_done_assign_proc : process(ap_CS_fsm_state2, tmp_fu_172_p2)
begin
if (((ap_const_lv1_1 = tmp_fu_172_p2) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state2, tmp_fu_172_p2)
begin
if (((ap_const_lv1_1 = tmp_fu_172_p2) and (ap_const_logic_1 = ap_CS_fsm_state2))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
bufi_Addr_A <= std_logic_vector(shift_left(unsigned(bufi_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufi_Addr_A_orig <= tmp_27_cast_fu_450_p1(32 - 1 downto 0);
bufi_Clk_A <= ap_clk;
bufi_Din_A <= ap_const_lv32_0;
bufi_EN_A_assign_proc : process(ap_CS_fsm_state10)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state10)) then
bufi_EN_A <= ap_const_logic_1;
else
bufi_EN_A <= ap_const_logic_0;
end if;
end process;
bufi_Rst_A <= ap_rst_n_inv;
bufi_WEN_A <= ap_const_lv4_0;
bufo_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufo_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bufo_addr_reg_510),32));
bufo_Clk_A <= ap_clk;
bufo_Din_A <= tmp_6_reg_599;
bufo_EN_A_assign_proc : process(ap_CS_fsm_state26, ap_CS_fsm_state15)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state15) or (ap_const_logic_1 = ap_CS_fsm_state26))) then
bufo_EN_A <= ap_const_logic_1;
else
bufo_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_Rst_A <= ap_rst_n_inv;
bufo_WEN_A_assign_proc : process(ap_CS_fsm_state26)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state26)) then
bufo_WEN_A <= ap_const_lv4_F;
else
bufo_WEN_A <= ap_const_lv4_0;
end if;
end process;
bufw_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(bufw_addr_reg_556),32));
bufw_Clk_A <= ap_clk;
bufw_Din_A <= ap_const_lv32_0;
bufw_EN_A_assign_proc : process(ap_CS_fsm_state10)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state10)) then
bufw_EN_A <= ap_const_logic_1;
else
bufw_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_Rst_A <= ap_rst_n_inv;
bufw_WEN_A <= ap_const_lv4_0;
col_b_1_fu_198_p2 <= std_logic_vector(unsigned(col_b_reg_101) + unsigned(ap_const_lv2_1));
col_b_cast5_cast_fu_184_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(col_b_reg_101),6));
col_b_cast_fu_188_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(col_b_reg_101),3));
i_1_fu_369_p2 <= std_logic_vector(unsigned(ap_const_lv3_1) + unsigned(i_reg_134));
i_cast2_fu_332_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(i_reg_134),64));
j_1_fu_430_p2 <= std_logic_vector(unsigned(j_reg_145) + unsigned(ap_const_lv3_1));
j_cast1_cast_fu_410_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(j_reg_145),9));
p_shl1_cast_fu_216_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_8_fu_208_p3),5));
p_shl2_cast_fu_306_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_18_fu_298_p3),6));
p_shl3_fu_288_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_16_fu_280_p3),64));
p_shl4_cast_fu_349_p3 <= (tmp_24_fu_345_p1 & ap_const_lv2_0);
p_shl5_cast_fu_396_p3 <= (tmp_28_fu_392_p1 & ap_const_lv3_0);
row_b_1_fu_178_p2 <= std_logic_vector(unsigned(row_b_reg_90) + unsigned(ap_const_lv2_1));
row_b_cast6_cast_fu_164_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(row_b_reg_90),6));
row_b_cast_fu_168_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(row_b_reg_90),3));
ti_b_1_fu_326_p2 <= std_logic_vector(unsigned(ti_b_reg_123) + unsigned(ap_const_lv2_1));
ti_b_cast3_cast_fu_267_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ti_b_reg_123),6));
tmp_10_cast_fu_226_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_10_fu_220_p2),6));
tmp_10_fu_220_p2 <= std_logic_vector(unsigned(p_shl1_cast_fu_216_p1) - unsigned(to_b_cast4_cast_fu_204_p1));
tmp_11_fu_230_p2 <= std_logic_vector(unsigned(row_b_cast6_cast_reg_454) + unsigned(tmp_10_cast_fu_226_p1));
tmp_12_fu_247_p2 <= std_logic_vector(shift_left(unsigned(tmp_11_reg_495),to_integer(unsigned('0' & ap_const_lv6_2(6-1 downto 0)))));
tmp_13_fu_252_p2 <= std_logic_vector(unsigned(tmp_12_fu_247_p2) - unsigned(tmp_11_reg_495));
tmp_14_cast_fu_262_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_14_fu_257_p2),64));
tmp_14_fu_257_p2 <= std_logic_vector(unsigned(col_b_cast5_cast_reg_472) + unsigned(tmp_13_fu_252_p2));
tmp_15_cast_fu_276_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_15_fu_271_p2),64));
tmp_15_fu_271_p2 <= std_logic_vector(signed(tmp_10_cast_reg_490) + signed(ti_b_cast3_cast_fu_267_p1));
tmp_16_fu_280_p3 <= (tmp_15_fu_271_p2 & ap_const_lv2_0);
tmp_17_fu_292_p2 <= std_logic_vector(signed(tmp_15_cast_fu_276_p1) + signed(p_shl3_fu_288_p1));
tmp_18_fu_298_p3 <= (ti_b_reg_123 & ap_const_lv3_0);
tmp_19_cast_fu_316_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_19_fu_310_p2),7));
tmp_19_fu_310_p2 <= std_logic_vector(unsigned(p_shl2_cast_fu_306_p1) - unsigned(ti_b_cast3_cast_fu_267_p1));
tmp_1_fu_192_p2 <= "1" when (col_b_reg_101 = ap_const_lv2_3) else "0";
tmp_20_fu_336_p2 <= std_logic_vector(unsigned(tmp_17_reg_515) + unsigned(i_cast2_fu_332_p1));
tmp_21_fu_341_p1 <= tmp_20_fu_336_p2(9 - 1 downto 0);
tmp_22_fu_357_p2 <= std_logic_vector(unsigned(tmp_21_fu_341_p1) + unsigned(p_shl4_cast_fu_349_p3));
tmp_23_cast_fu_388_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_23_fu_383_p2),9));
tmp_23_fu_383_p2 <= std_logic_vector(unsigned(tmp_9_cast_cast_fu_380_p1) + unsigned(tmp_19_cast_reg_520));
tmp_24_fu_345_p1 <= tmp_20_fu_336_p2(7 - 1 downto 0);
tmp_25_fu_404_p2 <= std_logic_vector(unsigned(p_shl5_cast_fu_396_p3) - unsigned(tmp_23_cast_fu_388_p1));
tmp_26_cast_fu_419_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_26_fu_414_p2),64));
tmp_26_fu_414_p2 <= std_logic_vector(unsigned(tmp_22_reg_533) + unsigned(j_cast1_cast_fu_410_p1));
tmp_27_cast_fu_450_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_27_reg_569),64));
tmp_27_fu_445_p2 <= std_logic_vector(unsigned(tmp_25_reg_551) + unsigned(tmp_2_cast_cast_fu_441_p1));
tmp_28_fu_392_p1 <= tmp_23_fu_383_p2(6 - 1 downto 0);
tmp_2_cast_cast_fu_441_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_2_fu_436_p2),9));
tmp_2_fu_436_p2 <= std_logic_vector(unsigned(col_b_cast_reg_477) + unsigned(j_reg_145));
tmp_3_fu_235_p2 <= "1" when (to_b_reg_112 = ap_const_lv2_3) else "0";
tmp_5_fu_320_p2 <= "1" when (ti_b_reg_123 = ap_const_lv2_3) else "0";
tmp_7_fu_363_p2 <= "1" when (i_reg_134 = ap_const_lv3_5) else "0";
tmp_8_fu_208_p3 <= (to_b_reg_112 & ap_const_lv2_0);
tmp_9_cast_cast_fu_380_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_9_reg_546),7));
tmp_9_fu_375_p2 <= std_logic_vector(unsigned(i_reg_134) + unsigned(row_b_cast_reg_459));
tmp_fu_172_p2 <= "1" when (row_b_reg_90 = ap_const_lv2_3) else "0";
tmp_s_fu_424_p2 <= "1" when (j_reg_145 = ap_const_lv3_5) else "0";
to_b_1_fu_241_p2 <= std_logic_vector(unsigned(ap_const_lv2_1) + unsigned(to_b_reg_112));
to_b_cast4_cast_fu_204_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(to_b_reg_112),5));
end behav;
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ipshared/f86a/hdl/proc_sys_reset_v5_0_vh_rfs.vhd
|
7
|
71590
|
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- upcnt_n - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: upcnt_n.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/07/01 -- First Release
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SIZE -- Number of bits in counter
--
--
-- Definition of Ports:
-- Data -- parallel data input
-- Cnt_en -- count enable
-- Load -- Load Data
-- Clr -- reset
-- Clk -- Clock
-- Qout -- Count output
--
-------------------------------------------------------------------------------
entity upcnt_n is
generic(
C_SIZE : Integer
);
port(
Data : in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
Cnt_en : in STD_LOGIC;
Load : in STD_LOGIC;
Clr : in STD_LOGIC;
Clk : in STD_LOGIC;
Qout : out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
);
end upcnt_n;
architecture imp of upcnt_n is
constant CLEAR : std_logic := '0';
signal q_int : UNSIGNED (C_SIZE-1 downto 0) := (others => '1');
begin
process(Clk)
begin
if (Clk'event) and Clk = '1' then
-- Clear output register
if (Clr = CLEAR) then
q_int <= (others => '0');
-- Load in start value
elsif (Load = '1') then
q_int <= UNSIGNED(Data);
-- If count enable is high
elsif Cnt_en = '1' then
q_int <= q_int + 1;
end if;
end if;
end process;
Qout <= STD_LOGIC_VECTOR(q_int);
end imp;
-------------------------------------------------------------------------------
-- sequence - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
-- -- proc_sys_reset.vhd
-- -- upcnt_n.vhd
-- -- lpf.vhd
-- -- sequence.vhd
-------------------------------------------------------------------------------
-- Filename: sequence.vhd
--
-- Description:
-- This file control the sequencing coming out of a reset.
-- The sequencing is as follows:
-- Bus_Struct_Reset comes out of reset first. Either when the
-- external or auxiliary reset goes inactive or 16 clocks
-- after a PPC Chip_Reset_Request, or 30 clocks after a PPC
-- System_Reset_Request.
-- Peripheral_Reset comes out of reset 16 clocks after
-- Bus_Struct_Reset.
-- The PPC resetcore, comes out of reset
-- 16 clocks after Peripheral_Reset.
-- The PPC resetchip and resetsystem come out of reset
-- at the same time as Bus_Struct_Reset.
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/12/01 -- First Release
-- LC Whittle 10/11/2004 -- Update for NCSim
-- rolandp 04/16/2007 -- v2.00a
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_12;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- Lpf_reset -- Low Pass Filtered in
-- System_Reset_Req -- System Reset Request
-- Chip_Reset_Req -- Chip Reset Request
-- Slowest_Sync_Clk -- Clock
-- Bsr_out -- Bus Structure Reset out
-- Pr_out -- Peripheral Reset out
-- Core_out -- Core reset out
-- Chip_out -- Chip reset out
-- Sys_out -- System reset out
-- MB_out -- MB reset out
--
-------------------------------------------------------------------------------
entity sequence_psr is
port(
Lpf_reset : in std_logic;
-- System_Reset_Req : in std_logic;
-- Chip_Reset_Req : in std_logic;
Slowest_Sync_Clk : in std_logic;
Bsr_out : out std_logic;
Pr_out : out std_logic;
-- Core_out : out std_logic;
-- Chip_out : out std_logic;
-- Sys_out : out std_logic;
MB_out : out std_logic
);
end sequence_psr;
architecture imp of sequence_psr is
constant CLEAR : std_logic := '0';
constant BSR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "001100"; -- 12
constant BSR_END_SYS : std_logic_vector(5 downto 0) := "011001"; -- 25
constant PR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "011100"; -- 28
constant PR_END_SYS : std_logic_vector(5 downto 0) := "101001"; -- 41
constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100"; -- 44
constant CORE_END_SYS : std_logic_vector(5 downto 0) := "111001"; -- 57
constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant CHIP_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
constant SYS_END_LPF : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant SYS_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
signal bsr : std_logic := '1';
signal bsr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal pr : std_logic := '1';
signal pr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Core : std_logic := '1';
signal core_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Chip : std_logic := '0';
signal chip_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Sys : std_logic := '0';
signal sys_dec : std_logic_vector(2 downto 0) := (others => '0');
signal chip_Reset_Req_d1 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d2 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d3 : std_logic := '0'; -- delayed Chip_Reset_Req
signal system_Reset_Req_d1 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d2 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d3 : std_logic := '0'; -- delayed System_Reset_Req
signal seq_cnt : std_logic_vector(5 downto 0);
signal seq_cnt_en : std_logic := '0';
signal seq_clr : std_logic := '0';
signal ris_edge : std_logic := '0';
signal sys_edge : std_logic := '0';
signal from_sys : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
Pr_out <= pr;
Bsr_out <= bsr;
MB_out <= core;
-- Core_out <= core;
-- Chip_out <= chip or sys;
-- Sys_out <= sys;
-------------------------------------------------------------------------------
-- This process remembers that the reset was caused be
-- System_Reset_Req
-------------------------------------------------------------------------------
SYS_FROM_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if Lpf_reset='1' or system_reset_req_d3='1' then
if (Lpf_reset = '1') then
from_sys <= '1';
--elsif Chip_Reset_Req_d3='1' then
-- from_sys <= '0';
elsif (Core = '0') then
from_sys <='0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This instantiates a counter to control the sequencing
-------------------------------------------------------------------------------
SEQ_COUNTER : entity proc_sys_reset_v5_0_12.UPCNT_N
generic map (C_SIZE => 6)
port map(
Data => "000000",
Cnt_en => seq_cnt_en,
Load => '0',
Clr => seq_clr,
Clk => Slowest_sync_clk,
Qout => seq_cnt
);
-------------------------------------------------------------------------------
-- SEQ_CNT_EN_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
-- count until all outputs are inactive
-------------------------------------------------------------------------------
SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (Lpf_reset='1' --or
--System_Reset_Req_d3='1' or
--Chip_Reset_Req_d3='1' or
--ris_edge = '1'
) then
seq_cnt_en <= '1';
elsif (Core='0') then -- Core always present and always last
seq_cnt_en <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- SEQ_CLR_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset to the sequence counter
-- Clear the counter on a rising edge of chip or system request or low pass
-- filter output
-------------------------------------------------------------------------------
SEQ_CLR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
seq_clr <= '0';
else
seq_clr <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
PR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
pr <= '1';
elsif (pr_dec(2) = '1') then
pr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
PR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3) and from_sys = '1')
) then
pr_dec(0) <= '1';
else
pr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1')
)then
pr_dec(1) <= '1';
else
pr_dec(1) <= '0';
end if;
pr_dec(2) <= pr_dec(1) and pr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Bus_Struct_Reset output signal
-------------------------------------------------------------------------------
BSR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
bsr <= '1';
elsif (bsr_dec(2) = '1') then
bsr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for BSR to use
-------------------------------------------------------------------------------
BSR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1')
)then
bsr_dec(0) <= '1';
else
bsr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1')
)then
bsr_dec(1) <= '1';
else
bsr_dec(1) <= '0';
end if;
bsr_dec(2) <= bsr_dec(1) and bsr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
CORE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
core <= '1';
elsif (core_dec(2) = '1') then
core <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
CORE_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1')
)then
core_dec(0) <= '1';
else
core_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1')
)then
core_dec(1) <= '1';
else
core_dec(1) <= '0';
end if;
core_dec(2) <= core_dec(1) and core_dec(0);
end if;
end process;
---------------------------------------------------------------------------------
---- This process defines the Chip output signal
---------------------------------------------------------------------------------
-- CHIP_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- -- if ris_edge = '1' or Lpf_reset = '1' then
-- if Lpf_reset = '1' then
-- chip <= '1';
-- elsif chip_dec(2) = '1' then
-- chip <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Chip to use
---- sys is overlapping the chip reset and thus no need to decode this here
---------------------------------------------------------------------------------
-- CHIP_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2)) then
-- chip_dec(0) <= '1';
-- else
-- chip_dec(0) <= '0';
-- end if;
-- if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then
-- chip_dec(1) <= '1';
-- else
-- chip_dec(1) <= '0';
-- end if;
-- chip_dec(2) <= chip_dec(1) and chip_dec(0);
-- end if;
-- end process;
---------------------------------------------------------------------------------
---- This process defines the Sys output signal
---------------------------------------------------------------------------------
-- SYS_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if sys_edge = '1' or Lpf_reset = '1' then
-- sys <= '1';
-- elsif sys_dec(2) = '1' then
-- sys <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Sys to use
---------------------------------------------------------------------------------
-- SYS_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or
-- (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1') then
-- sys_dec(0) <= '1';
-- else
-- sys_dec(0) <= '0';
-- end if;
-- if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or
-- (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1') then
-- sys_dec(1) <= '1';
-- else
-- sys_dec(1) <= '0';
-- end if;
-- sys_dec(2) <= sys_dec(1) and sys_dec(0);
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---------------------------------------------------------------------------------
-- DELAY_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- chip_reset_req_d1 <= Chip_Reset_Req ;
-- chip_reset_req_d2 <= chip_Reset_Req_d1 ;
-- chip_reset_req_d3 <= chip_Reset_Req_d2 ;
-- system_reset_req_d1 <= System_Reset_Req;
-- system_reset_req_d2 <= system_Reset_Req_d1;
-- system_reset_req_d3 <= system_Reset_Req_d2;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of either
-- Chip_Reset_Req or System_Reset_Req
-------------------------------------------------------------------------------
-- RIS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (chip_reset_req_d3='0' and chip_Reset_Req_d2= '1') -- rising edge
-- or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then
-- ris_edge <= '1';
-- else
-- ris_edge <='0';
-- end if;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of
-- System_Reset_Req
-------------------------------------------------------------------------------
-- SYS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (system_reset_req_d3='0' and system_reset_req_d2='1') then
-- sys_edge <= '1';
-- else
-- sys_edge <='0';
-- end if;
-- end if;
-- end process;
end architecture imp;
-------------------------------------------------------------------------------
-- lpf - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: lpf.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/08/01 -- First Release
--
-- KC 02/25/2002 -- Added Dcm_locked as an input
-- -- Added Power on reset srl_time_out
--
-- KC 08/26/2003 -- Added attribute statements for power on
-- reset SRL
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library lib_cdc_v1_0_2;
--use lib_cdc_v1_0_2.all;
library Unisim;
use Unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting
-- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting
-- C_EXT_RESET_HIGH -- External Reset Active High or Active Low
-- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low
--
-- Definition of Ports:
-- Slowest_sync_clk -- Clock
-- External_System_Reset -- External Reset Input
-- Auxiliary_System_Reset -- Auxiliary Reset Input
-- Dcm_locked -- DCM Locked, hold system in reset until 1
-- Lpf_reset -- Low Pass Filtered Output
--
-------------------------------------------------------------------------------
entity lpf is
generic(
C_EXT_RST_WIDTH : Integer;
C_AUX_RST_WIDTH : Integer;
C_EXT_RESET_HIGH : std_logic;
C_AUX_RESET_HIGH : std_logic
);
port(
MB_Debug_Sys_Rst : in std_logic;
Dcm_locked : in std_logic;
External_System_Reset : in std_logic;
Auxiliary_System_Reset : in std_logic;
Slowest_Sync_Clk : in std_logic;
Lpf_reset : out std_logic
);
end lpf;
architecture imp of lpf is
component SRL16 is
-- synthesis translate_off
generic (
INIT : bit_vector );
-- synthesis translate_on
port (D : in std_logic;
CLK : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16;
constant CLEAR : std_logic := '0';
signal exr_d1 : std_logic := '0'; -- delayed External_System_Reset
signal exr_lpf : std_logic_vector(0 to C_EXT_RST_WIDTH - 1)
:= (others => '0'); -- LPF DFF
signal asr_d1 : std_logic := '0'; -- delayed Auxiliary_System_Reset
signal asr_lpf : std_logic_vector(0 to C_AUX_RST_WIDTH - 1)
:= (others => '0'); -- LPF DFF
signal exr_and : std_logic := '0'; -- varible input width "and" gate
signal exr_nand : std_logic := '0'; -- vaiable input width "and" gate
signal asr_and : std_logic := '0'; -- varible input width "and" gate
signal asr_nand : std_logic := '0'; -- vaiable input width "and" gate
signal lpf_int : std_logic := '0'; -- internal Lpf_reset
signal lpf_exr : std_logic := '0';
signal lpf_asr : std_logic := '0';
signal srl_time_out : std_logic;
attribute INIT : string;
attribute INIT of POR_SRL_I: label is "FFFF";
begin
Lpf_reset <= lpf_int;
-------------------------------------------------------------------------------
-- Power On Reset Generation
-------------------------------------------------------------------------------
-- This generates a reset for the first 16 clocks after a power up
-------------------------------------------------------------------------------
POR_SRL_I: SRL16
-- synthesis translate_off
generic map (
INIT => X"FFFF")
-- synthesis translate_on
port map (
D => '0',
CLK => Slowest_sync_clk,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
Q => srl_time_out);
-------------------------------------------------------------------------------
-- LPF_OUTPUT_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
--
--ACTIVE_HIGH_LPF_EXT: if (C_EXT_RESET_HIGH = '1') generate
--begin
LPF_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
lpf_int <= lpf_exr or lpf_asr or srl_time_out or not Dcm_locked;
end if;
end process LPF_OUTPUT_PROCESS;
--end generate ACTIVE_HIGH_LPF_EXT;
--ACTIVE_LOW_LPF_EXT: if (C_EXT_RESET_HIGH = '0') generate
--begin
--LPF_OUTPUT_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- lpf_int <= not (lpf_exr or
-- lpf_asr or
-- srl_time_out)or
-- not Dcm_locked;
-- end if;
-- end process;
--end generate ACTIVE_LOW_LPF_EXT;
EXR_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if exr_and = '1' then
lpf_exr <= '1';
elsif (exr_and = '0' and exr_nand = '1') then
lpf_exr <= '0';
end if;
end if;
end process EXR_OUTPUT_PROCESS;
ASR_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if asr_and = '1' then
lpf_asr <= '1';
elsif (asr_and = '0' and asr_nand = '1') then
lpf_asr <= '0';
end if;
end if;
end process ASR_OUTPUT_PROCESS;
-------------------------------------------------------------------------------
-- This If-generate selects an active high input for External System Reset
-------------------------------------------------------------------------------
ACTIVE_HIGH_EXT: if (C_EXT_RESET_HIGH /= '0') generate
begin
-----------------------------------
exr_d1 <= External_System_Reset or MB_Debug_Sys_Rst;
ACT_HI_EXT: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => exr_d1,
prmry_ack => open,
scndry_out => exr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-----------------------------------
end generate ACTIVE_HIGH_EXT;
-------------------------------------------------------------------------------
-- This If-generate selects an active low input for External System Reset
-------------------------------------------------------------------------------
ACTIVE_LOW_EXT: if (C_EXT_RESET_HIGH = '0') generate
begin
exr_d1 <= not External_System_Reset or MB_Debug_Sys_Rst;
-------------------------------------
ACT_LO_EXT: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => exr_d1,
prmry_ack => open,
scndry_out => exr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_LOW_EXT;
-------------------------------------------------------------------------------
-- This If-generate selects an active high input for Auxiliary System Reset
-------------------------------------------------------------------------------
ACTIVE_HIGH_AUX: if (C_AUX_RESET_HIGH /= '0') generate
begin
asr_d1 <= Auxiliary_System_Reset;
-------------------------------------
ACT_HI_AUX: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => asr_d1,
prmry_ack => open,
scndry_out => asr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_HIGH_AUX;
-------------------------------------------------------------------------------
-- This If-generate selects an active low input for Auxiliary System Reset
-------------------------------------------------------------------------------
ACTIVE_LOW_AUX: if (C_AUX_RESET_HIGH = '0') generate
begin
-------------------------------------
asr_d1 <= not Auxiliary_System_Reset;
ACT_LO_AUX: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => asr_d1,
prmry_ack => open,
scndry_out => asr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_LOW_AUX;
-------------------------------------------------------------------------------
-- This For-generate creates the low pass filter D-Flip Flops
-------------------------------------------------------------------------------
EXT_LPF: for i in 1 to C_EXT_RST_WIDTH - 1 generate
begin
----------------------------------------
EXT_LPF_DFF : process (Slowest_Sync_Clk)
begin
if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then
exr_lpf(i) <= exr_lpf(i-1);
end if;
end process;
----------------------------------------
end generate EXT_LPF;
------------------------------------------------------------------------------------------
-- Implement the 'AND' function on the for the LPF
------------------------------------------------------------------------------------------
EXT_LPF_AND : process (exr_lpf)
Variable loop_and : std_logic;
Variable loop_nand : std_logic;
Begin
loop_and := '1';
loop_nand := '1';
for j in 0 to C_EXT_RST_WIDTH - 1 loop
loop_and := loop_and and exr_lpf(j);
loop_nand := loop_nand and not exr_lpf(j);
End loop;
exr_and <= loop_and;
exr_nand <= loop_nand;
end process;
-------------------------------------------------------------------------------
-- This For-generate creates the low pass filter D-Flip Flops
-------------------------------------------------------------------------------
AUX_LPF: for k in 1 to C_AUX_RST_WIDTH - 1 generate
begin
----------------------------------------
AUX_LPF_DFF : process (Slowest_Sync_Clk)
begin
if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then
asr_lpf(k) <= asr_lpf(k-1);
end if;
end process;
----------------------------------------
end generate AUX_LPF;
------------------------------------------------------------------------------------------
-- Implement the 'AND' function on the for the LPF
------------------------------------------------------------------------------------------
AUX_LPF_AND : process (asr_lpf)
Variable aux_loop_and : std_logic;
Variable aux_loop_nand : std_logic;
Begin
aux_loop_and := '1';
aux_loop_nand := '1';
for m in 0 to C_AUX_RST_WIDTH - 1 loop
aux_loop_and := aux_loop_and and asr_lpf(m);
aux_loop_nand := aux_loop_nand and not asr_lpf(m);
End loop;
asr_and <= aux_loop_and;
asr_nand <= aux_loop_nand;
end process;
end imp;
-------------------------------------------------------------------------------
-- proc_sys_reset - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: rolandp
-- History:
-- kc 11/07/01 -- First version
--
-- kc 02/25/2002 -- Changed generic names C_EXT_RST_ACTIVE to
-- C_EXT_RESET_HIGH and C_AUX_RST_ACTIVE to
-- C_AUX_RESET_HIGH to match generics used in
-- MicroBlaze. Added the DCM Lock as an input
-- to keep reset active until after the Lock
-- is valid.
-- lcw 10/11/2004 -- Updated for NCSim
-- Ravi 09/14/2006 -- Added Attributes for synthesis
-- rolandp 04/16/2007 -- version 2.00a
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-- ~~~~~~~
-- SK 05/12/11
-- ^^^^^^^
-- 1. Updated the core so remove the support for PPC related functionality.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_12;
use proc_sys_reset_v5_0_12.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting
-- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting
-- C_EXT_RESET_HIGH -- External Reset Active High or Active Low
-- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low
-- C_NUM_BUS_RST -- Number of Bus Structures reset to generate
-- C_NUM_PERP_RST -- Number of Peripheral resets to generate
--
-- C_NUM_INTERCONNECT_ARESETN -- No. of Active low reset to interconnect
-- C_NUM_PERP_ARESETN -- No. of Active low reset to peripheral
-- Definition of Ports:
-- slowest_sync_clk -- Clock
-- ext_reset_in -- External Reset Input
-- aux_reset_in -- Auxiliary Reset Input
-- mb_debug_sys_rst -- MDM Reset Input
-- dcm_locked -- DCM Locked, hold system in reset until 1
-- mb_reset -- MB core reset out
-- bus_struct_reset -- Bus structure reset out
-- peripheral_reset -- Peripheral reset out
-- interconnect_aresetn -- Interconnect Bus structure registered rst out
-- peripheral_aresetn -- Active Low Peripheral registered reset out
-------------------------------------------------------------------------------
entity proc_sys_reset is
generic (
C_FAMILY : string := "virtex7";
C_EXT_RST_WIDTH : integer := 4;
C_AUX_RST_WIDTH : integer := 4;
C_EXT_RESET_HIGH : std_logic := '0'; -- High active input
C_AUX_RESET_HIGH : std_logic := '1'; -- High active input
C_NUM_BUS_RST : integer := 1;
C_NUM_PERP_RST : integer := 1;
C_NUM_INTERCONNECT_ARESETN : integer := 1; -- 3/15/2010
C_NUM_PERP_ARESETN : integer := 1 -- 3/15/2010
);
port (
slowest_sync_clk : in std_logic;
ext_reset_in : in std_logic;
aux_reset_in : in std_logic;
-- from MDM
mb_debug_sys_rst : in std_logic;
-- DCM locked information
dcm_locked : in std_logic := '1';
-- -- from PPC
-- Core_Reset_Req_0 : in std_logic;
-- Chip_Reset_Req_0 : in std_logic;
-- System_Reset_Req_0 : in std_logic;
-- Core_Reset_Req_1 : in std_logic;
-- Chip_Reset_Req_1 : in std_logic;
-- System_Reset_Req_1 : in std_logic;
-- RstcPPCresetcore_0 : out std_logic := '0';
-- RstcPPCresetchip_0 : out std_logic := '0';
-- RstcPPCresetsys_0 : out std_logic := '0';
-- RstcPPCresetcore_1 : out std_logic := '0';
-- RstcPPCresetchip_1 : out std_logic := '0';
-- RstcPPCresetsys_1 : out std_logic := '0';
-- to Microblaze active high reset
mb_reset : out std_logic;
-- active high resets
bus_struct_reset : out std_logic_vector(0 to C_NUM_BUS_RST - 1)
:= (others => '0');
peripheral_reset : out std_logic_vector(0 to C_NUM_PERP_RST - 1)
:= (others => '0');
-- active low resets
interconnect_aresetn : out
std_logic_vector(0 to (C_NUM_INTERCONNECT_ARESETN-1))
:= (others => '1');
peripheral_aresetn : out std_logic_vector(0 to (C_NUM_PERP_ARESETN-1))
:= (others => '1')
);
end entity proc_sys_reset;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of proc_sys_reset is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-- signal Core_Reset_Req_0_d1 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_0_d2 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_0_d3 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d1 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d2 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d3 : std_logic := '0'; -- delayed Core_Reset_Req
constant T : std_logic := C_EXT_RESET_HIGH;
signal core_cnt_en_0 : std_logic := '0'; -- Core_Reset_Req_0 counter enable
signal core_cnt_en_1 : std_logic := '0'; -- Core_Reset_Req_1 counter enable
signal core_req_edge_0 : std_logic := '1'; -- Rising edge of Core_Reset_Req_0
signal core_req_edge_1 : std_logic := '1'; -- Rising edge of Core_Reset_Req_1
signal core_cnt_0 : std_logic_vector(3 downto 0); -- core counter output
signal core_cnt_1 : std_logic_vector(3 downto 0); -- core counter output
signal lpf_reset : std_logic; -- Low pass filtered ext or aux
--signal Chip_Reset_Req : std_logic := '0';
--signal System_Reset_Req : std_logic := '0';
signal Bsr_out : std_logic;
signal Pr_out : std_logic;
-- signal Core_out : std_logic;
-- signal Chip_out : std_logic;
-- signal Sys_out : std_logic;
signal MB_out : std_logic := C_EXT_RESET_HIGH;
signal MB_out1 : std_logic := C_EXT_RESET_HIGH;
signal pr_outn : std_logic;
signal bsr_outn : std_logic;
-------------------------------------------------------------------------------
-- Attributes to synthesis
-------------------------------------------------------------------------------
attribute equivalent_register_removal: string;
attribute equivalent_register_removal of bus_struct_reset : signal is "no";
attribute equivalent_register_removal of peripheral_reset : signal is "no";
attribute equivalent_register_removal of interconnect_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_aresetn : signal is "no";
begin
-------------------------------------------------------------------------------
-- ---------------------
-- -- MB_RESET_HIGH_GEN: Generate active high reset for Micro-Blaze
-- ---------------------
-- MB_RESET_HIGH_GEN: if C_INT_RESET_HIGH = 1 generate
-- begin
-- mb_reset <= MB_out1;
-- MB_Reset_PROCESS1: process (slowest_sync_clk)
-- begin
-- if (slowest_sync_clk'event and slowest_sync_clk = '1') then
-- MB_out1 <= MB_out;
-- end if;
-- end process;
FDRE_inst : FDRE
generic map (
INIT => '1') -- Initial value of register ('0' or '1')
port map (
Q => mb_reset, -- Data output
C => slowest_sync_clk, -- Clock input
CE => '1', -- Clock enable input
R => '0', -- Synchronous reset input
D => MB_out -- Data input
);
-- ----------------------------------------------------------------------------
-- -- This For-generate creates D-Flip Flops for the Bus_Struct_Reset output(s)
-- ----------------------------------------------------------------------------
BSR_OUT_DFF: for i in 0 to (C_NUM_BUS_RST-1) generate
FDRE_BSR : FDRE
generic map (
INIT => '1') -- Initial value of register ('0' or '1')
port map (
Q => bus_struct_reset(i), -- Data output
C => slowest_sync_clk, -- Clock input
CE => '1', -- Clock enable input
R => '0', -- Synchronous reset input
D => Bsr_out -- Data input
);
-- BSR_DFF : process (slowest_sync_clk)
-- begin
-- if (slowest_sync_clk'event and slowest_sync_clk = '1') then
-- bus_struct_reset(i) <= Bsr_out;
-- end if;
-- end process;
end generate BSR_OUT_DFF;
-- ---------------------------------------------------------------------------
-- This For-generate creates D-Flip Flops for the Interconnect_aresetn op(s)
-- ---------------------------------------------------------------------------
bsr_outn <= not(Bsr_out);
ACTIVE_LOW_BSR_OUT_DFF: for i in 0 to (C_NUM_INTERCONNECT_ARESETN-1) generate
FDRE_BSR_N : FDRE
generic map (
INIT => '0') -- Initial value of register ('0' or '1')
port map (
Q => interconnect_aresetn(i), -- Data output
C => slowest_sync_clk, -- Clock input
CE => '1', -- Clock enable input
R => '0', -- Synchronous reset input
D => bsr_outn -- Data input
);
-- BSR_DFF : process (slowest_sync_clk)
-- begin
-- if (slowest_sync_clk'event and slowest_sync_clk = '1') then
-- interconnect_aresetn(i) <= not (Bsr_out);
-- end if;
-- end process;
end generate ACTIVE_LOW_BSR_OUT_DFF;
-------------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
-- -- This For-generate creates D-Flip Flops for the Peripheral_Reset output(s)
-- ----------------------------------------------------------------------------
PR_OUT_DFF: for i in 0 to (C_NUM_PERP_RST-1) generate
FDRE_PER : FDRE
generic map (
INIT => '1') -- Initial value of register ('0' or '1')
port map (
Q => peripheral_reset(i), -- Data output
C => slowest_sync_clk, -- Clock input
CE => '1', -- Clock enable input
R => '0', -- Synchronous reset input
D => Pr_out -- Data input
);
-- PR_DFF : process (slowest_sync_clk)
-- begin
-- if (slowest_sync_clk'event and slowest_sync_clk = '1') then
-- peripheral_reset(i) <= Pr_out;
-- end if;
-- end process;
end generate PR_OUT_DFF;
-- ----------------------------------------------------------------------------
-- This For-generate creates D-Flip Flops for the Peripheral_aresetn op(s)
-- ---A-------------------------------------------------------------------------
pr_outn <= not(Pr_out);
ACTIVE_LOW_PR_OUT_DFF: for i in 0 to (C_NUM_PERP_ARESETN-1) generate
FDRE_PER_N : FDRE
generic map (
INIT => '0') -- Initial value of register ('0' or '1')
port map (
Q => peripheral_aresetn(i), -- Data output
C => slowest_sync_clk, -- Clock input
CE => '1', -- Clock enable input
R => '0', -- Synchronous reset input
D => Pr_outn -- Data input
);
-- ACTIVE_LOW_PR_DFF : process (slowest_sync_clk)
-- begin
-- if (slowest_sync_clk'event and slowest_sync_clk = '1') then
-- peripheral_aresetn(i) <= not(Pr_out);
-- end if;
-- end process;
end generate ACTIVE_LOW_PR_OUT_DFF;
-------------------------------------------------------------------------------
-- This process defines the RstcPPCreset and MB_Reset outputs
-------------------------------------------------------------------------------
-- Rstc_output_PROCESS_0: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- RstcPPCresetcore_0 <= not (core_cnt_0(3) and core_cnt_0(2) and
-- core_cnt_0(1) and core_cnt_0(0))
-- or Core_out;
-- RstcPPCresetchip_0 <= Chip_out;
-- RstcPPCresetsys_0 <= Sys_out;
-- end if;
-- end process;
-- Rstc_output_PROCESS_1: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- RstcPPCresetcore_1 <= not (core_cnt_1(3) and core_cnt_1(2) and
-- core_cnt_1(1) and core_cnt_1(0))
-- or Core_out;
-- RstcPPCresetchip_1 <= Chip_out;
-- RstcPPCresetsys_1 <= Sys_out;
-- end if;
-- end process;
-------------------------------------------------------------------------------
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---- Double register to sync up with slowest_sync_clk
---------------------------------------------------------------------------------
-- DELAY_PROCESS_0: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- core_reset_req_0_d1 <= Core_Reset_Req_0;
-- core_reset_req_0_d2 <= core_reset_req_0_d1;
-- core_reset_req_0_d3 <= core_reset_req_0_d2;
-- end if;
-- end process;
--
-- DELAY_PROCESS_1: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- core_reset_req_1_d1 <= Core_Reset_Req_1;
-- core_reset_req_1_d2 <= core_reset_req_1_d1;
-- core_reset_req_1_d3 <= core_reset_req_1_d2;
-- end if;
-- end process;
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- This instantiates a counter to ensure the Core_Reset_Req_* will genereate a
-- ** -- -- RstcPPCresetcore_* that is a mimimum of 15 clocks
-- ** -- -------------------------------------------------------------------------------
-- ** -- CORE_RESET_0 : entity proc_sys_reset_v5_0_12.UPCNT_N
-- ** -- generic map (C_SIZE => 4)
-- ** -- port map(
-- ** -- Data => "0000", -- in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
-- ** -- Cnt_en => core_cnt_en_0, -- in STD_LOGIC;
-- ** -- Load => '0', -- in STD_LOGIC;
-- ** -- Clr => core_req_edge_0, -- in STD_LOGIC;
-- ** -- Clk => Slowest_sync_clk, -- in STD_LOGIC;
-- ** -- Qout => core_cnt_0 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
-- ** -- );
-- ** --
-- ** -- CORE_RESET_1 : entity proc_sys_reset_v5_0_12.UPCNT_N
-- ** -- generic map (C_SIZE => 4)
-- ** -- port map(
-- ** -- Data => "0000", -- in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
-- ** -- Cnt_en => core_cnt_en_1, -- in STD_LOGIC;
-- ** -- Load => '0', -- in STD_LOGIC;
-- ** -- Clr => core_req_edge_1, -- in STD_LOGIC;
-- ** -- Clk => Slowest_sync_clk, -- in STD_LOGIC;
-- ** -- Qout => core_cnt_1 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
-- ** -- );
-- ** --
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- CORE_RESET_PROCESS
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- This generates the reset pulse and the count enable to core reset counter
-- ** -- --
-- ** -- CORE_RESET_PROCESS_0: process (Slowest_sync_clk)
-- ** -- begin
-- ** -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- ** -- core_cnt_en_0 <= not (core_cnt_0(3) and core_cnt_0(2) and core_cnt_0(1));
-- ** -- --or not core_req_edge_0;
-- ** -- --core_req_edge_0 <= not(Core_Reset_Req_0_d2 and not Core_Reset_Req_0_d3);
-- ** -- end if;
-- ** -- end process;
-- ** --
-- ** -- CORE_RESET_PROCESS_1: process (Slowest_sync_clk)
-- ** -- begin
-- ** -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- ** -- core_cnt_en_1 <= not (core_cnt_1(3) and core_cnt_1(2) and core_cnt_1(1));
-- ** -- --or not core_req_edge_1;
-- ** -- --core_req_edge_1 <= not(Core_Reset_Req_1_d2 and not Core_Reset_Req_1_d3);
-- ** -- end if;
-- ** -- end process;
-------------------------------------------------------------------------------
-- This instantiates a low pass filter to filter both External and Auxiliary
-- Reset Inputs.
-------------------------------------------------------------------------------
EXT_LPF : entity proc_sys_reset_v5_0_12.LPF
generic map (
C_EXT_RST_WIDTH => C_EXT_RST_WIDTH,
C_AUX_RST_WIDTH => C_AUX_RST_WIDTH,
C_EXT_RESET_HIGH => C_EXT_RESET_HIGH,
C_AUX_RESET_HIGH => C_AUX_RESET_HIGH
)
port map(
MB_Debug_Sys_Rst => mb_debug_sys_rst, -- in std_logic
Dcm_locked => dcm_locked, -- in std_logic
External_System_Reset => ext_reset_in, -- in std_logic
Auxiliary_System_Reset => aux_reset_in, -- in std_logic
Slowest_Sync_Clk => slowest_sync_clk, -- in std_logic
Lpf_reset => lpf_reset -- out std_logic
);
-------------------------------------------------------------------------------
-- This instantiates the sequencer
-- This controls the time between resets becoming inactive
-------------------------------------------------------------------------------
-- System_Reset_Req <= System_Reset_Req_0 or System_Reset_Req_1;
-- Chip_Reset_Req <= Chip_Reset_Req_0 or Chip_Reset_Req_1;
SEQ : entity proc_sys_reset_v5_0_12.SEQUENCE_PSR
--generic map (
-- C_EXT_RESET_HIGH_1 => C_EXT_RESET_HIGH
--)
port map(
Lpf_reset => lpf_reset, -- in std_logic
--System_Reset_Req => '0', -- System_Reset_Req, -- in std_logic
--Chip_Reset_Req => '0', -- Chip_Reset_Req, -- in std_logic
Slowest_Sync_Clk => slowest_sync_clk, -- in std_logic
Bsr_out => Bsr_out, -- out std_logic
Pr_out => Pr_out, -- out std_logic
--Core_out => open, -- Core_out, -- out std_logic
--Chip_out => open, -- Chip_out, -- out std_logic
--Sys_out => open, -- Sys_out, -- out std_logic
MB_out => MB_out); -- out std_logic
end imp;
--END_SINGLE_FILE_TAG
|
mit
|
VerkhovtsovPavel/BSUIR_Labs
|
Labs/POCP/POCP-6/src/TB/RegFile_T.vhd
|
1
|
1694
|
library ieee;
use ieee.std_logic_1164.all;
entity RegFile_T is
end RegFile_T;
architecture Beh of RegFile_T is
component RegFile
generic (
-- èíèöèàëèçàöèÿ ðåãèñòðà ïëþñ ðàçðÿäíîé øèíû äàííûõ
INITREG: std_logic_vector := "0000";
-- ðàçðÿäíîñòü øèíû àäðåñà
a: integer := 2);
port (
-- ñèãíàë èíèöèàëèçàöèè ðåãèñòðîâ
INIT: in std_logic;
-- øèíà äàííûõ äëÿ çàïèñè
WDP: in std_logic_vector(INITREG'range);
-- øèíà àäðåñà äëÿ çàïèñè
WA: in std_logic_vector(a-1 downto 0);
-- øèíà àäðåñà äëÿ ÷òåíèÿ
RA: in std_logic_vector(a-1 downto 0);
-- ñèãíàë ðàçðåøåíèÿ çàïèñè
WE: in std_logic;
-- ïðî÷èòàííûå äàííûå
RDP: out std_logic_vector(INITREG'range));
end component;
signal init: std_logic := '0';
signal wdp: std_logic_vector(3 downto 0):= "0000";
signal wa: std_logic_vector(1 downto 0) := "00";
signal ra: std_logic_vector(1 downto 0) := "00";
signal we: std_logic := '0';
signal rdp: std_logic_vector(3 downto 0) := "0000";
constant WAIT_Period: time := 10 ns;
begin
ufile: RegFile port map (
init => init,
wdp => wdp,
wa => wa,
ra => ra,
we => we,
rdp => rdp
);
main: process
begin
wait for wait_period;
init <= '1';
wait for wait_period / 2;
init <= '0';
wdp <= "1100";
wa <= "00";
we <= '1';
wait for wait_period / 2;
we <= '0';
wdp <= "1010";
wa <= "01";
wait for wait_period / 2;
we <= '1';
wait for wait_period / 2;
we <= '0';
wait for wait_period / 2;
ra <= "00";
wait for wait_period;
ra <= "01";
wait;
end process;
end Beh;
configuration config of RegFile_T is
for Beh
for ufile : RegFile
use entity work.regfile(Beh);
end for;
end for;
end config;
|
mit
|
Nooxet/embedded_bruteforce
|
brutus_system/pcores/bajsd_v1_00_a - Copy/hdl/vhdl/hash_array_pkg.vhd
|
3
|
434
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
package hash_array_pkg is
type hash_array is array(integer range <>) of unsigned(127 downto 0);
type md5_indata_t is
record
data_0 : unsigned(31 downto 0);
data_1 : unsigned(31 downto 0);
start : std_logic;
len : std_logic_vector(7 downto 0);
end record;
type md5_indata_t_array is array(integer range <>) of md5_indata_t;
end hash_array_pkg;
|
mit
|
Nooxet/embedded_bruteforce
|
vhdl/tb_brutus.vhd
|
2
|
2254
|
--------------------------------------------------------------------------------
-- Engineer: Noxet
--
-- Create Date: 17:00:22 09/23/2014
-- Module Name: C:/Users/ael10jso/Xilinx/embedded_bruteforce/vhdl/tb_brutus.vhd
-- Project Name: controller_sg_pp_md_comp
-- Description:
--
-- VHDL Test Bench Created by ISE for module: brutus_top
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY tb_brutus IS
END tb_brutus;
ARCHITECTURE behavior OF tb_brutus IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT brutus_top
PORT(
clk : IN std_logic;
rstn : IN std_logic;
i_fsl_data_recv : IN std_logic;
i_fsl_hash : IN std_logic_vector(127 downto 0);
o_pw_found : OUT std_logic;
o_passwd : OUT std_logic_vector(47 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rstn : std_logic := '0';
signal i_fsl_data_recv : std_logic := '0';
signal i_fsl_hash : std_logic_vector(127 downto 0) := (others => '0');
--Outputs
signal o_pw_found : std_logic;
signal o_passwd : std_logic_vector(47 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: brutus_top PORT MAP (
clk => clk,
rstn => rstn,
i_fsl_data_recv => i_fsl_data_recv,
i_fsl_hash => i_fsl_hash,
o_pw_found => o_pw_found,
o_passwd => o_passwd
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 10 ns;
rstn <= '0';
wait for clk_period*10;
rstn <= '1';
i_fsl_hash <= x"4124bc0a9335c27f086f24ba207a4912"; -- "aa"
i_fsl_data_recv <= '1';
wait for clk_period;
i_fsl_data_recv <= '0';
wait;
end process;
END;
|
mit
|
UdayanSinha/Code_Blocks
|
VHDL/Projects/work/counter_up_down_4bit.vhd
|
1
|
1036
|
LIBRARY IEEE; -- These lines informs the compiler that the library IEEE is used
USE IEEE.std_logic_1164.all; -- contains the definition for the std_logic type plus some useful conversion functions
USE IEEE.std_logic_signed.all; --math operations for signed std_logic
ENTITY counter_up_down_4bit IS
PORT(up, clk, reset: IN STD_LOGIC;
out1: OUT STD_LOGIC;
out2: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END counter_up_down_4bit;
ARCHITECTURE behave OF counter_up_down_4bit IS
SIGNAL count : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS (clk, reset)
BEGIN
IF reset='0' THEN --asynchronous active low reset
count<=(OTHERS=>'0');
ELSIF rising_edge(clk) THEN
CASE up IS
WHEN '1'=>
count<=count+1;
WHEN OTHERS=>
count<=count-1;
END CASE;
IF ((count=15 AND up='1') OR (count=0 AND up='0')) THEN
out1<='1';
ELSE
out1<='0';
END IF;
out2<=count;
END IF;
END PROCESS;
END behave; -- Arch_counter_sig
|
mit
|
RickvanLoo/Synthesizer
|
spi_async.vhd
|
1
|
2411
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY spi_async IS
PORT ( SCLK : IN std_logic;
RESET : IN std_logic;
SDATA : IN std_logic;
CS : IN std_logic;
BYTE0, BYTE1 : OUT std_logic_vector(7 downto 0);
dig0, dig1, dig2, dig3 : OUT std_logic_vector(6 DOWNTO 0) -- show key pressed on display dig2 en dig3 (resp high & low).
);
END spi_async;
ARCHITECTURE behav of spi_async is
FUNCTION hex2display (n:std_logic_vector(3 DOWNTO 0)) RETURN std_logic_vector IS
VARIABLE res : std_logic_vector(6 DOWNTO 0);
BEGIN
CASE n IS -- gfedcba; low active
WHEN "0000" => RETURN NOT "0111111";
WHEN "0001" => RETURN NOT "0000110";
WHEN "0010" => RETURN NOT "1011011";
WHEN "0011" => RETURN NOT "1001111";
WHEN "0100" => RETURN NOT "1100110";
WHEN "0101" => RETURN NOT "1101101";
WHEN "0110" => RETURN NOT "1111101";
WHEN "0111" => RETURN NOT "0000111";
WHEN "1000" => RETURN NOT "1111111";
WHEN "1001" => RETURN NOT "1101111";
WHEN "1010" => RETURN NOT "1110111";
WHEN "1011" => RETURN NOT "1111100";
WHEN "1100" => RETURN NOT "0111001";
WHEN "1101" => RETURN NOT "1011110";
WHEN "1110" => RETURN NOT "1111001";
WHEN OTHERS => RETURN NOT "1110001";
END CASE;
END hex2display;
signal SDATA_register : std_logic_vector(15 downto 0);
BEGIN
PROCESS(RESET, SCLK, CS)
variable byte0_reg, byte1_reg : std_logic_vector(7 downto 0);
BEGIN
if reset = '0' then
SDATA_register <= (others => '0');
BYTE0 <= (others => '0');
BYTE1 <= (others => '0');
byte0_reg := (others => '0');
byte1_reg := (others => '0');
dig0 <= hex2display("0000");
dig1 <= hex2display("0000");
dig2 <= hex2display("0000");
dig3 <= hex2display("0000");
elsif CS = '1' then
byte0_reg := SDATA_register(15 downto 8);
dig0 <= hex2display(byte0_reg(3 downto 0));
dig1 <= hex2display(byte0_reg(7 downto 4));
BYTE0 <= byte0_reg;
byte1_reg := SDATA_register(7 downto 0);
dig2 <= hex2display(byte1_reg(3 downto 0));
dig3 <= hex2display(byte1_reg(7 downto 4));
BYTE1 <= byte1_reg;
elsif rising_edge(SCLK) then
if CS = '0' then --Only get SDATA when slave is selected (Active low)
SDATA_register <= SDATA_register(14 downto 0) & SDATA; --Shift register 16 bytes
end if;
end if;
END PROCESS;
END behav;
|
mit
|
Nooxet/embedded_bruteforce
|
brutus_system/ISE/fsl_test/tb_fsl_test.vhd
|
1
|
3758
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:07:54 09/29/2014
-- Design Name:
-- Module Name: C:/Users/ael10jso/Xilinx/embedded_bruteforce/brutus_system/ISE/fsl_test/tb_fsl_test.vhd
-- Project Name: fsl_test
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: test
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_fsl_test IS
END tb_fsl_test;
ARCHITECTURE behavior OF tb_fsl_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT test
PORT(
FSL_Clk : IN std_logic;
FSL_Rst : IN std_logic;
FSL_S_Clk : IN std_logic;
FSL_S_Read : OUT std_logic;
FSL_S_Data : IN std_logic_vector(0 to 31);
FSL_S_Control : IN std_logic;
FSL_S_Exists : IN std_logic;
FSL_M_Clk : IN std_logic;
FSL_M_Write : OUT std_logic;
FSL_M_Data : OUT std_logic_vector(0 to 31);
FSL_M_Control : OUT std_logic;
FSL_M_Full : IN std_logic
);
END COMPONENT;
--Inputs
signal FSL_Clk : std_logic := '0';
signal FSL_Rst : std_logic := '0';
signal FSL_S_Clk : std_logic := '0';
signal FSL_S_Data : std_logic_vector(0 to 31) := (others => '0');
signal FSL_S_Control : std_logic := '0';
signal FSL_S_Exists : std_logic := '0';
signal FSL_M_Clk : std_logic := '0';
signal FSL_M_Full : std_logic := '0';
--Outputs
signal FSL_S_Read : std_logic;
signal FSL_M_Write : std_logic;
signal FSL_M_Data : std_logic_vector(0 to 31);
signal FSL_M_Control : std_logic;
-- Clock period definitions
constant FSL_Clk_period : time := 10 ns;
constant FSL_S_Clk_period : time := 10 ns;
constant FSL_M_Clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: test PORT MAP (
FSL_Clk => FSL_Clk,
FSL_Rst => FSL_Rst,
FSL_S_Clk => FSL_S_Clk,
FSL_S_Read => FSL_S_Read,
FSL_S_Data => FSL_S_Data,
FSL_S_Control => FSL_S_Control,
FSL_S_Exists => FSL_S_Exists,
FSL_M_Clk => FSL_M_Clk,
FSL_M_Write => FSL_M_Write,
FSL_M_Data => FSL_M_Data,
FSL_M_Control => FSL_M_Control,
FSL_M_Full => FSL_M_Full
);
-- Clock process definitions
FSL_Clk_process :process
begin
FSL_Clk <= '0';
wait for FSL_Clk_period/2;
FSL_Clk <= '1';
wait for FSL_Clk_period/2;
end process;
FSL_S_Clk_process :process
begin
FSL_S_Clk <= '0';
wait for FSL_S_Clk_period/2;
FSL_S_Clk <= '1';
wait for FSL_S_Clk_period/2;
end process;
FSL_M_Clk_process :process
begin
FSL_M_Clk <= '0';
wait for FSL_M_Clk_period/2;
FSL_M_Clk <= '1';
wait for FSL_M_Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for FSL_Clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
mit
|
tsotnep/vhdl_soc_audio_mixer
|
ZedBoard_Linux_Design/hw/xps_proj/pcores/adau1761_audio_v1_00_a/hdl/vhdl/i3c2.vhd
|
6
|
14346
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Create Date: 21:30:20 05/25/2013
-- Design Name: i3c2 - Intelligent I2C Controller
-- Module Name: i3c2 - Behavioral
-- Description: The main CPU/logic
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity i3c2 is
Generic( clk_divide : STD_LOGIC_VECTOR (7 downto 0));
Port ( clk : in STD_LOGIC;
inst_address : out STD_LOGIC_VECTOR (9 downto 0);
inst_data : in STD_LOGIC_VECTOR (8 downto 0);
i2c_scl : out STD_LOGIC := '1';
i2c_sda_i : in STD_LOGIC;
i2c_sda_o : out STD_LOGIC := '0';
i2c_sda_t : out STD_LOGIC := '1';
inputs : in STD_LOGIC_VECTOR (15 downto 0);
outputs : out STD_LOGIC_VECTOR (15 downto 0) := (others => '0');
reg_addr : out STD_LOGIC_VECTOR (4 downto 0);
reg_data : out STD_LOGIC_VECTOR (7 downto 0);
reg_write : out STD_LOGIC;
debug_scl : out STD_LOGIC := '1';
debug_sda : out STD_LOGIC;
error : out STD_LOGIC);
end i3c2;
architecture Behavioral of i3c2 is
constant STATE_RUN : std_logic_vector(3 downto 0) := "0000";
constant STATE_DELAY : std_logic_vector(3 downto 0) := "0001";
constant STATE_I2C_START : std_logic_vector(3 downto 0) := "0010";
constant STATE_I2C_BITS : std_logic_vector(3 downto 0) := "0011";
constant STATE_I2C_STOP : std_logic_vector(3 downto 0) := "0100";
signal state : std_logic_vector(3 downto 0) := STATE_RUN;
constant OPCODE_JUMP : std_logic_vector( 3 downto 0) := "0000";
constant OPCODE_SKIPSET : std_logic_vector( 3 downto 0) := "0001";
constant OPCODE_SKIPCLEAR : std_logic_vector( 3 downto 0) := "0010";
constant OPCODE_SET : std_logic_vector( 3 downto 0) := "0011";
constant OPCODE_CLEAR : std_logic_vector( 3 downto 0) := "0100";
constant OPCODE_I2C_READ : std_logic_vector( 3 downto 0) := "0101";
constant OPCODE_DELAY : std_logic_vector( 3 downto 0) := "0110";
constant OPCODE_SKIPACK : std_logic_vector( 3 downto 0) := "0111";
constant OPCODE_SKIPNACK : std_logic_vector( 3 downto 0) := "1000";
constant OPCODE_NOP : std_logic_vector( 3 downto 0) := "1001";
constant OPCODE_I2C_STOP : std_logic_vector( 3 downto 0) := "1010";
constant OPCODE_I2C_WRITE : std_logic_vector( 3 downto 0) := "1011";
constant OPCODE_WRITELOW : std_logic_vector( 3 downto 0) := "1100";
constant OPCODE_WRITEHI : std_logic_vector( 3 downto 0) := "1101";
constant OPCODE_UNKNOWN : std_logic_vector( 3 downto 0) := "1110";
signal opcode : std_logic_vector( 3 downto 0);
signal ack_flag : std_logic := '0';
signal skip : std_logic := '1'; -- IGNORE THE FIRST INSTRUCTION
-- I2C status
signal i2c_doing_read : std_logic := '0';
signal i2c_started : std_logic := '0';
signal i2c_bits_left : unsigned(3 downto 0);
-- counters
signal pcnext : unsigned(9 downto 0) := (others => '0');
signal delay : unsigned(15 downto 0);
signal bitcount : unsigned( 7 downto 0);
-- Input/output data
signal i2c_data : std_logic_vector( 8 downto 0);
begin
-- |Opcode | Instruction | Action
-- +---------+-------------+----------------------------------------
-- |00nnnnnnn| JUMP m | Set PC to m (n = m/8)
-- |01000nnnn| SKIPCLEAR n | Skip if input n clear
-- |01001nnnn| SKIPSET n | skip if input n set
-- |01010nnnn| CLEAR n | Clear output n
-- |01011nnnn| SET n | Set output n
-- |0110nnnnn| READ n | Read to register n
-- |01110nnnn| DELAY m | Delay m clock cycles (n = log2(m))
-- |011110000| SKIPNACK | Skip if NACK is set
-- |011110001| SKIPACK | Skip if ACK is set
-- |011110010| WRITELOW | Write inputs 7 downto 0 to the I2C bus
-- |011110011| WRITEHI | Write inputs 15 downto 8 to the I2C bus
-- |011110100| USER0 | User defined
-- |.........| |
-- |011111110| USER9 | User defined
-- |011111111| STOP | Send Stop on i2C bus
-- |1nnnnnnnn| WRITE n | Output n on I2C bus
opcode <= OPCODE_JUMP when inst_data(8 downto 7) = "00" else
OPCODE_SKIPCLEAR when inst_data(8 downto 4) = "01000" else
OPCODE_SKIPSET when inst_data(8 downto 4) = "01001" else
OPCODE_CLEAR when inst_data(8 downto 4) = "01010" else
OPCODE_SET when inst_data(8 downto 4) = "01011" else
OPCODE_I2C_READ when inst_data(8 downto 5) = "0110" else
OPCODE_DELAY when inst_data(8 downto 4) = "01110" else
OPCODE_SKIPACK when inst_data(8 downto 0) = "011110000" else
OPCODE_SKIPNACK when inst_data(8 downto 0) = "011110001" else
OPCODE_WRITELOW when inst_data(8 downto 0) = "011110010" else
OPCODE_WRITEHI when inst_data(8 downto 0) = "011110011" else
-- user codes can go here
OPCODE_NOP when inst_data(8 downto 0) = "011111110" else
OPCODE_I2C_STOP when inst_data(8 downto 0) = "011111111" else
OPCODE_I2C_WRITE when inst_data(8 downto 8) = "1" else OPCODE_UNKNOWN;
inst_address <= std_logic_vector(pcnext);
debug_sda <= i2c_sda_i;
i2c_sda_o <= '0';
cpu: process(clk)
begin
if rising_edge(clk) then
case state is
when STATE_I2C_START =>
i2c_started <= '1';
i2c_scl <= '1';
debug_scl <= '1';
if bitcount = unsigned("0" & clk_divide(clk_divide'high downto 1)) then
i2c_sda_t <= '0';
end if;
if bitcount = 0 then
state <= STATE_I2C_BITS;
i2c_scl <= '0';
debug_scl <= '0';
bitcount <= unsigned(clk_divide);
else
bitcount <= bitcount-1;
end if;
when STATE_I2C_BITS => -- scl has always just lowered '0' on entry
-- set the data half way through clock low half of the cycle
if bitcount = unsigned(clk_divide) - unsigned("00" & clk_divide(clk_divide'high downto 2)) then
if i2c_data(8) = '0' then
i2c_sda_t <= '0';
else
i2c_sda_t <= '1';
end if;
end if;
-- raise the clock half way through
if bitcount = unsigned("0" & clk_divide(clk_divide'high downto 1)) then
i2c_scl <= '1';
debug_scl <= '1';
-- Input bits halfway through the cycle
i2c_data <= i2c_data(7 downto 0) & i2c_sda_i;
end if;
-- lower the clock at the end of the cycle
if bitcount = 0 then
i2c_scl <= '0';
debug_scl <= '0';
if i2c_bits_left = "000" then
i2c_scl <= '0';
debug_scl <= '0';
if i2c_doing_read = '1' then
reg_data <= i2c_data(8 downto 1);
reg_write <= '1';
end if;
ack_flag <= NOT i2c_data(0);
state <= STATE_RUN;
pcnext <= pcnext+1;
else
i2c_bits_left <= i2c_bits_left -1;
end if;
bitcount <= unsigned(clk_divide);
else
bitcount <= bitcount-1;
end if;
when STATE_I2C_STOP =>
-- clock stays high, and data goes high half way through a bit
i2c_started <= '0';
if bitcount = unsigned(clk_divide) - unsigned("00" & clk_divide(clk_divide'high downto 2)) then
i2c_sda_t <= '0';
end if;
if bitcount = unsigned("0" & clk_divide(clk_divide'high downto 1)) then
i2c_scl <= '1';
debug_scl <= '1';
end if;
if bitcount = unsigned("00" & clk_divide(clk_divide'high downto 2)) then
i2c_sda_t <= '1';
end if;
if bitcount = 0 then
state <= STATE_RUN;
pcnext <= pcnext+1;
else
bitcount <= bitcount-1;
end if;
when STATE_DELAY =>
if bitcount /= 0 then
bitcount <= bitcount -1;
else
if delay = 0 then
pcnext <= pcnext+1;
state <= STATE_RUN;
else
delay <= delay-1;
bitcount <= unsigned(clk_divide) - 1;
end if;
end if;
when STATE_RUN =>
reg_data <= "XXXXXXXX";
if skip = '1'then
-- Do nothing for a cycle other than unset 'skip';
skip <= '0';
pcnext <= pcnext+1;
else
case opcode is
when OPCODE_JUMP =>
-- Ignore the next instruciton while fetching the jump destination
skip <= '1';
pcnext <= unsigned(inst_data(6 downto 0)) & "000";
when OPCODE_I2C_WRITE =>
i2c_data <= inst_data(7 downto 0) & "1";
bitcount <= unsigned(clk_divide);
i2c_doing_read <= '0';
i2c_bits_left <= "1000";
if i2c_started = '0' then
state <= STATE_I2C_START;
else
state <= STATE_I2C_BITS;
end if;
when OPCODE_I2C_READ =>
reg_addr <= inst_data(4 downto 0);
i2c_data <= x"FF" & "1"; -- keep the SDA pulled up while clocking in data & ACK
bitcount <= unsigned(clk_divide);
i2c_bits_left <= "1000";
i2c_doing_read <= '1';
if i2c_started = '0' then
state <= STATE_I2C_START;
else
state <= STATE_I2C_BITS;
end if;
when OPCODE_SKIPCLEAR =>
skip <= inputs(to_integer(unsigned(inst_data(3 downto 0)))) xnor inst_data(4);
pcnext <= pcnext+1;
when OPCODE_SKIPSET =>
skip <= inputs(to_integer(unsigned(inst_data(3 downto 0)))) xnor inst_data(4);
pcnext <= pcnext+1;
when OPCODE_CLEAR =>
outputs(to_integer(unsigned(inst_data(3 downto 0)))) <= inst_data(4);
pcnext <= pcnext+1;
when OPCODE_SET =>
outputs(to_integer(unsigned(inst_data(3 downto 0)))) <= inst_data(4);
pcnext <= pcnext+1;
when OPCODE_SKIPACK =>
skip <= ack_flag;
pcnext <= pcnext+1;
when OPCODE_SKIPNACK =>
skip <= not ack_flag;
pcnext <= pcnext+1;
when OPCODE_DELAY =>
state <= STATE_DELAY;
bitcount <= unsigned(clk_divide);
case inst_data(3 downto 0) is
when "0000" => delay <= x"0001";
when "0001" => delay <= x"0002";
when "0010" => delay <= x"0004";
when "0011" => delay <= x"0008";
when "0100" => delay <= x"0010";
when "0101" => delay <= x"0020";
when "0110" => delay <= x"0040";
when "0111" => delay <= x"0080";
when "1000" => delay <= x"0100";
when "1001" => delay <= x"0200";
when "1010" => delay <= x"0400";
when "1011" => delay <= x"0800";
when "1100" => delay <= x"1000";
when "1101" => delay <= x"2000";
when "1110" => delay <= x"4000";
when others => delay <= x"8000";
end case;
when OPCODE_I2C_STOP =>
bitcount <= unsigned(clk_divide);
state <= STATE_I2C_STOP;
when OPCODE_NOP =>
pcnext <= pcnext+1;
when others =>
error <= '1';
end case;
end if;
when others =>
state <= STATE_RUN;
pcnext <= (others => '0');
skip <= '1';
end case;
end if;
end process;
end Behavioral;
|
mit
|
tsotnep/vhdl_soc_audio_mixer
|
ZedBoard_Linux_Design/hw/xps_proj/pcores/adau1761_audio_v1_00_a/hdl/vhdl/ADAU1761_interface.vhd
|
6
|
895
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: ADAU1761_interface - Behavioral
-- Description: Was originally to do a lot more, but just creates a clock at 1/2
-- the projects 48MHz to send to the codec.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ADAU1761_interface is
Port ( clk_48 : in STD_LOGIC;
codec_master_clk : out STD_LOGIC);
end ADAU1761_interface;
architecture Behavioral of ADAU1761_interface is
signal master_clk : std_logic := '0';
begin
codec_master_clk <= master_clk;
process(clk_48)
begin
if rising_edge(clk_48) then
master_clk <= not master_clk;
end if;
end process;
end Behavioral;
|
mit
|
Nooxet/embedded_bruteforce
|
vhdl/md5_mux.vhd
|
3
|
1870
|
----------------------------------------------------------------------------------
-- Engineer: Noxet
--
-- Module Name: md5_mux - Behavioral
-- Description:
-- A mux to select which hash to compare
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- include the hash_array type --
use work.hash_array_pkg.all;
entity md5_mux is
generic (
N : integer
);
port (
clk : in std_logic;
rstn : in std_logic;
i_hash_0 : in unsigned(127 downto 0); --hash_array(N-1 downto 0);
i_hash_1 : in unsigned(127 downto 0); --hash_array(N-1 downto 0);
i_select : in unsigned(N-1 downto 0); -- should be ceil(log2(N-1))
o_hash_0 : out unsigned(31 downto 0);
o_hash_1 : out unsigned(31 downto 0);
o_hash_2 : out unsigned(31 downto 0);
o_hash_3 : out unsigned(31 downto 0)
);
end md5_mux;
architecture Behavioral of md5_mux is
begin
clk_proc : process(clk)
begin
if rising_edge(clk) then
if rstn = '0' then
o_hash_0 <= (others => '0');
o_hash_1 <= (others => '0');
o_hash_2 <= (others => '0');
o_hash_3 <= (others => '0');
else
o_hash_0 <= (others => '0');
o_hash_1 <= (others => '0');
o_hash_2 <= (others => '0');
o_hash_3 <= (others => '0');
--o_hash <= i_hash(to_integer(unsigned(i_select)));
if i_select = "00" then
o_hash_0 <= i_hash_0(127 downto 96);
o_hash_1 <= i_hash_0(95 downto 64);
o_hash_2 <= i_hash_0(63 downto 32);
o_hash_3 <= i_hash_0(31 downto 0);
elsif i_select = "01" then
o_hash_0 <= i_hash_1(127 downto 96);
o_hash_1 <= i_hash_1(95 downto 64);
o_hash_2 <= i_hash_1(63 downto 32);
o_hash_3 <= i_hash_1(31 downto 0);
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
Nooxet/embedded_bruteforce
|
brutus_system/pcores/bajsd_v1_00_a/hdl/vhdl/md5_mux.vhd
|
3
|
1870
|
----------------------------------------------------------------------------------
-- Engineer: Noxet
--
-- Module Name: md5_mux - Behavioral
-- Description:
-- A mux to select which hash to compare
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- include the hash_array type --
use work.hash_array_pkg.all;
entity md5_mux is
generic (
N : integer
);
port (
clk : in std_logic;
rstn : in std_logic;
i_hash_0 : in unsigned(127 downto 0); --hash_array(N-1 downto 0);
i_hash_1 : in unsigned(127 downto 0); --hash_array(N-1 downto 0);
i_select : in unsigned(N-1 downto 0); -- should be ceil(log2(N-1))
o_hash_0 : out unsigned(31 downto 0);
o_hash_1 : out unsigned(31 downto 0);
o_hash_2 : out unsigned(31 downto 0);
o_hash_3 : out unsigned(31 downto 0)
);
end md5_mux;
architecture Behavioral of md5_mux is
begin
clk_proc : process(clk)
begin
if rising_edge(clk) then
if rstn = '0' then
o_hash_0 <= (others => '0');
o_hash_1 <= (others => '0');
o_hash_2 <= (others => '0');
o_hash_3 <= (others => '0');
else
o_hash_0 <= (others => '0');
o_hash_1 <= (others => '0');
o_hash_2 <= (others => '0');
o_hash_3 <= (others => '0');
--o_hash <= i_hash(to_integer(unsigned(i_select)));
if i_select = "00" then
o_hash_0 <= i_hash_0(127 downto 96);
o_hash_1 <= i_hash_0(95 downto 64);
o_hash_2 <= i_hash_0(63 downto 32);
o_hash_3 <= i_hash_0(31 downto 0);
elsif i_select = "01" then
o_hash_0 <= i_hash_1(127 downto 96);
o_hash_1 <= i_hash_1(95 downto 64);
o_hash_2 <= i_hash_1(63 downto 32);
o_hash_3 <= i_hash_1(31 downto 0);
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
Nooxet/embedded_bruteforce
|
brutus_system/hdl/system_microblaze_0_wrapper.vhd
|
1
|
88130
|
-------------------------------------------------------------------------------
-- system_microblaze_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library microblaze_v8_40_a;
use microblaze_v8_40_a.all;
entity system_microblaze_0_wrapper is
port (
CLK : in std_logic;
RESET : in std_logic;
MB_RESET : in std_logic;
INTERRUPT : in std_logic;
INTERRUPT_ADDRESS : in std_logic_vector(0 to 31);
INTERRUPT_ACK : out std_logic_vector(0 to 1);
EXT_BRK : in std_logic;
EXT_NM_BRK : in std_logic;
DBG_STOP : in std_logic;
MB_Halted : out std_logic;
MB_Error : out std_logic;
WAKEUP : in std_logic_vector(0 to 1);
SLEEP : out std_logic;
DBG_WAKEUP : out std_logic;
LOCKSTEP_MASTER_OUT : out std_logic_vector(0 to 4095);
LOCKSTEP_SLAVE_IN : in std_logic_vector(0 to 4095);
LOCKSTEP_OUT : out std_logic_vector(0 to 4095);
INSTR : in std_logic_vector(0 to 31);
IREADY : in std_logic;
IWAIT : in std_logic;
ICE : in std_logic;
IUE : in std_logic;
INSTR_ADDR : out std_logic_vector(0 to 31);
IFETCH : out std_logic;
I_AS : out std_logic;
IPLB_M_ABort : out std_logic;
IPLB_M_ABus : out std_logic_vector(0 to 31);
IPLB_M_UABus : out std_logic_vector(0 to 31);
IPLB_M_BE : out std_logic_vector(0 to 3);
IPLB_M_busLock : out std_logic;
IPLB_M_lockErr : out std_logic;
IPLB_M_MSize : out std_logic_vector(0 to 1);
IPLB_M_priority : out std_logic_vector(0 to 1);
IPLB_M_rdBurst : out std_logic;
IPLB_M_request : out std_logic;
IPLB_M_RNW : out std_logic;
IPLB_M_size : out std_logic_vector(0 to 3);
IPLB_M_TAttribute : out std_logic_vector(0 to 15);
IPLB_M_type : out std_logic_vector(0 to 2);
IPLB_M_wrBurst : out std_logic;
IPLB_M_wrDBus : out std_logic_vector(0 to 31);
IPLB_MBusy : in std_logic;
IPLB_MRdErr : in std_logic;
IPLB_MWrErr : in std_logic;
IPLB_MIRQ : in std_logic;
IPLB_MWrBTerm : in std_logic;
IPLB_MWrDAck : in std_logic;
IPLB_MAddrAck : in std_logic;
IPLB_MRdBTerm : in std_logic;
IPLB_MRdDAck : in std_logic;
IPLB_MRdDBus : in std_logic_vector(0 to 31);
IPLB_MRdWdAddr : in std_logic_vector(0 to 3);
IPLB_MRearbitrate : in std_logic;
IPLB_MSSize : in std_logic_vector(0 to 1);
IPLB_MTimeout : in std_logic;
DATA_READ : in std_logic_vector(0 to 31);
DREADY : in std_logic;
DWAIT : in std_logic;
DCE : in std_logic;
DUE : in std_logic;
DATA_WRITE : out std_logic_vector(0 to 31);
DATA_ADDR : out std_logic_vector(0 to 31);
D_AS : out std_logic;
READ_STROBE : out std_logic;
WRITE_STROBE : out std_logic;
BYTE_ENABLE : out std_logic_vector(0 to 3);
DPLB_M_ABort : out std_logic;
DPLB_M_ABus : out std_logic_vector(0 to 31);
DPLB_M_UABus : out std_logic_vector(0 to 31);
DPLB_M_BE : out std_logic_vector(0 to 3);
DPLB_M_busLock : out std_logic;
DPLB_M_lockErr : out std_logic;
DPLB_M_MSize : out std_logic_vector(0 to 1);
DPLB_M_priority : out std_logic_vector(0 to 1);
DPLB_M_rdBurst : out std_logic;
DPLB_M_request : out std_logic;
DPLB_M_RNW : out std_logic;
DPLB_M_size : out std_logic_vector(0 to 3);
DPLB_M_TAttribute : out std_logic_vector(0 to 15);
DPLB_M_type : out std_logic_vector(0 to 2);
DPLB_M_wrBurst : out std_logic;
DPLB_M_wrDBus : out std_logic_vector(0 to 31);
DPLB_MBusy : in std_logic;
DPLB_MRdErr : in std_logic;
DPLB_MWrErr : in std_logic;
DPLB_MIRQ : in std_logic;
DPLB_MWrBTerm : in std_logic;
DPLB_MWrDAck : in std_logic;
DPLB_MAddrAck : in std_logic;
DPLB_MRdBTerm : in std_logic;
DPLB_MRdDAck : in std_logic;
DPLB_MRdDBus : in std_logic_vector(0 to 31);
DPLB_MRdWdAddr : in std_logic_vector(0 to 3);
DPLB_MRearbitrate : in std_logic;
DPLB_MSSize : in std_logic_vector(0 to 1);
DPLB_MTimeout : in std_logic;
M_AXI_IP_AWID : out std_logic_vector(0 downto 0);
M_AXI_IP_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_IP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_AWLOCK : out std_logic;
M_AXI_IP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_AWVALID : out std_logic;
M_AXI_IP_AWREADY : in std_logic;
M_AXI_IP_WDATA : out std_logic_vector(31 downto 0);
M_AXI_IP_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_IP_WLAST : out std_logic;
M_AXI_IP_WVALID : out std_logic;
M_AXI_IP_WREADY : in std_logic;
M_AXI_IP_BID : in std_logic_vector(0 downto 0);
M_AXI_IP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_BVALID : in std_logic;
M_AXI_IP_BREADY : out std_logic;
M_AXI_IP_ARID : out std_logic_vector(0 downto 0);
M_AXI_IP_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_IP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_ARLOCK : out std_logic;
M_AXI_IP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_ARVALID : out std_logic;
M_AXI_IP_ARREADY : in std_logic;
M_AXI_IP_RID : in std_logic_vector(0 downto 0);
M_AXI_IP_RDATA : in std_logic_vector(31 downto 0);
M_AXI_IP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_RLAST : in std_logic;
M_AXI_IP_RVALID : in std_logic;
M_AXI_IP_RREADY : out std_logic;
M_AXI_DP_AWID : out std_logic_vector(0 downto 0);
M_AXI_DP_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_DP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_AWLOCK : out std_logic;
M_AXI_DP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_AWVALID : out std_logic;
M_AXI_DP_AWREADY : in std_logic;
M_AXI_DP_WDATA : out std_logic_vector(31 downto 0);
M_AXI_DP_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_DP_WLAST : out std_logic;
M_AXI_DP_WVALID : out std_logic;
M_AXI_DP_WREADY : in std_logic;
M_AXI_DP_BID : in std_logic_vector(0 downto 0);
M_AXI_DP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_BVALID : in std_logic;
M_AXI_DP_BREADY : out std_logic;
M_AXI_DP_ARID : out std_logic_vector(0 downto 0);
M_AXI_DP_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_DP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_ARLOCK : out std_logic;
M_AXI_DP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_ARVALID : out std_logic;
M_AXI_DP_ARREADY : in std_logic;
M_AXI_DP_RID : in std_logic_vector(0 downto 0);
M_AXI_DP_RDATA : in std_logic_vector(31 downto 0);
M_AXI_DP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_RLAST : in std_logic;
M_AXI_DP_RVALID : in std_logic;
M_AXI_DP_RREADY : out std_logic;
M_AXI_IC_AWID : out std_logic_vector(0 downto 0);
M_AXI_IC_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_IC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_AWLOCK : out std_logic;
M_AXI_IC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_AWVALID : out std_logic;
M_AXI_IC_AWREADY : in std_logic;
M_AXI_IC_AWUSER : out std_logic_vector(4 downto 0);
M_AXI_IC_WDATA : out std_logic_vector(31 downto 0);
M_AXI_IC_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_IC_WLAST : out std_logic;
M_AXI_IC_WVALID : out std_logic;
M_AXI_IC_WREADY : in std_logic;
M_AXI_IC_WUSER : out std_logic_vector(0 downto 0);
M_AXI_IC_BID : in std_logic_vector(0 downto 0);
M_AXI_IC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IC_BVALID : in std_logic;
M_AXI_IC_BREADY : out std_logic;
M_AXI_IC_BUSER : in std_logic_vector(0 downto 0);
M_AXI_IC_ARID : out std_logic_vector(0 downto 0);
M_AXI_IC_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_IC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_ARLOCK : out std_logic;
M_AXI_IC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_ARVALID : out std_logic;
M_AXI_IC_ARREADY : in std_logic;
M_AXI_IC_ARUSER : out std_logic_vector(4 downto 0);
M_AXI_IC_RID : in std_logic_vector(0 downto 0);
M_AXI_IC_RDATA : in std_logic_vector(31 downto 0);
M_AXI_IC_RRESP : in std_logic_vector(1 downto 0);
M_AXI_IC_RLAST : in std_logic;
M_AXI_IC_RVALID : in std_logic;
M_AXI_IC_RREADY : out std_logic;
M_AXI_IC_RUSER : in std_logic_vector(0 downto 0);
M_AXI_DC_AWID : out std_logic_vector(0 downto 0);
M_AXI_DC_AWADDR : out std_logic_vector(31 downto 0);
M_AXI_DC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_AWLOCK : out std_logic;
M_AXI_DC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_AWVALID : out std_logic;
M_AXI_DC_AWREADY : in std_logic;
M_AXI_DC_AWUSER : out std_logic_vector(4 downto 0);
M_AXI_DC_WDATA : out std_logic_vector(31 downto 0);
M_AXI_DC_WSTRB : out std_logic_vector(3 downto 0);
M_AXI_DC_WLAST : out std_logic;
M_AXI_DC_WVALID : out std_logic;
M_AXI_DC_WREADY : in std_logic;
M_AXI_DC_WUSER : out std_logic_vector(0 downto 0);
M_AXI_DC_BID : in std_logic_vector(0 downto 0);
M_AXI_DC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DC_BVALID : in std_logic;
M_AXI_DC_BREADY : out std_logic;
M_AXI_DC_BUSER : in std_logic_vector(0 downto 0);
M_AXI_DC_ARID : out std_logic_vector(0 downto 0);
M_AXI_DC_ARADDR : out std_logic_vector(31 downto 0);
M_AXI_DC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_ARLOCK : out std_logic;
M_AXI_DC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_ARVALID : out std_logic;
M_AXI_DC_ARREADY : in std_logic;
M_AXI_DC_ARUSER : out std_logic_vector(4 downto 0);
M_AXI_DC_RID : in std_logic_vector(0 downto 0);
M_AXI_DC_RDATA : in std_logic_vector(31 downto 0);
M_AXI_DC_RRESP : in std_logic_vector(1 downto 0);
M_AXI_DC_RLAST : in std_logic;
M_AXI_DC_RVALID : in std_logic;
M_AXI_DC_RREADY : out std_logic;
M_AXI_DC_RUSER : in std_logic_vector(0 downto 0);
DBG_CLK : in std_logic;
DBG_TDI : in std_logic;
DBG_TDO : out std_logic;
DBG_REG_EN : in std_logic_vector(0 to 7);
DBG_SHIFT : in std_logic;
DBG_CAPTURE : in std_logic;
DBG_UPDATE : in std_logic;
DEBUG_RST : in std_logic;
Trace_Instruction : out std_logic_vector(0 to 31);
Trace_Valid_Instr : out std_logic;
Trace_PC : out std_logic_vector(0 to 31);
Trace_Reg_Write : out std_logic;
Trace_Reg_Addr : out std_logic_vector(0 to 4);
Trace_MSR_Reg : out std_logic_vector(0 to 14);
Trace_PID_Reg : out std_logic_vector(0 to 7);
Trace_New_Reg_Value : out std_logic_vector(0 to 31);
Trace_Exception_Taken : out std_logic;
Trace_Exception_Kind : out std_logic_vector(0 to 4);
Trace_Jump_Taken : out std_logic;
Trace_Delay_Slot : out std_logic;
Trace_Data_Address : out std_logic_vector(0 to 31);
Trace_Data_Access : out std_logic;
Trace_Data_Read : out std_logic;
Trace_Data_Write : out std_logic;
Trace_Data_Write_Value : out std_logic_vector(0 to 31);
Trace_Data_Byte_Enable : out std_logic_vector(0 to 3);
Trace_DCache_Req : out std_logic;
Trace_DCache_Hit : out std_logic;
Trace_DCache_Rdy : out std_logic;
Trace_DCache_Read : out std_logic;
Trace_ICache_Req : out std_logic;
Trace_ICache_Hit : out std_logic;
Trace_ICache_Rdy : out std_logic;
Trace_OF_PipeRun : out std_logic;
Trace_EX_PipeRun : out std_logic;
Trace_MEM_PipeRun : out std_logic;
Trace_MB_Halted : out std_logic;
Trace_Jump_Hit : out std_logic;
FSL0_S_CLK : out std_logic;
FSL0_S_READ : out std_logic;
FSL0_S_DATA : in std_logic_vector(0 to 31);
FSL0_S_CONTROL : in std_logic;
FSL0_S_EXISTS : in std_logic;
FSL0_M_CLK : out std_logic;
FSL0_M_WRITE : out std_logic;
FSL0_M_DATA : out std_logic_vector(0 to 31);
FSL0_M_CONTROL : out std_logic;
FSL0_M_FULL : in std_logic;
FSL1_S_CLK : out std_logic;
FSL1_S_READ : out std_logic;
FSL1_S_DATA : in std_logic_vector(0 to 31);
FSL1_S_CONTROL : in std_logic;
FSL1_S_EXISTS : in std_logic;
FSL1_M_CLK : out std_logic;
FSL1_M_WRITE : out std_logic;
FSL1_M_DATA : out std_logic_vector(0 to 31);
FSL1_M_CONTROL : out std_logic;
FSL1_M_FULL : in std_logic;
FSL2_S_CLK : out std_logic;
FSL2_S_READ : out std_logic;
FSL2_S_DATA : in std_logic_vector(0 to 31);
FSL2_S_CONTROL : in std_logic;
FSL2_S_EXISTS : in std_logic;
FSL2_M_CLK : out std_logic;
FSL2_M_WRITE : out std_logic;
FSL2_M_DATA : out std_logic_vector(0 to 31);
FSL2_M_CONTROL : out std_logic;
FSL2_M_FULL : in std_logic;
FSL3_S_CLK : out std_logic;
FSL3_S_READ : out std_logic;
FSL3_S_DATA : in std_logic_vector(0 to 31);
FSL3_S_CONTROL : in std_logic;
FSL3_S_EXISTS : in std_logic;
FSL3_M_CLK : out std_logic;
FSL3_M_WRITE : out std_logic;
FSL3_M_DATA : out std_logic_vector(0 to 31);
FSL3_M_CONTROL : out std_logic;
FSL3_M_FULL : in std_logic;
FSL4_S_CLK : out std_logic;
FSL4_S_READ : out std_logic;
FSL4_S_DATA : in std_logic_vector(0 to 31);
FSL4_S_CONTROL : in std_logic;
FSL4_S_EXISTS : in std_logic;
FSL4_M_CLK : out std_logic;
FSL4_M_WRITE : out std_logic;
FSL4_M_DATA : out std_logic_vector(0 to 31);
FSL4_M_CONTROL : out std_logic;
FSL4_M_FULL : in std_logic;
FSL5_S_CLK : out std_logic;
FSL5_S_READ : out std_logic;
FSL5_S_DATA : in std_logic_vector(0 to 31);
FSL5_S_CONTROL : in std_logic;
FSL5_S_EXISTS : in std_logic;
FSL5_M_CLK : out std_logic;
FSL5_M_WRITE : out std_logic;
FSL5_M_DATA : out std_logic_vector(0 to 31);
FSL5_M_CONTROL : out std_logic;
FSL5_M_FULL : in std_logic;
FSL6_S_CLK : out std_logic;
FSL6_S_READ : out std_logic;
FSL6_S_DATA : in std_logic_vector(0 to 31);
FSL6_S_CONTROL : in std_logic;
FSL6_S_EXISTS : in std_logic;
FSL6_M_CLK : out std_logic;
FSL6_M_WRITE : out std_logic;
FSL6_M_DATA : out std_logic_vector(0 to 31);
FSL6_M_CONTROL : out std_logic;
FSL6_M_FULL : in std_logic;
FSL7_S_CLK : out std_logic;
FSL7_S_READ : out std_logic;
FSL7_S_DATA : in std_logic_vector(0 to 31);
FSL7_S_CONTROL : in std_logic;
FSL7_S_EXISTS : in std_logic;
FSL7_M_CLK : out std_logic;
FSL7_M_WRITE : out std_logic;
FSL7_M_DATA : out std_logic_vector(0 to 31);
FSL7_M_CONTROL : out std_logic;
FSL7_M_FULL : in std_logic;
FSL8_S_CLK : out std_logic;
FSL8_S_READ : out std_logic;
FSL8_S_DATA : in std_logic_vector(0 to 31);
FSL8_S_CONTROL : in std_logic;
FSL8_S_EXISTS : in std_logic;
FSL8_M_CLK : out std_logic;
FSL8_M_WRITE : out std_logic;
FSL8_M_DATA : out std_logic_vector(0 to 31);
FSL8_M_CONTROL : out std_logic;
FSL8_M_FULL : in std_logic;
FSL9_S_CLK : out std_logic;
FSL9_S_READ : out std_logic;
FSL9_S_DATA : in std_logic_vector(0 to 31);
FSL9_S_CONTROL : in std_logic;
FSL9_S_EXISTS : in std_logic;
FSL9_M_CLK : out std_logic;
FSL9_M_WRITE : out std_logic;
FSL9_M_DATA : out std_logic_vector(0 to 31);
FSL9_M_CONTROL : out std_logic;
FSL9_M_FULL : in std_logic;
FSL10_S_CLK : out std_logic;
FSL10_S_READ : out std_logic;
FSL10_S_DATA : in std_logic_vector(0 to 31);
FSL10_S_CONTROL : in std_logic;
FSL10_S_EXISTS : in std_logic;
FSL10_M_CLK : out std_logic;
FSL10_M_WRITE : out std_logic;
FSL10_M_DATA : out std_logic_vector(0 to 31);
FSL10_M_CONTROL : out std_logic;
FSL10_M_FULL : in std_logic;
FSL11_S_CLK : out std_logic;
FSL11_S_READ : out std_logic;
FSL11_S_DATA : in std_logic_vector(0 to 31);
FSL11_S_CONTROL : in std_logic;
FSL11_S_EXISTS : in std_logic;
FSL11_M_CLK : out std_logic;
FSL11_M_WRITE : out std_logic;
FSL11_M_DATA : out std_logic_vector(0 to 31);
FSL11_M_CONTROL : out std_logic;
FSL11_M_FULL : in std_logic;
FSL12_S_CLK : out std_logic;
FSL12_S_READ : out std_logic;
FSL12_S_DATA : in std_logic_vector(0 to 31);
FSL12_S_CONTROL : in std_logic;
FSL12_S_EXISTS : in std_logic;
FSL12_M_CLK : out std_logic;
FSL12_M_WRITE : out std_logic;
FSL12_M_DATA : out std_logic_vector(0 to 31);
FSL12_M_CONTROL : out std_logic;
FSL12_M_FULL : in std_logic;
FSL13_S_CLK : out std_logic;
FSL13_S_READ : out std_logic;
FSL13_S_DATA : in std_logic_vector(0 to 31);
FSL13_S_CONTROL : in std_logic;
FSL13_S_EXISTS : in std_logic;
FSL13_M_CLK : out std_logic;
FSL13_M_WRITE : out std_logic;
FSL13_M_DATA : out std_logic_vector(0 to 31);
FSL13_M_CONTROL : out std_logic;
FSL13_M_FULL : in std_logic;
FSL14_S_CLK : out std_logic;
FSL14_S_READ : out std_logic;
FSL14_S_DATA : in std_logic_vector(0 to 31);
FSL14_S_CONTROL : in std_logic;
FSL14_S_EXISTS : in std_logic;
FSL14_M_CLK : out std_logic;
FSL14_M_WRITE : out std_logic;
FSL14_M_DATA : out std_logic_vector(0 to 31);
FSL14_M_CONTROL : out std_logic;
FSL14_M_FULL : in std_logic;
FSL15_S_CLK : out std_logic;
FSL15_S_READ : out std_logic;
FSL15_S_DATA : in std_logic_vector(0 to 31);
FSL15_S_CONTROL : in std_logic;
FSL15_S_EXISTS : in std_logic;
FSL15_M_CLK : out std_logic;
FSL15_M_WRITE : out std_logic;
FSL15_M_DATA : out std_logic_vector(0 to 31);
FSL15_M_CONTROL : out std_logic;
FSL15_M_FULL : in std_logic;
M0_AXIS_TLAST : out std_logic;
M0_AXIS_TDATA : out std_logic_vector(31 downto 0);
M0_AXIS_TVALID : out std_logic;
M0_AXIS_TREADY : in std_logic;
S0_AXIS_TLAST : in std_logic;
S0_AXIS_TDATA : in std_logic_vector(31 downto 0);
S0_AXIS_TVALID : in std_logic;
S0_AXIS_TREADY : out std_logic;
M1_AXIS_TLAST : out std_logic;
M1_AXIS_TDATA : out std_logic_vector(31 downto 0);
M1_AXIS_TVALID : out std_logic;
M1_AXIS_TREADY : in std_logic;
S1_AXIS_TLAST : in std_logic;
S1_AXIS_TDATA : in std_logic_vector(31 downto 0);
S1_AXIS_TVALID : in std_logic;
S1_AXIS_TREADY : out std_logic;
M2_AXIS_TLAST : out std_logic;
M2_AXIS_TDATA : out std_logic_vector(31 downto 0);
M2_AXIS_TVALID : out std_logic;
M2_AXIS_TREADY : in std_logic;
S2_AXIS_TLAST : in std_logic;
S2_AXIS_TDATA : in std_logic_vector(31 downto 0);
S2_AXIS_TVALID : in std_logic;
S2_AXIS_TREADY : out std_logic;
M3_AXIS_TLAST : out std_logic;
M3_AXIS_TDATA : out std_logic_vector(31 downto 0);
M3_AXIS_TVALID : out std_logic;
M3_AXIS_TREADY : in std_logic;
S3_AXIS_TLAST : in std_logic;
S3_AXIS_TDATA : in std_logic_vector(31 downto 0);
S3_AXIS_TVALID : in std_logic;
S3_AXIS_TREADY : out std_logic;
M4_AXIS_TLAST : out std_logic;
M4_AXIS_TDATA : out std_logic_vector(31 downto 0);
M4_AXIS_TVALID : out std_logic;
M4_AXIS_TREADY : in std_logic;
S4_AXIS_TLAST : in std_logic;
S4_AXIS_TDATA : in std_logic_vector(31 downto 0);
S4_AXIS_TVALID : in std_logic;
S4_AXIS_TREADY : out std_logic;
M5_AXIS_TLAST : out std_logic;
M5_AXIS_TDATA : out std_logic_vector(31 downto 0);
M5_AXIS_TVALID : out std_logic;
M5_AXIS_TREADY : in std_logic;
S5_AXIS_TLAST : in std_logic;
S5_AXIS_TDATA : in std_logic_vector(31 downto 0);
S5_AXIS_TVALID : in std_logic;
S5_AXIS_TREADY : out std_logic;
M6_AXIS_TLAST : out std_logic;
M6_AXIS_TDATA : out std_logic_vector(31 downto 0);
M6_AXIS_TVALID : out std_logic;
M6_AXIS_TREADY : in std_logic;
S6_AXIS_TLAST : in std_logic;
S6_AXIS_TDATA : in std_logic_vector(31 downto 0);
S6_AXIS_TVALID : in std_logic;
S6_AXIS_TREADY : out std_logic;
M7_AXIS_TLAST : out std_logic;
M7_AXIS_TDATA : out std_logic_vector(31 downto 0);
M7_AXIS_TVALID : out std_logic;
M7_AXIS_TREADY : in std_logic;
S7_AXIS_TLAST : in std_logic;
S7_AXIS_TDATA : in std_logic_vector(31 downto 0);
S7_AXIS_TVALID : in std_logic;
S7_AXIS_TREADY : out std_logic;
M8_AXIS_TLAST : out std_logic;
M8_AXIS_TDATA : out std_logic_vector(31 downto 0);
M8_AXIS_TVALID : out std_logic;
M8_AXIS_TREADY : in std_logic;
S8_AXIS_TLAST : in std_logic;
S8_AXIS_TDATA : in std_logic_vector(31 downto 0);
S8_AXIS_TVALID : in std_logic;
S8_AXIS_TREADY : out std_logic;
M9_AXIS_TLAST : out std_logic;
M9_AXIS_TDATA : out std_logic_vector(31 downto 0);
M9_AXIS_TVALID : out std_logic;
M9_AXIS_TREADY : in std_logic;
S9_AXIS_TLAST : in std_logic;
S9_AXIS_TDATA : in std_logic_vector(31 downto 0);
S9_AXIS_TVALID : in std_logic;
S9_AXIS_TREADY : out std_logic;
M10_AXIS_TLAST : out std_logic;
M10_AXIS_TDATA : out std_logic_vector(31 downto 0);
M10_AXIS_TVALID : out std_logic;
M10_AXIS_TREADY : in std_logic;
S10_AXIS_TLAST : in std_logic;
S10_AXIS_TDATA : in std_logic_vector(31 downto 0);
S10_AXIS_TVALID : in std_logic;
S10_AXIS_TREADY : out std_logic;
M11_AXIS_TLAST : out std_logic;
M11_AXIS_TDATA : out std_logic_vector(31 downto 0);
M11_AXIS_TVALID : out std_logic;
M11_AXIS_TREADY : in std_logic;
S11_AXIS_TLAST : in std_logic;
S11_AXIS_TDATA : in std_logic_vector(31 downto 0);
S11_AXIS_TVALID : in std_logic;
S11_AXIS_TREADY : out std_logic;
M12_AXIS_TLAST : out std_logic;
M12_AXIS_TDATA : out std_logic_vector(31 downto 0);
M12_AXIS_TVALID : out std_logic;
M12_AXIS_TREADY : in std_logic;
S12_AXIS_TLAST : in std_logic;
S12_AXIS_TDATA : in std_logic_vector(31 downto 0);
S12_AXIS_TVALID : in std_logic;
S12_AXIS_TREADY : out std_logic;
M13_AXIS_TLAST : out std_logic;
M13_AXIS_TDATA : out std_logic_vector(31 downto 0);
M13_AXIS_TVALID : out std_logic;
M13_AXIS_TREADY : in std_logic;
S13_AXIS_TLAST : in std_logic;
S13_AXIS_TDATA : in std_logic_vector(31 downto 0);
S13_AXIS_TVALID : in std_logic;
S13_AXIS_TREADY : out std_logic;
M14_AXIS_TLAST : out std_logic;
M14_AXIS_TDATA : out std_logic_vector(31 downto 0);
M14_AXIS_TVALID : out std_logic;
M14_AXIS_TREADY : in std_logic;
S14_AXIS_TLAST : in std_logic;
S14_AXIS_TDATA : in std_logic_vector(31 downto 0);
S14_AXIS_TVALID : in std_logic;
S14_AXIS_TREADY : out std_logic;
M15_AXIS_TLAST : out std_logic;
M15_AXIS_TDATA : out std_logic_vector(31 downto 0);
M15_AXIS_TVALID : out std_logic;
M15_AXIS_TREADY : in std_logic;
S15_AXIS_TLAST : in std_logic;
S15_AXIS_TDATA : in std_logic_vector(31 downto 0);
S15_AXIS_TVALID : in std_logic;
S15_AXIS_TREADY : out std_logic;
ICACHE_FSL_IN_CLK : out std_logic;
ICACHE_FSL_IN_READ : out std_logic;
ICACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
ICACHE_FSL_IN_CONTROL : in std_logic;
ICACHE_FSL_IN_EXISTS : in std_logic;
ICACHE_FSL_OUT_CLK : out std_logic;
ICACHE_FSL_OUT_WRITE : out std_logic;
ICACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
ICACHE_FSL_OUT_CONTROL : out std_logic;
ICACHE_FSL_OUT_FULL : in std_logic;
DCACHE_FSL_IN_CLK : out std_logic;
DCACHE_FSL_IN_READ : out std_logic;
DCACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
DCACHE_FSL_IN_CONTROL : in std_logic;
DCACHE_FSL_IN_EXISTS : in std_logic;
DCACHE_FSL_OUT_CLK : out std_logic;
DCACHE_FSL_OUT_WRITE : out std_logic;
DCACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
DCACHE_FSL_OUT_CONTROL : out std_logic;
DCACHE_FSL_OUT_FULL : in std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of system_microblaze_0_wrapper : entity is "microblaze_v8_40_a";
end system_microblaze_0_wrapper;
architecture STRUCTURE of system_microblaze_0_wrapper is
component microblaze is
generic (
C_SCO : integer;
C_FREQ : integer;
C_DATA_SIZE : integer;
C_DYNAMIC_BUS_SIZING : integer;
C_FAMILY : string;
C_INSTANCE : string;
C_AVOID_PRIMITIVES : integer;
C_FAULT_TOLERANT : integer;
C_ECC_USE_CE_EXCEPTION : integer;
C_LOCKSTEP_SLAVE : integer;
C_ENDIANNESS : integer;
C_AREA_OPTIMIZED : integer;
C_OPTIMIZATION : integer;
C_INTERCONNECT : integer;
C_STREAM_INTERCONNECT : integer;
C_DPLB_DWIDTH : integer;
C_DPLB_NATIVE_DWIDTH : integer;
C_DPLB_BURST_EN : integer;
C_DPLB_P2P : integer;
C_IPLB_DWIDTH : integer;
C_IPLB_NATIVE_DWIDTH : integer;
C_IPLB_BURST_EN : integer;
C_IPLB_P2P : integer;
C_M_AXI_DP_THREAD_ID_WIDTH : integer;
C_M_AXI_DP_DATA_WIDTH : integer;
C_M_AXI_DP_ADDR_WIDTH : integer;
C_M_AXI_DP_EXCLUSIVE_ACCESS : integer;
C_M_AXI_IP_THREAD_ID_WIDTH : integer;
C_M_AXI_IP_DATA_WIDTH : integer;
C_M_AXI_IP_ADDR_WIDTH : integer;
C_D_AXI : integer;
C_D_PLB : integer;
C_D_LMB : integer;
C_I_AXI : integer;
C_I_PLB : integer;
C_I_LMB : integer;
C_USE_MSR_INSTR : integer;
C_USE_PCMP_INSTR : integer;
C_USE_BARREL : integer;
C_USE_DIV : integer;
C_USE_HW_MUL : integer;
C_USE_FPU : integer;
C_USE_REORDER_INSTR : integer;
C_UNALIGNED_EXCEPTIONS : integer;
C_ILL_OPCODE_EXCEPTION : integer;
C_M_AXI_I_BUS_EXCEPTION : integer;
C_M_AXI_D_BUS_EXCEPTION : integer;
C_IPLB_BUS_EXCEPTION : integer;
C_DPLB_BUS_EXCEPTION : integer;
C_DIV_ZERO_EXCEPTION : integer;
C_FPU_EXCEPTION : integer;
C_FSL_EXCEPTION : integer;
C_USE_STACK_PROTECTION : integer;
C_PVR : integer;
C_PVR_USER1 : std_logic_vector(0 to 7);
C_PVR_USER2 : std_logic_vector(0 to 31);
C_DEBUG_ENABLED : integer;
C_NUMBER_OF_PC_BRK : integer;
C_NUMBER_OF_RD_ADDR_BRK : integer;
C_NUMBER_OF_WR_ADDR_BRK : integer;
C_INTERRUPT_IS_EDGE : integer;
C_EDGE_IS_POSITIVE : integer;
C_RESET_MSR : std_logic_vector;
C_OPCODE_0x0_ILLEGAL : integer;
C_FSL_LINKS : integer;
C_FSL_DATA_SIZE : integer;
C_USE_EXTENDED_FSL_INSTR : integer;
C_M0_AXIS_DATA_WIDTH : integer;
C_S0_AXIS_DATA_WIDTH : integer;
C_M1_AXIS_DATA_WIDTH : integer;
C_S1_AXIS_DATA_WIDTH : integer;
C_M2_AXIS_DATA_WIDTH : integer;
C_S2_AXIS_DATA_WIDTH : integer;
C_M3_AXIS_DATA_WIDTH : integer;
C_S3_AXIS_DATA_WIDTH : integer;
C_M4_AXIS_DATA_WIDTH : integer;
C_S4_AXIS_DATA_WIDTH : integer;
C_M5_AXIS_DATA_WIDTH : integer;
C_S5_AXIS_DATA_WIDTH : integer;
C_M6_AXIS_DATA_WIDTH : integer;
C_S6_AXIS_DATA_WIDTH : integer;
C_M7_AXIS_DATA_WIDTH : integer;
C_S7_AXIS_DATA_WIDTH : integer;
C_M8_AXIS_DATA_WIDTH : integer;
C_S8_AXIS_DATA_WIDTH : integer;
C_M9_AXIS_DATA_WIDTH : integer;
C_S9_AXIS_DATA_WIDTH : integer;
C_M10_AXIS_DATA_WIDTH : integer;
C_S10_AXIS_DATA_WIDTH : integer;
C_M11_AXIS_DATA_WIDTH : integer;
C_S11_AXIS_DATA_WIDTH : integer;
C_M12_AXIS_DATA_WIDTH : integer;
C_S12_AXIS_DATA_WIDTH : integer;
C_M13_AXIS_DATA_WIDTH : integer;
C_S13_AXIS_DATA_WIDTH : integer;
C_M14_AXIS_DATA_WIDTH : integer;
C_S14_AXIS_DATA_WIDTH : integer;
C_M15_AXIS_DATA_WIDTH : integer;
C_S15_AXIS_DATA_WIDTH : integer;
C_ICACHE_BASEADDR : std_logic_vector;
C_ICACHE_HIGHADDR : std_logic_vector;
C_USE_ICACHE : integer;
C_ALLOW_ICACHE_WR : integer;
C_ADDR_TAG_BITS : integer;
C_CACHE_BYTE_SIZE : integer;
C_ICACHE_USE_FSL : integer;
C_ICACHE_LINE_LEN : integer;
C_ICACHE_ALWAYS_USED : integer;
C_ICACHE_INTERFACE : integer;
C_ICACHE_VICTIMS : integer;
C_ICACHE_STREAMS : integer;
C_ICACHE_FORCE_TAG_LUTRAM : integer;
C_ICACHE_DATA_WIDTH : integer;
C_M_AXI_IC_THREAD_ID_WIDTH : integer;
C_M_AXI_IC_DATA_WIDTH : integer;
C_M_AXI_IC_ADDR_WIDTH : integer;
C_M_AXI_IC_USER_VALUE : integer;
C_M_AXI_IC_AWUSER_WIDTH : integer;
C_M_AXI_IC_ARUSER_WIDTH : integer;
C_M_AXI_IC_WUSER_WIDTH : integer;
C_M_AXI_IC_RUSER_WIDTH : integer;
C_M_AXI_IC_BUSER_WIDTH : integer;
C_DCACHE_BASEADDR : std_logic_vector;
C_DCACHE_HIGHADDR : std_logic_vector;
C_USE_DCACHE : integer;
C_ALLOW_DCACHE_WR : integer;
C_DCACHE_ADDR_TAG : integer;
C_DCACHE_BYTE_SIZE : integer;
C_DCACHE_USE_FSL : integer;
C_DCACHE_LINE_LEN : integer;
C_DCACHE_ALWAYS_USED : integer;
C_DCACHE_INTERFACE : integer;
C_DCACHE_USE_WRITEBACK : integer;
C_DCACHE_VICTIMS : integer;
C_DCACHE_FORCE_TAG_LUTRAM : integer;
C_DCACHE_DATA_WIDTH : integer;
C_M_AXI_DC_THREAD_ID_WIDTH : integer;
C_M_AXI_DC_DATA_WIDTH : integer;
C_M_AXI_DC_ADDR_WIDTH : integer;
C_M_AXI_DC_EXCLUSIVE_ACCESS : integer;
C_M_AXI_DC_USER_VALUE : integer;
C_M_AXI_DC_AWUSER_WIDTH : integer;
C_M_AXI_DC_ARUSER_WIDTH : integer;
C_M_AXI_DC_WUSER_WIDTH : integer;
C_M_AXI_DC_RUSER_WIDTH : integer;
C_M_AXI_DC_BUSER_WIDTH : integer;
C_USE_MMU : integer;
C_MMU_DTLB_SIZE : integer;
C_MMU_ITLB_SIZE : integer;
C_MMU_TLB_ACCESS : integer;
C_MMU_ZONES : integer;
C_MMU_PRIVILEGED_INSTR : integer;
C_USE_INTERRUPT : integer;
C_USE_EXT_BRK : integer;
C_USE_EXT_NM_BRK : integer;
C_USE_BRANCH_TARGET_CACHE : integer;
C_BRANCH_TARGET_CACHE_SIZE : integer;
C_PC_WIDTH : integer
);
port (
CLK : in std_logic;
RESET : in std_logic;
MB_RESET : in std_logic;
INTERRUPT : in std_logic;
INTERRUPT_ADDRESS : in std_logic_vector(0 to 31);
INTERRUPT_ACK : out std_logic_vector(0 to 1);
EXT_BRK : in std_logic;
EXT_NM_BRK : in std_logic;
DBG_STOP : in std_logic;
MB_Halted : out std_logic;
MB_Error : out std_logic;
WAKEUP : in std_logic_vector(0 to 1);
SLEEP : out std_logic;
DBG_WAKEUP : out std_logic;
LOCKSTEP_MASTER_OUT : out std_logic_vector(0 to 4095);
LOCKSTEP_SLAVE_IN : in std_logic_vector(0 to 4095);
LOCKSTEP_OUT : out std_logic_vector(0 to 4095);
INSTR : in std_logic_vector(0 to 31);
IREADY : in std_logic;
IWAIT : in std_logic;
ICE : in std_logic;
IUE : in std_logic;
INSTR_ADDR : out std_logic_vector(0 to 31);
IFETCH : out std_logic;
I_AS : out std_logic;
IPLB_M_ABort : out std_logic;
IPLB_M_ABus : out std_logic_vector(0 to 31);
IPLB_M_UABus : out std_logic_vector(0 to 31);
IPLB_M_BE : out std_logic_vector(0 to (C_IPLB_DWIDTH-1)/8);
IPLB_M_busLock : out std_logic;
IPLB_M_lockErr : out std_logic;
IPLB_M_MSize : out std_logic_vector(0 to 1);
IPLB_M_priority : out std_logic_vector(0 to 1);
IPLB_M_rdBurst : out std_logic;
IPLB_M_request : out std_logic;
IPLB_M_RNW : out std_logic;
IPLB_M_size : out std_logic_vector(0 to 3);
IPLB_M_TAttribute : out std_logic_vector(0 to 15);
IPLB_M_type : out std_logic_vector(0 to 2);
IPLB_M_wrBurst : out std_logic;
IPLB_M_wrDBus : out std_logic_vector(0 to C_IPLB_DWIDTH-1);
IPLB_MBusy : in std_logic;
IPLB_MRdErr : in std_logic;
IPLB_MWrErr : in std_logic;
IPLB_MIRQ : in std_logic;
IPLB_MWrBTerm : in std_logic;
IPLB_MWrDAck : in std_logic;
IPLB_MAddrAck : in std_logic;
IPLB_MRdBTerm : in std_logic;
IPLB_MRdDAck : in std_logic;
IPLB_MRdDBus : in std_logic_vector(0 to C_IPLB_DWIDTH-1);
IPLB_MRdWdAddr : in std_logic_vector(0 to 3);
IPLB_MRearbitrate : in std_logic;
IPLB_MSSize : in std_logic_vector(0 to 1);
IPLB_MTimeout : in std_logic;
DATA_READ : in std_logic_vector(0 to 31);
DREADY : in std_logic;
DWAIT : in std_logic;
DCE : in std_logic;
DUE : in std_logic;
DATA_WRITE : out std_logic_vector(0 to 31);
DATA_ADDR : out std_logic_vector(0 to 31);
D_AS : out std_logic;
READ_STROBE : out std_logic;
WRITE_STROBE : out std_logic;
BYTE_ENABLE : out std_logic_vector(0 to 3);
DPLB_M_ABort : out std_logic;
DPLB_M_ABus : out std_logic_vector(0 to 31);
DPLB_M_UABus : out std_logic_vector(0 to 31);
DPLB_M_BE : out std_logic_vector(0 to (C_DPLB_DWIDTH-1)/8);
DPLB_M_busLock : out std_logic;
DPLB_M_lockErr : out std_logic;
DPLB_M_MSize : out std_logic_vector(0 to 1);
DPLB_M_priority : out std_logic_vector(0 to 1);
DPLB_M_rdBurst : out std_logic;
DPLB_M_request : out std_logic;
DPLB_M_RNW : out std_logic;
DPLB_M_size : out std_logic_vector(0 to 3);
DPLB_M_TAttribute : out std_logic_vector(0 to 15);
DPLB_M_type : out std_logic_vector(0 to 2);
DPLB_M_wrBurst : out std_logic;
DPLB_M_wrDBus : out std_logic_vector(0 to C_DPLB_DWIDTH-1);
DPLB_MBusy : in std_logic;
DPLB_MRdErr : in std_logic;
DPLB_MWrErr : in std_logic;
DPLB_MIRQ : in std_logic;
DPLB_MWrBTerm : in std_logic;
DPLB_MWrDAck : in std_logic;
DPLB_MAddrAck : in std_logic;
DPLB_MRdBTerm : in std_logic;
DPLB_MRdDAck : in std_logic;
DPLB_MRdDBus : in std_logic_vector(0 to C_DPLB_DWIDTH-1);
DPLB_MRdWdAddr : in std_logic_vector(0 to 3);
DPLB_MRearbitrate : in std_logic;
DPLB_MSSize : in std_logic_vector(0 to 1);
DPLB_MTimeout : in std_logic;
M_AXI_IP_AWID : out std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IP_AWADDR : out std_logic_vector((C_M_AXI_IP_ADDR_WIDTH-1) downto 0);
M_AXI_IP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_AWLOCK : out std_logic;
M_AXI_IP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_AWVALID : out std_logic;
M_AXI_IP_AWREADY : in std_logic;
M_AXI_IP_WDATA : out std_logic_vector((C_M_AXI_IP_DATA_WIDTH-1) downto 0);
M_AXI_IP_WSTRB : out std_logic_vector(((C_M_AXI_IP_DATA_WIDTH/8)-1) downto 0);
M_AXI_IP_WLAST : out std_logic;
M_AXI_IP_WVALID : out std_logic;
M_AXI_IP_WREADY : in std_logic;
M_AXI_IP_BID : in std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_BVALID : in std_logic;
M_AXI_IP_BREADY : out std_logic;
M_AXI_IP_ARID : out std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IP_ARADDR : out std_logic_vector((C_M_AXI_IP_ADDR_WIDTH-1) downto 0);
M_AXI_IP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IP_ARLOCK : out std_logic;
M_AXI_IP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IP_ARVALID : out std_logic;
M_AXI_IP_ARREADY : in std_logic;
M_AXI_IP_RID : in std_logic_vector((C_M_AXI_IP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IP_RDATA : in std_logic_vector((C_M_AXI_IP_DATA_WIDTH-1) downto 0);
M_AXI_IP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_IP_RLAST : in std_logic;
M_AXI_IP_RVALID : in std_logic;
M_AXI_IP_RREADY : out std_logic;
M_AXI_DP_AWID : out std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DP_AWADDR : out std_logic_vector((C_M_AXI_DP_ADDR_WIDTH-1) downto 0);
M_AXI_DP_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_AWLOCK : out std_logic;
M_AXI_DP_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_AWVALID : out std_logic;
M_AXI_DP_AWREADY : in std_logic;
M_AXI_DP_WDATA : out std_logic_vector((C_M_AXI_DP_DATA_WIDTH-1) downto 0);
M_AXI_DP_WSTRB : out std_logic_vector(((C_M_AXI_DP_DATA_WIDTH/8)-1) downto 0);
M_AXI_DP_WLAST : out std_logic;
M_AXI_DP_WVALID : out std_logic;
M_AXI_DP_WREADY : in std_logic;
M_AXI_DP_BID : in std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DP_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_BVALID : in std_logic;
M_AXI_DP_BREADY : out std_logic;
M_AXI_DP_ARID : out std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DP_ARADDR : out std_logic_vector((C_M_AXI_DP_ADDR_WIDTH-1) downto 0);
M_AXI_DP_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DP_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DP_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DP_ARLOCK : out std_logic;
M_AXI_DP_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DP_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DP_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DP_ARVALID : out std_logic;
M_AXI_DP_ARREADY : in std_logic;
M_AXI_DP_RID : in std_logic_vector((C_M_AXI_DP_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DP_RDATA : in std_logic_vector((C_M_AXI_DP_DATA_WIDTH-1) downto 0);
M_AXI_DP_RRESP : in std_logic_vector(1 downto 0);
M_AXI_DP_RLAST : in std_logic;
M_AXI_DP_RVALID : in std_logic;
M_AXI_DP_RREADY : out std_logic;
M_AXI_IC_AWID : out std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IC_AWADDR : out std_logic_vector((C_M_AXI_IC_ADDR_WIDTH-1) downto 0);
M_AXI_IC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_AWLOCK : out std_logic;
M_AXI_IC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_AWVALID : out std_logic;
M_AXI_IC_AWREADY : in std_logic;
M_AXI_IC_AWUSER : out std_logic_vector((C_M_AXI_IC_AWUSER_WIDTH-1) downto 0);
M_AXI_IC_WDATA : out std_logic_vector((C_M_AXI_IC_DATA_WIDTH-1) downto 0);
M_AXI_IC_WSTRB : out std_logic_vector(((C_M_AXI_IC_DATA_WIDTH/8)-1) downto 0);
M_AXI_IC_WLAST : out std_logic;
M_AXI_IC_WVALID : out std_logic;
M_AXI_IC_WREADY : in std_logic;
M_AXI_IC_WUSER : out std_logic_vector((C_M_AXI_IC_WUSER_WIDTH-1) downto 0);
M_AXI_IC_BID : in std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_IC_BVALID : in std_logic;
M_AXI_IC_BREADY : out std_logic;
M_AXI_IC_BUSER : in std_logic_vector((C_M_AXI_IC_BUSER_WIDTH-1) downto 0);
M_AXI_IC_ARID : out std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IC_ARADDR : out std_logic_vector((C_M_AXI_IC_ADDR_WIDTH-1) downto 0);
M_AXI_IC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_IC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_IC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_IC_ARLOCK : out std_logic;
M_AXI_IC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_IC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_IC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_IC_ARVALID : out std_logic;
M_AXI_IC_ARREADY : in std_logic;
M_AXI_IC_ARUSER : out std_logic_vector((C_M_AXI_IC_ARUSER_WIDTH-1) downto 0);
M_AXI_IC_RID : in std_logic_vector((C_M_AXI_IC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_IC_RDATA : in std_logic_vector((C_M_AXI_IC_DATA_WIDTH-1) downto 0);
M_AXI_IC_RRESP : in std_logic_vector(1 downto 0);
M_AXI_IC_RLAST : in std_logic;
M_AXI_IC_RVALID : in std_logic;
M_AXI_IC_RREADY : out std_logic;
M_AXI_IC_RUSER : in std_logic_vector((C_M_AXI_IC_RUSER_WIDTH-1) downto 0);
M_AXI_DC_AWID : out std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DC_AWADDR : out std_logic_vector((C_M_AXI_DC_ADDR_WIDTH-1) downto 0);
M_AXI_DC_AWLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_AWSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_AWBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_AWLOCK : out std_logic;
M_AXI_DC_AWCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_AWPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_AWQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_AWVALID : out std_logic;
M_AXI_DC_AWREADY : in std_logic;
M_AXI_DC_AWUSER : out std_logic_vector((C_M_AXI_DC_AWUSER_WIDTH-1) downto 0);
M_AXI_DC_WDATA : out std_logic_vector((C_M_AXI_DC_DATA_WIDTH-1) downto 0);
M_AXI_DC_WSTRB : out std_logic_vector(((C_M_AXI_DC_DATA_WIDTH/8)-1) downto 0);
M_AXI_DC_WLAST : out std_logic;
M_AXI_DC_WVALID : out std_logic;
M_AXI_DC_WREADY : in std_logic;
M_AXI_DC_WUSER : out std_logic_vector((C_M_AXI_DC_WUSER_WIDTH-1) downto 0);
M_AXI_DC_BID : in std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DC_BRESP : in std_logic_vector(1 downto 0);
M_AXI_DC_BVALID : in std_logic;
M_AXI_DC_BREADY : out std_logic;
M_AXI_DC_BUSER : in std_logic_vector((C_M_AXI_DC_BUSER_WIDTH-1) downto 0);
M_AXI_DC_ARID : out std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DC_ARADDR : out std_logic_vector((C_M_AXI_DC_ADDR_WIDTH-1) downto 0);
M_AXI_DC_ARLEN : out std_logic_vector(7 downto 0);
M_AXI_DC_ARSIZE : out std_logic_vector(2 downto 0);
M_AXI_DC_ARBURST : out std_logic_vector(1 downto 0);
M_AXI_DC_ARLOCK : out std_logic;
M_AXI_DC_ARCACHE : out std_logic_vector(3 downto 0);
M_AXI_DC_ARPROT : out std_logic_vector(2 downto 0);
M_AXI_DC_ARQOS : out std_logic_vector(3 downto 0);
M_AXI_DC_ARVALID : out std_logic;
M_AXI_DC_ARREADY : in std_logic;
M_AXI_DC_ARUSER : out std_logic_vector((C_M_AXI_DC_ARUSER_WIDTH-1) downto 0);
M_AXI_DC_RID : in std_logic_vector((C_M_AXI_DC_THREAD_ID_WIDTH-1) downto 0);
M_AXI_DC_RDATA : in std_logic_vector((C_M_AXI_DC_DATA_WIDTH-1) downto 0);
M_AXI_DC_RRESP : in std_logic_vector(1 downto 0);
M_AXI_DC_RLAST : in std_logic;
M_AXI_DC_RVALID : in std_logic;
M_AXI_DC_RREADY : out std_logic;
M_AXI_DC_RUSER : in std_logic_vector((C_M_AXI_DC_RUSER_WIDTH-1) downto 0);
DBG_CLK : in std_logic;
DBG_TDI : in std_logic;
DBG_TDO : out std_logic;
DBG_REG_EN : in std_logic_vector(0 to 7);
DBG_SHIFT : in std_logic;
DBG_CAPTURE : in std_logic;
DBG_UPDATE : in std_logic;
DEBUG_RST : in std_logic;
Trace_Instruction : out std_logic_vector(0 to 31);
Trace_Valid_Instr : out std_logic;
Trace_PC : out std_logic_vector(0 to 31);
Trace_Reg_Write : out std_logic;
Trace_Reg_Addr : out std_logic_vector(0 to 4);
Trace_MSR_Reg : out std_logic_vector(0 to 14);
Trace_PID_Reg : out std_logic_vector(0 to 7);
Trace_New_Reg_Value : out std_logic_vector(0 to 31);
Trace_Exception_Taken : out std_logic;
Trace_Exception_Kind : out std_logic_vector(0 to 4);
Trace_Jump_Taken : out std_logic;
Trace_Delay_Slot : out std_logic;
Trace_Data_Address : out std_logic_vector(0 to 31);
Trace_Data_Access : out std_logic;
Trace_Data_Read : out std_logic;
Trace_Data_Write : out std_logic;
Trace_Data_Write_Value : out std_logic_vector(0 to 31);
Trace_Data_Byte_Enable : out std_logic_vector(0 to 3);
Trace_DCache_Req : out std_logic;
Trace_DCache_Hit : out std_logic;
Trace_DCache_Rdy : out std_logic;
Trace_DCache_Read : out std_logic;
Trace_ICache_Req : out std_logic;
Trace_ICache_Hit : out std_logic;
Trace_ICache_Rdy : out std_logic;
Trace_OF_PipeRun : out std_logic;
Trace_EX_PipeRun : out std_logic;
Trace_MEM_PipeRun : out std_logic;
Trace_MB_Halted : out std_logic;
Trace_Jump_Hit : out std_logic;
FSL0_S_CLK : out std_logic;
FSL0_S_READ : out std_logic;
FSL0_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL0_S_CONTROL : in std_logic;
FSL0_S_EXISTS : in std_logic;
FSL0_M_CLK : out std_logic;
FSL0_M_WRITE : out std_logic;
FSL0_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL0_M_CONTROL : out std_logic;
FSL0_M_FULL : in std_logic;
FSL1_S_CLK : out std_logic;
FSL1_S_READ : out std_logic;
FSL1_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL1_S_CONTROL : in std_logic;
FSL1_S_EXISTS : in std_logic;
FSL1_M_CLK : out std_logic;
FSL1_M_WRITE : out std_logic;
FSL1_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL1_M_CONTROL : out std_logic;
FSL1_M_FULL : in std_logic;
FSL2_S_CLK : out std_logic;
FSL2_S_READ : out std_logic;
FSL2_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL2_S_CONTROL : in std_logic;
FSL2_S_EXISTS : in std_logic;
FSL2_M_CLK : out std_logic;
FSL2_M_WRITE : out std_logic;
FSL2_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL2_M_CONTROL : out std_logic;
FSL2_M_FULL : in std_logic;
FSL3_S_CLK : out std_logic;
FSL3_S_READ : out std_logic;
FSL3_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL3_S_CONTROL : in std_logic;
FSL3_S_EXISTS : in std_logic;
FSL3_M_CLK : out std_logic;
FSL3_M_WRITE : out std_logic;
FSL3_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL3_M_CONTROL : out std_logic;
FSL3_M_FULL : in std_logic;
FSL4_S_CLK : out std_logic;
FSL4_S_READ : out std_logic;
FSL4_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL4_S_CONTROL : in std_logic;
FSL4_S_EXISTS : in std_logic;
FSL4_M_CLK : out std_logic;
FSL4_M_WRITE : out std_logic;
FSL4_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL4_M_CONTROL : out std_logic;
FSL4_M_FULL : in std_logic;
FSL5_S_CLK : out std_logic;
FSL5_S_READ : out std_logic;
FSL5_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL5_S_CONTROL : in std_logic;
FSL5_S_EXISTS : in std_logic;
FSL5_M_CLK : out std_logic;
FSL5_M_WRITE : out std_logic;
FSL5_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL5_M_CONTROL : out std_logic;
FSL5_M_FULL : in std_logic;
FSL6_S_CLK : out std_logic;
FSL6_S_READ : out std_logic;
FSL6_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL6_S_CONTROL : in std_logic;
FSL6_S_EXISTS : in std_logic;
FSL6_M_CLK : out std_logic;
FSL6_M_WRITE : out std_logic;
FSL6_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL6_M_CONTROL : out std_logic;
FSL6_M_FULL : in std_logic;
FSL7_S_CLK : out std_logic;
FSL7_S_READ : out std_logic;
FSL7_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL7_S_CONTROL : in std_logic;
FSL7_S_EXISTS : in std_logic;
FSL7_M_CLK : out std_logic;
FSL7_M_WRITE : out std_logic;
FSL7_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL7_M_CONTROL : out std_logic;
FSL7_M_FULL : in std_logic;
FSL8_S_CLK : out std_logic;
FSL8_S_READ : out std_logic;
FSL8_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL8_S_CONTROL : in std_logic;
FSL8_S_EXISTS : in std_logic;
FSL8_M_CLK : out std_logic;
FSL8_M_WRITE : out std_logic;
FSL8_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL8_M_CONTROL : out std_logic;
FSL8_M_FULL : in std_logic;
FSL9_S_CLK : out std_logic;
FSL9_S_READ : out std_logic;
FSL9_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL9_S_CONTROL : in std_logic;
FSL9_S_EXISTS : in std_logic;
FSL9_M_CLK : out std_logic;
FSL9_M_WRITE : out std_logic;
FSL9_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL9_M_CONTROL : out std_logic;
FSL9_M_FULL : in std_logic;
FSL10_S_CLK : out std_logic;
FSL10_S_READ : out std_logic;
FSL10_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL10_S_CONTROL : in std_logic;
FSL10_S_EXISTS : in std_logic;
FSL10_M_CLK : out std_logic;
FSL10_M_WRITE : out std_logic;
FSL10_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL10_M_CONTROL : out std_logic;
FSL10_M_FULL : in std_logic;
FSL11_S_CLK : out std_logic;
FSL11_S_READ : out std_logic;
FSL11_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL11_S_CONTROL : in std_logic;
FSL11_S_EXISTS : in std_logic;
FSL11_M_CLK : out std_logic;
FSL11_M_WRITE : out std_logic;
FSL11_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL11_M_CONTROL : out std_logic;
FSL11_M_FULL : in std_logic;
FSL12_S_CLK : out std_logic;
FSL12_S_READ : out std_logic;
FSL12_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL12_S_CONTROL : in std_logic;
FSL12_S_EXISTS : in std_logic;
FSL12_M_CLK : out std_logic;
FSL12_M_WRITE : out std_logic;
FSL12_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL12_M_CONTROL : out std_logic;
FSL12_M_FULL : in std_logic;
FSL13_S_CLK : out std_logic;
FSL13_S_READ : out std_logic;
FSL13_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL13_S_CONTROL : in std_logic;
FSL13_S_EXISTS : in std_logic;
FSL13_M_CLK : out std_logic;
FSL13_M_WRITE : out std_logic;
FSL13_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL13_M_CONTROL : out std_logic;
FSL13_M_FULL : in std_logic;
FSL14_S_CLK : out std_logic;
FSL14_S_READ : out std_logic;
FSL14_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL14_S_CONTROL : in std_logic;
FSL14_S_EXISTS : in std_logic;
FSL14_M_CLK : out std_logic;
FSL14_M_WRITE : out std_logic;
FSL14_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL14_M_CONTROL : out std_logic;
FSL14_M_FULL : in std_logic;
FSL15_S_CLK : out std_logic;
FSL15_S_READ : out std_logic;
FSL15_S_DATA : in std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL15_S_CONTROL : in std_logic;
FSL15_S_EXISTS : in std_logic;
FSL15_M_CLK : out std_logic;
FSL15_M_WRITE : out std_logic;
FSL15_M_DATA : out std_logic_vector(0 to C_FSL_DATA_SIZE-1);
FSL15_M_CONTROL : out std_logic;
FSL15_M_FULL : in std_logic;
M0_AXIS_TLAST : out std_logic;
M0_AXIS_TDATA : out std_logic_vector(C_M0_AXIS_DATA_WIDTH-1 downto 0);
M0_AXIS_TVALID : out std_logic;
M0_AXIS_TREADY : in std_logic;
S0_AXIS_TLAST : in std_logic;
S0_AXIS_TDATA : in std_logic_vector(C_S0_AXIS_DATA_WIDTH-1 downto 0);
S0_AXIS_TVALID : in std_logic;
S0_AXIS_TREADY : out std_logic;
M1_AXIS_TLAST : out std_logic;
M1_AXIS_TDATA : out std_logic_vector(C_M1_AXIS_DATA_WIDTH-1 downto 0);
M1_AXIS_TVALID : out std_logic;
M1_AXIS_TREADY : in std_logic;
S1_AXIS_TLAST : in std_logic;
S1_AXIS_TDATA : in std_logic_vector(C_S1_AXIS_DATA_WIDTH-1 downto 0);
S1_AXIS_TVALID : in std_logic;
S1_AXIS_TREADY : out std_logic;
M2_AXIS_TLAST : out std_logic;
M2_AXIS_TDATA : out std_logic_vector(C_M2_AXIS_DATA_WIDTH-1 downto 0);
M2_AXIS_TVALID : out std_logic;
M2_AXIS_TREADY : in std_logic;
S2_AXIS_TLAST : in std_logic;
S2_AXIS_TDATA : in std_logic_vector(C_S2_AXIS_DATA_WIDTH-1 downto 0);
S2_AXIS_TVALID : in std_logic;
S2_AXIS_TREADY : out std_logic;
M3_AXIS_TLAST : out std_logic;
M3_AXIS_TDATA : out std_logic_vector(C_M3_AXIS_DATA_WIDTH-1 downto 0);
M3_AXIS_TVALID : out std_logic;
M3_AXIS_TREADY : in std_logic;
S3_AXIS_TLAST : in std_logic;
S3_AXIS_TDATA : in std_logic_vector(C_S3_AXIS_DATA_WIDTH-1 downto 0);
S3_AXIS_TVALID : in std_logic;
S3_AXIS_TREADY : out std_logic;
M4_AXIS_TLAST : out std_logic;
M4_AXIS_TDATA : out std_logic_vector(C_M4_AXIS_DATA_WIDTH-1 downto 0);
M4_AXIS_TVALID : out std_logic;
M4_AXIS_TREADY : in std_logic;
S4_AXIS_TLAST : in std_logic;
S4_AXIS_TDATA : in std_logic_vector(C_S4_AXIS_DATA_WIDTH-1 downto 0);
S4_AXIS_TVALID : in std_logic;
S4_AXIS_TREADY : out std_logic;
M5_AXIS_TLAST : out std_logic;
M5_AXIS_TDATA : out std_logic_vector(C_M5_AXIS_DATA_WIDTH-1 downto 0);
M5_AXIS_TVALID : out std_logic;
M5_AXIS_TREADY : in std_logic;
S5_AXIS_TLAST : in std_logic;
S5_AXIS_TDATA : in std_logic_vector(C_S5_AXIS_DATA_WIDTH-1 downto 0);
S5_AXIS_TVALID : in std_logic;
S5_AXIS_TREADY : out std_logic;
M6_AXIS_TLAST : out std_logic;
M6_AXIS_TDATA : out std_logic_vector(C_M6_AXIS_DATA_WIDTH-1 downto 0);
M6_AXIS_TVALID : out std_logic;
M6_AXIS_TREADY : in std_logic;
S6_AXIS_TLAST : in std_logic;
S6_AXIS_TDATA : in std_logic_vector(C_S6_AXIS_DATA_WIDTH-1 downto 0);
S6_AXIS_TVALID : in std_logic;
S6_AXIS_TREADY : out std_logic;
M7_AXIS_TLAST : out std_logic;
M7_AXIS_TDATA : out std_logic_vector(C_M7_AXIS_DATA_WIDTH-1 downto 0);
M7_AXIS_TVALID : out std_logic;
M7_AXIS_TREADY : in std_logic;
S7_AXIS_TLAST : in std_logic;
S7_AXIS_TDATA : in std_logic_vector(C_S7_AXIS_DATA_WIDTH-1 downto 0);
S7_AXIS_TVALID : in std_logic;
S7_AXIS_TREADY : out std_logic;
M8_AXIS_TLAST : out std_logic;
M8_AXIS_TDATA : out std_logic_vector(C_M8_AXIS_DATA_WIDTH-1 downto 0);
M8_AXIS_TVALID : out std_logic;
M8_AXIS_TREADY : in std_logic;
S8_AXIS_TLAST : in std_logic;
S8_AXIS_TDATA : in std_logic_vector(C_S8_AXIS_DATA_WIDTH-1 downto 0);
S8_AXIS_TVALID : in std_logic;
S8_AXIS_TREADY : out std_logic;
M9_AXIS_TLAST : out std_logic;
M9_AXIS_TDATA : out std_logic_vector(C_M9_AXIS_DATA_WIDTH-1 downto 0);
M9_AXIS_TVALID : out std_logic;
M9_AXIS_TREADY : in std_logic;
S9_AXIS_TLAST : in std_logic;
S9_AXIS_TDATA : in std_logic_vector(C_S9_AXIS_DATA_WIDTH-1 downto 0);
S9_AXIS_TVALID : in std_logic;
S9_AXIS_TREADY : out std_logic;
M10_AXIS_TLAST : out std_logic;
M10_AXIS_TDATA : out std_logic_vector(C_M10_AXIS_DATA_WIDTH-1 downto 0);
M10_AXIS_TVALID : out std_logic;
M10_AXIS_TREADY : in std_logic;
S10_AXIS_TLAST : in std_logic;
S10_AXIS_TDATA : in std_logic_vector(C_S10_AXIS_DATA_WIDTH-1 downto 0);
S10_AXIS_TVALID : in std_logic;
S10_AXIS_TREADY : out std_logic;
M11_AXIS_TLAST : out std_logic;
M11_AXIS_TDATA : out std_logic_vector(C_M11_AXIS_DATA_WIDTH-1 downto 0);
M11_AXIS_TVALID : out std_logic;
M11_AXIS_TREADY : in std_logic;
S11_AXIS_TLAST : in std_logic;
S11_AXIS_TDATA : in std_logic_vector(C_S11_AXIS_DATA_WIDTH-1 downto 0);
S11_AXIS_TVALID : in std_logic;
S11_AXIS_TREADY : out std_logic;
M12_AXIS_TLAST : out std_logic;
M12_AXIS_TDATA : out std_logic_vector(C_M12_AXIS_DATA_WIDTH-1 downto 0);
M12_AXIS_TVALID : out std_logic;
M12_AXIS_TREADY : in std_logic;
S12_AXIS_TLAST : in std_logic;
S12_AXIS_TDATA : in std_logic_vector(C_S12_AXIS_DATA_WIDTH-1 downto 0);
S12_AXIS_TVALID : in std_logic;
S12_AXIS_TREADY : out std_logic;
M13_AXIS_TLAST : out std_logic;
M13_AXIS_TDATA : out std_logic_vector(C_M13_AXIS_DATA_WIDTH-1 downto 0);
M13_AXIS_TVALID : out std_logic;
M13_AXIS_TREADY : in std_logic;
S13_AXIS_TLAST : in std_logic;
S13_AXIS_TDATA : in std_logic_vector(C_S13_AXIS_DATA_WIDTH-1 downto 0);
S13_AXIS_TVALID : in std_logic;
S13_AXIS_TREADY : out std_logic;
M14_AXIS_TLAST : out std_logic;
M14_AXIS_TDATA : out std_logic_vector(C_M14_AXIS_DATA_WIDTH-1 downto 0);
M14_AXIS_TVALID : out std_logic;
M14_AXIS_TREADY : in std_logic;
S14_AXIS_TLAST : in std_logic;
S14_AXIS_TDATA : in std_logic_vector(C_S14_AXIS_DATA_WIDTH-1 downto 0);
S14_AXIS_TVALID : in std_logic;
S14_AXIS_TREADY : out std_logic;
M15_AXIS_TLAST : out std_logic;
M15_AXIS_TDATA : out std_logic_vector(C_M15_AXIS_DATA_WIDTH-1 downto 0);
M15_AXIS_TVALID : out std_logic;
M15_AXIS_TREADY : in std_logic;
S15_AXIS_TLAST : in std_logic;
S15_AXIS_TDATA : in std_logic_vector(C_S15_AXIS_DATA_WIDTH-1 downto 0);
S15_AXIS_TVALID : in std_logic;
S15_AXIS_TREADY : out std_logic;
ICACHE_FSL_IN_CLK : out std_logic;
ICACHE_FSL_IN_READ : out std_logic;
ICACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
ICACHE_FSL_IN_CONTROL : in std_logic;
ICACHE_FSL_IN_EXISTS : in std_logic;
ICACHE_FSL_OUT_CLK : out std_logic;
ICACHE_FSL_OUT_WRITE : out std_logic;
ICACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
ICACHE_FSL_OUT_CONTROL : out std_logic;
ICACHE_FSL_OUT_FULL : in std_logic;
DCACHE_FSL_IN_CLK : out std_logic;
DCACHE_FSL_IN_READ : out std_logic;
DCACHE_FSL_IN_DATA : in std_logic_vector(0 to 31);
DCACHE_FSL_IN_CONTROL : in std_logic;
DCACHE_FSL_IN_EXISTS : in std_logic;
DCACHE_FSL_OUT_CLK : out std_logic;
DCACHE_FSL_OUT_WRITE : out std_logic;
DCACHE_FSL_OUT_DATA : out std_logic_vector(0 to 31);
DCACHE_FSL_OUT_CONTROL : out std_logic;
DCACHE_FSL_OUT_FULL : in std_logic
);
end component;
begin
microblaze_0 : microblaze
generic map (
C_SCO => 0,
C_FREQ => 50000000,
C_DATA_SIZE => 32,
C_DYNAMIC_BUS_SIZING => 1,
C_FAMILY => "spartan6",
C_INSTANCE => "microblaze_0",
C_AVOID_PRIMITIVES => 0,
C_FAULT_TOLERANT => 0,
C_ECC_USE_CE_EXCEPTION => 0,
C_LOCKSTEP_SLAVE => 0,
C_ENDIANNESS => 1,
C_AREA_OPTIMIZED => 0,
C_OPTIMIZATION => 0,
C_INTERCONNECT => 2,
C_STREAM_INTERCONNECT => 0,
C_DPLB_DWIDTH => 32,
C_DPLB_NATIVE_DWIDTH => 32,
C_DPLB_BURST_EN => 0,
C_DPLB_P2P => 0,
C_IPLB_DWIDTH => 32,
C_IPLB_NATIVE_DWIDTH => 32,
C_IPLB_BURST_EN => 0,
C_IPLB_P2P => 0,
C_M_AXI_DP_THREAD_ID_WIDTH => 1,
C_M_AXI_DP_DATA_WIDTH => 32,
C_M_AXI_DP_ADDR_WIDTH => 32,
C_M_AXI_DP_EXCLUSIVE_ACCESS => 0,
C_M_AXI_IP_THREAD_ID_WIDTH => 1,
C_M_AXI_IP_DATA_WIDTH => 32,
C_M_AXI_IP_ADDR_WIDTH => 32,
C_D_AXI => 1,
C_D_PLB => 0,
C_D_LMB => 1,
C_I_AXI => 0,
C_I_PLB => 0,
C_I_LMB => 1,
C_USE_MSR_INSTR => 1,
C_USE_PCMP_INSTR => 1,
C_USE_BARREL => 1,
C_USE_DIV => 0,
C_USE_HW_MUL => 1,
C_USE_FPU => 0,
C_USE_REORDER_INSTR => 1,
C_UNALIGNED_EXCEPTIONS => 0,
C_ILL_OPCODE_EXCEPTION => 0,
C_M_AXI_I_BUS_EXCEPTION => 0,
C_M_AXI_D_BUS_EXCEPTION => 0,
C_IPLB_BUS_EXCEPTION => 0,
C_DPLB_BUS_EXCEPTION => 0,
C_DIV_ZERO_EXCEPTION => 0,
C_FPU_EXCEPTION => 0,
C_FSL_EXCEPTION => 0,
C_USE_STACK_PROTECTION => 0,
C_PVR => 0,
C_PVR_USER1 => X"00",
C_PVR_USER2 => X"00000000",
C_DEBUG_ENABLED => 1,
C_NUMBER_OF_PC_BRK => 1,
C_NUMBER_OF_RD_ADDR_BRK => 0,
C_NUMBER_OF_WR_ADDR_BRK => 0,
C_INTERRUPT_IS_EDGE => 0,
C_EDGE_IS_POSITIVE => 1,
C_RESET_MSR => X"00000000",
C_OPCODE_0x0_ILLEGAL => 0,
C_FSL_LINKS => 1,
C_FSL_DATA_SIZE => 32,
C_USE_EXTENDED_FSL_INSTR => 0,
C_M0_AXIS_DATA_WIDTH => 32,
C_S0_AXIS_DATA_WIDTH => 32,
C_M1_AXIS_DATA_WIDTH => 32,
C_S1_AXIS_DATA_WIDTH => 32,
C_M2_AXIS_DATA_WIDTH => 32,
C_S2_AXIS_DATA_WIDTH => 32,
C_M3_AXIS_DATA_WIDTH => 32,
C_S3_AXIS_DATA_WIDTH => 32,
C_M4_AXIS_DATA_WIDTH => 32,
C_S4_AXIS_DATA_WIDTH => 32,
C_M5_AXIS_DATA_WIDTH => 32,
C_S5_AXIS_DATA_WIDTH => 32,
C_M6_AXIS_DATA_WIDTH => 32,
C_S6_AXIS_DATA_WIDTH => 32,
C_M7_AXIS_DATA_WIDTH => 32,
C_S7_AXIS_DATA_WIDTH => 32,
C_M8_AXIS_DATA_WIDTH => 32,
C_S8_AXIS_DATA_WIDTH => 32,
C_M9_AXIS_DATA_WIDTH => 32,
C_S9_AXIS_DATA_WIDTH => 32,
C_M10_AXIS_DATA_WIDTH => 32,
C_S10_AXIS_DATA_WIDTH => 32,
C_M11_AXIS_DATA_WIDTH => 32,
C_S11_AXIS_DATA_WIDTH => 32,
C_M12_AXIS_DATA_WIDTH => 32,
C_S12_AXIS_DATA_WIDTH => 32,
C_M13_AXIS_DATA_WIDTH => 32,
C_S13_AXIS_DATA_WIDTH => 32,
C_M14_AXIS_DATA_WIDTH => 32,
C_S14_AXIS_DATA_WIDTH => 32,
C_M15_AXIS_DATA_WIDTH => 32,
C_S15_AXIS_DATA_WIDTH => 32,
C_ICACHE_BASEADDR => X"00000000",
C_ICACHE_HIGHADDR => X"3FFFFFFF",
C_USE_ICACHE => 0,
C_ALLOW_ICACHE_WR => 1,
C_ADDR_TAG_BITS => 0,
C_CACHE_BYTE_SIZE => 8192,
C_ICACHE_USE_FSL => 0,
C_ICACHE_LINE_LEN => 4,
C_ICACHE_ALWAYS_USED => 0,
C_ICACHE_INTERFACE => 0,
C_ICACHE_VICTIMS => 0,
C_ICACHE_STREAMS => 0,
C_ICACHE_FORCE_TAG_LUTRAM => 0,
C_ICACHE_DATA_WIDTH => 0,
C_M_AXI_IC_THREAD_ID_WIDTH => 1,
C_M_AXI_IC_DATA_WIDTH => 32,
C_M_AXI_IC_ADDR_WIDTH => 32,
C_M_AXI_IC_USER_VALUE => 2#11111#,
C_M_AXI_IC_AWUSER_WIDTH => 5,
C_M_AXI_IC_ARUSER_WIDTH => 5,
C_M_AXI_IC_WUSER_WIDTH => 1,
C_M_AXI_IC_RUSER_WIDTH => 1,
C_M_AXI_IC_BUSER_WIDTH => 1,
C_DCACHE_BASEADDR => X"00000000",
C_DCACHE_HIGHADDR => X"3FFFFFFF",
C_USE_DCACHE => 0,
C_ALLOW_DCACHE_WR => 1,
C_DCACHE_ADDR_TAG => 0,
C_DCACHE_BYTE_SIZE => 8192,
C_DCACHE_USE_FSL => 0,
C_DCACHE_LINE_LEN => 4,
C_DCACHE_ALWAYS_USED => 0,
C_DCACHE_INTERFACE => 0,
C_DCACHE_USE_WRITEBACK => 0,
C_DCACHE_VICTIMS => 0,
C_DCACHE_FORCE_TAG_LUTRAM => 0,
C_DCACHE_DATA_WIDTH => 0,
C_M_AXI_DC_THREAD_ID_WIDTH => 1,
C_M_AXI_DC_DATA_WIDTH => 32,
C_M_AXI_DC_ADDR_WIDTH => 32,
C_M_AXI_DC_EXCLUSIVE_ACCESS => 0,
C_M_AXI_DC_USER_VALUE => 2#11111#,
C_M_AXI_DC_AWUSER_WIDTH => 5,
C_M_AXI_DC_ARUSER_WIDTH => 5,
C_M_AXI_DC_WUSER_WIDTH => 1,
C_M_AXI_DC_RUSER_WIDTH => 1,
C_M_AXI_DC_BUSER_WIDTH => 1,
C_USE_MMU => 0,
C_MMU_DTLB_SIZE => 4,
C_MMU_ITLB_SIZE => 2,
C_MMU_TLB_ACCESS => 3,
C_MMU_ZONES => 16,
C_MMU_PRIVILEGED_INSTR => 0,
C_USE_INTERRUPT => 0,
C_USE_EXT_BRK => 1,
C_USE_EXT_NM_BRK => 1,
C_USE_BRANCH_TARGET_CACHE => 0,
C_BRANCH_TARGET_CACHE_SIZE => 0,
C_PC_WIDTH => 32
)
port map (
CLK => CLK,
RESET => RESET,
MB_RESET => MB_RESET,
INTERRUPT => INTERRUPT,
INTERRUPT_ADDRESS => INTERRUPT_ADDRESS,
INTERRUPT_ACK => INTERRUPT_ACK,
EXT_BRK => EXT_BRK,
EXT_NM_BRK => EXT_NM_BRK,
DBG_STOP => DBG_STOP,
MB_Halted => MB_Halted,
MB_Error => MB_Error,
WAKEUP => WAKEUP,
SLEEP => SLEEP,
DBG_WAKEUP => DBG_WAKEUP,
LOCKSTEP_MASTER_OUT => LOCKSTEP_MASTER_OUT,
LOCKSTEP_SLAVE_IN => LOCKSTEP_SLAVE_IN,
LOCKSTEP_OUT => LOCKSTEP_OUT,
INSTR => INSTR,
IREADY => IREADY,
IWAIT => IWAIT,
ICE => ICE,
IUE => IUE,
INSTR_ADDR => INSTR_ADDR,
IFETCH => IFETCH,
I_AS => I_AS,
IPLB_M_ABort => IPLB_M_ABort,
IPLB_M_ABus => IPLB_M_ABus,
IPLB_M_UABus => IPLB_M_UABus,
IPLB_M_BE => IPLB_M_BE,
IPLB_M_busLock => IPLB_M_busLock,
IPLB_M_lockErr => IPLB_M_lockErr,
IPLB_M_MSize => IPLB_M_MSize,
IPLB_M_priority => IPLB_M_priority,
IPLB_M_rdBurst => IPLB_M_rdBurst,
IPLB_M_request => IPLB_M_request,
IPLB_M_RNW => IPLB_M_RNW,
IPLB_M_size => IPLB_M_size,
IPLB_M_TAttribute => IPLB_M_TAttribute,
IPLB_M_type => IPLB_M_type,
IPLB_M_wrBurst => IPLB_M_wrBurst,
IPLB_M_wrDBus => IPLB_M_wrDBus,
IPLB_MBusy => IPLB_MBusy,
IPLB_MRdErr => IPLB_MRdErr,
IPLB_MWrErr => IPLB_MWrErr,
IPLB_MIRQ => IPLB_MIRQ,
IPLB_MWrBTerm => IPLB_MWrBTerm,
IPLB_MWrDAck => IPLB_MWrDAck,
IPLB_MAddrAck => IPLB_MAddrAck,
IPLB_MRdBTerm => IPLB_MRdBTerm,
IPLB_MRdDAck => IPLB_MRdDAck,
IPLB_MRdDBus => IPLB_MRdDBus,
IPLB_MRdWdAddr => IPLB_MRdWdAddr,
IPLB_MRearbitrate => IPLB_MRearbitrate,
IPLB_MSSize => IPLB_MSSize,
IPLB_MTimeout => IPLB_MTimeout,
DATA_READ => DATA_READ,
DREADY => DREADY,
DWAIT => DWAIT,
DCE => DCE,
DUE => DUE,
DATA_WRITE => DATA_WRITE,
DATA_ADDR => DATA_ADDR,
D_AS => D_AS,
READ_STROBE => READ_STROBE,
WRITE_STROBE => WRITE_STROBE,
BYTE_ENABLE => BYTE_ENABLE,
DPLB_M_ABort => DPLB_M_ABort,
DPLB_M_ABus => DPLB_M_ABus,
DPLB_M_UABus => DPLB_M_UABus,
DPLB_M_BE => DPLB_M_BE,
DPLB_M_busLock => DPLB_M_busLock,
DPLB_M_lockErr => DPLB_M_lockErr,
DPLB_M_MSize => DPLB_M_MSize,
DPLB_M_priority => DPLB_M_priority,
DPLB_M_rdBurst => DPLB_M_rdBurst,
DPLB_M_request => DPLB_M_request,
DPLB_M_RNW => DPLB_M_RNW,
DPLB_M_size => DPLB_M_size,
DPLB_M_TAttribute => DPLB_M_TAttribute,
DPLB_M_type => DPLB_M_type,
DPLB_M_wrBurst => DPLB_M_wrBurst,
DPLB_M_wrDBus => DPLB_M_wrDBus,
DPLB_MBusy => DPLB_MBusy,
DPLB_MRdErr => DPLB_MRdErr,
DPLB_MWrErr => DPLB_MWrErr,
DPLB_MIRQ => DPLB_MIRQ,
DPLB_MWrBTerm => DPLB_MWrBTerm,
DPLB_MWrDAck => DPLB_MWrDAck,
DPLB_MAddrAck => DPLB_MAddrAck,
DPLB_MRdBTerm => DPLB_MRdBTerm,
DPLB_MRdDAck => DPLB_MRdDAck,
DPLB_MRdDBus => DPLB_MRdDBus,
DPLB_MRdWdAddr => DPLB_MRdWdAddr,
DPLB_MRearbitrate => DPLB_MRearbitrate,
DPLB_MSSize => DPLB_MSSize,
DPLB_MTimeout => DPLB_MTimeout,
M_AXI_IP_AWID => M_AXI_IP_AWID,
M_AXI_IP_AWADDR => M_AXI_IP_AWADDR,
M_AXI_IP_AWLEN => M_AXI_IP_AWLEN,
M_AXI_IP_AWSIZE => M_AXI_IP_AWSIZE,
M_AXI_IP_AWBURST => M_AXI_IP_AWBURST,
M_AXI_IP_AWLOCK => M_AXI_IP_AWLOCK,
M_AXI_IP_AWCACHE => M_AXI_IP_AWCACHE,
M_AXI_IP_AWPROT => M_AXI_IP_AWPROT,
M_AXI_IP_AWQOS => M_AXI_IP_AWQOS,
M_AXI_IP_AWVALID => M_AXI_IP_AWVALID,
M_AXI_IP_AWREADY => M_AXI_IP_AWREADY,
M_AXI_IP_WDATA => M_AXI_IP_WDATA,
M_AXI_IP_WSTRB => M_AXI_IP_WSTRB,
M_AXI_IP_WLAST => M_AXI_IP_WLAST,
M_AXI_IP_WVALID => M_AXI_IP_WVALID,
M_AXI_IP_WREADY => M_AXI_IP_WREADY,
M_AXI_IP_BID => M_AXI_IP_BID,
M_AXI_IP_BRESP => M_AXI_IP_BRESP,
M_AXI_IP_BVALID => M_AXI_IP_BVALID,
M_AXI_IP_BREADY => M_AXI_IP_BREADY,
M_AXI_IP_ARID => M_AXI_IP_ARID,
M_AXI_IP_ARADDR => M_AXI_IP_ARADDR,
M_AXI_IP_ARLEN => M_AXI_IP_ARLEN,
M_AXI_IP_ARSIZE => M_AXI_IP_ARSIZE,
M_AXI_IP_ARBURST => M_AXI_IP_ARBURST,
M_AXI_IP_ARLOCK => M_AXI_IP_ARLOCK,
M_AXI_IP_ARCACHE => M_AXI_IP_ARCACHE,
M_AXI_IP_ARPROT => M_AXI_IP_ARPROT,
M_AXI_IP_ARQOS => M_AXI_IP_ARQOS,
M_AXI_IP_ARVALID => M_AXI_IP_ARVALID,
M_AXI_IP_ARREADY => M_AXI_IP_ARREADY,
M_AXI_IP_RID => M_AXI_IP_RID,
M_AXI_IP_RDATA => M_AXI_IP_RDATA,
M_AXI_IP_RRESP => M_AXI_IP_RRESP,
M_AXI_IP_RLAST => M_AXI_IP_RLAST,
M_AXI_IP_RVALID => M_AXI_IP_RVALID,
M_AXI_IP_RREADY => M_AXI_IP_RREADY,
M_AXI_DP_AWID => M_AXI_DP_AWID,
M_AXI_DP_AWADDR => M_AXI_DP_AWADDR,
M_AXI_DP_AWLEN => M_AXI_DP_AWLEN,
M_AXI_DP_AWSIZE => M_AXI_DP_AWSIZE,
M_AXI_DP_AWBURST => M_AXI_DP_AWBURST,
M_AXI_DP_AWLOCK => M_AXI_DP_AWLOCK,
M_AXI_DP_AWCACHE => M_AXI_DP_AWCACHE,
M_AXI_DP_AWPROT => M_AXI_DP_AWPROT,
M_AXI_DP_AWQOS => M_AXI_DP_AWQOS,
M_AXI_DP_AWVALID => M_AXI_DP_AWVALID,
M_AXI_DP_AWREADY => M_AXI_DP_AWREADY,
M_AXI_DP_WDATA => M_AXI_DP_WDATA,
M_AXI_DP_WSTRB => M_AXI_DP_WSTRB,
M_AXI_DP_WLAST => M_AXI_DP_WLAST,
M_AXI_DP_WVALID => M_AXI_DP_WVALID,
M_AXI_DP_WREADY => M_AXI_DP_WREADY,
M_AXI_DP_BID => M_AXI_DP_BID,
M_AXI_DP_BRESP => M_AXI_DP_BRESP,
M_AXI_DP_BVALID => M_AXI_DP_BVALID,
M_AXI_DP_BREADY => M_AXI_DP_BREADY,
M_AXI_DP_ARID => M_AXI_DP_ARID,
M_AXI_DP_ARADDR => M_AXI_DP_ARADDR,
M_AXI_DP_ARLEN => M_AXI_DP_ARLEN,
M_AXI_DP_ARSIZE => M_AXI_DP_ARSIZE,
M_AXI_DP_ARBURST => M_AXI_DP_ARBURST,
M_AXI_DP_ARLOCK => M_AXI_DP_ARLOCK,
M_AXI_DP_ARCACHE => M_AXI_DP_ARCACHE,
M_AXI_DP_ARPROT => M_AXI_DP_ARPROT,
M_AXI_DP_ARQOS => M_AXI_DP_ARQOS,
M_AXI_DP_ARVALID => M_AXI_DP_ARVALID,
M_AXI_DP_ARREADY => M_AXI_DP_ARREADY,
M_AXI_DP_RID => M_AXI_DP_RID,
M_AXI_DP_RDATA => M_AXI_DP_RDATA,
M_AXI_DP_RRESP => M_AXI_DP_RRESP,
M_AXI_DP_RLAST => M_AXI_DP_RLAST,
M_AXI_DP_RVALID => M_AXI_DP_RVALID,
M_AXI_DP_RREADY => M_AXI_DP_RREADY,
M_AXI_IC_AWID => M_AXI_IC_AWID,
M_AXI_IC_AWADDR => M_AXI_IC_AWADDR,
M_AXI_IC_AWLEN => M_AXI_IC_AWLEN,
M_AXI_IC_AWSIZE => M_AXI_IC_AWSIZE,
M_AXI_IC_AWBURST => M_AXI_IC_AWBURST,
M_AXI_IC_AWLOCK => M_AXI_IC_AWLOCK,
M_AXI_IC_AWCACHE => M_AXI_IC_AWCACHE,
M_AXI_IC_AWPROT => M_AXI_IC_AWPROT,
M_AXI_IC_AWQOS => M_AXI_IC_AWQOS,
M_AXI_IC_AWVALID => M_AXI_IC_AWVALID,
M_AXI_IC_AWREADY => M_AXI_IC_AWREADY,
M_AXI_IC_AWUSER => M_AXI_IC_AWUSER,
M_AXI_IC_WDATA => M_AXI_IC_WDATA,
M_AXI_IC_WSTRB => M_AXI_IC_WSTRB,
M_AXI_IC_WLAST => M_AXI_IC_WLAST,
M_AXI_IC_WVALID => M_AXI_IC_WVALID,
M_AXI_IC_WREADY => M_AXI_IC_WREADY,
M_AXI_IC_WUSER => M_AXI_IC_WUSER,
M_AXI_IC_BID => M_AXI_IC_BID,
M_AXI_IC_BRESP => M_AXI_IC_BRESP,
M_AXI_IC_BVALID => M_AXI_IC_BVALID,
M_AXI_IC_BREADY => M_AXI_IC_BREADY,
M_AXI_IC_BUSER => M_AXI_IC_BUSER,
M_AXI_IC_ARID => M_AXI_IC_ARID,
M_AXI_IC_ARADDR => M_AXI_IC_ARADDR,
M_AXI_IC_ARLEN => M_AXI_IC_ARLEN,
M_AXI_IC_ARSIZE => M_AXI_IC_ARSIZE,
M_AXI_IC_ARBURST => M_AXI_IC_ARBURST,
M_AXI_IC_ARLOCK => M_AXI_IC_ARLOCK,
M_AXI_IC_ARCACHE => M_AXI_IC_ARCACHE,
M_AXI_IC_ARPROT => M_AXI_IC_ARPROT,
M_AXI_IC_ARQOS => M_AXI_IC_ARQOS,
M_AXI_IC_ARVALID => M_AXI_IC_ARVALID,
M_AXI_IC_ARREADY => M_AXI_IC_ARREADY,
M_AXI_IC_ARUSER => M_AXI_IC_ARUSER,
M_AXI_IC_RID => M_AXI_IC_RID,
M_AXI_IC_RDATA => M_AXI_IC_RDATA,
M_AXI_IC_RRESP => M_AXI_IC_RRESP,
M_AXI_IC_RLAST => M_AXI_IC_RLAST,
M_AXI_IC_RVALID => M_AXI_IC_RVALID,
M_AXI_IC_RREADY => M_AXI_IC_RREADY,
M_AXI_IC_RUSER => M_AXI_IC_RUSER,
M_AXI_DC_AWID => M_AXI_DC_AWID,
M_AXI_DC_AWADDR => M_AXI_DC_AWADDR,
M_AXI_DC_AWLEN => M_AXI_DC_AWLEN,
M_AXI_DC_AWSIZE => M_AXI_DC_AWSIZE,
M_AXI_DC_AWBURST => M_AXI_DC_AWBURST,
M_AXI_DC_AWLOCK => M_AXI_DC_AWLOCK,
M_AXI_DC_AWCACHE => M_AXI_DC_AWCACHE,
M_AXI_DC_AWPROT => M_AXI_DC_AWPROT,
M_AXI_DC_AWQOS => M_AXI_DC_AWQOS,
M_AXI_DC_AWVALID => M_AXI_DC_AWVALID,
M_AXI_DC_AWREADY => M_AXI_DC_AWREADY,
M_AXI_DC_AWUSER => M_AXI_DC_AWUSER,
M_AXI_DC_WDATA => M_AXI_DC_WDATA,
M_AXI_DC_WSTRB => M_AXI_DC_WSTRB,
M_AXI_DC_WLAST => M_AXI_DC_WLAST,
M_AXI_DC_WVALID => M_AXI_DC_WVALID,
M_AXI_DC_WREADY => M_AXI_DC_WREADY,
M_AXI_DC_WUSER => M_AXI_DC_WUSER,
M_AXI_DC_BID => M_AXI_DC_BID,
M_AXI_DC_BRESP => M_AXI_DC_BRESP,
M_AXI_DC_BVALID => M_AXI_DC_BVALID,
M_AXI_DC_BREADY => M_AXI_DC_BREADY,
M_AXI_DC_BUSER => M_AXI_DC_BUSER,
M_AXI_DC_ARID => M_AXI_DC_ARID,
M_AXI_DC_ARADDR => M_AXI_DC_ARADDR,
M_AXI_DC_ARLEN => M_AXI_DC_ARLEN,
M_AXI_DC_ARSIZE => M_AXI_DC_ARSIZE,
M_AXI_DC_ARBURST => M_AXI_DC_ARBURST,
M_AXI_DC_ARLOCK => M_AXI_DC_ARLOCK,
M_AXI_DC_ARCACHE => M_AXI_DC_ARCACHE,
M_AXI_DC_ARPROT => M_AXI_DC_ARPROT,
M_AXI_DC_ARQOS => M_AXI_DC_ARQOS,
M_AXI_DC_ARVALID => M_AXI_DC_ARVALID,
M_AXI_DC_ARREADY => M_AXI_DC_ARREADY,
M_AXI_DC_ARUSER => M_AXI_DC_ARUSER,
M_AXI_DC_RID => M_AXI_DC_RID,
M_AXI_DC_RDATA => M_AXI_DC_RDATA,
M_AXI_DC_RRESP => M_AXI_DC_RRESP,
M_AXI_DC_RLAST => M_AXI_DC_RLAST,
M_AXI_DC_RVALID => M_AXI_DC_RVALID,
M_AXI_DC_RREADY => M_AXI_DC_RREADY,
M_AXI_DC_RUSER => M_AXI_DC_RUSER,
DBG_CLK => DBG_CLK,
DBG_TDI => DBG_TDI,
DBG_TDO => DBG_TDO,
DBG_REG_EN => DBG_REG_EN,
DBG_SHIFT => DBG_SHIFT,
DBG_CAPTURE => DBG_CAPTURE,
DBG_UPDATE => DBG_UPDATE,
DEBUG_RST => DEBUG_RST,
Trace_Instruction => Trace_Instruction,
Trace_Valid_Instr => Trace_Valid_Instr,
Trace_PC => Trace_PC,
Trace_Reg_Write => Trace_Reg_Write,
Trace_Reg_Addr => Trace_Reg_Addr,
Trace_MSR_Reg => Trace_MSR_Reg,
Trace_PID_Reg => Trace_PID_Reg,
Trace_New_Reg_Value => Trace_New_Reg_Value,
Trace_Exception_Taken => Trace_Exception_Taken,
Trace_Exception_Kind => Trace_Exception_Kind,
Trace_Jump_Taken => Trace_Jump_Taken,
Trace_Delay_Slot => Trace_Delay_Slot,
Trace_Data_Address => Trace_Data_Address,
Trace_Data_Access => Trace_Data_Access,
Trace_Data_Read => Trace_Data_Read,
Trace_Data_Write => Trace_Data_Write,
Trace_Data_Write_Value => Trace_Data_Write_Value,
Trace_Data_Byte_Enable => Trace_Data_Byte_Enable,
Trace_DCache_Req => Trace_DCache_Req,
Trace_DCache_Hit => Trace_DCache_Hit,
Trace_DCache_Rdy => Trace_DCache_Rdy,
Trace_DCache_Read => Trace_DCache_Read,
Trace_ICache_Req => Trace_ICache_Req,
Trace_ICache_Hit => Trace_ICache_Hit,
Trace_ICache_Rdy => Trace_ICache_Rdy,
Trace_OF_PipeRun => Trace_OF_PipeRun,
Trace_EX_PipeRun => Trace_EX_PipeRun,
Trace_MEM_PipeRun => Trace_MEM_PipeRun,
Trace_MB_Halted => Trace_MB_Halted,
Trace_Jump_Hit => Trace_Jump_Hit,
FSL0_S_CLK => FSL0_S_CLK,
FSL0_S_READ => FSL0_S_READ,
FSL0_S_DATA => FSL0_S_DATA,
FSL0_S_CONTROL => FSL0_S_CONTROL,
FSL0_S_EXISTS => FSL0_S_EXISTS,
FSL0_M_CLK => FSL0_M_CLK,
FSL0_M_WRITE => FSL0_M_WRITE,
FSL0_M_DATA => FSL0_M_DATA,
FSL0_M_CONTROL => FSL0_M_CONTROL,
FSL0_M_FULL => FSL0_M_FULL,
FSL1_S_CLK => FSL1_S_CLK,
FSL1_S_READ => FSL1_S_READ,
FSL1_S_DATA => FSL1_S_DATA,
FSL1_S_CONTROL => FSL1_S_CONTROL,
FSL1_S_EXISTS => FSL1_S_EXISTS,
FSL1_M_CLK => FSL1_M_CLK,
FSL1_M_WRITE => FSL1_M_WRITE,
FSL1_M_DATA => FSL1_M_DATA,
FSL1_M_CONTROL => FSL1_M_CONTROL,
FSL1_M_FULL => FSL1_M_FULL,
FSL2_S_CLK => FSL2_S_CLK,
FSL2_S_READ => FSL2_S_READ,
FSL2_S_DATA => FSL2_S_DATA,
FSL2_S_CONTROL => FSL2_S_CONTROL,
FSL2_S_EXISTS => FSL2_S_EXISTS,
FSL2_M_CLK => FSL2_M_CLK,
FSL2_M_WRITE => FSL2_M_WRITE,
FSL2_M_DATA => FSL2_M_DATA,
FSL2_M_CONTROL => FSL2_M_CONTROL,
FSL2_M_FULL => FSL2_M_FULL,
FSL3_S_CLK => FSL3_S_CLK,
FSL3_S_READ => FSL3_S_READ,
FSL3_S_DATA => FSL3_S_DATA,
FSL3_S_CONTROL => FSL3_S_CONTROL,
FSL3_S_EXISTS => FSL3_S_EXISTS,
FSL3_M_CLK => FSL3_M_CLK,
FSL3_M_WRITE => FSL3_M_WRITE,
FSL3_M_DATA => FSL3_M_DATA,
FSL3_M_CONTROL => FSL3_M_CONTROL,
FSL3_M_FULL => FSL3_M_FULL,
FSL4_S_CLK => FSL4_S_CLK,
FSL4_S_READ => FSL4_S_READ,
FSL4_S_DATA => FSL4_S_DATA,
FSL4_S_CONTROL => FSL4_S_CONTROL,
FSL4_S_EXISTS => FSL4_S_EXISTS,
FSL4_M_CLK => FSL4_M_CLK,
FSL4_M_WRITE => FSL4_M_WRITE,
FSL4_M_DATA => FSL4_M_DATA,
FSL4_M_CONTROL => FSL4_M_CONTROL,
FSL4_M_FULL => FSL4_M_FULL,
FSL5_S_CLK => FSL5_S_CLK,
FSL5_S_READ => FSL5_S_READ,
FSL5_S_DATA => FSL5_S_DATA,
FSL5_S_CONTROL => FSL5_S_CONTROL,
FSL5_S_EXISTS => FSL5_S_EXISTS,
FSL5_M_CLK => FSL5_M_CLK,
FSL5_M_WRITE => FSL5_M_WRITE,
FSL5_M_DATA => FSL5_M_DATA,
FSL5_M_CONTROL => FSL5_M_CONTROL,
FSL5_M_FULL => FSL5_M_FULL,
FSL6_S_CLK => FSL6_S_CLK,
FSL6_S_READ => FSL6_S_READ,
FSL6_S_DATA => FSL6_S_DATA,
FSL6_S_CONTROL => FSL6_S_CONTROL,
FSL6_S_EXISTS => FSL6_S_EXISTS,
FSL6_M_CLK => FSL6_M_CLK,
FSL6_M_WRITE => FSL6_M_WRITE,
FSL6_M_DATA => FSL6_M_DATA,
FSL6_M_CONTROL => FSL6_M_CONTROL,
FSL6_M_FULL => FSL6_M_FULL,
FSL7_S_CLK => FSL7_S_CLK,
FSL7_S_READ => FSL7_S_READ,
FSL7_S_DATA => FSL7_S_DATA,
FSL7_S_CONTROL => FSL7_S_CONTROL,
FSL7_S_EXISTS => FSL7_S_EXISTS,
FSL7_M_CLK => FSL7_M_CLK,
FSL7_M_WRITE => FSL7_M_WRITE,
FSL7_M_DATA => FSL7_M_DATA,
FSL7_M_CONTROL => FSL7_M_CONTROL,
FSL7_M_FULL => FSL7_M_FULL,
FSL8_S_CLK => FSL8_S_CLK,
FSL8_S_READ => FSL8_S_READ,
FSL8_S_DATA => FSL8_S_DATA,
FSL8_S_CONTROL => FSL8_S_CONTROL,
FSL8_S_EXISTS => FSL8_S_EXISTS,
FSL8_M_CLK => FSL8_M_CLK,
FSL8_M_WRITE => FSL8_M_WRITE,
FSL8_M_DATA => FSL8_M_DATA,
FSL8_M_CONTROL => FSL8_M_CONTROL,
FSL8_M_FULL => FSL8_M_FULL,
FSL9_S_CLK => FSL9_S_CLK,
FSL9_S_READ => FSL9_S_READ,
FSL9_S_DATA => FSL9_S_DATA,
FSL9_S_CONTROL => FSL9_S_CONTROL,
FSL9_S_EXISTS => FSL9_S_EXISTS,
FSL9_M_CLK => FSL9_M_CLK,
FSL9_M_WRITE => FSL9_M_WRITE,
FSL9_M_DATA => FSL9_M_DATA,
FSL9_M_CONTROL => FSL9_M_CONTROL,
FSL9_M_FULL => FSL9_M_FULL,
FSL10_S_CLK => FSL10_S_CLK,
FSL10_S_READ => FSL10_S_READ,
FSL10_S_DATA => FSL10_S_DATA,
FSL10_S_CONTROL => FSL10_S_CONTROL,
FSL10_S_EXISTS => FSL10_S_EXISTS,
FSL10_M_CLK => FSL10_M_CLK,
FSL10_M_WRITE => FSL10_M_WRITE,
FSL10_M_DATA => FSL10_M_DATA,
FSL10_M_CONTROL => FSL10_M_CONTROL,
FSL10_M_FULL => FSL10_M_FULL,
FSL11_S_CLK => FSL11_S_CLK,
FSL11_S_READ => FSL11_S_READ,
FSL11_S_DATA => FSL11_S_DATA,
FSL11_S_CONTROL => FSL11_S_CONTROL,
FSL11_S_EXISTS => FSL11_S_EXISTS,
FSL11_M_CLK => FSL11_M_CLK,
FSL11_M_WRITE => FSL11_M_WRITE,
FSL11_M_DATA => FSL11_M_DATA,
FSL11_M_CONTROL => FSL11_M_CONTROL,
FSL11_M_FULL => FSL11_M_FULL,
FSL12_S_CLK => FSL12_S_CLK,
FSL12_S_READ => FSL12_S_READ,
FSL12_S_DATA => FSL12_S_DATA,
FSL12_S_CONTROL => FSL12_S_CONTROL,
FSL12_S_EXISTS => FSL12_S_EXISTS,
FSL12_M_CLK => FSL12_M_CLK,
FSL12_M_WRITE => FSL12_M_WRITE,
FSL12_M_DATA => FSL12_M_DATA,
FSL12_M_CONTROL => FSL12_M_CONTROL,
FSL12_M_FULL => FSL12_M_FULL,
FSL13_S_CLK => FSL13_S_CLK,
FSL13_S_READ => FSL13_S_READ,
FSL13_S_DATA => FSL13_S_DATA,
FSL13_S_CONTROL => FSL13_S_CONTROL,
FSL13_S_EXISTS => FSL13_S_EXISTS,
FSL13_M_CLK => FSL13_M_CLK,
FSL13_M_WRITE => FSL13_M_WRITE,
FSL13_M_DATA => FSL13_M_DATA,
FSL13_M_CONTROL => FSL13_M_CONTROL,
FSL13_M_FULL => FSL13_M_FULL,
FSL14_S_CLK => FSL14_S_CLK,
FSL14_S_READ => FSL14_S_READ,
FSL14_S_DATA => FSL14_S_DATA,
FSL14_S_CONTROL => FSL14_S_CONTROL,
FSL14_S_EXISTS => FSL14_S_EXISTS,
FSL14_M_CLK => FSL14_M_CLK,
FSL14_M_WRITE => FSL14_M_WRITE,
FSL14_M_DATA => FSL14_M_DATA,
FSL14_M_CONTROL => FSL14_M_CONTROL,
FSL14_M_FULL => FSL14_M_FULL,
FSL15_S_CLK => FSL15_S_CLK,
FSL15_S_READ => FSL15_S_READ,
FSL15_S_DATA => FSL15_S_DATA,
FSL15_S_CONTROL => FSL15_S_CONTROL,
FSL15_S_EXISTS => FSL15_S_EXISTS,
FSL15_M_CLK => FSL15_M_CLK,
FSL15_M_WRITE => FSL15_M_WRITE,
FSL15_M_DATA => FSL15_M_DATA,
FSL15_M_CONTROL => FSL15_M_CONTROL,
FSL15_M_FULL => FSL15_M_FULL,
M0_AXIS_TLAST => M0_AXIS_TLAST,
M0_AXIS_TDATA => M0_AXIS_TDATA,
M0_AXIS_TVALID => M0_AXIS_TVALID,
M0_AXIS_TREADY => M0_AXIS_TREADY,
S0_AXIS_TLAST => S0_AXIS_TLAST,
S0_AXIS_TDATA => S0_AXIS_TDATA,
S0_AXIS_TVALID => S0_AXIS_TVALID,
S0_AXIS_TREADY => S0_AXIS_TREADY,
M1_AXIS_TLAST => M1_AXIS_TLAST,
M1_AXIS_TDATA => M1_AXIS_TDATA,
M1_AXIS_TVALID => M1_AXIS_TVALID,
M1_AXIS_TREADY => M1_AXIS_TREADY,
S1_AXIS_TLAST => S1_AXIS_TLAST,
S1_AXIS_TDATA => S1_AXIS_TDATA,
S1_AXIS_TVALID => S1_AXIS_TVALID,
S1_AXIS_TREADY => S1_AXIS_TREADY,
M2_AXIS_TLAST => M2_AXIS_TLAST,
M2_AXIS_TDATA => M2_AXIS_TDATA,
M2_AXIS_TVALID => M2_AXIS_TVALID,
M2_AXIS_TREADY => M2_AXIS_TREADY,
S2_AXIS_TLAST => S2_AXIS_TLAST,
S2_AXIS_TDATA => S2_AXIS_TDATA,
S2_AXIS_TVALID => S2_AXIS_TVALID,
S2_AXIS_TREADY => S2_AXIS_TREADY,
M3_AXIS_TLAST => M3_AXIS_TLAST,
M3_AXIS_TDATA => M3_AXIS_TDATA,
M3_AXIS_TVALID => M3_AXIS_TVALID,
M3_AXIS_TREADY => M3_AXIS_TREADY,
S3_AXIS_TLAST => S3_AXIS_TLAST,
S3_AXIS_TDATA => S3_AXIS_TDATA,
S3_AXIS_TVALID => S3_AXIS_TVALID,
S3_AXIS_TREADY => S3_AXIS_TREADY,
M4_AXIS_TLAST => M4_AXIS_TLAST,
M4_AXIS_TDATA => M4_AXIS_TDATA,
M4_AXIS_TVALID => M4_AXIS_TVALID,
M4_AXIS_TREADY => M4_AXIS_TREADY,
S4_AXIS_TLAST => S4_AXIS_TLAST,
S4_AXIS_TDATA => S4_AXIS_TDATA,
S4_AXIS_TVALID => S4_AXIS_TVALID,
S4_AXIS_TREADY => S4_AXIS_TREADY,
M5_AXIS_TLAST => M5_AXIS_TLAST,
M5_AXIS_TDATA => M5_AXIS_TDATA,
M5_AXIS_TVALID => M5_AXIS_TVALID,
M5_AXIS_TREADY => M5_AXIS_TREADY,
S5_AXIS_TLAST => S5_AXIS_TLAST,
S5_AXIS_TDATA => S5_AXIS_TDATA,
S5_AXIS_TVALID => S5_AXIS_TVALID,
S5_AXIS_TREADY => S5_AXIS_TREADY,
M6_AXIS_TLAST => M6_AXIS_TLAST,
M6_AXIS_TDATA => M6_AXIS_TDATA,
M6_AXIS_TVALID => M6_AXIS_TVALID,
M6_AXIS_TREADY => M6_AXIS_TREADY,
S6_AXIS_TLAST => S6_AXIS_TLAST,
S6_AXIS_TDATA => S6_AXIS_TDATA,
S6_AXIS_TVALID => S6_AXIS_TVALID,
S6_AXIS_TREADY => S6_AXIS_TREADY,
M7_AXIS_TLAST => M7_AXIS_TLAST,
M7_AXIS_TDATA => M7_AXIS_TDATA,
M7_AXIS_TVALID => M7_AXIS_TVALID,
M7_AXIS_TREADY => M7_AXIS_TREADY,
S7_AXIS_TLAST => S7_AXIS_TLAST,
S7_AXIS_TDATA => S7_AXIS_TDATA,
S7_AXIS_TVALID => S7_AXIS_TVALID,
S7_AXIS_TREADY => S7_AXIS_TREADY,
M8_AXIS_TLAST => M8_AXIS_TLAST,
M8_AXIS_TDATA => M8_AXIS_TDATA,
M8_AXIS_TVALID => M8_AXIS_TVALID,
M8_AXIS_TREADY => M8_AXIS_TREADY,
S8_AXIS_TLAST => S8_AXIS_TLAST,
S8_AXIS_TDATA => S8_AXIS_TDATA,
S8_AXIS_TVALID => S8_AXIS_TVALID,
S8_AXIS_TREADY => S8_AXIS_TREADY,
M9_AXIS_TLAST => M9_AXIS_TLAST,
M9_AXIS_TDATA => M9_AXIS_TDATA,
M9_AXIS_TVALID => M9_AXIS_TVALID,
M9_AXIS_TREADY => M9_AXIS_TREADY,
S9_AXIS_TLAST => S9_AXIS_TLAST,
S9_AXIS_TDATA => S9_AXIS_TDATA,
S9_AXIS_TVALID => S9_AXIS_TVALID,
S9_AXIS_TREADY => S9_AXIS_TREADY,
M10_AXIS_TLAST => M10_AXIS_TLAST,
M10_AXIS_TDATA => M10_AXIS_TDATA,
M10_AXIS_TVALID => M10_AXIS_TVALID,
M10_AXIS_TREADY => M10_AXIS_TREADY,
S10_AXIS_TLAST => S10_AXIS_TLAST,
S10_AXIS_TDATA => S10_AXIS_TDATA,
S10_AXIS_TVALID => S10_AXIS_TVALID,
S10_AXIS_TREADY => S10_AXIS_TREADY,
M11_AXIS_TLAST => M11_AXIS_TLAST,
M11_AXIS_TDATA => M11_AXIS_TDATA,
M11_AXIS_TVALID => M11_AXIS_TVALID,
M11_AXIS_TREADY => M11_AXIS_TREADY,
S11_AXIS_TLAST => S11_AXIS_TLAST,
S11_AXIS_TDATA => S11_AXIS_TDATA,
S11_AXIS_TVALID => S11_AXIS_TVALID,
S11_AXIS_TREADY => S11_AXIS_TREADY,
M12_AXIS_TLAST => M12_AXIS_TLAST,
M12_AXIS_TDATA => M12_AXIS_TDATA,
M12_AXIS_TVALID => M12_AXIS_TVALID,
M12_AXIS_TREADY => M12_AXIS_TREADY,
S12_AXIS_TLAST => S12_AXIS_TLAST,
S12_AXIS_TDATA => S12_AXIS_TDATA,
S12_AXIS_TVALID => S12_AXIS_TVALID,
S12_AXIS_TREADY => S12_AXIS_TREADY,
M13_AXIS_TLAST => M13_AXIS_TLAST,
M13_AXIS_TDATA => M13_AXIS_TDATA,
M13_AXIS_TVALID => M13_AXIS_TVALID,
M13_AXIS_TREADY => M13_AXIS_TREADY,
S13_AXIS_TLAST => S13_AXIS_TLAST,
S13_AXIS_TDATA => S13_AXIS_TDATA,
S13_AXIS_TVALID => S13_AXIS_TVALID,
S13_AXIS_TREADY => S13_AXIS_TREADY,
M14_AXIS_TLAST => M14_AXIS_TLAST,
M14_AXIS_TDATA => M14_AXIS_TDATA,
M14_AXIS_TVALID => M14_AXIS_TVALID,
M14_AXIS_TREADY => M14_AXIS_TREADY,
S14_AXIS_TLAST => S14_AXIS_TLAST,
S14_AXIS_TDATA => S14_AXIS_TDATA,
S14_AXIS_TVALID => S14_AXIS_TVALID,
S14_AXIS_TREADY => S14_AXIS_TREADY,
M15_AXIS_TLAST => M15_AXIS_TLAST,
M15_AXIS_TDATA => M15_AXIS_TDATA,
M15_AXIS_TVALID => M15_AXIS_TVALID,
M15_AXIS_TREADY => M15_AXIS_TREADY,
S15_AXIS_TLAST => S15_AXIS_TLAST,
S15_AXIS_TDATA => S15_AXIS_TDATA,
S15_AXIS_TVALID => S15_AXIS_TVALID,
S15_AXIS_TREADY => S15_AXIS_TREADY,
ICACHE_FSL_IN_CLK => ICACHE_FSL_IN_CLK,
ICACHE_FSL_IN_READ => ICACHE_FSL_IN_READ,
ICACHE_FSL_IN_DATA => ICACHE_FSL_IN_DATA,
ICACHE_FSL_IN_CONTROL => ICACHE_FSL_IN_CONTROL,
ICACHE_FSL_IN_EXISTS => ICACHE_FSL_IN_EXISTS,
ICACHE_FSL_OUT_CLK => ICACHE_FSL_OUT_CLK,
ICACHE_FSL_OUT_WRITE => ICACHE_FSL_OUT_WRITE,
ICACHE_FSL_OUT_DATA => ICACHE_FSL_OUT_DATA,
ICACHE_FSL_OUT_CONTROL => ICACHE_FSL_OUT_CONTROL,
ICACHE_FSL_OUT_FULL => ICACHE_FSL_OUT_FULL,
DCACHE_FSL_IN_CLK => DCACHE_FSL_IN_CLK,
DCACHE_FSL_IN_READ => DCACHE_FSL_IN_READ,
DCACHE_FSL_IN_DATA => DCACHE_FSL_IN_DATA,
DCACHE_FSL_IN_CONTROL => DCACHE_FSL_IN_CONTROL,
DCACHE_FSL_IN_EXISTS => DCACHE_FSL_IN_EXISTS,
DCACHE_FSL_OUT_CLK => DCACHE_FSL_OUT_CLK,
DCACHE_FSL_OUT_WRITE => DCACHE_FSL_OUT_WRITE,
DCACHE_FSL_OUT_DATA => DCACHE_FSL_OUT_DATA,
DCACHE_FSL_OUT_CONTROL => DCACHE_FSL_OUT_CONTROL,
DCACHE_FSL_OUT_FULL => DCACHE_FSL_OUT_FULL
);
end architecture STRUCTURE;
|
mit
|
Nooxet/embedded_bruteforce
|
brutus_system/pcores/ready4hood_v1_00_a/hdl/vhdl/ready4hood.vhd
|
1
|
3091
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ready4hood is
port
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
FSL_Clk : in std_logic;
FSL_Rst : in std_logic;
FSL_S_Clk : in std_logic;
FSL_S_Read : out std_logic;
FSL_S_Data : in std_logic_vector(0 to 31);
FSL_S_Control : in std_logic;
FSL_S_Exists : in std_logic;
FSL_M_Clk : in std_logic;
FSL_M_Write : out std_logic;
FSL_M_Data : out std_logic_vector(0 to 31);
FSL_M_Control : out std_logic;
FSL_M_Full : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of FSL_Clk : signal is "Clk";
attribute SIGIS of FSL_S_Clk : signal is "Clk";
attribute SIGIS of FSL_M_Clk : signal is "Clk";
end ready4hood;
architecture EXAMPLE of ready4hood is
-- Total number of input data.
constant NUMBER_OF_INPUT_WORDS : natural := 4;
-- Total number of output data
constant NUMBER_OF_OUTPUT_WORDS : natural := 1;
type STATE_TYPE is (Idle, Read_Inputs, Write_Outputs);
signal state : STATE_TYPE;
-- Accumulator to hold sum of inputs read at any point in time
signal sum : std_logic_vector(0 to 31);
-- Counters to store the number inputs read & outputs written
signal nr_of_reads : natural range 0 to NUMBER_OF_INPUT_WORDS - 1;
signal nr_of_writes : natural range 0 to NUMBER_OF_OUTPUT_WORDS - 1;
begin
FSL_S_Read <= FSL_S_Exists when state = Read_Inputs else '0';
FSL_M_Write <= not FSL_M_Full when state = Write_Outputs else '0';
FSL_M_Data <= sum;
The_SW_accelerator : process (FSL_Clk) is
begin -- process The_SW_accelerator
if FSL_Clk'event and FSL_Clk = '1' then -- Rising clock edge
if FSL_Rst = '1' then -- Synchronous reset (active high)
state <= Idle;
nr_of_reads <= 0;
nr_of_writes <= 0;
sum <= (others => '0');
else
case state is
when Idle =>
if (FSL_S_Exists = '1') then
state <= Read_Inputs;
nr_of_reads <= NUMBER_OF_INPUT_WORDS - 1;
sum <= (others => '0');
end if;
when Read_Inputs =>
if (FSL_S_Exists = '1') then
-- Coprocessor function (Adding) happens here
sum <= std_logic_vector(unsigned(sum) + unsigned(FSL_S_Data));
if (nr_of_reads = 0) then
state <= Write_Outputs;
nr_of_writes <= NUMBER_OF_OUTPUT_WORDS - 1;
else
nr_of_reads <= nr_of_reads - 1;
end if;
end if;
when Write_Outputs =>
if (nr_of_writes = 0) then
state <= Idle;
else
if (FSL_M_Full = '0') then
nr_of_writes <= nr_of_writes - 1;
end if;
end if;
end case;
end if;
end if;
end process The_SW_accelerator;
end architecture EXAMPLE;
|
mit
|
UdayanSinha/Code_Blocks
|
VHDL/Projects/work/nor_gate.vhd
|
1
|
376
|
LIBRARY IEEE; -- These lines informs the compiler that the library IEEE is used
USE IEEE.std_logic_1164.all; -- contains the definition for the std_logic type plus some useful conversion functions
ENTITY nor_gate IS
PORT (a:IN STD_LOGIC;
b:IN STD_LOGIC;
q:OUT STD_LOGIC);
END nor_gate;
ARCHITECTURE behave OF nor_gate IS
BEGIN
q<=a NOR b;
END behave;
|
mit
|
Nooxet/embedded_bruteforce
|
vhdl/tb_comp.vhd
|
1
|
3514
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer: Gabbe
--
-- Create Date: 12:04:52 09/17/2014
-- Design Name:
-- Module Name: H:/embedded_labs/comp/tb_comp.vhd
-- Project Name: comp
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: comp
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY tb_comp IS
END tb_comp;
ARCHITECTURE behavior OF tb_comp IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT comp
PORT(
clk : IN std_logic;
rstn : IN std_logic;
i_hash_0 : IN unsigned(31 downto 0);
i_hash_1 : IN unsigned(31 downto 0);
i_hash_2 : IN unsigned(31 downto 0);
i_hash_3 : IN unsigned(31 downto 0);
i_cmp_hash : IN std_logic_vector(127 downto 0);
i_start : IN std_logic;
o_equal : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rstn : std_logic := '1';
signal i_hash_0 : unsigned(31 downto 0) := (others => '0');
signal i_hash_1 : unsigned(31 downto 0) := (others => '0');
signal i_hash_2 : unsigned(31 downto 0) := (others => '0');
signal i_hash_3 : unsigned(31 downto 0) := (others => '0');
signal i_cmp_hash : std_logic_vector(127 downto 0) := (others => '0');
signal i_start : std_logic := '0';
--Outputs
signal o_equal : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: comp PORT MAP (
clk => clk,
rstn => rstn,
i_hash_0 => i_hash_0,
i_hash_1 => i_hash_1,
i_hash_2 => i_hash_2,
i_hash_3 => i_hash_3,
i_cmp_hash => i_cmp_hash,
i_start => i_start,
o_equal => o_res
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2;
rstn <= '0';
wait for clk_period;
rstn <= '1';
i_cmp_hash <= x"13121110232221203332313043424140";
i_start <= '1';
wait for clk_period;
i_start <= '0';
i_hash_0 <= x"10111213";
i_hash_1 <= x"20212223";
i_hash_2 <= x"30313233";
i_hash_3 <= x"40414243";
assert o_equal = '1' report "correct hash compared wrong";
wait for clk_period*4;
i_hash_0 <= x"11111111";
i_hash_1 <= x"11111111";
i_hash_2 <= x"11111111";
i_hash_3 <= x"11111111";
wait for clk_period;
assert o_equal = '0' report "false hash compared wrong";
wait;
end process;
END;
|
mit
|
tsotnep/vhdl_soc_audio_mixer
|
ZedBoard_Linux_Design/hw/xps_proj/pcores/adau1761_audio_v1_00_a/hdl/vhdl/i2c.vhd
|
3
|
2734
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Description: A controller to send I2C commands to the ADAU1761 codec
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity i2c is
Port ( clk : in STD_LOGIC;
i2c_sda_i : IN std_logic;
i2c_sda_o : OUT std_logic;
i2c_sda_t : OUT std_logic;
i2c_scl : out STD_LOGIC;
sw : in std_logic_vector(1 downto 0);
active : out std_logic_vector(1 downto 0));
end i2c;
architecture Behavioral of i2c is
COMPONENT i3c2
Generic( clk_divide : STD_LOGIC_VECTOR (7 downto 0));
PORT(
clk : IN std_logic;
i2c_sda_i : IN std_logic;
i2c_sda_o : OUT std_logic;
i2c_sda_t : OUT std_logic;
i2c_scl : OUT std_logic;
inst_data : IN std_logic_vector(8 downto 0);
inputs : IN std_logic_vector(15 downto 0);
inst_address : OUT std_logic_vector(9 downto 0);
debug_sda : OUT std_logic;
debug_scl : OUT std_logic;
outputs : OUT std_logic_vector(15 downto 0);
reg_addr : OUT std_logic_vector(4 downto 0);
reg_data : OUT std_logic_vector(7 downto 0);
reg_write : OUT std_logic;
error : OUT std_logic
);
END COMPONENT;
COMPONENT adau1761_configuraiton_data
PORT(
clk : IN std_logic;
address : IN std_logic_vector(9 downto 0);
data : OUT std_logic_vector(8 downto 0)
);
END COMPONENT;
signal inst_address : std_logic_vector(9 downto 0);
signal inst_data : std_logic_vector(8 downto 0);
signal sw_full :std_logic_vector(15 downto 0) := (others => '0');
signal active_full : std_logic_vector(15 downto 0) := (others => '0');
begin
sw_full(1 downto 0) <= sw;
active <= active_full(1 downto 0);
Inst_adau1761_configuraiton_data: adau1761_configuraiton_data PORT MAP(
clk => clk,
address => inst_address,
data => inst_data
);
Inst_i3c2: i3c2 GENERIC MAP (
clk_divide => "01111000" -- 120 (48,000/120 = 400kHz I2C clock)
) PORT MAP(
clk => clk,
inst_address => inst_address,
inst_data => inst_data,
i2c_scl => i2c_scl,
i2c_sda_i => i2c_sda_i,
i2c_sda_o => i2c_sda_o,
i2c_sda_t => i2c_sda_t,
inputs => sw_full,
outputs => active_full,
reg_addr => open,
reg_data => open,
reg_write => open,
debug_scl => open,
debug_sda => open,
error => open
);
end Behavioral;
|
mit
|
tsotnep/vhdl_soc_audio_mixer
|
ZedBoard_Linux_Design/hw/xps_proj/pcores/superip_v1_00_a/hdl/vhdl/Balance.vhd
|
2
|
5209
|
----------------------------------------------------------------------------------
-- Company: TTU_SoCDesign
-- Engineer: Mohamed Behery
--
-- Create Date: 16:51:21 04/29/2015
-- Design Name: Panning unit
-- Module Name: Balance - Behavioral
-- Project Name: Audio mixer
-- Target Devices: ZedBoard (Zynq7000)
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity Balance is
generic(INTBIT_WIDTH : positive ;
FRACBIT_WIDTH : positive ;
N : positive ;
Attenuation_Const : positive ); -- This constant is for attenuating the input signals so that the signal is not chopped if amplified
Port(CLK_BAL : in std_logic;
RESET_BAL : in std_logic;
POINTER : in integer;
CH_L_IN, CH_R_IN : in signed(INTBIT_WIDTH - 1 downto 0);
CH_L_OUT : out signed(INTBIT_WIDTH - 1 downto 0) := x"000000";
CH_R_OUT : out signed(INTBIT_WIDTH - 1 downto 0) := x"000000";
READY_BAL : out std_logic := '0'
);
end Balance;
Architecture Behavioral of Balance is
type Coeff_Array is array (0 to N / 2) of signed((INTBIT_WIDTH + FRACBIT_WIDTH) - 1 downto 0);
-- Coeffecients calculated via the Matlab m-file (check the Matlab code in the last code section)
-- constant Amp_Coeff : Coeff_Array := (500,667,767,867,909,923,937,951,962,967,972,977,982,986,991,995,1000); --The second half of the balance graph has it's amplification values placed in Amp_Coeff array
-- constant Att_Coeff : Coeff_Array := (500,333,233,133,91,77,63,49,38,33,28,23,18,14,9,5,0); --The second half of the balance graph has it's attenuation values placed in Att_Coeff array
constant Amp_Coeff : Coeff_Array := (x"0001F400", x"00029B00", x"0002FF00", x"00036300", x"00038D00", x"00039B00", x"0003A900", x"0003B700", x"0003C200", x"0003C700", x"0003CC00", x"0003D100", x"0003D600", x"0003DA00", x"0003DF00", x"0003E300", x"0003E800");
constant Att_Coeff : Coeff_Array := (x"0001F400", x"00014D00", x"0000E900", x"00008500", x"00005B00", x"00004D00", x"00003F00", x"00003100", x"00002600", x"00002100", x"00001C00", x"00001700", x"00001200", x"00000E00", x"00000900", x"00000500", x"00000000");
signal Coeff_Left : signed((INTBIT_WIDTH + FRACBIT_WIDTH) - 1 downto 0);
signal Coeff_Right : signed((INTBIT_WIDTH + FRACBIT_WIDTH) - 1 downto 0);
signal ready_signal_right : STD_LOGIC;
signal ready_signal_left : STD_LOGIC;
signal CH_R_IN_signal : signed(INTBIT_WIDTH - 1 downto 0);
signal CH_L_IN_signal : signed(INTBIT_WIDTH - 1 downto 0);
signal CH_L_OUT_signal : signed(INTBIT_WIDTH - 1 downto 0);
signal CH_R_OUT_signal : signed(INTBIT_WIDTH - 1 downto 0);
component AmplifierFP
Port(
CLK : in std_logic;
RESET : in std_logic;
IN_SIG : in signed((INTBIT_WIDTH - 1) downto 0); --amplifier input signal
IN_COEF : in signed((INTBIT_WIDTH + FRACBIT_WIDTH - 1) downto 0) := (others => '0'); --amplifying coefficient
OUT_AMP : out signed((INTBIT_WIDTH - 1) downto 0) := (others => '0'); --amplifier output
OUT_RDY : out std_logic
);
end component;
begin
Mult_Left : AmplifierFP port map(
CLK => CLK_BAL,
RESET => RESET_BAL,
IN_SIG => CH_L_IN_signal,
IN_COEF => Coeff_Left,
OUT_AMP => CH_L_OUT_signal,
OUT_RDY => ready_signal_left
);
Mult_Right : AmplifierFP port map(
CLK => CLK_BAL,
RESET => RESET_BAL,
IN_SIG => CH_R_IN_signal,
IN_COEF => Coeff_right,
OUT_AMP => CH_R_OUT_signal,
OUT_RDY => ready_signal_right
);
READY_BAL <= (ready_signal_right and ready_signal_left);
CH_L_IN_signal <= shift_right(CH_L_IN, Attenuation_Const); -- Attenuating the incoming data from the outside by 6dB
CH_R_IN_signal <= shift_right(CH_R_IN, Attenuation_Const); -- Attenuating the incoming data from the outside by 6dB
Combinational : process(POINTER) -- Here according to the value of the POINTER the coefficient graph "half" is either kept as it is or it's inverted
begin
if (POINTER > N / 2) then -- Case 1: Amplify Right and Attenuate Left
Coeff_Right <= Amp_Coeff(POINTER - N / 2); -- If the POINTER is above 50% the graph is kept as it is
Coeff_Left <= Att_Coeff(POINTER - N / 2);
elsif (POINTER < N / 2) then -- Case 2: Amplify Left and Attenuate Right
Coeff_Right <= Att_Coeff(N / 2 - POINTER); -- If the POINTER is below 50% the graph is inverted
Coeff_Left <= Amp_Coeff(N / 2 - POINTER);
else
Coeff_Right <= Att_Coeff(0); -- else: the POINTER = 50%, give the coefficients the 0th value in the array
Coeff_Left <= Amp_Coeff(0);
end if;
end process Combinational;
Sequential : process(CLK_BAL)
begin
if (CLK_BAL'event and CLK_BAL = '1') then
CH_L_OUT <= CH_L_OUT_signal;
CH_R_OUT <= CH_R_OUT_signal;
end if;
end process Sequential;
end Behavioral;
|
mit
|
Nooxet/embedded_bruteforce
|
brutus_system/pcores/bajsd_v1_00_a/hdl/vhdl/md5_demux.vhd
|
3
|
1412
|
----------------------------------------------------------------------------------
-- Engineer: Noxet
--
-- Module Name: md5_demux - Behavioral
-- Description:
-- A demux to select which md5 to use for hashing
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- include the hash_array type --
use work.hash_array_pkg.all;
entity md5_demux is
generic (
N : integer
);
port (
i_md5_indata : in md5_indata_t;
i_select : in unsigned(N-1 downto 0); -- should be ceil(log2(N-1))
o_md5_indata_0 : out md5_indata_t; --_array(N-1 downto 0)
o_md5_indata_1 : out md5_indata_t --_array(N-1 downto 0)
);
end md5_demux;
architecture Behavioral of md5_demux is
begin
comb_proc : process(i_select, i_md5_indata)
begin
o_md5_indata_0.data_0 <= (others => '0');
o_md5_indata_0.data_1 <= (others => '0');
o_md5_indata_0.start <= '0';
o_md5_indata_0.len <= (others => '0');
o_md5_indata_1.data_0 <= (others => '0');
o_md5_indata_1.data_1 <= (others => '0');
o_md5_indata_1.start <= '0';
o_md5_indata_1.len <= (others => '0');
--o_md5_indata(to_integer(unsigned(i_select))) <= i_md5_indata;
if i_select = 0 then
o_md5_indata_0 <= i_md5_indata;
elsif i_select = 1 then
o_md5_indata_1 <= i_md5_indata;
end if;
end process;
end Behavioral;
|
mit
|
RickvanLoo/Synthesizer
|
sample_clk_gen_entity.vhd
|
1
|
730
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
entity sample_clk_gen_entity is
GENERIC(divider : integer := 512
);
PORT (clk : IN std_logic;
reset : IN std_logic;
a_clk, a_clk_main : OUT std_logic
);
END sample_clk_gen_entity;
architecture behav of sample_clk_gen_entity is
signal local_clk : std_logic := '0';
begin
process(clk, reset)
variable count : integer := 0;
begin
if reset = '0' then
count := 0;
local_clk <= '0';
elsif falling_edge(clk) then
if count = divider then
local_clk <= not local_clk;
count := 0;
end if;
count := count + 1;
end if;
a_clk <= local_clk;
a_clk_main <= local_clk;
end process;
end behav;
|
mit
|
tsotnep/vhdl_soc_audio_mixer
|
ZedBoard_Linux_Design/hw/xps_proj/pcores/audio_buffer_v1_00_a/hdl/vhdl/user_logic.vhd
|
3
|
10518
|
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Mon Apr 13 19:59:47 2015 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_REG -- Number of software accessible registers
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 2;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
clk_48_i : in std_logic;
sample_data_L_in : in std_logic_vector(23 downto 0);
sample_data_R_in : in std_logic_vector(23 downto 0);
sample_data_L_out : out std_logic_vector(23 downto 0);
sample_data_R_out : out std_logic_vector(23 downto 0);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg1 : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_reg_write_sel : std_logic_vector(1 downto 0);
signal slv_reg_read_sel : std_logic_vector(1 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH-1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(1 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(1 downto 0);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
else
case slv_reg_write_sel is
when "10" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "01" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg1(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1 ) is
begin
case slv_reg_read_sel is
when "10" => slv_ip2bus_data <= slv_reg0;
when "01" => slv_ip2bus_data <= slv_reg1;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
|
mit
|
Nooxet/embedded_bruteforce
|
brutus_system/pcores/ready4hood_v1_00_a/hdl/vhdl/controller.vhd
|
2
|
5222
|
----------------------------------------------------------------------------------
-- Engineer: Noxet && Niklas
--
-- Create Date: 14:56:58 09/22/2014
-- Module Name: controller - Behavioral
-- Description:
-- The Brutus system controller
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity controller is
generic (
N : integer := 1
);
port (
clk : in std_logic;
rstn : in std_logic;
i_fsl_data_recv : in std_logic;
i_fsl_hash : in std_logic_vector(127 downto 0);
i_comp_eq : in std_logic; -- check if password was found
i_sg_done : in std_logic; -- string generator done signal
i_sg_string : in std_logic_vector(47 downto 0); -- current potential password
i_md5_done : in std_logic; -- done signal from the main MD5 core
o_passwd_hash : out std_logic_vector(127 downto 0); -- hash from FSL
o_pw_found : out std_logic; -- flag to indicate password found
-- o_pw_nfound : out ---
o_passwd : out std_logic_vector(47 downto 0); -- password string, send to user
o_start_sg_comp : out std_logic; -- start signals to sg and comp
o_start_md5 : out std_logic; -- start signal to MD5 cores
o_halt_sg : out std_logic; -- halt signal to sg
o_demux_sel : out std_logic_vector(N-1 downto 0); --
o_mux_sel : out std_logic_vector(N-1 downto 0) -- select signals to DEMUX/MUX
);
end controller;
architecture Behavioral of controller is
type states is (wait_fsl, calc_md5, wait_md5, comp_md5, send_fsl);
signal state_c, state_n : states;
signal dm_count_c, dm_count_n : unsigned(N-1 downto 0); -- DEMUX selector counter
signal m_count_c, m_count_n : unsigned(N-1 downto 0); -- MUX selector counter
type pw_buff_array is array(N-1 downto 0) of std_logic_vector(47 downto 0);
signal pw_buff_c, pw_buff_n : pw_buff_array;
begin
clk_proc: process(clk)
begin
if rising_edge(clk) then
if rstn = '0' then
state_c <= wait_fsl;
dm_count_c <= (others => '0');
m_count_c <= (others => '0');
pw_buff_c <= (others => (others => '0'));
else
state_c <= state_n;
dm_count_c <= dm_count_n;
m_count_c <= m_count_n;
pw_buff_c <= pw_buff_n;
end if;
end if;
end process;
fsm_proc: process(state_c, i_fsl_data_recv, i_comp_eq, i_sg_done, i_md5_done, i_sg_string, pw_buff_c, m_count_c, dm_count_c)
begin
-- defaults --
o_start_sg_comp <= '0';
o_start_md5 <= '0';
o_halt_sg <= '0';
dm_count_n <= dm_count_c;
m_count_n <= m_count_c;
o_passwd <= (others => '0');
o_pw_found <= '0';
pw_buff_n <= pw_buff_c;
state_n <= state_c;
case state_c is
-- KOLLA IFALL SG ÄR FÄRDIG, ISÅFALL HOPPA TILL /DEV/NULL --
when wait_fsl =>
dm_count_n <= (others => '0');
m_count_n <= (others => '0');
if i_fsl_data_recv = '1' then
state_n <= calc_md5;
o_start_sg_comp <= '1';
end if;
when calc_md5 =>
o_start_md5 <= '1'; -- start MD5 cores
dm_count_n <= dm_count_c + 1;
pw_buff_n(to_integer(dm_count_c)) <= i_sg_string; -- buffer the sg passwords
if dm_count_c = N-1 then -- should be N-1? CHECK THIS, we now
-- halt everything...
dm_count_n <= (others => '0');
o_halt_sg <= '1'; -- halt the sg while crunching MD5 hashes
state_n <= wait_md5;
end if;
-- wait for the main MD5 core to be finished
when wait_md5 =>
o_halt_sg <= '1'; -- halt until done
if i_md5_done = '1' then
state_n <= comp_md5;
end if;
when comp_md5 => -- rename to a better name
-- o_halt_sg <= '1'; -- TEST
m_count_n <= m_count_c + 1;
if i_comp_eq = '1' then
o_passwd <= pw_buff_c(to_integer(m_count_c));
o_pw_found <= '1';
state_n <= wait_fsl; -- back to init state
elsif m_count_c = N-1 then
m_count_n <= (others => '0');
state_n <= calc_md5; -- if pwd not found, calculate next hash
end if;
when others => null;
end case;
end process;
-- pass through signal --
o_passwd_hash <= i_fsl_hash;
o_demux_sel <= std_logic_vector(dm_count_c);
o_mux_sel <= std_logic_vector(m_count_c);
end Behavioral;
|
mit
|
Madh93/scpu
|
work/mux2/_primary.vhd
|
1
|
445
|
library verilog;
use verilog.vl_types.all;
entity mux2 is
generic(
WIDTH : integer := 8
);
port(
d0 : in vl_logic_vector;
d1 : in vl_logic_vector;
s : in vl_logic;
y : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of WIDTH : constant is 1;
end mux2;
|
mit
|
UdayanSinha/Code_Blocks
|
VHDL/Projects/work/d_latch.vhd
|
1
|
426
|
LIBRARY IEEE; -- These lines informs the compiler that the library IEEE is used
USE IEEE.std_logic_1164.all; -- contains the definition for the std_logic type plus some useful conversion functions
ENTITY d_latch IS
PORT(d, clk: IN STD_LOGIC;
q: OUT STD_LOGIC);
END d_latch;
ARCHITECTURE behave OF d_latch IS
BEGIN
PROCESS(clk, d)
BEGIN
IF (clk='1') THEN
q<=d;
END IF;
END PROCESS;
END behave;
|
mit
|
Nooxet/embedded_bruteforce
|
brutus_system/hdl/system_microblaze_0_ilmb_wrapper.vhd
|
1
|
3913
|
-------------------------------------------------------------------------------
-- system_microblaze_0_ilmb_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_v10_v2_00_b;
use lmb_v10_v2_00_b.all;
entity system_microblaze_0_ilmb_wrapper is
port (
LMB_Clk : in std_logic;
SYS_Rst : in std_logic;
LMB_Rst : out std_logic;
M_ABus : in std_logic_vector(0 to 31);
M_ReadStrobe : in std_logic;
M_WriteStrobe : in std_logic;
M_AddrStrobe : in std_logic;
M_DBus : in std_logic_vector(0 to 31);
M_BE : in std_logic_vector(0 to 3);
Sl_DBus : in std_logic_vector(0 to 31);
Sl_Ready : in std_logic_vector(0 to 0);
Sl_Wait : in std_logic_vector(0 to 0);
Sl_UE : in std_logic_vector(0 to 0);
Sl_CE : in std_logic_vector(0 to 0);
LMB_ABus : out std_logic_vector(0 to 31);
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_AddrStrobe : out std_logic;
LMB_ReadDBus : out std_logic_vector(0 to 31);
LMB_WriteDBus : out std_logic_vector(0 to 31);
LMB_Ready : out std_logic;
LMB_Wait : out std_logic;
LMB_UE : out std_logic;
LMB_CE : out std_logic;
LMB_BE : out std_logic_vector(0 to 3)
);
attribute x_core_info : STRING;
attribute x_core_info of system_microblaze_0_ilmb_wrapper : entity is "lmb_v10_v2_00_b";
end system_microblaze_0_ilmb_wrapper;
architecture STRUCTURE of system_microblaze_0_ilmb_wrapper is
component lmb_v10 is
generic (
C_LMB_NUM_SLAVES : integer;
C_LMB_AWIDTH : integer;
C_LMB_DWIDTH : integer;
C_EXT_RESET_HIGH : integer
);
port (
LMB_Clk : in std_logic;
SYS_Rst : in std_logic;
LMB_Rst : out std_logic;
M_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
M_ReadStrobe : in std_logic;
M_WriteStrobe : in std_logic;
M_AddrStrobe : in std_logic;
M_DBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
M_BE : in std_logic_vector(0 to (C_LMB_DWIDTH+7)/8-1);
Sl_DBus : in std_logic_vector(0 to (C_LMB_DWIDTH*C_LMB_NUM_SLAVES)-1);
Sl_Ready : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_Wait : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_UE : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
Sl_CE : in std_logic_vector(0 to C_LMB_NUM_SLAVES-1);
LMB_ABus : out std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_AddrStrobe : out std_logic;
LMB_ReadDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_WriteDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_Ready : out std_logic;
LMB_Wait : out std_logic;
LMB_UE : out std_logic;
LMB_CE : out std_logic;
LMB_BE : out std_logic_vector(0 to (C_LMB_DWIDTH+7)/8-1)
);
end component;
begin
microblaze_0_ilmb : lmb_v10
generic map (
C_LMB_NUM_SLAVES => 1,
C_LMB_AWIDTH => 32,
C_LMB_DWIDTH => 32,
C_EXT_RESET_HIGH => 1
)
port map (
LMB_Clk => LMB_Clk,
SYS_Rst => SYS_Rst,
LMB_Rst => LMB_Rst,
M_ABus => M_ABus,
M_ReadStrobe => M_ReadStrobe,
M_WriteStrobe => M_WriteStrobe,
M_AddrStrobe => M_AddrStrobe,
M_DBus => M_DBus,
M_BE => M_BE,
Sl_DBus => Sl_DBus,
Sl_Ready => Sl_Ready,
Sl_Wait => Sl_Wait,
Sl_UE => Sl_UE,
Sl_CE => Sl_CE,
LMB_ABus => LMB_ABus,
LMB_ReadStrobe => LMB_ReadStrobe,
LMB_WriteStrobe => LMB_WriteStrobe,
LMB_AddrStrobe => LMB_AddrStrobe,
LMB_ReadDBus => LMB_ReadDBus,
LMB_WriteDBus => LMB_WriteDBus,
LMB_Ready => LMB_Ready,
LMB_Wait => LMB_Wait,
LMB_UE => LMB_UE,
LMB_CE => LMB_CE,
LMB_BE => LMB_BE
);
end architecture STRUCTURE;
|
mit
|
jhladky/ratload
|
RAT_CPU/vgaDriverBuffer.vhd
|
1
|
2844
|
--
-- The interface to the VGA driver module. Extended to both read and write
-- to the framebuffer (to check the color values of a particular pixel).
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vgaDriverBuffer is
Port( CLK, we : in std_logic;
wa : in std_logic_vector(10 downto 0);
wd : in std_logic_vector(7 downto 0);
rout, gout : out std_logic_vector(2 downto 0);
Bout : out std_logic_vector(1 downto 0);
HS, vs : out std_logic;
pixelData : out std_logic_vector(7 downto 0));
end vgaDriverBuffer;
architecture Behavioral of vgaDriverBuffer is
-- vga driver signals
signal ra : std_logic_vector(10 downto 0);
signal vgaData : std_logic_vector(7 downto 0);
signal fb_wr, vgaclk : std_logic;
signal red, green : std_logic_vector(2 downto 0);
signal blue : std_logic_vector(1 downto 0);
signal row, column : std_logic_vector(9 downto 0);
-- Added to read the pixel data at address 'wa' -- pfh, 3/1/2012
signal pixelVal : std_logic_vector(7 downto 0);
-- Declare VGA driver components
component VGAdrive is
Port( clock : in std_logic; -- 25.175 Mhz clock
red, green : in std_logic_vector(2 downto 0);
blue : in std_logic_vector(1 downto 0);
row, column : out std_logic_vector(9 downto 0); -- for current pixel
Rout, Gout : out std_logic_vector(2 downto 0);
Bout : out std_logic_vector(1 downto 0);
H, V : out std_logic); -- VGA drive signals
end component;
component ram2k_8 is
Port( clk, we : in STD_LOGIC;
ra, wa : in STD_LOGIC_VECTOR(10 downto 0);
wd : in STD_LOGIC_VECTOR(7 downto 0);
rd, pixelval: out STD_LOGIC_VECTOR(7 downto 0));
end component;
component vga_clk_div is
Port( clk : in std_logic;
clkout : out std_logic);
end component;
begin
frameBuffer : ram2k_8 port map(
clk => clk, --CLK
we => we,
ra => ra,
wa => wa,
wd => wd,
rd => vgaData,
pixelVal => pixelVal);
vga_out : VGAdrive port map(
clock => vgaclk,
red => red,
green => green,
blue => blue,
row => row,
column => column,
Rout => Rout,
Gout => Gout,
Bout => Bout,
H => HS,
V => VS);
vga_clk : vga_clk_div port map(
clk => CLK,
clkout => vgaclk);
-- read signals from fb
ra <= row (8 downto 4) & column(9 downto 4);
red <= vgaData(7 downto 5);
green <= vgaData(4 downto 2);
blue <= vgaData(1 downto 0);
pixelData <= pixelVal; -- returns the pixel data in the framebuffer at address 'wa'
end Behavioral;
|
mit
|
jhladky/ratload
|
RAT_CPU/ascii_to_int.vhd
|
1
|
810
|
----------------------------------------------------------------------------------
-- Company: CPE233
-- Engineer: Jacob Hladky
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ascii_to_int is
Port( ascii_in : in STD_LOGIC_VECTOR (7 downto 0);
int_out : out STD_LOGIC_VECTOR (7 downto 0));
end ascii_to_int;
architecture ascii_to_int_a of ascii_to_int is begin
process(ascii_in) begin
if(ascii_in >= x"30" and ascii_in <= x"39") then
int_out <= ascii_in - x"30";
elsif(ascii_in >= x"41" and ascii_in <= x"46") then
int_out <= ascii_in - x"41" + 10;
else
int_out <= ascii_in;
end if;
end process;
end ascii_to_int_a;
|
mit
|
jhladky/ratload
|
RAT_CPU/register_file.vhd
|
1
|
1468
|
----------------------------------------------------------------------------------
-- Company: CPE 233
-- Engineer: Jacob Hladky and Curtis Jonaitis
---------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity register_file is
Port( FROM_IN_PORT : in STD_LOGIC_VECTOR(7 downto 0);
FROM_TRI_STATE : in STD_LOGIC_VECTOR(7 downto 0);
FROM_ALU : in STD_LOGIC_VECTOR(7 downto 0);
RF_MUX_SEL : in STD_LOGIC_VECTOR(1 downto 0);
ADRX, ADRY : in STD_LOGIC_VECTOR(4 downto 0);
WE, CLK, DX_OE : in STD_LOGIC;
DX_OUT, DY_OUT : out STD_LOGIC_VECTOR(7 downto 0));
end register_file;
architecture register_file_a of register_file is
TYPE memory is array (0 to 31) of std_logic_vector(7 downto 0);
SIGNAL REG: memory := (others=>(others=>'0'));
SIGNAL D_IN : STD_LOGIC_VECTOR(7 downto 0);
begin
with RF_MUX_SEL select
D_IN <= FROM_IN_PORT when "00",
FROM_TRI_STATE when "01",
FROM_ALU when "10",
(others => 'X') when others;
process(clk, we, d_in) begin
if (rising_edge(clk)) then
if (WE = '1') then
REG(conv_integer(ADRX)) <= D_IN;
end if;
end if;
end process;
DX_OUT <= REG(conv_integer(ADRX)) when DX_OE='1' else (others=>'Z');
DY_OUT <= REG(conv_integer(ADRY));
end register_file_a;
|
mit
|
Hyvok/HardHeat
|
sim/resonant_pfd/resonant_pfd_tb.vhd
|
1
|
1207
|
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity resonant_pfd_tb is
end entity;
architecture rtl of resonant_pfd_tb is
-- Clock frequency 100 MHz
constant CLK_PERIOD : time := 1 sec / 10e7;
-- Reference signal frequency 40 kHz
constant REF_PERIOD : time := 1 sec / 40e3;
-- Output signal frequency 50 kHz
constant SIG_PERIOD : time := 1 sec / 50e3;
signal clk : std_logic := '0';
signal reset : std_logic;
signal ref : std_logic := '0';
signal sig : std_logic := '0';
begin
DUT_inst: entity work.resonant_pfd(rtl)
port map
(
clk => clk,
reset => reset,
ref_in => ref,
sig_in => sig
);
reset <= '1' , '0' after 500 ns;
clk_gen: process(clk)
begin
clk <= not clk after CLK_PERIOD / 2;
end process;
ref_gen: process(ref)
begin
ref <= not ref after REF_PERIOD / 2;
end process;
sig_gen: process(sig)
begin
sig <= not sig after SIG_PERIOD / 2;
end process;
end;
|
mit
|
Hyvok/HardHeat
|
src/hardheat_top.vhd
|
1
|
7904
|
library ieee;
library work;
library altera;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.altera_pll_top_pkg.all;
use altera.altera_syn_attributes.all;
entity hardheat_top is
generic
(
-- Number of bits in time-to-digital converter
TDC_N : positive := 12;
-- Number of bitshifts to left for the filter proportional coefficient
FILT_P_SHIFT_N : integer := 0;
-- Number of bitshifts to right for the filter integral coefficient
FILT_I_SHIFT_N : integer := -5;
-- Initial output value from the filter
FILT_INIT_OUT_VAL : positive := 2**11 - 1;
-- Filter output offset
FILT_OUT_OFFSET : natural := 2**21;
-- Filter output value clamping limit
FILT_OUT_LIM : positive := 2**22;
-- Number of bits in the phase accumulator
ACCUM_BITS_N : positive := 32;
-- Number of bits in the tuning word for the phase accumulator
ACCUM_WORD_N : positive := 23;
-- Number of bits in the deadtime counter
DT_N : positive := 16;
-- Amount of deadtime in clock cycles
DT_VAL : natural := 100;
-- Number of bits in the lock detector "locked" counter
LD_LOCK_N : positive := 20;
-- Number of bits in the lock detector "unlocked" counter
LD_ULOCK_N : positive := 16;
-- Phase difference value under which we are considered to be locked
LD_LOCK_LIMIT : natural := 100;
-- Temperature conversion interval in clock cycles
TEMP_CONV_D : natural := 100000000;
-- Delay between conversion command and reading in clock cycles
TEMP_CONV_CMD_D : natural := 75000000;
-- Number of clock cycles for 1us delay for the 1-wire module
TEMP_OW_US_D : positive := 100;
-- Number of bits in the temperature PWM controller
TEMP_PWM_N : positive := 12;
-- Minimum PWM level (duty cycle)
TEMP_PWM_MIN_LVL : natural := 2**12 / 5;
-- Output maximum duty cycle on enable, measured in PWM cycles!
TEMP_PWM_EN_ON_D : natural := 100000;
-- Number of bitshifts to left for the PID-filter proportional coeff
TEMP_P_SHIFT_N : integer := 4;
-- Number of bitshifts to right for the PID-filter integral coeff
TEMP_I_SHIFT_N : integer := -11;
-- PID input offset applied to the temperature sensor output
TEMP_SETPOINT : integer := 320;
DEBOUNCE_D : natural := 1000000;
DEBOUNCE_FF_N : natural := 5
);
port
(
clk_in : in std_logic;
reset_in : in std_logic;
ref_in : in std_logic;
sig_in : in std_logic;
ow_in : in std_logic;
mod_lvl_in : in std_logic_vector(2 downto 0);
ow_out : out std_logic;
ow_pullup_out : out std_logic;
sig_lh_out : out std_logic;
sig_ll_out : out std_logic;
sig_rh_out : out std_logic;
sig_rl_out : out std_logic;
lock_out : out std_logic;
pwm_out : out std_logic;
temp_err_out : out std_logic
);
end entity;
architecture rtl_top of hardheat_top is
attribute noprune : boolean;
attribute preserve : boolean;
attribute keep : boolean;
signal clk : std_logic;
attribute noprune of clk : signal is true;
attribute keep of clk : signal is true;
signal temp : signed(16 - 1 downto 0);
signal temp_f : std_logic;
attribute keep of temp : signal is true;
attribute keep of temp_f : signal is true;
attribute noprune of temp : signal is true;
attribute noprune of temp_f : signal is true;
attribute preserve of temp : signal is true;
signal pll_clk : std_logic;
signal pll_locked : std_logic;
signal reset : std_logic;
signal mod_lvl : std_logic_vector(mod_lvl_in'range);
signal mod_lvl_f : std_logic;
signal debounced_sws : std_logic_vector(mod_lvl_in'range);
begin
-- Main clock from PLL on the SoCkit board
pll_p: altera_pll_top
port map
(
refclk => clk_in,
rst => not reset_in,
outclk_0 => pll_clk,
locked => pll_locked
);
clk <= pll_clk;
reset <= not pll_locked;
-- Read modulation level state from switches, debounce
debouncing_p: for i in 0 to mod_lvl_in'high generate
debouncer_p: entity work.debounce(rtl)
generic map
(
DEBOUNCE_D => DEBOUNCE_D,
FLIPFLOPS_N => DEBOUNCE_FF_N
)
port map
(
clk => clk,
reset => reset,
sig_in => mod_lvl_in(i),
sig_out => debounced_sws(i)
);
end generate;
-- Change modulation level when debounced modulation level changes
mod_lvl_p: process(clk, reset)
variable state : std_logic_vector(mod_lvl_in'high downto 0);
begin
if reset = '1' then
state := (others => '1');
mod_lvl <= state;
mod_lvl_f <= '0';
elsif rising_edge(clk) then
mod_lvl_f <= '0';
if not debounced_sws = state then
state := debounced_sws;
mod_lvl <= state;
mod_lvl_f <= '1';
end if;
end if;
end process;
-- TODO: Sig is internally connected!
hardheat_p: entity work.hardheat(rtl)
generic map
(
TDC_N => TDC_N,
FILT_P_SHIFT_N => FILT_P_SHIFT_N,
FILT_I_SHIFT_N => FILT_I_SHIFT_N,
FILT_INIT_OUT_VAL => FILT_INIT_OUT_VAL,
FILT_OUT_OFFSET => FILT_OUT_OFFSET,
FILT_OUT_LIM => FILT_OUT_LIM,
ACCUM_BITS_N => ACCUM_BITS_N,
ACCUM_WORD_N => ACCUM_WORD_N,
LD_LOCK_N => LD_LOCK_N,
LD_ULOCK_N => LD_ULOCK_N,
LD_LOCK_LIMIT => LD_LOCK_LIMIT,
DT_N => DT_N,
DT_VAL => DT_VAL,
TEMP_CONV_D => TEMP_CONV_D,
TEMP_CONV_CMD_D => TEMP_CONV_CMD_D,
TEMP_OW_US_D => TEMP_OW_US_D,
TEMP_PWM_N => TEMP_PWM_N,
TEMP_PWM_MIN_LVL => TEMP_PWM_MIN_LVL,
TEMP_PWM_EN_ON_D => TEMP_PWM_EN_ON_D,
TEMP_P_SHIFT_N => TEMP_P_SHIFT_N,
TEMP_I_SHIFT_N => TEMP_I_SHIFT_N,
TEMP_SETPOINT => TEMP_SETPOINT
)
port map
(
clk => clk,
reset => reset,
ref_in => ref_in,
sig_in => sig_in,
mod_lvl_in => unsigned(mod_lvl),
mod_lvl_in_f => mod_lvl_f,
sig_lh_out => sig_lh_out,
sig_ll_out => sig_ll_out,
sig_rh_out => sig_rh_out,
sig_rl_out => sig_rl_out,
lock_out => lock_out,
ow_in => ow_in,
ow_out => ow_out,
ow_pullup_out => ow_pullup_out,
temp_out => temp,
temp_out_f => temp_f,
temp_err_out => temp_err_out,
pwm_out => pwm_out
);
end;
|
mit
|
jz0229/open-ephys-pcie
|
serdes-interface/firmware/main_sm.vhd
|
2
|
9486
|
----------------------------------------------------------------------------------
--This is the main state machine of the serdes FPGA
--it generates the appropriate command
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity main_sm is
port(
clk_spi : in std_logic;
reset : in std_logic;
miso_reg : in std_logic_vector(15 downto 0);
data_lclkin : in std_logic; --this the signal that signal's end of a SPI command.
spi_start_o : out std_logic;
command_o : out std_logic_vector(15 downto 0);
hsync_o : out std_logic
);
end main_sm;
architecture Behavioral of main_sm is
--state machine
type master_sm_type is (IDLE, REGCONF, ADCCONF, ACQ);
signal master_sm, master_sm_next : master_sm_type;
type hsync_sm_type is (IDLE, CH0);
signal hsync_state, hsync_state_next : hsync_sm_type;
--signals
signal sm_cnt, sm_cnt_next : unsigned(5 downto 0);
signal cmd, cmd_next : std_logic_vector(15 downto 0);
signal cmd_d1, cmd_d2 : std_logic_vector(7 downto 0); --this is the delay version of command. currently only use for checking the configurations
signal spi_start, spi_start_next : std_logic;
signal verify_cnt, verify_cnt_next : unsigned(5 downto 0);
signal hsync_cnt, hsync_cnt_next : unsigned(4 downto 0);
signal hsync, hsync_next : std_logic;
--a bank of all the configuration values
type rom_type is array ( 0 to 21) of std_logic_vector(7 downto 0);
type dummyrom_type is array (0 to 3) of std_logic_vector(15 downto 0);
constant CONVERT: std_logic_vector(1 downto 0) := "00";
constant CALIB: std_logic_vector(15 downto 0) := "0101010100000000";
constant CLEAR: std_logic_vector(15 downto 0) := "0110101000000000";
constant WRITEREG: std_logic_vector(1 downto 0) := "10";
constant READREG: std_logic_vector(1 downto 0) := "11";
constant NO_CONF_REG : integer := 21; --17 for 32 channel
constant DUMMY_ROM : dummyrom_type := (
"11" & std_logic_vector(to_unsigned(40,6)) & "00000000",
"11" & std_logic_vector(to_unsigned(41,6)) & "00000000",
"11" & std_logic_vector(to_unsigned(42,6)) & "00000000",
"11" & std_logic_vector(to_unsigned(43,6)) & "00000000"
);
--generate command
--command <= "11" & std_logic_vector(to_unsigned(41,6)) & "00000000"; --read from 40 to 44 registers
--configuration sequence
-- 7654 3210
--R0 0x80DE "1101 1110"
--R1 0x8102 "0000 0010" -ADC buffer bias, 2 for >700 KS/s sampling rate.
--R2 0x8204 "0000 0100" -MUX bias 4 for >700 KS/s sampling rate
--R3 0x8302 "0000 0010" -digital out HiZ
--R4 0x845F "0101 1111" -MISO pull to highZ when CS is pulled high. twocomp. no absmode, DSP offset remove, k_freq = 0.000004857Hz
--R5 0x8500 "0000 0000" -disable impedance check
--R6 0x8600 "0000 0000" -disable impedance check DAC
--R7 0x8700 "0000 0000" -disable impedance check amplifier
--R8 0x8811 "0001 0001" -RH1 DAC1: 17 upper cutoff 10KHz
--R9 0x8980 "1000 0000" -RH1 DAC2: 0
--R10 0x8A10 "0001 0000" -RH2 DAC1: 16
--R11 0x8B80 "1000 0000" -RH2 DAC2: 0
--R12 0x8C10 "0001 0000" -RL DAC1
--R13 0x8DDC "1101 1100" -RL DAC2:28 DAC3:1 cutoff: 0.1HZ??????????????????????? confirm
--R14 0x8EFF "1111 1111"
--R15 0x8FFF "1111 1111"
--R16 0x90FF "1111 1111"
--R17 0x91FF "1111 1111"
--for 64 channels
--R18 0x8EFF "1111 1111"
--R19 0x8FFF "1111 1111"
--R20 0x90FF "1111 1111"
--R21 0x91FF "1111 1111"
constant CONFIG_ROM : rom_type := (
-- 76543210
"11011110", --0x80DE
"00000010", --0x8102
"00000100", --0x8204
"00000010", --0x8302
"00011111", --0x845F
"00000000", --0x8500
"00000000", --0x8600
"00000000", --0x8700
"00010001", --0x8811
"10000000", --0x8980
"00010000", --0x8A10
"10000000", --0x8B80
"00010000", --0x8C10
"11011100", --0x8DDC
"11111111", --0x8EFF
"11111111", --0x8FFF
"11111111", --0x90FF
"11111111",
"11111111", --0x8EFF
"11111111", --0x8FFF
"11111111", --0x90FF
"11111111"); --0x91FF
begin
--signal mapping
command_o <= cmd;
spi_start_o <= spi_start;
hsync_o <= hsync;
--delay the cmd output with data_lclk
delay_cmd_prc : process(data_lclkin, clk_spi, reset, cmd_d1)
begin
if (reset = '1') then
cmd_d1 <= (others=>'0');
cmd_d2 <= (others=>'0');
elsif (rising_edge(clk_spi)) then
if data_lclkin = '1' then
cmd_d1 <= cmd(7 downto 0);
cmd_d2 <= cmd_d1;
else
cmd_d1 <= cmd_d1;
cmd_d2 <= cmd_d2;
end if;
end if;
end process;
--Main state machine
main_proc: process(clk_spi, reset)
begin
if (reset = '1') then
master_sm <= IDLE;
sm_cnt <= (others=>'0');
cmd <= (others=>'0');
verify_cnt <= (others=>'0');
spi_start <= '0';
elsif (rising_edge(clk_spi)) then --next state logic
master_sm <= master_sm_next;
sm_cnt <= sm_cnt_next;
cmd <= cmd_next;
verify_cnt <= verify_cnt_next;
spi_start <= spi_start_next;
end if;
end process;
--next state logic
main_proc_next: process(data_lclkin, sm_cnt, master_sm, cmd, cmd_d2, miso_reg, verify_cnt)
begin
case master_sm is
when IDLE =>
master_sm_next <= REGCONF;
spi_start_next <= '1';
sm_cnt_next <= sm_cnt + 1;
cmd_next <= WRITEREG & std_logic_vector(sm_cnt) & CONFIG_ROM(to_integer(sm_cnt));
verify_cnt_next <= (others=>'0');
when REGCONF => --go through all the configuration registers (generate command, and spi_start signal, look for data_lclkin before moving to the next state)
if data_lclkin = '1' then
if sm_cnt <= 2 then
sm_cnt_next <= sm_cnt + 1;
master_sm_next <= REGCONF;
cmd_next <= WRITEREG & std_logic_vector(sm_cnt) & CONFIG_ROM(to_integer(sm_cnt));
verify_cnt_next <= verify_cnt;
spi_start_next <= '1';
elsif sm_cnt <= NO_CONF_REG and sm_cnt > 2 then
sm_cnt_next <= sm_cnt + 1;
master_sm_next <= REGCONF;
cmd_next <= WRITEREG & std_logic_vector(sm_cnt) & CONFIG_ROM(to_integer(sm_cnt));
if miso_reg(7 downto 0) = cmd_d2(7 downto 0) then
verify_cnt_next <= verify_cnt + 1;
else
verify_cnt_next <= verify_cnt;
end if;
spi_start_next <= '1';
elsif sm_cnt > NO_CONF_REG and sm_cnt <= (NO_CONF_REG + 3) then --this is the last of the verification period
sm_cnt_next <= sm_cnt + 1;
master_sm_next <= REGCONF;
cmd_next <= (others=>'0');
if miso_reg(7 downto 0) = cmd_d2(7 downto 0) then
verify_cnt_next <= verify_cnt + 1;
else
verify_cnt_next <= verify_cnt;
end if;
spi_start_next <= '1';
else --when sm_cnt > 20
if verify_cnt = 22 then
master_sm_next <= ADCCONF;
sm_cnt_next <= (others=>'0');
spi_start_next <= '1';
cmd_next <= CALIB; --initiate the calibration command
else --otherwise stuck in REGCONF
master_sm_next <= REGCONF; --debug change
sm_cnt_next <= sm_cnt;
spi_start_next <= '0';
cmd_next <= (others=>'0');
end if;
verify_cnt_next <= verify_cnt;
end if;
else
sm_cnt_next <= sm_cnt;
spi_start_next <= '0';
master_sm_next <= master_sm;
cmd_next <= cmd;
verify_cnt_next <= verify_cnt;
end if;
when ADCCONF =>
if data_lclkin = '1' then
if sm_cnt <= 50 then --9
sm_cnt_next <= sm_cnt + 1;
master_sm_next <= ADCCONF;
cmd_next <= DUMMY_ROM(0);
else
sm_cnt_next <= (others=>'0');
master_sm_next <= ACQ;
cmd_next <= cmd;
end if;
spi_start_next <= '1';
else
sm_cnt_next <= sm_cnt;
spi_start_next <= '0'; --debug
master_sm_next <= master_sm;
cmd_next <= cmd;
end if;
verify_cnt_next <= verify_cnt;
when ACQ =>
if data_lclkin = '1' then
if sm_cnt >= 34 then --reset channel count back to 0
sm_cnt_next <= (others=>'0');
else
sm_cnt_next <= sm_cnt + 1;
end if;
cmd_next <= "00" & std_logic_vector(sm_cnt) & "00000000";
--cmd_next <= "11" & std_logic_vector(to_unsigned(59,6)) & "00000000"; --read from 40 to 44 registers --read for INTAN
spi_start_next <= '1';
else
sm_cnt_next <= sm_cnt;
spi_start_next <= '0';
cmd_next <= cmd;
end if;
master_sm_next <= ACQ;
verify_cnt_next <= verify_cnt;
end case;
end process;
--one shot hsync for channel 0
one_shot_hsync : process(clk_spi, reset)
begin
if (reset = '1') then
hsync_state <= IDLE;
hsync_cnt <= (others=>'0');
hsync <= '0';
elsif (rising_edge(clk_spi)) then
hsync_state <= hsync_state_next;
hsync_cnt <= hsync_cnt_next;
hsync <= hsync_next;
end if;
end process;
--hsync
one_shot_next_proc : process(master_sm, hsync_state, sm_cnt, hsync_cnt, data_lclkin)
begin
case hsync_state is
when IDLE =>
if master_sm = ACQ and sm_cnt = 1 and data_lclkin = '1' then
--go to the CH0 state
hsync_state_next <= CH0;
hsync_next <= '1';
else
hsync_state_next <= IDLE ;
hsync_next <= '0';
end if;
hsync_cnt_next <= (others=>'0');
when CH0 =>
if hsync_cnt >= 10 then
hsync_state_next <= IDLE;
hsync_cnt_next <= (others=>'0');
hsync_next <= '0';
else
hsync_state_next <= CH0;
hsync_cnt_next <= hsync_cnt + 1;
hsync_next <= '1';
end if;
end case;
end process;
end Behavioral;
|
mit
|
Hyvok/HardHeat
|
quartus/altera_pll_top.vhd
|
1
|
17629
|
-- megafunction wizard: %Altera PLL v15.0%
-- GENERATION: XML
-- altera_pll_top.vhd
-- Generated using ACDS version 15.0 145
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity altera_pll_top is
port (
refclk : in std_logic := '0'; -- refclk.clk
rst : in std_logic := '0'; -- reset.reset
outclk_0 : out std_logic; -- outclk0.clk
locked : out std_logic -- locked.export
);
end entity altera_pll_top;
architecture rtl of altera_pll_top is
component altera_pll_top_0002 is
port (
refclk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
outclk_0 : out std_logic; -- clk
locked : out std_logic -- export
);
end component altera_pll_top_0002;
begin
altera_pll_top_inst : component altera_pll_top_0002
port map (
refclk => refclk, -- refclk.clk
rst => rst, -- reset.reset
outclk_0 => outclk_0, -- outclk0.clk
locked => locked -- locked.export
);
end architecture rtl; -- of altera_pll_top
-- Retrieval info: <?xml version="1.0"?>
--<!--
-- Generated by Altera MegaWizard Launcher Utility version 1.0
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
-- ************************************************************
-- Copyright (C) 1991-2015 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
---->
-- Retrieval info: <instance entity-name="altera_pll" version="15.0" >
-- Retrieval info: <generic name="debug_print_output" value="false" />
-- Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
-- Retrieval info: <generic name="device_family" value="Cyclone V" />
-- Retrieval info: <generic name="device" value="Unknown" />
-- Retrieval info: <generic name="gui_device_speed_grade" value="1" />
-- Retrieval info: <generic name="gui_pll_mode" value="Integer-N PLL" />
-- Retrieval info: <generic name="gui_reference_clock_frequency" value="50.0" />
-- Retrieval info: <generic name="gui_channel_spacing" value="0.0" />
-- Retrieval info: <generic name="gui_operation_mode" value="direct" />
-- Retrieval info: <generic name="gui_feedback_clock" value="Global Clock" />
-- Retrieval info: <generic name="gui_fractional_cout" value="32" />
-- Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
-- Retrieval info: <generic name="gui_use_locked" value="true" />
-- Retrieval info: <generic name="gui_en_adv_params" value="false" />
-- Retrieval info: <generic name="gui_number_of_clocks" value="1" />
-- Retrieval info: <generic name="gui_multiply_factor" value="1" />
-- Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
-- Retrieval info: <generic name="gui_divide_factor_n" value="1" />
-- Retrieval info: <generic name="gui_cascade_counter0" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency0" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units0" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift0" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg0" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift0" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle0" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter1" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency1" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units1" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift1" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg1" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle1" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter2" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency2" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c2" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units2" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift2" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg2" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift2" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle2" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter3" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency3" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c3" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units3" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift3" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg3" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift3" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle3" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter4" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency4" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c4" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units4" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift4" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg4" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift4" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle4" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter5" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency5" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c5" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units5" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift5" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg5" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift5" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle5" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter6" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency6" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c6" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units6" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift6" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg6" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift6" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle6" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter7" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency7" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c7" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units7" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift7" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg7" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift7" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle7" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter8" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency8" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c8" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units8" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift8" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg8" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift8" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle8" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter9" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency9" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c9" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units9" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift9" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg9" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift9" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle9" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter10" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency10" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c10" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units10" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift10" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg10" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift10" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle10" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter11" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency11" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c11" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units11" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift11" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg11" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift11" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle11" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter12" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency12" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c12" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units12" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift12" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg12" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift12" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle12" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter13" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency13" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c13" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units13" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift13" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg13" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift13" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle13" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter14" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency14" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c14" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units14" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift14" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg14" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift14" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle14" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter15" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency15" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c15" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units15" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift15" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg15" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift15" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle15" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter16" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency16" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c16" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units16" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift16" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg16" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift16" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle16" value="50" />
-- Retrieval info: <generic name="gui_cascade_counter17" value="false" />
-- Retrieval info: <generic name="gui_output_clock_frequency17" value="100.0" />
-- Retrieval info: <generic name="gui_divide_factor_c17" value="1" />
-- Retrieval info: <generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
-- Retrieval info: <generic name="gui_ps_units17" value="ps" />
-- Retrieval info: <generic name="gui_phase_shift17" value="0" />
-- Retrieval info: <generic name="gui_phase_shift_deg17" value="0.0" />
-- Retrieval info: <generic name="gui_actual_phase_shift17" value="0" />
-- Retrieval info: <generic name="gui_duty_cycle17" value="50" />
-- Retrieval info: <generic name="gui_pll_auto_reset" value="Off" />
-- Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" />
-- Retrieval info: <generic name="gui_en_reconf" value="false" />
-- Retrieval info: <generic name="gui_en_dps_ports" value="false" />
-- Retrieval info: <generic name="gui_en_phout_ports" value="false" />
-- Retrieval info: <generic name="gui_phout_division" value="1" />
-- Retrieval info: <generic name="gui_mif_generate" value="false" />
-- Retrieval info: <generic name="gui_enable_mif_dps" value="false" />
-- Retrieval info: <generic name="gui_dps_cntr" value="C0" />
-- Retrieval info: <generic name="gui_dps_num" value="1" />
-- Retrieval info: <generic name="gui_dps_dir" value="Positive" />
-- Retrieval info: <generic name="gui_refclk_switch" value="false" />
-- Retrieval info: <generic name="gui_refclk1_frequency" value="100.0" />
-- Retrieval info: <generic name="gui_switchover_mode" value="Automatic Switchover" />
-- Retrieval info: <generic name="gui_switchover_delay" value="0" />
-- Retrieval info: <generic name="gui_active_clk" value="false" />
-- Retrieval info: <generic name="gui_clk_bad" value="false" />
-- Retrieval info: <generic name="gui_enable_cascade_out" value="false" />
-- Retrieval info: <generic name="gui_cascade_outclk_index" value="0" />
-- Retrieval info: <generic name="gui_enable_cascade_in" value="false" />
-- Retrieval info: <generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
-- Retrieval info: </instance>
-- IPFS_FILES : altera_pll_top.vho
-- RELATED_FILES: altera_pll_top.vhd, altera_pll_top_0002.v
|
mit
|
jz0229/open-ephys-pcie
|
serdes-interface/firmware/ipcore_dir/pll/simulation/timing/pll_tb.vhd
|
2
|
7391
|
-- file: pll_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity pll_tb is
end pll_tb;
architecture test of pll_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 10.0 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bit of the sampling counter
signal COUNT : std_logic;
-- Status and control signals
signal RESET : std_logic := '0';
signal LOCKED : std_logic;
signal COUNTER_RESET : std_logic := '0';
signal timeout_counter : std_logic_vector (13 downto 0) := (others => '0');
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(1 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component pll_exdes
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(1 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
report "Timing checks are not valid" severity note;
RESET <= '1';
wait for (PER1*6);
RESET <= '0';
wait until LOCKED = '1';
wait for (PER1*20);
COUNTER_RESET <= '1';
wait for (PER1*19.5);
COUNTER_RESET <= '0';
wait for (PER1*1);
report "Timing checks are valid" severity note;
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
process (CLK_IN1)
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
begin
if (CLK_IN1'event and CLK_IN1='1') then
timeout_counter <= timeout_counter + '1';
if (timeout_counter = "10000000000000") then
if (LOCKED /= '1') then
simtimeprint;
report "NO LOCK signal" severity failure;
end if;
end if;
end if;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : pll_exdes
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT,
-- Status and control signals
RESET => RESET,
LOCKED => LOCKED);
-- Freq Check
end test;
|
mit
|
Hyvok/HardHeat
|
src/ds18b20.vhd
|
1
|
6113
|
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.utils_pkg.all;
entity ds18b20 is
generic
(
-- Conversion delay in clock cycles
CONV_DELAY_VAL : natural
);
port
(
clk : in std_logic;
reset : in std_logic;
-- Request temperature
conv_in_f : in std_logic;
-- Connections to 1-wire module
data_in : in std_logic_vector(8 - 1 downto 0);
data_in_f : in std_logic;
busy_in : in std_logic;
error_in : in std_logic;
error_id_in : in unsigned(1 downto 0);
crc_in : in std_logic_vector(8 - 1 downto 0);
reset_ow_out : out std_logic;
data_out : out std_logic_vector(8 - 1 downto 0);
data_out_f : out std_logic;
receive_data_out_f : out std_logic;
-- Temperature output and associated strobe
temp_out : out signed(16 - 1 downto 0);
temp_out_f : out std_logic;
temp_error_out : out std_logic;
pullup_out : out std_logic
);
end entity;
architecture rtl of ds18b20 is
constant DS18B20_ROM_CMD : std_logic_vector(8 - 1 downto 0) := x"CC";
constant DS18B20_CONV_CMD : std_logic_vector(8 - 1 downto 0) := x"44";
constant DS18B20_READ_CMD : std_logic_vector(8 - 1 downto 0) := x"BE";
begin
handler_p: process(clk, reset)
type ds18b20_state is (idle, wait_busy, reset_ow, reset_error, rom_cmd,
conv_cmd, conv_delay, read_cmd, start_read, read_byte);
type data_array is array (9 - 1 downto 0) of
std_logic_vector(8 - 1 downto 0);
variable state : ds18b20_state;
variable next_state : ds18b20_state;
variable next_cmd : ds18b20_state;
variable data : data_array;
variable bytes_left : unsigned(ceil_log2(data_in'length) downto 0);
variable busy_state : std_logic;
variable timer : unsigned(ceil_log2(CONV_DELAY_VAL) downto 0);
begin
if reset = '1' then
state := idle;
next_state := idle;
next_cmd := conv_cmd;
reset_ow_out <= '0';
busy_state := '0';
data := (others => (others => '0'));
bytes_left := (others => '0');
timer := (others => '0');
receive_data_out_f <= '0';
data_out <= (others => '0');
data_out_f <= '0';
temp_out <= (others => '0');
temp_out_f <= '0';
temp_error_out <= '0';
pullup_out <= '1';
elsif rising_edge(clk) then
if state = idle then
temp_out_f <= '0';
if conv_in_f = '1' then
reset_ow_out <= '1';
state := reset_ow;
end if;
elsif state = wait_busy then
data_out_f <= '0';
if not busy_state = busy_in and busy_in = '0' then
state := next_state;
end if;
busy_state := busy_in;
elsif state = reset_ow then
bytes_left := to_unsigned(data'length, bytes_left'length);
reset_ow_out <= '0';
-- Reset error flag
temp_error_out <= '0';
pullup_out <= '1';
state := wait_busy;
next_state := reset_error;
elsif state = reset_error then
-- No device present on the bus, stop and go back to idle
if error_in = '1' and error_id_in = 1 then
temp_error_out <= '1';
state := idle;
else
state := rom_cmd;
end if;
elsif state = rom_cmd then
data_out <= DS18B20_ROM_CMD;
data_out_f <= '1';
state := wait_busy;
next_state := next_cmd;
elsif state = conv_cmd then
data_out <= DS18B20_CONV_CMD;
data_out_f <= '1';
state := wait_busy;
next_state := conv_delay;
elsif state = conv_delay then
data_out_f <= '0';
pullup_out <= '0';
if timer < CONV_DELAY_VAL then
timer := timer + 1;
else
timer := (others => '0');
next_cmd := read_cmd;
reset_ow_out <= '1';
state := reset_ow;
end if;
elsif state = read_cmd then
data_out <= DS18B20_READ_CMD;
data_out_f <= '1';
state := wait_busy;
next_cmd := conv_cmd;
next_state := start_read;
elsif state = start_read then
receive_data_out_f <= '1';
state := read_byte;
elsif state = read_byte then
receive_data_out_f <= '0';
if data_in_f = '1' then
data(data'length - to_integer(bytes_left)) := data_in;
bytes_left := bytes_left - 1;
if bytes_left = 0 then
-- If CRC is valid
if crc_in = x"00" then
state := idle;
temp_out <= signed(std_logic_vector'(
data(1) & data(0)));
temp_out_f <= '1';
else
state := idle;
temp_error_out <= '1';
end if;
else
state := start_read;
end if;
end if;
end if;
end if;
end process;
end;
|
mit
|
jz0229/open-ephys-pcie
|
serdes-interface/firmware/data_split.vhd
|
3
|
6099
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:56:40 05/16/2017
-- Design Name:
-- Module Name: data_split - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity data_split is
port(
pclk : in std_logic;
reset : in std_logic;
vsync : in std_logic;
din : in std_logic_vector(7 downto 0);
stream1_o : out std_logic_vector(15 downto 0);
stream2_o : out std_logic_vector(15 downto 0);
stream3_o : out std_logic_vector(15 downto 0);
stream4_o : out std_logic_vector(15 downto 0);
vsync_pcie_o : out std_logic
);
end data_split;
architecture Behavioral of data_split is
type split_state_type is (IDLE, S1MSB, S1LSB, S2MSB, S2LSB, S3MSB, S3LSB, S4MSB, S4LSB, LATCHDATA, WAITLOW); --state machine definition
signal split_state, split_state_next : split_state_type;
signal stream1, stream1_next: std_logic_vector(15 downto 0);
signal stream2, stream2_next: std_logic_vector(15 downto 0);
signal stream3, stream3_next: std_logic_vector(15 downto 0);
signal stream4, stream4_next: std_logic_vector(15 downto 0);
signal stream1_masked : std_logic_vector(15 downto 0);
signal stream2_masked : std_logic_vector(15 downto 0);
signal stream3_masked : std_logic_vector(15 downto 0);
signal stream4_masked : std_logic_vector(15 downto 0);
signal vsync_pcie : std_logic;
begin
--signal mapping
vsync_pcie_o <= vsync_pcie;
stream1_o <= stream1_masked;
stream2_o <= stream2_masked;
stream3_o <= stream3_masked;
stream4_o <= stream4_masked;
--vsync triggers the data spliting process
process(reset, split_state, pclk, stream1, stream2, stream3, stream4, stream1_masked, stream2_masked, stream3_masked, stream3_masked)
begin
if (reset='1') then
split_state <= IDLE;
stream1 <= (others=>'0');
stream2 <= (others=>'0');
stream3 <= (others=>'0');
stream4 <= (others=>'0');
stream1_masked <= (others=>'0');
stream2_masked <= (others=>'0');
stream3_masked <= (others=>'0');
stream4_masked <= (others=>'0');
vsync_pcie <= '0';
elsif (rising_edge(pclk)) then
split_state <= split_state_next;
stream1 <= stream1_next;
stream2 <= stream2_next;
stream3 <= stream3_next;
stream4 <= stream4_next;
if split_state = WAITLOW then
vsync_pcie <= '1';
else
vsync_pcie <= '0';
end if;
if split_state = LATCHDATA then
stream1_masked <= stream1;
stream2_masked <= stream2;
stream3_masked <= stream3;
stream4_masked <= stream4;
else
stream1_masked <= stream1_masked;
stream2_masked <= stream2_masked;
stream3_masked <= stream3_masked;
stream4_masked <= stream4_masked;
end if;
end if;
end process;
--next process
process(reset, split_state, vsync, pclk, stream1, stream2, stream3, stream4, din)
begin
case split_state is
when IDLE =>
if (vsync = '1') then
split_state_next <= S1MSB;
stream1_next(15 downto 8) <= din;
stream1_next(7 downto 0) <= stream1(7 downto 0);
else
split_state_next <= IDLE;
stream1_next <= stream1;
end if;
--2,3,4 unchanged
stream2_next <= stream2;
stream3_next <= stream3;
stream4_next <= stream4;
when S1MSB =>
stream1_next(15 downto 8) <= stream1(15 downto 8);
stream1_next(7 downto 0) <= din;
split_state_next <= S1LSB;
--2,3,4 unchanged
stream2_next <= stream2;
stream3_next <= stream3;
stream4_next <= stream4;
when S1LSB =>
split_state_next <= S2MSB;
--2 MSB
stream2_next(15 downto 8) <= din;
stream2_next(7 downto 0) <= stream2(7 downto 0);
--1,3,4 unchanged
stream1_next <= stream1;
stream3_next <= stream3;
stream4_next <= stream4;
when S2MSB =>
split_state_next <= S2LSB;
--2 LSB
stream2_next(15 downto 8) <= stream2(15 downto 8);
stream2_next(7 downto 0) <= din;
--1,3,4 unchanged
stream1_next <= stream1;
stream3_next <= stream3;
stream4_next <= stream4;
when S2LSB =>
split_state_next <= S3MSB;
--3 MSB
stream3_next(15 downto 8) <= din;
stream3_next(7 downto 0) <= stream3(7 downto 0);
--1,2,4 unchanged
stream1_next <= stream1;
stream2_next <= stream2;
stream4_next <= stream4;
when S3MSB =>
split_state_next <= S3LSB;
--3 LSB
stream3_next(15 downto 8) <= stream3(15 downto 8);
stream3_next(7 downto 0) <= din;
--1,2,4 unchanged
stream1_next <= stream1;
stream2_next <= stream2;
stream4_next <= stream4;
when S3LSB =>
split_state_next <= S4MSB;
--4 MSB
stream4_next(15 downto 8) <= din;
stream4_next(7 downto 0) <= stream4(7 downto 0);
--1,2,3 unchanged
stream1_next <= stream1;
stream2_next <= stream2;
stream3_next <= stream3;
when S4MSB =>
split_state_next <= S4LSB;
--4 LSB
stream4_next(15 downto 8) <= stream4(15 downto 8);
stream4_next(7 downto 0) <= din;
--1,2,3 unchanged
stream1_next <= stream1;
stream2_next <= stream2;
stream3_next <= stream3;
when S4LSB =>
split_state_next <= LATCHDATA;
stream1_next <= stream1;
stream2_next <= stream2;
stream3_next <= stream3;
stream4_next <= stream4;
when LATCHDATA =>
stream1_next <= stream1;
split_state_next <= WAITLOW;
stream1_next <= stream1;
stream2_next <= stream2;
stream3_next <= stream3;
stream4_next <= stream4;
when WAITLOW =>
if (vsync = '0') then
split_state_next <= IDLE;
else
split_state_next <= WAITLOW;
end if;
stream1_next <= stream1;
stream2_next <= stream2;
stream3_next <= stream3;
stream4_next <= stream4;
end case;
end process;
end Behavioral;
|
mit
|
Hyvok/HardHeat
|
sim/adpll/adpll_tb.vhd
|
1
|
1381
|
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adpll_tb is
end entity;
architecture rtl of adpll_tb is
-- Clock frequency 100 MHz
constant CLK_PERIOD : time := 1 sec / 10e7;
-- Reference signal frequency 50 kHz
constant REF_PERIOD : time := 1 sec / 90e3;
signal clk : std_logic := '0';
signal reset : std_logic;
signal ref : std_logic := '0';
begin
DUT_inst: entity work.adpll(rtl)
generic map
(
TDC_N => 13,
FILT_P_SHIFT_N => 0,
FILT_I_SHIFT_N => -5,
ACCUM_BITS_N => 32,
ACCUM_WORD_N => 23,
FILT_INIT_OUT_VAL => 2**11,
FILT_OUT_OFFSET => 2**21,
FILT_OUT_LIMIT => 2**22,
LD_LOCK_N => 20,
LD_ULOCK_N => 16,
LD_LOCK_LIMIT => 100
)
port map
(
clk => clk,
reset => reset,
ref_in => ref
);
reset <= '1', '0' after 500 ns;
clk_gen: process(clk)
begin
clk <= not clk after CLK_PERIOD / 2;
end process;
ref_gen: process(ref)
begin
ref <= not ref after REF_PERIOD / 2;
end process;
end;
|
mit
|
jz0229/open-ephys-pcie
|
oepcie_host_firmware/HDLs/TB_hs_com_control.vhd
|
1
|
2083
|
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
use work.myDeclare.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY TB_hs_com_control IS
END TB_hs_com_control;
ARCHITECTURE behavior OF TB_hs_com_control IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT hs_com_control
PORT(
bus_clk : IN std_logic;
global_reset : IN std_logic;
hs_com_fifo_data : OUT std_logic_vector(31 downto 0);
dev_reset_in : in std_logic;
hs_com_fifo_enb : OUT std_logic
);
END COMPONENT;
--Inputs
signal bus_clk : std_logic := '0';
signal global_reset : std_logic := '0';
signal dev_reset_in : std_logic := '0';
--Outputs
signal hs_com_fifo_data : std_logic_vector(31 downto 0);
signal hs_com_fifo_enb : std_logic;
-- Clock period definitions
constant bus_clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: hs_com_control PORT MAP (
bus_clk => bus_clk,
global_reset => global_reset,
dev_reset_in => dev_reset_in,
hs_com_fifo_data => hs_com_fifo_data,
hs_com_fifo_enb => hs_com_fifo_enb
);
-- Clock process definitions
bus_clk_process :process
begin
bus_clk <= '0';
wait for bus_clk_period/2;
bus_clk <= '1';
wait for bus_clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
global_reset <= '1';
dev_reset_in <= '1';
wait for 100 ns;
global_reset <= '0';
dev_reset_in <= '0';
wait for 5 ms;
global_reset <= '1';
wait for 100 ns;
global_reset <= '0';
wait;
end process;
END;
|
mit
|
Hyvok/HardHeat
|
sim/pwr_sequencer/pwr_sequencer_tb.vhd
|
1
|
3166
|
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pwr_sequencer_tb is
generic
(
LEVELS_N : natural := 3;
TEST_D : natural := 10000
);
end entity;
architecture rtl of pwr_sequencer_tb is
-- Main clock frequency 100 MHz
constant CLK_PERIOD : time := 1 sec / 10e7;
signal clk : std_logic := '0';
signal reset : std_logic;
signal main_pwr_en : std_logic;
signal main_pwr_fail : std_logic;
signal start : std_logic;
signal fail : std_logic_vector(LEVELS_N - 1 downto 0);
signal enable : std_logic_vector(LEVELS_N - 1 downto 0);
begin
reset <= '1', '0' after 500 ns;
clk_gen: process(clk)
begin
clk <= not clk after CLK_PERIOD / 2;
end process;
DUT_inst: entity work.pwr_sequencer(rtl)
generic map
(
LEVELS_N => LEVELS_N
)
port map
(
clk => clk,
reset => reset,
start_in => start,
fail_in => fail,
en_out => enable,
main_pwr_en_out => main_pwr_en,
main_pwr_fail_out => main_pwr_fail
);
fail_gen: process(clk, reset)
type state_t is (idle, delay, power_on, cause_fail);
variable state : state_t;
variable timer : natural;
variable cur_level : natural;
begin
if reset = '1' then
state := idle;
timer := 0;
fail <= (others => '1');
cur_level := 0;
start <= '0';
elsif rising_edge(clk) then
if state = idle then
start <= '1';
for i in 0 to enable'high loop
if enable(i) = '1' then
cur_level := i;
state := delay;
end if;
end loop;
elsif state = delay then
timer := timer + 1;
if timer > TEST_D then
fail(cur_level) <= '0';
timer := 0;
if cur_level = enable'high then
state := power_on;
else
state := idle;
end if;
end if;
elsif state = power_on then
timer := timer + 1;
-- After succesfull sequencing cause a failure
if timer > TEST_D then
fail(0) <= '1';
timer := 0;
state := cause_fail;
end if;
elsif state = cause_fail then
timer := timer + 1;
start <= '0';
-- After succesfull power failure, restart
if timer > TEST_D then
start <= '1';
fail <= (others => '1');
timer := 0;
state := idle;
end if;
end if;
end if;
end process;
end;
|
mit
|
zerokill/vhdl-course
|
exercise_2/alu_tb.vhd
|
1
|
55763
|
-- Test Bench voor opdracht 3
-- Datum : 18 Mei 2007
-- E.G. van den Bor
-- Hogeschool Utrecht
--
-- In deze testbench worden een aantal constanten aan ingang A en B
-- gegeven.
-- Bij alle combinaties van de Code (deel van een ALU instructie)
-- wordt het resultaat van de aangeboden constanten gecontroleerd.
-- Deze testbench bestaat uit vijf processen
-- Dit zijn :
-- Stim_A en Stim_B : hierin worden de constanten gekoppeld aan ingang A en B
-- Stim_code : Hierin wordt de Code voor iedere bewerking bepaald
-- Expected : Hierin wordt de verwachtw waarde berekend
-- Controle : controleert of de uitgang overeen komt met de verwachte waarde
-- de vijf processen lopen parallel (concurrent).
-- Na iedere 10 ns is er een nieuw resultaat bekend.
-- De controle vindt plaats net voordat een nieuwe waarde wordt aangboden
-- Namelijk na 9 ns Zodat het uitgangssignaal stabiel is.
entity ALU_TB is
end;
library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;
architecture Bench of ALU_TB is
constant OP_SIZE : POSITIVE := 4; -- breedte van de opcode
-- Signalen die aan de ALU file worden verbonden
-- ingangen van de ALU
signal A, B: std_logic_vector(7 downto 0) := (others => '0');
signal Code: std_logic_vector(OP_SIZE-1 downto 0);
-- uitgangen van de ALU
signal Cout, Equal : Std_logic;
signal F: std_logic_vector(7 downto 0);
-- De onderstaande constanten worden als testwaarden
-- gebruikt van zowel ingang A als B bij iedere mogelijke
-- bewerking
constant Value0: Std_logic_vector := "00000000";
constant Value1: Std_logic_vector := "00000001";
constant Value2: Std_logic_vector := "00000011";
constant Value3: Std_logic_vector := "00001000";
constant Value4: Std_logic_vector := "00001111";
constant Value5: Std_logic_vector := "10000000";
constant Value6: Std_logic_vector := "11111000";
constant Value7: Std_logic_vector := "11111111";
constant NUM_TESTCONST : POSITIVE := 8; -- aantal testconstanten
constant NUM_OPCODES : POSITIVE := 2 ** OP_SIZE; -- aantal opcodes
constant NUM_TOT_VECTORS : POSITIVE := NUM_TESTCONST * NUM_TESTCONST * NUM_OPCODES;
-- totaal aantal testvectoren
-- Vertragingstijden
constant OP_DELAY : TIME := 10 ns;
constant A_DELAY : TIME := NUM_OPCODES * OP_DELAY;
constant B_DELAY : TIME := NUM_TESTCONST * A_DELAY;
-- Verwachte resultaten en fouttellers
signal Verwacht : Std_logic_vector(1 to 10); -- hierin komen de
-- verwachte resultaten
constant DONT_CARE : Std_logic_vector(7 downto 0) := "--------";
signal F_fout_teller : NATURAL := 0;
signal Cout_fout_teller : NATURAL := 0;
signal Equal_fout_teller : NATURAL := 0;
signal F_OK : BOOLEAN := TRUE;
signal Cout_OK : BOOLEAN := TRUE;
signal Equal_OK : BOOLEAN := TRUE;
begin
-- Koppel eerste de testbench file aan de ALU file
UUT: entity work.ALU port map (
A => A,
B => B,
Code => Code,
F => F,
Cout => Cout,
Equal => Equal);
-- Koppel aan ingang B steeds een testconstante
Stim_B: process
begin
B <= Value0;
wait for B_DELAY;
B <= Value1;
wait for B_DELAY;
B <= Value2;
wait for B_DELAY;
B <= Value3;
wait for B_DELAY;
B <= Value4;
wait for B_DELAY;
B <= Value5;
wait for B_DELAY;
B <= Value6;
wait for B_DELAY;
B <= Value7;
wait for B_DELAY;
wait;
end process Stim_B;
-- Koppel aan ingang A steeds een testconstante
-- terwijl ingang B tijdelijk gelijk blijft
Stim_A: process
begin
for I in 1 to NUM_TESTCONST loop
A <= Value0;
wait for A_DELAY;
A <= Value1;
wait for A_DELAY;
A <= Value2;
wait for A_DELAY;
A <= Value3;
wait for A_DELAY;
A <= Value4;
wait for A_DELAY;
A <= Value5;
wait for A_DELAY;
A <= Value6;
wait for A_DELAY;
A <= Value7;
wait for A_DELAY;
end loop;
wait;
end process Stim_A;
-- Geef de Opcode bij alle mogelijke combinaties van A en B
-- inclusief de niet gebruikte opcodes
Stim_Code: process
begin
for I in 1 to NUM_TESTCONST * NUM_TESTCONST loop
for J in 0 to NUM_OPCODES-1 loop
Code <= Std_logic_vector(To_unsigned(J,4));
wait for OP_DELAY;
end loop;
end loop;
wait;
end process Stim_Code;
-- Geef de verwachte waarden en plaats die in het signal "Verwacht".
Expected: process
begin
Verwacht <= "0000000001"; wait for OP_DELAY;
Verwacht <= "0000000001"; wait for OP_DELAY;
Verwacht <= "0000000001"; wait for OP_DELAY;
Verwacht <= "---------1"; wait for OP_DELAY;
Verwacht <= "0000000001"; wait for OP_DELAY;
Verwacht <= "0000000001"; wait for OP_DELAY;
Verwacht <= "0000000001"; wait for OP_DELAY;
Verwacht <= "0000000001"; wait for OP_DELAY;
Verwacht <= "0000000001"; wait for OP_DELAY;
Verwacht <= "0000000001"; wait for OP_DELAY;
Verwacht <= "0000000001"; wait for OP_DELAY;
Verwacht <= "0000000001"; wait for OP_DELAY;
Verwacht <= "---------1"; wait for OP_DELAY;
Verwacht <= "---------1"; wait for OP_DELAY;
Verwacht <= "0000000001"; wait for OP_DELAY;
Verwacht <= "1111111111"; wait for OP_DELAY;
Verwacht <= "0000000100"; wait for OP_DELAY;
Verwacht <= "0000000100"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000100"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0000001000"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0000001000"; wait for OP_DELAY;
Verwacht <= "1000000000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0000001100"; wait for OP_DELAY;
Verwacht <= "0000001100"; wait for OP_DELAY;
Verwacht <= "1111110110"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000001100"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111110110"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0000011000"; wait for OP_DELAY;
Verwacht <= "0000000100"; wait for OP_DELAY;
Verwacht <= "0000011000"; wait for OP_DELAY;
Verwacht <= "1000000100"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0000100000"; wait for OP_DELAY;
Verwacht <= "0000100000"; wait for OP_DELAY;
Verwacht <= "1111100010"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000100000"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111100010"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0001000000"; wait for OP_DELAY;
Verwacht <= "0000010000"; wait for OP_DELAY;
Verwacht <= "0001000000"; wait for OP_DELAY;
Verwacht <= "0000010000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0000111100"; wait for OP_DELAY;
Verwacht <= "0000111100"; wait for OP_DELAY;
Verwacht <= "1111000110"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000111100"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111000110"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0001111000"; wait for OP_DELAY;
Verwacht <= "0000011100"; wait for OP_DELAY;
Verwacht <= "0001111000"; wait for OP_DELAY;
Verwacht <= "1000011100"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "1000000010"; wait for OP_DELAY;
Verwacht <= "1000000010"; wait for OP_DELAY;
Verwacht <= "1000000000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "1000000010"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1000000000"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0000000010"; wait for OP_DELAY;
Verwacht <= "0100000000"; wait for OP_DELAY;
Verwacht <= "0000000110"; wait for OP_DELAY;
Verwacht <= "0100000000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "1111100010"; wait for OP_DELAY;
Verwacht <= "1111100010"; wait for OP_DELAY;
Verwacht <= "0000100000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "1111100010"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0000100000"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111000010"; wait for OP_DELAY;
Verwacht <= "0111110000"; wait for OP_DELAY;
Verwacht <= "1111000110"; wait for OP_DELAY;
Verwacht <= "0111110000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0000000100"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0000000100"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111010"; wait for OP_DELAY;
Verwacht <= "0111111100"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "1111111100"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0000000100"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0000000100"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0000000100"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0000001001"; wait for OP_DELAY;
Verwacht <= "0000000001"; wait for OP_DELAY;
Verwacht <= "0000000001"; wait for OP_DELAY;
Verwacht <= "---------1"; wait for OP_DELAY;
Verwacht <= "0000000101"; wait for OP_DELAY;
Verwacht <= "0000000101"; wait for OP_DELAY;
Verwacht <= "1111111111"; wait for OP_DELAY;
Verwacht <= "1111111111"; wait for OP_DELAY;
Verwacht <= "0000001001"; wait for OP_DELAY;
Verwacht <= "0000000001"; wait for OP_DELAY;
Verwacht <= "0000001001"; wait for OP_DELAY;
Verwacht <= "1000000001"; wait for OP_DELAY;
Verwacht <= "---------1"; wait for OP_DELAY;
Verwacht <= "---------1"; wait for OP_DELAY;
Verwacht <= "0000000001"; wait for OP_DELAY;
Verwacht <= "1111111111"; wait for OP_DELAY;
Verwacht <= "0000010000"; wait for OP_DELAY;
Verwacht <= "0000001000"; wait for OP_DELAY;
Verwacht <= "1111111010"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000001100"; wait for OP_DELAY;
Verwacht <= "0000000100"; wait for OP_DELAY;
Verwacht <= "1111110110"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0000011000"; wait for OP_DELAY;
Verwacht <= "0000000100"; wait for OP_DELAY;
Verwacht <= "0000011000"; wait for OP_DELAY;
Verwacht <= "1000000100"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0000100100"; wait for OP_DELAY;
Verwacht <= "0000011100"; wait for OP_DELAY;
Verwacht <= "1111100110"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000100000"; wait for OP_DELAY;
Verwacht <= "0000000100"; wait for OP_DELAY;
Verwacht <= "1111100010"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0001000000"; wait for OP_DELAY;
Verwacht <= "0000010000"; wait for OP_DELAY;
Verwacht <= "0001000000"; wait for OP_DELAY;
Verwacht <= "0000010000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0001000000"; wait for OP_DELAY;
Verwacht <= "0000111000"; wait for OP_DELAY;
Verwacht <= "1111001010"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000111100"; wait for OP_DELAY;
Verwacht <= "0000000100"; wait for OP_DELAY;
Verwacht <= "1111000110"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0001111000"; wait for OP_DELAY;
Verwacht <= "0000011100"; wait for OP_DELAY;
Verwacht <= "0001111000"; wait for OP_DELAY;
Verwacht <= "1000011100"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "1000000110"; wait for OP_DELAY;
Verwacht <= "0111111110"; wait for OP_DELAY;
Verwacht <= "1000000100"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "1000000010"; wait for OP_DELAY;
Verwacht <= "0000000100"; wait for OP_DELAY;
Verwacht <= "1000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0000000010"; wait for OP_DELAY;
Verwacht <= "0100000000"; wait for OP_DELAY;
Verwacht <= "0000000110"; wait for OP_DELAY;
Verwacht <= "0100000000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "1111100110"; wait for OP_DELAY;
Verwacht <= "1111011110"; wait for OP_DELAY;
Verwacht <= "0000100100"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "1111100010"; wait for OP_DELAY;
Verwacht <= "0000000100"; wait for OP_DELAY;
Verwacht <= "0000100000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "1111000010"; wait for OP_DELAY;
Verwacht <= "0111110000"; wait for OP_DELAY;
Verwacht <= "1111000110"; wait for OP_DELAY;
Verwacht <= "0111110000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111010"; wait for OP_DELAY;
Verwacht <= "0000001000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0000000100"; wait for OP_DELAY;
Verwacht <= "0000000100"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "1111111010"; wait for OP_DELAY;
Verwacht <= "0111111100"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "1111111100"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0000001100"; wait for OP_DELAY;
Verwacht <= "1111110110"; wait for OP_DELAY;
Verwacht <= "0000001100"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0000001100"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111110110"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0000010000"; wait for OP_DELAY;
Verwacht <= "1111111010"; wait for OP_DELAY;
Verwacht <= "0000001000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000100"; wait for OP_DELAY;
Verwacht <= "0000001100"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "1111110110"; wait for OP_DELAY;
Verwacht <= "0000001000"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0000001000"; wait for OP_DELAY;
Verwacht <= "1000000000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0000011001"; wait for OP_DELAY;
Verwacht <= "0000000001"; wait for OP_DELAY;
Verwacht <= "0000000001"; wait for OP_DELAY;
Verwacht <= "---------1"; wait for OP_DELAY;
Verwacht <= "0000001101"; wait for OP_DELAY;
Verwacht <= "0000001101"; wait for OP_DELAY;
Verwacht <= "1111110111"; wait for OP_DELAY;
Verwacht <= "1111110111"; wait for OP_DELAY;
Verwacht <= "0000011001"; wait for OP_DELAY;
Verwacht <= "0000000101"; wait for OP_DELAY;
Verwacht <= "0000011001"; wait for OP_DELAY;
Verwacht <= "1000000101"; wait for OP_DELAY;
Verwacht <= "---------1"; wait for OP_DELAY;
Verwacht <= "---------1"; wait for OP_DELAY;
Verwacht <= "0000000001"; wait for OP_DELAY;
Verwacht <= "1111111111"; wait for OP_DELAY;
Verwacht <= "0000101100"; wait for OP_DELAY;
Verwacht <= "0000010100"; wait for OP_DELAY;
Verwacht <= "1111101110"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000100000"; wait for OP_DELAY;
Verwacht <= "0000001100"; wait for OP_DELAY;
Verwacht <= "1111100010"; wait for OP_DELAY;
Verwacht <= "1111110110"; wait for OP_DELAY;
Verwacht <= "0001000000"; wait for OP_DELAY;
Verwacht <= "0000010000"; wait for OP_DELAY;
Verwacht <= "0001000000"; wait for OP_DELAY;
Verwacht <= "0000010000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0001001000"; wait for OP_DELAY;
Verwacht <= "0000110000"; wait for OP_DELAY;
Verwacht <= "1111010010"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000111100"; wait for OP_DELAY;
Verwacht <= "0000001100"; wait for OP_DELAY;
Verwacht <= "1111000110"; wait for OP_DELAY;
Verwacht <= "1111110110"; wait for OP_DELAY;
Verwacht <= "0001111000"; wait for OP_DELAY;
Verwacht <= "0000011100"; wait for OP_DELAY;
Verwacht <= "0001111000"; wait for OP_DELAY;
Verwacht <= "1000011100"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "1000001110"; wait for OP_DELAY;
Verwacht <= "0111110110"; wait for OP_DELAY;
Verwacht <= "1000001100"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "1000000010"; wait for OP_DELAY;
Verwacht <= "0000001100"; wait for OP_DELAY;
Verwacht <= "1000000000"; wait for OP_DELAY;
Verwacht <= "1111110110"; wait for OP_DELAY;
Verwacht <= "0000000010"; wait for OP_DELAY;
Verwacht <= "0100000000"; wait for OP_DELAY;
Verwacht <= "0000000110"; wait for OP_DELAY;
Verwacht <= "0100000000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "1111101110"; wait for OP_DELAY;
Verwacht <= "1111010110"; wait for OP_DELAY;
Verwacht <= "0000101100"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "1111100010"; wait for OP_DELAY;
Verwacht <= "0000001100"; wait for OP_DELAY;
Verwacht <= "0000100000"; wait for OP_DELAY;
Verwacht <= "1111110110"; wait for OP_DELAY;
Verwacht <= "1111000010"; wait for OP_DELAY;
Verwacht <= "0111110000"; wait for OP_DELAY;
Verwacht <= "1111000110"; wait for OP_DELAY;
Verwacht <= "0111110000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0000001000"; wait for OP_DELAY;
Verwacht <= "1111110010"; wait for OP_DELAY;
Verwacht <= "0000010000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0000001100"; wait for OP_DELAY;
Verwacht <= "0000000100"; wait for OP_DELAY;
Verwacht <= "1111110110"; wait for OP_DELAY;
Verwacht <= "1111111010"; wait for OP_DELAY;
Verwacht <= "0111111100"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "1111111100"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0000100000"; wait for OP_DELAY;
Verwacht <= "1111100010"; wait for OP_DELAY;
Verwacht <= "0000100000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0000100000"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111100010"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0000100100"; wait for OP_DELAY;
Verwacht <= "1111100110"; wait for OP_DELAY;
Verwacht <= "0000011100"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000100"; wait for OP_DELAY;
Verwacht <= "0000100000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "1111100010"; wait for OP_DELAY;
Verwacht <= "0000001000"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0000001000"; wait for OP_DELAY;
Verwacht <= "1000000000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0000101100"; wait for OP_DELAY;
Verwacht <= "1111101110"; wait for OP_DELAY;
Verwacht <= "0000010100"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000001100"; wait for OP_DELAY;
Verwacht <= "0000100000"; wait for OP_DELAY;
Verwacht <= "1111110110"; wait for OP_DELAY;
Verwacht <= "1111100010"; wait for OP_DELAY;
Verwacht <= "0000011000"; wait for OP_DELAY;
Verwacht <= "0000000100"; wait for OP_DELAY;
Verwacht <= "0000011000"; wait for OP_DELAY;
Verwacht <= "1000000100"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0001000001"; wait for OP_DELAY;
Verwacht <= "0000000001"; wait for OP_DELAY;
Verwacht <= "0000000001"; wait for OP_DELAY;
Verwacht <= "---------1"; wait for OP_DELAY;
Verwacht <= "0000100001"; wait for OP_DELAY;
Verwacht <= "0000100001"; wait for OP_DELAY;
Verwacht <= "1111100011"; wait for OP_DELAY;
Verwacht <= "1111100011"; wait for OP_DELAY;
Verwacht <= "0001000001"; wait for OP_DELAY;
Verwacht <= "0000010001"; wait for OP_DELAY;
Verwacht <= "0001000001"; wait for OP_DELAY;
Verwacht <= "0000010001"; wait for OP_DELAY;
Verwacht <= "---------1"; wait for OP_DELAY;
Verwacht <= "---------1"; wait for OP_DELAY;
Verwacht <= "0000000001"; wait for OP_DELAY;
Verwacht <= "1111111111"; wait for OP_DELAY;
Verwacht <= "0001011100"; wait for OP_DELAY;
Verwacht <= "0000011100"; wait for OP_DELAY;
Verwacht <= "1111100110"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000111100"; wait for OP_DELAY;
Verwacht <= "0000100000"; wait for OP_DELAY;
Verwacht <= "1111000110"; wait for OP_DELAY;
Verwacht <= "1111100010"; wait for OP_DELAY;
Verwacht <= "0001111000"; wait for OP_DELAY;
Verwacht <= "0000011100"; wait for OP_DELAY;
Verwacht <= "0001111000"; wait for OP_DELAY;
Verwacht <= "1000011100"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "1000100010"; wait for OP_DELAY;
Verwacht <= "0111100010"; wait for OP_DELAY;
Verwacht <= "1000100000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "1000000010"; wait for OP_DELAY;
Verwacht <= "0000100000"; wait for OP_DELAY;
Verwacht <= "1000000000"; wait for OP_DELAY;
Verwacht <= "1111100010"; wait for OP_DELAY;
Verwacht <= "0000000010"; wait for OP_DELAY;
Verwacht <= "0100000000"; wait for OP_DELAY;
Verwacht <= "0000000110"; wait for OP_DELAY;
Verwacht <= "0100000000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111000010"; wait for OP_DELAY;
Verwacht <= "0001000000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "1111100010"; wait for OP_DELAY;
Verwacht <= "0000100000"; wait for OP_DELAY;
Verwacht <= "0000100000"; wait for OP_DELAY;
Verwacht <= "1111100010"; wait for OP_DELAY;
Verwacht <= "1111000010"; wait for OP_DELAY;
Verwacht <= "0111110000"; wait for OP_DELAY;
Verwacht <= "1111000110"; wait for OP_DELAY;
Verwacht <= "0111110000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0000011100"; wait for OP_DELAY;
Verwacht <= "1111011110"; wait for OP_DELAY;
Verwacht <= "0000100100"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0000100000"; wait for OP_DELAY;
Verwacht <= "0000000100"; wait for OP_DELAY;
Verwacht <= "1111100010"; wait for OP_DELAY;
Verwacht <= "1111111010"; wait for OP_DELAY;
Verwacht <= "0111111100"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "1111111100"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0000111100"; wait for OP_DELAY;
Verwacht <= "1111000110"; wait for OP_DELAY;
Verwacht <= "0000111100"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0000111100"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111000110"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0001000000"; wait for OP_DELAY;
Verwacht <= "1111001010"; wait for OP_DELAY;
Verwacht <= "0000111000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000100"; wait for OP_DELAY;
Verwacht <= "0000111100"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "1111000110"; wait for OP_DELAY;
Verwacht <= "0000001000"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0000001000"; wait for OP_DELAY;
Verwacht <= "1000000000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0001001000"; wait for OP_DELAY;
Verwacht <= "1111010010"; wait for OP_DELAY;
Verwacht <= "0000110000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000001100"; wait for OP_DELAY;
Verwacht <= "0000111100"; wait for OP_DELAY;
Verwacht <= "1111110110"; wait for OP_DELAY;
Verwacht <= "1111000110"; wait for OP_DELAY;
Verwacht <= "0000011000"; wait for OP_DELAY;
Verwacht <= "0000000100"; wait for OP_DELAY;
Verwacht <= "0000011000"; wait for OP_DELAY;
Verwacht <= "1000000100"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0001011100"; wait for OP_DELAY;
Verwacht <= "1111100110"; wait for OP_DELAY;
Verwacht <= "0000011100"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000100000"; wait for OP_DELAY;
Verwacht <= "0000111100"; wait for OP_DELAY;
Verwacht <= "1111100010"; wait for OP_DELAY;
Verwacht <= "1111000110"; wait for OP_DELAY;
Verwacht <= "0001000000"; wait for OP_DELAY;
Verwacht <= "0000010000"; wait for OP_DELAY;
Verwacht <= "0001000000"; wait for OP_DELAY;
Verwacht <= "0000010000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0001111001"; wait for OP_DELAY;
Verwacht <= "0000000001"; wait for OP_DELAY;
Verwacht <= "0000000001"; wait for OP_DELAY;
Verwacht <= "---------1"; wait for OP_DELAY;
Verwacht <= "0000111101"; wait for OP_DELAY;
Verwacht <= "0000111101"; wait for OP_DELAY;
Verwacht <= "1111000111"; wait for OP_DELAY;
Verwacht <= "1111000111"; wait for OP_DELAY;
Verwacht <= "0001111001"; wait for OP_DELAY;
Verwacht <= "0000011101"; wait for OP_DELAY;
Verwacht <= "0001111001"; wait for OP_DELAY;
Verwacht <= "1000011101"; wait for OP_DELAY;
Verwacht <= "---------1"; wait for OP_DELAY;
Verwacht <= "---------1"; wait for OP_DELAY;
Verwacht <= "0000000001"; wait for OP_DELAY;
Verwacht <= "1111111111"; wait for OP_DELAY;
Verwacht <= "1000111110"; wait for OP_DELAY;
Verwacht <= "0111000110"; wait for OP_DELAY;
Verwacht <= "1000111100"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "1000000010"; wait for OP_DELAY;
Verwacht <= "0000111100"; wait for OP_DELAY;
Verwacht <= "1000000000"; wait for OP_DELAY;
Verwacht <= "1111000110"; wait for OP_DELAY;
Verwacht <= "0000000010"; wait for OP_DELAY;
Verwacht <= "0100000000"; wait for OP_DELAY;
Verwacht <= "0000000110"; wait for OP_DELAY;
Verwacht <= "0100000000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0000011100"; wait for OP_DELAY;
Verwacht <= "1110100110"; wait for OP_DELAY;
Verwacht <= "0001011100"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "1111100010"; wait for OP_DELAY;
Verwacht <= "0000111100"; wait for OP_DELAY;
Verwacht <= "0000100000"; wait for OP_DELAY;
Verwacht <= "1111000110"; wait for OP_DELAY;
Verwacht <= "1111000010"; wait for OP_DELAY;
Verwacht <= "0111110000"; wait for OP_DELAY;
Verwacht <= "1111000110"; wait for OP_DELAY;
Verwacht <= "0111110000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0000111000"; wait for OP_DELAY;
Verwacht <= "1111000010"; wait for OP_DELAY;
Verwacht <= "0001000000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0000111100"; wait for OP_DELAY;
Verwacht <= "0000000100"; wait for OP_DELAY;
Verwacht <= "1111000110"; wait for OP_DELAY;
Verwacht <= "1111111010"; wait for OP_DELAY;
Verwacht <= "0111111100"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "1111111100"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "1000000010"; wait for OP_DELAY;
Verwacht <= "1000000000"; wait for OP_DELAY;
Verwacht <= "1000000010"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1000000010"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1000000000"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "1000000110"; wait for OP_DELAY;
Verwacht <= "1000000100"; wait for OP_DELAY;
Verwacht <= "0111111110"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000100"; wait for OP_DELAY;
Verwacht <= "1000000010"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "1000000000"; wait for OP_DELAY;
Verwacht <= "0000001000"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0000001000"; wait for OP_DELAY;
Verwacht <= "1000000000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "1000001110"; wait for OP_DELAY;
Verwacht <= "1000001100"; wait for OP_DELAY;
Verwacht <= "0111110110"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000001100"; wait for OP_DELAY;
Verwacht <= "1000000010"; wait for OP_DELAY;
Verwacht <= "1111110110"; wait for OP_DELAY;
Verwacht <= "1000000000"; wait for OP_DELAY;
Verwacht <= "0000011000"; wait for OP_DELAY;
Verwacht <= "0000000100"; wait for OP_DELAY;
Verwacht <= "0000011000"; wait for OP_DELAY;
Verwacht <= "1000000100"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "1000100010"; wait for OP_DELAY;
Verwacht <= "1000100000"; wait for OP_DELAY;
Verwacht <= "0111100010"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000100000"; wait for OP_DELAY;
Verwacht <= "1000000010"; wait for OP_DELAY;
Verwacht <= "1111100010"; wait for OP_DELAY;
Verwacht <= "1000000000"; wait for OP_DELAY;
Verwacht <= "0001000000"; wait for OP_DELAY;
Verwacht <= "0000010000"; wait for OP_DELAY;
Verwacht <= "0001000000"; wait for OP_DELAY;
Verwacht <= "0000010000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "1000111110"; wait for OP_DELAY;
Verwacht <= "1000111100"; wait for OP_DELAY;
Verwacht <= "0111000110"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000111100"; wait for OP_DELAY;
Verwacht <= "1000000010"; wait for OP_DELAY;
Verwacht <= "1111000110"; wait for OP_DELAY;
Verwacht <= "1000000000"; wait for OP_DELAY;
Verwacht <= "0001111000"; wait for OP_DELAY;
Verwacht <= "0000011100"; wait for OP_DELAY;
Verwacht <= "0001111000"; wait for OP_DELAY;
Verwacht <= "1000011100"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0000000011"; wait for OP_DELAY;
Verwacht <= "0000000001"; wait for OP_DELAY;
Verwacht <= "0000000001"; wait for OP_DELAY;
Verwacht <= "---------1"; wait for OP_DELAY;
Verwacht <= "1000000011"; wait for OP_DELAY;
Verwacht <= "1000000011"; wait for OP_DELAY;
Verwacht <= "1000000001"; wait for OP_DELAY;
Verwacht <= "1000000001"; wait for OP_DELAY;
Verwacht <= "0000000011"; wait for OP_DELAY;
Verwacht <= "0100000001"; wait for OP_DELAY;
Verwacht <= "0000000111"; wait for OP_DELAY;
Verwacht <= "0100000001"; wait for OP_DELAY;
Verwacht <= "---------1"; wait for OP_DELAY;
Verwacht <= "---------1"; wait for OP_DELAY;
Verwacht <= "0000000001"; wait for OP_DELAY;
Verwacht <= "1111111111"; wait for OP_DELAY;
Verwacht <= "0111100010"; wait for OP_DELAY;
Verwacht <= "0111100000"; wait for OP_DELAY;
Verwacht <= "1000100010"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "1111100010"; wait for OP_DELAY;
Verwacht <= "1000000010"; wait for OP_DELAY;
Verwacht <= "0000100000"; wait for OP_DELAY;
Verwacht <= "1000000000"; wait for OP_DELAY;
Verwacht <= "1111000010"; wait for OP_DELAY;
Verwacht <= "0111110000"; wait for OP_DELAY;
Verwacht <= "1111000110"; wait for OP_DELAY;
Verwacht <= "0111110000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0111111110"; wait for OP_DELAY;
Verwacht <= "0111111100"; wait for OP_DELAY;
Verwacht <= "1000000110"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "1000000010"; wait for OP_DELAY;
Verwacht <= "0000000100"; wait for OP_DELAY;
Verwacht <= "1000000000"; wait for OP_DELAY;
Verwacht <= "1111111010"; wait for OP_DELAY;
Verwacht <= "0111111100"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "1111111100"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "1111100010"; wait for OP_DELAY;
Verwacht <= "0000100000"; wait for OP_DELAY;
Verwacht <= "1111100010"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111100010"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0000100000"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "1111100110"; wait for OP_DELAY;
Verwacht <= "0000100100"; wait for OP_DELAY;
Verwacht <= "1111011110"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000100"; wait for OP_DELAY;
Verwacht <= "1111100010"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0000100000"; wait for OP_DELAY;
Verwacht <= "0000001000"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0000001000"; wait for OP_DELAY;
Verwacht <= "1000000000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "1111101110"; wait for OP_DELAY;
Verwacht <= "0000101100"; wait for OP_DELAY;
Verwacht <= "1111010110"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000001100"; wait for OP_DELAY;
Verwacht <= "1111100010"; wait for OP_DELAY;
Verwacht <= "1111110110"; wait for OP_DELAY;
Verwacht <= "0000100000"; wait for OP_DELAY;
Verwacht <= "0000011000"; wait for OP_DELAY;
Verwacht <= "0000000100"; wait for OP_DELAY;
Verwacht <= "0000011000"; wait for OP_DELAY;
Verwacht <= "1000000100"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0001000000"; wait for OP_DELAY;
Verwacht <= "1111000010"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000100000"; wait for OP_DELAY;
Verwacht <= "1111100010"; wait for OP_DELAY;
Verwacht <= "1111100010"; wait for OP_DELAY;
Verwacht <= "0000100000"; wait for OP_DELAY;
Verwacht <= "0001000000"; wait for OP_DELAY;
Verwacht <= "0000010000"; wait for OP_DELAY;
Verwacht <= "0001000000"; wait for OP_DELAY;
Verwacht <= "0000010000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0000011100"; wait for OP_DELAY;
Verwacht <= "0001011100"; wait for OP_DELAY;
Verwacht <= "1110100110"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000111100"; wait for OP_DELAY;
Verwacht <= "1111100010"; wait for OP_DELAY;
Verwacht <= "1111000110"; wait for OP_DELAY;
Verwacht <= "0000100000"; wait for OP_DELAY;
Verwacht <= "0001111000"; wait for OP_DELAY;
Verwacht <= "0000011100"; wait for OP_DELAY;
Verwacht <= "0001111000"; wait for OP_DELAY;
Verwacht <= "1000011100"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0111100010"; wait for OP_DELAY;
Verwacht <= "1000100010"; wait for OP_DELAY;
Verwacht <= "0111100000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "1000000010"; wait for OP_DELAY;
Verwacht <= "1111100010"; wait for OP_DELAY;
Verwacht <= "1000000000"; wait for OP_DELAY;
Verwacht <= "0000100000"; wait for OP_DELAY;
Verwacht <= "0000000010"; wait for OP_DELAY;
Verwacht <= "0100000000"; wait for OP_DELAY;
Verwacht <= "0000000110"; wait for OP_DELAY;
Verwacht <= "0100000000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "1111000011"; wait for OP_DELAY;
Verwacht <= "0000000001"; wait for OP_DELAY;
Verwacht <= "0000000001"; wait for OP_DELAY;
Verwacht <= "---------1"; wait for OP_DELAY;
Verwacht <= "1111100011"; wait for OP_DELAY;
Verwacht <= "1111100011"; wait for OP_DELAY;
Verwacht <= "0000100001"; wait for OP_DELAY;
Verwacht <= "0000100001"; wait for OP_DELAY;
Verwacht <= "1111000011"; wait for OP_DELAY;
Verwacht <= "0111110001"; wait for OP_DELAY;
Verwacht <= "1111000111"; wait for OP_DELAY;
Verwacht <= "0111110001"; wait for OP_DELAY;
Verwacht <= "---------1"; wait for OP_DELAY;
Verwacht <= "---------1"; wait for OP_DELAY;
Verwacht <= "0000000001"; wait for OP_DELAY;
Verwacht <= "1111111111"; wait for OP_DELAY;
Verwacht <= "1111011110"; wait for OP_DELAY;
Verwacht <= "0000011100"; wait for OP_DELAY;
Verwacht <= "1111100110"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "1111100010"; wait for OP_DELAY;
Verwacht <= "0000000100"; wait for OP_DELAY;
Verwacht <= "0000100000"; wait for OP_DELAY;
Verwacht <= "1111111010"; wait for OP_DELAY;
Verwacht <= "0111111100"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "1111111100"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0000000100"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0000000100"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0000001000"; wait for OP_DELAY;
Verwacht <= "1111111010"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000100"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0000000100"; wait for OP_DELAY;
Verwacht <= "0000001000"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "0000001000"; wait for OP_DELAY;
Verwacht <= "1000000000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0000001000"; wait for OP_DELAY;
Verwacht <= "0000010000"; wait for OP_DELAY;
Verwacht <= "1111110010"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000001100"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "1111110110"; wait for OP_DELAY;
Verwacht <= "0000000100"; wait for OP_DELAY;
Verwacht <= "0000011000"; wait for OP_DELAY;
Verwacht <= "0000000100"; wait for OP_DELAY;
Verwacht <= "0000011000"; wait for OP_DELAY;
Verwacht <= "1000000100"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0000011100"; wait for OP_DELAY;
Verwacht <= "0000100100"; wait for OP_DELAY;
Verwacht <= "1111011110"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000100000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "1111100010"; wait for OP_DELAY;
Verwacht <= "0000000100"; wait for OP_DELAY;
Verwacht <= "0001000000"; wait for OP_DELAY;
Verwacht <= "0000010000"; wait for OP_DELAY;
Verwacht <= "0001000000"; wait for OP_DELAY;
Verwacht <= "0000010000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0000111000"; wait for OP_DELAY;
Verwacht <= "0001000000"; wait for OP_DELAY;
Verwacht <= "1111000010"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000111100"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "1111000110"; wait for OP_DELAY;
Verwacht <= "0000000100"; wait for OP_DELAY;
Verwacht <= "0001111000"; wait for OP_DELAY;
Verwacht <= "0000011100"; wait for OP_DELAY;
Verwacht <= "0001111000"; wait for OP_DELAY;
Verwacht <= "1000011100"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0111111110"; wait for OP_DELAY;
Verwacht <= "1000000110"; wait for OP_DELAY;
Verwacht <= "0111111100"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "1000000010"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "1000000000"; wait for OP_DELAY;
Verwacht <= "0000000100"; wait for OP_DELAY;
Verwacht <= "0000000010"; wait for OP_DELAY;
Verwacht <= "0100000000"; wait for OP_DELAY;
Verwacht <= "0000000110"; wait for OP_DELAY;
Verwacht <= "0100000000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "1111011110"; wait for OP_DELAY;
Verwacht <= "1111100110"; wait for OP_DELAY;
Verwacht <= "0000011100"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "1111100010"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "0000100000"; wait for OP_DELAY;
Verwacht <= "0000000100"; wait for OP_DELAY;
Verwacht <= "1111000010"; wait for OP_DELAY;
Verwacht <= "0111110000"; wait for OP_DELAY;
Verwacht <= "1111000110"; wait for OP_DELAY;
Verwacht <= "0111110000"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "---------0"; wait for OP_DELAY;
Verwacht <= "0000000000"; wait for OP_DELAY;
Verwacht <= "1111111110"; wait for OP_DELAY;
Verwacht <= "1111111011"; wait for OP_DELAY;
Verwacht <= "0000000001"; wait for OP_DELAY;
Verwacht <= "0000000001"; wait for OP_DELAY;
Verwacht <= "---------1"; wait for OP_DELAY;
Verwacht <= "1111111111"; wait for OP_DELAY;
Verwacht <= "1111111111"; wait for OP_DELAY;
Verwacht <= "0000000101"; wait for OP_DELAY;
Verwacht <= "0000000101"; wait for OP_DELAY;
Verwacht <= "1111111011"; wait for OP_DELAY;
Verwacht <= "0111111101"; wait for OP_DELAY;
Verwacht <= "1111111111"; wait for OP_DELAY;
Verwacht <= "1111111101"; wait for OP_DELAY;
Verwacht <= "---------1"; wait for OP_DELAY;
Verwacht <= "---------1"; wait for OP_DELAY;
Verwacht <= "0000000001"; wait for OP_DELAY;
Verwacht <= "1111111111"; wait for OP_DELAY;
wait;
end process Expected;
-- Dit process controleert of de verwachte resultaten
-- overeenstemmen met die uit de VHDL file.
-- Bij verwachte don't care waarde ('_') wordt de uitgang van de
-- VHDL file gegegeerd.
Controle : process
begin
wait for OP_DELAY - 1 NS;
for I in 1 to NUM_TOT_VECTORS loop
-- Hieronder staat de controle van uitgang F
if ( Verwacht(1 to 8) /= DONT_CARE ) and ( F /= Verwacht(1 to 8) ) then
F_OK <= FALSE;
F_fout_teller <= F_fout_teller + 1;
end if;
-- Hieronder staat de controle Carry out
if ( Verwacht(9) /= '-' ) and ( Cout /= Verwacht(9) ) then
Cout_OK <= FALSE;
Cout_fout_teller <= Cout_fout_teller + 1;
end if;
-- Hieronder staat de controle equal uitgang
if ( Verwacht(10) /= '-' ) and ( Equal /= Verwacht(10) ) then
Equal_OK <= FALSE;
Equal_fout_teller <= Equal_fout_teller + 1;
end if;
wait for OP_DELAY;
end loop;
wait;
end process Controle;
end architecture Bench;
|
mit
|
chebykinn/university
|
circuitry/lab4/shift_engine.vhd
|
2
|
5523
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity shift_engine is
generic (
-- Width of parallel data
width : natural := 8;
-- Delay after NSEL is pulled low, in ticks of clk_i
delay : natural := 2
);
port (
-- Clocking
clk_i : in std_logic;
rst_i : in std_logic;
-- Data
dat_i : in std_logic_vector((width - 1) downto 0);
dat_o : out std_logic_vector((width - 1) downto 0);
-- Control Signals
cpol_i : in std_logic; -- SPI Clock Polarity
cpha_i : in std_logic; -- SPI Clock Phase
div_i : in natural range 2 to width; -- SPI Clock Divider, relative to clk_i
cnt_i : in integer range 1 to (width - 1); -- Number of Bits to Shift
start_i : in std_logic;
done_o : out std_logic;
-- Shift Signals
sclk_o : out std_logic;
mosi_o : out std_logic;
miso_i : in std_logic
);
end shift_engine;
architecture Behavioral of shift_engine is
type shift_state_t is (
idle, enable, shift, hold, disable
);
signal state : shift_state_t;
signal miso : std_logic;
signal mosi : std_logic;
signal reg_rx : std_logic_vector((width - 1) downto 0);
signal reg_tx : std_logic_vector((width - 1) downto 0);
signal tx_load : std_logic;
signal shl : std_logic;
signal delay_cnt : integer range 0 to (delay - 1);
signal shift_cnt : integer range 0 to ((2 * width) - 1);
signal spi_delay : integer range 0 to ((2 ** width) - 1);
signal spi_cnt : integer range 0 to ((delay / 2) - 1);
signal spi_cnt_ld : std_logic;
signal spi_clk : std_logic;
signal spi_edge : std_logic;
signal spi_nedge : std_logic;
signal spi_clk_en : std_logic;
begin
spi_delay <= div_i / 2;
rx_sr : process (clk_i)
begin
if (rising_edge(clk_i)) then
miso <= miso_i;
if (shl = '1') then
reg_rx <= reg_rx((reg_rx'high - 1) downto 0) & miso;
end if;
end if;
end process rx_sr;
dat_o <= reg_rx;
tx_sr : process (clk_i)
begin
if (rising_edge(clk_i)) then
if (tx_load = '1') then
reg_tx <= dat_i;
end if;
if (shl = '1') then
reg_tx <= reg_tx((reg_rx'high - 1) downto 0) & '-';
end if;
mosi <= reg_tx(reg_tx'high);
end if;
end process tx_sr;
mosi_o <= mosi;
counter : process (clk_i)
begin
if (rising_edge(clk_i)) then
if (spi_cnt_ld = '1') then
spi_cnt <= spi_delay;
elsif (spi_clk_en = '1') then
spi_cnt <= spi_cnt - 1;
end if;
end if;
end process;
clkgen : process (clk_i)
begin
if (rising_edge(clk_i)) then
spi_edge <= '0';
spi_nedge <= '0';
shl <= '0';
spi_cnt_ld <= '0';
if (spi_clk_en = '1') then
if (spi_cnt = 0) then
spi_cnt_ld <= '1';
if (spi_clk = cpol_i) then
spi_edge <= '1';
if (cpha_i = '1') then
shl <= '1';
end if;
else
spi_nedge <= '1';
if (cpha_i = '0') then
shl <= '1';
end if;
end if;
spi_clk <= not spi_clk;
end if;
else
spi_clk <= cpol_i;
end if;
end if;
end process;
sclk_o <= spi_clk;
fsm : process
begin
wait until rising_edge(clk_i);
case state is
when idle =>
if (start_i = '1') then
done_o <= '0';
tx_load <= '1';
delay_cnt <= delay - 1;
state <= enable;
else
spi_clk_en <= '0';
done_o <= '1';
end if;
when enable =>
tx_load <= '0';
if (delay_cnt = 0) then
shift_cnt <= cnt_i;
spi_clk_en <= '1';
state <= shift;
else
delay_cnt <= delay_cnt - 1;
end if;
when shift =>
if (spi_edge = '1') then
if (shift_cnt = 0) then
state <= hold;
else
shift_cnt <= shift_cnt - 1;
end if;
end if;
when hold =>
if (spi_nedge = '1') then
spi_clk_en <= '0';
delay_cnt <= delay - 1;
state <= disable;
end if;
when disable =>
if (delay_cnt = 0) then
state <= idle;
else
delay_cnt <= delay_cnt - 1;
end if;
end case;
if (rst_i = '1') then
done_o <= '0';
spi_clk_en <= '0';
state <= idle;
end if;
end process fsm;
end Behavioral;
|
mit
|
chebykinn/university
|
circuitry/lab4/src/hdl/wb/wb.vhd
|
2
|
5373
|
-- Generated by PERL program wishbone.pl. Do not edit this file.
--
-- For defines see wishbone.defines
--
-- Generated Sun Oct 18 18:30:29 2015
--
-- Wishbone masters:
-- mips_wbm
--
-- Wishbone slaves:
-- ram_wbs
-- baseadr 0x00000000 - size 0x00000400
-- wbs
-- baseadr 0x00000400 - size 0x00000400
-----------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package intercon_package is
function "and" (
l : std_logic_vector;
r : std_logic)
return std_logic_vector;
end intercon_package;
package body intercon_package is
function "and" (
l : std_logic_vector;
r : std_logic)
return std_logic_vector is
variable result : std_logic_vector(l'range);
begin -- "and"
for i in l'range loop
result(i) := l(i) and r;
end loop; -- i
return result;
end "and";
end intercon_package;
library IEEE;
use IEEE.std_logic_1164.all;
use work.intercon_package.all;
entity intercon is
port (
-- wishbone master port(s)
-- mips_wbm
mips_wbm_dat_i : out std_logic_vector(31 downto 0);
mips_wbm_ack_i : out std_logic;
mips_wbm_dat_o : in std_logic_vector(31 downto 0);
mips_wbm_we_o : in std_logic;
mips_wbm_sel_o : in std_logic_vector(3 downto 0);
mips_wbm_adr_o : in std_logic_vector(31 downto 0);
mips_wbm_cyc_o : in std_logic;
mips_wbm_stb_o : in std_logic;
-- wishbone slave port(s)
-- ram_wbs
ram_wbs_dat_o : in std_logic_vector(31 downto 0);
ram_wbs_ack_o : in std_logic;
ram_wbs_dat_i : out std_logic_vector(31 downto 0);
ram_wbs_we_i : out std_logic;
ram_wbs_sel_i : out std_logic_vector(3 downto 0);
ram_wbs_adr_i : out std_logic_vector(31 downto 0);
ram_wbs_cyc_i : out std_logic;
ram_wbs_stb_i : out std_logic;
-- wbs1
wbs1_dat_o : in std_logic_vector(31 downto 0);
wbs1_ack_o : in std_logic;
wbs1_dat_i : out std_logic_vector(31 downto 0);
wbs1_we_i : out std_logic;
wbs1_sel_i : out std_logic_vector(3 downto 0);
wbs1_adr_i : out std_logic_vector(31 downto 0);
wbs1_cyc_i : out std_logic;
wbs1_stb_i : out std_logic;
-- wbs2
wbs2_dat_o : in std_logic_vector(31 downto 0);
wbs2_ack_o : in std_logic;
wbs2_dat_i : out std_logic_vector(31 downto 0);
wbs2_we_i : out std_logic;
wbs2_sel_i : out std_logic_vector(3 downto 0);
wbs2_adr_i : out std_logic_vector(31 downto 0);
wbs2_cyc_i : out std_logic;
wbs2_stb_i : out std_logic;
-- clock and reset
clk : in std_logic;
reset : in std_logic);
end intercon;
architecture rtl of intercon is
signal ram_wbs_ss : std_logic; -- slave select
signal wbs1_ss : std_logic; -- slave select
signal wbs2_ss : std_logic; -- slave select
begin -- rtl
decoder:block
signal adr : std_logic_vector(31 downto 0);
begin
adr <= (mips_wbm_adr_o);
ram_wbs_ss <= '1' when adr(31 downto 10)="0000000000000000000000" else '0';
wbs1_ss <= '1' when adr(31 downto 10)="0000000000000000000001" else '0';
wbs2_ss <= '1' when adr(31 downto 10)="0000000000000000000010" else '0';
ram_wbs_adr_i <= adr(31 downto 0);
wbs1_adr_i <= adr(31 downto 0);
wbs2_adr_i <= adr(31 downto 0);
end block decoder;
mux: block
signal cyc, stb, we, ack : std_logic;
signal sel : std_logic_vector(3 downto 0);
signal dat_m2s, dat_s2m : std_logic_vector(31 downto 0);
begin
cyc <= (mips_wbm_cyc_o);
ram_wbs_cyc_i <= ram_wbs_ss and cyc;
wbs1_cyc_i <= wbs1_ss and cyc;
wbs2_cyc_i <= wbs2_ss and cyc;
stb <= (mips_wbm_stb_o);
ram_wbs_stb_i <= stb;
wbs1_stb_i <= stb;
wbs2_stb_i <= stb;
we <= (mips_wbm_we_o);
ram_wbs_we_i <= we;
wbs1_we_i <= we;
wbs2_we_i <= we;
ack <= ram_wbs_ack_o or wbs1_ack_o or wbs2_ack_o;
mips_wbm_ack_i <= ack;
sel <= (mips_wbm_sel_o);
ram_wbs_sel_i <= sel;
wbs1_sel_i <= sel;
wbs2_sel_i <= sel;
dat_m2s <= (mips_wbm_dat_o);
ram_wbs_dat_i <= dat_m2s;
wbs1_dat_i <= dat_m2s;
wbs2_dat_i <= dat_m2s;
dat_s2m <= (ram_wbs_dat_o and ram_wbs_ss) or
(wbs1_dat_o and wbs1_ss) or
(wbs2_dat_o and wbs2_ss);
mips_wbm_dat_i <= dat_s2m;
end block mux;
end rtl;
|
mit
|
chebykinn/university
|
circuitry/lab3/src/hdl/wb/wb.vhd
|
2
|
5373
|
-- Generated by PERL program wishbone.pl. Do not edit this file.
--
-- For defines see wishbone.defines
--
-- Generated Sun Oct 18 18:30:29 2015
--
-- Wishbone masters:
-- mips_wbm
--
-- Wishbone slaves:
-- ram_wbs
-- baseadr 0x00000000 - size 0x00000400
-- wbs
-- baseadr 0x00000400 - size 0x00000400
-----------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package intercon_package is
function "and" (
l : std_logic_vector;
r : std_logic)
return std_logic_vector;
end intercon_package;
package body intercon_package is
function "and" (
l : std_logic_vector;
r : std_logic)
return std_logic_vector is
variable result : std_logic_vector(l'range);
begin -- "and"
for i in l'range loop
result(i) := l(i) and r;
end loop; -- i
return result;
end "and";
end intercon_package;
library IEEE;
use IEEE.std_logic_1164.all;
use work.intercon_package.all;
entity intercon is
port (
-- wishbone master port(s)
-- mips_wbm
mips_wbm_dat_i : out std_logic_vector(31 downto 0);
mips_wbm_ack_i : out std_logic;
mips_wbm_dat_o : in std_logic_vector(31 downto 0);
mips_wbm_we_o : in std_logic;
mips_wbm_sel_o : in std_logic_vector(3 downto 0);
mips_wbm_adr_o : in std_logic_vector(31 downto 0);
mips_wbm_cyc_o : in std_logic;
mips_wbm_stb_o : in std_logic;
-- wishbone slave port(s)
-- ram_wbs
ram_wbs_dat_o : in std_logic_vector(31 downto 0);
ram_wbs_ack_o : in std_logic;
ram_wbs_dat_i : out std_logic_vector(31 downto 0);
ram_wbs_we_i : out std_logic;
ram_wbs_sel_i : out std_logic_vector(3 downto 0);
ram_wbs_adr_i : out std_logic_vector(31 downto 0);
ram_wbs_cyc_i : out std_logic;
ram_wbs_stb_i : out std_logic;
-- wbs1
wbs1_dat_o : in std_logic_vector(31 downto 0);
wbs1_ack_o : in std_logic;
wbs1_dat_i : out std_logic_vector(31 downto 0);
wbs1_we_i : out std_logic;
wbs1_sel_i : out std_logic_vector(3 downto 0);
wbs1_adr_i : out std_logic_vector(31 downto 0);
wbs1_cyc_i : out std_logic;
wbs1_stb_i : out std_logic;
-- wbs2
wbs2_dat_o : in std_logic_vector(31 downto 0);
wbs2_ack_o : in std_logic;
wbs2_dat_i : out std_logic_vector(31 downto 0);
wbs2_we_i : out std_logic;
wbs2_sel_i : out std_logic_vector(3 downto 0);
wbs2_adr_i : out std_logic_vector(31 downto 0);
wbs2_cyc_i : out std_logic;
wbs2_stb_i : out std_logic;
-- clock and reset
clk : in std_logic;
reset : in std_logic);
end intercon;
architecture rtl of intercon is
signal ram_wbs_ss : std_logic; -- slave select
signal wbs1_ss : std_logic; -- slave select
signal wbs2_ss : std_logic; -- slave select
begin -- rtl
decoder:block
signal adr : std_logic_vector(31 downto 0);
begin
adr <= (mips_wbm_adr_o);
ram_wbs_ss <= '1' when adr(31 downto 10)="0000000000000000000000" else '0';
wbs1_ss <= '1' when adr(31 downto 10)="0000000000000000000001" else '0';
wbs2_ss <= '1' when adr(31 downto 10)="0000000000000000000010" else '0';
ram_wbs_adr_i <= adr(31 downto 0);
wbs1_adr_i <= adr(31 downto 0);
wbs2_adr_i <= adr(31 downto 0);
end block decoder;
mux: block
signal cyc, stb, we, ack : std_logic;
signal sel : std_logic_vector(3 downto 0);
signal dat_m2s, dat_s2m : std_logic_vector(31 downto 0);
begin
cyc <= (mips_wbm_cyc_o);
ram_wbs_cyc_i <= ram_wbs_ss and cyc;
wbs1_cyc_i <= wbs1_ss and cyc;
wbs2_cyc_i <= wbs2_ss and cyc;
stb <= (mips_wbm_stb_o);
ram_wbs_stb_i <= stb;
wbs1_stb_i <= stb;
wbs2_stb_i <= stb;
we <= (mips_wbm_we_o);
ram_wbs_we_i <= we;
wbs1_we_i <= we;
wbs2_we_i <= we;
ack <= ram_wbs_ack_o or wbs1_ack_o or wbs2_ack_o;
mips_wbm_ack_i <= ack;
sel <= (mips_wbm_sel_o);
ram_wbs_sel_i <= sel;
wbs1_sel_i <= sel;
wbs2_sel_i <= sel;
dat_m2s <= (mips_wbm_dat_o);
ram_wbs_dat_i <= dat_m2s;
wbs1_dat_i <= dat_m2s;
wbs2_dat_i <= dat_m2s;
dat_s2m <= (ram_wbs_dat_o and ram_wbs_ss) or
(wbs1_dat_o and wbs1_ss) or
(wbs2_dat_o and wbs2_ss);
mips_wbm_dat_i <= dat_s2m;
end block mux;
end rtl;
|
mit
|
zerokill/vhdl-course
|
exercise_2/opdr4.vhd
|
1
|
1228
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ALU is
port( A, B : in std_logic_vector(7 downto 0);
Code : in std_logic_vector(3 downto 0);
F : out std_logic_vector(7 downto 0);
Cout : out Std_logic;
Equal : out Std_logic);
end ALU;
architecture RTL of ALU is
signal INT : signed(8 downto 0);
signal sA, sB: signed(8 downto 0);
begin
sA <= resize(signed(A),sA'length);
sB <= resize(signed(B),sB'length);
process(sA,sB,code)
begin
case code is
when "0000" => INT <= sA + sB;
when "0001" => INT <= sA - sB;
when "0010" => INT <= sB - sA;
when "0100" => INT <= sA;
when "0101" => INT <= sB;
when "0110" => INT <= -sA;
when "0111" => INT <= -sB;
when "1000" => INT <= sA(7 downto 0) & '0';
when "1001" => INT <= "00" & sA(7 downto 1);
when "1010" => INT <= sA(7 downto 0) & sA(7);
when "1011" => INT <= '0' & sA(0) & sA(7 downto 1);
when "1110" => INT <= (others => '0');
when "1111" => INT <= (others => '1');
when others => INT <= INT;
end case;
end process;
process(sA,sB)
begin
if (sA = sB) then equal <= '1';
else equal <= '0';
end if;
end process;
F <= std_logic_vector(INT(7 downto 0));
Cout <= INT(8);
end RTL;
|
mit
|
bargei/NoC264
|
NoC264_3x3/noc_interface.vhd
|
1
|
6989
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
entity noc_interface is
generic(
data_width : integer := 64;
addr_width : integer := 1;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8;
use_vc : integer := 0
);
port(
--clk, reset
clk : in std_logic;
rst : in std_logic;
--user sending interface
send_data : in std_logic_vector(data_width-1 downto 0);
dest_addr : in std_logic_vector(addr_width-1 downto 0);
set_tail_flit : in std_logic;
send_flit : in std_logic;
ready_to_send : out std_logic;
--user receiving interface
recv_data : out std_logic_vector(data_width-1 downto 0);
src_addr : out std_logic_vector(addr_width-1 downto 0);
is_tail_flit : out std_logic;
data_in_buffer : out std_logic_vector(num_vc-1 downto 0);
dequeue : in std_logic_vector(num_vc-1 downto 0);
select_vc_read : in std_logic_vector(vc_sel_width-1 downto 0);
--interface to network
send_putFlit_flit_in : out std_logic_vector(data_width+addr_width+vc_sel_width+1 downto 0);
EN_send_putFlit : out std_logic;
EN_send_getNonFullVCs : out std_logic;
send_getNonFullVCs : in std_logic_vector(num_vc-1 downto 0);
EN_recv_getFlit : out std_logic;
recv_getFlit : in std_logic_vector(data_width+addr_width+vc_sel_width+1 downto 0);
recv_putNonFullVCs_nonFullVCs : out std_logic_vector(num_vc-1 downto 0);
EN_recv_putNonFullVCs : out std_logic;
recv_info_getRecvPortID : in std_logic_vector(addr_width-1 downto 0)
);
end entity noc_interface;
architecture structural of noc_interface is
--fifo buffer for reciving
component fifo_buffer is
generic(
word_len : integer := 64;
buff_len : integer := 8
);
port(
write_data : in std_logic_vector(word_len-1 downto 0);
read_data : out std_logic_vector(word_len-1 downto 0);
buffer_full : out std_logic;
buffer_empty : out std_logic;
enqueue : in std_logic;
dequeue : in std_logic;
clk : in std_logic;
rst : in std_logic
);
end component fifo_buffer;
type fifo_io is array(num_vc-1 downto 0) of std_logic_vector(vc_sel_width+data_width+addr_width+1 downto 0);
signal write_vc, read_vc: fifo_io;
signal buffer_full_vc, buffer_empty_vc, enqueue_vc, dequeue_vc: std_logic_vector(num_vc-1 downto 0);
signal receive_vc: std_logic_vector(vc_sel_width-1 downto 0);
-- priority encoder
component priority_encoder is
generic(
encoded_word_size : integer := 3
);
Port(
input : in std_logic_vector(2**encoded_word_size-1 downto 0);
output : out std_logic_vector(encoded_word_size-1 downto 0)
);
end component priority_encoder;
signal selected_vc : std_logic_vector(vc_sel_width-1 downto 0);
--constants to parse flits
constant data_msb : integer := data_width-1;
constant data_lsb : integer := 0;
constant vc_msb : integer := vc_sel_width+data_width-1;
constant vc_lsb : integer := data_width;
constant addr_msb : integer := vc_sel_width+data_width+addr_width-1;
constant addr_lsb : integer := vc_sel_width+data_width;
constant is_tail_index : integer := vc_sel_width+data_width+addr_width;
constant is_valid_index : integer := vc_sel_width+data_width+addr_width+1;
constant flit_size : integer := vc_sel_width+data_width+addr_width+2;
begin
---------------------------------------------------------------------------
--RECEIVE SIDE ------------------------------------------------------------
---------------------------------------------------------------------------
-- create and map 1 buffer for each VC
receive_buffer: for i in num_vc-1 downto 0 generate
signal vc_select : integer;
signal flit_valid : std_logic;
begin
ur_i: fifo_buffer generic map(data_width+addr_width+vc_sel_width+2, flit_buff_depth)
port map(write_vc(i), read_vc(i), buffer_full_vc(i), buffer_empty_vc(i),
enqueue_vc(i), dequeue_vc(i), clk, rst);
vc_select <= to_integer(unsigned(recv_getFlit(vc_msb downto vc_lsb)));
flit_valid <= recv_getFlit(is_valid_index);
write_vc(i) <= recv_getFlit when i = vc_select else std_logic_vector(to_unsigned(0,flit_size));
enqueue_vc(i) <= flit_valid when i = vc_select else '0';
end generate;
-- IO for receive side of controller
EN_recv_getFlit <= '1'; -- always read to receive flits as long as buffers aren't full
recv_putNonFullVCs_nonFullVCs <= not buffer_full_vc;
data_in_buffer <= not buffer_empty_vc;
recv_data <= read_vc(to_integer(unsigned(select_vc_read)))(data_msb downto data_lsb);
dequeue_vc <= dequeue;
is_tail_flit <= read_vc(to_integer(unsigned(select_vc_read)))(is_tail_index);
src_addr <= read_vc(to_integer(unsigned(select_vc_read)))(addr_msb downto addr_lsb);
EN_recv_putNonFullVCs <= '1'; -- readme is not clear about what this does, assuming it is not need for peek flow control
---------------------------------------------------------------------------
--SEND SIDE ---------------------------------------------------------------
---------------------------------------------------------------------------
-------- priority encoder to determine which vc to use
------us_0: priority_encoder generic map(vc_sel_width)
------ port map(send_getNonFullVCs, selected_vc);
------
------
-------- IO for sending side of controller
------send_putFlit_flit_in <= send_flit & set_tail_flit & dest_addr & selected_vc & send_data;
--------ready_to_send <= '0' when to_integer(unsigned(send_getNonFullVCs)) = 0 else '1';
--------ready_to_send <= or_reduce(send_getNonFullVCs);
------EN_send_putFlit <= send_flit;
------EN_send_getNonFullVCs <= '1'; --always read to recieve credits
------
------
-- temp version which only sends on a selected vc
-- priority encoder to determine which vc to use
selected_vc <= std_logic_vector(to_unsigned(use_vc, vc_sel_width));
-- IO for sending side of controller
send_putFlit_flit_in <= send_flit & set_tail_flit & dest_addr & selected_vc & send_data;
ready_to_send <= send_getNonFullVCs(use_vc);
EN_send_putFlit <= send_flit;
EN_send_getNonFullVCs <= '1'; --always read to recieve credits
end architecture structural;
|
mit
|
boztalay/OldProjects
|
FPGA/LCD_Control/TestCPU1_RegFile_TB.vhd
|
1
|
4262
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:08:51 10/04/2009
-- Design Name:
-- Module Name: C:/Users/Ben/Desktop/Folders/FPGA/Projects/Current Projects/Systems/TestCPU1/TestCPU1_RegFile_TB.vhd
-- Project Name: TestCPU1
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: TestCPU1_RegFile
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY TestCPU1_RegFile_TB IS
END TestCPU1_RegFile_TB;
ARCHITECTURE behavior OF TestCPU1_RegFile_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT TestCPU1_RegFile
PORT(
clock : IN std_logic;
reset : IN std_logic;
ld_val : IN std_logic;
ALUB_out : IN std_logic;
src1_addr : IN std_logic_vector(2 downto 0);
src2_addr : IN std_logic_vector(2 downto 0);
dest_addr : IN std_logic_vector(2 downto 0);
data_to_load : IN std_logic_vector(15 downto 0);
to_ALUA_out : OUT std_logic_vector(15 downto 0);
to_ALUB_out : OUT std_logic_vector(15 downto 0);
data_collection_1 : out STD_LOGIC_VECTOR(15 downto 0); --for simulation purposes only
data_collection_2 : out STD_LOGIC_VECTOR(15 downto 0); --
data_collection_3 : out STD_LOGIC_VECTOR(15 downto 0)); --
END COMPONENT;
--Inputs
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal ld_val : std_logic := '0';
signal ALUB_out : std_logic := '0';
signal src1_addr : std_logic_vector(2 downto 0) := (others => '0');
signal src2_addr : std_logic_vector(2 downto 0) := (others => '0');
signal dest_addr : std_logic_vector(2 downto 0) := (others => '0');
signal data_to_load : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal to_ALUA_out : std_logic_vector(15 downto 0);
signal to_ALUB_out : std_logic_vector(15 downto 0);
signal data_collection_1 : STD_LOGIC_VECTOR(15 downto 0); --for simulation purposes only
signal data_collection_2 : STD_LOGIC_VECTOR(15 downto 0); --
signal data_collection_3 : STD_LOGIC_VECTOR(15 downto 0); --
-- Clock period definitions
constant clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: TestCPU1_RegFile PORT MAP (
clock => clock,
reset => reset,
ld_val => ld_val,
ALUB_out => ALUB_out,
src1_addr => src1_addr,
src2_addr => src2_addr,
dest_addr => dest_addr,
data_to_load => data_to_load,
to_ALUA_out => to_ALUA_out,
to_ALUB_out => to_ALUB_out,
data_collection_1 => data_collection_1,
data_collection_2 => data_collection_2,
data_collection_3 => data_collection_3
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for 15 ns;
ld_val <= '1';
dest_addr <= b"001";
data_to_load <= x"0001";
wait for 10 ns;
dest_addr <= b"010";
data_to_load <= x"0002";
wait for 10 ns;
dest_addr <= b"011";
data_to_load <= x"0003";
wait for 10 ns;
ld_val <= '0';
ALUB_out <= '1';
src1_addr <= b"001";
wait for 10 ns;
src1_addr <= b"010";
src2_addr <= b"011";
wait for 10 ns;
ALUB_out <= '0';
wait for 10 ns;
reset <= '1';
wait;
end process;
END;
|
mit
|
bargei/NoC264
|
NoC264_3x3/network_interface_latched_vc.vhd
|
1
|
7360
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
entity network_interface is
generic(
data_width : integer := 64;
addr_width : integer := 1;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
port(
--clk, reset
clk : in std_logic;
rst : in std_logic;
--user sending interface
send_data : in std_logic_vector(data_width-1 downto 0);
dest_addr : in std_logic_vector(addr_width-1 downto 0);
set_tail_flit : in std_logic;
send_flit : in std_logic;
ready_to_send : out std_logic;
--user receiving interface
recv_data : out std_logic_vector(data_width-1 downto 0);
src_addr : out std_logic_vector(addr_width-1 downto 0);
is_tail_flit : out std_logic;
data_in_buffer : out std_logic_vector(num_vc-1 downto 0);
dequeue : in std_logic_vector(num_vc-1 downto 0);
select_vc_read : in std_logic_vector(vc_sel_width-1 downto 0);
--interface to network
send_putFlit_flit_in : out std_logic_vector(data_width+addr_width+vc_sel_width+1 downto 0);
EN_send_putFlit : out std_logic;
EN_send_getNonFullVCs : out std_logic;
send_getNonFullVCs : in std_logic_vector(num_vc-1 downto 0);
EN_recv_getFlit : out std_logic;
recv_getFlit : in std_logic_vector(data_width+addr_width+vc_sel_width+1 downto 0);
recv_putNonFullVCs_nonFullVCs : out std_logic_vector(num_vc-1 downto 0);
EN_recv_putNonFullVCs : out std_logic;
recv_info_getRecvPortID : in std_logic_vector(addr_width-1 downto 0)
);
end entity network_interface;
architecture structural of network_interface is
--fifo buffer for reciving
component fifo_buffer is
generic(
word_len : integer := 64;
buff_len : integer := 8
);
port(
write_data : in std_logic_vector(word_len-1 downto 0);
read_data : out std_logic_vector(word_len-1 downto 0);
buffer_full : out std_logic;
buffer_empty : out std_logic;
enqueue : in std_logic;
dequeue : in std_logic;
clk : in std_logic;
rst : in std_logic
);
end component fifo_buffer;
type fifo_io is array(num_vc-1 downto 0) of std_logic_vector(vc_sel_width+data_width+addr_width+1 downto 0);
signal write_vc, read_vc: fifo_io;
signal buffer_full_vc, buffer_empty_vc, enqueue_vc, dequeue_vc: std_logic_vector(num_vc-1 downto 0);
signal receive_vc: std_logic_vector(vc_sel_width-1 downto 0);
-- priority encoder
component priority_encoder is
generic(
encoded_word_size : integer := 3
);
Port(
input : in std_logic_vector(2**encoded_word_size-1 downto 0);
output : out std_logic_vector(encoded_word_size-1 downto 0)
);
end component priority_encoder;
signal selected_vc_d : std_logic_vector(vc_sel_width-1 downto 0);
signal selected_vc_q : std_logic_vector(vc_sel_width-1 downto 0);
signal selected_vc_enc : std_logic_vector(vc_sel_width-1 downto 0);
type ni_states is (idle, sending);
signal state, next_state : ni_states;
--constants to parse flits
constant data_msb : integer := data_width-1;
constant data_lsb : integer := 0;
constant vc_msb : integer := vc_sel_width+data_width-1;
constant vc_lsb : integer := data_width;
constant addr_msb : integer := vc_sel_width+data_width+addr_width-1;
constant addr_lsb : integer := vc_sel_width+data_width;
constant is_tail_index : integer := vc_sel_width+data_width+addr_width;
constant is_valid_index : integer := vc_sel_width+data_width+addr_width+1;
constant flit_size : integer := vc_sel_width+data_width+addr_width+2;
begin
---------------------------------------------------------------------------
--RECEIVE SIDE ------------------------------------------------------------
---------------------------------------------------------------------------
-- create and map 1 buffer for each VC
receive_buffer: for i in num_vc-1 downto 0 generate
signal vc_select : integer;
signal flit_valid : std_logic;
begin
ur_i: fifo_buffer generic map(data_width+addr_width+vc_sel_width+2, flit_buff_depth)
port map(write_vc(i), read_vc(i), buffer_full_vc(i), buffer_empty_vc(i),
enqueue_vc(i), dequeue_vc(i), clk, rst);
vc_select <= to_integer(unsigned(recv_getFlit(vc_msb downto vc_lsb)));
flit_valid <= recv_getFlit(is_valid_index);
write_vc(i) <= recv_getFlit when i = vc_select else std_logic_vector(to_unsigned(0,flit_size));
enqueue_vc(i) <= flit_valid when i = vc_select else '0';
end generate;
-- IO for receive side of controller
EN_recv_getFlit <= '1'; -- always read to receive flits as long as buffers aren't full
recv_putNonFullVCs_nonFullVCs <= not buffer_full_vc;
data_in_buffer <= not buffer_empty_vc;
recv_data <= read_vc(to_integer(unsigned(select_vc_read)))(data_msb downto data_lsb);
dequeue_vc <= dequeue;
is_tail_flit <= read_vc(to_integer(unsigned(select_vc_read)))(is_tail_index);
src_addr <= read_vc(to_integer(unsigned(select_vc_read)))(addr_msb downto addr_lsb);
EN_recv_putNonFullVCs <= '1'; -- readme is not clear about what this does, assuming it is not need for peek flow control
---------------------------------------------------------------------------
--SEND SIDE ---------------------------------------------------------------
---------------------------------------------------------------------------
-- priority encoder to determine which vc to use
us_0: priority_encoder generic map(vc_sel_width)
port map(send_getNonFullVCs, selected_vc_enc);
process(clk, rst)
begin
if rst = '1' then
selected_vc_q <= (others => '0');
state <= idle;
elsif rising_edge(clk) then
selected_vc_q <= selected_vc_d;
state <= next_state;
end if;
end process;
selected_vc_d <= selected_vc_enc when state = idle else
selected_vc_q;
process(state, send_flit, set_tail_flit)
begin
next_state <= state;
if state = idle and send_flit = '1' then
next_state <= sending;
end if;
if state = sending and set_tail_flit = '1' then
next_state <= idle;
end if;
end process;
-- IO for sending side of controller
send_putFlit_flit_in <= send_flit & set_tail_flit & dest_addr & selected_vc_q & send_data;
ready_to_send <= or_reduce(send_getNonFullVCs) when state = idle else
send_getNonFullVCs(0) when state = sending and selected_vc_q = "01" else
send_getNonFullVCs(1) when state = sending and selected_vc_q = "10";
EN_send_putFlit <= send_flit;
EN_send_getNonFullVCs <= '1'; --always read to recieve credits
end architecture structural;
|
mit
|
boztalay/OldProjects
|
FPGA/Current Projects/Subsystems/OZ-3/OZ-3.vhd
|
2
|
853
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:52:50 10/26/2009
-- Design Name:
-- Module Name: OZ-3 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity OZ-3 is
end OZ-3;
architecture Behavioral of OZ-3 is
begin
end Behavioral;
|
mit
|
boztalay/OldProjects
|
FPGA/Components/Comp_7segDecoder/Comp_7segDecoder.vhd
|
1
|
1704
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 02:59:14 04/10/2009
-- Design Name:
-- Module Name: Comp_7segDecoder - Behavioral
-- Project Name: Seven segment display decoder
-- Target Devices:
-- Tool versions:
-- Description: Takes in a 4-bit binary number and outputs it to a seven-segment display in hexadecimal
--
-- Dependencies: None
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Comp_7segDecoder is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
seg : out STD_LOGIC_VECTOR (6 downto 0));
end Comp_7segDecoder;
architecture Behavioral of Comp_7segDecoder is
begin
with A select
seg <= "0000001" when "0000",
"1001111" when "0001",
"0010010" when "0010",
"0000110" when "0011",
"1001100" when "0100",
"0100100" when "0101",
"0100000" when "0110",
"0001111" when "0111",
"0000000" when "1000",
"0000100" when "1001",
"0001000" when "1010",
"1100000" when "1011",
"0110001" when "1100",
"1000010" when "1101",
"0110000" when "1110",
"0111000" when "1111",
"0000001" when others;
end Behavioral;
|
mit
|
boztalay/OldProjects
|
FPGA/Sys_SecondTimer/Comp_DataMUX4x4.vhd
|
1
|
1733
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 15:51:47 07/30/2009
-- Design Name:
-- Module Name: Comp_DataMUX - Behavioral
-- Project Name: Data Multiplexer
-- Target Devices:
-- Tool versions:
-- Description: A multiplexer that multiplexes inputs with two or more bits each.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.10 - First draft written
-- Revision 0.15 - Syntax errors fixed
-- Revision 0.30 - UCF file written
-- Revision 1.00 - Generated programming file with successul hardware test
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Comp_DataMUX4x4 is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
C : in STD_LOGIC_VECTOR (3 downto 0);
D : in STD_LOGIC_VECTOR (3 downto 0);
sel : in STD_LOGIC_VECTOR (1 downto 0);
output : out STD_LOGIC_VECTOR (3 downto 0));
end Comp_DataMUX4x4;
architecture Behavioral of Comp_DataMUX4x4 is
begin
main : process(A, B, C, D, sel) is
begin
case sel is
when b"00" =>
output <= A;
when b"01" =>
output <= B;
when b"10" =>
output <= C;
when b"11" =>
output <= D;
when others =>
output <= b"0000";
end case;
end process main;
end Behavioral;
|
mit
|
bargei/NoC264
|
NoC264_3x3/fifo_buffer.vhd
|
2
|
1830
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fifo_buffer is
generic(
word_len : integer := 64;
buff_len : integer := 8
);
port(
write_data : in std_logic_vector(word_len-1 downto 0);
read_data : out std_logic_vector(word_len-1 downto 0);
buffer_full : out std_logic;
buffer_empty : out std_logic;
enqueue : in std_logic;
dequeue : in std_logic;
clk : in std_logic;
rst : in std_logic
);
end entity fifo_buffer;
architecture behavioral of fifo_buffer is
signal enqueue_pointer : integer;
type buffer_type is array(buff_len-1 downto 0) of std_logic_vector(word_len-1 downto 0);
signal the_buffer : buffer_type;
signal buffer_full_sig : std_logic;
signal buffer_empty_sig : std_logic;
begin
--read/write to buffer
process(clk, rst)
begin
if rst = '1' then
enqueue_pointer <= 0;
the_buffer <= (others => (others => '0'));
elsif rising_edge(clk) then
if enqueue = '1' and buffer_full_sig = '0' then
the_buffer(enqueue_pointer) <= write_data;
enqueue_pointer <= enqueue_pointer + 1;
end if;
if dequeue = '1' and buffer_empty_sig = '0' then
enqueue_pointer <= enqueue_pointer - 1;
the_buffer(buff_len-2 downto 0) <= the_buffer(buff_len-1 downto 1);
end if;
end if;
end process;
--output logic
read_data <= the_buffer(0);
buffer_full_sig <= '0' when enqueue_pointer < buff_len else '1';
buffer_empty_sig <= '0' when enqueue_pointer > 0 else '1';
buffer_full <= buffer_full_sig;
buffer_empty <= buffer_empty_sig;
end architecture behavioral;
|
mit
|
boztalay/OldProjects
|
FPGA/LCD_Control/TestCPU1_dRAM.vhd
|
1
|
1776
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 01:27:41 10/03/2009
-- Design Name:
-- Module Name: TestCPU1_dRAM - Behavioral
-- Project Name: Test CPU 1
-- Target Devices:
-- Tool versions:
-- Description: The data RAM for Test CPU 1
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TestCPU1_dRAM is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
write_e : in STD_LOGIC;
read_e : in STD_LOGIC;
addr : in STD_LOGIC_VECTOR(7 downto 0);
data_in : in STD_LOGIC_VECTOR(15 downto 0);
data_out : out STD_LOGIC_VECTOR(15 downto 0));
end TestCPU1_dRAM;
architecture Behavioral of TestCPU1_dRAM is
begin
dRAM: process (clock, reset, read_e) is
type dRAM_array is array (255 downto 0) of
STD_LOGIC_VECTOR(15 downto 0);
variable dRAM: dRAM_array := (others => b"0000000000000000");
begin
if falling_edge(clock) then
if reset = '1' then
dRAM := (others => b"0000000000000000");
elsif write_e = '1' then
dRAM(conv_integer(unsigned(addr))) := data_in;
end if;
end if;
if read_e = '0' then
data_out <= x"0000";
else
data_out <= dRAM(conv_integer(unsigned(addr)));
end if;
end process;
end Behavioral;
|
mit
|
boztalay/OldProjects
|
FPGA/Components/Comp_16bitShiftReg/Comp_16bitShiftReg/Comp_16bitShiftReg.vhd
|
1
|
2295
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 15:07:41 06/08/2009
-- Design Name:
-- Module Name: Comp_16bitShiftReg - Behavioral
-- Project Name: 16-Bit Shift Register
-- Target Devices:
-- Tool versions:
-- Description: A 16-bit shift register, no reset, activates on the falling edge
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity Comp_16bitShiftReg is
Port ( CLK : in STD_LOGIC;
Data : in STD_LOGIC;
Parallel : out STD_LOGIC_VECTOR (15 downto 0);
Carry : out STD_LOGIC);
end Comp_16bitShiftReg;
architecture Behavioral of Comp_16bitShiftReg is
--\Signals/--
signal Buf_CLK : STD_LOGIC;
signal Buf_Data : STD_LOGIC;
--/Signals\--
begin
--\BUFG Instantiations/--
BUFG_BufCLK : BUFG
port map (
O => Buf_CLK,
I => CLK
);
BUFG_BufData : BUFG
port map (
O => Buf_Data,
I => Data
);
--/BUFG Instantiations\--
main : process(Buf_CLK, Buf_Data)
variable storage : STD_LOGIC_VECTOR(15 downto 0) := "0000000000000000";
variable storage2 : STD_LOGIC_VECTOR(15 downto 0) := "0000000000000000";
begin
if (Buf_CLK'event and Buf_CLK = '0') then
storage2(0) := Buf_Data;
storage2(1) := storage(0);
storage2(2) := storage(1);
storage2(3) := storage(2);
storage2(4) := storage(3);
storage2(5) := storage(4);
storage2(6) := storage(5);
storage2(7) := storage(6);
storage2(8) := storage(7);
storage2(9) := storage(8);
storage2(10) := storage(9);
storage2(11) := storage(10);
storage2(12) := storage(11);
storage2(13) := storage(12);
storage2(14) := storage(13);
storage2(15) := storage(14);
Carry <= storage(15);
storage := storage2;
Parallel <= storage;
end if;
end process;
end Behavioral;
|
mit
|
bargei/NoC264
|
NoC264_2x2/iqit_node.vhd
|
1
|
16706
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use ieee.math_real.all;
entity iqit_node is
generic(
sample_width : integer := 8;
qp_width : integer := 8;
wo_dc_width : integer := 8;
data_width : integer := 64;
addr_width : integer := 1;
vc_sel_width : integer := 1;
num_vc : integer := 2;
flit_buff_depth : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
-- recv interface to network
recv_data : in std_logic_vector(data_width-1 downto 0);
src_addr : in std_logic_vector(addr_width-1 downto 0);
is_tail_flit : in std_logic;
data_in_buffer : in std_logic_vector(num_vc-1 downto 0);
dequeue : out std_logic_vector(num_vc-1 downto 0);
select_vc_read : out std_logic_vector(vc_sel_width-1 downto 0);
-- send interface to network
send_data : out std_logic_vector(data_width-1 downto 0);
dest_addr : out std_logic_vector(addr_width-1 downto 0);
set_tail_flit : out std_logic;
send_flit : out std_logic;
ready_to_send : in std_logic--;
----debug
-- state_out : out std_logic_vector(7 downto 0);
-- input_sample_0 : out std_logic_vector(7 downto 0);
-- input_sample_1 : out std_logic_vector(7 downto 0);
-- input_sample_2 : out std_logic_vector(7 downto 0);
-- input_sample_3 : out std_logic_vector(7 downto 0);
-- input_sample_4 : out std_logic_vector(7 downto 0);
-- input_sample_5 : out std_logic_vector(7 downto 0);
-- input_sample_6 : out std_logic_vector(7 downto 0);
-- input_sample_7 : out std_logic_vector(7 downto 0);
-- input_sample_8 : out std_logic_vector(7 downto 0);
-- input_sample_9 : out std_logic_vector(7 downto 0);
-- input_sample_A : out std_logic_vector(7 downto 0);
-- input_sample_B : out std_logic_vector(7 downto 0);
-- input_sample_C : out std_logic_vector(7 downto 0);
-- input_sample_D : out std_logic_vector(7 downto 0);
-- input_sample_E : out std_logic_vector(7 downto 0);
-- input_sample_F : out std_logic_vector(7 downto 0);
-- qp_out : out std_logic_vector(7 downto 0);
-- zigzag_0 : out std_logic_vector(7 downto 0);
-- zigzag_1 : out std_logic_vector(7 downto 0);
-- zigzag_2 : out std_logic_vector(7 downto 0);
-- zigzag_3 : out std_logic_vector(7 downto 0);
-- zigzag_4 : out std_logic_vector(7 downto 0);
-- zigzag_5 : out std_logic_vector(7 downto 0);
-- zigzag_6 : out std_logic_vector(7 downto 0);
-- zigzag_7 : out std_logic_vector(7 downto 0);
-- zigzag_8 : out std_logic_vector(7 downto 0);
-- zigzag_9 : out std_logic_vector(7 downto 0);
-- zigzag_A : out std_logic_vector(7 downto 0);
-- zigzag_B : out std_logic_vector(7 downto 0);
-- zigzag_C : out std_logic_vector(7 downto 0);
-- zigzag_D : out std_logic_vector(7 downto 0);
-- zigzag_E : out std_logic_vector(7 downto 0);
-- zigzag_F : out std_logic_vector(7 downto 0);
-- dequant_0 : out std_logic_vector(15 downto 0);
-- dequant_1 : out std_logic_vector(15 downto 0);
-- dequant_2 : out std_logic_vector(15 downto 0);
-- dequant_3 : out std_logic_vector(15 downto 0);
-- dequant_4 : out std_logic_vector(15 downto 0);
-- dequant_5 : out std_logic_vector(15 downto 0);
-- dequant_6 : out std_logic_vector(15 downto 0);
-- dequant_7 : out std_logic_vector(15 downto 0);
-- dequant_8 : out std_logic_vector(15 downto 0);
-- dequant_9 : out std_logic_vector(15 downto 0);
-- dequant_A : out std_logic_vector(15 downto 0);
-- dequant_B : out std_logic_vector(15 downto 0);
-- dequant_C : out std_logic_vector(15 downto 0);
-- dequant_D : out std_logic_vector(15 downto 0);
-- dequant_E : out std_logic_vector(15 downto 0);
-- dequant_F : out std_logic_vector(15 downto 0);
-- result_0 : out std_logic_vector(7 downto 0);
-- result_1 : out std_logic_vector(7 downto 0);
-- result_2 : out std_logic_vector(7 downto 0);
-- result_3 : out std_logic_vector(7 downto 0);
-- result_4 : out std_logic_vector(7 downto 0);
-- result_5 : out std_logic_vector(7 downto 0);
-- result_6 : out std_logic_vector(7 downto 0);
-- result_7 : out std_logic_vector(7 downto 0);
-- result_8 : out std_logic_vector(7 downto 0);
-- result_9 : out std_logic_vector(7 downto 0);
-- result_A : out std_logic_vector(7 downto 0);
-- result_B : out std_logic_vector(7 downto 0);
-- result_C : out std_logic_vector(7 downto 0);
-- result_D : out std_logic_vector(7 downto 0);
-- result_E : out std_logic_vector(7 downto 0);
-- result_F : out std_logic_vector(7 downto 0)
);
end entity iqit_node;
architecture fsmd of iqit_node is
--- COMPONENTS ------------------------------------------------------------
component zigzag is
generic(
sample_width : integer := 8
);
port(
x : in std_logic_vector((16*sample_width)-1 downto 0);
y : out std_logic_vector((16*sample_width)-1 downto 0)
);
end component zigzag;
component inverse_quant is
generic(
in_sample_width : integer := 8;
out_sample_width : integer := 16;
qp_width : integer := 8;
wo_dc_width : integer := 8
);
port(
quantized_samples : in std_logic_vector((16*in_sample_width)-1 downto 0);
quant_param : in std_logic_vector(qp_width-1 downto 0);
without_dc : in std_logic_vector(wo_dc_width-1 downto 0);
dequant_samples : out std_logic_vector((16*out_sample_width)-1 downto 0)
);
end component inverse_quant;
component inverse_transform is
generic(
in_sample_width : integer := 16;
out_sample_width : integer := 8
);
port(
transform_block : in std_logic_vector((16*in_sample_width)-1 downto 0);
inv_transform_block : out std_logic_vector((16*out_sample_width)-1 downto 0);
sign_mask : out std_logic_vector(15 downto 0)
);
end component inverse_transform;
component priority_encoder is
generic(
encoded_word_size : integer := 3
);
Port(
input : in std_logic_vector(2**encoded_word_size-1 downto 0);
output : out std_logic_vector(encoded_word_size-1 downto 0)
);
end component priority_encoder;
--- TYPES -----------------------------------------------------------------
type iqit_states is (idle,
sel_vc,
rx_header,
dequeue_header,
wait_row_4_3,
rx_row_4_3,
dequeue_row_4_3,
wait_row_2_1,
rx_row_2_1,
dequeue_row_2_1,
wait_tx_header,
tx_header,
wait_tx_row_4_3,
tx_row_4_3,
wait_tx_row_2_1,
tx_row_2_1
);
--- SIGNALS ---------------------------------------------------------------
signal state : iqit_states;
signal next_state : iqit_states;
signal quant_param_d : std_logic_vector(qp_width-1 downto 0);
signal quant_param_q : std_logic_vector(qp_width-1 downto 0);
signal without_dc_d : std_logic_vector(wo_dc_width-1 downto 0);
signal without_dc_q : std_logic_vector(wo_dc_width-1 downto 0);
signal identifier_d : std_logic_vector(7 downto 0);
signal identifier_q : std_logic_vector(7 downto 0);
signal input_samples_d : std_logic_vector((16*sample_width)-1 downto 0);
signal input_samples_q : std_logic_vector((16*sample_width)-1 downto 0);
signal samples_after_zigzag : std_logic_vector((16*sample_width)-1 downto 0);
signal samples_after_inv_q : std_logic_vector((16*2*sample_width)-1 downto 0);
signal inv_t_input : std_logic_vector((16*2*sample_width)-1 downto 0);
signal result_samples : std_logic_vector((16*sample_width)-1 downto 0);
signal tx_header_data : std_logic_vector(data_width-1 downto 0);
signal tx_row_4_3_data : std_logic_vector(data_width-1 downto 0);
signal tx_row_2_1_data : std_logic_vector(data_width-1 downto 0);
signal sel_vc_d : std_logic_vector(vc_sel_width-1 downto 0);
signal sel_vc_q : std_logic_vector(vc_sel_width-1 downto 0);
signal sel_vc_enc : std_logic_vector(vc_sel_width-1 downto 0);
signal sel_vc_one_hot : std_logic_vector(num_vc-1 downto 0);
signal dc_high_byte_q : std_logic_vector(7 downto 0);
signal dc_high_byte_d : std_logic_vector(7 downto 0);
signal sign_mask : std_logic_vector(15 downto 0);
signal x_pass_thru_d : std_logic_vector(10 downto 0);
signal y_pass_thru_d : std_logic_vector(10 downto 0);
signal LCbCr_pass_thru_d : std_logic_vector(1 downto 0);
signal x_pass_thru_q : std_logic_vector(10 downto 0);
signal y_pass_thru_q : std_logic_vector(10 downto 0);
signal LCbCr_pass_thru_q : std_logic_vector(1 downto 0);
constant do_iqit_cmd : std_logic_vector(7 downto 0) := x"03";
begin
--- DATAPATH --------------------------------------------------------------
u0: component zigzag
generic map(
sample_width => sample_width
)
port map(
x => input_samples_q,
y => samples_after_zigzag
);
u1: component inverse_quant
generic map(
in_sample_width => sample_width,
out_sample_width => 2*sample_width,
qp_width => qp_width,
wo_dc_width => wo_dc_width
)
port map(
quantized_samples => samples_after_zigzag,
quant_param => quant_param_q,
without_dc => without_dc_q,
dequant_samples => samples_after_inv_q
);
u2: component inverse_transform
generic map(
in_sample_width => 2*sample_width,
out_sample_width => sample_width
)
port map(
transform_block => inv_t_input,
inv_transform_block => result_samples,
sign_mask => sign_mask
);
u3: component priority_encoder
generic map(
encoded_word_size => vc_sel_width
)
Port map(
input => data_in_buffer,
output => sel_vc_enc
);
--register process
process(clk, rst) begin
if rst = '1' then
state <= idle;
quant_param_q <= (others => '0');
without_dc_q <= (others => '0');
identifier_q <= (others => '0');
input_samples_q <= (others => '0');
sel_vc_q <= (others => '0');
dc_high_byte_q <= (others => '0');
x_pass_thru_q <= (others => '0');
y_pass_thru_q <= (others => '0');
LCbCr_pass_thru_q <= (others => '0');
elsif rising_edge(clk) then
state <= next_state;
quant_param_q <= quant_param_d;
without_dc_q <= without_dc_d;
identifier_q <= identifier_d;
input_samples_q <= input_samples_d;
sel_vc_q <= sel_vc_d;
dc_high_byte_q <= dc_high_byte_d;
x_pass_thru_q <= x_pass_thru_d;
y_pass_thru_q <= y_pass_thru_d;
LCbCr_pass_thru_q <= LCbCr_pass_thru_d;
end if;
end process;
--insert high byte of dc into signal if non-zero
inv_t_input <= samples_after_inv_q(16*2*sample_width-1 downto sample_width*2) & dc_high_byte_q & samples_after_inv_q(sample_width-1 downto 0) when or_reduce(dc_high_byte_q) = '1' else
samples_after_inv_q;
--parse packet
quant_param_d <= recv_data(47 downto 40) when state = rx_header else quant_param_q;
without_dc_d <= recv_data(39 downto 32) when state = rx_header else without_dc_q;
identifier_d <= recv_data(7 downto 0) when state = rx_header else identifier_q;
dc_high_byte_d <= recv_data(55 downto 48) when state = rx_header else dc_high_byte_q;
x_pass_thru_d <= recv_data(18 downto 8) when state = rx_header else x_pass_thru_q;
y_pass_thru_d <= recv_data(29 downto 19) when state = rx_header else y_pass_thru_q;
LCbCr_pass_thru_d <= recv_data(31 downto 30) when state = rx_header else LCbCr_pass_thru_q;
input_samples_d((16*sample_width)-1 downto (8*sample_width)) <= recv_data when state = rx_row_4_3 else
input_samples_q((16*sample_width)-1 downto (8*sample_width));
input_samples_d((8*sample_width)-1 downto 0) <= recv_data when state = rx_row_2_1 else
input_samples_q((8*sample_width)-1 downto 0);
-- format repsonse packet
tx_header_data <= x_pass_thru_q & "00000" &sign_mask& "000" & LCbCr_pass_thru_q & y_pass_thru_q &do_iqit_cmd&identifier_q;
tx_row_4_3_data <= result_samples((16*sample_width)-1 downto (8*sample_width));
tx_row_2_1_data <= result_samples((8*sample_width)-1 downto 0) ;
-- channel selection logic
sel_vc_d <= sel_vc_enc when state = sel_vc else sel_vc_q;
--rx controls
dequeue <= sel_vc_one_hot when state = dequeue_header or state = dequeue_row_4_3 or state = dequeue_row_2_1 else "00";
select_vc_read <= sel_vc_q;
sel_vc_one_hot <= "01" when sel_vc_q = "0" else "10";
--packet generation
send_data <= tx_header_data when state = wait_tx_header or state = tx_header else
tx_row_4_3_data when state = wait_tx_row_4_3 or state = tx_row_4_3 else
tx_row_2_1_data when state = wait_tx_row_2_1 or state = tx_row_2_1 else
std_logic_vector(to_unsigned(0, data_width));
dest_addr <= std_logic_vector(to_unsigned(7, addr_width));
set_tail_flit <= '1' when state = wait_row_2_1 or state = tx_row_2_1 else '0';
send_flit <= '1' when state = tx_header or state = tx_row_4_3 or state = tx_row_2_1 else '0';
-- STATE MACHINE ----------------------------------------------------------
process(state, data_in_buffer, is_tail_flit, sel_vc_one_hot, ready_to_send)
begin
next_state <= state; --default behaviour
if state = idle and or_reduce(data_in_buffer) = '1' then
next_state <= sel_vc;
end if;
if state = sel_vc then
next_state <= rx_header;
end if;
if state = rx_header then
next_state <= dequeue_header;
end if;
if state = dequeue_header then
next_state <= wait_row_4_3;
end if;
if state = wait_row_4_3 and or_reduce(sel_vc_one_hot and data_in_buffer) = '1' then
next_state <= rx_row_4_3;
end if;
if state = rx_row_4_3 then
next_state <= dequeue_row_4_3;
end if;
if state = dequeue_row_4_3 then
next_state <= wait_row_2_1;
end if;
if state = wait_row_2_1 and or_reduce(sel_vc_one_hot and data_in_buffer) = '1' then
next_state <= rx_row_2_1;
end if;
if state = rx_row_2_1 then
next_state <= dequeue_row_2_1;
end if;
if state = dequeue_row_2_1 then
next_state <= wait_tx_header;
end if;
if state = wait_tx_header and ready_to_send = '1' then
next_state <= tx_header;
end if;
if state = tx_header then
next_state <= wait_tx_row_4_3;
end if;
if state = wait_tx_row_4_3 and ready_to_send = '1' then
next_state <= tx_row_4_3;
end if;
if state = tx_row_4_3 then
next_state <= wait_tx_row_2_1;
end if;
if state = wait_tx_row_2_1 and ready_to_send = '1' then
next_state <= tx_row_2_1;
end if;
if state = tx_row_2_1 then
next_state <= idle;
end if;
end process;
end architecture fsmd;
|
mit
|
boztalay/OldProjects
|
FPGA/Current Projects/Subsystems/OZ-3/IpinReg.vhd
|
3
|
865
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:02:28 10/26/2009
-- Design Name:
-- Module Name: IpinReg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity IpinReg is
end IpinReg;
architecture Behavioral of IpinReg is
begin
end Behavioral;
|
mit
|
boztalay/OldProjects
|
FPGA/Components/Comp_FrequencyDivider/Comp_FrequencyDivider.vhd
|
1
|
1772
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Ben Oztalay
--
-- Create Date: 22:15:19 04/10/2009
-- Design Name:
-- Module Name: Comp_DivideBy50Mil - Behavioral
-- Project Name: Frequency Divider
-- Target Devices:
-- Tool versions:
-- Description: A frequency divider for use by a digital clock. Takes the Nexys 2 50Mhz clock
-- and produces a 1Hz clock and 500Hz clock.
-- Dependencies: None
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Comp_FrequencyDivider is
Port ( SysCLK : in STD_LOGIC;
out1 : out STD_LOGIC;
out2 : out STD_LOGIC);
end Comp_FrequencyDivider;
architecture Behavioral of Comp_FrequencyDivider is
signal cntr : STD_LOGIC_VECTOR (25 downto 0);
signal cntr2 : STD_LOGIC_VECTOR (16 downto 0);
begin
process (SysCLK)
begin
if SysCLK'event and SysCLK = '0' then
cntr <= cntr + 1;
if cntr = "01011111010111100001000000" then
out1 <= '1';
end if;
if cntr = "10111110101111000010000000" then
out1 <= '0';
cntr <= "00000000000000000000000000";
end if;
end if;
if SysCLK'event and SysCLK = '0' then
cntr2 <= cntr2 + 1;
if cntr2 = "01100001101010000" then
out2 <= '1';
end if;
if cntr2 = "11000011010100000" then
out2 <= '0';
cntr2 <= "00000000000000000";
end if;
end if;
end process;
end Behavioral;
|
mit
|
bargei/NoC264
|
NoC264_2x2/h264_deblock_filter_core.vhd
|
2
|
9247
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity h264_deblock_filter_core is
port(
clk : in std_logic;
rst : in std_logic;
is_chroma : in std_logic;
boundary_strength : in signed(8 downto 0);
p0 : in signed(8 downto 0);
p1 : in signed(8 downto 0);
p2 : in signed(8 downto 0);
p3 : in signed(8 downto 0);
q0 : in signed(8 downto 0);
q1 : in signed(8 downto 0);
q2 : in signed(8 downto 0);
q3 : in signed(8 downto 0);
alpha : in signed(8 downto 0);
beta : in signed(8 downto 0);
tc0 : in signed(8 downto 0);
p0_out : out signed(8 downto 0);
p1_out : out signed(8 downto 0);
p2_out : out signed(8 downto 0);
q0_out : out signed(8 downto 0);
q1_out : out signed(8 downto 0);
q2_out : out signed(8 downto 0)
);
end entity h264_deblock_filter_core;
architecture rtl of h264_deblock_filter_core is
signal normal_filter : boolean;
signal strong_filter : boolean;
signal ap, aq : boolean;
signal strong_filter_test : boolean;
signal basic_checks : boolean; -- and of three test always needed
signal extra_filter_normal_p : boolean;
signal extra_filter_normal_q : boolean;
signal p0_if_normal_filtd : signed(15 downto 0);
signal p1_if_normal_filtd : signed(15 downto 0);
signal q0_if_normal_filtd : signed(15 downto 0);
signal q1_if_normal_filtd : signed(15 downto 0);
signal p0_if_strong_filtd_0 : signed(15 downto 0);
signal p1_if_strong_filtd_0 : signed(15 downto 0);
signal p2_if_strong_filtd_0 : signed(15 downto 0);
signal q0_if_strong_filtd_0 : signed(15 downto 0);
signal q1_if_strong_filtd_0 : signed(15 downto 0);
signal q2_if_strong_filtd_0 : signed(15 downto 0);
signal p0_if_strong_filtd_1 : signed(15 downto 0);
signal p1_if_strong_filtd_1 : signed(15 downto 0);
signal p2_if_strong_filtd_1 : signed(15 downto 0);
signal q0_if_strong_filtd_1 : signed(15 downto 0);
signal q1_if_strong_filtd_1 : signed(15 downto 0);
signal q2_if_strong_filtd_1 : signed(15 downto 0);
signal p0_if_strong_filtd : signed(15 downto 0);
signal p1_if_strong_filtd : signed(15 downto 0);
signal p2_if_strong_filtd : signed(15 downto 0);
signal q0_if_strong_filtd : signed(15 downto 0);
signal q1_if_strong_filtd : signed(15 downto 0);
signal q2_if_strong_filtd : signed(15 downto 0);
signal delta_pre_clip : signed(15 downto 0);
signal delta : signed(15 downto 0);
signal p1_pre_clip_component : signed(15 downto 0);
signal q1_pre_clip_component : signed(15 downto 0);
signal p1_post_clip_component : signed(15 downto 0);
signal q1_post_clip_component : signed(15 downto 0);
signal tc0_prime : signed(8 downto 0);
begin
-- normal filtering
basic_checks <= (abs(p0-q0) < alpha) and
(abs(p1-p0) < beta ) and
(abs(q1-q0) < beta );
extra_filter_normal_p <= abs(p2-p0) < beta;
extra_filter_normal_q <= abs(q2-q0) < beta;
tc0_prime <= tc0 when not (extra_filter_normal_p or extra_filter_normal_q) else
tc0 + to_signed(1, 9) when extra_filter_normal_p xor extra_filter_normal_q else
tc0 + to_signed(2, 9);
delta_pre_clip <= shift_right((shift_left((("0000000"&q0) - ("0000000"&p0)) , 2) +
(("0000000"&p1) - ("0000000"&q1)) + (to_signed(4, 16))) , 3);
delta <= delta_pre_clip when delta_pre_clip > -tc0_prime and delta_pre_clip < tc0_prime else
"1111111"&(-tc0_prime) when delta_pre_clip < -tc0_prime else
"0000000"&tc0_prime;
p1_pre_clip_component <= shift_right((("0000000"&p2) + shift_right((("0000000"&p0) + ("0000000"&q0) + to_signed(1, 16)) , 1) - shift_left(("0000000"&p1) , 1)) , 1);
p1_post_clip_component <= p1_pre_clip_component when p1_pre_clip_component > -tc0 and p1_pre_clip_component < tc0 else
"1111111"&(-tc0) when p1_pre_clip_component < -tc0 else
"0000000"&tc0;
q1_pre_clip_component <= shift_right((("0000000"&q2) + shift_right((("0000000"&p0) + ("0000000"&q0) + to_signed(1, 16)) , 1) - shift_left(("0000000"&q1) , 1)) , 1);
q1_post_clip_component <= q1_pre_clip_component when q1_pre_clip_component > -tc0 and q1_pre_clip_component < tc0 else
"1111111"&(-tc0) when q1_pre_clip_component < -tc0 else
"0000000"&tc0;
p0_if_normal_filtd <= ("0000000"&p0) + delta;
p1_if_normal_filtd <= ("0000000"&p1) + p1_post_clip_component;
q0_if_normal_filtd <= ("0000000"&q0) - delta;
q1_if_normal_filtd <= ("0000000"&q1) + q1_post_clip_component;
normal_filter <= boundary_strength < to_signed(4, 9) and boundary_strength > to_signed(0, 9);
--strong filtering
ap <= extra_filter_normal_p;
aq <= extra_filter_normal_q;
strong_filter <= boundary_strength = to_signed(4, 9);
strong_filter_test <= (abs((X"0"&p0) - (X"0"&q0)) < (shift_right(X"0"&alpha, 2) + to_signed(2, 13))) and (is_chroma = '0');
p0_if_strong_filtd_0 <= shift_right(( shift_left("0000000"&p1, 1) + ("0000000"&p0) + ("0000000"&q1) + to_signed(2, 16) ) , 2);
p1_if_strong_filtd_0 <= "0000000"&p1;
p2_if_strong_filtd_0 <= "0000000"&p2;
q0_if_strong_filtd_0 <= shift_right(( shift_left("0000000"&q1, 1) + ("0000000"&q0) + ("0000000"&p1) + to_signed(2, 16) ) , 2);
q1_if_strong_filtd_0 <= "0000000"&q1;
q2_if_strong_filtd_0 <= "0000000"&q2;
p0_if_strong_filtd_1 <= shift_right((("0000000"&p2) + shift_left("0000000"&p1, 1) + shift_left("0000000"&p0,1) + shift_left("0000000"&q0,1) + ("0000000"&q1) + to_signed(4, 16) ), 3);
p1_if_strong_filtd_1 <= shift_right(( ("0000000"&p2) + ("0000000"&p1) + ("0000000"&p0) + ("0000000"&q0) + to_signed(2, 16) ), 2);
p2_if_strong_filtd_1 <= shift_right((shift_left("0000000"&p3, 1) + (to_signed(3, 7)*p2) + ("0000000"&p1) + ("0000000"&p0) + ("0000000"&q0) + to_signed(4, 16) ) , 3);
q0_if_strong_filtd_1 <= shift_right((("0000000"&q2) + shift_left("0000000"&q1, 1) + shift_left("0000000"&q0,1) + shift_left("0000000"&p0,1) + ("0000000"&p1) + to_signed(4, 16) ), 3);
q1_if_strong_filtd_1 <= shift_right(( ("0000000"&q2) + ("0000000"&q1) + ("0000000"&q0) + ("0000000"&p0) + to_signed(2, 16) ), 2);
q2_if_strong_filtd_1 <= shift_right((shift_left("0000000"&q3, 1) + (to_signed(3, 7)*q2) + ("0000000"&q1) + ("0000000"&q0) + ("0000000"&p0) + to_signed(4, 16) ) , 3);
p0_if_strong_filtd <= p0_if_strong_filtd_1 when strong_filter_test else p0_if_strong_filtd_0;
p1_if_strong_filtd <= p1_if_strong_filtd_1 when strong_filter_test else p1_if_strong_filtd_0;
p2_if_strong_filtd <= p2_if_strong_filtd_1 when strong_filter_test else p2_if_strong_filtd_0;
q0_if_strong_filtd <= q0_if_strong_filtd_1 when strong_filter_test else q0_if_strong_filtd_0;
q1_if_strong_filtd <= q1_if_strong_filtd_1 when strong_filter_test else q1_if_strong_filtd_0;
q2_if_strong_filtd <= q2_if_strong_filtd_1 when strong_filter_test else q2_if_strong_filtd_0;
-- output (will need modifing once strong filtering is built)
p0_out <= p0_if_normal_filtd(8 downto 0) when normal_filter and basic_checks else
p0_if_strong_filtd(8 downto 0) when strong_filter and basic_checks else
p0;
p1_out <= p1_if_normal_filtd(8 downto 0) when normal_filter and basic_checks and extra_filter_normal_p else
p1_if_strong_filtd(8 downto 0) when strong_filter and basic_checks else
p1;
p2_out <= p2_if_strong_filtd(8 downto 0) when strong_filter and basic_checks else p2;
q0_out <= q0_if_normal_filtd(8 downto 0) when normal_filter and basic_checks else
q0_if_strong_filtd(8 downto 0) when strong_filter and basic_checks else
q0;
q1_out <= q1_if_normal_filtd(8 downto 0) when normal_filter and basic_checks and extra_filter_normal_q else
q1_if_strong_filtd(8 downto 0) when strong_filter and basic_checks else
q1;
q2_out <= q2_if_strong_filtd(8 downto 0) when strong_filter and basic_checks else q2;
end architecture rtl;
|
mit
|
boztalay/OldProjects
|
FPGA/Key_test/Keyboard.vhd
|
1
|
2610
|
----------------------------------------------------------------------------------
--Ben Oztalay, 2009-2010
--
--Module Title: Keyboard
--Module Description:
-- This is a simple module that eases the interface with a keyboard. It takes the
-- PS/2 bus clock and data pins as inputs, as well as an acknowledgment signal. The
-- outputs are the 8-bit scan code and a signal that tells the host device that
-- the scan code is ready. Every 11 clock cycles, when the entire packet has been sent,
-- the code_ready output is driven high, and stays high until the acknowledgement
-- input is raised to '1'. It doesn't take scan codes while the code_ready output
-- is high.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Keyboard is
Port ( key_clock : in STD_LOGIC;
key_data : in STD_LOGIC;
acknowledge : in STD_LOGIC;
scan_code : out STD_LOGIC_VECTOR (7 to 0);
code_ready : out STD_LOGIC);
end Keyboard;
architecture Behavioral of Keyboard is
--//Components\\--
component Gen_Shift_Reg_Falling is
generic (size : integer);
Port ( clock : in STD_LOGIC;
enable : in STD_LOGIC;
reset : in STD_LOGIC;
data_in : in STD_LOGIC;
data_out : out STD_LOGIC_VECTOR ((size-1) downto 0));
end component;
--\\Components//--
--//Signals\\--
signal code_ready_sig : STD_LOGIC;
signal enable : STD_LOGIC;
signal reg_out : STD_LOGIC_VECTOR(10 downto 0);
--\\Signals//--
begin
count_chk : process (key_clock, acknowledge, enable) is
variable count : integer := 0;
variable ready : STD_LOGIC := '0';
begin
if enable = '1' then
if falling_edge(key_clock) then
count := count + 1;
if count = 11 then
count := 0;
ready := '1';
end if;
end if;
end if;
if (ready = '1') and (acknowledge = '1') then
ready := '0';
end if;
code_ready_sig <= ready;
end process;
shift_reg : Gen_Shift_Reg_Falling generic map (size => 11)
port map (clock => key_clock,
enable => enable,
reset => '0',
data_in => key_data,
data_out => reg_out);
enable <= (not (key_clock and code_ready_sig));
code_ready <= code_ready_sig;
scan_code <= regout(2) & regout(3) & regout(4) & regout(5) & regout(6) & regout(7) & regout(8) & regout(9);
end Behavioral;
|
mit
|
c-lipka/linguist
|
samples/VHDL/foo.vhd
|
91
|
217
|
-- VHDL example file
library ieee;
use ieee.std_logic_1164.all;
entity inverter is
port(a : in std_logic;
b : out std_logic);
end entity;
architecture rtl of inverter is
begin
b <= not a;
end architecture;
|
mit
|
MikhailKoslowski/Variax
|
Quartus/FlashController.vhd
|
1
|
1112
|
-----------------------------------------------------------
-- Default Libs
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
-- My libs
-- USE work.my_functions.all
-----------------------------------------------------------
ENTITY FlashController IS
GENERIC( freq : NATURAL := 50_000_000 );
PORT ( clk : IN STD_LOGIC;
addr : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
rdy : OUT STD_LOGIC
);
END FlashController;
--------------------------------------------------------
ARCHITECTURE structure OF FlashController IS
SIGNAL s_addr : STD_LOGIC_VECTOR(18 DOWNTO 0);
SIGNAL s_data : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
PROCESS(clk)
VARIABLE count: NATURAL RANGE 0 TO freq := 0;
BEGIN
-- clk rising edge.
IF clk'EVENT AND clk='1' THEN
IF count = 0 THEN
s_addr <= addr;
ELSIF count = freq THEN
data <= s_data;
rdy <= '1';
ELSE
s_data <= s_addr(7 DOWNTO 0);
rdy <= '0';
END IF;
count := count + 1;
END IF;
END PROCESS;
END structure;
--------------------------------------------------------
|
mit
|
boztalay/OZ-4
|
OZ-4 FPGA/OZ4/mem_ctl.vhd
|
2
|
1224
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity memory_control is
port(clk : in std_logic;
rst : in std_logic;
address : in std_logic_vector(31 downto 0);
data_in : in std_logic_vector(31 downto 0);
data_out : out std_logic_vector(31 downto 0);
we : in std_logic;
mem_addr : out std_logic_vector(31 downto 0);
mem_write_data : out std_logic_vector(31 downto 0);
mem_read_data : in std_logic_vector(31 downto 0);
mem_we : out std_logic;
mem_clk : out std_logic
);
end memory_control;
architecture behavioral of memory_control is
signal addr_r, data_r : std_logic_vector(31 downto 0);
begin
--Not much to it, just here so it can be expanded later in need be
mem_clk <= clk;
mem_addr <= addr_r;
mem_write_data <= data_r;
data_out <= mem_read_data;
mem_we <= we;
latch : process (clk, rst) is
begin
if rst = '1' then
addr_r <= (others => '0');
data_r <= (others => '0');
elsif rising_edge(clk) then
addr_r <= address;
data_r <= data_in;
end if;
end process;
end behavioral;
|
mit
|
boztalay/OZ-4
|
OZ-4 FPGA/OZ4/ieee_proposed/fixed_pkg_c.vhd
|
3
|
291386
|
------------------------------------------------------------------------------
-- "fixed_pkg" package contains functions for fixed point math.
-- Please see the documentation for the fixed point package.
-- This package should be compiled into "ieee_proposed" and used as follows:
-- use ieee.std_logic_1164.all;
-- use ieee.numeric_std.all;
-- use ieee_proposed.fixed_pkg.all;
-- Last Modified: $Date: 2006/05/09 19:21:24 $
-- RCS ID: $Id: fixed_pkg_c.vhd,v 1.1 2006/05/09 19:21:24 sandeepd Exp $
--
-- Created for VHDL-200X par, David Bishop ([email protected])
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- synthesis translate_off
use std.textio.all;
-- synthesis translate_on
package fixed_pkg is
--%%% Uncomment the Generics
-- new work.fixed_generic_pkg
-- generic map (
-- fixed_round_style => true; -- fixed_round
-- fixed_overflow_style => true; -- fixed_saturate
-- fixed_guard_bits => 3; -- number of guard bits
-- no_warning => false -- show warnings
-- );
--%%% REMOVE THE REST OF THIS FILE.
constant fixed_round_style : BOOLEAN := true; -- round
constant fixed_overflow_style : BOOLEAN := true; -- saturate
constant fixed_guard_bits : NATURAL := 3; -- number of guard bits
constant no_warning : BOOLEAN := false; -- issue warnings
-- Author David Bishop ([email protected])
-- These 5 constants are used as defaults.
-- There is a mechanism to override them in every function
constant fixed_round : BOOLEAN := true; -- Turn on rounding routine
constant fixed_truncate : BOOLEAN := false; -- Trun off rounding routine
constant fixed_saturate : BOOLEAN := true; -- Saturate large numbers
constant fixed_wrap : BOOLEAN := false; -- Wrap large numbers
constant fixedsynth_or_real : BOOLEAN; -- differed constant
-- base Unsigned fixed point type, downto direction assumed
type ufixed is array (INTEGER range <>) of STD_LOGIC;
-- base Signed fixed point type, downto direction assumed
type sfixed is array (INTEGER range <>) of STD_LOGIC;
-----------------------------------------------------------------------------
-- Fixed point type is defined as follows:
-- 0000000000
-- 4321012345
-- 4 0 -5
-- The decimal point is assumed between the "0" and "-1" index
-- Thus "0011010000" = 6.5 and would be written as 00110.10000
-- All types are assumed to be in the "downto" direction.
--===========================================================================
-- Arithmetic Operators:
--===========================================================================
-- Modify the sign of the number, 2's complement
function "abs" (arg : sfixed) return sfixed;
function "-" (arg : sfixed)return sfixed;
-- Convert a signed fixed to an unsigned fixed
function "abs" (arg : sfixed) return ufixed;
-- Addition
-- ufixed(a downto b) + ufixed(c downto d)
-- = ufixed(max(a,c)+1 downto min(b,d))
function "+" (l, r : ufixed) return ufixed;
-- sfixed(a downto b) + sfixed(c downto d)
-- = sfixed(max(a,c)+1 downto min(b,d))
function "+" (l, r : sfixed) return sfixed;
-- Subtraction
-- ufixed(a downto b) - ufixed(c downto d)
-- = ufixed(max(a,c)+1 downto min(b,d))
function "-" (l, r : ufixed) return ufixed;
-- sfixed(a downto b) - sfixed(c downto d)
-- = sfixed(max(a,c)+1 downto min(b,d))
function "-" (l, r : sfixed) return sfixed;
-- Multiplication
-- ufixed(a downto b) * ufixed(c downto d) = ufixed(a+c+1 downto b+d)
function "*" (l, r : ufixed) return ufixed;
-- sfixed(a downto b) * sfixed(c downto d) = sfixed(a+c+1 downto b+d)
function "*" (l, r : sfixed) return sfixed;
-- Division
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function "/" (l, r : ufixed) return ufixed;
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function "/" (l, r : sfixed) return sfixed;
-- Remainder
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b,d))
function "rem" (l, r : ufixed) return ufixed;
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (min(a,c) downto min(b,d))
function "rem" (l, r : sfixed) return sfixed;
-- Modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b, d))
function "mod" (l, r : ufixed) return ufixed;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto min(b, d))
function "mod" (l, r : sfixed) return sfixed;
----------------------------------------------------------------------------
-- Overload routines. In these routines the "real" or "natural" (integer)
-- are converted into a fixed point number and then the operation is
-- performed. It is assumed that the array will be large enough.
-- If the input is "real" then the real number is converted into a fixed of
-- the same size as the fixed point input. If the number is an "integer"
-- then it is converted into fixed with the range (l'high downto 0).
----------------------------------------------------------------------------
-- ufixed(a downto b) + ufixed(a downto b) = ufixed(a+1 downto b)
function "+" (l : ufixed; r : REAL) return ufixed;
-- ufixed(c downto d) + ufixed(c downto d) = ufixed(c+1 downto d)
function "+" (l : REAL; r : ufixed) return ufixed;
-- ufixed(a downto b) + ufixed(a downto 0) = ufixed(a+1 downto min(0,b))
function "+" (l : ufixed; r : NATURAL) return ufixed;
-- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto min(0,d))
function "+" (l : NATURAL; r : ufixed) return ufixed;
-- ufixed(a downto b) - ufixed(a downto b) = ufixed(a+1 downto b)
function "-" (l : ufixed; r : REAL) return ufixed;
-- ufixed(c downto d) - ufixed(c downto d) = ufixed(c+1 downto d)
function "-" (l : REAL; r : ufixed) return ufixed;
-- ufixed(a downto b) - ufixed(a downto 0) = ufixed(a+1 downto min(0,b))
function "-" (l : ufixed; r : NATURAL) return ufixed;
-- ufixed(a downto 0) + ufixed(c downto d) = ufixed(c+1 downto min(0,d))
function "-" (l : NATURAL; r : ufixed) return ufixed;
-- ufixed(a downto b) * ufixed(a downto b) = ufixed(2a+1 downto 2b)
function "*" (l : ufixed; r : REAL) return ufixed;
-- ufixed(c downto d) * ufixed(c downto d) = ufixed(2c+1 downto 2d)
function "*" (l : REAL; r : ufixed) return ufixed;
-- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b)
function "*" (l : ufixed; r : NATURAL) return ufixed;
-- ufixed (a downto b) * ufixed (a downto 0) = ufixed (2a+1 downto b)
function "*" (l : NATURAL; r : ufixed) return ufixed;
-- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1)
function "/" (l : ufixed; r : REAL) return ufixed;
-- ufixed(a downto b) / ufixed(a downto b) = ufixed(a-b downto b-a-1)
function "/" (l : REAL; r : ufixed) return ufixed;
-- ufixed(a downto b) / ufixed(a downto 0) = ufixed(a downto b-a-1)
function "/" (l : ufixed; r : NATURAL) return ufixed;
-- ufixed(c downto 0) / ufixed(c downto d) = ufixed(c-d downto -c-1)
function "/" (l : NATURAL; r : ufixed) return ufixed;
-- ufixed (a downto b) rem ufixed (a downto b) = ufixed (a downto b)
function "rem" (l : ufixed; r : REAL) return ufixed;
-- ufixed (c downto d) rem ufixed (c downto d) = ufixed (c downto d)
function "rem" (l : REAL; r : ufixed) return ufixed;
-- ufixed (a downto b) rem ufixed (a downto 0) = ufixed (a downto min(b,0))
function "rem" (l : ufixed; r : NATURAL) return ufixed;
-- ufixed (c downto 0) rem ufixed (c downto d) = ufixed (c downto min(d,0))
function "rem" (l : NATURAL; r : ufixed) return ufixed;
-- ufixed (a downto b) mod ufixed (a downto b) = ufixed (a downto b)
function "mod" (l : ufixed; r : REAL) return ufixed;
-- ufixed (c downto d) mod ufixed (c downto d) = ufixed (c downto d)
function "mod" (l : REAL; r : ufixed) return ufixed;
-- ufixed (a downto b) mod ufixed (a downto 0) = ufixed (a downto min(b,0))
function "mod" (l : ufixed; r : NATURAL) return ufixed;
-- ufixed (c downto 0) mod ufixed (c downto d) = ufixed (c downto min(d,0))
function "mod" (l : NATURAL; r : ufixed) return ufixed;
-- sfixed(a downto b) + sfixed(a downto b) = sfixed(a+1 downto b)
function "+" (l : sfixed; r : REAL) return sfixed;
-- sfixed(c downto d) + sfixed(c downto d) = sfixed(c+1 downto d)
function "+" (l : REAL; r : sfixed) return sfixed;
-- sfixed(a downto b) + sfixed(a downto 0) = sfixed(a+1 downto min(0,b))
function "+" (l : sfixed; r : INTEGER) return sfixed;
-- sfixed(c downto 0) + sfixed(c downto d) = sfixed(c+1 downto min(0,d))
function "+" (l : INTEGER; r : sfixed) return sfixed;
-- sfixed(a downto b) - sfixed(a downto b) = sfixed(a+1 downto b)
function "-" (l : sfixed; r : REAL) return sfixed;
-- sfixed(c downto d) - sfixed(c downto d) = sfixed(c+1 downto d)
function "-" (l : REAL; r : sfixed) return sfixed;
-- sfixed(a downto b) - sfixed(a downto 0) = sfixed(a+1 downto min(0,b))
function "-" (l : sfixed; r : INTEGER) return sfixed;
-- sfixed(c downto 0) - sfixed(c downto d) = sfixed(c+1 downto min(0,d))
function "-" (l : INTEGER; r : sfixed) return sfixed;
-- sfixed(a downto b) * sfixed(a downto b) = sfixed(2a+1 downto 2b)
function "*" (l : sfixed; r : REAL) return sfixed;
-- sfixed(c downto d) * sfixed(c downto d) = sfixed(2c+1 downto 2d)
function "*" (l : REAL; r : sfixed) return sfixed;
-- sfixed(a downto b) * sfixed(a downto 0) = sfixed(2a+1 downto b)
function "*" (l : sfixed; r : INTEGER) return sfixed;
-- sfixed(c downto 0) * sfixed(c downto d) = sfixed(2c+1 downto d)
function "*" (l : INTEGER; r : sfixed) return sfixed;
-- sfixed(a downto b) / sfixed(a downto b) = sfixed(a-b+1 downto b-a)
function "/" (l : sfixed; r : REAL) return sfixed;
-- sfixed(c downto d) / sfixed(c downto d) = sfixed(c-d+1 downto d-c)
function "/" (l : REAL; r : sfixed) return sfixed;
-- sfixed(a downto b) / sfixed(a downto 0) = sfixed(a+1 downto b-a)
function "/" (l : sfixed; r : INTEGER) return sfixed;
-- sfixed(c downto 0) / sfixed(c downto d) = sfixed(c-d+1 downto -c)
function "/" (l : INTEGER; r : sfixed) return sfixed;
-- sfixed (a downto b) rem sfixed (a downto b) = sfixed (a downto b)
function "rem" (l : sfixed; r : REAL) return sfixed;
-- sfixed (c downto d) rem sfixed (c downto d) = sfixed (c downto d)
function "rem" (l : REAL; r : sfixed) return sfixed;
-- sfixed (a downto b) rem sfixed (a downto 0) = sfixed (a downto min(b,0))
function "rem" (l : sfixed; r : INTEGER) return sfixed;
-- sfixed (c downto 0) rem sfixed (c downto d) = sfixed (c downto min(d,0))
function "rem" (l : INTEGER; r : sfixed) return sfixed;
-- sfixed (a downto b) mod sfixed (a downto b) = sfixed (a downto b)
function "mod" (l : sfixed; r : REAL) return sfixed;
-- sfixed (c downto d) mod sfixed (c downto d) = sfixed (c downto d)
function "mod" (l : REAL; r : sfixed) return sfixed;
-- sfixed (a downto b) mod sfixed (a downto 0) = sfixed (a downto min(b,0))
function "mod" (l : sfixed; r : INTEGER) return sfixed;
-- sfixed (c downto 0) mod sfixed (c downto d) = sfixed (c downto min(d,0))
function "mod" (l : INTEGER; r : sfixed) return sfixed;
-- This version of divide gives the user more control
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function divide (
l, r : ufixed;
constant round_style : BOOLEAN := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return ufixed;
-- This version of divide gives the user more control
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function divide (
l, r : sfixed;
constant round_style : BOOLEAN := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return sfixed;
-- These functions return 1/X
-- 1 / ufixed(a downto b) = ufixed(-b downto -a-1)
function reciprocal (
arg : ufixed; -- fixed point input
constant round_style : BOOLEAN := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return ufixed;
-- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a)
function reciprocal (
arg : sfixed; -- fixed point input
constant round_style : BOOLEAN := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return sfixed;
-- REM function
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b,d))
function remainder (
l, r : ufixed;
constant round_style : BOOLEAN := fixed_round_style)
return ufixed;
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (min(a,c) downto min(b,d))
function remainder (
l, r : sfixed;
constant round_style : BOOLEAN := fixed_round_style)
return sfixed;
-- mod function
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b, d))
function modulo (
l, r : ufixed;
constant round_style : BOOLEAN := fixed_round_style)
return ufixed;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto min(b, d))
function modulo (
l, r : sfixed;
constant overflow_style : BOOLEAN := fixed_overflow_style;
constant round_style : BOOLEAN := fixed_round_style)
return sfixed;
-- Procedure for those who need an "accumulator" function.
-- add_carry (ufixed(a downto b), ufixed (c downto d))
-- = ufixed (max(a,c) downto min(b,d))
procedure add_carry (
L, R : in ufixed;
c_in : in STD_ULOGIC;
result : out ufixed;
c_out : out STD_ULOGIC);
-- add_carry (sfixed(a downto b), sfixed (c downto d))
-- = sfixed (max(a,c) downto min(b,d))
procedure add_carry (
L, R : in sfixed;
c_in : in STD_ULOGIC;
result : out sfixed;
c_out : out STD_ULOGIC);
-- Scales the result by a power of 2. Width of input = width of output with
-- the decimal point moved.
function scalb (y : ufixed; N : integer) return ufixed;
function scalb (y : ufixed; N : SIGNED) return ufixed;
function scalb (y : sfixed; N : integer) return sfixed;
function scalb (y : sfixed; N : SIGNED) return sfixed;
function Is_Negative (arg : sfixed) return BOOLEAN;
--===========================================================================
-- Comparison Operators
--===========================================================================
function ">" (l, r : ufixed) return BOOLEAN;
function ">" (l, r : sfixed) return BOOLEAN;
function "<" (l, r : ufixed) return BOOLEAN;
function "<" (l, r : sfixed) return BOOLEAN;
function "<=" (l, r : ufixed) return BOOLEAN;
function "<=" (l, r : sfixed) return BOOLEAN;
function ">=" (l, r : ufixed) return BOOLEAN;
function ">=" (l, r : sfixed) return BOOLEAN;
function "=" (l, r : ufixed) return BOOLEAN;
function "=" (l, r : sfixed) return BOOLEAN;
function "/=" (l, r : ufixed) return BOOLEAN;
function "/=" (l, r : sfixed) return BOOLEAN;
--%%% Uncomment the following (new syntax)
-- function "?=" (L, R : ufixed) return BOOLEAN;
-- function "?=" (L, R : sfixed) return BOOLEAN;
-- --%%% remove the following (old syntax)
function \?=\ (L, R : ufixed) return STD_ULOGIC;
function \?=\ (L, R : sfixed) return STD_ULOGIC;
-- These need to be overloaded for sfixed and ufixed
function \?/=\ (L, R : ufixed) return STD_ULOGIC;
function \?>\ (L, R : ufixed) return STD_ULOGIC;
function \?>=\ (L, R : ufixed) return STD_ULOGIC;
function \?<\ (L, R : ufixed) return STD_ULOGIC;
function \?<=\ (L, R : ufixed) return STD_ULOGIC;
function \?/=\ (L, R : sfixed) return STD_ULOGIC;
function \?>\ (L, R : sfixed) return STD_ULOGIC;
function \?>=\ (L, R : sfixed) return STD_ULOGIC;
function \?<\ (L, R : sfixed) return STD_ULOGIC;
function \?<=\ (L, R : sfixed) return STD_ULOGIC;
-- %%% Replace with the following (new syntax)
-- function "?=" (L, R : ufixed) return STD_ULOGIC;
-- function "?/=" (L, R : ufixed) return STD_ULOGIC;
-- function "?>" (L, R : ufixed) return STD_ULOGIC;
-- function "?>=" (L, R : ufixed) return STD_ULOGIC;
-- function "?<" (L, R : ufixed) return STD_ULOGIC;
-- function "?<=" (L, R : ufixed) return STD_ULOGIC;
-- function "?=" (L, R : sfixed) return STD_ULOGIC;
-- function "?/=" (L, R : sfixed) return STD_ULOGIC;
-- function "?>" (L, R : sfixed) return STD_ULOGIC;
-- function "?>=" (L, R : sfixed) return STD_ULOGIC;
-- function "?<" (L, R : sfixed) return STD_ULOGIC;
-- function "?<=" (L, R : sfixed) return STD_ULOGIC;
function std_match (L, R : ufixed) return BOOLEAN;
function std_match (L, R : sfixed) return BOOLEAN;
-- Overloads the default "maximum" and "minimum" function
function maximum (l, r : ufixed) return ufixed;
function minimum (l, r : ufixed) return ufixed;
function maximum (l, r : sfixed) return sfixed;
function minimum (l, r : sfixed) return sfixed;
----------------------------------------------------------------------------
-- In these compare functions a natural is converted into a
-- fixed point number of the bounds "max(l'high,0) downto 0"
----------------------------------------------------------------------------
function "=" (l : ufixed; r : NATURAL) return BOOLEAN;
function "/=" (l : ufixed; r : NATURAL) return BOOLEAN;
function ">=" (l : ufixed; r : NATURAL) return BOOLEAN;
function "<=" (l : ufixed; r : NATURAL) return BOOLEAN;
function ">" (l : ufixed; r : NATURAL) return BOOLEAN;
function "<" (l : ufixed; r : NATURAL) return BOOLEAN;
function "=" (l : NATURAL; r : ufixed) return BOOLEAN;
function "/=" (l : NATURAL; r : ufixed) return BOOLEAN;
function ">=" (l : NATURAL; r : ufixed) return BOOLEAN;
function "<=" (l : NATURAL; r : ufixed) return BOOLEAN;
function ">" (l : NATURAL; r : ufixed) return BOOLEAN;
function "<" (l : NATURAL; r : ufixed) return BOOLEAN;
----------------------------------------------------------------------------
-- In these compare functions a real is converted into a
-- fixed point number of the bounds "l'high+1 downto l'low"
----------------------------------------------------------------------------
function "=" (l : ufixed; r : REAL) return BOOLEAN;
function "/=" (l : ufixed; r : REAL) return BOOLEAN;
function ">=" (l : ufixed; r : REAL) return BOOLEAN;
function "<=" (l : ufixed; r : REAL) return BOOLEAN;
function ">" (l : ufixed; r : REAL) return BOOLEAN;
function "<" (l : ufixed; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : ufixed) return BOOLEAN;
function "/=" (l : REAL; r : ufixed) return BOOLEAN;
function ">=" (l : REAL; r : ufixed) return BOOLEAN;
function "<=" (l : REAL; r : ufixed) return BOOLEAN;
function ">" (l : REAL; r : ufixed) return BOOLEAN;
function "<" (l : REAL; r : ufixed) return BOOLEAN;
----------------------------------------------------------------------------
-- In these compare functions an integer is converted into a
-- fixed point number of the bounds "max(l'high,1) downto 0"
----------------------------------------------------------------------------
function "=" (l : sfixed; r : INTEGER) return BOOLEAN;
function "/=" (l : sfixed; r : INTEGER) return BOOLEAN;
function ">=" (l : sfixed; r : INTEGER) return BOOLEAN;
function "<=" (l : sfixed; r : INTEGER) return BOOLEAN;
function ">" (l : sfixed; r : INTEGER) return BOOLEAN;
function "<" (l : sfixed; r : INTEGER) return BOOLEAN;
function "=" (l : INTEGER; r : sfixed) return BOOLEAN;
function "/=" (l : INTEGER; r : sfixed) return BOOLEAN;
function ">=" (l : INTEGER; r : sfixed) return BOOLEAN;
function "<=" (l : INTEGER; r : sfixed) return BOOLEAN;
function ">" (l : INTEGER; r : sfixed) return BOOLEAN;
function "<" (l : INTEGER; r : sfixed) return BOOLEAN;
----------------------------------------------------------------------------
-- In these compare functions a real is converted into a
-- fixed point number of the bounds "l'high+1 downto l'low"
----------------------------------------------------------------------------
function "=" (l : sfixed; r : REAL) return BOOLEAN;
function "/=" (l : sfixed; r : REAL) return BOOLEAN;
function ">=" (l : sfixed; r : REAL) return BOOLEAN;
function "<=" (l : sfixed; r : REAL) return BOOLEAN;
function ">" (l : sfixed; r : REAL) return BOOLEAN;
function "<" (l : sfixed; r : REAL) return BOOLEAN;
function "=" (l : REAL; r : sfixed) return BOOLEAN;
function "/=" (l : REAL; r : sfixed) return BOOLEAN;
function ">=" (l : REAL; r : sfixed) return BOOLEAN;
function "<=" (l : REAL; r : sfixed) return BOOLEAN;
function ">" (l : REAL; r : sfixed) return BOOLEAN;
function "<" (l : REAL; r : sfixed) return BOOLEAN;
--===========================================================================
-- Shift and Rotate Functions.
-- Note that sra and sla are not the same as the BIT_VECTOR version
--===========================================================================
function "sll" (ARG : ufixed; COUNT : INTEGER) return ufixed;
function "srl" (ARG : ufixed; COUNT : INTEGER) return ufixed;
function "rol" (ARG : ufixed; COUNT : INTEGER) return ufixed;
function "ror" (ARG : ufixed; COUNT : INTEGER) return ufixed;
function "sla" (ARG : ufixed; COUNT : INTEGER) return ufixed;
function "sra" (ARG : ufixed; COUNT : INTEGER) return ufixed;
function "sll" (ARG : sfixed; COUNT : INTEGER) return sfixed;
function "srl" (ARG : sfixed; COUNT : INTEGER) return sfixed;
function "rol" (ARG : sfixed; COUNT : INTEGER) return sfixed;
function "ror" (ARG : sfixed; COUNT : INTEGER) return sfixed;
function "sla" (ARG : sfixed; COUNT : INTEGER) return sfixed;
function "sra" (ARG : sfixed; COUNT : INTEGER) return sfixed;
function SHIFT_LEFT (ARG : ufixed; COUNT : NATURAL) return ufixed;
function SHIFT_RIGHT (ARG : ufixed; COUNT : NATURAL) return ufixed;
function SHIFT_LEFT (ARG : sfixed; COUNT : NATURAL) return sfixed;
function SHIFT_RIGHT (ARG : sfixed; COUNT : NATURAL) return sfixed;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (L : ufixed) return ufixed;
function "and" (L, R : ufixed) return ufixed;
function "or" (L, R : ufixed) return ufixed;
function "nand" (L, R : ufixed) return ufixed;
function "nor" (L, R : ufixed) return ufixed;
function "xor" (L, R : ufixed) return ufixed;
function "xnor" (L, R : ufixed) return ufixed;
function "not" (L : sfixed) return sfixed;
function "and" (L, R : sfixed) return sfixed;
function "or" (L, R : sfixed) return sfixed;
function "nand" (L, R : sfixed) return sfixed;
function "nor" (L, R : sfixed) return sfixed;
function "xor" (L, R : sfixed) return sfixed;
function "xnor" (L, R : sfixed) return sfixed;
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (L : STD_ULOGIC; R : ufixed) return ufixed;
function "and" (L : ufixed; R : STD_ULOGIC) return ufixed;
function "or" (L : STD_ULOGIC; R : ufixed) return ufixed;
function "or" (L : ufixed; R : STD_ULOGIC) return ufixed;
function "nand" (L : STD_ULOGIC; R : ufixed) return ufixed;
function "nand" (L : ufixed; R : STD_ULOGIC) return ufixed;
function "nor" (L : STD_ULOGIC; R : ufixed) return ufixed;
function "nor" (L : ufixed; R : STD_ULOGIC) return ufixed;
function "xor" (L : STD_ULOGIC; R : ufixed) return ufixed;
function "xor" (L : ufixed; R : STD_ULOGIC) return ufixed;
function "xnor" (L : STD_ULOGIC; R : ufixed) return ufixed;
function "xnor" (L : ufixed; R : STD_ULOGIC) return ufixed;
function "and" (L : STD_ULOGIC; R : sfixed) return sfixed;
function "and" (L : sfixed; R : STD_ULOGIC) return sfixed;
function "or" (L : STD_ULOGIC; R : sfixed) return sfixed;
function "or" (L : sfixed; R : STD_ULOGIC) return sfixed;
function "nand" (L : STD_ULOGIC; R : sfixed) return sfixed;
function "nand" (L : sfixed; R : STD_ULOGIC) return sfixed;
function "nor" (L : STD_ULOGIC; R : sfixed) return sfixed;
function "nor" (L : sfixed; R : STD_ULOGIC) return sfixed;
function "xor" (L : STD_ULOGIC; R : sfixed) return sfixed;
function "xor" (L : sfixed; R : STD_ULOGIC) return sfixed;
function "xnor" (L : STD_ULOGIC; R : sfixed) return sfixed;
function "xnor" (L : sfixed; R : STD_ULOGIC) return sfixed;
-- Reduction operators, same as numeric_std functions
-- %%% remove 12 functions (old syntax)
function and_reduce(arg : ufixed) return STD_ULOGIC;
function nand_reduce(arg : ufixed) return STD_ULOGIC;
function or_reduce(arg : ufixed) return STD_ULOGIC;
function nor_reduce(arg : ufixed) return STD_ULOGIC;
function xor_reduce(arg : ufixed) return STD_ULOGIC;
function xnor_reduce(arg : ufixed) return STD_ULOGIC;
function and_reduce(arg : sfixed) return STD_ULOGIC;
function nand_reduce(arg : sfixed) return STD_ULOGIC;
function or_reduce(arg : sfixed) return STD_ULOGIC;
function nor_reduce(arg : sfixed) return STD_ULOGIC;
function xor_reduce(arg : sfixed) return STD_ULOGIC;
function xnor_reduce(arg : sfixed) return STD_ULOGIC;
-- %%% Uncomment the following 12 functions (new syntax)
-- function "and" ( arg : ufixed ) RETURN std_ulogic;
-- function "nand" ( arg : ufixed ) RETURN std_ulogic;
-- function "or" ( arg : ufixed ) RETURN std_ulogic;
-- function "nor" ( arg : ufixed ) RETURN std_ulogic;
-- function "xor" ( arg : ufixed ) RETURN std_ulogic;
-- function "xnor" ( arg : ufixed ) RETURN std_ulogic;
-- function "and" ( arg : sfixed ) RETURN std_ulogic;
-- function "nand" ( arg : sfixed ) RETURN std_ulogic;
-- function "or" ( arg : sfixed ) RETURN std_ulogic;
-- function "nor" ( arg : sfixed ) RETURN std_ulogic;
-- function "xor" ( arg : sfixed ) RETURN std_ulogic;
-- function "xnor" ( arg : sfixed ) RETURN std_ulogic;
-- returns arg'low-1 if not found
function find_msb (arg : ufixed; y : STD_ULOGIC) return INTEGER;
function find_msb (arg : sfixed; y : STD_ULOGIC) return INTEGER;
-- returns arg'high+1 if not found
function find_lsb (arg : ufixed; y : STD_ULOGIC) return INTEGER;
function find_lsb (arg : sfixed; y : STD_ULOGIC) return INTEGER;
--===========================================================================
-- RESIZE Functions
--===========================================================================
-- resizes the number (larger or smaller)
-- The returned result will be ufixed (left_index downto right_index)
-- If "round_style" is true, then the result will be rounded. If the MSB
-- of the remainder is a "1" AND the LSB of the unround result is a '1' or
-- the lower bits of the remainder include a '1' then the result will be
-- increased by the smallest representable number for that type.
-- The default is "true" for round_style.
-- "overflow_style" can be "true" (saturate mode) or "false" (wrap mode).
-- In saturate mode, if the number overflows then the largest possible
-- representable number is returned. If wrap mode, then the upper bits
-- of the number are truncated.
function resize (
arg : ufixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow
constant round_style : BOOLEAN := fixed_round_style) -- rounding
return ufixed;
-- "size_res" functions create the size of the output from the length
-- of the "size_res" input. The actual value of "size_res" is not used.
function resize (
arg : ufixed; -- input
size_res : ufixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow
constant round_style : BOOLEAN := fixed_round_style) -- rounding
return ufixed;
-- Note that in "wrap" mode the sign bit is not replicated. Thus the
-- resize of a negative number can have a positive result in wrap mode.
function resize (
arg : sfixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return sfixed;
function resize (
arg : sfixed; -- input
size_res : sfixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return sfixed;
--===========================================================================
-- Conversion Functions
--===========================================================================
-- integer (natural) to unsigned fixed point.
-- arguments are the upper and lower bounds of the number, thus
-- ufixed (7 downto -3) <= to_ufixed (int, 7, -3);
function to_ufixed (
arg : NATURAL; -- integer
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding
return ufixed;
function to_ufixed (
arg : NATURAL; -- integer
size_res : ufixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding
return ufixed;
-- real to unsigned fixed point
function to_ufixed (
arg : REAL; -- real
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style; -- rounding by default
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return ufixed;
function to_ufixed (
arg : REAL; -- real
size_res : ufixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style; -- rounding by default
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return ufixed;
-- unsigned to unsigned fixed point
function to_ufixed (
arg : UNSIGNED; -- unsigned
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return ufixed;
function to_ufixed (
arg : UNSIGNED; -- unsigned
size_res : ufixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return ufixed;
-- Performs a casting. ufixed (arg'range) is returned
function to_ufixed (
arg : UNSIGNED) -- unsigned
return ufixed;
-- unsigned fixed point to unsigned
function to_unsigned (
arg : ufixed; -- fixed point input
constant size : NATURAL; -- length of output
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return UNSIGNED;
-- unsigned fixed point to unsigned
function to_unsigned (
arg : ufixed; -- fixed point input
size_res : UNSIGNED; -- used for length of output
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return UNSIGNED;
-- unsigned fixed point to real
function to_real (
arg : ufixed) -- fixed point input
return REAL;
-- unsigned fixed point to integer
function to_integer (
arg : ufixed; -- fixed point input
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return NATURAL;
-- Integer to sfixed
function to_sfixed (
arg : INTEGER; -- integer
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return sfixed;
function to_sfixed (
arg : INTEGER; -- integer
size_res : sfixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return sfixed;
-- Real to sfixed
function to_sfixed (
arg : REAL; -- real
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style; -- rounding by default
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return sfixed;
function to_sfixed (
arg : REAL; -- real
size_res : sfixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style; -- rounding by default
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return sfixed;
-- signed to sfixed
function to_sfixed (
arg : SIGNED; -- signed
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return sfixed;
function to_sfixed (
arg : SIGNED; -- signed
size_res : sfixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return sfixed;
-- signed to sfixed (output assumed to be size of signed input)
function to_sfixed (
arg : SIGNED) -- signed
return sfixed;
-- unsigned fixed point to signed fixed point (adds a "0" sign bit)
function add_sign (
arg : ufixed) -- unsigned fixed point
return sfixed;
-- signed fixed point to signed
function to_signed (
arg : sfixed; -- fixed point input
constant size : NATURAL; -- length of output
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return SIGNED;
-- signed fixed point to signed
function to_signed (
arg : sfixed; -- fixed point input
size_res : SIGNED; -- used for length of output
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return SIGNED;
-- signed fixed point to real
function to_real (
arg : sfixed) -- fixed point input
return REAL;
-- signed fixed point to integer
function to_integer (
arg : sfixed; -- fixed point input
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return INTEGER;
-- Because of the farily complicated sizing rules in the fixed point
-- packages these functions are provided to compute the result ranges
-- Example:
-- signal uf1 : ufixed (3 downto -3);
-- signal uf2 : ufixed (4 downto -2);
-- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto
-- ufixed_low (3, -3, '*', 4, -2));
-- uf1multuf2 <= uf1 * uf2;
-- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod)
function ufixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function ufixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function sfixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
function sfixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER;
-- Same as above, but using the "size_res" input only for their ranges:
-- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto
-- ufixed_low (uf1, '*', uf2));
-- uf1multuf2 <= uf1 * uf2;
function ufixed_high (size_res : ufixed;
operation : CHARACTER := 'X';
size_res2 : ufixed)
return INTEGER;
function ufixed_low (size_res : ufixed;
operation : CHARACTER := 'X';
size_res2 : ufixed)
return INTEGER;
function sfixed_high (size_res : sfixed;
operation : CHARACTER := 'X';
size_res2 : sfixed)
return INTEGER;
function sfixed_low (size_res : sfixed;
operation : CHARACTER := 'X';
size_res2 : sfixed)
return INTEGER;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed;
function saturate (
size_res : ufixed) -- only the size of this is used
return ufixed;
function saturate (
size_res : sfixed) -- only the size of this is used
return sfixed;
--===========================================================================
-- Translation Functions
--===========================================================================
-- Maps meta-logical values
function to_01 (
s : ufixed; -- fixed point input
constant XMAP : STD_LOGIC := '0') -- Map x to
return ufixed;
-- maps meta-logical values
function to_01 (
s : sfixed; -- fixed point input
constant XMAP : STD_LOGIC := '0') -- Map x to
return sfixed;
function Is_X (arg : ufixed) return BOOLEAN;
function Is_X (arg : sfixed) return BOOLEAN;
function to_X01 (arg : ufixed) return ufixed;
function to_X01 (arg : sfixed) return sfixed;
function to_X01Z (arg : ufixed) return ufixed;
function to_X01Z (arg : sfixed) return sfixed;
function to_UX01 (arg : ufixed) return ufixed;
function to_UX01 (arg : sfixed) return sfixed;
-- straight vector conversion routines, needed for synthesis.
-- These functions are here so that a std_logic_vector can be
-- converted to and from sfixed and ufixed. Note that you can
-- not cast these vectors because of their negative index.
function to_slv (
arg : ufixed) -- fp vector
return STD_LOGIC_VECTOR;
-- alias to_StdLogicVector is to_slv [ufixed return STD_LOGIC_VECTOR];
-- alias to_Std_Logic_Vector is to_slv [ufixed return STD_LOGIC_VECTOR];
function to_slv (
arg : sfixed) -- fp vector
return STD_LOGIC_VECTOR;
-- alias to_StdLogicVector is to_slv [sfixed return STD_LOGIC_VECTOR];
-- alias to_Std_Logic_Vector is to_slv [sfixed return STD_LOGIC_VECTOR];
function to_sulv (
arg : ufixed) -- fp vector
return STD_ULOGIC_VECTOR;
-- alias to_StdULogicVector is to_sulv [ufixed return STD_ULOGIC_VECTOR];
-- alias to_Std_ULogic_Vector is to_sulv [ufixed return STD_ULOGIC_VECTOR];
function to_sulv (
arg : sfixed) -- fp vector
return STD_ULOGIC_VECTOR;
-- alias to_StdULogicVector is to_sulv [sfixed return STD_ULOGIC_VECTOR];
-- alias to_Std_ULogic_Vector is to_sulv [sfixed return STD_ULOGIC_VECTOR];
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed;
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : ufixed) -- for size only
return ufixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : sfixed) -- for size only
return sfixed;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : ufixed) -- for size only
return ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : sfixed) -- for size only
return sfixed;
-- As a concession to those who use a graphical DSP environment,
-- these functions take parameters in those tools format and create
-- fixed point numbers. These functions are designed to convert from
-- a std_logic_vector to the VHDL fixed point format using the conventions
-- of these packages. In a pure VHDL environment you should use the
-- "to_ufixed" and "to_sfixed" routines.
-- Unsigned fixed point
function to_UFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return ufixed;
-- signed fixed point
function to_SFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return sfixed;
-- finding the bounds of a number. These functions can be used like this:
-- signal xxx : ufixed (7 downto -3);
-- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))"
-- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3)
-- downto UFix_low(11, 3, "+", 11, 3));
-- Where "11" is the width of xxx (xxx'length),
-- and 3 is the lower bound (abs (xxx'low))
-- In a pure VHDL environment use "ufixed_high" and "ufixed_low"
function UFix_high (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
function UFix_low (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
-- Same as above but for signed fixed point. Note that the width
-- of a signed fixed point number ignores the sign bit, thus
-- width = sxxx'length-1
function SFix_high (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
function SFix_low (width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER;
--===========================================================================
-- string and textio Functions
--===========================================================================
-- rtl_synthesis off
-- synthesis translate_off
-- purpose: writes fixed point into a line
procedure WRITE (
L : inout LINE; -- input line
VALUE : in ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
-- purpose: writes fixed point into a line
procedure WRITE (
L : inout LINE; -- input line
VALUE : in sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure READ(L : inout LINE;
VALUE : out ufixed);
procedure READ(L : inout LINE;
VALUE : out ufixed;
GOOD : out BOOLEAN);
procedure READ(L : inout LINE;
VALUE : out sfixed);
procedure READ(L : inout LINE;
VALUE : out sfixed;
GOOD : out BOOLEAN);
alias bwrite is WRITE [LINE, ufixed, SIDE, width];
alias bwrite is WRITE [LINE, sfixed, SIDE, width];
alias bread is READ [LINE, ufixed];
alias bread is READ [LINE, ufixed, BOOLEAN];
alias bread is READ [LINE, sfixed];
alias bread is READ [LINE, sfixed, BOOLEAN];
-- octal read and write
procedure OWRITE (
L : inout LINE; -- input line
VALUE : in ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure OWRITE (
L : inout LINE; -- input line
VALUE : in sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure OREAD(L : inout LINE;
VALUE : out ufixed);
procedure OREAD(L : inout LINE;
VALUE : out ufixed;
GOOD : out BOOLEAN);
procedure OREAD(L : inout LINE;
VALUE : out sfixed);
procedure OREAD(L : inout LINE;
VALUE : out sfixed;
GOOD : out BOOLEAN);
-- hex read and write
procedure HWRITE (
L : inout LINE; -- input line
VALUE : in ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
-- purpose: writes fixed point into a line
procedure HWRITE (
L : inout LINE; -- input line
VALUE : in sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0);
procedure HREAD(L : inout LINE;
VALUE : out ufixed);
procedure HREAD(L : inout LINE;
VALUE : out ufixed;
GOOD : out BOOLEAN);
procedure HREAD(L : inout LINE;
VALUE : out sfixed);
procedure HREAD(L : inout LINE;
VALUE : out sfixed;
GOOD : out BOOLEAN);
-- returns a string, useful for:
-- assert (x = y) report "error found " & to_string(x) severity error;
function to_string (
value : ufixed;
justified : SIDE := right;
field : WIDTH := 0
) return STRING;
alias to_bstring is to_string [ufixed, SIDE, width return STRING];
function to_ostring (
value : ufixed;
justified : SIDE := right;
field : WIDTH := 0
) return STRING;
function to_hstring (
value : ufixed;
justified : SIDE := right;
field : WIDTH := 0
) return STRING;
function to_string (
value : sfixed;
justified : SIDE := right;
field : WIDTH := 0
) return STRING;
alias to_bstring is to_string [sfixed, SIDE, width return STRING];
function to_ostring (
value : sfixed;
justified : SIDE := right;
field : WIDTH := 0
) return STRING;
function to_hstring (
value : sfixed;
justified : SIDE := right;
field : WIDTH := 0
) return STRING;
-- From string functions allow you to convert a string into a fixed
-- point number. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5
-- The "." is optional in this syntax, however it exist and is
-- in the wrong location an error is produced. Overflow will
-- result in saturation.
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed;
alias from_bstring is from_string [STRING, INTEGER, INTEGER return ufixed];
-- Octal and hex conversions work as follows:
-- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped)
-- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped)
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed;
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed;
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed;
alias from_bstring is from_string [STRING, INTEGER, INTEGER return sfixed];
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed;
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed;
-- Same as above, "size_res" is used for it's range only.
function from_string (
bstring : STRING; -- binary string
size_res : ufixed)
return ufixed;
alias from_bstring is from_string [STRING, ufixed return ufixed];
function from_ostring (
ostring : STRING; -- Octal string
size_res : ufixed)
return ufixed;
function from_hstring (
hstring : STRING; -- hex string
size_res : ufixed)
return ufixed;
function from_string (
bstring : STRING; -- binary string
size_res : sfixed)
return sfixed;
alias from_bstring is from_string [STRING, sfixed return sfixed];
function from_ostring (
ostring : STRING; -- Octal string
size_res : sfixed)
return sfixed;
function from_hstring (
hstring : STRING; -- hex string
size_res : sfixed)
return sfixed;
-- Direct converstion functions. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100"); -- 6.5
-- In this case the "." is not optional, and the size of
-- the output must match exactly.
function from_string (
bstring : STRING) -- binary string
return ufixed;
alias from_bstring is from_string [STRING return ufixed];
-- Direct octal and hex converstion functions. In this case
-- the string lengths must match. Example:
-- signal sf1 := sfixed (5 downto -3);
-- sf1 <= from_ostring ("71.4") -- -6.5
function from_ostring (
ostring : STRING) -- Octal string
return ufixed;
function from_hstring (
hstring : STRING) -- hex string
return ufixed;
function from_string (
bstring : STRING) -- binary string
return sfixed;
alias from_bstring is from_string [STRING return sfixed];
function from_ostring (
ostring : STRING) -- Octal string
return sfixed;
function from_hstring (
hstring : STRING) -- hex string
return sfixed;
-- synthesis translate_on
-- rtl_synthesis on
-- This type is here for the floating point package.
type round_type is (round_nearest, -- Default, nearest LSB '0'
round_inf, -- Round to positive
round_neginf, -- Round to negate
round_zero); -- Round towards zero
-- These are the same as the C FE_TONEAREST, FE_UPWARD, FE_DOWNWARD,
-- and FE_TOWARDZERO floating point rounding macros.
function to_StdLogicVector (
arg : ufixed) -- fp vector
return STD_LOGIC_VECTOR;
function to_Std_Logic_Vector (
arg : ufixed) -- fp vector
return STD_LOGIC_VECTOR;
function to_StdLogicVector (
arg : sfixed) -- fp vector
return STD_LOGIC_VECTOR;
function to_Std_Logic_Vector (
arg : sfixed) -- fp vector
return STD_LOGIC_VECTOR;
end package fixed_pkg;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use std.textio.all;
use ieee.std_logic_textio.all; -- %%% for testing only
package body fixed_pkg is
-- Author David Bishop ([email protected])
-- Other contributers: Jim Lewis, Yannick Grugni, Ryan W. Hilton
-- null array constants
constant NAUF : ufixed (0 downto 1) := (others => '0');
constant NASF : sfixed (0 downto 1) := (others => '0');
constant NSLV : STD_LOGIC_VECTOR (0 downto 1) := (others => '0');
-- This differed constant will tell you if the package body is synthesizable
-- or implemented as real numbers, set to "true" if synthesizable.
constant fixedsynth_or_real : BOOLEAN := true;
--%%% Can be removed in vhdl-200x, will be implicit.
-- purpose: To find the largest of 2 numbers
function maximum (l, r : INTEGER)
return INTEGER is
begin -- function maximum
if L > R then return L;
else return R;
end if;
end function maximum;
function minimum (l, r : INTEGER)
return INTEGER is
begin -- function minimum
if L > R then return R;
else return L;
end if;
end function minimum;
-- %%% Remove the following function (duplicates of new numeric_std)
function "sra" (arg : SIGNED; count : INTEGER)
return SIGNED is
begin
if (COUNT >= 0) then
return SHIFT_RIGHT(arg, count);
else
return SHIFT_LEFT(arg, -count);
end if;
end function "sra";
-- %%% Replace or_reducex with "or", and_reducex with "and", and
-- %%% xor_reducex with "xor", then remove the following 3 functions
-- purpose: OR all of the bits in a vector together
-- This is a copy of the proposed "or_reduce" from 1076.3
function or_reducex (arg : STD_LOGIC_VECTOR)
return STD_LOGIC is
variable Upper, Lower : STD_LOGIC;
variable Half : INTEGER;
variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_LOGIC;
begin
if (arg'length < 1) then -- In the case of a NULL range
Result := '0';
else
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int (BUS_int'right) or BUS_int (BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := or_reducex (BUS_int (BUS_int'left downto Half));
Lower := or_reducex (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper or Lower;
end if;
end if;
return Result;
end function or_reducex;
-- purpose: AND all of the bits in a vector together
-- This is a copy of the proposed "and_reduce" from 1076.3
function and_reducex (arg : STD_LOGIC_VECTOR)
return STD_LOGIC is
variable Upper, Lower : STD_LOGIC;
variable Half : INTEGER;
variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_LOGIC;
begin
if (arg'length < 1) then -- In the case of a NULL range
Result := '1';
else
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int (BUS_int'right) and BUS_int (BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := and_reducex (BUS_int (BUS_int'left downto Half));
Lower := and_reducex (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper and Lower;
end if;
end if;
return Result;
end function and_reducex;
function xor_reducex (arg : STD_LOGIC_VECTOR) return STD_ULOGIC is
variable Upper, Lower : STD_ULOGIC;
variable Half : INTEGER;
variable BUS_int : STD_LOGIC_VECTOR (arg'length - 1 downto 0);
variable Result : STD_ULOGIC := '0'; -- In the case of a NULL range
begin
if (arg'length >= 1) then
BUS_int := to_ux01 (arg);
if (BUS_int'length = 1) then
Result := BUS_int (BUS_int'left);
elsif (BUS_int'length = 2) then
Result := BUS_int(BUS_int'right) xor BUS_int(BUS_int'left);
else
Half := (BUS_int'length + 1) / 2 + BUS_int'right;
Upper := xor_reducex (BUS_int (BUS_int'left downto Half));
Lower := xor_reducex (BUS_int (Half - 1 downto BUS_int'right));
Result := Upper xor Lower;
end if;
end if;
return Result;
end function xor_reducex;
--%%% remove the following function and table
-- Match table, copied form new std_logic_1164
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
constant match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | X |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | 0 |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1'), -- | W |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '1'), -- | L |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '1'), -- | H |
('1', '1', '1', '1', '1', '1', '1', '1', '1') -- | - |
);
constant no_match_logic_table : stdlogic_table := (
-----------------------------------------------------
-- U X 0 1 Z W L H - | |
-----------------------------------------------------
('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '0'), -- | U |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | X |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | 0 |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | 1 |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | Z |
('U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '0'), -- | W |
('U', 'X', '0', '1', 'X', 'X', '0', '1', '0'), -- | L |
('U', 'X', '1', '0', 'X', 'X', '1', '0', '0'), -- | H |
('0', '0', '0', '0', '0', '0', '0', '0', '0') -- | - |
);
-------------------------------------------------------------------
-- ?= functions, Similar to "std_match", but returns "std_ulogic".
-------------------------------------------------------------------
-- %%% FUNCTION "?=" ( l, r : std_ulogic ) RETURN std_ulogic IS
function \?=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return match_logic_table (l, r);
end function \?=\;
-- %%% END FUNCTION "?=";
-- %%% FUNCTION "?/=" ( l, r : std_ulogic ) RETURN std_ulogic is
function \?/=\ (l, r : STD_ULOGIC) return STD_ULOGIC is
begin
return no_match_logic_table (l, r);
end function \?/=\;
-- %%% END FUNCTION "?/=";
-- %%% end remove
-- Special version of "minimum" to do some boundary checking without errors
function mins (l, r : INTEGER)
return INTEGER is
begin -- function mins
if (L = INTEGER'low or R = INTEGER'low) then
return 0; -- error condition
end if;
return minimum (L, R);
end function mins;
-- Special version of "minimum" to do some boundary checking with errors
function mine (l, r : INTEGER)
return INTEGER is
begin -- function mine
if (L = INTEGER'low or R = INTEGER'low) then
report "FIXED_GENERIC_PKG: Unbounded number passed, was a literal used?"
severity error;
return 0;
end if;
return minimum (L, R);
end function mine;
-- The following functions are used only internally. Every function
-- calls "cleanvec" either directly or indirectly.
-- purpose: Fixes "downto" problem and resolves meta states
function cleanvec (
arg : sfixed) -- input
return sfixed is
constant left_index : INTEGER := maximum(arg'left, arg'right);
constant right_index : INTEGER := mins(arg'left, arg'right);
variable result : sfixed (arg'range);
begin -- function cleanvec
assert not ((arg'left < arg'right) and (arg'low /= INTEGER'low))
report "FIXED_GENERIC_PKG: Vector passed using a ""to"" range, expected is ""downto"""
severity error;
return arg;
end function cleanvec;
-- purpose: Fixes "downto" problem and resolves meta states
function cleanvec (
arg : ufixed) -- input
return ufixed is
constant left_index : INTEGER := maximum(arg'left, arg'right);
constant right_index : INTEGER := mins(arg'left, arg'right);
variable result : ufixed (arg'range);
begin -- function cleanvec
assert not ((arg'left < arg'right) and (arg'low /= INTEGER'low))
report "FIXED_GENERIC_PKG: Vector passed using a ""to"" range, expected is ""downto"""
severity error;
return arg;
end function cleanvec;
-- Type cast a "unsigned" into a "ufixed", used internally
function to_fixed (
arg : UNSIGNED; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed is
variable result : ufixed (left_index downto right_index);
-- variable j : INTEGER := arg'high; -- index for arg
begin -- function to_fixed
result := ufixed(arg);
-- floop : for i in result'range loop
-- result(i) := arg(j); -- res(4) := arg (4 + 3)
-- j := j - 1;
-- end loop floop;
return result;
end function to_fixed;
-- Type cast a "signed" into an "sfixed", used internally
function to_fixed (
arg : SIGNED; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed is
variable result : sfixed (left_index downto right_index);
-- variable j : INTEGER := arg'high; -- index for arg
begin -- function to_fixed
result := sfixed(arg);
-- floop : for i in result'range loop
-- result(i) := arg(j); -- res(4) := arg (4 + 3)
-- j := j - 1;
-- end loop floop;
return result;
end function to_fixed;
-- Type cast a "ufixed" into an "unsigned", used internally
function to_uns (
arg : ufixed) -- fp vector
return UNSIGNED is
subtype t is UNSIGNED(arg'high - arg'low downto 0);
variable slv : t;
begin -- function to_uns
slv := t(arg);
-- floop : for i in slv'range loop
-- slv(i) := arg(i + arg'low); -- slv(7) := arg (7 - 3)
-- end loop floop;
return UNSIGNED(to_X01(std_logic_vector(slv)));
end function to_uns;
-- Type cast an "sfixed" into a "signed", used internally
function to_s (
arg : sfixed) -- fp vector
return SIGNED is
subtype t is SIGNED(arg'high - arg'low downto 0);
variable slv : t;
begin -- function to_s
slv := t(arg);
-- floop : for i in slv'range loop
-- slv(i) := arg(i + arg'low); -- slv(7) := arg (7 - 3)
-- end loop floop;
return SIGNED(to_X01(std_logic_vector(slv)));
end function to_s;
-- adds 1 to the LSB of the number
procedure round_up (arg : in ufixed;
result : out ufixed;
overflowx : out BOOLEAN) is
variable arguns, resuns : UNSIGNED (arg'high-arg'low+1 downto 0) :=
(others => '0');
begin -- round_up
arguns (arguns'high-1 downto 0) := to_uns (arg);
resuns := arguns + 1;
result := to_fixed(resuns(arg'high-arg'low
downto 0), arg'high, arg'low);
overflowx := (resuns(resuns'high) = '1');
end procedure round_up;
-- adds 1 to the LSB of the number
procedure round_up (arg : in sfixed;
result : out sfixed;
overflowx : out BOOLEAN) is
variable args, ress : SIGNED (arg'high-arg'low+1 downto 0);
begin -- round_up
args (args'high-1 downto 0) := to_s (arg);
args(args'high) := arg(arg'high); -- sign extend
ress := args + 1;
result := to_fixed(ress (ress'high-1
downto 0), arg'high, arg'low);
overflowx := ((arg(arg'high) /= ress(ress'high-1))
and (or_reducex (STD_LOGIC_VECTOR(ress)) /= '0'));
end procedure round_up;
-- Rounding - Performs a "round_nearest" (IEEE 754) which rounds up
-- when the remainder is > 0.5. If the remainder IS 0.5 then if the
-- bottom bit is a "1" it is rounded, otherwise it remains the same.
function round_fixed (arg : ufixed;
remainder : ufixed;
overflow_style : BOOLEAN := fixed_overflow_style)
return ufixed is
variable rounds : BOOLEAN;
variable round_overflow : BOOLEAN;
variable result : ufixed (arg'range);
begin
rounds := false;
if (remainder'length > 1) then
if (remainder (remainder'high) = '1') then
rounds := (arg(arg'low) = '1')
or (or_reducex (to_slv(remainder(remainder'high-1 downto
remainder'low))) = '1');
end if;
else
rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1');
end if;
if rounds then
round_up(arg => arg,
result => result,
overflowx => round_overflow);
else
result := arg;
end if;
if (overflow_style = fixed_saturate) and round_overflow then
result := saturate (result'high, result'low);
end if;
return result;
end function round_fixed;
-- Rounding case statement
function round_fixed (arg : sfixed;
remainder : sfixed;
overflow_style : BOOLEAN := fixed_overflow_style)
return sfixed is
variable rounds : BOOLEAN;
variable round_overflow : BOOLEAN;
variable result : sfixed (arg'range);
begin
rounds := false;
if (remainder'length > 1) then
if (remainder (remainder'high) = '1') then
rounds := (arg(arg'low) = '1')
or (or_reducex (to_slv(remainder(remainder'high-1 downto
remainder'low))) = '1');
end if;
else
rounds := (arg(arg'low) = '1') and (remainder (remainder'high) = '1');
end if;
if rounds then
round_up(arg => arg,
result => result,
overflowx => round_overflow);
else
result := arg;
end if;
if round_overflow then
if (overflow_style = fixed_saturate) then
if arg(arg'high) = '0' then
result := saturate (result'high, result'low);
else
result := not saturate (result'high, result'low);
end if;
-- else
-- result(result'high) := arg(arg'high); -- fix sign bit in wrap
end if;
end if;
return result;
end function round_fixed;
-----------------------------------------------------------------------------
-- Visible functions
-----------------------------------------------------------------------------
-- casting functions. These are needed for synthesis where typically
-- the only input and output type is a std_logic_vector.
function to_slv (
arg : ufixed) -- fixed point vector
return STD_LOGIC_VECTOR is
subtype t is STD_LOGIC_VECTOR (arg'high - arg'low downto 0);
variable slv : t;
begin
if arg'length < 1 then
return NSLV;
end if;
slv := t (arg);
return slv;
end function to_slv;
function to_slv (
arg : sfixed) -- fixed point vector
return STD_LOGIC_VECTOR is
subtype t is STD_LOGIC_VECTOR (arg'high - arg'low downto 0);
variable slv : t;
begin
if arg'length < 1 then
return NSLV;
end if;
slv := t (arg);
return slv;
end function to_slv;
function to_sulv (
arg : ufixed) -- fixed point vector
return STD_ULOGIC_VECTOR is
begin
return to_stdulogicvector (to_slv(arg));
end function to_sulv;
function to_sulv (
arg : sfixed) -- fixed point vector
return STD_ULOGIC_VECTOR is
begin
return to_stdulogicvector (to_slv(arg));
end function to_sulv;
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed is
variable result : ufixed (left_index downto right_index);
begin
if (arg'length < 1 or right_index > left_index) then
return NAUF;
end if;
if (arg'length /= result'length) then
report "FIXED_GENERIC_PKG.TO_UFIXED (STD_LOGIC_VECTOR) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NAUF;
else
result := to_fixed (arg => UNSIGNED(arg),
left_index => left_index,
right_index => right_index);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed is
variable result : sfixed (left_index downto right_index);
begin
if (arg'length < 1 or right_index > left_index) then
return NASF;
end if;
if (arg'length /= result'length) then
report "FIXED_GENERIC_PKG.TO_SFIXED (STD_LOGIC_VECTOR) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NASF;
else
result := to_fixed (arg => SIGNED(arg),
left_index => left_index,
right_index => right_index);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed is
begin
return to_ufixed (arg => to_stdlogicvector(arg),
left_index => left_index,
right_index => right_index);
end function to_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed is
begin
return to_sfixed (arg => to_stdlogicvector(arg),
left_index => left_index,
right_index => right_index);
end function to_sfixed;
-- Two's complement number, Grows the vector by 1 bit.
-- because "abs (1000.000) = 01000.000" or abs(-16) = 16.
function "abs" (
arg : sfixed) -- fixed point input
return sfixed is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable ressns : SIGNED (arg'length downto 0);
variable result : sfixed (left_index+1 downto right_index);
begin
if (arg'length < 1 or result'length < 1) then
return NASF;
end if;
ressns (arg'length-1 downto 0) := to_s (cleanvec (arg));
ressns (arg'length) := ressns (arg'length-1); -- expand sign bit
result := to_fixed (abs(ressns), left_index+1, right_index);
return result;
end function "abs";
-- also grows the vector by 1 bit.
function "-" (
arg : sfixed) -- fixed point input
return sfixed is
constant left_index : INTEGER := arg'high+1;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable ressns : SIGNED (arg'length downto 0);
variable result : sfixed (left_index downto right_index);
begin
if (arg'length < 1 or result'length < 1) then
return NASF;
end if;
ressns (arg'length-1 downto 0) := to_s (cleanvec(arg));
ressns (arg'length) := ressns (arg'length-1); -- expand sign bit
result := to_fixed (-ressns, left_index, right_index);
return result;
end function "-";
function "abs" (arg : sfixed) return ufixed is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := mine(arg'low, arg'low);
variable xarg : sfixed(left_index+1 downto right_index);
variable result : ufixed(left_index downto right_index);
begin
if arg'length < 1 then
return NAUF;
end if;
xarg := abs(arg);
result := ufixed (xarg (left_index downto right_index));
return result;
end function "abs";
-- Addition
function "+" (
l, r : ufixed) -- ufixed(a downto b) + ufixed(c downto d) =
return ufixed is -- ufixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable result : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNSIGNED (left_index-right_index
downto 0);
begin
if (l'length < 1 or r'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv + rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "+";
function "+" (
l, r : sfixed) -- sfixed(a downto b) + sfixed(c downto d) =
return sfixed is -- sfixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable result : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (left_index-right_index downto 0);
variable result_slv : SIGNED (left_index-right_index downto 0);
begin
if (l'length < 1 or r'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv + rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "+";
-- Subtraction
function "-" (
l, r : ufixed) -- ufixed(a downto b) - ufixed(c downto d) =
return ufixed is -- ufixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable result : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNSIGNED (left_index-right_index
downto 0);
begin
if (l'length < 1 or r'length < 1) then
return NAUF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv - rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "-";
function "-" (
l, r : sfixed) -- sfixed(a downto b) - sfixed(c downto d) =
return sfixed is -- sfixed(max(a,c)+1 downto min(b,d))
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable result : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (left_index-right_index downto 0);
variable result_slv : SIGNED (left_index-right_index downto 0);
begin
if (l'length < 1 or r'length < 1) then
return NASF;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv - rslv;
result := to_fixed(result_slv, left_index, right_index);
return result;
end function "-";
function "*" (
l, r : ufixed) -- ufixed(a downto b) * ufixed(c downto d) =
return ufixed is -- ufixed(a+c+1 downto b+d)
variable lslv : UNSIGNED (l'length-1 downto 0);
variable rslv : UNSIGNED (r'length-1 downto 0);
variable result_slv : UNSIGNED (r'length+l'length-1 downto 0);
variable result : ufixed (l'high + r'high+1 downto
mine(l'low, l'low) + mine(r'low, r'low));
begin
if (l'length < 1 or r'length < 1 or
result'length /= result_slv'length) then
return NAUF;
end if;
lslv := to_uns (cleanvec(l));
rslv := to_uns (cleanvec(r));
result_slv := lslv * rslv;
result := to_fixed (result_slv, result'high, result'low);
return result;
end function "*";
function "*" (
l, r : sfixed) -- sfixed(a downto b) * sfixed(c downto d) =
return sfixed is -- sfixed(a+c+1 downto b+d)
variable lslv : SIGNED (l'length-1 downto 0);
variable rslv : SIGNED (r'length-1 downto 0);
variable result_slv : SIGNED (r'length+l'length-1 downto 0);
variable result : sfixed (l'high + r'high+1 downto
mine(l'low, l'low) + mine(r'low, r'low));
begin
if (l'length < 1 or r'length < 1 or
result'length /= result_slv'length) then
return NASF;
end if;
lslv := to_s (cleanvec(l));
rslv := to_s (cleanvec(r));
result_slv := lslv * rslv;
result := to_fixed (result_slv, result'high, result'low);
return result;
end function "*";
function "/" (
l, r : ufixed) -- ufixed(a downto b) / ufixed(c downto d) =
return ufixed is -- ufixed(a-d downto b-c-1)
begin
return divide (l, r);
end function "/";
function "/" (
l, r : sfixed) -- sfixed(a downto b) / sfixed(c downto d) =
return sfixed is -- sfixed(a-d+1 downto b-c)
begin
return divide (l, r);
end function "/";
-- This version of divide gives the user more control
-- ufixed(a downto b) / ufixed(c downto d) = ufixed(a-d downto b-c-1)
function divide (
l, r : ufixed;
constant round_style : BOOLEAN := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return ufixed is
variable result : ufixed (l'high - mine(r'low, r'low)
downto mine (l'low, l'low) - r'high -1);
variable dresult : ufixed (result'high downto result'low -guard_bits);
variable lresize : ufixed (l'high downto l'high - dresult'length+1);
variable lslv : UNSIGNED (lresize'length-1 downto 0);
variable rslv : UNSIGNED (r'length-1 downto 0);
variable result_slv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NAUF;
end if;
lresize := resize (l, lresize'high, lresize'low);
lslv := to_uns (cleanvec (lresize));
rslv := to_uns (cleanvec (r));
if (rslv = 0) then
report "FIXED_GENERIC_PKG.DIVIDE uFixed point Division by zero" severity error;
result := saturate (result'high, result'low); -- saturate
else
result_slv := lslv / rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
round_style => round_style,
overflow_style => fixed_wrap); -- overflow impossible
end if;
return result;
end function divide;
-- sfixed(a downto b) / sfixed(c downto d) = sfixed(a-d+1 downto b-c)
function divide (
l, r : sfixed;
constant round_style : BOOLEAN := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return sfixed is
variable result : sfixed (l'high - mine(r'low, r'low)+1
downto mine (l'low, l'low) - r'high);
variable dresult : sfixed (result'high downto result'low-guard_bits);
variable lresize : sfixed (l'high+1 downto l'high+1 -dresult'length+1);
variable lslv : SIGNED (lresize'length-1 downto 0);
variable rslv : SIGNED (r'length-1 downto 0);
variable result_slv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
lresize := resize (l, lresize'high, lresize'low);
lslv := to_s (cleanvec (lresize));
rslv := to_s (cleanvec (r));
if (rslv = 0) then
report "FIXED_GENERIC_PKG.DIVIDE uFixed point Division by zero" severity error;
result := saturate (result'high, result'low);
else
result_slv := lslv / rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
round_style => round_style,
overflow_style => fixed_wrap); -- overflow impossible
end if;
return result;
end function divide;
-- 1 / ufixed(a downto b) = ufixed(-b downto -a-1)
function reciprocal (
arg : ufixed; -- fixed point input
constant round_style : BOOLEAN := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return ufixed is
constant one : ufixed (0 downto 0) := "1";
begin
return divide(l => one,
r => arg,
round_style => round_style,
guard_bits => guard_bits);
end function reciprocal;
-- 1 / sfixed(a downto b) = sfixed(-b+1 downto -a)
function reciprocal (
arg : sfixed; -- fixed point input
constant round_style : BOOLEAN := fixed_round_style;
constant guard_bits : NATURAL := fixed_guard_bits)
return sfixed is
constant one : sfixed (1 downto 0) := "01"; -- extra bit.
variable resultx : sfixed (-mine(arg'low, arg'low)+2 downto -arg'high);
begin
if (arg'length < 1 or resultx'length < 1) then
return NASF;
else
resultx := divide(l => one,
r => arg,
round_style => round_style,
guard_bits => guard_bits);
return resultx (resultx'high-1 downto resultx'low); -- remove extra bit
end if;
end function reciprocal;
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b,d))
function "rem" (
l, r : ufixed) -- fixed point input
return ufixed is
begin
return remainder (l => l,
r => r,
round_style => fixed_round_style);
end function "rem";
-- remainder
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (min(a,c) downto min(b,d))
function "rem" (
l, r : sfixed) -- fixed point input
return sfixed is
begin
return remainder (l => l,
r => r,
round_style => fixed_round_style);
end function "rem";
-- ufixed (a downto b) rem ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b,d))
function remainder (
l, r : ufixed; -- fixed point input
constant round_style : BOOLEAN := fixed_round_style)
return ufixed is
variable result : ufixed (minimum(l'high, r'high) downto mine(l'low, r'low));
variable dresult : ufixed (r'high downto r'low);
variable lresize : ufixed (maximum(l'high, r'low) downto mins(r'low, r'low));
variable lslv : UNSIGNED (lresize'length-1 downto 0);
variable rslv : UNSIGNED (r'length-1 downto 0);
variable result_slv : UNSIGNED (rslv'range);
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NAUF;
end if;
lresize := resize (arg => l,
left_index => lresize'high,
right_index => lresize'low,
overflow_style => fixed_wrap, -- vector only grows
round_style => fixed_truncate);
lslv := to_uns (lresize);
rslv := to_uns (cleanvec(r));
if (rslv = 0) then
report "FIXED_GENERIC_PKG.rem uFixed point Division by zero" severity error;
result := saturate (result'high, result'low); -- saturate
else
if (r'low <= l'high) then
result_slv := lslv rem rslv;
dresult := to_fixed (result_slv, dresult'high, dresult'low);
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => fixed_wrap,
round_style => round_style);
-- result(result'high downto r'low) := dresult(result'high downto r'low);
end if;
if l'low < r'low then
result(mins(r'low-1, l'high) downto l'low) :=
cleanvec(l(mins(r'low-1, l'high) downto l'low));
end if;
end if;
return result;
end function remainder;
-- remainder
-- sfixed (a downto b) rem sfixed (c downto d)
-- = sfixed (min(a,c) downto min(b,d))
function remainder (
l, r : sfixed; -- fixed point input
constant round_style : BOOLEAN := fixed_round_style)
return sfixed is
variable l_abs : ufixed (l'range);
variable r_abs : ufixed (r'range);
variable result : sfixed (minimum(r'high, l'high) downto mine(r'low, l'low));
variable neg_result : sfixed (minimum(r'high, l'high)+1 downto mins(r'low, l'low));
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
l_abs := abs(l);
r_abs := abs(r);
result := sfixed(remainder (l => l_abs,
r => r_abs,
round_style => round_style));
neg_result := -result;
if l(l'high) = '1' then
result := neg_result(result'range);
end if;
return result;
end function remainder;
-- modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b, d))
function "mod" (
l, r : ufixed) -- fixed point input
return ufixed is
begin
return modulo (l => l,
r => r,
round_style => fixed_round_style);
end function "mod";
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto min(b, d))
function "mod" (
l, r : sfixed) -- fixed point input
return sfixed is
begin
return modulo(l => l,
r => r,
round_style => fixed_round_style);
end function "mod";
-- modulo
-- ufixed (a downto b) mod ufixed (c downto d)
-- = ufixed (min(a,c) downto min(b, d))
function modulo (
l, r : ufixed; -- fixed point input
constant round_style : BOOLEAN := fixed_round_style)
return ufixed is
begin
return remainder(l => l,
r => r,
round_style => round_style);
end function modulo;
-- sfixed (a downto b) mod sfixed (c downto d)
-- = sfixed (c downto min(b, d))
function modulo (
l, r : sfixed; -- fixed point input
constant overflow_style : BOOLEAN := fixed_overflow_style;
constant round_style : BOOLEAN := fixed_round_style)
return sfixed is
variable l_abs : ufixed (l'range);
variable r_abs : ufixed (r'range);
variable result : sfixed (r'high downto
mine(r'low, l'low));
variable dresult : sfixed (minimum(r'high, l'high)+1 downto
mins(r'low, l'low));
variable dresult_not_zero : BOOLEAN;
begin
if (l'length < 1 or r'length < 1 or
mins(r'low, r'low) /= r'low or mins(l'low, l'low) /= l'low) then
return NASF;
end if;
l_abs := abs(l);
r_abs := abs(r);
dresult := "0" & sfixed(remainder (l => l_abs,
r => r_abs,
round_style => round_style));
if (to_s(dresult) = 0) then
dresult_not_zero := false;
else
dresult_not_zero := true;
end if;
if to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '0'
and dresult_not_zero then
result := resize (arg => r - dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
elsif to_x01(l(l'high)) = '1' and to_x01(r(r'high)) = '1' then
result := resize (arg => -dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
elsif to_x01(l(l'high)) = '0' and to_x01(r(r'high)) = '1'
and dresult_not_zero then
result := resize (arg => dresult + r,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
else
result := resize (arg => dresult,
left_index => result'high,
right_index => result'low,
overflow_style => overflow_style,
round_style => round_style);
end if;
return result;
end function modulo;
-- Procedure for those who need an "accumulator" function
procedure add_carry (
L, R : in ufixed;
c_in : in STD_ULOGIC;
result : out ufixed;
c_out : out STD_ULOGIC) is
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (left_index-right_index
downto 0);
variable result_slv : UNSIGNED (left_index-right_index
downto 0);
variable cx : UNSIGNED (0 downto 0); -- Carry in
begin
if (l'length < 1 or r'length < 1) then
result := NAUF;
c_out := '0';
else
cx (0) := c_in;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
result_slv := lslv + rslv + cx;
c_out := result_slv(left_index);
result := to_fixed(result_slv (left_index-right_index-1 downto 0),
left_index-1, right_index);
end if;
end procedure add_carry;
procedure add_carry (
L, R : in sfixed;
c_in : in STD_ULOGIC;
result : out sfixed;
c_out : out STD_ULOGIC) is
constant left_index : INTEGER := maximum(l'high, r'high)+1;
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (left_index-right_index
downto 0);
variable result_slv : SIGNED (left_index-right_index
downto 0);
variable cx : SIGNED (1 downto 0); -- Carry in
begin
if (l'length < 1 or r'length < 1) then
result := NASF;
c_out := '0';
else
cx (1) := '0';
cx (0) := c_in;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
result_slv := lslv + rslv + cx;
c_out := result_slv(left_index);
result := to_fixed(result_slv (left_index-right_index-1 downto 0),
left_index-1, right_index);
end if;
end procedure add_carry;
-- Scales the result by a power of 2. Width of input = width of output with
-- the decimal point moved.
function scalb (y : ufixed; N : integer) return ufixed is
variable result : ufixed (y'high+N downto y'low+N);
begin
if y'length < 1 then
return NAUF;
else
result := y;
return result;
end if;
end function scalb;
function scalb (y : ufixed; N : SIGNED) return ufixed is
begin
return scalb (y => y,
N => to_integer(N));
end function scalb;
function scalb (y : sfixed; N : integer) return sfixed is
variable result : sfixed (y'high+N downto y'low+N);
begin
if y'length < 1 then
return NASF;
else
result := y;
return result;
end if;
end function scalb;
function scalb (y : sfixed; N : SIGNED) return sfixed is
begin
return scalb (y => y,
N => to_integer(N));
end function scalb;
function Is_Negative (arg : sfixed) return BOOLEAN is
begin
if to_X01(arg(arg'high)) = '1' then
return true;
else
return false;
end if;
end function Is_Negative;
function find_lsb (arg : ufixed; y : STD_ULOGIC) return INTEGER is
begin
for_loop : for i in arg'low to arg'high loop
if arg(i) = y then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_lsb;
function find_msb (arg : ufixed; y : STD_ULOGIC) return INTEGER is
begin
for_loop : for i in arg'high downto arg'low loop
if arg(i) = y then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_msb;
function find_lsb (arg : sfixed; y : STD_ULOGIC) return INTEGER is
begin
for_loop : for i in arg'low to arg'high loop
if arg(i) = y then
return i;
end if;
end loop;
return arg'high+1; -- return out of bounds 'high
end function find_lsb;
function find_msb (arg : sfixed; y : STD_ULOGIC) return INTEGER is
begin
for_loop : for i in arg'high downto arg'low loop
if arg(i) = y then
return i;
end if;
end loop;
return arg'low-1; -- return out of bounds 'low
end function find_msb;
function "sll" (ARG : ufixed; COUNT : INTEGER) return ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sll";
function "srl" (ARG : ufixed; COUNT : INTEGER) return ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "srl";
function "rol" (ARG : ufixed; COUNT : INTEGER) return ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv rol COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "rol";
function "ror" (ARG : ufixed; COUNT : INTEGER) return ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : ufixed (arg'range);
begin
argslv := to_uns (arg);
argslv := argslv ror COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "ror";
function "sla" (ARG : ufixed; COUNT : INTEGER) return ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : ufixed (arg'range);
begin
argslv := to_uns (arg);
-- Arithmetic shift on an unsigned is a logical shift
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sla";
function "sra" (ARG : ufixed; COUNT : INTEGER) return ufixed is
variable argslv : UNSIGNED (arg'length-1 downto 0);
variable result : ufixed (arg'range);
begin
argslv := to_uns (arg);
-- Arithmetic shift on an unsigned is a logical shift
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sra";
function "sll" (ARG : sfixed; COUNT : INTEGER) return sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv sll COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sll";
function "srl" (ARG : sfixed; COUNT : INTEGER) return sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv srl COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "srl";
function "rol" (ARG : sfixed; COUNT : INTEGER) return sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv rol COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "rol";
function "ror" (ARG : sfixed; COUNT : INTEGER) return sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : sfixed (arg'range);
begin
argslv := to_s (arg);
argslv := argslv ror COUNT;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "ror";
function "sla" (ARG : sfixed; COUNT : INTEGER) return sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : sfixed (arg'range);
begin
argslv := to_s (arg);
if COUNT > 0 then
-- Arithmetic shift left on a 2's complement number is a logic shift
argslv := argslv sll COUNT;
else
argslv := argslv sra -COUNT;
end if;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sla";
function "sra" (ARG : sfixed; COUNT : INTEGER) return sfixed is
variable argslv : SIGNED (arg'length-1 downto 0);
variable result : sfixed (arg'range);
begin
argslv := to_s (arg);
if COUNT > 0 then
argslv := argslv sra COUNT;
else
-- Arithmetic shift left on a 2's complement number is a logic shift
argslv := argslv sll -COUNT;
end if;
result := to_fixed (argslv, result'high, result'low);
return result;
end function "sra";
-- Because some people want the older functions.
function SHIFT_LEFT (ARG : ufixed; COUNT : NATURAL) return ufixed is
begin
if (ARG'length < 1) then
return NAUF;
end if;
return ARG sla COUNT;
end function SHIFT_LEFT;
function SHIFT_RIGHT (ARG : ufixed; COUNT : NATURAL) return ufixed is
begin
if (ARG'length < 1) then
return NAUF;
end if;
return ARG sra COUNT;
end function SHIFT_RIGHT;
function SHIFT_LEFT (ARG : sfixed; COUNT : NATURAL) return sfixed is
begin
if (ARG'length < 1) then
return NASF;
end if;
return ARG sla COUNT;
end function SHIFT_LEFT;
function SHIFT_RIGHT (ARG : sfixed; COUNT : NATURAL) return sfixed is
begin
if (ARG'length < 1) then
return NASF;
end if;
return ARG sra COUNT;
end function SHIFT_RIGHT;
----------------------------------------------------------------------------
-- logical functions
----------------------------------------------------------------------------
function "not" (L : ufixed) return ufixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
RESULT := not to_slv(L);
return to_ufixed(RESULT, L'high, L'low);
end function "not";
function "and" (L, R : ufixed) return ufixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) and to_slv(R);
else
report "FIXED_GENERIC_PKG.""and"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "and";
function "or" (L, R : ufixed) return ufixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) or to_slv(R);
else
report "FIXED_GENERIC_PKG.""or"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "or";
function "nand" (L, R : ufixed) return ufixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) nand to_slv(R);
else
report "FIXED_GENERIC_PKG.""nand"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "nand";
function "nor" (L, R : ufixed) return ufixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) nor to_slv(R);
else
report "FIXED_GENERIC_PKG.""nor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "nor";
function "xor" (L, R : ufixed) return ufixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) xor to_slv(R);
else
report "FIXED_GENERIC_PKG.""xor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "xor";
function "xnor" (L, R : ufixed) return ufixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) xnor to_slv(R);
else
report "FIXED_GENERIC_PKG.""xnor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_ufixed(RESULT, L'high, L'low);
end function "xnor";
function "not" (L : sfixed) return sfixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
RESULT := not to_slv(L);
return to_sfixed(RESULT, L'high, L'low);
end function "not";
function "and" (L, R : sfixed) return sfixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) and to_slv(R);
else
report "FIXED_GENERIC_PKG.""and"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "and";
function "or" (L, R : sfixed) return sfixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) or to_slv(R);
else
report "FIXED_GENERIC_PKG.""or"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "or";
function "nand" (L, R : sfixed) return sfixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) nand to_slv(R);
else
report "FIXED_GENERIC_PKG.""nand"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "nand";
function "nor" (L, R : sfixed) return sfixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) nor to_slv(R);
else
report "FIXED_GENERIC_PKG.""nor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "nor";
function "xor" (L, R : sfixed) return sfixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) xor to_slv(R);
else
report "FIXED_GENERIC_PKG.""xor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "xor";
function "xnor" (L, R : sfixed) return sfixed is
variable RESULT : STD_LOGIC_VECTOR(L'length-1 downto 0); -- force downto
begin
if (L'high = R'high and L'low = R'low) then
RESULT := to_slv(L) xnor to_slv(R);
else
report "FIXED_GENERIC_PKG.""xnor"": Range error L'RANGE /= R'RANGE"
severity warning;
RESULT := (others => 'U');
end if;
return to_sfixed(RESULT, L'high, L'low);
end function "xnor";
-- Vector and std_ulogic functions, same as functions in numeric_std
function "and" (L : STD_ULOGIC; R : ufixed) return ufixed is
variable result : ufixed (R'range);
begin
for i in result'range loop
result(i) := L and R(i);
end loop;
return result;
end function "and";
function "and" (L : ufixed; R : STD_ULOGIC) return ufixed is
variable result : ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) and R;
end loop;
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : ufixed) return ufixed is
variable result : ufixed (R'range);
begin
for i in result'range loop
result(i) := L or R(i);
end loop;
return result;
end function "or";
function "or" (L : ufixed; R : STD_ULOGIC) return ufixed is
variable result : ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) or R;
end loop;
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : ufixed) return ufixed is
variable result : ufixed (R'range);
begin
for i in result'range loop
result(i) := L nand R(i);
end loop;
return result;
end function "nand";
function "nand" (L : ufixed; R : STD_ULOGIC) return ufixed is
variable result : ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nand R;
end loop;
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : ufixed) return ufixed is
variable result : ufixed (R'range);
begin
for i in result'range loop
result(i) := L nor R(i);
end loop;
return result;
end function "nor";
function "nor" (L : ufixed; R : STD_ULOGIC) return ufixed is
variable result : ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nor R;
end loop;
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : ufixed) return ufixed is
variable result : ufixed (R'range);
begin
for i in result'range loop
result(i) := L xor R(i);
end loop;
return result;
end function "xor";
function "xor" (L : ufixed; R : STD_ULOGIC) return ufixed is
variable result : ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xor R;
end loop;
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : ufixed) return ufixed is
variable result : ufixed (R'range);
begin
for i in result'range loop
result(i) := L xnor R(i);
end loop;
return result;
end function "xnor";
function "xnor" (L : ufixed; R : STD_ULOGIC) return ufixed is
variable result : ufixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xnor R;
end loop;
return result;
end function "xnor";
function "and" (L : STD_ULOGIC; R : sfixed) return sfixed is
variable result : sfixed (R'range);
begin
for i in result'range loop
result(i) := L and R(i);
end loop;
return result;
end function "and";
function "and" (L : sfixed; R : STD_ULOGIC) return sfixed is
variable result : sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) and R;
end loop;
return result;
end function "and";
function "or" (L : STD_ULOGIC; R : sfixed) return sfixed is
variable result : sfixed (R'range);
begin
for i in result'range loop
result(i) := L or R(i);
end loop;
return result;
end function "or";
function "or" (L : sfixed; R : STD_ULOGIC) return sfixed is
variable result : sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) or R;
end loop;
return result;
end function "or";
function "nand" (L : STD_ULOGIC; R : sfixed) return sfixed is
variable result : sfixed (R'range);
begin
for i in result'range loop
result(i) := L nand R(i);
end loop;
return result;
end function "nand";
function "nand" (L : sfixed; R : STD_ULOGIC) return sfixed is
variable result : sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nand R;
end loop;
return result;
end function "nand";
function "nor" (L : STD_ULOGIC; R : sfixed) return sfixed is
variable result : sfixed (R'range);
begin
for i in result'range loop
result(i) := L nor R(i);
end loop;
return result;
end function "nor";
function "nor" (L : sfixed; R : STD_ULOGIC) return sfixed is
variable result : sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) nor R;
end loop;
return result;
end function "nor";
function "xor" (L : STD_ULOGIC; R : sfixed) return sfixed is
variable result : sfixed (R'range);
begin
for i in result'range loop
result(i) := L xor R(i);
end loop;
return result;
end function "xor";
function "xor" (L : sfixed; R : STD_ULOGIC) return sfixed is
variable result : sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xor R;
end loop;
return result;
end function "xor";
function "xnor" (L : STD_ULOGIC; R : sfixed) return sfixed is
variable result : sfixed (R'range);
begin
for i in result'range loop
result(i) := L xnor R(i);
end loop;
return result;
end function "xnor";
function "xnor" (L : sfixed; R : STD_ULOGIC) return sfixed is
variable result : sfixed (L'range);
begin
for i in result'range loop
result(i) := L(i) xnor R;
end loop;
return result;
end function "xnor";
-- Reduction operators, same as numeric_std functions
-- %%% remove 12 functions (old syntax)
function and_reduce(arg : ufixed) return STD_ULOGIC is
begin
return and_reducex (to_slv(arg));
end function and_reduce;
function nand_reduce(arg : ufixed) return STD_ULOGIC is
begin
return not and_reducex (to_slv(arg));
end function nand_reduce;
function or_reduce(arg : ufixed) return STD_ULOGIC is
begin
return or_reducex (to_slv(arg));
end function or_reduce;
function nor_reduce(arg : ufixed) return STD_ULOGIC is
begin
return not or_reducex (to_slv(arg));
end function nor_reduce;
function xor_reduce(arg : ufixed) return STD_ULOGIC is
begin
return xor_reducex (to_slv(arg));
end function xor_reduce;
function xnor_reduce(arg : ufixed) return STD_ULOGIC is
begin
return not xor_reducex (to_slv(arg));
end function xnor_reduce;
function and_reduce(arg : sfixed) return STD_ULOGIC is
begin
return and_reducex (to_slv(arg));
end function and_reduce;
function nand_reduce(arg : sfixed) return STD_ULOGIC is
begin
return not and_reducex (to_slv(arg));
end function nand_reduce;
function or_reduce(arg : sfixed) return STD_ULOGIC is
begin
return or_reducex (to_slv(arg));
end function or_reduce;
function nor_reduce(arg : sfixed) return STD_ULOGIC is
begin
return not or_reducex (to_slv(arg));
end function nor_reduce;
function xor_reduce(arg : sfixed) return STD_ULOGIC is
begin
return xor_reducex (to_slv(arg));
end function xor_reduce;
function xnor_reduce(arg : sfixed) return STD_ULOGIC is
begin
return not xor_reducex (to_slv(arg));
end function xnor_reduce;
-- %%% Uncomment the following 12 functions (new syntax)
-- function "and" ( arg : ufixed ) RETURN std_ulogic is
-- begin
-- return and to_slv(arg);
-- end function "and";
-- function "nand" ( arg : ufixed ) RETURN std_ulogic is
-- begin
-- return nand to_slv(arg);
-- end function "nand";;
-- function "or" ( arg : ufixed ) RETURN std_ulogic is
-- begin
-- return or to_slv(arg);
-- end function "or";
-- function "nor" ( arg : ufixed ) RETURN std_ulogic is
-- begin
-- return nor to_slv(arg);
-- end function "nor";
-- function "xor" ( arg : ufixed ) RETURN std_ulogic is
-- begin
-- return xor to_slv(arg);
-- end function "xor";
-- function "xnor" ( arg : ufixed ) RETURN std_ulogic is
-- begin
-- return xnor to_slv(arg);
-- end function "xnor";
-- function "and" ( arg : sfixed ) RETURN std_ulogic is
-- begin
-- return and to_slv(arg);
-- end function "and";;
-- function "nand" ( arg : sfixed ) RETURN std_ulogic is
-- begin
-- return nand to_slv(arg);
-- end function "nand";;
-- function "or" ( arg : sfixed ) RETURN std_ulogic is
-- begin
-- return or to_slv(arg);
-- end function "or";
-- function "nor" ( arg : sfixed ) RETURN std_ulogic is
-- begin
-- return nor to_slv(arg);
-- end function "nor";
-- function "xor" ( arg : sfixed ) RETURN std_ulogic is
-- begin
-- return xor to_slv(arg);
-- end function "xor";
-- function "xnor" ( arg : sfixed ) RETURN std_ulogic is
-- begin
-- return xnor to_slv(arg);
-- end function "xnor";
-- %%% Replace with the following (new syntax)
-- function "?=" (L, R : ufixed) return STD_ULOGIC is
function \?=\ (L, R : ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
result := '1';
for i in lresize'reverse_range loop
result1 := \?=\(lresize(i), rresize(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- end function "?=";
-- function "?/=" (L, R : ufixed) return STD_ULOGIC is
function \?/=\ (L, R : ufixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?/=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?/="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
result := '0';
for i in lresize'reverse_range loop
result1 := \?/=\ (lresize(i), rresize(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
-- end function "?/=";
-- function "?>" (L, R : ufixed) return STD_ULOGIC is
function \?>\ (L, R : ufixed) return STD_ULOGIC is
begin -- ?>
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?>"": null detected, returning X"
severity warning;
return 'X';
elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
report "FIXED_GENERIC_PKG.""?>"": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
-- end function "?>";
-- function "?>=" (L, R : ufixed) return STD_ULOGIC is
function \?>=\ (L, R : ufixed) return STD_ULOGIC is
begin -- ?>=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?>="": null detected, returning X"
severity warning;
return 'X';
elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
report "FIXED_GENERIC_PKG.""?>="": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
-- end function "?>=";
-- function "?<" (L, R : ufixed) return STD_ULOGIC is
function \?<\ (L, R : ufixed) return STD_ULOGIC is
begin -- ?<
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?<"": null detected, returning X"
severity warning;
return 'X';
elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
report "FIXED_GENERIC_PKG.""?<"": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
-- end function "?<";
-- function "?<=" (L, R : ufixed) return STD_ULOGIC is
function \?<=\ (L, R : ufixed) return STD_ULOGIC is
begin -- ?<=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?<="": null detected, returning X"
severity warning;
return 'X';
elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
report "FIXED_GENERIC_PKG.""?<="": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- end function "?<=";
-- function "?=" (L, R : sfixed) return STD_ULOGIC is
function \?=\ (L, R : sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
result := '1';
for i in lresize'reverse_range loop
result1 := \?=\ (lresize(i), rresize(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result and result1;
end if;
end loop;
return result;
end if;
end function \?=\;
-- end function "?=";
-- function "?/=" (L, R : sfixed) return STD_ULOGIC is
function \?/=\ (L, R : sfixed) return STD_ULOGIC is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable result, result1 : STD_ULOGIC; -- result
begin -- ?/=
if ((L'LENGTH < 1) or (R'LENGTH < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?/="": null detected, returning X"
severity warning;
return 'X';
else
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
result := '0';
for i in lresize'reverse_range loop
result1 := \?/=\ (lresize(i), rresize(i));
if result1 = 'U' then
return 'U';
elsif result1 = 'X' or result = 'X' then
result := 'X';
else
result := result or result1;
end if;
end loop;
return result;
end if;
end function \?/=\;
-- end function "?/=";
-- function "?>" (L, R : sfixed) return STD_ULOGIC is
function \?>\ (L, R : sfixed) return STD_ULOGIC is
begin -- ?>
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?>"": null detected, returning X"
severity warning;
return 'X';
elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
report "FIXED_GENERIC_PKG.""?>"": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l > r then
return '1';
else
return '0';
end if;
end if;
end function \?>\;
-- end function "?>";
-- function "?>=" (L, R : sfixed) return STD_ULOGIC is
function \?>=\ (L, R : sfixed) return STD_ULOGIC is
begin -- ?>=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?>="": null detected, returning X"
severity warning;
return 'X';
elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
report "FIXED_GENERIC_PKG.""?>="": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l >= r then
return '1';
else
return '0';
end if;
end if;
end function \?>=\;
-- end function "?>=";
-- function "?<" (L, R : sfixed) return STD_ULOGIC is
function \?<\ (L, R : sfixed) return STD_ULOGIC is
begin -- ?<
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?<"": null detected, returning X"
severity warning;
return 'X';
elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
report "FIXED_GENERIC_PKG.""?<"": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l < r then
return '1';
else
return '0';
end if;
end if;
end function \?<\;
-- end function "?<";
-- function "?<=" (L, R : sfixed) return STD_ULOGIC is
function \?<=\ (L, R : sfixed) return STD_ULOGIC is
begin -- ?<=
if ((l'length < 1) or (r'length < 1)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""?<="": null detected, returning X"
severity warning;
return 'X';
elsif (find_msb (l, '-') /= l'low-1) or (find_msb (r, '-') /= r'low-1) then
report "FIXED_GENERIC_PKG.""?<="": '-' found in compare string"
severity error;
return 'X';
else
if is_x(l) or is_x(r) then
return 'X';
elsif l <= r then
return '1';
else
return '0';
end if;
end if;
end function \?<=\;
-- end function "?<=";
-- %%% end replace
-- Match function, similar to "std_match" from numeric_std
function std_match (L, R : ufixed) return BOOLEAN is
begin
if (L'high = R'high and L'low = R'low) then
return std_match(to_slv(L), to_slv(R));
else
report "FIXED_GENERIC_PKG.STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
severity warning;
return false;
end if;
end function std_match;
function std_match (L, R : sfixed) return BOOLEAN is
begin
if (L'high = R'high and L'low = R'low) then
return std_match(to_slv(L), to_slv(R));
else
report "FIXED_GENERIC_PKG.STD_MATCH: L'RANGE /= R'RANGE, returning FALSE"
severity warning;
return false;
end if;
end function std_match;
--%%% end remove
-- compare functions
function "=" (
l, r : ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv = rslv;
end function "=";
function "=" (
l, r : sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv = rslv;
end function "=";
function "/=" (
l, r : ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""/="": null argument detected, returning TRUE"
severity warning;
return true;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv /= rslv;
end function "/=";
function "/=" (
l, r : sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""/="": null argument detected, returning TRUE"
severity warning;
return true;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""/="": metavalue detected, returning TRUE"
severity warning;
return true;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv /= rslv;
end function "/=";
function ">" (
l, r : ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG."">"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG."">"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv > rslv;
end function ">";
function ">" (
l, r : sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG."">"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG."">"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv > rslv;
end function ">";
function "<" (
l, r : ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""<"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv < rslv;
end function "<";
function "<" (
l, r : sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""<"": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""<"": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv < rslv;
end function "<";
function ">=" (
l, r : ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG."">="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG."">="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv >= rslv;
end function ">=";
function ">=" (
l, r : sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG."">="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG."">="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv >= rslv;
end function ">=";
function "<=" (
l, r : ufixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : ufixed (left_index downto right_index);
variable lslv, rslv : UNSIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""<="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_uns (lresize);
rslv := to_uns (rresize);
return lslv <= rslv;
end function "<=";
function "<=" (
l, r : sfixed) -- fixed point input
return BOOLEAN is
constant left_index : INTEGER := maximum(l'high, r'high);
constant right_index : INTEGER := mins(l'low, r'low);
variable lresize, rresize : sfixed (left_index downto right_index);
variable lslv, rslv : SIGNED (lresize'length-1 downto 0);
begin
if (l'length < 1 or r'length < 1) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""<="": null argument detected, returning FALSE"
severity warning;
return false;
elsif (Is_X(l) or Is_X(r)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.""<="": metavalue detected, returning FALSE"
severity warning;
return false;
end if;
lresize := resize (l, left_index, right_index);
rresize := resize (r, left_index, right_index);
lslv := to_s (lresize);
rslv := to_s (rresize);
return lslv <= rslv;
end function "<=";
-- overloads of the default maximum and minimum functions
function maximum (l, r : ufixed) return ufixed is
begin
if l > r then return l;
else return r;
end if;
end function maximum;
function maximum (l, r : sfixed) return sfixed is
begin
if l > r then return l;
else return r;
end if;
end function maximum;
function minimum (l, r : ufixed) return ufixed is
begin
if l > r then return r;
else return l;
end if;
end function minimum;
function minimum (l, r : sfixed) return sfixed is
begin
if l > r then return r;
else return l;
end if;
end function minimum;
function to_ufixed (
arg : NATURAL; -- integer
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default
return ufixed is
variable argx : INTEGER;
constant fw : INTEGER := mine (right_index, right_index); -- catch literals
variable result : ufixed (left_index downto fw) := (others => '0');
variable sresult : UNSIGNED (left_index downto 0); -- integer portion
variable bound : NATURAL; -- find the numerical bounds
begin
if (left_index < fw) then
return NAUF;
end if;
if left_index >= 0 then
if (left_index < 30) then
bound := 2**(left_index+1);
else
bound := INTEGER'high;
end if;
end if;
if (arg /= 0) then
if arg >= bound or left_index < 0 then
assert NO_WARNING
report "FIXED_GENERIC_PKG.TO_UFIXED(NATURAL): vector truncated"
severity warning;
if (overflow_style = fixed_wrap) then -- wrap
if bound = 0 then
argx := 0;
else
argx := arg mod bound;
end if;
else -- saturate
return saturate (result'high, result'low);
end if;
else
argx := arg;
end if;
else
return result; -- return zero
end if;
sresult := to_unsigned (argx, sresult'high+1);
result := resize (arg => ufixed (sresult),
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_ufixed;
function to_sfixed (
arg : INTEGER; -- integer
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default
return sfixed is
variable argx : INTEGER;
constant fw : INTEGER := mine (right_index, right_index); -- catch literals
variable result : sfixed (left_index downto fw) := (others => '0');
variable sresult : SIGNED (left_index+1 downto 0); -- integer portion
variable bound : NATURAL := 0;
begin
if (left_index < fw) then -- null range
return NASF;
end if;
if left_index >= 0 then
if (left_index < 30) then
bound := 2**(left_index);
else
bound := INTEGER'high;
end if;
end if;
if (arg /= 0) then
if (arg >= bound or arg < -bound or left_index < 0) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.TO_SFIXED(INTEGER): vector truncated"
severity warning;
if overflow_style = fixed_wrap then -- wrap
if bound = 0 then -- negative integer_range trap
argx := 0;
else -- shift off the top bits
argx := arg rem (bound*2);
end if;
else -- saturate
if arg < 0 then
result := not saturate (result'high, result'low); -- underflow
else
result := saturate (result'high, result'low); -- overflow
end if;
return result;
end if;
else
argx := arg;
end if;
else
return result; -- return zero
end if;
sresult := to_signed (argx, sresult'length);
result := resize (arg => sfixed (sresult),
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_sfixed;
function to_ufixed (
arg : REAL; -- real
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style; -- turn on rounding by default
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return ufixed is
constant fw : INTEGER := mine (right_index, right_index); -- catch literals
variable result : ufixed (left_index downto fw) := (others => '0');
variable Xresult : ufixed (left_index downto fw-guard_bits) := (others => '0');
variable presult : REAL;
variable overflow_needed : BOOLEAN;
begin
-- If negative or null range, return.
if (left_index < fw) then
return NAUF;
end if;
if (arg < 0.0) then
report "FIXED_GENERIC_PKG.TO_UFIXED: Negative argument passed "
& REAL'image(arg) severity error;
return result;
end if;
presult := arg;
if presult >= (2.0**(left_index+1)) then
assert NO_WARNING report "FIXED_GENERIC_PKG.TO_UFIXED(REAL): vector truncated"
severity warning;
overflow_needed := (overflow_style = fixed_saturate);
if overflow_style = fixed_wrap then
presult := presult mod (2.0**(left_index+1)); -- wrap
else
return saturate (result'high, result'low);
end if;
end if;
for i in Xresult'range loop
if presult >= 2.0**i then
Xresult(i) := '1';
presult := presult - 2.0**i;
else
Xresult(i) := '0';
end if;
end loop;
if guard_bits > 0 and round_style = fixed_round then
result := round_fixed (arg => Xresult (left_index
downto right_index),
remainder => Xresult (right_index-1 downto
right_index-guard_bits),
overflow_style => overflow_style);
else
result := Xresult (result'range);
end if;
return result;
end function to_ufixed;
function to_sfixed (
arg : REAL; -- real
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style; -- turn on rounding by default
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return sfixed is
constant fw : INTEGER := mine (right_index, right_index); -- catch literals
variable result : sfixed (left_index downto fw) := (others => '0');
variable Xresult : sfixed (left_index+1 downto fw-guard_bits) := (others => '0');
variable presult : REAL;
begin
if (left_index < fw) then -- null range
return NASF;
end if;
if (arg >= (2.0**left_index) or arg < -(2.0**left_index)) then
assert NO_WARNING report "FIXED_GENERIC_PKG.TO_SFIXED(REAL): vector truncated"
severity warning;
if overflow_style = fixed_saturate then
if arg < 0.0 then -- saturate
result := not saturate (result'high, result'low); -- underflow
else
result := saturate (result'high, result'low); -- overflow
end if;
return result;
else
presult := abs(arg) mod (2.0**(left_index+1)); -- wrap
end if;
else
presult := abs(arg);
end if;
for i in Xresult'range loop
if presult >= 2.0**i then
Xresult(i) := '1';
presult := presult - 2.0**i;
else
Xresult(i) := '0';
end if;
end loop;
if arg < 0.0 then
Xresult := to_fixed(-to_s(Xresult), Xresult'high, Xresult'low);
end if;
if guard_bits > 0 and round_style then
result := round_fixed (arg => Xresult (left_index
downto right_index),
remainder => Xresult (right_index-1 downto
right_index-guard_bits),
overflow_style => overflow_style);
else
result := Xresult (result'range);
end if;
return result;
end function to_sfixed;
function to_ufixed (
arg : UNSIGNED; -- unsigned
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default
return ufixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
constant fw : INTEGER := mine (right_index, right_index); -- catch literals
variable result : ufixed (left_index downto fw);
begin
if arg'length < 1 or (left_index < fw) then
return NAUF;
end if;
result := resize (arg => ufixed (XARG),
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_ufixed;
-- casted version
function to_ufixed (
arg : UNSIGNED) -- unsigned
return ufixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : UNSIGNED(ARG_LEFT downto 0) is ARG;
begin
if arg'length < 1 then
return NAUF;
end if;
return ufixed(xarg);
end function to_ufixed;
function to_sfixed (
arg : SIGNED; -- signed
constant left_index : INTEGER; -- size of integer portion
constant right_index : INTEGER := 0; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default
return sfixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;
constant fw : INTEGER := mine (right_index, right_index); -- catch literals
variable result : sfixed (left_index downto fw);
begin
if arg'length < 1 or (left_index < fw) then
return NASF;
end if;
result := resize (arg => sfixed (XARG),
left_index => left_index,
right_index => right_index,
round_style => round_style,
overflow_style => overflow_style);
return result;
end function to_sfixed;
-- casted version
function to_sfixed (
arg : SIGNED) -- signed
return sfixed is
constant ARG_LEFT : INTEGER := ARG'length-1;
alias XARG : SIGNED(ARG_LEFT downto 0) is ARG;
begin
if arg'length < 1 then
return NASF;
end if;
return sfixed(xarg);
end function to_sfixed;
function add_sign (arg : ufixed) return sfixed is
variable result : sfixed (arg'high+1 downto arg'low);
begin
if arg'length < 1 then
return NASF;
end if;
result (arg'high downto arg'low) := sfixed(cleanvec(arg));
result (arg'high+1) := '0';
return result;
end function add_sign;
-- Because of the farily complicated sizing rules in the fixed point
-- packages these functions are provided to compute the result ranges
-- Example:
-- signal uf1 : ufixed (3 downto -3);
-- signal uf2 : ufixed (4 downto -2);
-- signal uf1multuf2 : ufixed (ufixed_high (3, -3, '*', 4, -2) downto
-- ufixed_low (3, -3, '*', 4, -2));
-- uf1multuf2 <= uf1 * uf2;
-- Valid characters: '+', '-', '*', '/', 'r' or 'R' (rem), 'm' or 'M' (mod),
-- '1' (reciprocal), 'A', 'a' (abs), 'N', 'n' (-sfixed)
function ufixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return maximum (left_index, left_index2) + 1;
when '*' => return left_index + left_index2 + 1;
when '/' => return left_index - right_index2;
when '1' => return -right_index; -- reciprocal
when 'R'|'r' => return mins (left_index, left_index2); -- "rem"
when 'M'|'m' => return mins (left_index, left_index2); -- "mod"
when others => return left_index; -- For abs and default
end case;
end function ufixed_high;
function ufixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return mins (right_index, right_index2);
when '*' => return right_index + right_index2;
when '/' => return right_index - left_index2 - 1;
when '1' => return -left_index - 1; -- reciprocal
when 'R'|'r' => return mins (right_index, right_index2); -- "rem"
when 'M'|'m' => return mins (right_index, right_index2); -- "mod"
when others => return right_index; -- for abs and default
end case;
end function ufixed_low;
function sfixed_high (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return maximum (left_index, left_index2) + 1;
when '*' => return left_index + left_index2 + 1;
when '/' => return left_index - right_index2 + 1;
when '1' => return -right_index + 1; -- reciprocal
when 'R'|'r' => return mins (left_index, left_index2); -- "rem"
when 'M'|'m' => return left_index2; -- "mod"
when 'A'|'a' => return left_index + 1; -- "abs"
when 'N'|'n' => return left_index + 1; -- -sfixed
when others => return left_index;
end case;
end function sfixed_high;
function sfixed_low (left_index, right_index : INTEGER;
operation : CHARACTER := 'X';
left_index2, right_index2 : INTEGER := 0)
return INTEGER is
begin
case operation is
when '+'| '-' => return mins (right_index, right_index2);
when '*' => return right_index + right_index2;
when '/' => return right_index - left_index2;
when '1' => return -left_index; -- reciprocal
when 'R'|'r' => return mins (right_index, right_index2); -- "rem"
when 'M'|'m' => return mins (right_index, right_index2); -- "mod"
when others => return right_index; -- default for abs, neg and default
end case;
end function sfixed_low;
-- Same as above, but using the "size_res" input only for their ranges:
-- signal uf1multuf2 : ufixed (ufixed_high (uf1, '*', uf2) downto
-- ufixed_low (uf1, '*', uf2));
-- uf1multuf2 <= uf1 * uf2;
function ufixed_high (size_res : ufixed;
operation : CHARACTER := 'X';
size_res2 : ufixed)
return INTEGER is
begin
return ufixed_high (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function ufixed_high;
function ufixed_low (size_res : ufixed;
operation : CHARACTER := 'X';
size_res2 : ufixed)
return INTEGER is
begin
return ufixed_low (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function ufixed_low;
function sfixed_high (size_res : sfixed;
operation : CHARACTER := 'X';
size_res2 : sfixed)
return INTEGER is
begin
return sfixed_high (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function sfixed_high;
function sfixed_low (size_res : sfixed;
operation : CHARACTER := 'X';
size_res2 : sfixed)
return INTEGER is
begin
return sfixed_low (left_index => size_res'high,
right_index => size_res'low,
operation => operation,
left_index2 => size_res2'high,
right_index2 => size_res2'low);
end function sfixed_low;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed is
constant sat : ufixed (left_index downto right_index) := (others => '1');
begin
return sat;
end function saturate;
-- purpose: returns a saturated number
function saturate (
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed is
variable sat : sfixed (left_index downto right_index) := (others => '1');
begin
-- saturate positive, to saturate negative, just do "not saturate()"
sat (left_index) := '0';
return sat;
end function saturate;
function saturate (
size_res : ufixed) -- only the size of this is used
return ufixed is
begin
return saturate (size_res'high, size_res'low);
end function saturate;
function saturate (
size_res : sfixed) -- only the size of this is used
return sfixed is
begin
return saturate (size_res'high, size_res'low);
end function saturate;
-- As a concession to those who use a graphical DSP environment,
-- these functions take parameters in those tools format and create
-- fixed point numbers. These functions are designed to convert from
-- a std_logic_vector to the VHDL fixed point format using the conventions
-- of these packages. In a pure VHDL environment you should use the
-- "to_ufixed" and "to_sfixed" routines.
-- Unsigned fixed point
function to_UFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return ufixed is
variable result : ufixed (width-fraction-1 downto -fraction);
begin
if (arg'length /= result'length) then
report "FIXED_GENERIC_PKG.TO_UFIX (STD_LOGIC_VECTOR) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NAUF;
else
result := to_ufixed (arg, result'high, result'low);
return result;
end if;
end function to_UFix;
-- signed fixed point
function to_SFix (
arg : STD_LOGIC_VECTOR;
width : NATURAL; -- width of vector
fraction : NATURAL) -- width of fraction
return sfixed is
variable result : sfixed (width-fraction-1 downto -fraction);
begin
if (arg'length /= result'length) then
report "FIXED_GENERIC_PKG.TO_SFIX (STD_LOGIC_VECTOR) "
& "Vector lengths do not match. Input length is "
& INTEGER'image(arg'length) & " and output will be "
& INTEGER'image(result'length) & " wide."
severity error;
return NASF;
else
result := to_sfixed (arg, result'high, result'low);
return result;
end if;
end function to_SFix;
-- finding the bounds of a number. These functions can be used like this:
-- signal xxx : ufixed (7 downto -3);
-- -- Which is the same as "ufixed (UFix_high (11,3) downto UFix_low(11,3))"
-- signal yyy : ufixed (UFix_high (11, 3, "+", 11, 3)
-- downto UFix_low(11, 3, "+", 11, 3));
-- Where "11" is the width of xxx (xxx'length),
-- and 3 is the lower bound (abs (xxx'low))
-- In a pure VHDL environment use "ufixed_high" and "ufixed_low"
function ufix_high (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return ufixed_high (left_index => width - 1 - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - 1 - fraction2,
right_index2 => -fraction2);
end function ufix_high;
function ufix_low (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return ufixed_low (left_index => width - 1 - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - 1 - fraction2,
right_index2 => -fraction2);
end function ufix_low;
function sfix_high (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return sfixed_high (left_index => width - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - fraction2,
right_index2 => -fraction2);
end function sfix_high;
function sfix_low (
width, fraction : NATURAL;
operation : CHARACTER := 'X';
width2, fraction2 : NATURAL := 0)
return INTEGER is
begin
return sfixed_low (left_index => width - fraction,
right_index => -fraction,
operation => operation,
left_index2 => width2 - fraction2,
right_index2 => -fraction2);
end function sfix_low;
function to_unsigned (
arg : ufixed; -- ufixed point input
constant size : NATURAL; -- length of output
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return UNSIGNED is
begin
return to_uns(resize (arg => arg,
left_index => size-1,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
end function to_unsigned;
function to_unsigned (
arg : ufixed; -- ufixed point input
size_res : UNSIGNED; -- length of output
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return UNSIGNED is
begin
return to_unsigned (arg => arg,
size => size_res'length,
round_style => round_style,
overflow_style => overflow_style);
end function to_unsigned;
function to_signed (
arg : sfixed; -- ufixed point input
constant size : NATURAL; -- length of output
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return SIGNED is
begin
return to_s(resize (arg => arg,
left_index => size-1,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
end function to_signed;
function to_signed (
arg : sfixed; -- ufixed point input
size_res : SIGNED; -- used for length of output
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return SIGNED is
begin
return to_signed (arg => arg,
size => size_res'length,
round_style => round_style,
overflow_style => overflow_style);
end function to_signed;
function to_real (
arg : ufixed) -- ufixed point input
return REAL is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable result : REAL; -- result
variable arg_int : ufixed (left_index downto right_index);
begin
if (arg'length < 1) then
return 0.0;
end if;
arg_int := cleanvec(arg);
if (Is_X(arg_int)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.TO_REAL: metavalue detected, returning 0.0"
severity warning;
return 0.0;
end if;
result := 0.0;
for i in arg_int'range loop
if (arg_int(i) = '1') then
result := result + (2.0**i);
end if;
end loop;
return result;
end function to_real;
function to_real (
arg : sfixed) -- ufixed point input
return REAL is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable result : REAL; -- result
variable arg_int : sfixed (left_index downto right_index);
-- unsigned version of argument
variable arg_uns : ufixed (left_index downto right_index);
-- absolute of argument
begin
if (arg'length < 1) then
return 0.0;
end if;
arg_int := cleanvec(arg);
if (Is_X(arg_int)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.TO_REAL: metavalue detected, returning 0.0"
severity warning;
return 0.0;
end if;
arg_uns := abs(arg_int);
result := to_real (arg_uns);
if (arg_int(arg_int'high) = '1') then
result := -result;
end if;
return result;
end function to_real;
function to_integer (
arg : ufixed; -- fixed point input
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return NATURAL is
constant left_index : INTEGER := arg'high;
variable arg_uns : UNSIGNED (minimum(31, left_index+1) downto 0)
:= (others => '0');
begin
if (arg'length < 1) then
return 0;
end if;
if (Is_X (arg)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.TO_INTEGER: metavalue detected, returning 0"
severity warning;
return 0;
end if;
if (left_index < -1) then
return 0;
end if;
arg_uns := to_uns(resize (arg => arg,
left_index => arg_uns'high,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
return to_integer (arg_uns);
end function to_integer;
function to_integer (
arg : sfixed; -- fixed point input
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- rounding by default
return INTEGER is
constant left_index : INTEGER := arg'high;
constant right_index : INTEGER := arg'low;
variable arg_s : SIGNED (minimum(31, left_index+1) downto 0);
begin
if (arg'length < 1) then
return 0;
end if;
if (Is_X (arg)) then
assert NO_WARNING
report "FIXED_GENERIC_PKG.TO_INTEGER: metavalue detected, returning 0"
severity warning;
return 0;
end if;
if (left_index < -1) then
return 0;
end if;
arg_s := to_s(resize (arg => arg,
left_index => arg_s'high,
right_index => 0,
round_style => round_style,
overflow_style => overflow_style));
return to_integer (arg_s);
end function to_integer;
function to_01 (
s : ufixed; -- ufixed point input
constant XMAP : STD_LOGIC := '0') -- Map x to
return ufixed is
variable result : ufixed (s'range); -- result
begin
for i in s'range loop
case s(i) is
when '0' | 'L' => result(i) := '0';
when '1' | 'H' => result(i) := '1';
when others => result(i) := XMAP;
end case;
end loop;
return result;
end function to_01;
function to_01 (
s : sfixed; -- ufixed point input
constant XMAP : STD_LOGIC := '0') -- Map x to
return sfixed is
variable result : sfixed (s'range);
begin
for i in s'range loop
case s(i) is
when '0' | 'L' => result(i) := '0';
when '1' | 'H' => result(i) := '1';
when others => result(i) := XMAP;
end case;
end loop;
return result;
end function to_01;
function Is_X (
arg : ufixed)
return BOOLEAN is
variable argslv : STD_LOGIC_VECTOR (arg'length-1 downto 0); -- slv
begin
argslv := to_slv(arg);
return Is_X(argslv);
end function Is_X;
function Is_X (
arg : sfixed)
return BOOLEAN is
variable argslv : STD_LOGIC_VECTOR (arg'length-1 downto 0); -- slv
begin
argslv := to_slv(arg);
return Is_X(argslv);
end function Is_X;
function To_X01 (
arg : ufixed)
return ufixed is
begin
return to_ufixed (To_X01(to_slv(arg)), arg'high, arg'low);
end function To_X01;
function to_X01 (
arg : sfixed)
return sfixed is
begin
return to_sfixed (To_X01(to_slv(arg)), arg'high, arg'low);
end function To_X01;
function To_X01Z (
arg : ufixed)
return ufixed is
begin
return to_ufixed (To_X01Z(to_slv(arg)), arg'high, arg'low);
end function To_X01Z;
function to_X01Z (
arg : sfixed)
return sfixed is
begin
return to_sfixed (To_X01Z(to_slv(arg)), arg'high, arg'low);
end function To_X01Z;
function To_UX01 (
arg : ufixed)
return ufixed is
begin
return to_ufixed (To_UX01(to_slv(arg)), arg'high, arg'low);
end function To_UX01;
function to_UX01 (
arg : sfixed)
return sfixed is
begin
return to_sfixed (To_UX01(to_slv(arg)), arg'high, arg'low);
end function To_UX01;
function resize (
arg : ufixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow
constant round_style : BOOLEAN := fixed_round_style) -- rounding
return ufixed is
constant arghigh : INTEGER := maximum (arg'high, arg'low);
constant arglow : INTEGER := mine (arg'high, arg'low);
variable invec : ufixed (arghigh downto arglow);
variable result : ufixed(left_index downto right_index) :=
(others => '0');
variable needs_rounding : BOOLEAN := false;
begin -- resize
if (arg'length < 1) or (result'length < 1) then
return NAUF;
elsif (invec'length < 1) then
return result; -- string literal value
else
invec := cleanvec(arg);
if (right_index > arghigh) then -- return top zeros
needs_rounding := (round_style = fixed_round) and
(right_index = arghigh+1);
elsif (left_index < arglow) then -- return overflow
if (overflow_style = fixed_saturate) and
(or_reducex(to_slv(invec)) = '1') then
result := saturate (result'high, result'low); -- saturate
end if;
elsif (arghigh > left_index) then
-- wrap or saturate?
if (overflow_style and
or_reducex(to_slv(invec(arghigh downto left_index+1))) = '1')
then
result := saturate (result'high, result'low); -- saturate
else
if (arglow >= right_index) then
result (left_index downto arglow) :=
invec(left_index downto arglow);
else
result (left_index downto right_index) :=
invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
end if;
else -- arghigh <= integer width
if (arglow >= right_index) then
result (arghigh downto arglow) := invec;
else
result (arghigh downto right_index) :=
invec (arghigh downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
end if;
-- Round result
if needs_rounding then
result := round_fixed (arg => result,
remainder => invec (right_index-1
downto arglow),
overflow_style => overflow_style);
end if;
return result;
end if;
end function resize;
function resize (
arg : sfixed; -- input
constant left_index : INTEGER; -- integer portion
constant right_index : INTEGER; -- size of fraction
constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow
constant round_style : BOOLEAN := fixed_round_style) -- rounding
return sfixed is
constant arghigh : INTEGER := maximum (arg'high, arg'low);
constant arglow : INTEGER := mine (arg'high, arg'low);
variable invec : sfixed (arghigh downto arglow);
variable result : sfixed(left_index downto right_index) :=
(others => '0');
variable reduced : STD_ULOGIC;
variable needs_rounding : BOOLEAN := false; -- rounding
begin -- resize
if (arg'length < 1) or (result'length < 1) then
return NASF;
elsif (invec'length < 1) then
return result; -- string literal value
else
invec := cleanvec(arg);
if (right_index > arghigh) then -- return top zeros
if (arg'low /= INTEGER'low) then -- check for a literal
result := (others => arg(arghigh)); -- sign extend
end if;
needs_rounding := (round_style = fixed_round) and
(right_index = arghigh+1);
elsif (left_index < arglow) then -- return overflow
if (overflow_style) then
reduced := or_reducex(to_slv(invec));
if (reduced = '1') then
if (invec(arghigh) = '0') then
-- saturate POSITIVE
result := saturate (result'high, result'low);
else
-- saturate negative
result := not saturate (result'high, result'low);
end if;
-- else return 0 (input was 0)
end if;
-- else return 0 (wrap)
end if;
elsif (arghigh > left_index) then
if (invec(arghigh) = '0') then
reduced := or_reducex(to_slv(invec(arghigh-1 downto
left_index)));
if overflow_style and reduced = '1' then
-- saturate positive
result := saturate (result'high, result'low);
else
if (right_index > arglow) then
result := invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round);
else
result (left_index downto arglow) :=
invec (left_index downto arglow);
end if;
end if;
else
reduced := and_reducex(to_slv(invec(arghigh-1 downto
left_index)));
if overflow_style and reduced = '0' then
result := not saturate (result'high, result'low);
else
if (right_index > arglow) then
result := invec (left_index downto right_index);
needs_rounding := (round_style = fixed_round);
else
result (left_index downto arglow) :=
invec (left_index downto arglow);
end if;
end if;
end if;
else -- arghigh <= integer width
if (arglow >= right_index) then
result (arghigh downto arglow) := invec;
else
result (arghigh downto right_index) :=
invec (arghigh downto right_index);
needs_rounding := (round_style = fixed_round); -- round
end if;
if (left_index > arghigh) then -- sign extend
result(left_index downto arghigh+1) := (others => invec(arghigh));
end if;
end if;
-- Round result
if (needs_rounding) then
result := round_fixed (arg => result,
remainder => invec (right_index-1
downto arglow),
overflow_style => overflow_style);
end if;
return result;
end if;
end function resize;
-- size_res functions
-- These functions compute the size from a passed variable named "size_res"
-- The only part of this variable used it it's size, it is never passed
-- to a lower level routine.
function to_ufixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : ufixed) -- for size only
return ufixed is
variable result : ufixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : STD_LOGIC_VECTOR; -- shifted vector
size_res : sfixed) -- for size only
return sfixed is
variable result : sfixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : ufixed) -- for size only
return ufixed is
variable result : ufixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_ufixed (arg => to_stdlogicvector(arg),
left_index => size_res'high,
right_index => size_res'low);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : STD_ULOGIC_VECTOR; -- shifted vector
size_res : sfixed) -- for size only
return sfixed is
variable result : sfixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_sfixed (arg => to_stdlogicvector(arg),
left_index => size_res'high,
right_index => size_res'low);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : NATURAL; -- integer
size_res : ufixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default
return ufixed is
variable result : ufixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : INTEGER; -- integer
size_res : sfixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default
return sfixed is
variable result : sfixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : REAL; -- real
size_res : ufixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style; -- turn on rounding by default
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return ufixed is
variable result : ufixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
guard_bits => guard_bits,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : REAL; -- real
size_res : sfixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style; -- turn on rounding by default
constant guard_bits : NATURAL := fixed_guard_bits) -- # of guard bits
return sfixed is
variable result : sfixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
guard_bits => guard_bits,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function to_ufixed (
arg : UNSIGNED; -- unsigned
size_res : ufixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow
constant round_style : BOOLEAN := fixed_round_style) -- rounding
return ufixed is
variable result : ufixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_ufixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_ufixed;
function to_sfixed (
arg : SIGNED; -- signed
size_res : sfixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- saturate by default
constant round_style : BOOLEAN := fixed_round_style) -- turn on rounding by default
return sfixed is
variable result : sfixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := to_sfixed (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function to_sfixed;
function resize (
arg : ufixed; -- input
size_res : ufixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow
constant round_style : BOOLEAN := fixed_round_style) -- rounding
return ufixed is
variable result : ufixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := resize (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function resize;
function resize (
arg : sfixed; -- input
size_res : sfixed; -- for size only
constant overflow_style : BOOLEAN := fixed_overflow_style; -- overflow
constant round_style : BOOLEAN := fixed_round_style) -- rounding
return sfixed is
variable result : sfixed (size_res'left downto size_res'right);
begin
if (result'length < 1) then
return result;
else
result := resize (arg => arg,
left_index => size_res'high,
right_index => size_res'low,
round_style => round_style,
overflow_style => overflow_style);
return result;
end if;
end function resize;
-- Overloaded functions
function "+" (
l : ufixed; -- fixed point input
r : REAL)
return ufixed is
begin
return (l +
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "+";
function "+" (
l : REAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
+ r);
end function "+";
function "+" (
l : sfixed; -- fixed point input
r : REAL)
return sfixed is
begin
return (l +
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "+";
function "+" (
l : REAL;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
+ r);
end function "+";
-- Overloaded functions
function "-" (
l : ufixed; -- fixed point input
r : REAL)
return ufixed is
begin
return (l -
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "-";
function "-" (
l : REAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
- r);
end function "-";
function "-" (
l : sfixed; -- fixed point input
r : REAL)
return sfixed is
begin
return (l -
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "-";
function "-" (
l : REAL;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
- r);
end function "-";
-- Overloaded functions
function "*" (
l : ufixed; -- fixed point input
r : REAL)
return ufixed is
begin
return (l *
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "*";
function "*" (
l : REAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
* r);
end function "*";
function "*" (
l : sfixed; -- fixed point input
r : REAL)
return sfixed is
begin
return (l *
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "*";
function "*" (
l : REAL;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
* r);
end function "*";
-- Overloaded functions
function "/" (
l : ufixed; -- fixed point input
r : REAL)
return ufixed is
begin
return (l /
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "/";
function "/" (
l : REAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
/ r);
end function "/";
function "/" (
l : sfixed; -- fixed point input
r : REAL)
return sfixed is
begin
return (l /
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "/";
function "/" (
l : REAL;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
/ r);
end function "/";
-- Overloaded functions
function "rem" (
l : ufixed; -- fixed point input
r : REAL)
return ufixed is
begin
return (l rem
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "rem";
function "rem" (
l : REAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
rem r);
end function "rem";
function "rem" (
l : sfixed; -- fixed point input
r : REAL)
return sfixed is
begin
return (l rem
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "rem";
function "rem" (
l : REAL;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
rem r);
end function "rem";
function "mod" (
l : ufixed; -- fixed point input
r : REAL)
return ufixed is
begin
return (l mod
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "mod";
function "mod" (
l : REAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
mod r);
end function "mod";
function "mod" (
l : sfixed; -- fixed point input
r : REAL)
return sfixed is
begin
return (l mod
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "mod";
function "mod" (
l : REAL;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
mod r);
end function "mod";
-- Overloaded functions for integers
function "+" (
l : ufixed; -- fixed point input
r : NATURAL)
return ufixed is
begin
return (l + to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)); -- rounding not needed
end function "+";
function "+" (
l : NATURAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
+ r);
end function "+";
function "+" (
l : sfixed; -- fixed point input
r : INTEGER)
return sfixed is
begin
return (l + to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "+";
function "+" (
l : INTEGER;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
+ r);
end function "+";
-- Overloaded functions
function "-" (
l : ufixed; -- fixed point input
r : NATURAL)
return ufixed is
begin
return (l - to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "-";
function "-" (
l : NATURAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
- r);
end function "-";
function "-" (
l : sfixed; -- fixed point input
r : INTEGER)
return sfixed is
begin
return (l - to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "-";
function "-" (
l : INTEGER;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
- r);
end function "-";
-- Overloaded functions
function "*" (
l : ufixed; -- fixed point input
r : NATURAL)
return ufixed is
begin
return (l * to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "*";
function "*" (
l : NATURAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
* r);
end function "*";
function "*" (
l : sfixed; -- fixed point input
r : INTEGER)
return sfixed is
begin
return (l * to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "*";
function "*" (
l : INTEGER;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
* r);
end function "*";
-- Overloaded functions
function "/" (
l : ufixed; -- fixed point input
r : NATURAL)
return ufixed is
begin
return (l / to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "/";
function "/" (
l : NATURAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
/ r);
end function "/";
function "/" (
l : sfixed; -- fixed point input
r : INTEGER)
return sfixed is
begin
return (l / to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "/";
function "/" (
l : INTEGER;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
/ r);
end function "/";
-- Overloaded functions
function "rem" (
l : ufixed; -- fixed point input
r : NATURAL)
return ufixed is
begin
return (l rem to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "rem";
function "rem" (
l : NATURAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
rem r);
end function "rem";
function "rem" (
l : sfixed; -- fixed point input
r : INTEGER)
return sfixed is
begin
return (l rem to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "rem";
function "rem" (
l : INTEGER;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
rem r);
end function "rem";
function "mod" (
l : ufixed; -- fixed point input
r : NATURAL)
return ufixed is
begin
return (l mod to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "mod";
function "mod" (
l : NATURAL;
r : ufixed) -- fixed point input
return ufixed is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
mod r);
end function "mod";
function "mod" (
l : sfixed; -- fixed point input
r : INTEGER)
return sfixed is
begin
return (l mod to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "mod";
function "mod" (
l : INTEGER;
r : sfixed) -- fixed point input
return sfixed is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
mod r);
end function "mod";
-- overloaded compare functions
function "=" (
l : ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l = to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "=";
function "/=" (
l : ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l /= to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "/=";
function ">=" (
l : ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l >= to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function ">=";
function "<=" (
l : ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l <= to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "<=";
function ">" (
l : ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l > to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function ">";
function "<" (
l : ufixed;
r : NATURAL) -- fixed point input
return BOOLEAN is
begin
return (l < to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "<";
function "=" (
l : NATURAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
= r);
end function "=";
function "/=" (
l : NATURAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
/= r);
end function "/=";
function ">=" (
l : NATURAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
>= r);
end function ">=";
function "<=" (
l : NATURAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
<= r);
end function "<=";
function ">" (
l : NATURAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
> r);
end function ">";
function "<" (
l : NATURAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
< r);
end function "<";
function "=" (
l : ufixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l =
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "=";
function "/=" (
l : ufixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l /=
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "/=";
function ">=" (
l : ufixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l >=
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function ">=";
function "<=" (
l : ufixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l <=
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "<=";
function ">" (
l : ufixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l >
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function ">";
function "<" (
l : ufixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l <
to_ufixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "<";
function "=" (
l : REAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
= r);
end function "=";
function "/=" (
l : REAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
/= r);
end function "/=";
function ">=" (
l : REAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
>= r);
end function ">=";
function "<=" (
l : REAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
<= r);
end function "<=";
function ">" (
l : REAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
> r);
end function ">";
function "<" (
l : REAL;
r : ufixed) -- fixed point input
return BOOLEAN is
begin
return (to_ufixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
< r);
end function "<";
function "=" (
l : sfixed;
r : INTEGER) -- fixed point input
return BOOLEAN is
begin
return (l = to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "=";
function "/=" (
l : sfixed;
r : INTEGER) -- fixed point input
return BOOLEAN is
begin
return (l /= to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "/=";
function ">=" (
l : sfixed;
r : INTEGER) -- fixed point input
return BOOLEAN is
begin
return (l >= to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function ">=";
function "<=" (
l : sfixed;
r : INTEGER) -- fixed point input
return BOOLEAN is
begin
return (l <= to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "<=";
function ">" (
l : sfixed;
r : INTEGER) -- fixed point input
return BOOLEAN is
begin
return (l > to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function ">";
function "<" (
l : sfixed;
r : INTEGER) -- fixed point input
return BOOLEAN is
begin
return (l < to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style));
end function "<";
function "=" (
l : INTEGER;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
= r);
end function "=";
function "/=" (
l : INTEGER;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
/= r);
end function "/=";
function ">=" (
l : INTEGER;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
>= r);
end function ">=";
function "<=" (
l : INTEGER;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
<= r);
end function "<=";
function ">" (
l : INTEGER;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
> r);
end function ">";
function "<" (
l : INTEGER;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style)
< r);
end function "<";
function "=" (
l : sfixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l =
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "=";
function "/=" (
l : sfixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l /=
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "/=";
function ">=" (
l : sfixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l >=
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function ">=";
function "<=" (
l : sfixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l <=
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "<=";
function ">" (
l : sfixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l >
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function ">";
function "<" (
l : sfixed;
r : REAL) -- fixed point input
return BOOLEAN is
begin
return (l <
to_sfixed (arg => r,
left_index => l'high,
right_index => l'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits));
end function "<";
function "=" (
l : REAL;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
= r);
end function "=";
function "/=" (
l : REAL;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
/= r);
end function "/=";
function ">=" (
l : REAL;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
>= r);
end function ">=";
function "<=" (
l : REAL;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
<= r);
end function "<=";
function ">" (
l : REAL;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
> r);
end function ">";
function "<" (
l : REAL;
r : sfixed) -- fixed point input
return BOOLEAN is
begin
return (to_sfixed (arg => l,
left_index => r'high,
right_index => r'low,
overflow_style => fixed_overflow_style,
round_style => fixed_round_style,
guard_bits => fixed_guard_bits)
< r);
end function "<";
-- rtl_synthesis off
-- synthesis translate_off
-- copied from std_logic_textio
type MVL9plus is ('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-', error);
type char_indexed_by_MVL9 is array (STD_ULOGIC) of CHARACTER;
type MVL9_indexed_by_char is array (CHARACTER) of STD_ULOGIC;
type MVL9plus_indexed_by_char is array (CHARACTER) of MVL9plus;
constant MVL9_to_char : char_indexed_by_MVL9 := "UX01ZWLH-";
constant char_to_MVL9 : MVL9_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => 'U');
constant char_to_MVL9plus : MVL9plus_indexed_by_char :=
('U' => 'U', 'X' => 'X', '0' => '0', '1' => '1', 'Z' => 'Z',
'W' => 'W', 'L' => 'L', 'H' => 'H', '-' => '-', others => error);
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
constant NUS : STRING(2 to 1) := (others => ' ');
-- purpose: writes fixed point into a line
procedure write (
L : inout LINE; -- input line
VALUE : in ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to value'length +1) := (others => ' ');
variable sindx : INTEGER;
begin -- function write Example: 0011.1100
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx +1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx +1;
end loop;
write(l, s, justified, field);
end procedure write;
-- purpose: writes fixed point into a line
procedure write (
L : inout LINE; -- input line
VALUE : in sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
variable s : STRING(1 to value'length +1);
variable sindx : INTEGER;
begin -- function write Example: 0011.1100
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx +1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx +1;
end loop;
write(l, s, justified, field);
end procedure write;
procedure READ(L : inout LINE;
VALUE : out ufixed) is
-- Possible data: 00000.0000000
-- 000000000000
variable c : CHARACTER;
variable s : STRING(1 to value'length-1);
variable readOk : BOOLEAN;
variable i : INTEGER; -- index variable
begin -- READ
VALUE (VALUE'range) := (others => 'U');
loop -- skip white space
read(l, c, readOk);
exit when (readOk = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
i := value'high;
readloop : loop
if readOk = false then -- Bail out if there was a bad read
report "FIXED_GENERIC_PKG.READ(ufixed) "
& "Error: end of string encountered"
severity error;
return;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
assert i = value'low
report "FIXED_GENERIC_PKG.READ(ufixed) "
& "Warning: Value truncated " severity warning;
return;
elsif c = '.' then -- separator, ignore
assert (i = -1)
report "FIXED_GENERIC_PKG.READ(ufixed) "
& "Warning: Decimal point does not match number format "
severity warning;
elsif (char_to_MVL9plus(c) = error) then
report "FIXED_GENERIC_PKG.READ(ufixed) "
& "Error: Character '" & c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
value (i) := char_to_MVL9(c);
i := i - 1;
if i < value'low then
return;
end if;
end if;
read(l, c, readOk);
end loop readloop;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out ufixed;
GOOD : out BOOLEAN) is
-- Possible data: 00000.0000000
-- 000000000000
variable c : CHARACTER;
variable i : INTEGER; -- index variable
variable readOk : BOOLEAN;
begin -- READ
VALUE (VALUE'range) := (others => 'U');
loop -- skip white space
read(l, c, readOk);
exit when (readOk = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
i := value'high;
good := true;
readloop : loop
if readOk = false then -- Bail out if there was a bad read
good := false;
return;
elsif c = ' ' or c = NBSP or c = HT then -- reading done
good := false;
return;
elsif c = '.' then -- separator, ignore
good := (i = -1);
elsif (char_to_MVL9plus(c) = error) then
good := false;
return;
else
value (i) := char_to_MVL9(c);
i := i - 1;
if i < value'low then
return;
end if;
end if;
read(l, c, readOk);
end loop readloop;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out sfixed) is
-- Possible data: 00000.0000000
-- 000000000000
variable c : CHARACTER;
variable readOk : BOOLEAN;
variable i : INTEGER; -- index variable
begin -- READ
VALUE (VALUE'range) := (others => 'U');
loop -- skip white space
read(l, c, readOk);
exit when (readOk = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
i := value'high;
readloop : loop
if readOk = false then -- Bail out if there was a bad read
report "FIXED_GENERIC_PKG.READ(sfixed) "
& "Error end of string encountered"
severity error;
return;
elsif c = ' ' or c = NBSP or c = HT then -- reading done.
assert i = value'low
report "FIXED_GENERIC_PKG.READ(sfixed) "
& "Warning: Value truncated " severity warning;
return;
elsif c = '.' then -- separator, ignore
assert (i = -1)
report "FIXED_GENERIC_PKG.READ(sfixed) "
& "Warning: Decimal point does not match number format "
severity warning;
elsif (char_to_MVL9plus(c) = error) then
report "FIXED_GENERIC_PKG.READ(sfixed) "
& "Error: Character '" & c & "' read, expected STD_ULOGIC literal."
severity error;
return;
else
value (i) := char_to_MVL9(c);
i := i - 1;
if i < value'low then
return;
end if;
end if;
read(l, c, readOk);
end loop readloop;
end procedure READ;
procedure READ(L : inout LINE;
VALUE : out sfixed;
GOOD : out BOOLEAN) is
-- Possible data: 00000.0000000
-- 000000000000
variable c : CHARACTER;
variable i : INTEGER; -- index variable
variable readOk : BOOLEAN;
begin -- READ
VALUE (VALUE'range) := (others => 'U');
loop -- skip white space
read(l, c, readOk);
exit when (readOk = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
i := value'high;
good := true;
readloop : loop
if readOk = false then -- Bail out if there was a bad read
good := false;
return;
elsif c = ' ' or c = NBSP or c = HT then -- reading done
good := false;
return;
elsif c = '.' then -- separator, ignore
good := (i = -1);
elsif (char_to_MVL9plus(c) = error) then
good := false;
return;
else
value (i) := char_to_MVL9(c);
i := i - 1;
if i < value'low then
return;
end if;
end if;
read(l, c, readOk);
end loop readloop;
end procedure READ;
-- octal read and write
procedure owrite (
L : inout LINE; -- input line
VALUE : in ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_ostring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure owrite;
procedure owrite (
L : inout LINE; -- input line
VALUE : in sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_ostring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure owrite;
procedure Char2TriBits (C : CHARACTER;
RESULT : out STD_LOGIC_VECTOR(2 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := o"0"; good := true;
when '1' => result := o"1"; good := true;
when '2' => result := o"2"; good := true;
when '3' => result := o"3"; good := true;
when '4' => result := o"4"; good := true;
when '5' => result := o"5"; good := true;
when '6' => result := o"6"; good := true;
when '7' => result := o"7"; good := true;
when 'Z' => result := "ZZZ"; good := true;
when 'X' => result := "XXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"FIXED_GENERIC_PKG.OREAD Error: Read a '" & c &
"', expected an Octal character (0-7)."
severity error;
result := "UUU";
good := false;
end case;
end procedure Char2TriBits;
-- Note that for Octal and Hex read, you can not start with a ".",
-- the read is for numbers formatted "A.BC". These routines go to
-- the nearest bounds, so "F.E" will fit into an sfixed (2 downto -3).
procedure OREAD(L : inout LINE;
VALUE : out ufixed) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(-3, VALUE'low)-2)/3)*3;
variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable c : CHARACTER; -- to read the "."
variable valuex : ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
variable i : INTEGER;
begin
VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
loop -- skip white space
read(L, c, igood);
exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
if igood = false then
report "FIXED_GENERIC_PKG.OREAD(ufixed): "
& "Error end of string encountered"
severity error;
return;
else
Char2triBits(c, nybble, igood, true);
i := hbv-lbv - 3; -- Top - 3
slv (hbv-lbv downto i+1) := nybble;
end if;
while (i /= -1) and igood and L.all'length /= 0 loop
read (L, c, igood);
if igood = false then
report "FIXED_GENERIC_PKG.OREAD(ufixed): "
& "Error end of string encountered"
severity error;
elsif (c = '.') then
if (i + 1 /= -lbv) then
igood := false;
report "FIXED_GENERIC_PKG.OREAD(ufixed): "
& "encountered ""."" at wrong index"
severity error;
end if;
else
Char2TriBits(c, nybble, igood, true);
slv (i downto i-2) := nybble;
i := i - 3;
end if;
end loop;
if igood then -- We did not get another error
assert (i = -1) and -- We read everything, and high bits 0
(or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')
report "FIXED_GENERIC_PKG.OREAD(ufixed): Vector truncated."
severity error;
if (or_reducex(slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report "FIXED_GENERIC_PKG.OREAD(ufixed): Vector truncated"
severity warning;
end if;
end if;
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out ufixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(-3, VALUE'low)-2)/3)*3;
variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable c : CHARACTER; -- to read the "."
variable valuex : ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
variable i : INTEGER;
begin
VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
loop -- skip white space
read(L, c, igood);
exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
if igood = false then
return;
else
Char2triBits(c, nybble, igood, false);
i := hbv-lbv - 3; -- Top - 3
slv (hbv-lbv downto i+1) := nybble;
end if;
while (i /= -1) and igood and L.all'length /= 0 loop
read (L, c, igood);
if igood then
if (c = '.') then
igood := igood and (i + 1 = -lbv);
else
Char2TriBits(c, nybble, igood, false);
slv (i downto i-2) := nybble;
i := i - 3;
end if;
end if;
end loop;
good := igood and -- We did not get another error
(i = -1) and -- We read everything, and high bits 0
(or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0');
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out sfixed) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(-3, VALUE'low)-2)/3)*3;
variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable c : CHARACTER; -- to read the "."
variable valuex : sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
variable i : INTEGER;
begin
VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
loop -- skip white space
read(L, c, igood);
exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
if igood = false then
report "FIXED_GENERIC_PKG.OREAD(sfixed): "
& "Error end of string encountered"
severity error;
return;
else
Char2triBits(c, nybble, igood, true);
i := hbv-lbv - 3; -- Top - 3
slv (hbv-lbv downto i+1) := nybble;
end if;
while (i /= -1) and igood and L.all'length /= 0 loop
read (L, c, igood);
if igood = false then
report "FIXED_GENERIC_PKG.OREAD(sfixed): "
& "Error end of string encountered"
severity error;
elsif (c = '.') then
if (i + 1 /= -lbv) then
igood := false;
report "FIXED_GENERIC_PKG.OREAD(sfixed): "
& "encountered ""."" at wrong index"
severity error;
end if;
else
Char2TriBits(c, nybble, igood, true);
slv (i downto i-2) := nybble;
i := i - 3;
end if;
end loop;
if igood then -- We did not get another error
assert (i = -1) and -- We read everything
((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))
report "FIXED_GENERIC_PKG.OREAD(sfixed): Vector truncated."
severity error;
if (or_reducex(slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report "FIXED_GENERIC_PKG.OREAD(sfixed): Vector truncated"
severity warning;
end if;
end if;
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end procedure OREAD;
procedure OREAD(L : inout LINE;
VALUE : out sfixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(3, (VALUE'high+1))+2)/3)*3)-1;
constant lbv : INTEGER := ((mine(-3, VALUE'low)-2)/3)*3;
variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable c : CHARACTER; -- to read the "."
variable valuex : sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (2 downto 0); -- 3 bits
variable i : INTEGER;
begin
VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
loop -- skip white space
read(L, c, igood);
exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
if igood = false then
return;
else
Char2triBits(c, nybble, igood, false);
i := hbv-lbv - 3; -- Top - 3
slv (hbv-lbv downto i+1) := nybble;
end if;
while (i /= -1) and igood and L.all'length /= 0 loop
read (L, c, igood);
if igood then
if (c = '.') then
igood := igood and (i + 1 = -lbv);
else
Char2TriBits(c, nybble, igood, false);
slv (i downto i-2) := nybble;
i := i - 3;
end if;
end if;
end loop;
good := igood -- We did not get another error
and (i = -1) -- We read everything
and ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'));
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end procedure OREAD;
-- hex read and write
procedure hwrite (
L : inout LINE; -- input line
VALUE : in ufixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_hstring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure hwrite;
-- purpose: writes fixed point into a line
procedure hwrite (
L : inout LINE; -- input line
VALUE : in sfixed; -- fixed point input
JUSTIFIED : in SIDE := right;
FIELD : in WIDTH := 0) is
begin -- Example 03.30
write (L => L,
VALUE => to_hstring (VALUE),
JUSTIFIED => JUSTIFIED,
FIELD => FIELD);
end procedure hwrite;
-- Hex Read and Write procedures for STD_ULOGIC_VECTOR.
-- Modified from the original to be more forgiving.
procedure Char2QuadBits (C : CHARACTER;
RESULT : out STD_LOGIC_VECTOR(3 downto 0);
GOOD : out BOOLEAN;
ISSUE_ERROR : in BOOLEAN) is
begin
case c is
when '0' => result := x"0"; good := true;
when '1' => result := x"1"; good := true;
when '2' => result := x"2"; good := true;
when '3' => result := x"3"; good := true;
when '4' => result := x"4"; good := true;
when '5' => result := x"5"; good := true;
when '6' => result := x"6"; good := true;
when '7' => result := x"7"; good := true;
when '8' => result := x"8"; good := true;
when '9' => result := x"9"; good := true;
when 'A' | 'a' => result := x"A"; good := true;
when 'B' | 'b' => result := x"B"; good := true;
when 'C' | 'c' => result := x"C"; good := true;
when 'D' | 'd' => result := x"D"; good := true;
when 'E' | 'e' => result := x"E"; good := true;
when 'F' | 'f' => result := x"F"; good := true;
when 'Z' => result := "ZZZZ"; good := true;
when 'X' => result := "XXXX"; good := true;
when others =>
assert not ISSUE_ERROR
report
"FIXED_GENERIC_PKG.HREAD Error: Read a '" & c &
"', expected a Hex character (0-F)."
severity error;
result := "UUUU";
good := false;
end case;
end procedure Char2QuadBits;
procedure HREAD(L : inout LINE;
VALUE : out ufixed) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(-4, VALUE'low)-3)/4)*4;
variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable c : CHARACTER; -- to read the "."
variable valuex : ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
variable i : INTEGER;
begin
VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
loop -- skip white space
read(L, c, igood);
exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
if igood = false then
report "FIXED_GENERIC_PKG.HREAD(ufixed): "
& "Error end of string encountered"
severity error;
return;
else
Char2QuadBits(c, nybble, igood, true);
i := hbv-lbv - 4; -- Top - 4
slv (hbv-lbv downto i+1) := nybble;
end if;
while (i /= -1) and igood and L.all'length /= 0 loop
read (L, c, igood);
if igood = false then
report "FIXED_GENERIC_PKG.HREAD(ufixed): "
& "Error end of string encountered"
severity error;
elsif (c = '.') then
if (i + 1 /= -lbv) then
igood := false;
report "FIXED_GENERIC_PKG.HREAD(ufixed): "
& "encountered ""."" at wrong index"
severity error;
end if;
else
Char2QuadBits(c, nybble, igood, true);
slv (i downto i-3) := nybble;
i := i - 4;
end if;
end loop;
if igood then -- We did not get another error
assert (i = -1) and -- We read everything, and high bits 0
(or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0')
report "FIXED_GENERIC_PKG.HREAD(ufixed): Vector truncated."
severity error;
if (or_reducex(slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report "FIXED_GENERIC_PKG.HREAD(ufixed): Vector truncated"
severity warning;
end if;
end if;
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out ufixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(-4, VALUE'low)-3)/4)*4;
variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable c : CHARACTER; -- to read the "."
variable valuex : ufixed (hbv downto lbv);
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
variable i : INTEGER;
begin
VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
loop -- skip white space
read(L, c, igood);
exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
if igood = false then
return;
else
Char2QuadBits(c, nybble, igood, false);
i := hbv-lbv - 4; -- Top - 4
slv (hbv-lbv downto i+1) := nybble;
end if;
while (i /= -1) and igood and L.all'length /= 0 loop
read (L, c, igood);
if igood then
if (c = '.') then
igood := igood and (i + 1 = -lbv);
else
Char2QuadBits(c, nybble, igood, false);
slv (i downto i-3) := nybble;
i := i - 4;
end if;
end if;
end loop;
good := igood and -- We did not get another error
(i = -1) and -- We read everything, and high bits 0
(or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0');
valuex := to_ufixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out sfixed) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(-4, VALUE'low)-3)/4)*4;
variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable c : CHARACTER; -- to read the "."
variable valuex : sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
variable i : INTEGER;
begin
VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
loop -- skip white space
read(L, c, igood);
exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
if igood = false then
report "FIXED_GENERIC_PKG.HREAD(sfixed): "
& "Error end of string encountered"
severity error;
return;
else
Char2QuadBits(c, nybble, igood, true);
i := hbv-lbv - 4; -- Top - 4
slv (hbv-lbv downto i+1) := nybble;
end if;
while (i /= -1) and igood and L.all'length /= 0 loop
read (L, c, igood);
if igood = false then
report "FIXED_GENERIC_PKG.HREAD(sfixed): "
& "Error end of string encountered"
severity error;
elsif (c = '.') then
if (i + 1 /= -lbv) then
igood := false;
report "FIXED_GENERIC_PKG.HREAD(sfixed): "
& "encountered ""."" at wrong index"
severity error;
end if;
else
Char2QuadBits(c, nybble, igood, true);
slv (i downto i-3) := nybble;
i := i - 4;
end if;
end loop;
if igood then -- We did not get another error
assert (i = -1) -- We read everything
and ((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'))
report "FIXED_GENERIC_PKG.HREAD(sfixed): Vector truncated."
severity error;
if (or_reducex(slv(VALUE'low-lbv-1 downto 0)) = '1') then
assert NO_WARNING
report "FIXED_GENERIC_PKG.HREAD(sfixed): Vector truncated"
severity warning;
end if;
end if;
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end procedure HREAD;
procedure HREAD(L : inout LINE;
VALUE : out sfixed;
GOOD : out BOOLEAN) is
constant hbv : INTEGER := (((maximum(4, (VALUE'high+1))+3)/4)*4)-1;
constant lbv : INTEGER := ((mine(-4, VALUE'low)-3)/4)*4;
variable slv : STD_LOGIC_VECTOR (hbv-lbv downto 0); -- high bits
variable c : CHARACTER; -- to read the "."
variable valuex : sfixed (hbv downto lbv);
variable igood : BOOLEAN;
variable nybble : STD_LOGIC_VECTOR (3 downto 0); -- 4 bits
variable i : INTEGER;
begin
VALUE (VALUE'range) := (others => 'U'); -- initialize to a "U"
loop -- skip white space
read(L, c, igood);
exit when (igood = false) or ((c /= ' ') and (c /= NBSP) and (c /= HT));
end loop;
if igood = false then
return;
else
Char2QuadBits(c, nybble, igood, false);
i := hbv-lbv - 4; -- Top - 4
slv (hbv-lbv downto i+1) := nybble;
end if;
while (i /= -1) and igood and L.all'length /= 0 loop
read (L, c, igood);
if igood then
if (c = '.') then
igood := igood and (i + 1 = -lbv);
else
Char2QuadBits(c, nybble, igood, false);
slv (i downto i-3) := nybble;
i := i - 4;
end if;
end if;
end loop;
good := igood and -- We did not get another error
(i = -1) and -- We read everything
((slv(VALUE'high-lbv) = '0' and -- sign bits = extra bits
or_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '0') or
(slv(VALUE'high-lbv) = '1' and
and_reducex(slv(hbv-lbv downto VALUE'high+1-lbv)) = '1'));
valuex := to_sfixed (slv, hbv, lbv);
VALUE := valuex (VALUE'range);
end procedure HREAD;
-----------------------------------------------------------------------------
-- %%% Remove the following 3 functions. They are a duplicate needed for
-- testing
-----------------------------------------------------------------------------
-- purpose: Justify a string to the right
function justify (
value : STRING;
justified : SIDE := right;
field : width := 0)
return STRING is
constant VAL_LEN : INTEGER := value'length;
variable result : STRING (1 to field) := (others => ' ');
begin -- function justify
-- return value if field is too small
if VAL_LEN >= field then
return value;
end if;
if justified = left then
result(1 to VAL_LEN) := value;
elsif justified = right then
result(field - VAL_LEN + 1 to field) := value;
end if;
return result;
end function justify;
function to_ostring (
value : STD_LOGIC_VECTOR;
justified : SIDE := right;
field : width := 0
) return STRING is
constant ne : INTEGER := (value'length+2)/3;
variable pad : STD_LOGIC_VECTOR(0 to (ne*3 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*3 - 1);
variable result : STRING(1 to ne);
variable tri : STD_LOGIC_VECTOR(0 to 2);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
tri := To_X01Z(ivalue(3*i to 3*i+2));
case tri is
when o"0" => result(i+1) := '0';
when o"1" => result(i+1) := '1';
when o"2" => result(i+1) := '2';
when o"3" => result(i+1) := '3';
when o"4" => result(i+1) := '4';
when o"5" => result(i+1) := '5';
when o"6" => result(i+1) := '6';
when o"7" => result(i+1) := '7';
when "ZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return justify(result, justified, field);
end if;
end function to_ostring;
-------------------------------------------------------------------
function to_hstring (
value : STD_LOGIC_VECTOR;
justified : SIDE := right;
field : width := 0
) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_LOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_LOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return NUS;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return justify(result, justified, field);
end if;
end function to_hstring;
-- %%% End remove here
function to_string (
value : ufixed;
justified : SIDE := right;
field : width := 0
) return STRING is
variable s : STRING(1 to value'length +1) := (others => ' ');
variable sindx : INTEGER;
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_string (resize (value, 0, value'low), justified, field);
elsif value'low > 0 then
return to_string (resize (value, value'high, -1), justified, field);
else
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx +1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx +1;
end loop;
return justify(s, justified, field);
end if;
end if;
end function to_string;
function to_string (
value : sfixed;
justified : SIDE := right;
field : width := 0
) return STRING is
variable s : STRING(1 to value'length +1) := (others => ' ');
variable sindx : INTEGER;
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_string (resize (value, 0, value'low), justified, field);
elsif value'low > 0 then
return to_string (resize (value, value'high, -1), justified, field);
else
sindx := 1;
for i in value'high downto value'low loop
if i = -1 then
s(sindx) := '.';
sindx := sindx +1;
end if;
s(sindx) := MVL9_to_char(STD_ULOGIC(value(i)));
sindx := sindx +1;
end loop;
return justify(s, justified, field);
end if;
end if;
end function to_string;
function to_ostring (
value : ufixed;
justified : SIDE := right;
field : width := 0
) return STRING is
constant lne : INTEGER := (-VALUE'low+2)/3;
constant lpad : STD_LOGIC_VECTOR (0 to (lne*3 + VALUE'low) -1) :=
(others => '0');
variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_ostring (resize (value, 2, value'low), justified, field);
elsif value'low > 0 then
return to_ostring (resize (value, value'high, -3), justified, field);
else
slv := to_slv (value);
return justify(to_ostring(slv(slv'high downto slv'high-VALUE'high))
& "."
& to_ostring(slv(slv'high-VALUE'high-1 downto 0)&lpad),
justified, field);
end if;
end if;
end function to_ostring;
function to_hstring (
value : ufixed;
justified : SIDE := right;
field : width := 0
) return STRING is
constant lne : INTEGER := (-VALUE'low+3)/4;
constant lpad : STD_LOGIC_VECTOR (0 to (lne*4 + VALUE'low) -1) :=
(others => '0');
variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
if value'high < 0 then
return to_hstring (resize (value, 3, value'low), justified, field);
elsif value'low > 0 then
return to_hstring (resize (value, value'high, -4), justified, field);
else
slv := to_slv (value);
return justify(to_hstring(slv(slv'high downto slv'high-VALUE'high))
& "."
& to_hstring(slv(slv'high-VALUE'high-1 downto 0)&lpad),
justified, field);
end if;
end if;
end function to_hstring;
function to_ostring (
value : sfixed;
justified : SIDE := right;
field : width := 0
) return STRING is
constant ne : INTEGER := ((value'high+1)+2)/3;
variable pad : STD_LOGIC_VECTOR(0 to (ne*3 - (value'high+1)) - 1);
constant lne : INTEGER := (-VALUE'low+2)/3;
constant lpad : STD_LOGIC_VECTOR (0 to (lne*3 + VALUE'low) -1) :=
(others => '0');
variable slv : STD_LOGIC_VECTOR (VALUE'high - VALUE'low downto 0);
begin
if value'length < 1 then
return NUS;
else
pad := (others => value(value'high));
if value'high < 0 then
return to_ostring (resize (value, 2, value'low), justified, field);
elsif value'low > 0 then
return to_ostring (resize (value, value'high, -3), justified, field);
else
slv := to_slv (value);
return justify(to_ostring(pad
& slv(slv'high downto slv'high-VALUE'high))
& "."
& to_ostring(slv(slv'high-VALUE'high-1 downto 0)
& lpad),
justified, field);
end if;
end if;
end function to_ostring;
function to_hstring (
value : sfixed;
justified : SIDE := right;
field : width := 0
) return STRING is
constant ne : INTEGER := ((value'high+1)+3)/4;
variable pad : STD_LOGIC_VECTOR(0 to (ne*4 - (value'high+1)) - 1);
constant lne : INTEGER := (-VALUE'low+3)/4;
constant lpad : STD_LOGIC_VECTOR (0 to (lne*4 + VALUE'low) -1) :=
(others => '0');
variable slv : STD_LOGIC_VECTOR (value'length-1 downto 0);
begin
if value'length < 1 then
return NUS;
else
pad := (others => value(value'high));
if value'high < 0 then
return to_hstring (resize (value, 3, value'low), justified, field);
elsif value'low > 0 then
return to_hstring (resize (value, value'high, -4), justified, field);
else
slv := to_slv (value);
return justify(to_hstring(pad&slv(slv'high downto slv'high-VALUE'high))
& "."
& to_hstring(slv(slv'high-VALUE'high-1 downto 0)&lpad),
justified, field);
end if;
end if;
end function to_hstring;
-- From string functions allow you to convert a string into a fixed
-- point number. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100", uf1'high, uf1'low); -- 6.5
-- The "." is optional in this syntax, however it exist and is
-- in the wrong location an error is produced. Overflow will
-- result in saturation.
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed is
variable result : ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
read (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
return result;
end function from_string;
-- Octal and hex conversions work as follows:
-- uf1 <= from_hstring ("6.8", 3, -3); -- 6.5 (bottom zeros dropped)
-- uf1 <= from_ostring ("06.4", 3, -3); -- 6.5 (top zeros dropped)
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed is
variable result : ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
oread (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return ufixed is
variable result : ufixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
hread (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
return result;
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed is
variable result : sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
read (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
return result;
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed is
variable result : sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
oread (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
constant left_index : INTEGER;
constant right_index : INTEGER)
return sfixed is
variable result : sfixed (left_index downto right_index);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
hread (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
return result;
end function from_hstring;
-- Same as above, "size_res" is used for it's range only.
function from_string (
bstring : STRING; -- binary string
size_res : ufixed)
return ufixed is
variable result : ufixed (size_res'high downto size_res'low);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
read (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
return result;
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : ufixed)
return ufixed is
variable result : ufixed (size_res'high downto size_res'low);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
oread (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : ufixed)
return ufixed is
variable result : ufixed (size_res'high downto size_res'low);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
hread (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
return result;
end function from_hstring;
function from_string (
bstring : STRING; -- binary string
size_res : sfixed)
return sfixed is
variable result : sfixed (size_res'high downto size_res'low);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(bstring);
read (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
return result;
end function from_string;
function from_ostring (
ostring : STRING; -- Octal string
size_res : sfixed)
return sfixed is
variable result : sfixed (size_res'high downto size_res'low);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(ostring);
oread (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
return result;
end function from_ostring;
function from_hstring (
hstring : STRING; -- hex string
size_res : sfixed)
return sfixed is
variable result : sfixed (size_res'high downto size_res'low);
variable L : LINE;
variable good : BOOLEAN;
begin
L := new STRING'(hstring);
hread (L, result, good);
deallocate (L);
assert (good)
report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
return result;
end function from_hstring;
-- purpose: find a dot in a string, return -1 if no dot (internal function)
function finddot (
arg : STRING)
return INTEGER is
alias xarg : STRING (arg'length downto 1) is arg; -- make it a downto
begin
for i in xarg'reverse_range loop
if (xarg(i) = '.') then
return i-1;
end if;
end loop;
return -1;
end function finddot;
-- Direct converstion functions. Example:
-- signal uf1 : ufixed (3 downto -3);
-- uf1 <= from_string ("0110.100"); -- 6.5
-- In this case the "." is not optional, and the size of
-- the output must match exactly.
function from_string (
bstring : STRING) -- binary string
return ufixed is
variable result : ufixed (bstring'length-2 downto 0);
variable result_nodot : ufixed (bstring'length-1 downto 0);
variable bstring_nodot : STRING (1 to bstring'length-1);
variable L : LINE;
variable good : BOOLEAN;
variable dot, i, j : INTEGER;
begin
dot := finddot(bstring);
if (dot = -1) then
L := new STRING'(bstring);
read (L, result_nodot, good);
assert (good)
report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
deallocate (L);
return result_nodot;
else
j := 1;
for i in 1 to bstring'high loop
if (bstring(i) /= '.') then
bstring_nodot(j) := bstring(i); -- get rid of the dot.
j := j + 1;
end if;
end loop;
L := new STRING'(bstring_nodot);
read (L, result, good);
assert (good)
report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
deallocate (L);
return to_ufixed(to_slv(result), bstring'length-dot-2, -dot);
end if;
end function from_string;
-- Direct octal and hex converstion functions. In this case
-- the string lengths must match. Example:
-- signal sf1 := sfixed (5 downto -3);
-- sf1 <= from_ostring ("71.4") -- -6.5
function from_ostring (
ostring : STRING) -- Octal string
return ufixed is
variable result : STD_LOGIC_VECTOR((ostring'length-1)*3-1 downto 0);
variable result_nodot : STD_LOGIC_VECTOR((ostring'length)*3-1 downto 0);
variable ostring_nodot : STRING (1 to ostring'length-1);
variable L : LINE;
variable good : BOOLEAN;
variable dot, i, j : INTEGER;
begin
dot := finddot(ostring);
if (dot = -1) then
L := new STRING'(ostring);
oread (L, result_nodot, good);
assert (good)
report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
deallocate (L);
return to_ufixed(UNSIGNED(result_nodot));
else
j := 1;
for i in 1 to ostring'high loop
if (ostring(i) /= '.') then
ostring_nodot(j) := ostring(i); -- get rid of the dot.
j := j + 1;
end if;
end loop;
L := new STRING'(ostring_nodot);
oread (L, result, good);
assert (good)
report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
deallocate (L);
return to_ufixed(result, (ostring'length-1-dot)*3-1, -dot*3);
end if;
end function from_ostring;
function from_hstring (
hstring : STRING) -- hex string
return ufixed is
variable result : STD_LOGIC_VECTOR((hstring'length-1)*4-1 downto 0);
variable result_nodot : STD_LOGIC_VECTOR((hstring'length)*4-1 downto 0);
variable hstring_nodot : STRING (1 to hstring'length-1);
variable L : LINE;
variable good : BOOLEAN;
variable dot, i, j : INTEGER;
begin
dot := finddot(hstring);
if (dot = -1) then
L := new STRING'(hstring);
hread (L, result_nodot, good);
assert (good)
report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
deallocate (L);
return to_ufixed(UNSIGNED(result_nodot));
else
j := 1;
for i in 1 to hstring'high loop
if (hstring(i) /= '.') then
hstring_nodot(j) := hstring(i); -- get rid of the dot.
j := j + 1;
end if;
end loop;
L := new STRING'(hstring_nodot);
hread (L, result, good);
assert (good)
report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
deallocate (L);
return to_ufixed(result, (hstring'length-1-dot)*4-1, -dot*4);
end if;
end function from_hstring;
function from_string (
bstring : STRING) -- binary string
return sfixed is
variable result : sfixed (bstring'length-2 downto 0);
variable result_nodot : sfixed (bstring'length-1 downto 0);
variable bstring_nodot : STRING (1 to bstring'length-1);
variable L : LINE;
variable good : BOOLEAN;
variable dot, i, j : INTEGER;
begin
dot := finddot(bstring);
if (dot = -1) then
L := new STRING'(bstring);
read (L, result_nodot, good);
assert (good)
report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
deallocate (L);
return result_nodot;
else
j := 1;
for i in 1 to bstring'high loop
if (bstring(i) /= '.') then
bstring_nodot(j) := bstring(i); -- get rid of the dot.
j := j + 1;
end if;
end loop;
L := new STRING'(bstring_nodot);
read (L, result, good);
assert (good)
report "fixed_generic_pkg.from_string: Bad string "& bstring severity error;
deallocate (L);
return to_sfixed(to_slv(result), bstring'length-dot-2, -dot);
end if;
end function from_string;
function from_ostring (
ostring : STRING) -- Octal string
return sfixed is
variable result : STD_LOGIC_VECTOR((ostring'length-1)*3-1 downto 0);
variable result_nodot : STD_LOGIC_VECTOR((ostring'length)*3-1 downto 0);
variable ostring_nodot : STRING (1 to ostring'length-1);
variable L : LINE;
variable good : BOOLEAN;
variable dot, i, j : INTEGER;
begin
dot := finddot(ostring);
if (dot = -1) then
L := new STRING'(ostring);
oread (L, result_nodot, good);
assert (good)
report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
deallocate (L);
return to_sfixed(SIGNED(result_nodot));
else
j := 1;
for i in 1 to ostring'high loop
if (ostring(i) /= '.') then
ostring_nodot(j) := ostring(i); -- get rid of the dot.
j := j + 1;
end if;
end loop;
L := new STRING'(ostring_nodot);
oread (L, result, good);
assert (good)
report "fixed_generic_pkg.from_ostring: Bad string "& ostring severity error;
deallocate (L);
return to_sfixed(result, (ostring'length-1-dot)*3-1, -dot*3);
end if;
end function from_ostring;
function from_hstring (
hstring : STRING) -- hex string
return sfixed is
variable result : STD_LOGIC_VECTOR((hstring'length-1)*4-1 downto 0);
variable result_nodot : STD_LOGIC_VECTOR((hstring'length)*4-1 downto 0);
variable hstring_nodot : STRING (1 to hstring'length-1);
variable L : LINE;
variable good : BOOLEAN;
variable dot, i, j : INTEGER;
begin
dot := finddot(hstring);
if (dot = -1) then
L := new STRING'(hstring);
hread (L, result_nodot, good);
assert (good)
report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
deallocate (L);
return sfixed(SIGNED(result_nodot));
else
j := 1;
for i in 1 to hstring'high loop
if (hstring(i) /= '.') then
hstring_nodot(j) := hstring(i); -- get rid of the dot.
j := j + 1;
end if;
end loop;
L := new STRING'(hstring_nodot);
hread (L, result, good);
assert (good)
report "fixed_generic_pkg.from_hstring: Bad string "& hstring severity error;
deallocate (L);
return to_sfixed(result, (hstring'length-1-dot)*4-1, -dot*4);
end if;
end function from_hstring;
-- synthesis translate_on
-- rtl_synthesis on
function to_StdLogicVector (
arg : ufixed) -- fp vector
return STD_LOGIC_VECTOR is
begin
return to_slv (arg);
end function to_StdLogicVector;
function to_Std_Logic_Vector (
arg : ufixed) -- fp vector
return STD_LOGIC_VECTOR is
begin
return to_slv (arg);
end function to_Std_Logic_Vector;
function to_StdLogicVector (
arg : sfixed) -- fp vector
return STD_LOGIC_VECTOR is
begin
return to_slv (arg);
end function to_StdLogicVector;
function to_Std_Logic_Vector (
arg : sfixed) -- fp vector
return STD_LOGIC_VECTOR is
begin
return to_slv (arg);
end function to_Std_Logic_Vector;
function to_StdULogicVector (
arg : ufixed) -- fp vector
return STD_ULOGIC_VECTOR is
begin
return to_sulv (arg);
end function to_StdULogicVector;
function to_Std_ULogic_Vector (
arg : ufixed) -- fp vector
return STD_ULOGIC_VECTOR is
begin
return to_sulv (arg);
end function to_Std_ULogic_Vector;
function to_StdULogicVector (
arg : sfixed) -- fp vector
return STD_ULOGIC_VECTOR is
begin
return to_sulv (arg);
end function to_StdULogicVector;
function to_Std_ULogic_Vector (
arg : sfixed) -- fp vector
return STD_ULOGIC_VECTOR is
begin
return to_sulv (arg);
end function to_Std_ULogic_Vector;
end package body fixed_pkg;
|
mit
|
hubertokf/VHDL-MIPS-Pipeline
|
dec5p1.vhd
|
1
|
2018
|
Library IEEE;
Use ieee.std_logic_1164.all;
Entity dec5to1 is
port (
input: in std_logic_vector(4 downto 0);
output : out std_logic_vector(31 downto 0)
);
end dec5to1;
architecture rtl of dec5to1 is
begin
with input select
output <=
"00000000000000000000000000000001" when "00000",
"00000000000000000000000000000010" when "00001",
"00000000000000000000000000000100" when "00010",
"00000000000000000000000000001000" when "00011",
"00000000000000000000000000010000" when "00100",
"00000000000000000000000000100000" when "00101",
"00000000000000000000000001000000" when "00110",
"00000000000000000000000010000000" when "00111",
"00000000000000000000000100000000" when "01000",
"00000000000000000000001000000000" when "01001",
"00000000000000000000010000000000" when "01010",
"00000000000000000000100000000000" when "01011",
"00000000000000000001000000000000" when "01100",
"00000000000000000010000000000000" when "01101",
"00000000000000000100000000000000" when "01110",
"00000000000000001000000000000000" when "01111",
"00000000000000010000000000000000" when "10000",
"00000000000000100000000000000000" when "10001",
"00000000000001000000000000000000" when "10010",
"00000000000010000000000000000000" when "10011",
"00000000000100000000000000000000" when "10100",
"00000000001000000000000000000000" when "10101",
"00000000010000000000000000000000" when "10110",
"00000000100000000000000000000000" when "10111",
"00000001000000000000000000000000" when "11000",
"00000010000000000000000000000000" when "11001",
"00000100000000000000000000000000" when "11010",
"00001000000000000000000000000000" when "11011",
"00010000000000000000000000000000" when "11100",
"00100000000000000000000000000000" when "11101",
"01000000000000000000000000000000" when "11110",
"10000000000000000000000000000000" when "11111",
"00000000000000000000000000000000" when others;
end rtl;
|
mit
|
rad-/VHDL-Pong
|
KeyboardController.vhd
|
1
|
2419
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity KeyboardController is
Port ( Clock : in STD_LOGIC;
KeyboardClock : in STD_LOGIC;
KeyboardData : in STD_LOGIC;
LeftPaddleDirection : inout integer;
RightPaddleDirection : inout integer
);
end KeyboardController;
architecture Behavioral of KeyboardController is
signal bitCount : integer range 0 to 100 := 0;
signal scancodeReady : STD_LOGIC := '0';
signal scancode : STD_LOGIC_VECTOR(7 downto 0);
signal breakReceived : STD_LOGIC := '0';
constant keyboardA : STD_LOGIC_VECTOR(7 downto 0) := "00011100";
constant keyboardZ : STD_LOGIC_VECTOR(7 downto 0) := "00011010";
constant keyboardK : STD_LOGIC_VECTOR(7 downto 0) := "01000010";
constant keyboardM : STD_LOGIC_VECTOR(7 downto 0) := "00111010";
begin
keyboard_scan_ready_enable : process(KeyboardClock)
begin
if falling_edge(KeyboardClock) then
if bitCount = 0 and KeyboardData = '0' then --keyboard wants to send data
scancodeReady <= '0';
bitCount <= bitCount + 1;
elsif bitCount > 0 and bitCount < 9 then -- shift one bit into the scancode from the left
scancode <= KeyboardData & scancode(7 downto 1);
bitCount <= bitCount + 1;
elsif bitCount = 9 then -- parity bit
bitCount <= bitCount + 1;
elsif bitCount = 10 then -- end of message
scancodeReady <= '1';
bitCount <= 0;
end if;
end if;
end process keyboard_scan_ready_enable;
scan_keyboard : process(scancodeReady, scancode)
begin
if scancodeReady'event and scancodeReady = '1' then
-- breakcode breaks the current scancode
if breakReceived = '1' then
breakReceived <= '0';
if scancode = keyboardA or scancode = keyboardY then
LeftPaddleDirection <= 0;
elsif scancode = keyboardK or scancode = keyboardM then
RightPaddleDirection <= 0;
end if;
elsif breakReceived = '0' then
-- scancode processing
if scancode = "11110000" then
-- mark break for next scancode
breakReceived <= '1';
end if;
if scancode = keyboardA then
LeftPaddleDirection <= -1;
elsif scancode = keyboardY then
LeftPaddleDirection <= 1;
elsif scancode = keyboardK then
RightPaddleDirection <= -1;
elsif scancode = keyboardM then
RightPaddleDirection <= 1;
end if;
end if;
end if;
end process scan_keyboard;
end Behavioral;
|
mit
|
mr-kenhoff/Bitmap-VHDL-Package
|
rtl/vga_bmp_sink.vhd
|
1
|
3146
|
-------------------------------------------------------------------------------
-- File : vga_bmp_sink.vhd
-- Author : mr-kenhoff
-------------------------------------------------------------------------------
-- Description:
-- Saves a conventional VGA-Standard input into a .bmp File
--
-- Target: Simulator
-- Dependencies: bmp_pkg.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.bmp_pkg.all;
entity vga_bmp_sink is
generic (
FILENAME : string
);
port (
clk_i : in std_logic;
dat_i : in std_logic_vector(23 downto 0);
active_vid_i : in std_logic;
h_sync_i : in std_logic;
v_sync_i : in std_logic
);
end vga_bmp_sink;
architecture Behavioral of vga_bmp_sink is
signal h_sync_dly : std_logic := '0';
signal v_sync_dly : std_logic := '0';
signal eol : std_logic := '0';
signal eof : std_logic := '0';
signal x : natural := 0;
signal y : natural := 0;
signal is_active_line : std_logic := '0';
signal is_active_frame : std_logic := '0';
begin
h_sync_dly <= h_sync_i when rising_edge(clk_i);
v_sync_dly <= v_sync_i when rising_edge(clk_i);
eol_eof_gen_process : process(clk_i)
begin
if rising_edge(clk_i) then
-- EOL
if h_sync_dly = '0' and h_sync_i = '1' then
eol <= '1';
else
eol <= '0';
end if;
-- EOF
if v_sync_dly = '0' and v_sync_i = '1' then
eof <= '1';
else
eof <= '0';
end if;
end if;
end process;
sink_process : process( clk_i )
variable sink_bmp : bmp_ptr;
variable sink_pix : bmp_pix;
variable is_bmp_created : boolean := false;
variable is_bmp_saved : boolean := false;
begin
-- Create bitmap on startup
if is_bmp_created = false then
sink_bmp := new bmp;
is_bmp_created := true;
end if;
if rising_edge( clk_i ) then
if active_vid_i = '1' then
sink_pix.r := dat_i(23 downto 16);
sink_pix.g := dat_i(15 downto 8);
sink_pix.b := dat_i(7 downto 0);
bmp_set_pix( sink_bmp, x, y, sink_pix );
x <= x + 1;
is_active_line <= '1';
is_active_frame <= '1';
else
if eol = '1' then
x <= 0;
if is_active_line = '1' then
y <= y + 1;
end if;
is_active_line <= '0';
end if;
if eof = '1' then
y <= 0;
if is_active_frame = '1' then
bmp_save( sink_bmp, FILENAME );
end if;
is_active_frame <= '0';
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
Vladilit/fpga-multi-effect
|
ip_repo/zed_audio_ctrl/zed_audio_ctrl.srcs/sources_1/imports/i2s_audio/common_types.vhd
|
3
|
3567
|
--
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use work.family_support.all;
package common_types is
-- TYPE DECLARATIONS
type SLV32_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 31);
subtype SLV64_TYPE is std_logic_vector(0 to 63);
type SLV64_ARRAY_TYPE is array (natural range <>) of SLV64_TYPE;
type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-- FUNCTION GENERATIONS
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer;
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer;
function clog2(x : positive) return natural;
end common_types;
package body common_types is
-----------------------------------------------------------------------------
-- Function calc_num_ce
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The array is input to
-- the function and an integer is returned reflecting the total number of
-- Chip Enables required for the CE, RdCE, and WrCE Buses
-----------------------------------------------------------------------------
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer is
Variable ce_num_sum : integer := 0;
begin
for i in 0 to (ce_num_array'length)-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
return(ce_num_sum);
end function calc_num_ce;
-----------------------------------------------------------------------------
-- Function calc_start_ce_index
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The CE Size array is
-- input to the function and an integer index representing the index of the
-- target module in the ce_num_array. An integer is returned reflecting the
-- starting index of the assigned Chip Enables within the CE, RdCE, and
-- WrCE Buses.
-----------------------------------------------------------------------------
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer is
Variable ce_num_sum : integer := 0;
begin
If (index = 0) Then
ce_num_sum := 0;
else
for i in 0 to index-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
End if;
return(ce_num_sum);
end function calc_start_ce_index;
--------------------------------------------------------------------------------
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
-- i.e., the least integer greater than or equal to log2(x).
--------------------------------------------------------------------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
end common_types;
|
mit
|
Vladilit/fpga-multi-effect
|
ip_repo/VL_user_octaver_1.0/sources_1/new/octaver.vhd
|
1
|
6941
|
----------------------------------------------------
-- Vladi & Adi --
-- TAU EE Senior year project --
-- --
--************************************************--
--****************** Octaver *********************--
--************************************************--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity octaver is
generic (
T: integer := 20000;
B: integer := 15 --15 bits for 20,000 memory places
);
Port ( x : in STD_LOGIC_VECTOR(31 downto 0);
y : out STD_LOGIC_VECTOR(31 downto 0);
clk_48: in std_logic;
options : in STD_LOGIC_VECTOR(0 to 3);
en : in STD_LOGIC_VECTOR(0 to 3)
);
end octaver;
architecture Behavioral of octaver is
signal y_temp_s : signed(31 downto 0):= x"00000000";
signal i : std_logic_vector (B-1 downto 0) := "000000000000000";
signal max_delay : integer := T-1;
--********************** BRAM signals
signal we : std_logic := '1';
signal addr1 : std_logic_vector(B-1 downto 0) := "000000000000000";
signal addr2 : std_logic_vector(B-1 downto 0):= "000000000000000";
signal data_in : std_logic_vector(31 downto 0); --32 bit word
signal data_out1 : std_logic_vector(31 downto 0);
signal data_out2 : std_logic_vector(31 downto 0);
--*************************
component bram_oct is
generic (
T: integer := 20000;
B: integer := 15 --15 bits for 20,000 memory places
);
port (
CLK : in std_logic;
WE : in std_logic;
ADDR1 : in std_logic_vector(B-1 downto 0);
ADDR2 : in std_logic_vector(B-1 downto 0);
DI : in std_logic_vector(31 downto 0); --32 bit word
DO1 : out std_logic_vector(31 downto 0);
DO2 : out std_logic_vector(31 downto 0)
);
end component bram_oct;
begin
--*********** temporary debugging signals *********
--addr1_temp0 <= "00000000000000000" & std_logic_vector(addr1);
--addr2_temp1 <= "00000000000000000" & std_logic_vector(addr2);
--*************************************************
bram_oct_inst : bram_oct
port map (
CLK => clk_48,
WE => we,
ADDR1 => addr1,
ADDR2 => addr2,
DI => data_in,
DO1 => data_out1,
DO2 => data_out2
);
mem:process(clk_48)
begin
if rising_edge(clk_48) then
if to_integer(unsigned(i))= max_delay-2 then
i<= "000000000000000";
else
i <= std_logic_vector(unsigned(i)+1);
end if;
end if;
end process;
addr_1:process(clk_48)
begin
if rising_edge(clk_48) then
if (to_integer(unsigned(addr1)) = max_delay-2) then
addr1 <= "000000000000000";
else
addr1 <= std_logic_vector(unsigned(addr1) + 1);
end if;
end if;
end process;
addr_2:process(clk_48)
begin
if rising_edge(clk_48) then
--*********************** 1 octave up ****************
if (options="1000" or options="1100" or options="1110" or options="0011" or options="1111" or options="0111") then
if (to_integer(unsigned(addr2)) >= max_delay-2) then
addr2 <= "000000000000000";
end if;
addr2 <= std_logic_vector(shift_left(unsigned(i),1) + 1);
end if;
--***************************************************
--*********************** 2 octaves up ****************
if (options="0100" or options="0001" ) then
if (to_integer(unsigned(addr2)) >= max_delay-2) then
addr2 <= "000000000000000";
end if;
addr2 <= std_logic_vector(shift_left(unsigned(i),2) + 1);
end if;
--***************************************************
--*********************** 1 octave dowm ****************
if (options="0010") then
if (to_integer(unsigned(addr2)) >= max_delay-2) then
addr2 <= "000000000000000";
end if;
addr2 <= std_logic_vector(shift_right(unsigned(i),1) + 1);
end if;
--***************************************************
end if;
end process;
process (clk_48, options)
begin
if en(1)= '1' then
if rising_edge(clk_48) then
if options="1000" then --fir, 1up, 3000
max_delay <= 3000;
y_temp_s <= signed(x) + signed("00000000" & std_logic_vector(shift_right(signed(data_out2(23 downto 0)),1)));
data_in <= x;
y <= std_logic_vector(y_temp_s);
end if;
if options="1100" then --fir, 1up, 8000
max_delay <= 8000;
y_temp_s <= signed(x) + signed("00000000" & std_logic_vector(shift_right(signed(data_out2(23 downto 0)),1)));
data_in <= x;
y <= std_logic_vector(y_temp_s);
end if;
if options="1110" then --fir, 1up, 15000
max_delay <= 15000;
y_temp_s <= signed(x) + signed("00000000" & std_logic_vector(shift_right(signed(data_out2(23 downto 0)),1)));
data_in <= x;
y <= std_logic_vector(y_temp_s);
end if;
if options="1111" then --iir, 1up, 5000 (T/4)
max_delay <= 5000;
y_temp_s <= signed(x) + signed("00000000" & std_logic_vector(shift_right(signed(data_out2(23 downto 0)),1)));
data_in <= std_logic_vector(y_temp_s);
y <= std_logic_vector(y_temp_s);
end if;
if options="0111" then --iir, 1up, 10000 (T/2)
max_delay <= 10000;
y_temp_s <= signed(x) + signed("00000000" & std_logic_vector(shift_right(signed(data_out2(23 downto 0)),1)));
data_in <= std_logic_vector(y_temp_s);
y <= std_logic_vector(y_temp_s);
end if;
if options="0011" then --iir, 1up, 19999 (T-1)
max_delay <= 19999;
y_temp_s <= signed(x) + signed("00000000" & std_logic_vector(shift_right(signed(data_out2(23 downto 0)),1)));
data_in <= std_logic_vector(y_temp_s);
y <= std_logic_vector(y_temp_s);
end if;
--********************************************************
if options="0100" then --fir, 2up, 3000
max_delay <= 3000;
y_temp_s <= signed(x) + signed("00000000" & std_logic_vector(shift_right(signed(data_out2(23 downto 0)),1)));
data_in <= x;
y <= std_logic_vector(y_temp_s);
end if;
if options="0001" then --fir, 2up, 500 - robot sound
max_delay <= 500;
y_temp_s <= signed(x) + signed("00000000" & std_logic_vector(shift_right(signed(data_out2(23 downto 0)),1)));
data_in <= x;
y <= std_logic_vector(y_temp_s);
end if;
--********************************************************
if options="0010" then --fir, 1down, 8000
max_delay <= 8000;
y_temp_s <= signed(x) + signed("00000000" & std_logic_vector(shift_right(signed(data_out2(23 downto 0)),1)));
data_in <= x;
y <= std_logic_vector(y_temp_s);
end if;
--********************************************************
end if;
else
y<=x;
end if;
end process;
end Behavioral;
|
mit
|
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